Merge branch 'master' of https://github.com/RT-Thread/rt-thread into imx1050

.travis.yml

@@ -28,6 +28,7 @@ env:
   - RTT_BSP='asm9260t' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='at91sam9260' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='allwinner_tina' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='imxrt1052-evk' RTT_TOOL_CHAIN='sourcery-arm'
 #  - RTT_BSP='avr32uc3b0' RTT_TOOL_CHAIN='atmel-avr32'
 #  - RTT_BSP='bf533' # no scons
   - RTT_BSP='efm32' RTT_TOOL_CHAIN='sourcery-arm' 

README.md

@@ -1,5 +1,7 @@
 # RT-Thread #
 
+[中文页](README_zh.md) |
+
 [![Build Status](https://travis-ci.org/RT-Thread/rt-thread.svg)](https://travis-ci.org/RT-Thread/rt-thread)
 [![Gitter](https://badges.gitter.im/Join%20Chat.svg)](https://gitter.im/RT-Thread/rt-thread?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
 

bsp/CME_M7/rtconfig.py

@@ -16,7 +16,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'	
+	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'	
 
 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -106,7 +106,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --cpu=Cortex-M3' 
     CFLAGS += ' -e' 
     CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
     CFLAGS += ' -Ol'    
         
     AFLAGS = ''
@@ -120,5 +120,5 @@ elif PLATFORM == 'iar':
     LFLAGS += ' --semihosting' 
     LFLAGS += ' --entry __iar_program_start'    
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = ''

bsp/allwinner_tina/drivers/Kconfig

@@ -14,3 +14,24 @@ config TINA_USING_UART2
     bool "Using UART2"
     select RT_USING_SERIAL
     default y
+
+config TINA_USING_SDIO0
+    bool "Using SDIO0"
+    select RT_USING_SDIO
+    default y
+
+config TINA_USING_SPI0
+    bool "Using spi0"
+    select RT_USING_SPI
+    default y
+
+config TINA_USING_SPI1
+    bool "Using spi1"
+    select RT_USING_SPI
+    default y
+
+config TINA_USING_SPI_FLASH
+    bool "Using flash"
+    select TINA_USING_SPI0
+    select RT_USING_SFUD
+    default y

bsp/allwinner_tina/drivers/drv_clock.c

@@ -525,3 +525,89 @@ rt_err_t bus_software_reset_enalbe(enum bus_gate bus)
     return RT_EOK;
 }
 
+rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz)
+{
+    unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
+    volatile rt_uint32_t *mmc_clk = (clk_id == SDMMC0) ? \
+        (&CCU->sdmmc0_clk) : (&CCU->sdmmc1_clk);
+
+    if (hz < 0)
+    {
+        return RT_EINVAL;
+    }
+
+    if (hz == 0)
+    {
+        *mmc_clk &= ~(0x1 << 31);
+        return RT_EOK;
+    }
+    
+    if (hz <= 24000000)
+    {
+        pll = (0x0 << 24);
+        pll_hz = 24000000;
+    }
+    else
+    {
+        pll = (0x1 << 24);
+        pll_hz = periph_get_pll_clk();
+    }
+
+    div = pll_hz / hz;
+    if (pll_hz % hz)
+    {
+        div++;
+    }
+
+    n = 0;
+    while (div > 16)
+    {
+        n++;
+        div = (div + 1) / 2;
+    }
+
+    if (n > 3)
+    {
+        return -1;
+    }
+
+    /* determine delays */
+    if (hz <= 400000)
+    {
+        oclk_dly = 0;
+        sclk_dly = 0;
+    }
+    else if (hz <= 25000000)
+    {
+        oclk_dly = 0;
+        sclk_dly = 5;
+    }
+    else if (hz <= 50000000)
+    {
+        oclk_dly = 3;
+        sclk_dly = 4;
+    }
+    else
+    {
+        /* hz > 50000000 */
+        oclk_dly = 1;
+        sclk_dly = 4;
+    }
+    
+    *mmc_clk = (0x1 << 31) | pll | (sclk_dly << 20) | \
+           (n << 16) | (oclk_dly << 8) | (div - 1);
+
+    return RT_EOK;
+}
+
+rt_err_t dram_gate_clk_enable(enum dram_gate dram_gate)
+{
+    CCU->dram_gating |= (0x01 << dram_gate);
+    return RT_EOK;
+}
+
+rt_err_t dram_gate_clk_disable(enum dram_gate dram_gate)
+{
+    CCU->dram_gating &= ~(0x01 << dram_gate);
+    return RT_EOK;
+}

bsp/allwinner_tina/drivers/drv_clock.h

@@ -34,13 +34,6 @@
 #define CLK_PLL_SRC             (0x02)
 #define PRE_DIV_SRC             (0x03)
 
-/*  */
-#define BE_GATING_DRAM          (0x1<<26)
-#define FE_GATING_DRAM          (0x1<<24)
-#define TVD_GATING_DRAM         (0x1<<3)
-#define DEINTERLACE_GATING_DRAM (0x1<<2)
-#define CSI_GATING_DRAM         (0x1<<1)
-#define VE_GATING_DRAM          (0x1<<0)
 
 /*  */
 #define TCON_PLL_VIDEO_X1       (0x000)
@@ -142,6 +135,21 @@ enum bus_gate
     AUDIO_CODEC_GATING = (0x00 | (0x2 << BUS_GATE_OFFSET_BIT)),
 };
 
+enum dram_gate
+{
+    BE_GATING_DRAM          = 26,
+    FE_GATING_DRAM          = 24,
+    TVD_GATING_DRAM         = 3,
+    DEINTERLACE_GATING_DRAM = 2,
+    CSI_GATING_DRAM         = 1,
+    VE_GATING_DRAM          = 0
+};
+enum mmc_clk_id
+{
+    SDMMC0,
+    SDMMC1,
+};
+
 struct tina_ccu
 {
     volatile rt_uint32_t pll_cpu_ctrl;         /* 0x000 */
@@ -240,4 +248,8 @@ rt_err_t bus_gate_clk_disalbe(enum bus_gate bus);
 rt_err_t bus_software_reset_enalbe(enum bus_gate bus);
 rt_err_t bus_software_reset_disalbe(enum bus_gate bus);
 
+rt_err_t dram_gate_clk_enable(enum dram_gate dram_gate);
+rt_err_t dram_gate_clk_disable(enum dram_gate dram_gate);
+
+rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz);
 #endif

bsp/allwinner_tina/drivers/drv_sdio.c

@@ -0,0 +1,795 @@
+/*
+ * File      : drv_sdio.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-02-08     RT-Thread    the first version
+ */
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+#include <string.h>
+
+#include "drv_sdio.h"
+#include "interrupt.h"
+#include "mmu.h"
+#include "drv_gpio.h"
+#include "drv_clock.h"
+
+#define DBG_ENABLE
+#define DBG_SECTION_NAME  "[MMC]"
+// #define DBG_LEVEL DBG_LOG    
+// #define DBG_LEVEL DBG_INFO   
+#define DBG_LEVEL DBG_WARNING
+// #define DBG_LEVEL DBG_ERROR  
+#define DBG_COLOR
+#include <rtdbg.h>
+
+#ifdef RT_USING_SDIO
+#define CONFIG_MMC_USE_DMA
+#define DMA_ALIGN       (32U)
+
+struct mmc_xfe_des
+{
+    rt_uint32_t size;    /* block size  */
+	rt_uint32_t num;     /* block num   */
+	rt_uint8_t *buff;    /* buff addr   */
+	rt_uint32_t flag;    /* write or read or stream */
+#define MMC_DATA_WRITE	(1 << 0)
+#define MMC_DATA_READ	(1 << 1)
+#define MMC_DATA_STREAM	(1 << 2)
+};
+
+struct mmc_flag
+{
+    volatile rt_uint32_t risr;
+    volatile rt_uint32_t idst;
+};
+
+struct sdio_drv
+{
+    struct rt_mmcsd_host *host;
+    struct rt_mmcsd_req  *req;
+    struct rt_semaphore rt_sem;
+    struct mmc_xfe_des xfe;
+    struct mmc_flag flag;
+    tina_mmc_t mmc_des;
+    rt_uint8_t *mmc_buf;
+    rt_uint8_t usedma;
+    
+};
+
+#ifdef CONFIG_MMC_USE_DMA
+#ifdef TINA_USING_SDIO0
+ALIGN(32) static rt_uint8_t dma_buffer[64 * 1024];
+#endif
+#endif
+
+static void mmc_request_end(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req);
+
+static void mmc_delay_us(int us)
+{
+    volatile unsigned int temp;
+
+    while (us--)
+    {
+        temp = 0x2f;
+        while (temp--)
+        {
+            temp = temp;
+        };
+    }
+}
+
+static void mmc_dump_errinfo(unsigned int err)
+{
+    dbg_log(DBG_ERROR, "[err]:0x%08x, %s%s%s%s%s%s%s%s%s%s%s\n",
+               err,
+               err & SDXC_RespErr     ? " RE"     : "",
+               err & SDXC_RespCRCErr  ? " RCE"    : "",
+               err & SDXC_DataCRCErr  ? " DCE"    : "",
+               err & SDXC_RespTimeout ? " RTO"    : "",
+               err & SDXC_DataTimeout ? " DTO"    : "",
+               err & SDXC_DataStarve  ? " DS"     : "",
+               err & SDXC_FIFORunErr  ? " FE"     : "",
+               err & SDXC_HardWLocked ? " HL"     : "",
+               err & SDXC_StartBitErr ? " SBE"    : "",
+               err & SDXC_EndBitErr   ? " EBE"    : "",
+               err == 0  ? " STO"    : ""
+              );
+}
+
+static int mmc_update_clk(tina_mmc_t mmc)
+{
+    rt_uint32_t cmd;
+    rt_uint32_t timeout = 2000000;
+
+    /* cmd load */
+    cmd = SDXC_LOAD_CMD | SDXC_UPDATE_CLOCK_CMD | SDXC_WAIT_OVER_CMD;
+    mmc->cmdr_reg = cmd;
+    /* while load success */
+    while ((mmc->cmdr_reg & SDXC_LOAD_CMD) && (--timeout))
+    {
+        mmc_delay_us(1);
+    }
+    if (!timeout)
+    {
+        dbg_log(DBG_ERROR, "mmc update clk failed\n");
+        return -RT_ERROR;
+    }
+    /* clean interrupt */
+    mmc->risr_reg = mmc->risr_reg;
+    return RT_EOK;
+}
+    
+static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
+{
+    ALIGN(32) static struct mmc_des_v4p1 pdes[128];  // mast ALIGN(32)
+    unsigned i, rval;
+    unsigned des_idx;
+    unsigned length = xfe->size * xfe->num;
+    unsigned buff_frag_num = length >> SDXC_DES_NUM_SHIFT;
+    unsigned remain = length & (SDXC_DES_BUFFER_MAX_LEN - 1);
+    
+    if (remain)
+    {
+        buff_frag_num ++;
+    }
+    else
+    {
+        remain = SDXC_DES_BUFFER_MAX_LEN;
+    }
+    memset(pdes, 0, sizeof(pdes));
+    mmu_clean_dcache((rt_uint32_t)(xfe->buff), length);
+    for (i = 0, des_idx = 0; i < buff_frag_num; i++, des_idx++) 
+    {
+        // memset((void*)&pdes[des_idx], 0, sizeof(struct mmc_v4p1));
+        pdes[des_idx].des_chain = 1;
+        pdes[des_idx].own = 1;
+        pdes[des_idx].dic = 1;
+        if ((buff_frag_num > 1) && (i != buff_frag_num - 1))
+        {
+            pdes[des_idx].data_buf1_sz = SDXC_DES_BUFFER_MAX_LEN;
+        }
+        else
+        {
+            pdes[des_idx].data_buf1_sz = remain;
+        }
+        pdes[des_idx].buf_addr_ptr1 = (unsigned long)(xfe->buff) + i * SDXC_DES_BUFFER_MAX_LEN;
+        if (i == 0)
+        {
+            pdes[des_idx].first_des = 1;
+        }
+
+        if (i == (buff_frag_num - 1))
+        {
+            pdes[des_idx].dic = 0;
+            pdes[des_idx].last_des = 1;
+            pdes[des_idx].end_of_ring = 1;
+            pdes[des_idx].buf_addr_ptr2 = 0;
+        } 
+        else 
+        {
+            pdes[des_idx].buf_addr_ptr2 = (unsigned long)&pdes[des_idx+1];
+        }
+
+        dbg_log(DBG_LOG, "frag %d, remain %d, des[%d](%08x): " \
+            "[0] = %08x, [1] = %08x, [2] = %08x, [3] = %08x\n", \
+            i, remain, des_idx, (unsigned int)&pdes[des_idx],
+            (unsigned int)((unsigned int*)&pdes[des_idx])[0], (unsigned int)((unsigned int*)&pdes[des_idx])[1],
+            (unsigned int)((unsigned int*)&pdes[des_idx])[2], (unsigned int)((unsigned int*)&pdes[des_idx])[3]);
+    }
+    mmu_clean_dcache((rt_uint32_t)pdes, sizeof(struct mmc_des_v4p1) * (des_idx + 1));
+
+    /*
+     * GCTRLREG
+     * GCTRL[2] : DMA reset
+     * GCTRL[5] : DMA enable
+     *
+     * IDMACREG
+     * IDMAC[0] : IDMA soft reset
+     * IDMAC[1] : IDMA fix burst flag
+     * IDMAC[7] : IDMA on
+     *
+     * IDIECREG
+     * IDIE[0]  : IDMA transmit interrupt flag
+     * IDIE[1]  : IDMA receive interrupt flag
+     */
+    rval = mmc->gctl_reg;
+    mmc->gctl_reg = rval | (1 << 5) | (1 << 2); /* dma enable           */
+    mmc->dmac_reg = (1 << 0);                   /* idma reset           */
+    while(mmc->dmac_reg & 0x1) {};              /* wait idma reset done */
+    mmc->dmac_reg = (1 << 1) | (1 << 7);        /* idma on              */
+    rval = mmc->idie_reg & (~3);
+    if (xfe->flag == MMC_DATA_WRITE)
+        rval |= (1 << 0);        
+    else
+        rval |= (1 << 1);
+    mmc->idie_reg = rval;
+    mmc->dlba_reg = (unsigned long)pdes;
+    mmc->fwlr_reg = (2U << 28) | (7U << 16) | 8;
+
+    return 0;
+}
+
+static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
+{
+    unsigned i;
+    unsigned byte_cnt = xfe->size * xfe->num;
+    unsigned *buff = (unsigned *)(xfe->buff);
+    volatile unsigned timeout = 2000000;
+
+    if (xfe->flag == MMC_DATA_WRITE)
+    {
+        for (i = 0; i < (byte_cnt >> 2); i++) 
+        {
+            while(--timeout && (mmc->star_reg & (1 << 3)));
+
+            if (timeout <= 0)
+            {
+                dbg_log(DBG_ERROR, "write data by cpu failed status:0x%08x\n", mmc->star_reg);
+                return -RT_ERROR;
+            }
+            mmc->fifo_reg = buff[i];
+            timeout = 2000000;
+        }
+    }
+    else
+    {
+        for (i = 0; i < (byte_cnt >> 2); i++) 
+        {
+            while(--timeout && (mmc->star_reg & (1 << 2)));
+
+            if (timeout <= 0)
+            {
+                dbg_log(DBG_ERROR, "read data by cpu failed status:0x%08x\n", mmc->star_reg);
+                return -RT_ERROR;
+            }
+            buff[i] = mmc->fifo_reg;
+            timeout = 2000000;
+        }
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t mmc_config_clock(tina_mmc_t mmc, int clk)
+{
+    rt_uint32_t rval = 0;
+
+    /* disable card clock */
+    rval = mmc->ckcr_reg;
+    rval &= ~(1 << 16);
+    mmc->ckcr_reg = rval;
+    if (mmc_update_clk(mmc) != RT_EOK)
+    {
+        dbg_log(DBG_ERROR, "clk update fail line:%d\n", __LINE__);
+        return -RT_ERROR;
+    }
+
+    if (mmc == MMC0)
+    {
+        mmc_set_clk(SDMMC0, clk);
+    }
+    else
+    {
+        mmc_set_clk(SDMMC1, clk);
+    }
+    
+    /* Re-enable card clock */
+    rval = mmc->ckcr_reg;
+    rval |=  (0x1 << 16); //(3 << 16);
+    mmc->ckcr_reg = rval;
+    if(mmc_update_clk(mmc) != RT_EOK)
+    {
+        dbg_log(DBG_ERROR, "clk update fail line:%d\n", __LINE__);
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t mmc_set_ios(tina_mmc_t mmc, int clk, int bus_width)
+{
+    dbg_log(DBG_LOG, "mmc set io bus width:%d clock:%d\n", \
+        (bus_width == MMCSD_BUS_WIDTH_8 ? 8 : (bus_width == MMCSD_BUS_WIDTH_4 ? 4 : 1)), clk);
+    /* change clock */
+    if (clk && (mmc_config_clock(mmc, clk) != RT_EOK))
+    {
+        dbg_log(DBG_ERROR, "update clock failed\n");
+        return -RT_ERROR;
+    }
+
+    /* Change bus width */
+    if (bus_width == MMCSD_BUS_WIDTH_8)
+    {
+        mmc->bwdr_reg = 2;
+    }
+    else if (bus_width == MMCSD_BUS_WIDTH_4)
+    {
+        mmc->bwdr_reg = 1;
+    }
+    else
+    {
+        mmc->bwdr_reg = 0;
+    }
+
+    return RT_EOK;
+}
+
+static int mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd)
+{
+
+    unsigned int cmdval  = 0x80000000;
+    signed int timeout   = 0;
+    int err              = 0;
+    unsigned int status  = 0;
+    struct rt_mmcsd_data *data = cmd->data;
+    unsigned int bytecnt = 0;
+    struct sdio_drv *sdio_des = (struct sdio_drv *)host->private_data;
+    tina_mmc_t mmc = sdio_des->mmc_des;
+
+    timeout = 5000 * 1000;
+    status = mmc->star_reg;
+    while (status & (1 << 9))
+    {
+        dbg_log(DBG_LOG, "note: check card busy\n");
+
+        status = mmc->star_reg;
+        if (!timeout--)
+        {
+            err = -1;
+            dbg_log(DBG_ERROR, "mmc cmd12 busy timeout data:0x%08x\n", status);
+            return err;
+        }
+        mmc_delay_us(1);
+    }
+    /*
+     * CMDREG
+     * CMD[5:0] : Command index
+     * CMD[6]   : Has response
+     * CMD[7]   : Long response
+     * CMD[8]   : Check response CRC
+     * CMD[9]   : Has data
+     * CMD[10]  : Write
+     * CMD[11]  : Steam mode
+     * CMD[12]  : Auto stop
+     * CMD[13]  : Wait previous over
+     * CMD[14]  : About cmd
+     * CMD[15]  : Send initialization
+     * CMD[21]  : Update clock
+     * CMD[31]  : Load cmd
+     */
+    if (!cmd->cmd_code)
+        cmdval |= (1 << 15);
+    if (resp_type(cmd) != RESP_NONE)
+        cmdval |= (1 << 6);
+    if (resp_type(cmd) == RESP_R2)
+        cmdval |= (1 << 7);
+    if ((resp_type(cmd) != RESP_R3) && (resp_type(cmd) != RESP_R4))
+        cmdval |= (1 << 8);
+    
+    if (data)
+    {
+        cmdval |= (1 << 9) | (1 << 13);
+        if (data->flags & DATA_DIR_WRITE)
+            cmdval |= (1 << 10);
+        if (data->blks > 1)
+            cmdval |= (1 << 12);
+        mmc->bksr_reg = data->blksize;
+        bytecnt = data->blksize * data->blks;
+        mmc->bycr_reg = bytecnt;
+    }
+
+    dbg_log(DBG_LOG, "cmd %d(0x%08x), arg 0x%08x\n", cmd->cmd_code, cmdval | cmd->cmd_code, cmd->arg);
+    mmc->cagr_reg = cmd->arg;
+    if (!data)
+    {
+        mmc->cmdr_reg = cmdval | cmd->cmd_code;
+        mmc->imkr_reg |= 0x1 << 2;
+    }
+
+    /*
+     * transfer data and check status
+     * STATREG[2] : FIFO empty
+     * STATREG[3] : FIFO full
+     */
+    if (data)
+    {
+        dbg_log(DBG_LOG, "mmc trans data %d bytes addr:0x%08x\n", bytecnt, data);
+#ifdef CONFIG_MMC_USE_DMA
+        if (bytecnt > 64)
+        {
+#else
+        if (0)
+        {
+#endif
+            sdio_des->usedma = 1;
+            mmc->gctl_reg = mmc->gctl_reg & (~0x80000000);
+            mmc_trans_data_by_dma(mmc, &sdio_des->xfe);
+            mmc->cmdr_reg = cmdval | cmd->cmd_code;
+        }
+        else
+        {
+            sdio_des->usedma = 0;
+            mmc->gctl_reg = mmc->gctl_reg | 0x80000000;
+            mmc->cmdr_reg = cmdval | cmd->cmd_code;
+            mmc_trans_data_by_cpu(mmc, &sdio_des->xfe);
+        }
+
+        if (data->blks > 1)
+        {
+            mmc->imkr_reg |= (0x1 << 14);
+        }
+        else
+        {
+            mmc->imkr_reg |= (0x1 << 3);
+        }
+    }
+
+    mmc->imkr_reg |= 0xbfc2;
+
+    if (data)
+    {
+        //TODO:2 * bytecnt * 4?
+        timeout = sdio_des->usedma ? (2 * bytecnt * 4) : 100; //0.04us(25M)*2(4bit width)*25()
+        if (timeout < 10)
+        {
+            timeout = 10;
+        }
+    }
+    else
+    {
+        timeout = 200;
+    }
+
+    if (rt_sem_take(&sdio_des->rt_sem, timeout) != RT_EOK)
+    {
+        err = (mmc->risr_reg | sdio_des->flag.risr) & 0xbfc2;
+        goto out;
+    }
+
+    err = (mmc->risr_reg | sdio_des->flag.risr) & 0xbfc2;
+    if (err)
+    {
+        cmd->err = -RT_ETIMEOUT;
+        goto out;
+    }
+
+    if (resp_type(cmd) == RESP_R2)
+    {
+        cmd->resp[3] = mmc->resp0_reg;
+        cmd->resp[2] = mmc->resp1_reg;
+        cmd->resp[1] = mmc->resp2_reg;
+        cmd->resp[0] = mmc->resp3_reg;
+        dbg_log(DBG_LOG, "mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
+                  cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
+    }
+    else
+    {
+        cmd->resp[0] = mmc->resp0_reg;
+        dbg_log(DBG_LOG, "mmc resp 0x%08x\n", cmd->resp[0]);
+    }
+
+out:
+    if (err)
+    {
+        mmc_dump_errinfo(err & 0xbfc2);
+    }
+    if (data && sdio_des->usedma)
+    {
+        /* IDMASTAREG
+         * IDST[0] : idma tx int
+         * IDST[1] : idma rx int
+         * IDST[2] : idma fatal bus error
+         * IDST[4] : idma descriptor invalid
+         * IDST[5] : idma error summary
+         * IDST[8] : idma normal interrupt sumary
+         * IDST[9] : idma abnormal interrupt sumary
+         */
+        status = mmc->idst_reg;
+        mmc->idst_reg = status;
+        mmc->idie_reg = 0;
+        mmc->dmac_reg = 0;
+        mmc->gctl_reg = mmc->gctl_reg & (~(1 << 5));
+    }
+    if (err)
+    {
+        if (data && (data->flags & DATA_DIR_READ) && (bytecnt == 512))
+        {
+            mmc->gctl_reg = mmc->gctl_reg | 0x80000000;
+            mmc->dbgc_reg = 0xdeb;
+            timeout = 1000;
+            dbg_log(DBG_LOG, "Read remain data\n");
+            while (mmc->bbcr_reg < 512)
+            {
+                unsigned int tmp = mmc->fifo_reg;
+                tmp = tmp;
+                dbg_log(DBG_LOG, "Read data 0x%08x, bbcr 0x%04x\n", tmp, mmc->bbcr_reg);
+                mmc_delay_us(1);
+                if (!(timeout--))
+                {
+                    dbg_log(DBG_ERROR, "Read remain data timeout\n");
+                    break;
+                }
+            }
+        }
+
+        mmc->gctl_reg = 0x7;
+        while (mmc->gctl_reg & 0x7) { };
+
+        mmc_update_clk(mmc);
+        cmd->err = -RT_ETIMEOUT;
+        dbg_log(DBG_ERROR, "mmc cmd %d err\n", cmd->cmd_code);
+    }
+
+    mmc->gctl_reg &= ~(0x1 << 4);
+    mmc->imkr_reg &= ~0xffff;
+    mmc->risr_reg = 0xffffffff;
+    mmc->gctl_reg |= 0x1 << 4;
+    while (!rt_sem_take(&sdio_des->rt_sem, 0)) {}
+    mmc_request_end(sdio_des->host, sdio_des->req);
+
+    return err;
+}
+
+static void mmc_request_end(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
+{
+    struct rt_mmcsd_data *data;
+    unsigned byte_cnt;
+    struct sdio_drv *sdio = (struct sdio_drv *)host->private_data;
+
+#ifdef CONFIG_MMC_USE_DMA
+    data = req->cmd->data;
+    if (data)
+    {
+        byte_cnt = data->blksize * data->blks;
+        if ((byte_cnt > 64) && (data->flags & DATA_DIR_READ))
+        {
+            mmu_invalidate_dcache((rt_uint32_t)sdio->xfe.buff, (rt_uint32_t)byte_cnt);
+
+            if (((rt_uint32_t)data->buf) & (DMA_ALIGN - 1))
+            {
+                memcpy(data->buf, sdio->xfe.buff, byte_cnt);
+            }
+        }
+    }
+#endif
+    mmcsd_req_complete(host);
+}
+
+static void sdio_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
+{
+    struct rt_mmcsd_data *data;
+    int byte_cnt;
+    struct sdio_drv *sdio;
+
+    sdio = (struct sdio_drv *)host->private_data;
+    sdio->req = req;
+    data = req->cmd->data;
+
+    if (data)
+    {
+        sdio->xfe.size = data->blksize;
+        sdio->xfe.num  = data->blks;
+        sdio->xfe.buff = (rt_uint8_t *)data->buf;
+        sdio->xfe.flag = (data->flags & DATA_DIR_WRITE) ? \
+            MMC_DATA_WRITE : MMC_DATA_READ;
+#ifdef CONFIG_MMC_USE_DMA
+        byte_cnt = data->blksize * data->blks;
+        if ((byte_cnt > 64) && (((rt_uint32_t)data->buf) & (DMA_ALIGN - 1)))
+        {
+            sdio->xfe.buff = (rt_uint8_t *)sdio->mmc_buf;
+            if (data->flags & DATA_DIR_WRITE)
+            {
+                memcpy(sdio->mmc_buf, data->buf, byte_cnt);
+                mmu_clean_dcache((rt_uint32_t)sdio->mmc_buf, (rt_uint32_t)byte_cnt);
+            }
+        }
+#endif
+    }
+
+    memset(&sdio->flag, 0, sizeof(struct mmc_flag));
+    mmc_send_cmd(host, req->cmd);
+    
+    return;
+}
+
+static void sdio_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
+{
+    int clk = io_cfg->clock;
+    int width = io_cfg->bus_width;
+    struct sdio_drv *sdio_des = (struct sdio_drv *)host->private_data;
+    tina_mmc_t mmc = sdio_des->mmc_des;
+
+    mmc_set_ios(mmc, clk, width);
+}
+
+static const struct rt_mmcsd_host_ops ops =
+{
+    sdio_request_send,
+    sdio_set_iocfg,
+    RT_NULL,
+    RT_NULL,
+};
+
+static void sdio_interrupt_handle(int irqno, void *param)
+{
+    rt_uint32_t risr, idst;
+    rt_uint32_t status;
+    struct sdio_drv *sdio_des = (struct sdio_drv *)param;
+    struct rt_mmcsd_data *data = sdio_des->req->cmd->data;
+    tina_mmc_t mmc = sdio_des->mmc_des;
+
+    risr = mmc->risr_reg;
+    idst = mmc->idst_reg;
+
+    mmc->risr_reg = risr & mmc->imkr_reg;
+    mmc->idst_reg = idst & mmc->idie_reg;
+
+    sdio_des->flag.risr |= risr;
+    sdio_des->flag.idst |= idst;
+
+    if (data)
+    {
+        int done = 0;
+
+        status = sdio_des->flag.risr | mmc->risr_reg;
+        if (data->blks > 1)//not wait auto stop when MMC_CMD_MANUAL is set
+        {
+            if (sdio_des->usedma)
+                done = ((status & (1 << 14)) && (sdio_des->flag.idst & 0x3)) ? 1 : 0;
+            else
+                done = status & (1 << 14);
+        }
+        else
+        {
+            if (sdio_des->usedma)
+                done = ((status & (1 << 3)) && (sdio_des->flag.idst & 0x3)) ? 1 : 0;
+            else
+                done = status & (1 << 3);
+        }
+
+        if (done)
+        {
+            rt_sem_release(&sdio_des->rt_sem);
+        }
+    }
+    else
+    {
+        rt_sem_release(&sdio_des->rt_sem);
+    }
+}
+
+static void sdio_gpio_init(struct sdio_drv *sdio_des)
+{
+    int pin;
+
+    if ((rt_uint32_t)sdio_des->mmc_des == MMC0_BASE_ADDR)
+    {
+        /* SDC0: PF0-PF5 */
+        for (pin = GPIO_PIN_0; pin <= GPIO_PIN_5; pin++)
+        {
+            gpio_set_func(GPIO_PORT_F, pin, IO_FUN_1);
+            gpio_set_pull_mode(GPIO_PORT_F, pin, PULL_UP);
+            gpio_set_drive_level(GPIO_PORT_F, pin, DRV_LEVEL_2);
+        }
+    }
+    else if ((rt_uint32_t)sdio_des->mmc_des == MMC1_BASE_ADDR)
+    {
+        //todo: config gpio port
+        RT_ASSERT(0);
+    }
+
+}
+
+static void sdio_clk_io_on(struct sdio_drv *sdio_des)
+{
+    if ((rt_uint32_t)sdio_des->mmc_des == MMC0_BASE_ADDR)
+    {
+        CCU->bus_clk_gating0 |= 0x1 << 8;
+        CCU->bus_soft_rst0 |= 0x1 << 8;
+    }
+    else if ((rt_uint32_t)sdio_des->mmc_des == MMC1_BASE_ADDR)
+    {
+        CCU->bus_clk_gating0 |= 0x1 << 9;
+        CCU->bus_soft_rst0 |= 0x1 << 9;
+    }
+
+    mmc_set_clk(SDMMC0, 24000000);
+}
+
+static void sdio_irq_init(void *param)
+{
+    struct sdio_drv *sdio_des = (struct sdio_drv *)param;
+
+    if ((rt_uint32_t)sdio_des->mmc_des == MMC0_BASE_ADDR)
+    {
+        rt_hw_interrupt_install(SDC0_INTERRUPT, sdio_interrupt_handle, param, "mmc0_irq");
+        rt_hw_interrupt_umask(SDC0_INTERRUPT);
+    }
+    else if ((rt_uint32_t)sdio_des->mmc_des == MMC1_BASE_ADDR)
+    {
+        rt_hw_interrupt_install(SDC1_INTERRUPT, sdio_interrupt_handle, param, "mmc1_irq");
+        rt_hw_interrupt_umask(SDC1_INTERRUPT);
+    }
+
+    sdio_des->mmc_des->gctl_reg |= (0x1 << 4);
+}
+
+int tina_sdio_init(void)
+{
+    struct rt_mmcsd_host *host;
+
+#ifdef TINA_USING_SDIO0
+    {
+        static struct sdio_drv _sdio_drv;
+
+        host = mmcsd_alloc_host();
+        if (!host)
+        {
+            dbg_log(DBG_ERROR, "alloc host failed\n");
+            goto err;
+        }
+
+        if (rt_sem_init(&_sdio_drv.rt_sem, "sdio_sem", RT_NULL, RT_IPC_FLAG_FIFO))
+        {
+            dbg_log(DBG_ERROR, "sem init failed\n");
+            goto err;
+        }
+        _sdio_drv.mmc_des = (tina_mmc_t)MMC0_BASE_ADDR;
+        _sdio_drv.mmc_buf = dma_buffer;
+        //init gpio pin
+        sdio_gpio_init(&_sdio_drv);
+        //clk is on
+        sdio_clk_io_on(&_sdio_drv);
+        //irq init
+        sdio_irq_init(&_sdio_drv);
+
+        host->ops = &ops;
+        host->freq_min = 400 * 1000;
+        host->freq_max = 50 * 1000 * 1000;
+        host->valid_ocr = VDD_26_27 | VDD_27_28 | VDD_28_29 | VDD_29_30 | VDD_30_31 | VDD_31_32 |
+        VDD_32_33 | VDD_33_34 | VDD_34_35 | VDD_35_36;
+        host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ | MMCSD_SUP_HIGHSPEED;
+        host->max_seg_size = 2048;
+        host->max_dma_segs = 10;
+        host->max_blk_size = 512;
+        host->max_blk_count = 4096;
+
+        host->private_data = &_sdio_drv;
+
+        _sdio_drv.host = host;
+
+        mmcsd_change(host);
+    }
+#endif
+
+    return RT_EOK;
+
+err:
+    if (host)
+    {
+        rt_free(host);
+    }
+
+    return RT_ERROR;
+}
+INIT_APP_EXPORT(tina_sdio_init);
+#endif

bsp/allwinner_tina/drivers/drv_sdio.h

@@ -0,0 +1,180 @@
+/*
+ * File      : drv_sdio.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-02-08     RT-Thread    the first version
+ */
+#ifndef __DRV_SDIO_H__
+#define __DRV_SDIO_H__
+
+
+#define MMC0_BASE_ADDR     0x01C0F000
+#define MMC1_BASE_ADDR     0x01C10000
+
+struct tina_mmc
+{
+    volatile rt_uint32_t gctl_reg;            /* (0x000) */
+    volatile rt_uint32_t ckcr_reg;            /* (0x004) */
+    volatile rt_uint32_t tmor_reg;            /* (0x008) */
+    volatile rt_uint32_t bwdr_reg;            /* (0x00C) */
+    volatile rt_uint32_t bksr_reg;            /* (0x010) */
+    volatile rt_uint32_t bycr_reg;            /* (0x014) */
+    volatile rt_uint32_t cmdr_reg;            /* (0x018) */
+    volatile rt_uint32_t cagr_reg;            /* (0x01C) */
+    volatile rt_uint32_t resp0_reg;           /* (0x020) */
+    volatile rt_uint32_t resp1_reg;           /* (0x024) */
+    volatile rt_uint32_t resp2_reg;           /* (0x028) */
+    volatile rt_uint32_t resp3_reg;           /* (0x02C) */
+    volatile rt_uint32_t imkr_reg;            /* (0x030) */
+    volatile rt_uint32_t misr_reg;            /* (0x034) */
+    volatile rt_uint32_t risr_reg;            /* (0x038) */
+    volatile rt_uint32_t star_reg;            /* (0x03C) */
+    volatile rt_uint32_t fwlr_reg;            /* (0x040) */
+    volatile rt_uint32_t funs_reg;            /* (0x044) */
+    volatile rt_uint32_t cbcr_reg;            /* (0x048) */
+    volatile rt_uint32_t bbcr_reg;            /* (0x04C) */
+    volatile rt_uint32_t dbgc_reg;            /* (0x050) */
+    volatile rt_uint32_t reserved0;
+    volatile rt_uint32_t a12a_reg;            /* (0x058) */
+    volatile rt_uint32_t reserved1[7];
+    volatile rt_uint32_t hwrst_reg;           /* (0x078) */
+    volatile rt_uint32_t reserved2;
+    volatile rt_uint32_t dmac_reg;            /* (0x080) */
+    volatile rt_uint32_t dlba_reg;            /* (0x084) */
+    volatile rt_uint32_t idst_reg;            /* (0x088) */
+    volatile rt_uint32_t idie_reg;            /* (0x08C) */
+    volatile rt_uint32_t chda_reg;            /* (0x090) */
+    volatile rt_uint32_t cbda_reg;            /* (0x094) */
+    volatile rt_uint32_t reserved3[26];
+    volatile rt_uint32_t card_thldc_reg;      /* (0x100) */
+    volatile rt_uint32_t reserved4[2];
+    volatile rt_uint32_t emmc_dsbd_reg;       /* (0x10c) */
+    volatile rt_uint32_t reserved5[12];
+    volatile rt_uint32_t reserved6[48];
+    volatile rt_uint32_t fifo_reg;            /* (0x200) */
+};
+
+typedef struct tina_mmc *tina_mmc_t;
+
+#define MMC0    ((tina_mmc_t)MMC0_BASE_ADDR)
+#define MMC1    ((tina_mmc_t)MMC1_BASE_ADDR)
+
+
+#define BIT(x)              (1<<(x))
+/* Struct for Intrrrupt Information */
+#define SDXC_RespErr        BIT(1)  //0x2
+#define SDXC_CmdDone        BIT(2)  //0x4
+#define SDXC_DataOver       BIT(3)  //0x8
+#define SDXC_TxDataReq      BIT(4)  //0x10
+#define SDXC_RxDataReq      BIT(5)  //0x20
+#define SDXC_RespCRCErr     BIT(6)  //0x40
+#define SDXC_DataCRCErr     BIT(7)  //0x80
+#define SDXC_RespTimeout    BIT(8)  //0x100
+#define SDXC_ACKRcv         BIT(8)  //0x100
+#define SDXC_DataTimeout    BIT(9)  //0x200
+#define SDXC_BootStart      BIT(9)  //0x200
+#define SDXC_DataStarve     BIT(10) //0x400
+#define SDXC_VolChgDone     BIT(10) //0x400
+#define SDXC_FIFORunErr     BIT(11) //0x800
+#define SDXC_HardWLocked    BIT(12) //0x1000
+#define SDXC_StartBitErr    BIT(13) //0x2000
+#define SDXC_AutoCMDDone    BIT(14) //0x4000
+#define SDXC_EndBitErr      BIT(15) //0x8000
+#define SDXC_SDIOInt        BIT(16) //0x10000
+#define SDXC_CardInsert     BIT(30) //0x40000000
+#define SDXC_CardRemove     BIT(31) //0x80000000
+#define SDXC_IntErrBit      (SDXC_RespErr | SDXC_RespCRCErr | SDXC_DataCRCErr \
+                            | SDXC_RespTimeout | SDXC_DataTimeout | SDXC_FIFORunErr \
+                            | SDXC_HardWLocked | SDXC_StartBitErr | SDXC_EndBitErr)  //0xbfc2
+
+/*
+    SD CMD reg
+REG[0-5] : Cmd ID
+REG[6]   : Has response
+REG[7]   : Long response
+REG[8]   : Check response CRC
+REG[9]   : Has data
+REG[10]  : Write
+REG[11]  : Steam mode
+REG[12]  : Auto stop
+REG[13]  : Wait previous over
+REG[14]  : About cmd
+REG[15]  : Send initialization
+REG[21]  : Update clock
+REG[31]  : Load cmd
+*/
+#define SDXC_RESPONSE_CMD        BIT(6)
+#define SDXC_LONG_RESPONSE_CMD   BIT(7)
+#define SDXC_CHECK_CRC_CMD       BIT(8)
+#define SDXC_HAS_DATA_CMD        BIT(9)
+#define SDXC_WRITE_CMD           BIT(10)
+#define SDXC_STEAM_CMD           BIT(11)
+#define SDXC_AUTO_STOP_CMD       BIT(12)
+#define SDXC_WAIT_OVER_CMD       BIT(13)
+#define SDXC_ABOUT_CMD           BIT(14)
+#define SDXC_SEND_INIT_CMD       BIT(15)
+#define SDXC_UPDATE_CLOCK_CMD    BIT(21)
+#define SDXC_LOAD_CMD            BIT(31)
+
+/* 
+    SD status reg 
+REG[0]   : FIFO_RX_LEVEL
+REG[1]   : FIFO_TX_LEVEL
+REG[2]   : FIFO_EMPTY
+REG[3]   : FIFO_FULL
+REG[4-7] : FSM_STA
+REG[8]   : CARD_PRESENT
+REG[9]   : CARD_BUSY
+REG[10]  : FSM_BUSY
+REG[11-16]: RESP_IDX 
+REG[17-21]: FIFO_LEVEL
+REG[31]   : DMA_REQ
+*/
+
+#define SDXC_FIFO_RX_LEVEL    BIT(0)
+#define SDXC_FIFO_TX_LEVEL    BIT(1)
+#define SDXC_FIFO_EMPTY       BIT(2)
+#define SDXC_FIFO_FULL        BIT(3)
+#define SDXC_CARD_PRESENT     BIT(8)
+#define SDXC_CARD_BUSY        BIT(9)
+#define SDXC_FSM_BUSY         BIT(10)
+#define SDXC_DMA_REQ          BIT(31)
+
+struct mmc_des_v4p1
+{
+    rt_uint32_t                         : 1,
+                    dic                 : 1, /* disable interrupt on completion                                    */
+                    last_des            : 1, /* 1-this data buffer is the last buffer                              */
+                    first_des           : 1, /* 1-data buffer is the first buffer,0-data buffer contained in the next descriptor is 1st buffer        */
+                    des_chain           : 1, /* 1-the 2nd address in the descriptor is the next descriptor address */
+                    end_of_ring         : 1, /* 1-last descriptor flag when using dual data buffer in descriptor   */
+                                        : 24,
+                    card_err_sum        : 1, /* transfer error flag                                                */
+                    own                 : 1; /* des owner:1-idma owns it, 0-host owns it                           */
+
+#define SDXC_DES_NUM_SHIFT 12  /* smhc2!! */
+#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT)
+    rt_uint32_t data_buf1_sz  : 16,
+                data_buf2_sz     : 16;
+    rt_uint32_t buf_addr_ptr1;
+    rt_uint32_t buf_addr_ptr2;
+};
+
+#endif

bsp/allwinner_tina/drivers/spi/SConscript

@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('spi', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/allwinner_tina/drivers/spi/drv_spi.c

@@ -0,0 +1,793 @@
+/*
+ * File      : drv_spi.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-08-30     tanek        first implementation.
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+#include <stdbool.h>
+
+#include "drv_spi.h"
+#include "drv_gpio.h"
+#include "drv_clock.h"
+
+#define SPI_BUS_MAX_CLK    (30 * 1000 * 1000)
+
+#define DBG_ENABLE
+#define DBG_SECTION_NAME  "[SPI]"
+#define DBG_LEVEL         DBG_WARNING
+#define DBG_COLOR
+#include <rtdbg.h>
+
+#ifdef RT_USING_SPI
+
+//#define DEBUG
+
+#define ARR_LEN(__N)      (sizeof(__N) / sizeof(__N[0]))
+
+#ifdef DEBUG
+#define DEBUG_PRINTF(...)   rt_kprintf(__VA_ARGS__)
+#else
+#define DEBUG_PRINTF(...)
+#endif
+
+
+#define __SPI_STATIC_INLINE__ rt_inline
+
+/*
+ * @brief Hardware Layer Interface
+ */
+__SPI_STATIC_INLINE__
+rt_uint32_t SPI_GetVersion(SPI_T *spi)
+{
+    return spi->VER;
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_Reset(SPI_T *spi)
+{
+    HAL_SET_BIT(spi->CTRL, SPI_CTRL_RST_MASK);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_SetMode(SPI_T *spi, SPI_CTRL_Mode mode)
+{
+    HAL_MODIFY_REG(spi->CTRL, SPI_CTRL_MODE_MASK, mode);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_Enable(SPI_T *spi)
+{
+    HAL_SET_BIT(spi->CTRL, SPI_CTRL_EN_MASK);
+}
+
+__SPI_STATIC_INLINE__
+void SPI_Disable(SPI_T *spi)
+{
+    HAL_CLR_BIT(spi->CTRL, SPI_CTRL_EN_MASK);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_StartTransmit(SPI_T *spi)
+{
+    HAL_SET_BIT(spi->TCTRL, SPI_TCTRL_XCH_MASK);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_SetFirstTransmitBit(SPI_T *spi, SPI_TCTRL_Fbs bit)
+{
+    HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_FBS_MASK, bit);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_EnableRapidsMode(SPI_T *spi, bool delay_sample)
+{
+    HAL_SET_BIT(spi->TCTRL, SPI_TCTRL_RPSM_MASK);
+    HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SDC_MASK, delay_sample << SPI_TCTRL_SDC_SHIFT);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_DisableRapidsMode(SPI_T *spi)
+{
+    HAL_CLR_BIT(spi->TCTRL, SPI_TCTRL_RPSM_MASK);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_SetDuplex(SPI_T *spi, SPI_TCTRL_DHB_Duplex duplex)
+{
+    HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_DHB_MASK, duplex);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_SetCsLevel(SPI_T *spi,  bool level)
+{
+    HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SS_LEVEL_MASK, level << SPI_TCTRL_SS_LEVEL_SHIFT);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_ManualChipSelect(SPI_T *spi, SPI_TCTRL_SS_Sel cs)
+{
+    HAL_SET_BIT(spi->TCTRL, SPI_TCTRL_SS_OWNER_MASK);
+    HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SS_SEL_MASK, cs);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_AutoChipSelect(SPI_T *spi, SPI_TCTRL_SS_Sel cs, bool cs_remain)
+{
+    HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SS_SEL_MASK, cs);
+    HAL_CLR_BIT(spi->TCTRL, SPI_TCTRL_SS_OWNER_MASK);
+    HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SS_CTL_MASK, (!cs_remain) << SPI_TCTRL_SS_CTL_SHIFT);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_SetCsIdle(SPI_T *spi, bool idle)
+{
+    HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SPOL_MASK, (!!idle) << SPI_TCTRL_SPOL_SHIFT);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_SetSclkMode(SPI_T *spi, SPI_SCLK_Mode mode)
+{
+    HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_CPOL_MASK | SPI_TCTRL_CPHA_MASK, mode);
+}
+
+typedef enum
+{
+    SPI_INT_CS_DESELECT = SPI_IER_SS_INT_EN_MASK,
+    SPI_INT_TRANSFER_COMPLETE = SPI_IER_TC_INT_EN_MASK,
+    SPI_INT_TXFIFO_UNDER_RUN = SPI_IER_TF_UDR_INT_EN_MASK,
+    SPI_INT_TXFIFO_OVERFLOW = SPI_IER_TF_OVF_INT_EN_MASK,
+    SPI_INT_RXFIFO_UNDER_RUN = SPI_IER_RF_UDR_INT_EN_MASK,
+    SPI_INT_RXFIFO_OVERFLOW = SPI_IER_RF_OVF_INT_EN_MASK,
+    SPI_INT_TXFIFO_FULL = SPI_IER_TF_FUL_INT_EN_MASK,
+    SPI_INT_TXFIFO_EMPTY = SPI_IER_TX_EMP_INT_EN_MASK,
+    SPI_INT_TXFIFO_READY = SPI_IER_TX_ERQ_INT_EN_MASK,
+    SPI_INT_RXFIFO_FULL = SPI_IER_RF_FUL_INT_EN_MASK,
+    SPI_INT_RXFIFO_EMPTY = SPI_IER_RX_EMP_INT_EN_MASK,
+    SPI_INT_RXFIFO_READY = SPI_IER_RF_RDY_INT_EN_MASK
+} SPI_Int_Type;
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_EnableInt(SPI_T *spi, SPI_Int_Type type)
+{
+    HAL_SET_BIT(spi->IER, type);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_DisableInt(SPI_T *spi, SPI_Int_Type type)
+{
+    HAL_CLR_BIT(spi->IER, type);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+bool SPI_IntState(SPI_T *spi, SPI_Int_Type type)
+{
+    return !!HAL_GET_BIT(spi->STA, type);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+bool SPI_ClearInt(SPI_T *spi, SPI_Int_Type type)
+{
+    HAL_SET_BIT(spi->STA, type);
+    return HAL_GET_BIT(spi->STA, type);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_DebugReadTx(SPI_T *spi, rt_uint32_t *data)
+{
+    // tbc...
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_DebugWriteRx(SPI_T *spi, rt_uint32_t *data)
+{
+    // tbc...
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_ResetTxFifo(SPI_T *spi)
+{
+    HAL_SET_BIT(spi->FCTL, SPI_FCTL_TF_RST_MASK);
+    while (HAL_GET_BIT(spi->FCTL, SPI_FCTL_TF_RST_MASK) != 0);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_ResetRxFifo(SPI_T *spi)
+{
+    HAL_SET_BIT(spi->FCTL, SPI_FCTL_RF_RST_MASK);
+    while (HAL_GET_BIT(spi->FCTL, SPI_FCTL_RF_RST_MASK) != 0);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_DMA(SPI_T *spi, bool txEn, bool rxEn)
+{
+    HAL_MODIFY_REG(spi->FCTL,
+                   SPI_FCTL_TF_DRQ_EN_MASK | SPI_FCTL_RF_DRQ_EN_MASK,
+                   ((!!txEn) << SPI_FCTL_TF_DRQ_EN_SHIFT) | ((!!rxEn) << SPI_FCTL_RF_DRQ_EN_SHIFT));
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_SetTxFifoThreshold(SPI_T *spi, uint8_t threshold)
+{
+    HAL_MODIFY_REG(spi->FCTL, SPI_FCTL_TX_TRIG_LEVEL_MASK, threshold << SPI_FCTL_TX_TRIG_LEVEL_SHIFT);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_SetRxFifoThreshold(SPI_T *spi, uint8_t threshold)
+{
+    HAL_MODIFY_REG(spi->FCTL, SPI_FCTL_RX_TRIG_LEVEL_MASK, threshold << SPI_FCTL_RX_TRIG_LEVEL_SHIFT);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+uint8_t SPI_GetTxFifoCounter(SPI_T *spi)
+{
+    return (uint8_t)((spi->FST & SPI_FST_TF_CNT_MASK) >> SPI_FST_TF_CNT_SHIFT);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+uint8_t SPI_GetRxFifoCounter(SPI_T *spi)
+{
+    return (uint8_t)((spi->FST & SPI_FST_RF_CNT_MASK) >> SPI_FST_RF_CNT_SHIFT);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_EnableDualMode(SPI_T *spi)
+{
+    HAL_SET_BIT(spi->BCC, SPI_BCC_DRM_MASK);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_DisableDualMode(SPI_T *spi)
+{
+    HAL_CLR_BIT(spi->BCC, SPI_BCC_DRM_MASK);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_SetInterval(SPI_T *spi, uint16_t nSCLK)
+{
+    HAL_MODIFY_REG(spi->WAIT, SPI_WAIT_WCC_MASK, nSCLK << SPI_WAIT_WCC_SHIFT);
+}
+
+/*
+ * @brief
+ */
+static void SPI_SetClkDiv(SPI_T *spi, uint16_t div)
+{
+    uint8_t n = 0;
+    if (div < 1)
+    {
+        return;
+    }
+
+    if (div > 2 * (0xFF + 1))
+    {
+        HAL_CLR_BIT(spi->CCTR, SPI_CCTR_DRS_MASK);
+        do
+        {
+            div = (div == 1) ? 0 : ((div + 1) / 2);
+            n++;
+        }
+        while (div);
+
+        HAL_MODIFY_REG(spi->CCTR, SPI_CCTR_CDR1_MASK, (n & 0x0F) << SPI_CCTR_CDR1_SHIFT);
+    }
+    else
+    {
+        HAL_SET_BIT(spi->CCTR, SPI_CCTR_DRS_MASK);
+        n = ((div + 1) / 2) - 1;
+        HAL_MODIFY_REG(spi->CCTR, SPI_CCTR_CDR2_MASK, (n & 0xFF) << SPI_CCTR_CDR2_SHIFT);
+    }
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_SetDataSize(SPI_T *spi, rt_uint32_t data_size, rt_uint32_t dummy_size)
+{
+    HAL_MODIFY_REG(spi->BC, SPI_BC_MBC_MASK, data_size + dummy_size);
+    HAL_MODIFY_REG(spi->TC, SPI_TC_MWTC_MASK, data_size);
+    HAL_MODIFY_REG(spi->BCC, SPI_BCC_STC_MASK, data_size);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_Write(SPI_T *spi, uint8_t *data)
+{
+    HAL_REG_8BIT(&spi->TXD) = *data;
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+void SPI_Read(SPI_T *spi, uint8_t *data)
+{
+    *data = HAL_REG_8BIT(&spi->RXD);
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+uint8_t *SPI_TxAddress(SPI_T *spi)
+{
+    return (uint8_t *)&spi->TXD;
+}
+
+/*
+ * @brief
+ */
+__SPI_STATIC_INLINE__
+uint8_t *SPI_RxAddress(SPI_T *spi)
+{
+    return (uint8_t *)&spi->RXD;
+}
+
+/* private rt-thread spi ops function */
+static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
+static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *message);
+
+static struct rt_spi_ops tina_spi_ops =
+{
+    configure,
+    xfer
+};
+
+static rt_err_t configure(struct rt_spi_device *device,
+                          struct rt_spi_configuration *configuration)
+{
+    struct rt_spi_bus *spi_bus = (struct rt_spi_bus *)device->bus;
+    struct tina_spi_cs *tina_spi_cs = device->parent.user_data;
+    struct tina_spi *_spi_info = (struct tina_spi *)spi_bus->parent.user_data;
+    SPI_T *spi = _spi_info->spi;
+
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(configuration != RT_NULL);
+
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+
+    DEBUG_PRINTF("spi address: %08X\n", (rt_uint32_t)spi);
+
+    SPI_Disable(spi);
+    SPI_Reset(spi);
+    SPI_ResetRxFifo(spi);
+    SPI_ResetTxFifo(spi);
+
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+
+    /* data_width */
+    if (configuration->data_width != 8)
+    {
+        DEBUG_PRINTF("error: data_width is %d\n", configuration->data_width);
+        return RT_EIO;
+    }
+
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+    SPI_SetDuplex(spi, SPI_TCTRL_DHB_FULL_DUPLEX);
+    SPI_SetMode(spi, SPI_CTRL_MODE_MASTER);
+
+    /* MSB or LSB */
+    if (configuration->mode & RT_SPI_MSB)
+    {
+        SPI_SetFirstTransmitBit(spi, SPI_TCTRL_FBS_MSB);
+    }
+    else
+    {
+        SPI_SetFirstTransmitBit(spi, SPI_TCTRL_FBS_LSB);
+    }
+
+    switch (configuration->mode)
+    {
+    case RT_SPI_MODE_0:
+        SPI_SetSclkMode(spi, SPI_SCLK_Mode0);
+        break;
+    case RT_SPI_MODE_1:
+        SPI_SetSclkMode(spi, SPI_SCLK_Mode1);
+        break;
+    case RT_SPI_MODE_2:
+        SPI_SetSclkMode(spi, SPI_SCLK_Mode2);
+        break;
+    case RT_SPI_MODE_3:
+        SPI_SetSclkMode(spi, SPI_SCLK_Mode3);
+        break;
+    }
+
+    /* baudrate */
+    {
+        unsigned int spi_clock = 0;
+        rt_uint32_t max_hz;
+        rt_uint32_t div;
+
+        DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+
+        max_hz = configuration->max_hz;
+
+        if (max_hz > SPI_BUS_MAX_CLK)
+        {
+            max_hz = SPI_BUS_MAX_CLK;
+        }
+        spi_clock = ahb_get_clk();
+
+        DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+
+        div = (spi_clock + max_hz - 1) / max_hz;
+
+        dbg_log(DBG_LOG, "configuration->max_hz: %d\n", configuration->max_hz);
+        dbg_log(DBG_LOG, "max freq: %d\n", max_hz);
+        dbg_log(DBG_LOG, "spi_clock: %d\n", spi_clock);
+        dbg_log(DBG_LOG, "div: %d\n", div);
+
+        SPI_SetClkDiv(spi, div / 2);
+    } /* baudrate */
+
+    SPI_ManualChipSelect(spi, tina_spi_cs->cs);
+    SPI_SetDataSize(spi, 0, 0);
+    SPI_Enable(spi);
+
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+
+    return RT_EOK;
+};
+
+static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    struct rt_spi_bus *r6_spi_bus = (struct rt_spi_bus *)device->bus;
+    struct tina_spi *_spi_info = (struct tina_spi *)r6_spi_bus->parent.user_data;
+    SPI_T *spi = _spi_info->spi;
+    struct rt_spi_configuration *config = &device->config;
+    struct tina_spi_cs *tina_spi_cs = device->parent.user_data;
+
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(message != NULL);
+
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+    DEBUG_PRINTF("spi_info: %08X\n", (rt_uint32_t)_spi_info);
+    DEBUG_PRINTF("spi address: %08X\n", (rt_uint32_t)spi);
+
+    /* take CS */
+    if (message->cs_take)
+    {
+        SPI_ManualChipSelect(spi, tina_spi_cs->cs);
+        SPI_SetCsLevel(spi, false);
+        DEBUG_PRINTF("spi take cs\n");
+    }
+
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+
+    {
+        if ((config->data_width <= 8) && (message->length > 0))
+        {
+            const rt_uint8_t *send_ptr = message->send_buf;
+            rt_uint8_t *recv_ptr = message->recv_buf;
+            rt_uint32_t tx_size = message->length;
+            rt_uint32_t rx_size = message->length;
+
+            DEBUG_PRINTF("spi poll transfer start: %d\n", tx_size);
+
+            SPI_ResetTxFifo(spi);
+            SPI_ResetRxFifo(spi);
+            SPI_SetDataSize(spi, tx_size, 0);
+
+            SPI_StartTransmit(spi);
+
+            DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+
+            while (tx_size > 0 || rx_size > 0)
+            {
+                uint8_t tx_data = 0xFF;
+                uint8_t rx_data = 0xFF;
+
+                while ((SPI_GetTxFifoCounter(spi) < SPI_FIFO_SIZE) && (tx_size > 0))
+                {
+                    if (send_ptr != RT_NULL)
+                    {
+                        tx_data = *send_ptr++;
+                    }
+                    SPI_Write(spi, &tx_data);
+                    tx_size--;
+                }
+
+                while (SPI_GetRxFifoCounter(spi) > 0)
+                {
+                    rx_size--;
+                    SPI_Read(spi, &rx_data);
+
+                    if (recv_ptr != RT_NULL)
+                    {
+                        *recv_ptr++ = rx_data;
+                    }
+                }
+            }
+
+            DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+
+            if ((tx_size != 0) || (rx_size != 0))
+            {
+                DEBUG_PRINTF("spi_tx_rx error with tx count = %d, rx count = %d.\n", tx_size, rx_size);
+
+                return 0;
+            }
+
+            DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+
+            while (SPI_IntState(spi, SPI_INT_TRANSFER_COMPLETE) == 0);
+            SPI_ClearInt(spi, SPI_INT_TRANSFER_COMPLETE);
+
+            DEBUG_PRINTF("spi poll transfer finsh\n");
+        }
+        else if (config->data_width > 8)
+        {
+            DEBUG_PRINTF("data width: %d\n", config->data_width);
+            RT_ASSERT(NULL);
+        }
+    }
+
+    /* release CS */
+    if (message->cs_release)
+    {
+        SPI_SetCsLevel(spi, true);
+        DEBUG_PRINTF("spi release cs\n");
+    }
+
+    return message->length;
+};
+
+#ifdef TINA_USING_SPI0
+static struct rt_spi_bus spi_bus0;
+#endif
+
+#ifdef TINA_USING_SPI1
+static struct rt_spi_bus spi_bus1;
+#endif
+
+static const struct tina_spi spis[] =
+{
+#ifdef TINA_USING_SPI0
+    {(SPI_T *)SPI0_BASE_ADDR, SPI0_GATING, &spi_bus0},
+#endif
+
+#ifdef TINA_USING_SPI1
+    {(SPI_T *)SPI1_BASE_ADDR, SPI1_GATING, &spi_bus1},
+#endif
+};
+
+
+
+/** \brief init and register r6 spi bus.
+ *
+ * \param SPI: R6 SPI, e.g: SPI1,SPI2,SPI3.
+ * \param spi_bus_name: spi bus name, e.g: "spi1"
+ * \return
+ *
+ */
+rt_err_t tina_spi_bus_register(SPI_T *spi, const char *spi_bus_name)
+{
+    int i;
+
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+
+    RT_ASSERT(spi_bus_name != RT_NULL);
+
+    for (i = 0; i < ARR_LEN(spis); i++)
+    {
+        if (spi == spis[i].spi)
+        {
+            bus_software_reset_disalbe(spis[i].spi_gate);
+            bus_gate_clk_enalbe(spis[i].spi_gate);
+
+            spis[i].spi_bus->parent.user_data = (void *)&spis[i];
+            DEBUG_PRINTF("bus  addr: %08X\n", (rt_uint32_t)spis[i].spi_bus);
+            DEBUG_PRINTF("user_data: %08X\n", (rt_uint32_t)spis[i].spi_bus->parent.user_data);
+            DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+            rt_spi_bus_register(spis[i].spi_bus, spi_bus_name, &tina_spi_ops);
+            DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+            return RT_EOK;
+        }
+    }
+
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+
+    return RT_ERROR;
+}
+
+int rt_hw_spi_init(void)
+{
+    DEBUG_PRINTF("register spi bus\n");
+
+#ifdef TINA_USING_SPI0
+    /* register spi bus */
+    {
+        rt_err_t result;
+
+        DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+
+        gpio_set_func(GPIO_PORT_C, GPIO_PIN_0, IO_FUN_1);
+        gpio_set_func(GPIO_PORT_C, GPIO_PIN_2, IO_FUN_1);
+        gpio_set_func(GPIO_PORT_C, GPIO_PIN_3, IO_FUN_1);
+
+        DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+
+        result = tina_spi_bus_register((SPI_T *)SPI0_BASE_ADDR, "spi0");
+        if (result != RT_EOK)
+        {
+            DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+            return result;
+        }
+    }
+
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+    /* attach cs */
+    {
+        static struct rt_spi_device spi_device;
+        static struct tina_spi_cs  spi_cs;
+        rt_err_t result;
+
+        DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+        spi_cs.cs = SPI_TCTRL_SS_SEL_SS0;
+
+        DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+        gpio_set_func(GPIO_PORT_C, GPIO_PIN_1, IO_FUN_1);
+
+        DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+        result = rt_spi_bus_attach_device(&spi_device, "spi00", "spi0", (void *)&spi_cs);
+        if (result != RT_EOK)
+        {
+            DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+            return result;
+        }
+    }
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+#endif
+
+#ifdef TINA_USING_SPI1
+    /* register spi bus */
+    {
+        rt_err_t result;
+
+        gpio_set_func(GPIO_PORT_A, GPIO_PIN_1,  IO_FUN_5);
+        gpio_set_func(GPIO_PORT_A, GPIO_PIN_2,  IO_FUN_5);
+        gpio_set_func(GPIO_PORT_A, GPIO_PIN_3, IO_FUN_5);
+
+        result = tina_spi_bus_register((SPI_T *)SPI1_BASE_ADDR, "spi1");
+        if (result != RT_EOK)
+        {
+            DEBUG_PRINTF("register spi bus faild: %d\n", result);
+            return result;
+        }
+    }
+
+    DEBUG_PRINTF("attach cs\n");
+    /* attach cs */
+    {
+        static struct rt_spi_device spi_device;
+        static struct tina_spi_cs spi_cs;
+        rt_err_t result;
+
+        spi_cs.cs = SPI_TCTRL_SS_SEL_SS0;
+        gpio_set_func(GPIO_PORT_A, GPIO_PIN_0,  IO_FUN_5);
+
+        result = rt_spi_bus_attach_device(&spi_device, "spi10", "spi1", (void *)&spi_cs);
+        if (result != RT_EOK)
+        {
+            DEBUG_PRINTF("attach cs faild: %d\n", result);
+            return result;
+        }
+    }
+#endif
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_hw_spi_init);
+#endif

bsp/allwinner_tina/drivers/spi/drv_spi.h

@@ -0,0 +1,428 @@
+/*
+ * File      : drv_spi.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-02-08     RT-Thread    the first version
+ */
+
+#ifndef __DRV_SPI_H__
+#define __DRV_SPI_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/********************** private ************************************/
+
+#define SPI0_BASE_ADDR     (0x01C05000)
+#define SPI1_BASE_ADDR     (0x01C06000)
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+typedef struct
+{
+    volatile rt_uint32_t VER;               /* SPI Version number Register,                          Address offset: 0x00   */
+    volatile rt_uint32_t CTRL;              /* SPI Global Control Register,                          Address offset: 0x04   */
+    volatile rt_uint32_t TCTRL;             /* SPI Transfer Control Register,                        Address offset: 0x08   */
+    volatile rt_uint32_t RESERVED1[1];      /* Reserved, 0x0C                                                               */
+    volatile rt_uint32_t IER;               /* SPI Interrupt Control Register,                       Address offset: 0x10   */
+    volatile rt_uint32_t STA;               /* SPI Interrupt Status Register,                        Address offset: 0x14   */
+    volatile rt_uint32_t FCTL;              /* SPI FIFO Control Register,                            Address offset: 0x18   */
+    volatile rt_uint32_t FST;               /* SPI FIFO Status Register,                             Address offset: 0x1C   */
+    volatile rt_uint32_t WAIT;              /* SPI Wait Clock Counter Register,                      Address offset: 0x20   */
+    volatile rt_uint32_t CCTR;              /* SPI Clock Rate Control Register,                      Address offset: 0x24   */
+    volatile rt_uint32_t RESERVED2[2];      /* Reserved, 0x28-0x2C                                                          */
+    volatile rt_uint32_t BC;                /* SPI Master mode Burst Control Register,               Address offset: 0x30   */
+    volatile rt_uint32_t TC;                /* SPI Master mode Transmit Counter Register,            Address offset: 0x34   */
+    volatile rt_uint32_t BCC;               /* SPI Burst Control Register,                           Address offset: 0x38   */
+    volatile rt_uint32_t RESERVED3[19];     /* Reserved, 0x3C-0x84                                                          */
+    volatile rt_uint32_t NDMA_MODE_CTRL;    /* SPI Nomal DMA Mode Control Regist                     Address offset: 0x88   */
+    volatile rt_uint32_t RESERVED4[93];     /* Reserved, 0x8C-0x1FC                                                         */
+    volatile rt_uint32_t TXD;               /* SPI TX Date Register,                                 Address offset: 0x200  */
+    volatile rt_uint32_t RESERVED5[63];     /* Reserved, 0x204-0x2FC                                                        */
+    volatile rt_uint32_t RXD;               /* SPI RX Date Register,                                 Address offset: 0x300  */
+} SPI_T;
+
+/*
+ * @brief SPI Global Control Register
+ */
+#define SPI_CTRL_RST_SHIFT                  (31)
+#define SPI_CTRL_RST_MASK                   (0x1U << SPI_CTRL_RST_SHIFT)
+
+#define SPI_CTRL_TP_EN_SHIFT                (7)
+#define SPI_CTRL_TP_EN_MASK                 (0x1U << SPI_CTRL_TP_EN_SHIFT)
+
+#define SPI_CTRL_MODE_SHIFT                 (1)
+#define SPI_CTRL_MODE_MASK                  (0x1U << SPI_CTRL_MODE_SHIFT)
+typedef enum
+{
+    SPI_CTRL_MODE_SLAVE = 0 << SPI_CTRL_MODE_SHIFT,
+    SPI_CTRL_MODE_MASTER = 1 << SPI_CTRL_MODE_SHIFT
+} SPI_CTRL_Mode;
+
+#define SPI_CTRL_EN_SHIFT                   (0)
+#define SPI_CTRL_EN_MASK                    (0x1U << SPI_CTRL_EN_SHIFT)
+typedef enum
+{
+    SPI_CTRL_EN_DISABLE = 0 << SPI_CTRL_EN_SHIFT,
+    SPI_CTRL_EN_ENABLE = 1 << SPI_CTRL_EN_SHIFT
+} SPI_CTRL_En;
+
+/*
+ * @brief SPI Transfer Control Register
+ */
+#define SPI_TCTRL_XCH_SHIFT                 (31)
+#define SPI_TCTRL_XCH_MASK                  (0x1U << SPI_TCTRL_XCH_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_XCH_IDLE = 0 << SPI_TCTRL_XCH_SHIFT,
+    SPI_TCTRL_XCH_START = 1 << SPI_TCTRL_XCH_SHIFT
+} SPI_TCTRL_Xch;
+
+#define SPI_TCTRL_SDDM_SHIFT                (14)
+#define SPI_TCTRL_SDDM_MASK                 (0x0U << SPI_TCTRL_SDDM_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_SDDM_SEND_NODELAY = 0 << SPI_TCTRL_SDDM_SHIFT,
+    SPI_TCTRL_SDDM_SEND_DELAY = 1 << SPI_TCTRL_SDDM_SHIFT
+} SPI_TCTRL_Sddm;
+
+#define SPI_TCTRL_SDM_SHIFT                 (13)
+#define SPI_TCTRL_SDM_MASK                  (0x1U << SPI_TCTRL_SDM_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_SDM_SAMPLE_NODELAY = 1 << SPI_TCTRL_SDM_SHIFT,
+    SPI_TCTRL_SDM_SAMPLE_DELAY = 0 << SPI_TCTRL_SDM_SHIFT
+} SPI_TCTRL_Sdm;
+
+#define SPI_TCTRL_FBS_SHIFT                 (12)
+#define SPI_TCTRL_FBS_MASK                  (0x1U << SPI_TCTRL_FBS_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_FBS_MSB = 0 << SPI_TCTRL_FBS_SHIFT,
+    SPI_TCTRL_FBS_LSB = 1 << SPI_TCTRL_FBS_SHIFT
+} SPI_TCTRL_Fbs;
+
+#define SPI_TCTRL_SDC_SHIFT                 (11)
+#define SPI_TCTRL_SDC_MASK                  (0x1U << SPI_TCTRL_SDC_SHIFT)
+
+#define SPI_TCTRL_RPSM_SHIFT                (10)
+#define SPI_TCTRL_RPSM_MASK                 (0x1U << SPI_TCTRL_RPSM_SHIFT)
+
+#define SPI_TCTRL_DDB_SHIFT                 (9)
+#define SPI_TCTRL_DDB_MASK                  (0x1U << SPI_TCTRL_DDB_SHIFT)
+
+#define SPI_TCTRL_DHB_SHIFT                 (8)
+#define SPI_TCTRL_DHB_MASK                  (0x1U << SPI_TCTRL_DHB_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_DHB_FULL_DUPLEX = 0 << SPI_TCTRL_DHB_SHIFT,
+    SPI_TCTRL_DHB_HALF_DUPLEX = 1 << SPI_TCTRL_DHB_SHIFT
+} SPI_TCTRL_DHB_Duplex;
+
+#define SPI_TCTRL_SS_LEVEL_SHIFT            (7)
+#define SPI_TCTRL_SS_LEVEL_MASK             (0x1U << SPI_TCTRL_SS_LEVEL_SHIFT)
+
+#define SPI_TCTRL_SS_OWNER_SHIFT            (6)
+#define SPI_TCTRL_SS_OWNER_MASK             (0x1U << SPI_TCTRL_SS_OWNER_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_SS_OWNER_CONTROLLER = 0 << SPI_TCTRL_SS_OWNER_SHIFT,
+    SPI_TCTRL_SS_OWNER_SOFTWARE = 1 << SPI_TCTRL_SS_OWNER_SHIFT
+} SPI_TCTRL_SS_OWNER;
+
+#define SPI_TCTRL_SS_SEL_SHIFT              (4)
+#define SPI_TCTRL_SS_SEL_MASK               (0x3U << SPI_TCTRL_SS_SEL_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_SS_SEL_SS0 = 0 << SPI_TCTRL_SS_SEL_SHIFT,
+    SPI_TCTRL_SS_SEL_SS1 = 1 << SPI_TCTRL_SS_SEL_SHIFT,
+    SPI_TCTRL_SS_SEL_SS2 = 2 << SPI_TCTRL_SS_SEL_SHIFT,
+    SPI_TCTRL_SS_SEL_SS3 = 3 << SPI_TCTRL_SS_SEL_SHIFT
+} SPI_TCTRL_SS_Sel;
+
+#define SPI_TCTRL_SS_CTL_SHIFT              (3)
+#define SPI_TCTRL_SS_CTL_MASK               (0x1U << SPI_TCTRL_SS_CTL_SHIFT)
+
+#define SPI_TCTRL_SPOL_SHIFT                (2)
+#define SPI_TCTRL_SPOL_MASK                 (0x1U << SPI_TCTRL_SPOL_SHIFT)
+
+#define SPI_TCTRL_CPOL_SHIFT                (1)
+#define SPI_TCTRL_CPOL_MASK                 (0x1U << SPI_TCTRL_CPOL_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_CPOL_HIGH = 0 << SPI_TCTRL_CPOL_SHIFT,
+    SPI_TCTRL_CPOL_LOW = 1 << SPI_TCTRL_CPOL_SHIFT
+} SPI_TCTRL_Cpol;
+
+#define SPI_TCTRL_CPHA_SHIFT                (0)
+#define SPI_TCTRL_CPHA_MASK                 (0x1U << SPI_TCTRL_CPHA_SHIFT)
+typedef enum
+{
+    SPI_TCTRL_CPHA_PHASE0  = 0 << SPI_TCTRL_CPHA_SHIFT,
+    SPI_TCTRL_CPHA_PHASE1  = 1 << SPI_TCTRL_CPHA_SHIFT
+} SPI_TCTRL_Cpha;
+
+typedef enum
+{
+    SPI_SCLK_Mode0 = 0 << SPI_TCTRL_CPHA_SHIFT,
+    SPI_SCLK_Mode1 = 1 << SPI_TCTRL_CPHA_SHIFT,
+    SPI_SCLK_Mode2 = 2 << SPI_TCTRL_CPHA_SHIFT,
+    SPI_SCLK_Mode3 = 3 << SPI_TCTRL_CPHA_SHIFT
+} SPI_SCLK_Mode;
+
+/*
+ * @brief SPI Interrupt Control Register
+ */
+#define SPI_IER_SS_INT_EN_SHIFT             (13)
+#define SPI_IER_SS_INT_EN_MASK              (0x1U << SPI_IER_SS_INT_EN_SHIFT)
+
+#define SPI_IER_TC_INT_EN_SHIFT             (12)
+#define SPI_IER_TC_INT_EN_MASK              (0x1U << SPI_IER_TC_INT_EN_SHIFT)
+
+#define SPI_IER_TF_UDR_INT_EN_SHIFT         (11)
+#define SPI_IER_TF_UDR_INT_EN_MASK          (0x1U << SPI_IER_TF_UDR_INT_EN_SHIFT)
+
+#define SPI_IER_TF_OVF_INT_EN_SHIFT         (10)
+#define SPI_IER_TF_OVF_INT_EN_MASK          (0x1U << SPI_IER_TF_OVF_INT_EN_SHIFT)
+
+#define SPI_IER_RF_UDR_INT_EN_SHIFT         (9)
+#define SPI_IER_RF_UDR_INT_EN_MASK          (0x1U << SPI_IER_RF_UDR_INT_EN_SHIFT)
+
+#define SPI_IER_RF_OVF_INT_EN_SHIFT         (8)
+#define SPI_IER_RF_OVF_INT_EN_MASK          (0x1U << SPI_IER_RF_OVF_INT_EN_SHIFT)
+
+#define SPI_IER_TF_FUL_INT_EN_SHIFT         (6)
+#define SPI_IER_TF_FUL_INT_EN_MASK          (0x1U << SPI_IER_TF_FUL_INT_EN_SHIFT)
+
+#define SPI_IER_TX_EMP_INT_EN_SHIFT         (5)
+#define SPI_IER_TX_EMP_INT_EN_MASK          (0x1U << SPI_IER_TX_EMP_INT_EN_SHIFT)
+
+#define SPI_IER_TX_ERQ_INT_EN_SHIFT         (4)
+#define SPI_IER_TX_ERQ_INT_EN_MASK          (0x1U << SPI_IER_TX_ERQ_INT_EN_SHIFT)
+
+#define SPI_IER_RF_FUL_INT_EN_SHIFT         (2)
+#define SPI_IER_RF_FUL_INT_EN_MASK          (0x1U << SPI_IER_RF_FUL_INT_EN_SHIFT)
+
+#define SPI_IER_RX_EMP_INT_EN_SHIFT         (1)
+#define SPI_IER_RX_EMP_INT_EN_MASK          (0x1U << SPI_IER_RX_EMP_INT_EN_SHIFT)
+
+#define SPI_IER_RF_RDY_INT_EN_SHIFT         (0)
+#define SPI_IER_RF_RDY_INT_EN_MASK          (0x1U << SPI_IER_RF_RDY_INT_EN_SHIFT)
+
+/*
+ * @brief SPI Interrupt Status Register
+ */
+#define SPI_STA_SSI_SHIFT                   (13)
+#define SPI_STA_SSI_MASK                    (0x1U << SPI_STA_SSI_SHIFT)
+
+#define SPI_STA_TC_SHIFT                    (12)
+#define SPI_STA_TC_MASK                     (0x1U << SPI_STA_TC_SHIFT)
+
+#define SPI_STA_TF_UDF_SHIFT                (11)
+#define SPI_STA_TF_UDF_MASK                 (0x1U << SPI_STA_TF_UDF_SHIFT)
+
+#define SPI_STA_TF_OVF_SHIFT                (10)
+#define SPI_STA_TF_OVF_MASK                 (0x1U << SPI_STA_TF_OVF_SHIFT)
+
+#define SPI_STA_RX_UDF_SHIFT                (9)
+#define SPI_STA_RX_UDF_MASK                 (0x1U << SPI_STA_RX_UDF_SHIFT)
+
+#define SPI_STA_RX_OVF_SHIFT                (8)
+#define SPI_STA_RX_OVF_MASK                 (0x1U << SPI_STA_RX_OVF_SHIFT)
+
+#define SPI_STA_TX_FULL_SHIFT               (6)
+#define SPI_STA_TX_FULL_MASK                (0x1U << SPI_STA_TX_FULL_SHIFT)
+
+#define SPI_STA_TX_EMP_SHIFT                (5)
+#define SPI_STA_TX_EMP_MASK                 (0x1U << SPI_STA_TX_EMP_SHIFT)
+
+#define SPI_STA_TX_READY_SHIFT              (4)
+#define SPI_STA_TX_READY_MASK               (0x1U << SPI_STA_TX_READY_SHIFT)
+
+#define SPI_STA_RX_FULL_SHIFT               (2)
+#define SPI_STA_RX_FULL_MASK                (0x1U << SPI_STA_RX_FULL_SHIFT)
+
+#define SPI_STA_RX_EMP_SHIFT                (1)
+#define SPI_STA_RX_EMP_MASK                 (0x1U << SPI_STA_RX_EMP_SHIFT)
+
+#define SPI_STA_RX_RDY_SHIFT                (0)
+#define SPI_STA_RX_RDY_MASK                 (0x1U << SPI_STA_RX_RDY_SHIFT)
+
+/*
+ * @brief SPI FIFO Control Register
+ */
+#define SPI_FCTL_TF_RST_SHIFT               (31)
+#define SPI_FCTL_TF_RST_MASK                (0x1U << SPI_FCTL_TF_RST_SHIFT)
+
+#define SPI_FCTL_TF_TEST_EN_SHIFT           (30)
+#define SPI_FCTL_TF_TEST_EN_MASK            (0x1U << SPI_FCTL_TF_TEST_EN_SHIFT)
+
+#define SPI_FCTL_TF_DRQ_EN_SHIFT            (24)
+#define SPI_FCTL_TF_DRQ_EN_MASK             (0x1U << SPI_FCTL_TF_DRQ_EN_SHIFT)
+#define SPI_FCTL_TF_DRQ_EN_BIT              HAL_BIT(24)
+
+#define SPI_FCTL_TX_TRIG_LEVEL_SHIFT        (16)
+#define SPI_FCTL_TX_TRIG_LEVEL_MASK         (0xFFU << SPI_FCTL_TX_TRIG_LEVEL_SHIFT)
+
+#define SPI_FCTL_RF_RST_SHIFT               (15)
+#define SPI_FCTL_RF_RST_MASK                (0x1U << SPI_FCTL_RF_RST_SHIFT)
+
+#define SPI_FCTL_RF_TEST_SHIFT              (14)
+#define SPI_FCTL_RF_TEST_MASK               (0x1U << SPI_FCTL_RF_TEST_SHIFT)
+
+#define SPI_FCTL_RF_DRQ_EN_SHIFT            (8)
+#define SPI_FCTL_RF_DRQ_EN_MASK             (0x1U << SPI_FCTL_RF_DRQ_EN_SHIFT)
+
+#define SPI_FCTL_RX_TRIG_LEVEL_SHIFT        (0)
+#define SPI_FCTL_RX_TRIG_LEVEL_MASK         (0xFFU << SPI_FCTL_RX_TRIG_LEVEL_SHIFT)
+
+/*
+ * @brief SPI FIFO Status Registe
+ */
+#define SPI_FST_TB_WR_SHIFT                 (31)
+#define SPI_FST_TB_WR_MASK                  (0x1U << SPI_FST_TB_WR_SHIFT)
+
+#define SPI_FST_TB_CNT_SHIFT                (28)
+#define SPI_FST_TB_CNT_MASK                 (0x7U << SPI_FST_TB_CNT_SHIFT)
+
+#define SPI_FST_TF_CNT_SHIFT                (16)
+#define SPI_FST_TF_CNT_MASK                 (0xFFU << SPI_FST_TF_CNT_SHIFT)
+
+#define SPI_FST_RB_WR_SHIFT                 (15)
+#define SPI_FST_RB_WR_MASK                  (0x1U << SPI_FST_RB_WR_SHIFT)
+
+#define SPI_FST_RB_CNT_SHIFT                (12)
+#define SPI_FST_RB_CNT_MASK                 (0x7U << SPI_FST_RB_CNT_SHIFT)
+
+#define SPI_FST_RF_CNT_SHIFT                (0)
+#define SPI_FST_RF_CNT_MASK                 (0xFFU << SPI_FST_RF_CNT_SHIFT)
+
+/*
+ * @brief SPI Wait Clock Counter Register
+ */
+#define SPI_WAIT_SWC_SHIFT                  (16)
+#define SPI_WAIT_SWC_MASK                   (0xFU << SPI_WAIT_SWC_SHIFT)
+
+#define SPI_WAIT_WCC_SHIFT                  (0)
+#define SPI_WAIT_WCC_MASK                   (0xFFFFU << SPI_WAIT_WCC_SHIFT)
+
+/*
+ * @brief SPI Clock Rate Control Register
+ */
+#define SPI_CCTR_DRS_SHIFT                  (12)
+#define SPI_CCTR_DRS_MASK                   (0x1U << SPI_CCTR_DRS_SHIFT)
+typedef enum
+{
+    SPI_CCTR_DRS_type_divRate1 = 0 << SPI_CCTR_DRS_SHIFT,
+    SPI_CCTR_DRS_type_divRate2 = 1 << SPI_CCTR_DRS_SHIFT
+} SPI_CCTR_DRS_type;
+
+#define SPI_CCTR_CDR1_SHIFT                 (8)
+#define SPI_CCTR_CDR1_MASK                  (0xFU << SPI_CCTR_CDR1_SHIFT)
+
+#define SPI_CCTR_CDR2_SHIFT                 (0)
+#define SPI_CCTR_CDR2_MASK                  (0xFFU << SPI_CCTR_CDR2_SHIFT)
+
+/*
+ * @brief SPI Master mode Burst Control Register
+ */
+#define SPI_BC_MBC_SHIFT                    (0)
+#define SPI_BC_MBC_MASK                     (0xFFFFFFU << SPI_BC_MBC_SHIFT)
+
+/*
+ * @brief SPI Master mode Transmit Counter Register
+ */
+#define SPI_TC_MWTC_SHIFT                   (0)
+#define SPI_TC_MWTC_MASK                    (0xFFFFFFU << SPI_TC_MWTC_SHIFT)
+
+/*
+ * @brief SPI Burst Control Register
+ */
+#define SPI_BCC_DRM_SHIFT                   (28)
+#define SPI_BCC_DRM_MASK                    (0x1U << SPI_BCC_DRM_SHIFT)
+
+#define SPI_BCC_DBC_SHIFT                   (24)
+#define SPI_BCC_DBC_MASK                    (0xFU << SPI_BCC_DBC_SHIFT)
+
+#define SPI_BCC_STC_SHIFT                   (0)
+#define SPI_BCC_STC_MASK                    (0xFFFFFFU << SPI_BCC_STC_SHIFT)
+
+/*
+ * @brief SPI Nomal DMA Mode Control Regist
+ */
+#define SPI_NDMA_MODE_CTRL_SHIFT            (0)
+#define SPI_NDMA_MODE_CTRL_MASK             (0xFFU << SPI_NDMA_MODE_CTRL_SHIFT)
+
+/*
+ * @brief SPI TX Date Register
+ */
+#define SPI_TXD_SHIFT                       (0)
+#define SPI_TXD_MASK                        (0xFFFFFFFFU << SPI_TXD_SHIFT)
+
+/*
+ * @brief SPI RX Date Register
+ */
+#define SPI_RXD_SHIFT                       (0)
+#define SPI_RXD_MASK                        (0xFFFFFFFFU << SPI_RXD_SHIFT)
+
+/* other */
+#define SPI_FIFO_SIZE                       (64)
+#define SPI_MAX_WAIT_MS (2000)
+#define SPI_SOURCE_CLK (24 * 1000 * 1000)
+
+/* io ops */
+#define HAL_BIT(pos)                        (1U << (pos))
+
+#define HAL_SET_BIT(reg, mask)              ((reg) |= (mask))
+#define HAL_CLR_BIT(reg, mask)              ((reg) &= ~(mask))
+#define HAL_GET_BIT(reg, mask)              ((reg) & (mask))
+#define HAL_GET_BIT_VAL(reg, shift, vmask)  (((reg) >> (shift)) & (vmask))
+
+#define HAL_MODIFY_REG(reg, clr_mask, set_mask) \
+    ((reg) = (((reg) & (~(clr_mask))) | (set_mask)))
+
+/* access LSBs of a 32-bit register (little endian only) */
+#define HAL_REG_32BIT(reg_addr)  (*((volatile rt_uint32_t *)(reg_addr)))
+#define HAL_REG_16BIT(reg_addr)  (*((volatile rt_uint16_t *)(reg_addr)))
+#define HAL_REG_8BIT(reg_addr)   (*((volatile rt_uint8_t  *)(reg_addr)))
+
+#define HAL_WAIT_FOREVER    OS_WAIT_FOREVER
+
+#define HAL_ARRAY_SIZE(a)   (sizeof((a)) / sizeof((a)[0]))
+
+struct tina_spi
+{
+    SPI_T *spi;
+    unsigned int spi_gate;
+    struct rt_spi_bus *spi_bus;
+};
+
+struct tina_spi_cs
+{
+    SPI_TCTRL_SS_Sel cs;
+};
+/* public function */
+rt_err_t r6_spi_bus_register(SPI_T *spi, const char *spi_bus_name);
+
+#ifdef __cplusplus
+}
+#endif
+#endif //

bsp/allwinner_tina/drivers/spi/drv_spi_flash.c

@@ -0,0 +1,80 @@
+/*
+ * File      : drv_spi_flash.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-02-08     RT-Thread    the first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+
+#define DBG_ENABLE
+#define DBG_SECTION_NAME  "[FLASH]"
+#define DBG_LEVEL         DBG_LOG
+#define DBG_COLOR
+#include <rtdbg.h>
+
+#define SPI_FLASH_DEVICE_NAME       "spi00"
+#define SPI_FLASH_CHIP              "gd25qxx"
+
+//#define DEBUG
+
+#ifdef DEBUG
+#define DEBUG_PRINTF(...)   rt_kprintf(__VA_ARGS__)
+#else
+#define DEBUG_PRINTF(...)
+#endif
+
+#ifdef TINA_USING_SPI_FLASH
+
+#include "spi_flash.h"
+
+#if defined(RT_USING_SFUD)
+#include "spi_flash_sfud.h"
+rt_spi_flash_device_t spi_device;
+int rt_hw_spi_flash_with_sfud_init(void)
+{
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+    spi_device = rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME);
+    if (spi_device == NULL)
+    {
+        DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+        return RT_ERROR;
+    };
+
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+    return RT_EOK;
+}
+INIT_PREV_EXPORT(rt_hw_spi_flash_with_sfud_init);
+
+#elif defined(RT_USING_W25QXX)
+#include "spi_flash_w25qxx.h"
+
+int rt_hw_spi_flash_init(void)
+{
+    DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
+    return w25qxx_init(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME);
+}
+INIT_DEVICE_EXPORT(rt_hw_spi_flash_init);
+
+#endif
+
+#endif

bsp/asm9260t/rtconfig.py

@@ -17,7 +17,7 @@ elif CROSS_TOOL == 'keil':
     EXEC_PATH   = 'C:/Keil_v5'
 elif CROSS_TOOL == 'iar':
     PLATFORM    = 'iar'
-    IAR_PATH    = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0'
+    EXEC_PATH    = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0'
 
 if os.getenv('RTT_EXEC_PATH'):
     EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -113,7 +113,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --endian=little'
     CFLAGS += ' -e'
     CFLAGS += ' --fpu=none'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
     CFLAGS += ' --silent'
 
     AFLAGS = '--cpu '+ DEVICE
@@ -135,5 +135,5 @@ elif PLATFORM == 'iar':
     LFLAGS += ' --map ' + MAP_FILE
     LFLAGS += ' --silent'
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = 'ielftool  --silent --bin $TARGET ' + TARGET_NAME

bsp/at91sam9260/rtconfig.py

@@ -16,7 +16,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil_v5'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0'
+	EXEC_PATH 	= 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0'
 
 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -111,7 +111,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --endian=little'
     CFLAGS += ' -e'
     CFLAGS += ' --fpu=none'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
     CFLAGS += ' --silent'
 
     AFLAGS = '--cpu '+ DEVICE
@@ -133,5 +133,5 @@ elif PLATFORM == 'iar':
     LFLAGS += ' --map ' + MAP_FILE
     LFLAGS += ' --silent'
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = 'ielftool  --silent --bin $TARGET ' + TARGET_NAME

bsp/gd32450z-eval/project.ewp

@@ -298,32 +298,28 @@
         </option>
         <option>
           <name>CCIncludePath2</name>
-          <state>$PROJ_DIR$\../../components/drivers/include</state>
-          <state>$PROJ_DIR$\../../libcpu/arm/cortex-m4</state>
-          <state>$PROJ_DIR$\Libraries/CMSIS</state>
-          <state>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Include</state>
-          <state>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/include</state>
-          <state>$PROJ_DIR$\../../components/finsh</state>
-          <state>$PROJ_DIR$\Libraries/CMSIS/GD/GD32F4xx/Include</state>
-          <state>$PROJ_DIR$\../../components/net/lwip-2.0.2/src</state>
+          <state>$PROJ_DIR$\..\..\include</state>
+          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\netif</state>
+          <state>$PROJ_DIR$\Libraries\CMSIS\GD\GD32F4xx\Include</state>
+          <state>$PROJ_DIR$\..\..\libcpu\arm\common</state>
+          <state>$PROJ_DIR$\..\..\components\drivers\include</state>
+          <state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
+          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src</state>
           <state>$PROJ_DIR$\drivers</state>
-          <state>$PROJ_DIR$\../../libcpu/arm/common</state>
-          <state>$PROJ_DIR$\../../components/dfs/filesystems/devfs</state>
+          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\ipv4</state>
+          <state>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Include</state>
           <state>$PROJ_DIR$\.</state>
-          <state>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/arch/include</state>
-          <state>$PROJ_DIR$\../../components/drivers/spi</state>
-          <state>$PROJ_DIR$\../../components/gui/include/rtgui</state>
-          <state>$PROJ_DIR$\../../components/dfs/filesystems/elmfat</state>
-          <state>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/include/posix</state>
+          <state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m4</state>
+          <state>$PROJ_DIR$\..\..\components\drivers\spi\sfud\inc</state>
+          <state>$PROJ_DIR$\..\..\components\dfs\include</state>
+          <state>$PROJ_DIR$\Libraries\CMSIS</state>
+          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include</state>
+          <state>$PROJ_DIR$\..\..\components\drivers\spi</state>
           <state>$PROJ_DIR$\applications</state>
-          <state>$PROJ_DIR$\../../include</state>
-          <state>$PROJ_DIR$\../../components/gui/include/rtgui/widgets</state>
-          <state>$PROJ_DIR$\../../components/gui/include</state>
-          <state>$PROJ_DIR$\../../components/drivers/spi/sfud/inc</state>
-          <state>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/include/netif</state>
-          <state>$PROJ_DIR$\../../components/dfs/include</state>
-          <state>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/include/ipv4</state>
-          <state>$PROJ_DIR$\../../components/gui/src</state>
+          <state>$PROJ_DIR$\..\..\components\finsh</state>
+          <state>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat</state>
+          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\posix</state>
+          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\arch\include</state>
         </option>
         <option>
           <name>CCStdIncCheck</name>
@@ -1268,32 +1264,28 @@
         <option>
           <name>CCIncludePath2</name>
           <state />
-          <state>$PROJ_DIR$\../../components/drivers/include</state>
-          <state>$PROJ_DIR$\../../libcpu/arm/cortex-m4</state>
-          <state>$PROJ_DIR$\Libraries/CMSIS</state>
-          <state>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Include</state>
-          <state>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/include</state>
-          <state>$PROJ_DIR$\../../components/finsh</state>
-          <state>$PROJ_DIR$\Libraries/CMSIS/GD/GD32F4xx/Include</state>
-          <state>$PROJ_DIR$\../../components/net/lwip-2.0.2/src</state>
+          <state>$PROJ_DIR$\..\..\include</state>
+          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\netif</state>
+          <state>$PROJ_DIR$\Libraries\CMSIS\GD\GD32F4xx\Include</state>
+          <state>$PROJ_DIR$\..\..\libcpu\arm\common</state>
+          <state>$PROJ_DIR$\..\..\components\drivers\include</state>
+          <state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
+          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src</state>
           <state>$PROJ_DIR$\drivers</state>
-          <state>$PROJ_DIR$\../../libcpu/arm/common</state>
-          <state>$PROJ_DIR$\../../components/dfs/filesystems/devfs</state>
+          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\ipv4</state>
+          <state>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Include</state>
           <state>$PROJ_DIR$\.</state>
-          <state>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/arch/include</state>
-          <state>$PROJ_DIR$\../../components/drivers/spi</state>
-          <state>$PROJ_DIR$\../../components/gui/include/rtgui</state>
-          <state>$PROJ_DIR$\../../components/dfs/filesystems/elmfat</state>
-          <state>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/include/posix</state>
+          <state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m4</state>
+          <state>$PROJ_DIR$\..\..\components\drivers\spi\sfud\inc</state>
+          <state>$PROJ_DIR$\..\..\components\dfs\include</state>
+          <state>$PROJ_DIR$\Libraries\CMSIS</state>
+          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include</state>
+          <state>$PROJ_DIR$\..\..\components\drivers\spi</state>
           <state>$PROJ_DIR$\applications</state>
-          <state>$PROJ_DIR$\../../include</state>
-          <state>$PROJ_DIR$\../../components/gui/include/rtgui/widgets</state>
-          <state>$PROJ_DIR$\../../components/gui/include</state>
-          <state>$PROJ_DIR$\../../components/drivers/spi/sfud/inc</state>
-          <state>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/include/netif</state>
-          <state>$PROJ_DIR$\../../components/dfs/include</state>
-          <state>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/include/ipv4</state>
-          <state>$PROJ_DIR$\../../components/gui/src</state>
+          <state>$PROJ_DIR$\..\..\components\finsh</state>
+          <state>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat</state>
+          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\posix</state>
+          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\arch\include</state>
         </option>
         <option>
           <name>CCStdIncCheck</name>
@@ -1941,561 +1933,429 @@
     </settings>
   </configuration>
   <group>
-    <name>Drivers</name>
-    <file>
-      <name>$PROJ_DIR$\drivers/board.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\drivers/drv_exmc_sdram.c</name>
-    </file>
+    <name>Applications</name>
     <file>
-      <name>$PROJ_DIR$\drivers/drv_usart.c</name>
+      <name>$PROJ_DIR$\applications\application.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\drivers/drv_enet.c</name>
+      <name>$PROJ_DIR$\applications\rtgui_demo.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\drivers/synopsys_emac.c</name>
+      <name>$PROJ_DIR$\applications\startup.c</name>
     </file>
+  </group>
+  <group>
+    <name>Drivers</name>
     <file>
-      <name>$PROJ_DIR$\drivers/drv_lcd.c</name>
+      <name>$PROJ_DIR$\drivers\board.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\drivers/gd32f450z_lcd_eval.c</name>
+      <name>$PROJ_DIR$\drivers\drv_exmc_sdram.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\drivers/drv_spi_flash.c</name>
+      <name>$PROJ_DIR$\drivers\drv_usart.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\drivers/drv_spi.c</name>
+      <name>$PROJ_DIR$\drivers\drv_enet.c</name>
     </file>
-  </group>
-  <group>
-    <name>Applications</name>
     <file>
-      <name>$PROJ_DIR$\applications/application.c</name>
+      <name>$PROJ_DIR$\drivers\synopsys_emac.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\applications/rtgui_demo.c</name>
+      <name>$PROJ_DIR$\drivers\drv_spi_flash.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\applications/startup.c</name>
+      <name>$PROJ_DIR$\drivers\drv_spi.c</name>
     </file>
   </group>
   <group>
     <name>GD32_Lib</name>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_adc.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_can.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_crc.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_ctc.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_dac.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_dbg.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_dci.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_dma.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_enet.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_exmc.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_fmc.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_fwdgt.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_i2c.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_ipa.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_iref.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_pmu.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_rtc.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_sdio.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_spi.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_tli.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_trng.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_wwdgt.c</name>
+      <name>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_wwdgt.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c</name>
+      <name>$PROJ_DIR$\Libraries\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\Libraries/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f4xx.s</name>
+      <name>$PROJ_DIR$\Libraries\CMSIS\GD\GD32F4xx\Source\IAR\startup_gd32f4xx.s</name>
     </file>
   </group>
   <group>
     <name>Kernel</name>
     <file>
-      <name>$PROJ_DIR$\../../src/clock.c</name>
+      <name>$PROJ_DIR$\..\..\src\clock.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../src/components.c</name>
+      <name>$PROJ_DIR$\..\..\src\components.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../src/device.c</name>
+      <name>$PROJ_DIR$\..\..\src\device.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../src/idle.c</name>
+      <name>$PROJ_DIR$\..\..\src\idle.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../src/ipc.c</name>
+      <name>$PROJ_DIR$\..\..\src\ipc.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../src/irq.c</name>
+      <name>$PROJ_DIR$\..\..\src\irq.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../src/kservice.c</name>
+      <name>$PROJ_DIR$\..\..\src\kservice.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../src/mem.c</name>
+      <name>$PROJ_DIR$\..\..\src\mem.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../src/memheap.c</name>
+      <name>$PROJ_DIR$\..\..\src\memheap.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../src/mempool.c</name>
+      <name>$PROJ_DIR$\..\..\src\mempool.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../src/module.c</name>
+      <name>$PROJ_DIR$\..\..\src\module.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../src/object.c</name>
+      <name>$PROJ_DIR$\..\..\src\object.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../src/scheduler.c</name>
+      <name>$PROJ_DIR$\..\..\src\scheduler.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../src/signal.c</name>
+      <name>$PROJ_DIR$\..\..\src\signal.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../src/thread.c</name>
+      <name>$PROJ_DIR$\..\..\src\thread.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../src/timer.c</name>
+      <name>$PROJ_DIR$\..\..\src\timer.c</name>
     </file>
   </group>
   <group>
     <name>CORTEX-M4</name>
     <file>
-      <name>$PROJ_DIR$\../../libcpu/arm/cortex-m4/cpuport.c</name>
+      <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m4\cpuport.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../libcpu/arm/cortex-m4/context_iar.S</name>
+      <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m4\context_iar.S</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../libcpu/arm/common/backtrace.c</name>
+      <name>$PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../libcpu/arm/common/div0.c</name>
+      <name>$PROJ_DIR$\..\..\libcpu\arm\common\div0.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../libcpu/arm/common/showmem.c</name>
+      <name>$PROJ_DIR$\..\..\libcpu\arm\common\showmem.c</name>
     </file>
   </group>
   <group>
-    <name>DeviceDrivers</name>
-    <file>
-      <name>$PROJ_DIR$\../../components/drivers/i2c/i2c_core.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/drivers/i2c/i2c_dev.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/drivers/i2c/i2c-bit-ops.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/drivers/serial/serial.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/drivers/rtc/rtc.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/drivers/spi/spi_core.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/drivers/spi/spi_dev.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/drivers/spi/spi_flash_sfud.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/drivers/spi/sfud/src/sfud.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/drivers/src/completion.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/drivers/src/dataqueue.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/drivers/src/pipe.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/drivers/src/ringbuffer.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/drivers/src/waitqueue.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/drivers/src/workqueue.c</name>
-    </file>
-  </group>
-  <group>
-    <name>finsh</name>
-    <file>
-      <name>$PROJ_DIR$\../../components/finsh/shell.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/finsh/symbol.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/finsh/cmd.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/finsh/finsh_compiler.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/finsh/finsh_error.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/finsh/finsh_heap.c</name>
-    </file>
+    <name>Filesystem</name>
     <file>
-      <name>$PROJ_DIR$\../../components/finsh/finsh_init.c</name>
+      <name>$PROJ_DIR$\..\..\components\dfs\src\dfs.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/finsh/finsh_node.c</name>
+      <name>$PROJ_DIR$\..\..\components\dfs\src\dfs_file.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/finsh/finsh_ops.c</name>
+      <name>$PROJ_DIR$\..\..\components\dfs\src\dfs_fs.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/finsh/finsh_parser.c</name>
+      <name>$PROJ_DIR$\..\..\components\dfs\src\dfs_posix.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/finsh/finsh_var.c</name>
+      <name>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs\devfs.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/finsh/finsh_vm.c</name>
+      <name>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\dfs_elm.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/finsh/finsh_token.c</name>
+      <name>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\ff.c</name>
     </file>
   </group>
   <group>
-    <name>GuiEngine</name>
-    <file>
-      <name>$PROJ_DIR$\../../components/gui/src/asc12font.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/gui/src/asc16font.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/gui/src/blit.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/gui/src/box.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/gui/src/color.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/gui/src/container.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/gui/src/dc.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/gui/src/dc_blend.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/gui/src/dc_buffer.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/gui/src/dc_client.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/gui/src/dc_hw.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/gui/src/dc_rotozoom.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/gui/src/dc_trans.c</name>
-    </file>
+    <name>DeviceDrivers</name>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/filerw.c</name>
+      <name>$PROJ_DIR$\..\..\components\drivers\i2c\i2c_core.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/font.c</name>
+      <name>$PROJ_DIR$\..\..\components\drivers\i2c\i2c_dev.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/font_bmp.c</name>
+      <name>$PROJ_DIR$\..\..\components\drivers\i2c\i2c-bit-ops.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/font_fnt.c</name>
+      <name>$PROJ_DIR$\..\..\components\drivers\rtc\rtc.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/font_freetype.c</name>
+      <name>$PROJ_DIR$\..\..\components\drivers\serial\serial.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/font_hz_bmp.c</name>
+      <name>$PROJ_DIR$\..\..\components\drivers\spi\spi_core.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/font_hz_file.c</name>
+      <name>$PROJ_DIR$\..\..\components\drivers\spi\spi_dev.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/hz12font.c</name>
+      <name>$PROJ_DIR$\..\..\components\drivers\spi\spi_flash_sfud.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/hz16font.c</name>
+      <name>$PROJ_DIR$\..\..\components\drivers\spi\sfud\src\sfud.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/image.c</name>
+      <name>$PROJ_DIR$\..\..\components\drivers\src\completion.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/image_bmp.c</name>
+      <name>$PROJ_DIR$\..\..\components\drivers\src\dataqueue.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/image_container.c</name>
+      <name>$PROJ_DIR$\..\..\components\drivers\src\pipe.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/image_hdc.c</name>
+      <name>$PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/image_jpg.c</name>
+      <name>$PROJ_DIR$\..\..\components\drivers\src\waitqueue.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/image_png.c</name>
+      <name>$PROJ_DIR$\..\..\components\drivers\src\workqueue.c</name>
     </file>
+  </group>
+  <group>
+    <name>finsh</name>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/image_xpm.c</name>
+      <name>$PROJ_DIR$\..\..\components\finsh\shell.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/matrix.c</name>
+      <name>$PROJ_DIR$\..\..\components\finsh\symbol.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/mouse.c</name>
+      <name>$PROJ_DIR$\..\..\components\finsh\cmd.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/region.c</name>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_compiler.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/rtgui_app.c</name>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_error.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/rtgui_driver.c</name>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_heap.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/rtgui_object.c</name>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_init.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/rtgui_system.c</name>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_node.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/server.c</name>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_ops.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/title.c</name>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_parser.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/topwin.c</name>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_var.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/widget.c</name>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_vm.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/gui/src/window.c</name>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_token.c</name>
     </file>
   </group>
   <group>
     <name>lwIP</name>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/arch/sys_arch.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/api/api_lib.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/api/api_msg.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/api/err.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\api_lib.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/api/netbuf.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\api_msg.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/api/netdb.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\err.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/api/netifapi.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\netbuf.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/api/sockets.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\netdb.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/api/tcpip.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\netifapi.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/def.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\sockets.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/dns.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\tcpip.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/inet_chksum.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\def.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/init.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\dns.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/ip.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/memp.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\init.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/netif.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ip.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/pbuf.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\memp.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/raw.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\netif.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/stats.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\pbuf.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/sys.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\raw.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/tcp.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\stats.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/tcp_in.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\sys.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/tcp_out.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\tcp.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/timeouts.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\tcp_in.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/udp.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\tcp_out.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/netif/ethernet.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\timeouts.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/netif/ethernetif.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\udp.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/netif/lowpan6.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\netif\ethernet.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/ipv4/autoip.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/ipv4/dhcp.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/ipv4/etharp.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/ipv4/icmp.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/ipv4/igmp.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/ipv4/ip4.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/ipv4/ip4_addr.c</name>
-    </file>
-    <file>
-      <name>$PROJ_DIR$\../../components/net/lwip-2.0.2/src/core/ipv4/ip4_frag.c</name>
-    </file>
-  </group>
-  <group>
-    <name>Filesystem</name>
-    <file>
-      <name>$PROJ_DIR$\../../components/dfs/src/dfs.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/dfs/src/dfs_file.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/dfs/src/dfs_fs.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/dfs/src/dfs_posix.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/dfs/filesystems/devfs/devfs.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/dfs/filesystems/elmfat/dfs_elm.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/dfs/filesystems/elmfat/ff.c</name>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c</name>
     </file>
   </group>
 </project>

bsp/imx6ul/rtconfig.py

@@ -8,15 +8,12 @@ CROSS_TOOL='gcc'
 if os.getenv('RTT_CC'):
     CROSS_TOOL = os.getenv('RTT_CC')
 
-if  CROSS_TOOL == 'gcc':
-    PLATFORM 	= 'gcc'
-    EXEC_PATH   = '/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
-elif CROSS_TOOL == 'keil':
-    PLATFORM 	= 'armcc'
-    EXEC_PATH 	= 'C:/Keil'
+# only support GNU GCC compiler.
+PLATFORM  = 'gcc'
+EXEC_PATH = '/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
 
 if os.getenv('RTT_EXEC_PATH'):
-	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
 
 BUILD = 'debug'
 
@@ -54,48 +51,3 @@ if PLATFORM == 'gcc':
 
     POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
                   SIZE + ' $TARGET \n'
-
-elif PLATFORM == 'armcc':
-    # toolchains
-    CC = 'armcc'
-    CXX = 'armcc'
-    AS = 'armasm'
-    AR = 'armar'
-    LINK = 'armlink'
-    TARGET_EXT = 'axf'
-
-    DEVICE = ' --device DARMP'
-    CFLAGS = DEVICE + ' --apcs=interwork'
-    AFLAGS = DEVICE
-    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-imx6.map --scatter imx6.sct'
-
-    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
-    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
-
-    EXEC_PATH += '/arm/bin40/'
-
-    if BUILD == 'debug':
-        CFLAGS += ' -g -O0'
-        AFLAGS += ' -g'
-    else:
-        CFLAGS += ' -O2'
-
-    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
-
-elif PLATFORM == 'iar':
-    # toolchains
-    CC = 'iccarm'
-    AS = 'iasmarm'
-    AR = 'iarchive'
-    LINK = 'ilinkarm'
-    TARGET_EXT = 'out'
-
-    DEVICE = ' --cpu DARMP'
-
-    CFLAGS = ''
-    AFLAGS = ''
-    LFLAGS = ' --config imx6.icf'
-
-    EXEC_PATH += '/arm/bin/'
-    RT_USING_MINILIBC = False
-    POST_ACTION = ''

bsp/imxrt1052-evk/.config

@@ -76,6 +76,7 @@ CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
 CONFIG_FINSH_USING_SYMTAB=y
 CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
 CONFIG_FINSH_THREAD_PRIORITY=20
 CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_CMD_SIZE=80
@@ -134,7 +135,13 @@ CONFIG_RT_USING_RTC=y
 # CONFIG_RT_USING_SOFT_RTC is not set
 # CONFIG_RTC_SYNC_USING_NTP is not set
 CONFIG_RT_USING_SDIO=y
-# CONFIG_RT_USING_SPI is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_SPI_MSD is not set
+# CONFIG_RT_USING_SFUD is not set
+# CONFIG_RT_USING_W25QXX is not set
+# CONFIG_RT_USING_GD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
 # CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_WIFI is not set
 
@@ -297,6 +304,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # tools packages
 #
 # CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
 # CONFIG_PKG_USING_IPERF is not set
@@ -307,12 +315,82 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_FASTLZ is not set
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_SAMPLES is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
 
 #
 # example package: hello
 #
 # CONFIG_PKG_USING_HELLO is not set
-# CONFIG_PKG_USING_MULTIBUTTON is not set
 CONFIG_SOC_IMXRT1052=y
+CONFIG_BOARD_RT1050_EVK=y
+# CONFIG_BOARD_RT1050_FIRE is not set
+
+#
+# RT1050 Bsp Config
+#
+
+#
+# Select uart drivers
+#
 CONFIG_RT_USING_UART1=y
-CONFIG_RT_USING_HP_RTC=y
+# CONFIG_RT_USING_UART2 is not set
+# CONFIG_RT_USING_UART3 is not set
+# CONFIG_RT_USING_UART4 is not set
+# CONFIG_RT_USING_UART5 is not set
+# CONFIG_RT_USING_UART6 is not set
+# CONFIG_RT_USING_UART7 is not set
+# CONFIG_RT_USING_UART8 is not set
+
+#
+# Select spi bus and dev drivers
+#
+CONFIG_LPSPI_CLK_SOURCE_FROM_PLL3PFD1=y
+# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL3PFD0 is not set
+# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL2 is not set
+# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL2PFD2 is not set
+CONFIG_LPSPI_CLK_SOURCE=0
+CONFIG_LPSPI_CLK_SOURCE_DIVIDER=8
+# CONFIG_RT_USING_SPIBUS1 is not set
+# CONFIG_RT_USING_SPIBUS2 is not set
+# CONFIG_RT_USING_SPIBUS3 is not set
+CONFIG_RT_USING_SPIBUS4=y
+CONFIG_LPSPI4_SCK_GPIO_1=y
+# CONFIG_LPSPI4_SCK_GPIO_2 is not set
+CONFIG_LPSPI4_SDO_GPIO_1=y
+# CONFIG_LPSPI4_SDO_GPIO_2 is not set
+CONFIG_LPSPI4_SDI_GPIO_1=y
+# CONFIG_LPSPI4_SDI_GPIO_2 is not set
+# CONFIG_RT_USING_SPI_FLASH is not set
+
+#
+# Select i2c bus drivers
+#
+CONFIG_LPI2C_CLOCK_SOURCE_DIVIDER=4
+CONFIG_RT_USING_I2C1=y
+# CONFIG_RT_USING_I2C1_BITOPS is not set
+# CONFIG_RT_USING_I2C2 is not set
+# CONFIG_RT_USING_I2C3 is not set
+# CONFIG_RT_USING_I2C4 is not set
+
+#
+# Select lcd driver
+#
+
+#
+# Notice: Evk Board para: 480*272 4 4 8 2 40 10 106 45
+#
+CONFIG_RT_USING_LCD=y
+CONFIG_LCD_WIDTH=480
+CONFIG_LCD_HEIGHT=272
+CONFIG_LCD_HFP=4
+CONFIG_LCD_VFP=4
+CONFIG_LCD_HBP=8
+CONFIG_LCD_VBP=2
+CONFIG_LCD_HSW=40
+CONFIG_LCD_VSW=10
+CONFIG_LCD_BL_PIN=106
+CONFIG_LCD_RST_PIN=45
+CONFIG_RT_USING_SDRAM=y
+CONFIG_RT_USING_RTC_HP=y

bsp/imxrt1052-evk/Kconfig

@@ -23,17 +23,387 @@ config SOC_IMXRT1052
     select ARCH_ARM_CORTEX_M7
     default y
 
-if RT_USING_SERIAL
-config RT_USING_UART1
-    bool "Using RT_USING_UART1"
-    default y 
-endif
+# RT1050 board select!
+choice
+    prompt "RT1050 Board select"
+    default BOARD_RT1050_EVK
+    config BOARD_RT1050_EVK
+        bool "RT1050_EVK"
+    config BOARD_RT1050_FIRE
+        bool "RT1050_FIRE"
+endchoice
 
-if RT_USING_RTC
-config RT_USING_HP_RTC
-    bool "Using RT_USING_HP_RTC"
-    default n 
-endif
+menu "RT1050 Bsp Config" 
+
+menu "Select uart drivers"
+    config RT_USING_UART1
+        bool "Using uart1"
+        select RT_USING_SERIAL
+        default y 
+    config RT_USING_UART2
+        bool "Using uart2"
+        select RT_USING_SERIAL
+        default n 
+    config RT_USING_UART3
+        bool "Using uart3"
+        select RT_USING_SERIAL
+        default n 
+    config RT_USING_UART4
+        bool "Using uart4"
+        select RT_USING_SERIAL
+        default n 
+    config RT_USING_UART5
+        bool "Using uart5"
+        select RT_USING_SERIAL
+        default n 
+    config RT_USING_UART6
+        bool "Using uart6"
+        select RT_USING_SERIAL
+        default n 
+    config RT_USING_UART7
+        bool "Using uart7"
+        select RT_USING_SERIAL
+        default n 
+    config RT_USING_UART8
+        bool "Using uart8"
+        select RT_USING_SERIAL
+        default n 
+endmenu
+
+menu "Select spi bus and dev drivers"
+    choice 
+        prompt "SPI bus clock source"
+        default LPSPI_CLK_SOURCE_FROM_PLL3PFD1
+
+        config LPSPI_CLK_SOURCE_FROM_PLL3PFD1
+            bool "PLL3PFD1"
+        config LPSPI_CLK_SOURCE_FROM_PLL3PFD0
+            bool "PLL3PFD0"
+        config LPSPI_CLK_SOURCE_FROM_PLL2
+            bool "PLL2"
+        config LPSPI_CLK_SOURCE_FROM_PLL2PFD2
+            bool "PLL2PFD2"
+    endchoice
+    config LPSPI_CLK_SOURCE
+        int
+        default 0 if LPSPI_CLK_SOURCE_FROM_PLL3PFD1
+        default 1 if LPSPI_CLK_SOURCE_FROM_PLL3PFD0
+        default 2 if LPSPI_CLK_SOURCE_FROM_PLL2
+        default 3 if LPSPI_CLK_SOURCE_FROM_PLL2PFD2
+
+    config LPSPI_CLK_SOURCE_DIVIDER
+        int "SPI bus clock source divider"
+        range 1 8
+        default 8
+
+    config RT_USING_SPIBUS1
+        bool "Using spi1 bus"
+        select RT_USING_SPI
+        default n 
+    choice
+        prompt "spi1 bus sck io choice"
+        default LPSPI1_SCK_GPIO_1
+        depends on RT_USING_SPIBUS1
+        config LPSPI1_SCK_GPIO_1
+            bool "GPIO_EMC_27"
+        config LPSPI1_SCK_GPIO_2
+            bool "GPIO_SD_B0_00"
+    endchoice
+    choice
+        prompt "spi1 bus sdo io choice"
+        default LPSPI1_SDO_GPIO_1
+        depends on RT_USING_SPIBUS1
+        config LPSPI1_SDO_GPIO_1
+            bool "GPIO_EMC_28"
+        config LPSPI1_SDO_GPIO_2
+            bool "GPIO_SD_B0_02"
+    endchoice
+    choice
+        prompt "spi1 bus sdi io choice"
+        default LPSPI1_SDI_GPIO_1
+        depends on RT_USING_SPIBUS1
+        config LPSPI1_SDI_GPIO_1
+            bool "GPIO_EMC_29"
+        config LPSPI1_SDI_GPIO_2
+            bool "GPIO_SD_B0_03"
+    endchoice
+
+    config RT_USING_SPIBUS2
+        bool "Using spi2 bus"
+        select RT_USING_SPI
+        default n 
+    choice
+        prompt "spi2 bus sck io choice"
+        default LPSPI2_SCK_GPIO_1
+        depends on RT_USING_SPIBUS2
+        config LPSPI2_SCK_GPIO_1
+            bool "GPIO_SD_B1_07"
+        config LPSPI2_SCK_GPIO_2
+            bool "GPIO_EMC_00"
+    endchoice
+    choice
+        prompt "spi2 bus sdo io choice"
+        default LPSPI2_SDO_GPIO_1
+        depends on RT_USING_SPIBUS2
+        config LPSPI2_SDO_GPIO_1
+            bool "GPIO_SD_B1_08"
+        config LPSPI2_SDO_GPIO_2
+            bool "GPIO_EMC_02"
+    endchoice
+    choice
+        prompt "spi2 bus sdi io choice"
+        default LPSPI2_SDI_GPIO_1
+        depends on RT_USING_SPIBUS2
+        config LPSPI2_SDI_GPIO_1
+            bool "GPIO_SD_B1_09"
+        config LPSPI2_SDI_GPIO_2
+            bool "GPIO_EMC_03"
+    endchoice
+
+    config RT_USING_SPIBUS3
+        bool "Using spi3 bus"
+        select RT_USING_SPI
+        default n 
+    choice
+        prompt "spi3 bus sck io choice"
+        default LPSPI3_SCK_GPIO_1
+        depends on RT_USING_SPIBUS3
+        config LPSPI3_SCK_GPIO_1
+            bool "GPIO_AD_B1_15"
+        config LPSPI3_SCK_GPIO_2
+            bool "GPIO_AD_B0_00"
+    endchoice
+    choice
+        prompt "spi3 bus sdo io choice"
+        default LPSPI3_SDO_GPIO_1
+        depends on RT_USING_SPIBUS3
+        config LPSPI3_SDO_GPIO_1
+            bool "GPIO_AD_B1_14"
+        config LPSPI3_SDO_GPIO_2
+            bool "GPIO_AD_B0_01"
+    endchoice
+    choice
+        prompt "spi3 bus sdi io choice"
+        default LPSPI3_SDI_GPIO_1
+        depends on RT_USING_SPIBUS3
+        config LPSPI3_SDI_GPIO_1
+            bool "GPIO_AD_B1_13"
+        config LPSPI3_SDI_GPIO_2
+            bool "GPIO_AD_B0_02"
+    endchoice
+
+    config RT_USING_SPIBUS4
+        bool "Using spi4 bus"
+        select RT_USING_SPI
+        default y 
+    choice
+        prompt "spi4 bus sck io choice"
+        default LPSPI4_SCK_GPIO_1
+        depends on RT_USING_SPIBUS4
+        config LPSPI4_SCK_GPIO_1
+            bool "GPIO_B0_03"
+        config LPSPI4_SCK_GPIO_2
+            bool "GPIO_B1_07"
+    endchoice
+    choice
+        prompt "spi4 bus sdo io choice"
+        default LPSPI4_SDO_GPIO_1
+        depends on RT_USING_SPIBUS4
+        config LPSPI4_SDO_GPIO_1
+            bool "GPIO_B0_02"
+        config LPSPI4_SDO_GPIO_2
+            bool "GPIO_B1_06"
+    endchoice
+    choice
+        prompt "spi4 bus sdi io choice"
+        default LPSPI4_SDI_GPIO_1
+        depends on RT_USING_SPIBUS4
+        config LPSPI4_SDI_GPIO_1
+            bool "GPIO_B0_01"
+        config LPSPI4_SDI_GPIO_2
+            bool "GPIO_B1_05"
+    endchoice
+
+    config RT_USING_SPI_FLASH
+        bool "Using spi flash with sfud"
+        default n 
+        select RT_USING_SPI
+        select RT_USING_SFUD
+        select RT_USING_PIN
+    choice 
+        prompt "SPI flash using spibus"
+        default SPI_FLASH_USING_SPIBUS4
+        depends on RT_USING_SPI_FLASH
+
+        config SPI_FLASH_USING_SPIBUS1
+            bool "spi1"
+            select RT_USING_SPIBUS1
+        config SPI_FLASH_USING_SPIBUS2
+            bool "spi2"
+            select RT_USING_SPIBUS2
+        config SPI_FLASH_USING_SPIBUS3
+            bool "spi3"
+            select RT_USING_SPIBUS3
+        config SPI_FLASH_USING_SPIBUS4
+            bool "spi4"
+            select RT_USING_SPIBUS4
+    endchoice
+    config SPI_FLASH_USING_SPIBUS_NAME
+        string
+        default "spi1" if SPI_FLASH_USING_SPIBUS1
+        default "spi2" if SPI_FLASH_USING_SPIBUS2
+        default "spi3" if SPI_FLASH_USING_SPIBUS3
+        default "spi4" if SPI_FLASH_USING_SPIBUS4
+
+    config SPI_FLASH_NAME
+        string "SPI flash device name"
+        default "flash0" 
+        depends on RT_USING_SPI_FLASH
+
+    config SPI_FLASH_USING_CS_PIN
+        int "SPI flash cs pin index"
+        default 79 
+        range 1 127
+        depends on RT_USING_SPI_FLASH
+endmenu
+
+menu "Select iic bus drivers"
+
+    config RT_USING_HW_I2C1
+        bool "using hardware i2c1"
+        select RT_USING_I2C
+        default y 
+    choice
+        prompt "i2c1 bus badurate choice"
+        default HW_I2C1_BADURATE_100kHZ
+        depends on RT_USING_HW_I2C1
+        config HW_I2C1_BADURATE_100kHZ
+            bool "100kHZ"
+        config HW_I2C1_BADURATE_400kHZ
+            bool "400kHZ"
+    endchoice
+	
+    config RT_USING_HW_I2C2
+        bool "using hardware i2c2"
+        select RT_USING_I2C
+        default n 
+    choice
+        prompt "i2c2 bus badurate choice"
+        default HW_I2C2_BADURATE_100kHZ
+        depends on RT_USING_HW_I2C2
+        config HW_I2C2_BADURATE_100kHZ
+            bool "100kHZ"
+        config HW_I2C2_BADURATE_400kHZ
+            bool "400kHZ"
+    endchoice
+	
+    config RT_USING_HW_I2C3
+        bool "using hardware i2c3"
+        select RT_USING_I2C
+        default n 
+    choice
+        prompt "i2c3 bus badurate choice"
+        default HW_I2C3_BADURATE_100kHZ
+        depends on RT_USING_HW_I2C3
+        config HW_I2C3_BADURATE_100kHZ
+            bool "100kHZ"
+        config HW_I2C3_BADURATE_400kHZ
+            bool "400kHZ"
+    endchoice
+	
+    config RT_USING_HW_I2C4
+        bool "using hardware i2c4"
+        select RT_USING_I2C
+        default n 
+    choice
+        prompt "i2c4 bus badurate choice"
+        default HW_I2C4_BADURATE_100kHZ
+        depends on RT_USING_HW_I2C4
+        config HW_I2C4_BADURATE_100kHZ
+            bool "100kHZ"
+        config HW_I2C4_BADURATE_400kHZ
+            bool "400kHZ"
+    endchoice
+
+endmenu
+
+menu "Select lcd driver"
+    if RT_USING_LCD && BOARD_RT1050_EVK
+    comment "Notice: Evk Board para: 480*272 4 4 8 2 40 10 106 45" 
+    endif
+
+    if RT_USING_LCD && BOARD_RT1050_FIRE
+    comment "Notice: Fire Board para: 800*480 4 4 8 2 40 10 58 45" 
+    endif
+
+    config RT_USING_LCD
+        bool "Using lcd"
+        default n 
+
+    config LCD_WIDTH
+        int "Width pixel num"
+        default 480 if BOARD_RT1050_EVK
+        default 800 if BOARD_RT1050_FIRE
+        depends on RT_USING_LCD
+    config LCD_HEIGHT
+        int "Height pixel num" 
+        default 272 if BOARD_RT1050_EVK
+        default 480 if BOARD_RT1050_FIRE
+        depends on RT_USING_LCD
+    config LCD_HFP
+        int "HFP"
+        default 4 if BOARD_RT1050_EVK
+        default 4 if BOARD_RT1050_FIRE
+        depends on RT_USING_LCD
+    config LCD_VFP
+        int "VFP"
+        default 4 if BOARD_RT1050_EVK
+        default 4 if BOARD_RT1050_FIRE
+        depends on RT_USING_LCD
+    config LCD_HBP
+        int "HBP"
+        default 8 if BOARD_RT1050_EVK
+        default 8 if BOARD_RT1050_FIRE
+        depends on RT_USING_LCD
+    config LCD_VBP
+        int "VBP"
+        default 2 if BOARD_RT1050_EVK
+        default 2 if BOARD_RT1050_FIRE
+        depends on RT_USING_LCD
+    config LCD_HSW
+        int "HSW"
+        default 40 if BOARD_RT1050_EVK
+        default 40 if BOARD_RT1050_FIRE
+        depends on RT_USING_LCD
+    config LCD_VSW
+        int "VSW"
+        default 10 if BOARD_RT1050_EVK
+        default 10 if BOARD_RT1050_FIRE
+        depends on RT_USING_LCD 
+    config LCD_BL_PIN
+        int "Backlight pin index"
+        default 106 if BOARD_RT1050_EVK
+        default 58  if BOARD_RT1050_FIRE
+        depends on RT_USING_LCD 
+    config LCD_RST_PIN
+        int "Reset pin index"
+        default 45 if BOARD_RT1050_EVK
+        default 45 if BOARD_RT1050_FIRE
+        depends on RT_USING_LCD 
+endmenu
+
+#menu "Select SDRAM driver"
+    config RT_USING_SDRAM
+        bool "Using sdram"
+        default y 
+#endmenu
+
+#menu "Select RTC driver"
+    config RT_USING_RTC_HP
+        bool "Using hp rtc"
+        select RT_USING_RTC
+        default n 
+#endmenu
 
 if RT_USING_USB_DEVICE
     choice
@@ -47,4 +417,4 @@ if RT_USING_USB_DEVICE
     endchoice
 endif
 
-
+endmenu

bsp/imxrt1052-evk/Libraries/SConscript

@@ -5,7 +5,11 @@ Import('RTT_ROOT')
 from building import *
 
 cwd = GetCurrentDir()
-src  = Glob('drivers/*.c')
+src = Glob('drivers/*.c')
+
+if GetDepend('BOARD_RT1050_FIRE'): 
+    SrcRemove(src, r'drivers\fsl_enet.c')
+
 SrcRemove(src, 'drivers/dataqueue.c')
 src += Glob('common/chip/*.c')
 src += [cwd + '/system_MIMXRT1052.c']

bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.c

@@ -1345,7 +1345,13 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
 #else
         address = (uint32_t)curBuffDescrip->buffer;
 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
-        memcpy((void *)address, data, length);
+        
+        {
+            // Change SDK to reduce memory copy
+            extern void pbuf2mem(const uint8_t *data, void *dataptr, uint32_t len);
+            pbuf2mem(data, (void *)address, length);
+        }
+        //memcpy((void *)address, data, length);
         /* Set data length. */
         curBuffDescrip->length = length;
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE

bsp/imxrt1052-evk/README.md

@@ -0,0 +1,77 @@
+#  i.MX RT1050
+
+## 1. 简介
+
+​i.MX RT 1050系列芯片，是由 NXP 半导体公司推出的跨界处理器芯片。它基于应用处理器的芯片架构，采用了微控制器的内核Cortex-M7，从而具有应用处理器的高性能及丰富的功能，又具备传统微控制器的易用、实时及低功耗的特性。
+
+BSP默认支持的i.MX RT1052处理器具备以下简要的特性：
+
+| 介绍 | 描述 |
+| ---- | ---- |
+| 主CPU平台 | ARM Cortex-M7 |
+| 最高频率 | 600MHz |
+| 内部存储器 | 512KB  SRAM |
+| 外部存储器接口 | NAND、eMMC、QuadSPI NOR Flash 和 Parallel NOR Flash |
+
+## 2. 编译说明
+
+i.MX RT1050板级包支持MDK5﹑IAR开发环境和GCC编译器，以下是具体版本信息：
+
+| IDE/编译器 | 已测试版本 |
+| ---------- | --------- |
+| MDK5 | MDK525 |
+| IAR | IAR 8.11.3.13984 |
+| GCC | GCC 5.4.1 20160919 (release) |
+
+## 3.BSP使用
+
+### 3.1 配置工程
+
+i.MX RT1052 BSP支持多块开发板，包括官方开发板MIMXRT1050-EVK，野火的i.MX RT1052开发板。如果不是基于官方开发板，那么重新配置并生成工程：
+
+- 在bsp下打开env工具
+- 输入`menuconfig`命令，`RT1052 Board select (***)-->`选择正确的开发板。
+- 输入`scons --target=mdk5 -s`或`scons --target=iar`来生成需要的工程
+
+### 3.2 下载和仿真
+
+#### 3.2.1 MIMXRT1050-EVK
+
+EVK开发板有板载OpenSDA仿真器，仿真器还连接到i.MX RT1052的UART1。使用USB线连接电脑和仿真器的USB口(J28)，就可以进行下载和仿真。在终端工具里打开仿真器的虚拟串口就可以看到shell输出
+
+#### 3.2.2 野火开发板
+
+### 3.3 运行结果
+
+如果编译 & 烧写无误，当复位设备后，会在串口上（PuTTY）看到RT-Thread的启动logo信息：
+
+TODO
+
+## 4. 驱动支持情况及计划
+
+| 驱动 | 支持情况  | 备注 |
+| ------ | ----  | ------ |
+| UART | 支持 | UART 1~8 |
+| GPIO | 支持 |  |
+| IIC | 支持 | IIC 1~4 |
+| SPI | 支持 | SPI 1~4 |
+| ETH | 支持 | 野火开发板的ETH还没支持 |
+| LCD | 支持 |  |
+| RTC | 支持 |  |
+| SDIO | 支持 | 暂时仅仅支持一个SDIO，还不支持中断方式 |
+| SDRAM | 支持 | 32M SDRAM，后面2M作为Non Cache区域 |
+
+## 5. 联系人信息
+
+维护人：
+
+- [tanek](https://github.com/TanekLiang)
+- [liu2guang](https://github.com/liu2guang)
+
+## 6. 参考
+
+- [MIMXRT1050-EVK: i.MX RT1050评估套件概述](https://www.nxp.com/cn/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK)
+- [MIMXRT1050 EVK Board Hardware User’s Guide ](https://www.nxp.com/docs/en/user-guide/MIMXRT1050EVKHUG.pdf)
+- [i.MX RT Series Crossover Processor Quick Start Guide](https://www.nxp.com/docs/en/user-guide/IMXRT1050EVKQSG.pdf)
+- [i.MX RT Series Crossover Processor Fact Sheet](https://www.nxp.com/docs/en/fact-sheet/IMXRTSERIESFS.pdf)
+- [Evaluation Kit Based on i.MX RT1050 Crossover Processors](https://www.nxp.com/docs/en/fact-sheet/IMXRT1050EVKFS.pdf)

bsp/imxrt1052-evk/SConstruct

@@ -46,3 +46,26 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 
 # make a building
 DoBuilding(TARGET, objs)
+
+def Update_MDKFlashProgrammingAlgorithm(flash_dict):
+    import xml.etree.ElementTree as etree
+    from utils import xml_indent
+
+    project_tree = etree.parse('project.uvoptx')
+    root = project_tree.getroot()
+    out = file('project.uvoptx', 'wb')
+
+    for elem in project_tree.iterfind('.//Target/TargetOption/TargetDriverDllRegistry/SetRegEntry'):
+        Key = elem.find('Key')
+        if Key.text in flash_dict.keys():
+            elem.find('Name').text = flash_dict[Key.text]
+
+    xml_indent(root)
+    out.write(etree.tostring(root, encoding='utf-8'))
+    out.close()
+
+if GetOption('target') and GetDepend('BOARD_RT1050_FIRE'):
+    Update_MDKFlashProgrammingAlgorithm({
+        "JL2CM3": '-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI-JP0 -JP0 -RST1 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FCF000 -FN1 -FF0iMXRT1052_W25Q256JV_By_Fire -FS060000000 -FL02000000',
+        "CMSIS_AGDI": '-X"Any" -UAny -O974 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FCF000 -FN1 -FF0iMXRT1052_W25Q256JV_By_Fire -FS060000000 -FL02000000',
+    })

bsp/imxrt1052-evk/applications/main.c

@@ -38,29 +38,29 @@
 
 void dump_clock(void)
 {
-    rt_kprintf("CPU clock: %d\n",                   CLOCK_GetFreq(kCLOCK_CpuClk));
-	rt_kprintf("AHB clock : %d\n",                  CLOCK_GetFreq(kCLOCK_AhbClk));
-	rt_kprintf("SEMC clock : %d\n",                 CLOCK_GetFreq(kCLOCK_SemcClk));
-	rt_kprintf("IPG clock : %d\n",                  CLOCK_GetFreq(kCLOCK_IpgClk));
-	rt_kprintf("OSC clock selected : %d\n",         CLOCK_GetFreq(kCLOCK_OscClk));
-	rt_kprintf("RTC clock: %d\n",                   CLOCK_GetFreq(kCLOCK_RtcClk));
-	rt_kprintf("ARMPLLCLK : %d\n",                  CLOCK_GetFreq(kCLOCK_ArmPllClk));
-	rt_kprintf("USB1PLLCLK : %d\n",                 CLOCK_GetFreq(kCLOCK_Usb1PllClk));
-	rt_kprintf("USB1PLLPDF0CLK : %d\n",             CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk));
-	rt_kprintf("USB1PLLPFD1CLK : %d\n",             CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk));
-	rt_kprintf("USB1PLLPFD2CLK : %d\n",             CLOCK_GetFreq(kCLOCK_Usb1PllPfd2Clk));
-	rt_kprintf("USB1PLLPFD3CLK : %d\n",             CLOCK_GetFreq(kCLOCK_Usb1PllPfd3Clk));
-	rt_kprintf("USB2PLLCLK : %d\n",                 CLOCK_GetFreq(kCLOCK_Usb2PllClk));
-	rt_kprintf("SYSPLLCLK : %d\n",                  CLOCK_GetFreq(kCLOCK_SysPllClk));
-	rt_kprintf("SYSPLLPDF0CLK : %d\n",              CLOCK_GetFreq(kCLOCK_SysPllPfd0Clk));
-	rt_kprintf("SYSPLLPFD1CLK : %d\n",              CLOCK_GetFreq(kCLOCK_SysPllPfd1Clk));
-	rt_kprintf("SYSPLLPFD2CLK : %d\n",              CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk));
-	rt_kprintf("SYSPLLPFD3CLK : %d\n",              CLOCK_GetFreq(kCLOCK_SysPllPfd3Clk));
-	rt_kprintf("Enet PLLCLK ref_enetpll0 : %d\n",   CLOCK_GetFreq(kCLOCK_EnetPll0Clk));
-	rt_kprintf("Enet PLLCLK ref_enetpll1 : %d\n",   CLOCK_GetFreq(kCLOCK_EnetPll1Clk));
-	rt_kprintf("Enet PLLCLK ref_enetpll2 : %d\n",   CLOCK_GetFreq(kCLOCK_EnetPll2Clk));
-	rt_kprintf("Audio PLLCLK : %d\n",               CLOCK_GetFreq(kCLOCK_AudioPllClk));
-	rt_kprintf("Video PLLCLK : %d\n",               CLOCK_GetFreq(kCLOCK_VideoPllClk));
+    rt_kprintf("OSC clock : %d\n",                  CLOCK_GetFreq(kCLOCK_OscClk));
+    rt_kprintf("RTC clock : %d\n",                  CLOCK_GetFreq(kCLOCK_RtcClk));
+    rt_kprintf("CPU clock: %d\n",                   CLOCK_GetFreq(kCLOCK_CpuClk)); 
+    rt_kprintf("AHB clock : %d\n",                  CLOCK_GetFreq(kCLOCK_AhbClk)); 
+    rt_kprintf("SEMC clock : %d\n",                 CLOCK_GetFreq(kCLOCK_SemcClk)); 
+    rt_kprintf("IPG clock : %d\n",                  CLOCK_GetFreq(kCLOCK_IpgClk));
+    rt_kprintf("ARMPLLCLK(PLL1) : %d\n",            CLOCK_GetFreq(kCLOCK_ArmPllClk));
+    rt_kprintf("SYSPLLCLK(PLL2/528_PLL) : %d\n",    CLOCK_GetFreq(kCLOCK_SysPllClk));
+    rt_kprintf("SYSPLLPDF0CLK : %d\n",              CLOCK_GetFreq(kCLOCK_SysPllPfd0Clk));
+    rt_kprintf("SYSPLLPFD1CLK : %d\n",              CLOCK_GetFreq(kCLOCK_SysPllPfd1Clk));
+    rt_kprintf("SYSPLLPFD2CLK : %d\n",              CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk));
+    rt_kprintf("SYSPLLPFD3CLK : %d\n",              CLOCK_GetFreq(kCLOCK_SysPllPfd3Clk));
+    rt_kprintf("USB1PLLCLK(PLL3) : %d\n",           CLOCK_GetFreq(kCLOCK_Usb1PllClk));
+    rt_kprintf("USB1PLLPDF0CLK : %d\n",             CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk));
+    rt_kprintf("USB1PLLPFD1CLK : %d\n",             CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk));
+    rt_kprintf("USB1PLLPFD2CLK : %d\n",             CLOCK_GetFreq(kCLOCK_Usb1PllPfd2Clk));
+    rt_kprintf("USB1PLLPFD3CLK : %d\n",             CLOCK_GetFreq(kCLOCK_Usb1PllPfd3Clk));
+    rt_kprintf("Audio PLLCLK(PLL4) : %d\n",         CLOCK_GetFreq(kCLOCK_AudioPllClk));
+    rt_kprintf("Video PLLCLK(PLL5) : %d\n",         CLOCK_GetFreq(kCLOCK_VideoPllClk));
+    rt_kprintf("Enet PLLCLK ref_enetpll0 : %d\n",   CLOCK_GetFreq(kCLOCK_EnetPll0Clk));
+    rt_kprintf("Enet PLLCLK ref_enetpll1 : %d\n",   CLOCK_GetFreq(kCLOCK_EnetPll1Clk));
+    rt_kprintf("Enet PLLCLK ref_enetpll2 : %d\n",   CLOCK_GetFreq(kCLOCK_EnetPll2Clk));
+    rt_kprintf("USB2PLLCLK(PLL7) : %d\n",           CLOCK_GetFreq(kCLOCK_Usb2PllClk));
 }
 
 void dump_cc_info(void)

bsp/imxrt1052-evk/drivers/SConscript

@@ -2,41 +2,65 @@ Import('RTT_ROOT')
 Import('rtconfig')
 from building import *
 
-cwd     = os.path.join(str(Dir('#')), 'drivers')
+cwd = os.path.join(str(Dir('#')), 'drivers')
 
 # add the general drivers.
 src = Split("""
 board.c
 drv_uart.c
-hyper_flash_boot.c
-drv_sdram.c
+drv_cache.c
 """)
 
 CPPPATH = [cwd]
 CPPDEFINES = []
 
+# add sdram driver code
+if GetDepend('RT_USING_SDRAM'):
+    src = src + ['drv_sdram.c'] 
+
+# add pin driver code
 if GetDepend('RT_USING_PIN'):
     src += ['drv_pin.c']
 
-if GetDepend('RT_USING_HP_RTC'):
-    src += ['drv_hp_rtc.c']
+# add rtc driver code
+if GetDepend('RT_USING_RTC_HP'):
+    src = src + ['drv_rtc.c'] 
+
+# add spibus driver code
+if GetDepend('RT_USING_SPI'):
+    src += ['drv_spi_bus.c']
+
+# add spi flash driver code
+if GetDepend('RT_USING_SPI_FLASH'):
+    src += ['drv_spi_flash.c']
+
+# add i2cbus driver code
+if GetDepend('RT_USING_I2C'):
+    src += ['drv_i2c.c']
 
-if GetDepend('RT_USING_LWIP'):
-    src += ['drv_eth.c', 'fsl_phy.c']
-    CPPDEFINES += ['FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE']
-    
+# add lcd driver code
+if GetDepend('RT_USING_LCD'):
+    src += ['drv_lcd.c']
+
+# add sdio driver code
 if GetDepend('RT_USING_SDIO'):
     src += ['drv_sdio.c']
-if GetDepend('RT_USING_USB_DEVICE'):
-    src += Glob('usb/phy/*.c')
-    CPPDEFINES += ['ENDIANNESS']
-    
+
+# add usb device driver code
 if GetDepend('RT_USING_USB_DEVICE'):
     src += ['drv_usbd.c']
     src += Glob('usb/device/*.c')
-    
-if GetDepend('RT_USING_RTGUI') or GetDepend('PKG_USING_GUIENGINE'):
-    src += ['drv_lcd.c', 'drv_ft5406.c', 'drv_i2c.c']
+# add usb phy driver code
+if GetDepend('RT_USING_USB_DEVICE'):
+    src += Glob('usb/phy/*.c')
+    CPPDEFINES += ['ENDIANNESS']
+
+if GetDepend('BOARD_RT1050_EVK'):
+    src += ['hyper_flash_boot.c']
+
+    if GetDepend('RT_USING_LWIP'):
+        src += ['drv_eth.c', 'fsl_phy.c']
+        CPPDEFINES += ['FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE']
 
 if GetDepend('RT_USING_AUDIO'):
     src += ['drv_codec.c', 'fsl_wm8960.c']

bsp/imxrt1052-evk/drivers/board.c

@@ -18,7 +18,9 @@
 #include "board.h"
 #include "drv_uart.h"
 
+#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP)
 static struct rt_memheap system_heap;
+#endif
 
 /* ARM PLL configuration for RUN mode */
 const clock_arm_pll_config_t armPllConfig = { .loopDivider = 100U };
@@ -46,40 +48,39 @@ static void BOARD_BootClockRUN(void)
     /* Boot ROM did initialize the XTAL, here we only sets external XTAL OSC freq */
     CLOCK_SetXtalFreq(24000000U);
     CLOCK_SetRtcXtalFreq(32768U);
-    
+
     CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); /* Set PERIPH_CLK2 MUX to OSC */
-    CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */   
-    
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+
     /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz */
     DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
-    
+
     CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */
 #ifndef SKIP_SYSCLK_INIT
     CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL to 528M */
 #endif
-#ifndef SKIP_USB_PLL_INIT    
+#ifndef SKIP_USB_PLL_INIT
     CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */
-#endif    
+#endif
     CLOCK_SetDiv(kCLOCK_ArmDiv, 0x1); /* Set ARM PODF to 0, divide by 2 */
-    CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */ 
-    CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */ 
-    
-    CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); /* Set PRE_PERIPH_CLK to PLL1, 1200M */    
-    CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */       
-    
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */
+
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); /* Set PRE_PERIPH_CLK to PLL1, 1200M */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */
+
     /* Disable unused clock */
-    BOARD_BootClockGate();    
-    
-    /* Power down all unused PLL */    
+    BOARD_BootClockGate();
+
+    /* Power down all unused PLL */
     CLOCK_DeinitAudioPll();
     CLOCK_DeinitVideoPll();
     CLOCK_DeinitEnetPll();
     CLOCK_DeinitUsb2Pll();
 
-    /* Configure UART divider to default */
-    CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */
-    CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */    
-    
+    /* iomuxc clock (iomuxc_clk_enable): 0x03u */
+    CLOCK_EnableClock(kCLOCK_Iomuxc);
+
     /* Update core clock */
     SystemCoreClockUpdate();
 }
@@ -162,54 +163,43 @@ void rt_lowlevel_init(void)
 {
     BOARD_ConfigMPU();
 
+#if defined(RT_USING_SDRAM)
     extern int imxrt_sdram_init(void);
     imxrt_sdram_init();
+#endif
 }
 
 /**
- * This function will initial LPC8XX board.
+ * This function will initial rt1050 board.
  */
 void rt_hw_board_init()
 {
     BOARD_BootClockRUN();
 
     SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
-    
+
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
-    
+
 #ifdef RT_USING_CONSOLE
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
-    
+
 #ifdef RT_USING_HEAP
+
+#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP)
     rt_kprintf("sdram heap, begin: 0x%p, end: 0x%p\n", SDRAM_BEGIN, SDRAM_END);
-    rt_system_heap_init((void*)SDRAM_BEGIN, (void*)SDRAM_END);
+    rt_system_heap_init((void *)SDRAM_BEGIN, (void *)SDRAM_END);
 
     rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END);
     rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE);
+#else
+    rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END);
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
 #endif
-}
-
-#ifdef PKG_USING_GUIENGINE
-#include <rtgui/driver.h>
-#include "drv_lcd.h"
 
-/* initialize for gui driver */
-int rtgui_lcd_init(void)
-{
-    rt_device_t device;
-
-    imxrt_hw_lcd_init();
-
-    device = rt_device_find("lcd");
-    /* set graphic device */
-    rtgui_graphic_set_device(device);
-
-    return 0;
-}
-INIT_DEVICE_EXPORT(rtgui_lcd_init);
 #endif
+}
 
 /*@}*/

bsp/imxrt1052-evk/drivers/drv_cache.c

@@ -0,0 +1,75 @@
+/*
+ * File      : drv_cache.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-04-02     tanek        first implementation
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <fsl_cache.h>
+
+void rt_hw_cpu_icache_enable(void)
+{
+    SCB_EnableICache();
+}
+
+void rt_hw_cpu_icache_disable(void)
+{
+    SCB_DisableICache();
+}
+
+rt_base_t rt_hw_cpu_icache_status(void)
+{
+    return 0;
+}
+
+void rt_hw_cpu_icache_ops(int ops, void* addr, int size)
+{
+    if (ops & RT_HW_CACHE_INVALIDATE)
+    {
+        ICACHE_InvalidateByRange((uint32_t)addr, size);
+    }
+}
+
+void rt_hw_cpu_dcache_enable(void)
+{
+    SCB_EnableDCache();
+}
+
+void rt_hw_cpu_dcache_disable(void)
+{
+    SCB_DisableDCache();
+}
+
+rt_base_t rt_hw_cpu_dcache_status(void)
+{
+    return 0;
+}
+
+void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)
+{
+    if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE))
+    {
+        DCACHE_CleanInvalidateByRange((uint32_t)addr, size);
+    }
+    else if (ops & RT_HW_CACHE_FLUSH)
+    {
+        DCACHE_CleanByRange((uint32_t)addr, size);
+    }
+    else if (ops & RT_HW_CACHE_INVALIDATE)
+    {
+        DCACHE_InvalidateByRange((uint32_t)addr, size);
+    }
+    else
+    {
+        RT_ASSERT(0);
+    }
+}

bsp/imxrt1052-evk/drivers/drv_eth.c

@@ -16,7 +16,7 @@
 #include <rtdevice.h>
 
 #ifdef RT_USING_FINSH
-#include <finsh.h>
+    #include <finsh.h>
 #endif
 
 #include "fsl_enet.h"
@@ -50,13 +50,13 @@
 
 struct rt_imxrt_eth
 {
-	/* inherit from ethernet device */
-	struct eth_device parent;
+    /* inherit from ethernet device */
+    struct eth_device parent;
 
     enet_handle_t enet_handle;
     ENET_Type *enet_base;
     enet_data_error_stats_t error_statistic;
-	rt_uint8_t  dev_addr[MAX_ADDR_LEN];			/* hw address	*/
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];         /* hw address   */
 
     rt_bool_t tx_is_waiting;
     struct rt_semaphore tx_wait;
@@ -73,18 +73,18 @@ ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_rxDataBuff[ENET_RXBD_NUM][RT_ALIGN(ENET_
 
 static struct rt_imxrt_eth imxrt_eth_device;
 
-void _enet_rx_callback(struct rt_imxrt_eth * eth)
+void _enet_rx_callback(struct rt_imxrt_eth *eth)
 {
     rt_err_t result;
 
     ENET_DisableInterrupts(eth->enet_base, kENET_RxFrameInterrupt);
 
     result = eth_device_ready(&(eth->parent));
-    if( result != RT_EOK )
-        rt_kprintf("RX err =%d\n", result );
+    if (result != RT_EOK)
+        rt_kprintf("RX err =%d\n", result);
 }
 
-void _enet_tx_callback(struct rt_imxrt_eth * eth)
+void _enet_tx_callback(struct rt_imxrt_eth *eth)
 {
     if (eth->tx_is_waiting == RT_TRUE)
     {
@@ -95,7 +95,7 @@ void _enet_tx_callback(struct rt_imxrt_eth * eth)
 
 void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData)
 {
-    switch(event)
+    switch (event)
     {
     case kENET_RxEvent:
 
@@ -130,53 +130,53 @@ void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event,
 
 static void _enet_io_init(void)
 {
-  CLOCK_EnableClock(kCLOCK_Iomuxc);          /* iomuxc clock (iomuxc_clk_enable): 0x03u */
-
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,        /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_AD_B0_10_GPIO1_IO10,        /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_AD_B0_12_LPUART1_TX,        /* GPIO_AD_B0_12 is configured as LPUART1_TX */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_AD_B0_13_LPUART1_RX,        /* GPIO_AD_B0_13 is configured as LPUART1_RX */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B1_04_ENET_RX_DATA00,       /* GPIO_B1_04 is configured as ENET_RX_DATA00 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B1_05_ENET_RX_DATA01,       /* GPIO_B1_05 is configured as ENET_RX_DATA01 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B1_06_ENET_RX_EN,           /* GPIO_B1_06 is configured as ENET_RX_EN */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B1_07_ENET_TX_DATA00,       /* GPIO_B1_07 is configured as ENET_TX_DATA00 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B1_08_ENET_TX_DATA01,       /* GPIO_B1_08 is configured as ENET_TX_DATA01 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B1_09_ENET_TX_EN,           /* GPIO_B1_09 is configured as ENET_TX_EN */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B1_10_ENET_REF_CLK,         /* GPIO_B1_10 is configured as ENET_REF_CLK */
-      1U);                                    /* Software Input On Field: Force input path of pad GPIO_B1_10 */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B1_11_ENET_RX_ER,           /* GPIO_B1_11 is configured as ENET_RX_ER */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_EMC_40_ENET_MDC,            /* GPIO_EMC_40 is configured as ENET_MDC */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_EMC_41_ENET_MDIO,           /* GPIO_EMC_41 is configured as ENET_MDIO */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,        /* GPIO_AD_B0_09 PAD functional properties : */
-      0xB0A9u);                               /* Slew Rate Field: Fast Slew Rate
+    CLOCK_EnableClock(kCLOCK_Iomuxc);          /* iomuxc clock (iomuxc_clk_enable): 0x03u */
+
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,        /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_AD_B0_10_GPIO1_IO10,        /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_AD_B0_12_LPUART1_TX,        /* GPIO_AD_B0_12 is configured as LPUART1_TX */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_AD_B0_13_LPUART1_RX,        /* GPIO_AD_B0_13 is configured as LPUART1_RX */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_04_ENET_RX_DATA00,       /* GPIO_B1_04 is configured as ENET_RX_DATA00 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_05_ENET_RX_DATA01,       /* GPIO_B1_05 is configured as ENET_RX_DATA01 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_06_ENET_RX_EN,           /* GPIO_B1_06 is configured as ENET_RX_EN */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_07_ENET_TX_DATA00,       /* GPIO_B1_07 is configured as ENET_TX_DATA00 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_08_ENET_TX_DATA01,       /* GPIO_B1_08 is configured as ENET_TX_DATA01 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_09_ENET_TX_EN,           /* GPIO_B1_09 is configured as ENET_TX_EN */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_10_ENET_REF_CLK,         /* GPIO_B1_10 is configured as ENET_REF_CLK */
+        1U);                                    /* Software Input On Field: Force input path of pad GPIO_B1_10 */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_11_ENET_RX_ER,           /* GPIO_B1_11 is configured as ENET_RX_ER */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_EMC_40_ENET_MDC,            /* GPIO_EMC_40 is configured as ENET_MDC */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_EMC_41_ENET_MDIO,           /* GPIO_EMC_41 is configured as ENET_MDIO */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,        /* GPIO_AD_B0_09 PAD functional properties : */
+        0xB0A9u);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: medium(100MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -184,9 +184,9 @@ static void _enet_io_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_AD_B0_10_GPIO1_IO10,        /* GPIO_AD_B0_10 PAD functional properties : */
-      0xB0A9u);                               /* Slew Rate Field: Fast Slew Rate
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_AD_B0_10_GPIO1_IO10,        /* GPIO_AD_B0_10 PAD functional properties : */
+        0xB0A9u);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: medium(100MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -194,9 +194,9 @@ static void _enet_io_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_AD_B0_12_LPUART1_TX,        /* GPIO_AD_B0_12 PAD functional properties : */
-      0x10B0u);                               /* Slew Rate Field: Slow Slew Rate
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_AD_B0_12_LPUART1_TX,        /* GPIO_AD_B0_12 PAD functional properties : */
+        0x10B0u);                               /* Slew Rate Field: Slow Slew Rate
                                                  Drive Strength Field: R0/6
                                                  Speed Field: medium(100MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -204,9 +204,9 @@ static void _enet_io_init(void)
                                                  Pull / Keep Select Field: Keeper
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Down
                                                  Hyst. Enable Field: Hysteresis Disabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_AD_B0_13_LPUART1_RX,        /* GPIO_AD_B0_13 PAD functional properties : */
-      0x10B0u);                               /* Slew Rate Field: Slow Slew Rate
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_AD_B0_13_LPUART1_RX,        /* GPIO_AD_B0_13 PAD functional properties : */
+        0x10B0u);                               /* Slew Rate Field: Slow Slew Rate
                                                  Drive Strength Field: R0/6
                                                  Speed Field: medium(100MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -214,9 +214,9 @@ static void _enet_io_init(void)
                                                  Pull / Keep Select Field: Keeper
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Down
                                                  Hyst. Enable Field: Hysteresis Disabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B1_04_ENET_RX_DATA00,       /* GPIO_B1_04 PAD functional properties : */
-      0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_04_ENET_RX_DATA00,       /* GPIO_B1_04 PAD functional properties : */
+        0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: max(200MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -224,9 +224,9 @@ static void _enet_io_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B1_05_ENET_RX_DATA01,       /* GPIO_B1_05 PAD functional properties : */
-      0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_05_ENET_RX_DATA01,       /* GPIO_B1_05 PAD functional properties : */
+        0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: max(200MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -234,9 +234,9 @@ static void _enet_io_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B1_06_ENET_RX_EN,           /* GPIO_B1_06 PAD functional properties : */
-      0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_06_ENET_RX_EN,           /* GPIO_B1_06 PAD functional properties : */
+        0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: max(200MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -244,9 +244,9 @@ static void _enet_io_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B1_07_ENET_TX_DATA00,       /* GPIO_B1_07 PAD functional properties : */
-      0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_07_ENET_TX_DATA00,       /* GPIO_B1_07 PAD functional properties : */
+        0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: max(200MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -254,9 +254,9 @@ static void _enet_io_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B1_08_ENET_TX_DATA01,       /* GPIO_B1_08 PAD functional properties : */
-      0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_08_ENET_TX_DATA01,       /* GPIO_B1_08 PAD functional properties : */
+        0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: max(200MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -264,9 +264,9 @@ static void _enet_io_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B1_09_ENET_TX_EN,           /* GPIO_B1_09 PAD functional properties : */
-      0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_09_ENET_TX_EN,           /* GPIO_B1_09 PAD functional properties : */
+        0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: max(200MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -274,9 +274,9 @@ static void _enet_io_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B1_10_ENET_REF_CLK,         /* GPIO_B1_10 PAD functional properties : */
-      0x31u);                                 /* Slew Rate Field: Fast Slew Rate
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_10_ENET_REF_CLK,         /* GPIO_B1_10 PAD functional properties : */
+        0x31u);                                 /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/6
                                                  Speed Field: low(50MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -284,9 +284,9 @@ static void _enet_io_init(void)
                                                  Pull / Keep Select Field: Keeper
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Down
                                                  Hyst. Enable Field: Hysteresis Disabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B1_11_ENET_RX_ER,           /* GPIO_B1_11 PAD functional properties : */
-      0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_11_ENET_RX_ER,           /* GPIO_B1_11 PAD functional properties : */
+        0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: max(200MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -294,9 +294,9 @@ static void _enet_io_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_EMC_40_ENET_MDC,            /* GPIO_EMC_40 PAD functional properties : */
-      0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_EMC_40_ENET_MDC,            /* GPIO_EMC_40 PAD functional properties : */
+        0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: max(200MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -304,9 +304,9 @@ static void _enet_io_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_EMC_41_ENET_MDIO,           /* GPIO_EMC_41 PAD functional properties : */
-      0xB829u);                               /* Slew Rate Field: Fast Slew Rate
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_EMC_41_ENET_MDIO,           /* GPIO_EMC_41 PAD functional properties : */
+        0xB829u);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: low(50MHz)
                                                  Open Drain Enable Field: Open Drain Enabled
@@ -314,8 +314,6 @@ static void _enet_io_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-
-
 }
 
 static void _enet_clk_init(void)
@@ -353,7 +351,8 @@ static void _enet_config(void)
     uint32_t sysClock;
 
     /* prepare the buffer configuration. */
-    enet_buffer_config_t buffConfig = {
+    enet_buffer_config_t buffConfig =
+    {
         ENET_RXBD_NUM,
         ENET_TXBD_NUM,
         SDK_SIZEALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT),
@@ -390,6 +389,43 @@ static void _enet_config(void)
     ENET_ActiveRead(imxrt_eth_device.enet_base);
 }
 
+#if defined(ETH_RX_DUMP) ||  defined(ETH_TX_DUMP)
+static void packet_dump(const char *msg, const struct pbuf *p)
+{
+    const struct pbuf *q;
+    rt_uint32_t i, j;
+    rt_uint8_t *ptr;
+
+    rt_kprintf("%s %d byte\n", msg, p->tot_len);
+
+    i = 0;
+    for (q = p; q != RT_NULL; q = q->next)
+    {
+        ptr = q->payload;
+
+        for (j = 0; j < q->len; j++)
+        {
+            if ((i % 8) == 0)
+            {
+                rt_kprintf("  ");
+            }
+            if ((i % 16) == 0)
+            {
+                rt_kprintf("\r\n");
+            }
+            rt_kprintf("%02x ", *ptr);
+
+            i++;
+            ptr++;
+        }
+    }
+
+    rt_kprintf("\n\n");
+}
+#else
+#define packet_dump(...)
+#endif /* dump */
+
 /* initialize the interface */
 static rt_err_t rt_imxrt_eth_init(rt_device_t dev)
 {
@@ -402,127 +438,112 @@ static rt_err_t rt_imxrt_eth_init(rt_device_t dev)
 static rt_err_t rt_imxrt_eth_open(rt_device_t dev, rt_uint16_t oflag)
 {
     dbg_log(DBG_LOG, "rt_imxrt_eth_open...\n");
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_imxrt_eth_close(rt_device_t dev)
 {
     dbg_log(DBG_LOG, "rt_imxrt_eth_close...\n");
-	return RT_EOK;
+    return RT_EOK;
 }
 
-static rt_size_t rt_imxrt_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+static rt_size_t rt_imxrt_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
 {
     dbg_log(DBG_LOG, "rt_imxrt_eth_read...\n");
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
-static rt_size_t rt_imxrt_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+static rt_size_t rt_imxrt_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
 {
     dbg_log(DBG_LOG, "rt_imxrt_eth_write...\n");
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args)
 {
     dbg_log(DBG_LOG, "rt_imxrt_eth_control...\n");
-	switch(cmd)
-	{
-	case NIOCTL_GADDR:
-		/* get mac address */
-		if(args) rt_memcpy(args, imxrt_eth_device.dev_addr, 6);
-		else return -RT_ERROR;
-		break;
-
-	default :
-		break;
-	}
-
-	return RT_EOK;
+    switch (cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get mac address */
+        if (args) rt_memcpy(args, imxrt_eth_device.dev_addr, 6);
+        else return -RT_ERROR;
+        break;
+
+    default :
+        break;
+    }
+
+    return RT_EOK;
 }
 
 /* ethernet device interface */
 /* transmit packet. */
-rt_err_t rt_imxrt_eth_tx( rt_device_t dev, struct pbuf* p)
+rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p)
 {
 	rt_err_t result = RT_EOK;
 	enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle;
 
-	RT_ASSERT(p != NULL);
+    RT_ASSERT(p != NULL);
     RT_ASSERT(enet_handle != RT_NULL);
 
-	dbg_log(DBG_LOG, "rt_imxrt_eth_tx: %d\n", p->len);
+    dbg_log(DBG_LOG, "rt_imxrt_eth_tx: %d\n", p->len);
 
 #ifdef ETH_TX_DUMP
-	{
-		int i;
-		uint8_t * buf;
-		buf = (uint8_t *)p->payload;
-		for (i = 0; i < p->len; i++)
-		{
-			dbg_log(DBG_LOG, "%02X ", buf[i]);
-			if (i % 16 == 15)
-				dbg_log(DBG_LOG, "\n");
-		}
-		dbg_log(DBG_LOG, "\n");
-	}
+    packet_dump("send", p);
 #endif
 
-	do
-	{
-		result = ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, p->payload, p->len);
+    do
+    {
+        result = ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, (const uint8_t *)p, p->tot_len);
+
+        if (result == kStatus_ENET_TxFrameBusy)
+        {
+            imxrt_eth_device.tx_is_waiting = RT_TRUE;
+            rt_sem_take(&imxrt_eth_device.tx_wait, RT_WAITING_FOREVER);
+        }
 
-		if (result == kStatus_ENET_TxFrameBusy)
-		{
-			rt_sem_take(&imxrt_eth_device.tx_wait, RT_WAITING_FOREVER);
-		}
+    }
+    while (result == kStatus_ENET_TxFrameBusy);
 
-	} while (result == kStatus_ENET_TxFrameBusy);
+    return RT_EOK;
+}
 
-	return RT_EOK;
+void pbuf2mem(const uint8_t *data, void *dataptr, uint32_t len)
+{
+    pbuf_copy_partial((const struct pbuf *)data, dataptr, len, 0);
 }
 
 /* reception packet. */
 struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
 {
- 	uint32_t length = 0;
-	status_t status;
+    uint32_t length = 0;
+    status_t status;
 
-	struct pbuf* p = RT_NULL;
-	enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle;
+    struct pbuf *p = RT_NULL;
+    enet_handle_t *enet_handle = &imxrt_eth_device.enet_handle;
     ENET_Type *enet_base = imxrt_eth_device.enet_base;
     enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic;
 
-	/* Get the Frame size */
-	status = ENET_GetRxFrameSize(enet_handle, &length);
+    /* Get the Frame size */
+    status = ENET_GetRxFrameSize(enet_handle, &length);
 
-	/* Call ENET_ReadFrame when there is a received frame. */
-	if (length != 0)
-	{
-		/* Received valid frame. Deliver the rx buffer with the size equal to length. */
-		p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
+    /* Call ENET_ReadFrame when there is a received frame. */
+    if (length != 0)
+    {
+        /* Received valid frame. Deliver the rx buffer with the size equal to length. */
+        p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
 
         if (p != NULL)
         {
             status = ENET_ReadFrame(enet_base, enet_handle, p->payload, length);
             if (status == kStatus_Success)
             {
-    #ifdef ETH_RX_DUMP
-                uint8_t *buf;
-                int i;
-
-                ETH_PRINTF("A frame received. the length:%d\n", p->len);
-                buf = (uint8_t *)p->payload;
-                for (i = 0; i < p->len; i++)
-                {
-                    dbg_log(DBG_LOG, "%02X ", buf[i]);
-                    if (i % 16 == 15)
-                        dbg_log(DBG_LOG, "\n");
-                }
-                dbg_log(DBG_LOG, "\n");
-    #endif
+#ifdef ETH_RX_DUMP
+                packet_dump("recv", p);
+#endif
                 return p;
             }
             else
@@ -535,16 +556,16 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
         {
             dbg_log(DBG_LOG, " pbuf_alloc faild\n");
         }
-	}
-	else if (status == kStatus_ENET_RxFrameError)
-	{
-		dbg_log(DBG_WARNING, "ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n");
-		/* Update the received buffer when error happened. */
-		/* Get the error information of the received g_frame. */
-		ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic);
-		/* update the receive buffer. */
-		ENET_ReadFrame(enet_base, enet_handle, NULL, 0);
-	}
+    }
+    else if (status == kStatus_ENET_RxFrameError)
+    {
+        dbg_log(DBG_WARNING, "ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n");
+        /* Update the received buffer when error happened. */
+        /* Get the error information of the received g_frame. */
+        ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic);
+        /* update the receive buffer. */
+        ENET_ReadFrame(enet_base, enet_handle, NULL, 0);
+    }
 
     ENET_EnableInterrupts(enet_base, kENET_RxFrameInterrupt);
     return NULL;
@@ -552,29 +573,28 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
 
 static void phy_monitor_thread_entry(void *parameter)
 {
-    
     phy_speed_t speed;
     phy_duplex_t duplex;
     bool link = false;
-    
+
     _enet_phy_reset_by_gpio();
 
     PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, CLOCK_GetFreq(kCLOCK_AhbClk));
-    
+
     while (1)
     {
         bool new_link = false;
         status_t status = PHY_GetLinkStatus(imxrt_eth_device.enet_base, PHY_ADDRESS, &new_link);
-        
+
         if ((status == kStatus_Success) && (link != new_link))
         {
             link = new_link;
-            
+
             if (link)   // link up
             {
-                PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base, 
+                PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base,
                                        PHY_ADDRESS, &speed, &duplex);
-                
+
                 if (kPHY_Speed10M == speed)
                 {
                     dbg_log(DBG_LOG, "10M\n");
@@ -583,7 +603,7 @@ static void phy_monitor_thread_entry(void *parameter)
                 {
                     dbg_log(DBG_LOG, "100M\n");
                 }
-                
+
                 if (kPHY_HalfDuplex == duplex)
                 {
                     dbg_log(DBG_LOG, "half dumplex\n");
@@ -592,13 +612,13 @@ static void phy_monitor_thread_entry(void *parameter)
                 {
                     dbg_log(DBG_LOG, "full dumplex\n");
                 }
-                
-                if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed) 
-                    || (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex))
+
+                if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed)
+                        || (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex))
                 {
-                    imxrt_eth_device.speed = (enet_mii_speed_t)speed; 
+                    imxrt_eth_device.speed = (enet_mii_speed_t)speed;
                     imxrt_eth_device.duplex = (enet_mii_duplex_t)duplex;
-                    
+
                     dbg_log(DBG_LOG, "link up, and update eth mode.\n");
                     rt_imxrt_eth_init((rt_device_t)&imxrt_eth_device);
                 }
@@ -615,7 +635,7 @@ static void phy_monitor_thread_entry(void *parameter)
                 eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE);
             }
         }
-        
+
         rt_thread_delay(RT_TICK_PER_SECOND * 2);
     }
 }
@@ -626,17 +646,17 @@ static int rt_hw_imxrt_eth_init(void)
 
     _enet_io_init();
     _enet_clk_init();
-    
+
     /* OUI 00-80-E1 STMICROELECTRONICS. */
     imxrt_eth_device.dev_addr[0] = 0x00;
-    imxrt_eth_device.dev_addr[1] = 0x80;
-    imxrt_eth_device.dev_addr[2] = 0xE1;
+    imxrt_eth_device.dev_addr[1] = 0x04;
+    imxrt_eth_device.dev_addr[2] = 0x9F;
     /* generate MAC addr from 96bit unique ID (only for test). */
-    imxrt_eth_device.dev_addr[3] = 0x12;
-    imxrt_eth_device.dev_addr[4] = 0x34;
-    imxrt_eth_device.dev_addr[5] = 0x56;
-    
-    imxrt_eth_device.speed = kENET_MiiSpeed100M; 
+    imxrt_eth_device.dev_addr[3] = 0x05;
+    imxrt_eth_device.dev_addr[4] = 0x44;
+    imxrt_eth_device.dev_addr[5] = 0xE5;
+
+    imxrt_eth_device.speed = kENET_MiiSpeed100M;
     imxrt_eth_device.duplex = kENET_MiiFullDuplex;
 
     imxrt_eth_device.enet_base = ENET;
@@ -667,9 +687,9 @@ static int rt_hw_imxrt_eth_init(void)
     {
         dbg_log(DBG_LOG, "eth_device_init faild: %d\r\n", state);
     }
-    
+
     eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE);
-    
+
     /* start phy monitor */
     {
         rt_thread_t tid;
@@ -682,7 +702,7 @@ static int rt_hw_imxrt_eth_init(void)
         if (tid != RT_NULL)
             rt_thread_startup(tid);
     }
-    
+
     return state;
 }
 INIT_DEVICE_EXPORT(rt_hw_imxrt_eth_init);
@@ -756,102 +776,102 @@ void enet_reg_dump(void)
 #define DUMP_REG(__REG)  \
     rt_kprintf("%s(%08X): %08X\n", #__REG, (uint32_t)&enet_base->__REG, enet_base->__REG)
 
-	DUMP_REG(EIR);
-	DUMP_REG(EIMR);
-	DUMP_REG(RDAR);
-	DUMP_REG(TDAR);
-	DUMP_REG(ECR);
-	DUMP_REG(MMFR);
-	DUMP_REG(MSCR);
-	DUMP_REG(MIBC);
-	DUMP_REG(RCR);
-	DUMP_REG(TCR);
-	DUMP_REG(PALR);
-	DUMP_REG(PAUR);
-	DUMP_REG(OPD);
-	DUMP_REG(TXIC);
-	DUMP_REG(RXIC);
-	DUMP_REG(IAUR);
-	DUMP_REG(IALR);
-	DUMP_REG(GAUR);
-	DUMP_REG(GALR);
-	DUMP_REG(TFWR);
-	DUMP_REG(RDSR);
-	DUMP_REG(TDSR);
-	DUMP_REG(MRBR);
-	DUMP_REG(RSFL);
-	DUMP_REG(RSEM);
-	DUMP_REG(RAEM);
-	DUMP_REG(RAFL);
-	DUMP_REG(TSEM);
-	DUMP_REG(TAEM);
-	DUMP_REG(TAFL);
-	DUMP_REG(TIPG);
-	DUMP_REG(FTRL);
-	DUMP_REG(TACC);
-	DUMP_REG(RACC);
-	DUMP_REG(RMON_T_DROP);
-	DUMP_REG(RMON_T_PACKETS);
-	DUMP_REG(RMON_T_BC_PKT);
-	DUMP_REG(RMON_T_MC_PKT);
-	DUMP_REG(RMON_T_CRC_ALIGN);
-	DUMP_REG(RMON_T_UNDERSIZE);
-	DUMP_REG(RMON_T_OVERSIZE);
-	DUMP_REG(RMON_T_FRAG);
-	DUMP_REG(RMON_T_JAB);
-	DUMP_REG(RMON_T_COL);
-	DUMP_REG(RMON_T_P64);
-	DUMP_REG(RMON_T_P65TO127);
-	DUMP_REG(RMON_T_P128TO255);
-	DUMP_REG(RMON_T_P256TO511);
-	DUMP_REG(RMON_T_P512TO1023);
-	DUMP_REG(RMON_T_P1024TO2047);
-	DUMP_REG(RMON_T_P_GTE2048);
-	DUMP_REG(RMON_T_OCTETS);
-	DUMP_REG(IEEE_T_DROP);
-	DUMP_REG(IEEE_T_FRAME_OK);
-	DUMP_REG(IEEE_T_1COL);
-	DUMP_REG(IEEE_T_MCOL);
-	DUMP_REG(IEEE_T_DEF);
-	DUMP_REG(IEEE_T_LCOL);
-	DUMP_REG(IEEE_T_EXCOL);
-	DUMP_REG(IEEE_T_MACERR);
-	DUMP_REG(IEEE_T_CSERR);
-	DUMP_REG(IEEE_T_SQE);
-	DUMP_REG(IEEE_T_FDXFC);
-	DUMP_REG(IEEE_T_OCTETS_OK);
-	DUMP_REG(RMON_R_PACKETS);
-	DUMP_REG(RMON_R_BC_PKT);
-	DUMP_REG(RMON_R_MC_PKT);
-	DUMP_REG(RMON_R_CRC_ALIGN);
-	DUMP_REG(RMON_R_UNDERSIZE);
-	DUMP_REG(RMON_R_OVERSIZE);
-	DUMP_REG(RMON_R_FRAG);
-	DUMP_REG(RMON_R_JAB);
-	DUMP_REG(RMON_R_RESVD_0);
-	DUMP_REG(RMON_R_P64);
-	DUMP_REG(RMON_R_P65TO127);
-	DUMP_REG(RMON_R_P128TO255);
-	DUMP_REG(RMON_R_P256TO511);
-	DUMP_REG(RMON_R_P512TO1023);
-	DUMP_REG(RMON_R_P1024TO2047);
-	DUMP_REG(RMON_R_P_GTE2048);
-	DUMP_REG(RMON_R_OCTETS);
-	DUMP_REG(IEEE_R_DROP);
-	DUMP_REG(IEEE_R_FRAME_OK);
-	DUMP_REG(IEEE_R_CRC);
-	DUMP_REG(IEEE_R_ALIGN);
-	DUMP_REG(IEEE_R_MACERR);
-	DUMP_REG(IEEE_R_FDXFC);
-	DUMP_REG(IEEE_R_OCTETS_OK);
-	DUMP_REG(ATCR);
-	DUMP_REG(ATVR);
-	DUMP_REG(ATOFF);
-	DUMP_REG(ATPER);
-	DUMP_REG(ATCOR);
-	DUMP_REG(ATINC);
-	DUMP_REG(ATSTMP);
-	DUMP_REG(TGSR);
+    DUMP_REG(EIR);
+    DUMP_REG(EIMR);
+    DUMP_REG(RDAR);
+    DUMP_REG(TDAR);
+    DUMP_REG(ECR);
+    DUMP_REG(MMFR);
+    DUMP_REG(MSCR);
+    DUMP_REG(MIBC);
+    DUMP_REG(RCR);
+    DUMP_REG(TCR);
+    DUMP_REG(PALR);
+    DUMP_REG(PAUR);
+    DUMP_REG(OPD);
+    DUMP_REG(TXIC);
+    DUMP_REG(RXIC);
+    DUMP_REG(IAUR);
+    DUMP_REG(IALR);
+    DUMP_REG(GAUR);
+    DUMP_REG(GALR);
+    DUMP_REG(TFWR);
+    DUMP_REG(RDSR);
+    DUMP_REG(TDSR);
+    DUMP_REG(MRBR);
+    DUMP_REG(RSFL);
+    DUMP_REG(RSEM);
+    DUMP_REG(RAEM);
+    DUMP_REG(RAFL);
+    DUMP_REG(TSEM);
+    DUMP_REG(TAEM);
+    DUMP_REG(TAFL);
+    DUMP_REG(TIPG);
+    DUMP_REG(FTRL);
+    DUMP_REG(TACC);
+    DUMP_REG(RACC);
+    DUMP_REG(RMON_T_DROP);
+    DUMP_REG(RMON_T_PACKETS);
+    DUMP_REG(RMON_T_BC_PKT);
+    DUMP_REG(RMON_T_MC_PKT);
+    DUMP_REG(RMON_T_CRC_ALIGN);
+    DUMP_REG(RMON_T_UNDERSIZE);
+    DUMP_REG(RMON_T_OVERSIZE);
+    DUMP_REG(RMON_T_FRAG);
+    DUMP_REG(RMON_T_JAB);
+    DUMP_REG(RMON_T_COL);
+    DUMP_REG(RMON_T_P64);
+    DUMP_REG(RMON_T_P65TO127);
+    DUMP_REG(RMON_T_P128TO255);
+    DUMP_REG(RMON_T_P256TO511);
+    DUMP_REG(RMON_T_P512TO1023);
+    DUMP_REG(RMON_T_P1024TO2047);
+    DUMP_REG(RMON_T_P_GTE2048);
+    DUMP_REG(RMON_T_OCTETS);
+    DUMP_REG(IEEE_T_DROP);
+    DUMP_REG(IEEE_T_FRAME_OK);
+    DUMP_REG(IEEE_T_1COL);
+    DUMP_REG(IEEE_T_MCOL);
+    DUMP_REG(IEEE_T_DEF);
+    DUMP_REG(IEEE_T_LCOL);
+    DUMP_REG(IEEE_T_EXCOL);
+    DUMP_REG(IEEE_T_MACERR);
+    DUMP_REG(IEEE_T_CSERR);
+    DUMP_REG(IEEE_T_SQE);
+    DUMP_REG(IEEE_T_FDXFC);
+    DUMP_REG(IEEE_T_OCTETS_OK);
+    DUMP_REG(RMON_R_PACKETS);
+    DUMP_REG(RMON_R_BC_PKT);
+    DUMP_REG(RMON_R_MC_PKT);
+    DUMP_REG(RMON_R_CRC_ALIGN);
+    DUMP_REG(RMON_R_UNDERSIZE);
+    DUMP_REG(RMON_R_OVERSIZE);
+    DUMP_REG(RMON_R_FRAG);
+    DUMP_REG(RMON_R_JAB);
+    DUMP_REG(RMON_R_RESVD_0);
+    DUMP_REG(RMON_R_P64);
+    DUMP_REG(RMON_R_P65TO127);
+    DUMP_REG(RMON_R_P128TO255);
+    DUMP_REG(RMON_R_P256TO511);
+    DUMP_REG(RMON_R_P512TO1023);
+    DUMP_REG(RMON_R_P1024TO2047);
+    DUMP_REG(RMON_R_P_GTE2048);
+    DUMP_REG(RMON_R_OCTETS);
+    DUMP_REG(IEEE_R_DROP);
+    DUMP_REG(IEEE_R_FRAME_OK);
+    DUMP_REG(IEEE_R_CRC);
+    DUMP_REG(IEEE_R_ALIGN);
+    DUMP_REG(IEEE_R_MACERR);
+    DUMP_REG(IEEE_R_FDXFC);
+    DUMP_REG(IEEE_R_OCTETS_OK);
+    DUMP_REG(ATCR);
+    DUMP_REG(ATVR);
+    DUMP_REG(ATOFF);
+    DUMP_REG(ATPER);
+    DUMP_REG(ATCOR);
+    DUMP_REG(ATINC);
+    DUMP_REG(ATSTMP);
+    DUMP_REG(TGSR);
 }
 
 void enet_nvic_tog(void)
@@ -891,24 +911,23 @@ void enet_rx_stat(void)
 
 void enet_buf_info(void)
 {
-
     int i = 0;
     for (i = 0; i < ENET_RXBD_NUM; i++)
     {
         rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n",
-                    i,
-                    g_rxBuffDescrip[i].length,
-                    g_rxBuffDescrip[i].control,
-                    g_rxBuffDescrip[i].buffer);
+                   i,
+                   g_rxBuffDescrip[i].length,
+                   g_rxBuffDescrip[i].control,
+                   g_rxBuffDescrip[i].buffer);
     }
 
     for (i = 0; i < ENET_TXBD_NUM; i++)
     {
         rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n",
-                    i,
-                    g_txBuffDescrip[i].length,
-                    g_txBuffDescrip[i].control,
-                    g_txBuffDescrip[i].buffer);
+                   i,
+                   g_txBuffDescrip[i].length,
+                   g_txBuffDescrip[i].control,
+                   g_txBuffDescrip[i].buffer);
     }
 }
 

bsp/imxrt1052-evk/drivers/drv_ft5406.c

@@ -40,7 +40,7 @@
 
 #define BSP_TOUCH_SAMPLE_HZ     30
 
-#define I2CBUS_NAME  "i2c0"
+#define I2CBUS_NAME  "i2c1"
 
 #if 0
 #define FTDEBUG      rt_kprintf

bsp/imxrt1052-evk/drivers/drv_hwtimer.c

@@ -0,0 +1,189 @@
+/*
+* File      : drv_hwtimer.c
+* This file is part of RT-Thread RTOS
+* COPYRIGHT (C) 2017, RT-Thread Development Team
+*
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+*
+*  You should have received a copy of the GNU General Public License along
+*  with this program; if not, write to the Free Software Foundation, Inc.,
+*  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*
+* Change Logs:
+* Date           Author       Notes
+* 2018-04-17     WangBing     the first version.
+*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "drv_hwtimer.h"
+
+#include "fsl_common.h"
+#include "fsl_gpt.h"
+
+#ifdef RT_USING_HWTIMER
+
+#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
+#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
+#endif
+
+/* Select IPG Clock as PERCLK_CLK clock source */
+#define EXAMPLE_GPT_CLOCK_SOURCE_SELECT (0U)
+/* Clock divider for PERCLK_CLK clock source */
+#define EXAMPLE_GPT_CLOCK_DIVIDER_SELECT (5U)
+/* Get source clock for GPT driver (GPT prescaler = 6) */
+#define EXAMPLE_GPT_CLK_FREQ (CLOCK_GetFreq(kCLOCK_IpgClk) / (EXAMPLE_GPT_CLOCK_DIVIDER_SELECT + 1U))
+
+static void NVIC_Configuration(void)
+{
+    EnableIRQ(GPT1_IRQn);
+}
+
+static rt_err_t rt1052_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args)
+{
+    rt_err_t err = RT_EOK;
+    GPT_Type *hwtimer_dev;
+    hwtimer_dev = (GPT_Type *)timer->parent.user_data;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    switch (cmd)
+    {
+    case HWTIMER_CTRL_FREQ_SET:
+    {
+        uint32_t clk;
+        uint32_t pre;
+        clk = EXAMPLE_GPT_CLK_FREQ;
+        pre = clk / *((uint32_t *)args) - 1;
+        GPT_SetClockDivider(hwtimer_dev, pre);
+    }
+    break;
+    default:
+        err = -RT_ENOSYS;
+        break;
+    }
+    return err;
+}
+
+static rt_uint32_t rt1052_hwtimer_count_get(rt_hwtimer_t *timer)
+{
+    rt_uint32_t CurrentTimer_Count;
+    GPT_Type *hwtimer_dev;
+    hwtimer_dev = (GPT_Type *)timer->parent.user_data;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    CurrentTimer_Count = GPT_GetCurrentTimerCount(hwtimer_dev);
+
+    return CurrentTimer_Count;
+}
+
+static void rt1052_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
+{
+    GPT_Type *hwtimer_dev;
+    gpt_config_t gptConfig;
+    hwtimer_dev = (GPT_Type *)timer->parent.user_data;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    GPT_Deinit(hwtimer_dev);
+
+    if (state == 1)
+    {
+        /*Clock setting for GPT*/
+        CLOCK_SetMux(kCLOCK_PerclkMux, EXAMPLE_GPT_CLOCK_SOURCE_SELECT);
+        CLOCK_SetDiv(kCLOCK_PerclkDiv, EXAMPLE_GPT_CLOCK_DIVIDER_SELECT);
+
+        /* Initialize GPT module by default config */
+        GPT_GetDefaultConfig(&gptConfig);
+        GPT_Init(hwtimer_dev, &gptConfig);
+    }
+}
+
+static rt_err_t rt1052_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode)
+{
+    GPT_Type *hwtimer_dev;
+    hwtimer_dev = (GPT_Type *)timer->parent.user_data;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    hwtimer_dev->CR |= (mode == HWTIMER_MODE_PERIOD) ? GPT_CR_FRR_MASK : 0U;
+
+    GPT_SetOutputCompareValue(hwtimer_dev, kGPT_OutputCompare_Channel1, cnt);
+
+    GPT_EnableInterrupts(hwtimer_dev, kGPT_OutputCompare1InterruptEnable);
+
+    NVIC_Configuration();
+
+    GPT_StartTimer(hwtimer_dev);
+
+    return RT_EOK;
+}
+
+static void rt1052_hwtimer_stop(rt_hwtimer_t *timer)
+{
+    GPT_Type *hwtimer_dev;
+    hwtimer_dev = (GPT_Type *)timer->parent.user_data;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    GPT_StopTimer(hwtimer_dev);
+}
+
+static const struct rt_hwtimer_ops rt1052_hwtimer_ops =
+{
+    rt1052_hwtimer_init,
+    rt1052_hwtimer_start,
+    rt1052_hwtimer_stop,
+    rt1052_hwtimer_count_get,
+    rt1052_hwtimer_control,
+};
+
+static const struct rt_hwtimer_info rt1052_hwtimer_info =
+{
+    25000000,           /* the maximum count frequency can be set */
+    6103,               /* the minimum count frequency can be set */
+    0xFFFFFFFF,
+    HWTIMER_CNTMODE_UP,
+};
+
+static rt_hwtimer_t GPT_timer1;
+
+int rt1052_hw_hwtimer_init(void)
+{
+    int ret = RT_EOK;
+
+    GPT_timer1.info = &rt1052_hwtimer_info;
+    GPT_timer1.ops  = &rt1052_hwtimer_ops;
+
+    rt_device_hwtimer_register(&GPT_timer1, "_timer", GPT1);
+
+    return ret;
+}
+
+void GPT1_IRQHandler(void)
+{
+    if (GPT_GetStatusFlags(GPT1, kGPT_OutputCompare1Flag) != 0)
+    {
+        GPT_ClearStatusFlags(GPT1, kGPT_OutputCompare1Flag);
+        rt_device_hwtimer_isr(&GPT_timer1);
+    }
+
+    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M7F Store immediate overlapping
+      exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U || __CORTEX_M == 7U)
+    __DSB();
+#endif
+}
+
+INIT_DEVICE_EXPORT(rt1052_hw_hwtimer_init);
+
+#endif /*RT_USING_HWTIMER*/

bsp/imxrt1052-evk/drivers/drv_hwtimer.h

@@ -0,0 +1,34 @@
+/*
+* File      : drv_hwtimer.h
+* This file is part of RT-Thread RTOS
+* COPYRIGHT (C) 2017, RT-Thread Development Team
+*
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+*
+*  You should have received a copy of the GNU General Public License along
+*  with this program; if not, write to the Free Software Foundation, Inc.,
+*  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*
+* Change Logs:
+* Date           Author       Notes
+* 2018-04-17     WangBing     the first version.
+*/
+ 
+#ifndef __DRV_HWTIMER_H__
+#define __DRV_HWTIMER_H__
+
+#include <rtthread.h> 
+#include <rtdevice.h> 
+
+int rt1052_hw_hwtimer_init(void);
+
+#endif
+

bsp/imxrt1052-evk/drivers/drv_i2c.c

@@ -19,171 +19,379 @@
  * Change Logs:
  * Date           Author       Notes
  * 2017-08-08     Yang        the first version
+ * 2018-03-24     LaiYiKeTang add hardware iic
  */
- 
+
 #include <rtthread.h>
 #include <rtdevice.h>
 #include "board.h"
 #include "fsl_gpio.h"
 #include "fsl_lpi2c.h"
+#include "drv_i2c.h"
 
 //#define DRV_I2C_DEBUG
 
 #ifdef RT_USING_I2C
 
-#ifdef RT_USING_I2C_BITOPS
+#define I2C1BUS_NAME  "i2c1"
+#define I2C2BUS_NAME  "i2c2"
+#define I2C3BUS_NAME  "i2c3"
+#define I2C4BUS_NAME  "i2c4"
+
+#define LPI2C_CLOCK_SOURCE_DIVIDER 4
 
-#define I2CBUS_NAME             "i2c0"
+/* Get frequency of lpi2c clock */
+#define LPI2C_CLOCK_FREQUENCY ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER))
 
-struct stm32_i2c_bit_data
+#ifdef RT_USING_HW_I2C1
+static struct rt1052_i2c_bus lpi2c1 =
 {
-    struct
-    {
-        GPIO_Type *base;
-        uint32_t pin;
-    } scl, sda;
+    .I2C = LPI2C1,
+    .device_name = I2C1BUS_NAME,
+};
+#endif /* RT_USING_HW_I2C1 */
+
+#ifdef RT_USING_HW_I2C2
+static struct rt1052_i2c_bus lpi2c2 =
+{
+    .I2C = LPI2C2,
+    .device_name = I2C2BUS_NAME,
 };
+#endif /* RT_USING_HW_I2C2 */
 
-static void gpio_udelay(rt_uint32_t us)
+#ifdef RT_USING_HW_I2C3
+static struct rt1052_i2c_bus lpi2c3 =
 {
-    volatile rt_int32_t i;
-    for (; us > 0; us--)
+    .I2C = LPI2C3,
+    .device_name = I2C3BUS_NAME,
+};
+#endif /* RT_USING_HW_I2C3 */
+
+#ifdef RT_USING_HW_I2C4
+static struct rt1052_i2c_bus lpi2c4 =
+{
+    .I2C = LPI2C4,
+    .device_name = I2C4BUS_NAME,
+};
+#endif /* RT_USING_HW_I2C4 */
+
+#if (defined(RT_USING_HW_I2C1) || defined(RT_USING_HW_I2C2) || defined(RT_USING_HW_I2C3) || defined(RT_USING_HW_I2C4))
+
+static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num);
+static rt_size_t imxrt_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num);
+static rt_err_t imxrt_i2c_bus_control(struct rt_i2c_bus_device *bus,
+                                      rt_uint32_t,
+                                      rt_uint32_t);
+
+static const struct rt_i2c_bus_device_ops imxrt_i2c_ops =
+{
+    imxrt_i2c_mst_xfer,
+    imxrt_i2c_slv_xfer,
+    imxrt_i2c_bus_control,
+};
+
+void imxrt_lpi2c_gpio_init(struct rt1052_i2c_bus *bus)
+{
+    if (bus->I2C == LPI2C1)
+    {
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL,
+            1U);
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA,
+            1U);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL,
+            0xD8B0u);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA,
+            0xD8B0u);
+    }
+    else if (bus->I2C == LPI2C2)
+    {
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_B0_04_LPI2C2_SCL,
+            1U);
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_B0_05_LPI2C2_SDA,
+            1U);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_B0_04_LPI2C2_SCL,
+            0xD8B0u);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_B0_05_LPI2C2_SDA,
+            0xD8B0u);
+    }
+    else if (bus->I2C == LPI2C3)
     {
-        i = 1000;
-        while (i--);
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL,
+            1U);
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA,
+            1U);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL,
+            0xD8B0u);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA,
+            0xD8B0u);
     }
+    else if (bus->I2C == LPI2C4)
+    {
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_EMC_12_LPI2C4_SCL,
+            1U);
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_EMC_11_LPI2C4_SDA,
+            1U);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_EMC_12_LPI2C4_SCL,
+            0xD8B0u);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_EMC_11_LPI2C4_SDA,
+            0xD8B0u);
+    }
+    else
+    {
+        RT_ASSERT(RT_NULL);
+    }
+}
+
+static rt_err_t imxrt_lpi2c_configure(struct rt1052_i2c_bus *bus, lpi2c_master_config_t *cfg)
+{
+    RT_ASSERT(bus != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    imxrt_lpi2c_gpio_init(bus);
+    bus->parent.ops = &imxrt_i2c_ops;
+    LPI2C_MasterInit(bus->I2C, cfg, LPI2C_CLOCK_FREQUENCY);
+    return RT_EOK;
 }
 
-static void gpio_set_input(GPIO_Type* base, uint32_t pin)
+status_t LPI2C_MasterCheck(LPI2C_Type *base, uint32_t status)
 {
-    if (base->GDIR & (1 << pin))        //output mode
+    status_t result = kStatus_Success;
+
+    /* Check for error. These errors cause a stop to automatically be sent. We must */
+    /* clear the errors before a new transfer can start. */
+    status &= 0x3c00;
+    if (status)
     {
-        base->GDIR &= ~(1 << pin);
-        gpio_udelay(5);
+        /* Select the correct error code. Ordered by severity, with bus issues first. */
+        if (status & kLPI2C_MasterPinLowTimeoutFlag)
+        {
+            result = kStatus_LPI2C_PinLowTimeout;
+        }
+        else if (status & kLPI2C_MasterArbitrationLostFlag)
+        {
+            result = kStatus_LPI2C_ArbitrationLost;
+        }
+        else if (status & kLPI2C_MasterNackDetectFlag)
+        {
+            result = kStatus_LPI2C_Nak;
+        }
+        else if (status & kLPI2C_MasterFifoErrFlag)
+        {
+            result = kStatus_LPI2C_FifoError;
+        }
+        else
+        {
+            assert(false);
+        }
+
+        /* Clear the flags. */
+        LPI2C_MasterClearStatusFlags(base, status);
+
+        /* Reset fifos. These flags clear automatically. */
+        base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
     }
+
+    return result;
 }
 
-static void gpio_set_output(GPIO_Type* base, uint32_t pin)
+/*!
+ * @brief Wait until the tx fifo all empty.
+ * @param base The LPI2C peripheral base address.
+ * @retval #kStatus_Success
+ * @retval #kStatus_LPI2C_PinLowTimeout
+ * @retval #kStatus_LPI2C_ArbitrationLost
+ * @retval #kStatus_LPI2C_Nak
+ * @retval #kStatus_LPI2C_FifoError
+ */
+static status_t LPI2C_MasterWaitForTxFifoAllEmpty(LPI2C_Type *base)
 {
-    if (!(base->GDIR & (1 << pin)))        //input mode
-    {    
-        base->GDIR |= (1 << pin);
-        gpio_udelay(5);
+    uint32_t status;
+    size_t txCount;
+    do
+    {
+        status_t result;
+
+        /* Get the number of words in the tx fifo and compute empty slots. */
+        LPI2C_MasterGetFifoCounts(base, NULL, &txCount);
+
+        /* Check for error flags. */
+        status = LPI2C_MasterGetStatusFlags(base);
+        result = LPI2C_MasterCheck(base, status);
+        if (result)
+        {
+            return result;
+        }
     }
+    while (txCount);
+    return kStatus_Success;
 }
 
-static void gpio_set_sda(void *data, rt_int32_t state)
+static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num)
 {
-    struct stm32_i2c_bit_data *bd = data;
-    
-    gpio_set_output(bd->sda.base, bd->sda.pin);
-    
-    GPIO_PinWrite(bd->sda.base, bd->sda.pin, !!state);
+    struct rt1052_i2c_bus *rt1052_i2c;
+    rt_size_t i;
+    RT_ASSERT(bus != RT_NULL);
+    rt1052_i2c = (struct rt1052_i2c_bus *) bus;
+
+    rt1052_i2c->msg = msgs;
+    rt1052_i2c->msg_ptr = 0;
+    rt1052_i2c->msg_cnt = num;
+    rt1052_i2c->dptr = 0;
+
+    for (i = 0; i < num; i++)
+    {
+        if (rt1052_i2c->msg[i].flags & RT_I2C_RD)
+        {
+            if (LPI2C_MasterStart(rt1052_i2c->I2C, rt1052_i2c->msg[i].addr, kLPI2C_Read) != kStatus_Success)
+            {
+                i = 0;
+                break;
+            }
+            if (LPI2C_MasterWaitForTxFifoAllEmpty(rt1052_i2c->I2C) != kStatus_Success)
+            {
+                i = 0;
+                break;
+            }
+            if (LPI2C_MasterReceive(rt1052_i2c->I2C, rt1052_i2c->msg[i].buf, rt1052_i2c->msg[i].len) != kStatus_Success)
+            {
+                i = 0;
+                break;
+            }
+            if (LPI2C_MasterWaitForTxFifoAllEmpty(rt1052_i2c->I2C) != kStatus_Success)
+            {
+                i = 0;
+                break;
+            }
+        }
+        else
+        {
+            if (LPI2C_MasterStart(rt1052_i2c->I2C, rt1052_i2c->msg[i].addr, kLPI2C_Write) != kStatus_Success)
+            {
+                i = 0;
+                break;
+            }
+            if (LPI2C_MasterWaitForTxFifoAllEmpty(rt1052_i2c->I2C) != kStatus_Success)
+            {
+                i = 0;
+                break;
+            }
+            if (LPI2C_MasterSend(rt1052_i2c->I2C, rt1052_i2c->msg[i].buf, rt1052_i2c->msg[i].len) != kStatus_Success)
+            {
+                i = 0;
+                break;
+            }
+            if (LPI2C_MasterWaitForTxFifoAllEmpty(rt1052_i2c->I2C) != kStatus_Success)
+            {
+                i = 0;
+                break;
+            }
+        }
+    }
+    i2c_dbg("send stop condition\n");
+    if (LPI2C_MasterStop(rt1052_i2c->I2C) != kStatus_Success)
+    {
+        i = 0;
+    }
+
+    rt1052_i2c->msg = RT_NULL;
+    rt1052_i2c->msg_ptr = 0;
+    rt1052_i2c->msg_cnt = 0;
+    rt1052_i2c->dptr = 0;
+    return i;
 }
 
-static void gpio_set_scl(void *data, rt_int32_t state)
+static rt_size_t imxrt_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num)
 {
-    struct stm32_i2c_bit_data *bd = data;
-    
-    gpio_set_output(bd->scl.base, bd->scl.pin);
-    
-    GPIO_PinWrite(bd->scl.base, bd->scl.pin, !!state);
+    return 0;
 }
-
-static rt_int32_t gpio_get_sda(void *data)
+static rt_err_t imxrt_i2c_bus_control(struct rt_i2c_bus_device *bus,
+                                      rt_uint32_t cmd,
+                                      rt_uint32_t arg)
 {
-    struct stm32_i2c_bit_data *bd = data;
-    
-    gpio_set_input(bd->sda.base, bd->sda.pin);
-
-    return GPIO_ReadPinInput(bd->sda.base, bd->sda.pin);
+    return RT_ERROR;
 }
 
-static rt_int32_t gpio_get_scl(void *data)
+#endif
+
+int rt_hw_i2c_init(void)
 {
-    struct stm32_i2c_bit_data *bd = data;
-    
-    gpio_set_input(bd->scl.base, bd->scl.pin);
+#if (defined(RT_USING_HW_I2C1) || defined(RT_USING_HW_I2C2) || defined(RT_USING_HW_I2C3) || defined(RT_USING_HW_I2C4))
 
-    return GPIO_ReadPinInput(bd->scl.base, bd->scl.pin);
-}
+    lpi2c_master_config_t masterConfig = {0};
 
+    /*Clock setting for LPI2C*/
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, LPI2C_CLOCK_SOURCE_DIVIDER - 1);
 
-#else /* RT_USING_I2C_BITOPS */
-    // todo : add hardware i2c
-#endif /* RT_USING_I2C_BITOPS */
+#endif
 
-int rt_hw_i2c_init(void)
-{
-#ifdef RT_USING_I2C_BITOPS
-    /* register I2C1: SCL/P0_20 SDA/P0_19 */
-    {
-        static struct rt_i2c_bus_device i2c_device;
+#if   defined(RT_USING_HW_I2C1)
+    LPI2C_MasterGetDefaultConfig(&masterConfig);
+#if   defined(HW_I2C1_BADURATE_400kHZ)
+    masterConfig.baudRate_Hz = 400000U;
+#elif defined(HW_I2C1_BADURATE_100kHZ)
+    masterConfig.baudRate_Hz = 100000U;
+#endif
+    imxrt_lpi2c_configure(&lpi2c1, &masterConfig);
+    rt_i2c_bus_device_register(&lpi2c1.parent, lpi2c1.device_name);
+#endif
 
-        static const struct stm32_i2c_bit_data _i2c_bdata =
-        {
-            /* SCL */ {GPIO1, 16},
-            /* SDA */ {GPIO1, 17},
-        };
+#if   defined(RT_USING_HW_I2C2)
+    LPI2C_MasterGetDefaultConfig(&masterConfig);
+#if   defined(HW_I2C2_BADURATE_400kHZ)
+    masterConfig.baudRate_Hz = 400000U;
+#elif defined(HW_I2C2_BADURATE_100kHZ)
+    masterConfig.baudRate_Hz = 100000U;
+#endif
+    imxrt_lpi2c_configure(&lpi2c2, &masterConfig);
+    rt_i2c_bus_device_register(&lpi2c2.parent, lpi2c2.device_name);
+#endif
 
-        static const struct rt_i2c_bit_ops _i2c_bit_ops =
-        {
-            (void*)&_i2c_bdata,
-            gpio_set_sda,
-            gpio_set_scl,
-            gpio_get_sda,
-            gpio_get_scl,
-
-            gpio_udelay,
-
-            50,
-            1000
-        };
-
-        gpio_pin_config_t pin_config = {
-            kGPIO_DigitalOutput, 0,
-        };
-        
-        CLOCK_EnableClock(kCLOCK_Iomuxc);
-
-        IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_GPIO1_IO16, 1U);
-            IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_GPIO1_IO16,
-            0xD8B0u);                                /* Slew Rate Field: Slow Slew Rate
-                                                        Drive Strength Field: R0/6
-                                                        Speed Field: medium(100MHz)
-                                                        Open Drain Enable Field: Open Drain Enabled
-                                                        Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                        Pull / Keep Select Field: Keeper
-                                                        Pull Up / Down Config. Field: 22K Ohm Pull Up
-                                                        Hyst. Enable Field: Hysteresis Disabled */
-        IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_GPIO1_IO17, 1U);
-            IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_GPIO1_IO17,
-            0xD8B0u);                                /* Slew Rate Field: Slow Slew Rate
-                                                        Drive Strength Field: R0/6
-                                                        Speed Field: medium(100MHz)
-                                                        Open Drain Enable Field: Open Drain Enabled
-                                                        Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                        Pull / Keep Select Field: Keeper
-                                                        Pull Up / Down Config. Field: 22K Ohm Pull Up
-                                                        Hyst. Enable Field: Hysteresis Disabled */
-        /* Enable touch panel controller */
-        GPIO_PinInit(_i2c_bdata.sda.base, _i2c_bdata.sda.pin, &pin_config);
-        GPIO_PinInit(_i2c_bdata.scl.base, _i2c_bdata.scl.pin, &pin_config);
-        
-        GPIO_PortSet(_i2c_bdata.sda.base, _i2c_bdata.sda.pin);
-        GPIO_PortSet(_i2c_bdata.scl.base, _i2c_bdata.scl.pin);
-        
-        //RT_ASSERT(gpio_get_scl(&_i2c_bdata) != 0);
-        //RT_ASSERT(gpio_get_sda(&_i2c_bdata) != 0);
-
-        i2c_device.priv = (void *)&_i2c_bit_ops;
-        rt_i2c_bit_add_bus(&i2c_device, I2CBUS_NAME);
-    } /* register I2C */
-
-#else /* RT_USING_I2C_BITOPS */
-    // Todo : add hardware i2c
-
-#endif /* RT_USING_I2C_BITOPS */
+#if   defined(RT_USING_HW_I2C3)
+    LPI2C_MasterGetDefaultConfig(&masterConfig);
+#if   defined(HW_I2C3_BADURATE_400kHZ)
+    masterConfig.baudRate_Hz = 400000U;
+#elif defined(HW_I2C3_BADURATE_100kHZ)
+    masterConfig.baudRate_Hz = 100000U;
+#endif
+    imxrt_lpi2c_configure(&lpi2c3, &masterConfig);
+    rt_i2c_bus_device_register(&lpi2c3.parent, lpi2c3.device_name);
+#endif
+
+#if   defined(RT_USING_HW_I2C4)
+    LPI2C_MasterGetDefaultConfig(&masterConfig);
+#if   defined(HW_I2C4_BADURATE_400kHZ)
+    masterConfig.baudRate_Hz = 400000U;
+#elif defined(HW_I2C4_BADURATE_100kHZ)
+    masterConfig.baudRate_Hz = 100000U;
+#endif
+    imxrt_lpi2c_configure(&lpi2c4, &masterConfig);
+    rt_i2c_bus_device_register(&lpi2c4.parent, lpi2c4.device_name);
+#endif
 
     return 0;
 }
@@ -197,7 +405,7 @@ static rt_device_t _i2c_find(const char *name)
     rt_device_t dev;
 
     dev = rt_device_find(name);
-    if (!dev) 
+    if (!dev)
     {
         rt_kprintf("search device failed: %s\n", name);
         return RT_NULL;
@@ -210,7 +418,7 @@ static rt_device_t _i2c_find(const char *name)
     }
 
     rt_kprintf("open i2c bus: %s\n", name);
-    
+
     return dev;
 }
 
@@ -231,36 +439,37 @@ static void _search_i2c_device(rt_device_t dev, uint8_t cmd)
     for (int i = 0; i <= 0x7f; i++)
     {
         int len;
-        
+
         msgs[0].addr  = i;
         msgs[1].addr  = i;
-        len = rt_i2c_transfer(dev, msgs, 2);
+        len = rt_i2c_transfer((struct rt_i2c_bus_device *)dev, msgs, 2);
         if (len == 2)
         {
             count++;
             rt_kprintf("add:%02X transfer success, id: %02X\n", i, buf);
-        } 
+        }
     }
-    
+
     rt_kprintf("i2c device: %d\n", count);
 }
 
 static int i2c_test(const char *name, uint8_t cmd)
 {
     rt_device_t dev = _i2c_find(name);
+
     if (dev == RT_NULL)
     {
         rt_kprintf("search i2c device faild\n");
         return -1;
     }
-    
+
     _search_i2c_device(dev, cmd);
-    
     rt_device_close(dev);
-    
+
     return 0;
 }
-FINSH_FUNCTION_EXPORT(i2c_test, e.g: i2c_test("i2c0", 0xA3));
+FINSH_FUNCTION_EXPORT(i2c_test, e.g: i2c_test("i2c1", 0xA3));
+
 #endif
 
 #endif /* RT_USING_I2C */

bsp/imxrt1052-evk/drivers/drv_i2c.h

@@ -0,0 +1,34 @@
+/*
+ * File      : drv_i2c.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-03-24     LaiYiKeTang  the first version
+ */
+
+#ifndef __DRVI2C_H__
+#define __DRVI2C_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+struct rt1052_i2c_bus
+{
+    struct rt_i2c_bus_device parent;
+    LPI2C_Type *I2C;
+    struct rt_i2c_msg *msg;
+    rt_uint32_t msg_cnt;
+    volatile rt_uint32_t msg_ptr;
+    volatile rt_uint32_t dptr;
+    char *device_name;
+};
+
+#endif
+

bsp/imxrt1052-evk/drivers/drv_lcd.c

@@ -1,7 +1,7 @@
 /*
- * File      : usart.c
+ * File      : drv_lcd.c
  * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
@@ -10,510 +10,164 @@
  * Change Logs:
  * Date           Author       Notes
  * 2017-10-30     Tanek        the first version
+ * 2018-04-05     Liu2guang    export LCD config parameters.
  */
-
-#include <board.h>
-#include <rtthread.h>
+ 
+#include "drv_lcd.h" 
 
 #include "fsl_common.h"
+#include "fsl_iomuxc.h" 
 #include "fsl_elcdif.h"
-#include "fsl_gpio.h"
-
-//#define LCD_DEBUG
-
-#ifdef PKG_USING_GUIENGINE
-
-#define APP_HSW 41
-#define APP_HFP 4
-#define APP_HBP 8
-#define APP_VSW 10
-#define APP_VFP 4
-#define APP_VBP 2
-#define APP_POL_FLAGS \
-    (kELCDIF_DataEnableActiveHigh | kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DriveDataOnRisingClkEdge)
-
-#define FRAME_BUFFER_ALIGN              64
-        
-#define LCD_PIXEL_T                     uint16_t
-#define LCD_BITS_PER_PIXEL              (sizeof(LCD_PIXEL_T) * 8)
-
-#define LCD_INIT_DATA                   (0x00)
-
-        
-/* Display. */
-#define LCD_DISP_GPIO                   GPIO1
-#define LCD_DISP_GPIO_PIN               2
-/* Back light. */
-#define LCD_BL_GPIO                     GPIO2
-#define LCD_BL_GPIO_PIN                 31
-        
-#define APP_ELCDIF LCDIF
-#define APP_LCDIF_DATA_BUS              kELCDIF_DataBus16Bit
-#define FRAME_BUFFER_COUNT              2
-
-#define RT_HW_LCD_WIDTH                 ((uint16_t)800)     /* LCD PIXEL WIDTH            */
-#define RT_HW_LCD_HEIGHT                ((uint16_t)480)     /* LCD PIXEL HEIGHT           */
-        
-ALIGN(FRAME_BUFFER_ALIGN)
-static LCD_PIXEL_T lcdif_frame_buffer[FRAME_BUFFER_COUNT][RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH] SECTION("NonCacheable");
 
-
-#ifdef LCD_DEBUG
-static volatile bool s_frameDone = false;
+#if !defined(LCD_WIDTH) || !defined(LCD_HEIGHT) 
+#error "Please config lcd pixel parameters." 
 #endif
 
-struct imxrt_lcd_t
-{
-    struct rt_device_graphic_info lcd_info;
-    struct rt_device lcd;
-    struct rt_semaphore lcd_sem;
-    rt_uint32_t index;              //lcd buffer
-    LCD_PIXEL_T * framebuffer;
-    bool update;
-};
-
-static struct imxrt_lcd_t imxrt_lcd;
-
-static void _lcd_gpio_config(void) 
-{
-  CLOCK_EnableClock(kCLOCK_Iomuxc);          /* iomuxc clock (iomuxc_clk_enable): 0x03u */
-
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_AD_B0_02_GPIO1_IO02,        /* GPIO_AD_B0_02 is configured as GPIO1_IO02 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B0_00_LCD_CLK,              /* GPIO_B0_00 is configured as LCD_CLK */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B0_01_LCD_ENABLE,           /* GPIO_B0_01 is configured as LCD_ENABLE */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B0_02_LCD_HSYNC,            /* GPIO_B0_02 is configured as LCD_HSYNC */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B0_03_LCD_VSYNC,            /* GPIO_B0_03 is configured as LCD_VSYNC */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B0_04_LCD_DATA00,           /* GPIO_B0_04 is configured as LCD_DATA00 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B0_05_LCD_DATA01,           /* GPIO_B0_05 is configured as LCD_DATA01 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B0_06_LCD_DATA02,           /* GPIO_B0_06 is configured as LCD_DATA02 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B0_07_LCD_DATA03,           /* GPIO_B0_07 is configured as LCD_DATA03 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B0_08_LCD_DATA04,           /* GPIO_B0_08 is configured as LCD_DATA04 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B0_09_LCD_DATA05,           /* GPIO_B0_09 is configured as LCD_DATA05 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B0_10_LCD_DATA06,           /* GPIO_B0_10 is configured as LCD_DATA06 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B0_11_LCD_DATA07,           /* GPIO_B0_11 is configured as LCD_DATA07 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B0_12_LCD_DATA08,           /* GPIO_B0_12 is configured as LCD_DATA08 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B0_13_LCD_DATA09,           /* GPIO_B0_13 is configured as LCD_DATA09 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B0_14_LCD_DATA10,           /* GPIO_B0_14 is configured as LCD_DATA10 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B0_15_LCD_DATA11,           /* GPIO_B0_15 is configured as LCD_DATA11 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B1_00_LCD_DATA12,           /* GPIO_B1_00 is configured as LCD_DATA12 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B1_01_LCD_DATA13,           /* GPIO_B1_01 is configured as LCD_DATA13 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B1_02_LCD_DATA14,           /* GPIO_B1_02 is configured as LCD_DATA14 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B1_03_LCD_DATA15,           /* GPIO_B1_03 is configured as LCD_DATA15 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinMux(
-      IOMUXC_GPIO_B1_15_GPIO2_IO31,           /* GPIO_B1_15 is configured as GPIO2_IO31 */
-      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_AD_B0_02_GPIO1_IO02,        /* GPIO_AD_B0_02 PAD functional properties : */
-      0x10B0u);                               /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Keeper
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
-                                                 Hyst. Enable Field: Hysteresis Disabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B0_00_LCD_CLK,              /* GPIO_B0_00 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B0_01_LCD_ENABLE,           /* GPIO_B0_01 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B0_02_LCD_HSYNC,            /* GPIO_B0_02 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B0_03_LCD_VSYNC,            /* GPIO_B0_03 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B0_04_LCD_DATA00,           /* GPIO_B0_04 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B0_05_LCD_DATA01,           /* GPIO_B0_05 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B0_06_LCD_DATA02,           /* GPIO_B0_06 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B0_07_LCD_DATA03,           /* GPIO_B0_07 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B0_08_LCD_DATA04,           /* GPIO_B0_08 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B0_09_LCD_DATA05,           /* GPIO_B0_09 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B0_10_LCD_DATA06,           /* GPIO_B0_10 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B0_11_LCD_DATA07,           /* GPIO_B0_11 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B0_12_LCD_DATA08,           /* GPIO_B0_12 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B0_13_LCD_DATA09,           /* GPIO_B0_13 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B0_14_LCD_DATA10,           /* GPIO_B0_14 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B0_15_LCD_DATA11,           /* GPIO_B0_15 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B1_00_LCD_DATA12,           /* GPIO_B1_00 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B1_01_LCD_DATA13,           /* GPIO_B1_01 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B1_02_LCD_DATA14,           /* GPIO_B1_02 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B1_03_LCD_DATA15,           /* GPIO_B1_03 PAD functional properties : */
-      0x01B0B0u);                             /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Pull
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Enabled */
-  IOMUXC_SetPinConfig(
-      IOMUXC_GPIO_B1_15_GPIO2_IO31,           /* GPIO_B1_15 PAD functional properties : */
-      0x10B0u);                               /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Keeper
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
-                                                 Hyst. Enable Field: Hysteresis Disabled */
-}
-
-static void _lcd_clock_config(void)
-{
-    /*
-     * The desired output frame rate is 60Hz. So the pixel clock frequency is:
-     * (480 + 41 + 4 + 18) * (272 + 10 + 4 + 2) * 60 = 9.2M.
-     * Here set the LCDIF pixel clock to 9.3M.
-     */
-
-    /*
-     * Initialize the Video PLL.
-     * Video PLL output clock is OSC24M * (loopDivider + (denominator / numerator)) / postDivider = 93MHz.
-     */
-    clock_video_pll_config_t config = {
-        .loopDivider = 31, .postDivider = 8, .numerator = 0, .denominator = 0,
-    };
-
-    CLOCK_InitVideoPll(&config);
-
-    /*
-     * 000 derive clock from PLL2
-     * 001 derive clock from PLL3 PFD3
-     * 010 derive clock from PLL5
-     * 011 derive clock from PLL2 PFD0
-     * 100 derive clock from PLL2 PFD1
-     * 101 derive clock from PLL3 PFD1
-     */
-    CLOCK_SetMux(kCLOCK_Lcdif1PreMux, 2);
-
-    CLOCK_SetDiv(kCLOCK_Lcdif1PreDiv, 4);
-
-    CLOCK_SetDiv(kCLOCK_Lcdif1Div, 1);
-
-    /*
-     * 000 derive clock from divided pre-muxed lcdif1 clock
-     * 001 derive clock from ipp_di0_clk
-     * 010 derive clock from ipp_di1_clk
-     * 011 derive clock from ldb_di0_clk
-     * 100 derive clock from ldb_di1_clk
-     */
-    CLOCK_SetMux(kCLOCK_Lcdif1Mux, 0);
-}
-
-/* Initialize the LCD_DISP. */
-static void _lcd_hardware_reset(void)
-{
-    volatile uint32_t i = 0x100U;
-
-    gpio_pin_config_t config = {
-        kGPIO_DigitalOutput, 0,
-    };
-
-    /* Reset the LCD. */
-    GPIO_PinInit(LCD_DISP_GPIO, LCD_DISP_GPIO_PIN, &config);
-
-    GPIO_PinWrite(LCD_DISP_GPIO, LCD_DISP_GPIO_PIN, 0);
-
-    while (i--)
-    {
-    }
-
-    GPIO_PinWrite(LCD_DISP_GPIO, LCD_DISP_GPIO_PIN, 1);
-
-    /* Backlight. */
-    config.outputLogic = 1;
-    GPIO_PinInit(LCD_BL_GPIO, LCD_BL_GPIO_PIN, &config);
-}
-
-static void _lcdif_init(void)
-{
-    const elcdif_rgb_mode_config_t config = {
-        .panelWidth = RT_HW_LCD_WIDTH,
-        .panelHeight = RT_HW_LCD_HEIGHT,
-        .hsw = APP_HSW,
-        .hfp = APP_HFP,
-        .hbp = APP_HBP,
-        .vsw = APP_VSW,
-        .vfp = APP_VFP,
-        .vbp = APP_VBP,
-        .polarityFlags = APP_POL_FLAGS,
-        .bufferAddr = (uint32_t)lcdif_frame_buffer[0],
-        .pixelFormat = kELCDIF_PixelFormatRGB565,
-        .dataBus = APP_LCDIF_DATA_BUS,
-    };
+#if !defined(LCD_HFP) || !defined(LCD_HBP) || !defined(LCD_HSW) || \
+    !defined(LCD_VFP) || !defined(LCD_VBP) || !defined(LCD_VSW)
+#error "Please config lcd timing parameters." 
+#endif
 
-    ELCDIF_RgbModeInit(LCDIF, &config);
-}
+#if !defined(LCD_BL_PIN) || !defined(LCD_RST_PIN) 
+#error "Please config lcd backlight or reset pin." 
+#endif
 
-static void _lcd_interrupt_init(void)
+struct rt1050_lcd
 {
-    EnableIRQ(LCDIF_IRQn);
-    ELCDIF_EnableInterrupts(LCDIF, kELCDIF_CurFrameDoneInterruptEnable);
-}
+    struct rt_device device; 
+    struct rt_device_graphic_info info; 
+}; 
 
-static void _lcd_start(void)
-{
-    ELCDIF_RgbModeStart(LCDIF);
-}
+static struct rt1050_lcd lcd; 
+ALIGN(64) static uint16_t frame_buffer[LCD_HEIGHT][LCD_WIDTH] SECTION("NonCacheable"); 
 
-void LCDIF_IRQHandler(void)
+static rt_err_t rt1050_lcd_init(rt_device_t device)
 {
-    uint32_t intStatus;
-
-    intStatus = ELCDIF_GetInterruptStatus(LCDIF);
-
-    ELCDIF_ClearInterruptStatus(LCDIF, intStatus);
-
-    if (intStatus & kELCDIF_CurFrameDone)
-    {
-#ifdef LCD_DEBUG
-        s_frameDone = true;  
-#endif
+    RT_ASSERT(device != RT_NULL); 
+    
+    rt_memset(frame_buffer, 0x00, sizeof(frame_buffer)); 
 
-        if (imxrt_lcd.update)
-        {
-            ELCDIF_SetNextBufferAddr(LCDIF, (uint32_t)lcdif_frame_buffer[imxrt_lcd.index]);
-            imxrt_lcd.update = false;
-            rt_sem_release(&imxrt_lcd.lcd_sem);
-        }
+    /* CLK */
+    clock_video_pll_config_t pll_config;
+    
+    pll_config.loopDivider = 43;
+    pll_config.postDivider = 4;
+    pll_config.numerator   = 0;
+    pll_config.denominator = 0;
+    
+    CLOCK_InitVideoPll(&pll_config); 
 
-    }
+    CLOCK_SetMux(kCLOCK_Lcdif1PreMux, 2); 
+    CLOCK_SetDiv(kCLOCK_Lcdif1PreDiv, 4); 
+    CLOCK_SetMux(kCLOCK_Lcdif1Mux, 0); 
+    CLOCK_SetDiv(kCLOCK_Lcdif1Div, 1); 
+    
+    /* GPIO */ 
+    CLOCK_EnableClock(kCLOCK_Iomuxc); 
+    
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B0_04_LCD_DATA00, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_LCD_DATA00, 0x01B0B0U); /* LCD_B3 */ 
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B0_05_LCD_DATA01, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_LCD_DATA01, 0x01B0B0U); /* LCD_B4 */ 
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B0_06_LCD_DATA02, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_06_LCD_DATA02, 0x01B0B0U); /* LCD_B5 */ 
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B0_07_LCD_DATA03, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_07_LCD_DATA03, 0x01B0B0U); /* LCD_B6 */ 
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B0_08_LCD_DATA04, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_08_LCD_DATA04, 0x01B0B0U); /* LCD_B7 */ 
+    
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B0_09_LCD_DATA05, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_09_LCD_DATA05, 0x01B0B0U); /* LCD_G2 */ 
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B0_10_LCD_DATA06, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_10_LCD_DATA06, 0x01B0B0U); /* LCD_G3 */ 
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B0_11_LCD_DATA07, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_11_LCD_DATA07, 0x01B0B0U); /* LCD_G4 */ 
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B0_12_LCD_DATA08, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_LCD_DATA08, 0x01B0B0U); /* LCD_G5 */ 
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B0_13_LCD_DATA09, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_LCD_DATA09, 0x01B0B0U); /* LCD_G6 */ 
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B0_14_LCD_DATA10, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_LCD_DATA10, 0x01B0B0U); /* LCD_G7 */ 
+    
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B0_15_LCD_DATA11, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_LCD_DATA11, 0x01B0B0U); /* LCD_R3 */ 
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B1_00_LCD_DATA12, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LCD_DATA12, 0x01B0B0U); /* LCD_R4 */ 
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B1_01_LCD_DATA13, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LCD_DATA13, 0x01B0B0U); /* LCD_R5 */ 
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B1_02_LCD_DATA14, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_LCD_DATA14, 0x01B0B0U); /* LCD_R6 */ 
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B1_03_LCD_DATA15, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_LCD_DATA15, 0x01B0B0U); /* LCD_R7 */ 
+    
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B0_00_LCD_CLK,    0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LCD_CLK,    0x01B0B0u); /* LCD_CLK */ 
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B0_02_LCD_HSYNC,  0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LCD_HSYNC,  0x01B0B0u); /* LCD_HSYNC */ 
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B0_03_LCD_VSYNC,  0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LCD_VSYNC,  0x01B0B0u); /* LCD_VSYNC */ 
+    IOMUXC_SetPinMux   (IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U); 
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0x01B0B0u); /* LCD_ENABLE */ 
+    
+    rt_pin_mode(LCD_RST_PIN, PIN_MODE_OUTPUT); /* LCD_RESET */ 
+    rt_pin_write(LCD_RST_PIN, PIN_LOW); 
+    rt_thread_delay(RT_TICK_PER_SECOND/100); 
+    rt_pin_write(LCD_RST_PIN, PIN_HIGH); 
+    
+    rt_pin_mode (LCD_BL_PIN, PIN_MODE_OUTPUT);  /* LCD_BL */ 
+    rt_pin_write(LCD_BL_PIN, PIN_HIGH); 
+    
+    /* LCD */ 
+    elcdif_rgb_mode_config_t lcd_config; 
+    
+    lcd_config.hfp           = LCD_HFP; 
+    lcd_config.vfp           = LCD_VFP; 
+    lcd_config.hbp           = LCD_HBP; 
+    lcd_config.vbp           = LCD_VBP; 
+    lcd_config.hsw           = LCD_HSW; 
+    lcd_config.vsw           = LCD_VSW; 
+    
+    lcd_config.polarityFlags = kELCDIF_DataEnableActiveHigh | 
+                               kELCDIF_VsyncActiveHigh      | 
+                               kELCDIF_HsyncActiveLow       | 
+                               kELCDIF_DriveDataOnRisingClkEdge;
+    
+    lcd_config.panelWidth    = LCD_WIDTH; 
+    lcd_config.panelHeight   = LCD_HEIGHT; 
+    lcd_config.pixelFormat   = kELCDIF_PixelFormatRGB565; 
+    lcd_config.dataBus       = kELCDIF_DataBus16Bit; 
+    lcd_config.bufferAddr    = (uint32_t)frame_buffer; 
+    
+    ELCDIF_RgbModeInit (LCDIF, &lcd_config);
+    ELCDIF_RgbModeStart(LCDIF); 
+    
+    /* LCD DEVICE */
+    lcd.info.width          = LCD_WIDTH;
+    lcd.info.height         = LCD_HEIGHT;
+    lcd.info.pixel_format   = RTGRAPHIC_PIXEL_FORMAT_RGB565;
+    lcd.info.bits_per_pixel = 16; 
+    lcd.info.framebuffer    = (void *)frame_buffer;
+
+    return RT_EOK; 
 }
 
-static rt_err_t rt_lcd_control(rt_device_t dev, int cmd, void *args)
+static rt_err_t rt1050_lcd_control(rt_device_t device, int cmd, void *args)
 {
-    switch (cmd)
+    switch(cmd)
     {
-    case RTGRAPHIC_CTRL_RECT_UPDATE:
-    {        
-        if(rt_sem_take(&imxrt_lcd.lcd_sem, RT_TICK_PER_SECOND/20) != RT_EOK)
-        {
-            rt_kprintf("lcdtimeout!\n");
-        }
-        
-        imxrt_lcd.index = (imxrt_lcd.index + 1) % FRAME_BUFFER_COUNT;
-        memcpy(lcdif_frame_buffer[imxrt_lcd.index], imxrt_lcd.framebuffer, 
-               sizeof(LCD_PIXEL_T) * RT_HW_LCD_WIDTH * RT_HW_LCD_HEIGHT);
-        imxrt_lcd.update = true;
-    }
-    break;
+    case RTGRAPHIC_CTRL_RECT_UPDATE: 
+        break;
     
-    case RTGRAPHIC_CTRL_POWERON:
+    case RTGRAPHIC_CTRL_POWERON: 
+        rt_pin_write(LCD_BL_PIN, PIN_HIGH); 
         break;
     
-    case RTGRAPHIC_CTRL_POWEROFF:
+    case RTGRAPHIC_CTRL_POWEROFF: 
+        rt_pin_write(LCD_BL_PIN, PIN_LOW); 
         break;
     
     case RTGRAPHIC_CTRL_GET_INFO:
-        memcpy(args, &imxrt_lcd.lcd_info, sizeof(imxrt_lcd.lcd_info));
+        rt_memcpy(args, &lcd.info, sizeof(lcd.info)); 
         break;
     
     case RTGRAPHIC_CTRL_SET_MODE:
@@ -523,166 +177,22 @@ static rt_err_t rt_lcd_control(rt_device_t dev, int cmd, void *args)
     return RT_EOK;
 }
 
-int imxrt_hw_lcd_init(void)
+int rt_hw_lcd_init(void)
 {
-    LCD_PIXEL_T * framebuffer;
-    
-    framebuffer = rt_malloc_align(sizeof(LCD_PIXEL_T) * RT_HW_LCD_WIDTH * RT_HW_LCD_HEIGHT, FRAME_BUFFER_ALIGN);
-    if(!framebuffer)
-    {
-        rt_kprintf("malloc framebuffer fail\n");
-        return -1;
-    }
-    imxrt_lcd.framebuffer = framebuffer;
-    
-    memset(framebuffer,         LCD_INIT_DATA, sizeof(LCD_PIXEL_T) * RT_HW_LCD_WIDTH * RT_HW_LCD_HEIGHT);
-    memset(lcdif_frame_buffer,  LCD_INIT_DATA, sizeof(lcdif_frame_buffer));
-    
-    rt_kprintf("framebuffer: %p, lcdif_frame_buffer: %p, lcdif_frame_buffer[0]: %p, lcdif_frame_buffer[1]: %p\n", \
-        framebuffer, lcdif_frame_buffer, lcdif_frame_buffer[0], lcdif_frame_buffer[1]);
-
-    _lcd_gpio_config();
-    _lcd_clock_config();
-    _lcd_hardware_reset();
-    _lcdif_init();
-    _lcd_interrupt_init();
-    _lcd_start();
-        
-    imxrt_lcd.index = 0;
-    imxrt_lcd.update = false;
-    
-    imxrt_lcd.lcd_info.bits_per_pixel = LCD_BITS_PER_PIXEL;
-    imxrt_lcd.lcd_info.pixel_format   = RTGRAPHIC_PIXEL_FORMAT_RGB565;
-    imxrt_lcd.lcd_info.framebuffer    = (void *)framebuffer;
-    imxrt_lcd.lcd_info.width          = RT_HW_LCD_WIDTH;
-    imxrt_lcd.lcd_info.height         = RT_HW_LCD_HEIGHT;
+    rt_err_t ret; 
+
+    lcd.device.type    = RT_Device_Class_Graphic; 
+    lcd.device.init    = rt1050_lcd_init; 
+    lcd.device.open    = RT_NULL;
+    lcd.device.close   = RT_NULL;
+    lcd.device.read    = RT_NULL;
+    lcd.device.write   = RT_NULL;
+    lcd.device.control = rt1050_lcd_control; 
     
-    imxrt_lcd.lcd.type    = RT_Device_Class_Graphic;
-    imxrt_lcd.lcd.init    = NULL;
-    imxrt_lcd.lcd.open    = NULL;
-    imxrt_lcd.lcd.close   = NULL;
-    imxrt_lcd.lcd.read    = NULL;
-    imxrt_lcd.lcd.write   = NULL;
-    imxrt_lcd.lcd.control = rt_lcd_control;
-    imxrt_lcd.lcd.user_data = (void *)&imxrt_lcd.lcd_info;
+    lcd.device.user_data = (void *)&lcd.info; 
     
-    rt_sem_init(&imxrt_lcd.lcd_sem, "lcd_sem", 1, RT_IPC_FLAG_FIFO);
-    
-    /* register lcd device to RT-Thread */
-    rt_device_register(&imxrt_lcd.lcd, "lcd", RT_DEVICE_FLAG_RDWR);
-    
-
-    return 0;
-}
-//INIT_DEVICE_EXPORT(imxrt_hw_lcd_init);
-
-#ifdef LCD_DEBUG
-#include <finsh.h>
-
-void APP_FillFrameBuffer(uint32_t frameBuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH])
-{
-    /* Background color. */
-    static const uint32_t bgColor = 0U;
-    /* Foreground color. */
-    static uint8_t fgColorIndex = 0U;
-    static const uint32_t fgColorTable[] = {0x000000FFU, 0x0000FF00U, 0x0000FFFFU, 0x00FF0000U,
-                                            0x00FF00FFU, 0x00FFFF00U, 0x00FFFFFFU};
-    uint32_t fgColor = fgColorTable[fgColorIndex];
-
-    /* Position of the foreground rectangle. */
-    static uint16_t upperLeftX = 0U;
-    static uint16_t upperLeftY = 0U;
-    static uint16_t lowerRightX = (RT_HW_LCD_WIDTH - 1U) / 2U;
-    static uint16_t lowerRightY = (RT_HW_LCD_HEIGHT - 1U) / 2U;
-
-    static int8_t incX = 1;
-    static int8_t incY = 1;
-
-    /* Change color in next forame or not. */
-    static bool changeColor = false;
-
-    uint32_t i, j;
-
-    /* Background color. */
-    for (i = 0; i < RT_HW_LCD_HEIGHT; i++)
-    {
-        for (j = 0; j < RT_HW_LCD_WIDTH; j++)
-        {
-            frameBuffer[i][j] = bgColor;
-        }
-    }
-
-    /* Foreground color. */
-    for (i = upperLeftY; i < lowerRightY; i++)
-    {
-        for (j = upperLeftX; j < lowerRightX; j++)
-        {
-            frameBuffer[i][j] = fgColor;
-        }
-    }
-
-    /* Update the format: color and rectangle position. */
-    upperLeftX += incX;
-    upperLeftY += incY;
-    lowerRightX += incX;
-    lowerRightY += incY;
-
-    changeColor = false;
-
-    if (0U == upperLeftX)
-    {
-        incX = 1;
-        changeColor = true;
-    }
-    else if (RT_HW_LCD_WIDTH - 1 == lowerRightX)
-    {
-        incX = -1;
-        changeColor = true;
-    }
-
-    if (0U == upperLeftY)
-    {
-        incY = 1;
-        changeColor = true;
-    }
-    else if (RT_HW_LCD_HEIGHT - 1 == lowerRightY)
-    {
-        incY = -1;
-        changeColor = true;
-    }
-
-    if (changeColor)
-    {
-        fgColorIndex++;
-
-        if (ARRAY_SIZE(fgColorTable) == fgColorIndex)
-        {
-            fgColorIndex = 0U;
-        }
-    }
-}
-
-void lcd_test(void)
-{
-    uint32_t frameBufferIndex = 0;
+    ret = rt_device_register(&lcd.device, "lcd", RT_DEVICE_FLAG_RDWR); 
     
-    APP_FillFrameBuffer(lcdif_frame_buffer[frameBufferIndex]);
-     
-    while (1)
-    {
-        frameBufferIndex ^= 1U;
-
-        APP_FillFrameBuffer(lcdif_frame_buffer[frameBufferIndex]);
-
-        ELCDIF_SetNextBufferAddr(LCDIF, (uint32_t)lcdif_frame_buffer[frameBufferIndex]);
-
-        s_frameDone = false;
-        /* Wait for previous frame complete. */
-        while (!s_frameDone)
-        {
-        }
-    }
+    return ret; 
 }
-FINSH_FUNCTION_EXPORT(lcd_test, lcd test);
-#endif
-#endif
+INIT_DEVICE_EXPORT(rt_hw_lcd_init); 

bsp/imxrt1052-evk/drivers/drv_lcd.h

@@ -1,29 +1,23 @@
 /*
- * File      : drv_i2c.c
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * File      : drv_lcd2.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
  *
  * Change Logs:
  * Date           Author       Notes
- * 2017-12-15     Tanek        the first version
+ * 2018-04-05     Liuguang     the first version.
  */
  
 #ifndef __DRV_LCD_H__
 #define __DRV_LCD_H__
 
-extern int imxrt_hw_lcd_init(void);
+#include <rtthread.h> 
+#include <rtdevice.h> 
+
+int rt_hw_lcd_init(void);
 
 #endif

bsp/imxrt1052-evk/drivers/drv_pin.c

@@ -392,7 +392,6 @@ void GPIO5_Combined_0_15_IRQHandler(void)
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
-    
     rt_interrupt_leave();
 }
 
@@ -473,13 +472,13 @@ static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     {
         CLOCK_EnableClock(kCLOCK_Iomuxc); 
         
-        IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 0); 
+        IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 1); 
     }
     else
     {
         CLOCK_EnableClock(kCLOCK_IomuxcSnvs); 
         
-        IOMUXC_SetPinMux(0x401F8000U + (pin-125)*4, 0x5U, 0, 0, 0, 0); 
+        IOMUXC_SetPinMux(0x401F8000U + (pin-125)*4, 0x5U, 0, 0, 0, 1); 
     }
     
     gpio.outputLogic = 0; 
@@ -530,7 +529,7 @@ static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 
 static int rt1052_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    return GPIO_PinRead(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin); 
+    return GPIO_PinReadPadStatus(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin); 
 }
 
 static void rt1052_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)

bsp/imxrt1052-evk/drivers/drv_hp_rtc.c → bsp/imxrt1052-evk/drivers/drv_rtc.c

@@ -1,5 +1,5 @@
 /*
- * File      : drv_hp_rtc.c
+ * File      : drv_rtc.c
  * This file is part of RT-Thread RTOS
  * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
  *
@@ -11,11 +11,12 @@
  * Date           Author       Notes
  * 2018-03-15     Liuguang     the first version.
  */
-#include "drv_hp_rtc.h" 
-#include <time.h>
+#include "drv_rtc.h" 
+
 #include "fsl_common.h" 
 #include "fsl_snvs_hp.h"
 #include "fsl_snvs_lp.h"
+#include <time.h>
 
 #ifdef RT_USING_RTC
 
@@ -35,7 +36,7 @@ static time_t get_timestamp(void)
     tm_new.tm_hour = rtcDate.hour;
     
     tm_new.tm_mday = rtcDate.day; 
-    tm_new.tm_mon  = rtcDate.month - 1;  
+    tm_new.tm_mon  = rtcDate.month - 1; 
     tm_new.tm_year = rtcDate.year - 1900; 
 
     return mktime(&tm_new);

bsp/imxrt1052-evk/drivers/drv_hp_rtc.h → bsp/imxrt1052-evk/drivers/drv_rtc.h

@@ -1,5 +1,5 @@
 /*
- * File      : drv_hp_rtc.h
+ * File      : drv_rtc.h
  * This file is part of RT-Thread RTOS
  * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
  *

bsp/imxrt1052-evk/drivers/drv_sdio.c

@@ -56,7 +56,7 @@ static int enable_log = 1;
 
 #define USDHC_ADMA_TABLE_WORDS      (8U)        /* define the ADMA descriptor table length */
 #define USDHC_ADMA2_ADDR_ALIGN      (4U)        /* define the ADMA2 descriptor table addr align size */
-#define IMXRT_MAX_FREQ              (400 * 1000u)
+#define IMXRT_MAX_FREQ              (50UL * 1000UL * 1000UL)
     
 #define USDHC_ADMA_TABLE_WORDS      (8U)        /* define the ADMA descriptor table length */
 #define USDHC_ADMA2_ADDR_ALIGN      (4U)        /* define the ADMA2 descriptor table addr align size */
@@ -357,7 +357,7 @@ static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
             if (buf)
             {
                 MMCSD_DGB(" write(data->buf to buf) ");
-                memcpy(buf, data->buf, fsl_data.blockSize * fsl_data.blockCount);
+                rt_memcpy(buf, data->buf, fsl_data.blockSize * fsl_data.blockCount);
                 fsl_data.txData = (uint32_t const *)buf;
             }
             else
@@ -401,7 +401,7 @@ static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
         if (fsl_data.rxData)
         {
             MMCSD_DGB("read copy buf to data->buf ");
-            memcpy(data->buf, buf, fsl_data.blockSize * fsl_data.blockCount);
+            rt_memcpy(data->buf, buf, fsl_data.blockSize * fsl_data.blockCount);
         }
     
         rt_free_align(buf);

bsp/imxrt1052-evk/drivers/drv_spi_bus.c

@@ -0,0 +1,428 @@
+/*
+ * File      : drv_spi_bus.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-03-27     Liuguang     the first version.
+ */
+ 
+#include "drv_spi_bus.h" 
+
+#include "fsl_common.h" 
+#include "fsl_iomuxc.h" 
+#include "fsl_lpspi.h" 
+
+#if defined(RT_USING_SPIBUS1) || defined(RT_USING_SPIBUS2) || \
+    defined(RT_USING_SPIBUS3) || defined(RT_USING_SPIBUS4)
+
+#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
+    #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
+#endif
+
+#if !defined(LPSPI_CLK_SOURCE)
+#define LPSPI_CLK_SOURCE         (1U) /* PLL3 PFD0 */ 
+#endif
+#if !defined(LPSPI_CLK_SOURCE_DIVIDER)
+#define LPSPI_CLK_SOURCE_DIVIDER (8U) /* 8div */
+#endif
+
+/* LPSPI1 SCK SDO SDI IOMUX Config */
+#if   defined(LPSPI1_SCK_GPIO_1) 
+#define LPSPI1_SCK_GPIO IOMUXC_GPIO_EMC_27_LPSPI1_SCK
+#elif defined(LPSPI1_SCK_GPIO_2) 
+#define LPSPI1_SCK_GPIO IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK
+#else
+#define LPSPI1_SCK_GPIO IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK
+#endif 
+
+#if   defined(LPSPI1_SDO_GPIO_1) 
+#define LPSPI1_SDO_GPIO IOMUXC_GPIO_EMC_28_LPSPI1_SDO
+#elif defined(LPSPI1_SDO_GPIO_2) 
+#define LPSPI1_SDO_GPIO IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO
+#else
+#define LPSPI1_SDO_GPIO IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO
+#endif 
+
+#if   defined(LPSPI1_SDI_GPIO_1) 
+#define LPSPI1_SDI_GPIO IOMUXC_GPIO_EMC_29_LPSPI1_SDI
+#elif defined(LPSPI1_SDI_GPIO_2) 
+#define LPSPI1_SDI_GPIO IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI
+#else
+#define LPSPI1_SDI_GPIO IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI
+#endif 
+
+/* LPSPI2 SCK SDO SDI IOMUX Config */
+#if   defined(LPSPI2_SCK_GPIO_1) 
+#define LPSPI2_SCK_GPIO IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK
+#elif defined(LPSPI2_SCK_GPIO_2) 
+#define LPSPI2_SCK_GPIO IOMUXC_GPIO_EMC_00_LPSPI2_SCK
+#else
+#define LPSPI2_SCK_GPIO IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK
+#endif 
+
+#if   defined(LPSPI2_SDO_GPIO_1) 
+#define LPSPI2_SDO_GPIO IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0
+#elif defined(LPSPI2_SDO_GPIO_2) 
+#define LPSPI2_SDO_GPIO IOMUXC_GPIO_EMC_02_LPSPI2_SDO
+#else
+#define LPSPI2_SDO_GPIO IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0
+#endif 
+
+#if   defined(LPSPI2_SDI_GPIO_1) 
+#define LPSPI2_SDI_GPIO IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI
+#elif defined(LPSPI2_SDI_GPIO_2) 
+#define LPSPI2_SDI_GPIO IOMUXC_GPIO_EMC_03_LPSPI2_SDI
+#else
+#define LPSPI2_SDI_GPIO IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI
+#endif 
+
+/* LPSPI3 SCK SDO SDI IOMUX Config */
+#if   defined(LPSPI3_SCK_GPIO_1) 
+#define LPSPI3_SCK_GPIO IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK
+#elif defined(LPSPI3_SCK_GPIO_2) 
+#define LPSPI3_SCK_GPIO IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK
+#else
+#define LPSPI3_SCK_GPIO IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK
+#endif 
+
+#if   defined(LPSPI3_SDO_GPIO_1) 
+#define LPSPI3_SDO_GPIO IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO
+#elif defined(LPSPI3_SDO_GPIO_2) 
+#define LPSPI3_SDO_GPIO IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO
+#else
+#define LPSPI3_SDO_GPIO IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO
+#endif 
+
+#if   defined(LPSPI3_SDI_GPIO_1) 
+#define LPSPI3_SDI_GPIO IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI
+#elif defined(LPSPI3_SDI_GPIO_2) 
+#define LPSPI3_SDI_GPIO IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI
+#else
+#define LPSPI3_SDI_GPIO IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI
+#endif 
+
+/* LPSPI4 SCK SDO SDI IOMUX Config */
+#if   defined(LPSPI4_SCK_GPIO_1) 
+#define LPSPI4_SCK_GPIO IOMUXC_GPIO_B0_03_LPSPI4_SCK
+#elif defined(LPSPI4_SCK_GPIO_2) 
+#define LPSPI4_SCK_GPIO IOMUXC_GPIO_B1_07_LPSPI4_SCK
+#else
+#define LPSPI4_SCK_GPIO IOMUXC_GPIO_B0_03_LPSPI4_SCK
+#endif 
+
+#if   defined(LPSPI4_SDO_GPIO_1) 
+#define LPSPI4_SDO_GPIO IOMUXC_GPIO_B0_02_LPSPI4_SDO
+#elif defined(LPSPI4_SDO_GPIO_2) 
+#define LPSPI4_SDO_GPIO IOMUXC_GPIO_B1_06_LPSPI4_SDO
+#else
+#define LPSPI4_SDO_GPIO IOMUXC_GPIO_B0_02_LPSPI4_SDO
+#endif 
+
+#if   defined(LPSPI4_SDI_GPIO_1) 
+#define LPSPI4_SDI_GPIO IOMUXC_GPIO_B0_01_LPSPI4_SDI
+#elif defined(LPSPI4_SDI_GPIO_2) 
+#define LPSPI4_SDI_GPIO IOMUXC_GPIO_B1_05_LPSPI4_SDI
+#else
+#define LPSPI4_SDI_GPIO IOMUXC_GPIO_B0_01_LPSPI4_SDI
+#endif 
+
+struct rt1050_spi
+{
+    LPSPI_Type *base;
+    struct rt_spi_configuration *cfg;
+};
+
+struct rt1050_sw_spi_cs
+{
+    rt_uint32_t pin;
+};
+
+static uint32_t rt1050_get_lpspi_freq(void)
+{
+    uint32_t freq = 0;
+
+    /* CLOCK_GetMux(kCLOCK_LpspiMux):
+       00b: derive clock from PLL3 PFD1 720M 
+       01b: derive clock from PLL3 PFD0 720M 
+       10b: derive clock from PLL2      528M 
+       11b: derive clock from PLL2 PFD2 396M 
+    */
+    switch(CLOCK_GetMux(kCLOCK_LpspiMux))
+    {
+    case 0:
+        freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk); 
+        break; 
+        
+    case 1:
+        freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk); 
+        break; 
+    
+    case 2:
+        freq = CLOCK_GetFreq(kCLOCK_SysPllClk); 
+        break; 
+    
+    case 3:
+        freq = CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk); 
+        break; 
+    }
+    
+    freq /= (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1U); 
+
+    return freq;
+}
+
+static rt_err_t rt1050_spi_init(LPSPI_Type *base, struct rt_spi_configuration *cfg)
+{
+    lpspi_master_config_t masterConfig; 
+    
+    RT_ASSERT(cfg != RT_NULL); 
+    
+    if(cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32)
+    {
+        return RT_EINVAL; 
+    }
+    
+#if defined(RT_USING_SPIBUS1)
+    if(base == LPSPI1)
+    {
+        IOMUXC_SetPinMux   (LPSPI1_SCK_GPIO, 0U); 
+        IOMUXC_SetPinConfig(LPSPI1_SCK_GPIO, 0x10B0u); 
+        IOMUXC_SetPinMux   (LPSPI1_SDO_GPIO, 0U); 
+        IOMUXC_SetPinConfig(LPSPI1_SDO_GPIO, 0x10B0u); 
+        IOMUXC_SetPinMux   (LPSPI1_SDI_GPIO, 0U); 
+        IOMUXC_SetPinConfig(LPSPI1_SDI_GPIO, 0x10B0u); 
+    }
+#endif 
+    
+#if defined(RT_USING_SPIBUS2)
+    if(base == LPSPI2)
+    {
+        IOMUXC_SetPinMux   (LPSPI2_SCK_GPIO, 0U); 
+        IOMUXC_SetPinConfig(LPSPI2_SCK_GPIO, 0x10B0u); 
+        IOMUXC_SetPinMux   (LPSPI2_SDO_GPIO, 0U); 
+        IOMUXC_SetPinConfig(LPSPI2_SDO_GPIO, 0x10B0u); 
+        IOMUXC_SetPinMux   (LPSPI2_SDI_GPIO, 0U); 
+        IOMUXC_SetPinConfig(LPSPI2_SDI_GPIO, 0x10B0u); 
+    }
+#endif 
+    
+#if defined(RT_USING_SPIBUS3)
+    if(base == LPSPI3)
+    {
+        IOMUXC_SetPinMux   (LPSPI3_SCK_GPIO, 0U); 
+        IOMUXC_SetPinConfig(LPSPI3_SCK_GPIO, 0x10B0u); 
+        IOMUXC_SetPinMux   (LPSPI3_SDO_GPIO, 0U); 
+        IOMUXC_SetPinConfig(LPSPI3_SDO_GPIO, 0x10B0u); 
+        IOMUXC_SetPinMux   (LPSPI3_SDI_GPIO, 0U); 
+        IOMUXC_SetPinConfig(LPSPI3_SDI_GPIO, 0x10B0u); 
+    }
+#endif 
+    
+#if defined(RT_USING_SPIBUS4)
+    if(base == LPSPI4)
+    {
+        IOMUXC_SetPinMux   (LPSPI4_SCK_GPIO, 0U); 
+        IOMUXC_SetPinConfig(LPSPI4_SCK_GPIO, 0x10B0u); 
+        IOMUXC_SetPinMux   (LPSPI4_SDO_GPIO, 0U); 
+        IOMUXC_SetPinConfig(LPSPI4_SDO_GPIO, 0x10B0u); 
+        IOMUXC_SetPinMux   (LPSPI4_SDI_GPIO, 0U); 
+        IOMUXC_SetPinConfig(LPSPI4_SDI_GPIO, 0x10B0u); 
+    }
+#endif 
+    
+    LPSPI_MasterGetDefaultConfig(&masterConfig); 
+    
+    if(cfg->max_hz > 40*1000*1000)
+    {
+        cfg->max_hz = 40*1000*1000;
+    }
+    masterConfig.baudRate     = cfg->max_hz; 
+    masterConfig.bitsPerFrame = cfg->data_width; 
+    
+    if(cfg->mode & RT_SPI_MSB)
+    {
+        masterConfig.direction = kLPSPI_MsbFirst; 
+    }
+    else
+    {
+        masterConfig.direction = kLPSPI_LsbFirst; 
+    }
+    
+    if(cfg->mode & RT_SPI_CPHA)
+    {
+        masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge; 
+    }
+    else
+    {
+        masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge; 
+    }
+    
+    if(cfg->mode & RT_SPI_CPOL)
+    {
+        masterConfig.cpol = kLPSPI_ClockPolarityActiveLow; 
+    }
+    else
+    {
+        masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh; 
+    }
+    
+    masterConfig.pinCfg                        = kLPSPI_SdiInSdoOut; 
+    masterConfig.dataOutConfig                 = kLpspiDataOutTristate;
+    masterConfig.pcsToSckDelayInNanoSec        = 1000000000 / masterConfig.baudRate; 
+    masterConfig.lastSckToPcsDelayInNanoSec    = 1000000000 / masterConfig.baudRate; 
+    masterConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.baudRate; 
+    
+    LPSPI_MasterInit(base, &masterConfig, rt1050_get_lpspi_freq()); 
+    base->CFGR1 |= LPSPI_CFGR1_PCSCFG_MASK; 
+    
+    return RT_EOK; 
+}
+
+rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin)
+{
+    rt_err_t ret = RT_EOK; 
+    
+    struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); 
+    RT_ASSERT(spi_device != RT_NULL); 
+    
+    struct rt1050_sw_spi_cs *cs_pin = (struct rt1050_sw_spi_cs *)rt_malloc(sizeof(struct rt1050_sw_spi_cs)); 
+    RT_ASSERT(cs_pin != RT_NULL);
+    
+    cs_pin->pin = pin;
+    rt_pin_mode(pin, PIN_MODE_OUTPUT); 
+    rt_pin_write(pin, PIN_HIGH); 
+    
+    ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); 
+    
+    return ret; 
+}
+
+static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
+{
+    rt_err_t ret = RT_EOK; 
+    struct rt1050_spi *spi = RT_NULL; 
+    
+    RT_ASSERT(cfg != RT_NULL);
+    RT_ASSERT(device != RT_NULL);
+    
+    spi = (struct rt1050_spi *)(device->bus->parent.user_data); 
+    spi->cfg = cfg; 
+    ret = rt1050_spi_init(spi->base, cfg); 
+    
+    return ret;
+}
+
+static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    lpspi_transfer_t transfer; 
+    
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device->bus != RT_NULL);
+    RT_ASSERT(device->bus->parent.user_data != RT_NULL);
+    
+    struct rt1050_spi *spi = (struct rt1050_spi *)(device->bus->parent.user_data); 
+    struct rt1050_sw_spi_cs *cs = device->parent.user_data; 
+    
+    if(message->cs_take)
+    {
+        rt_pin_write(cs->pin, PIN_LOW);
+    }
+    
+    transfer.dataSize = message->length; 
+    transfer.rxData   = (uint8_t *)(message->recv_buf); 
+    transfer.txData   = (uint8_t *)(message->send_buf); 
+    
+    LPSPI_MasterTransferBlocking(spi->base, &transfer); 
+    
+    if(message->cs_release)
+    {
+        rt_pin_write(cs->pin, PIN_HIGH);
+    }
+    
+    return message->length; 
+}
+
+#if defined(RT_USING_SPIBUS1)
+static struct rt1050_spi spi1 = 
+{
+    .base = LPSPI1
+}; 
+static struct rt_spi_bus spi1_bus = 
+{
+    .parent.user_data = &spi1
+}; 
+#endif
+
+#if defined(RT_USING_SPIBUS2)
+static struct rt1050_spi spi2 = 
+{
+    .base = LPSPI2
+}; 
+static struct rt_spi_bus spi2_bus = 
+{
+    .parent.user_data = &spi2
+}; 
+#endif
+
+#if defined(RT_USING_SPIBUS3)
+static struct rt1050_spi spi3 = 
+{
+    .base = LPSPI3
+}; 
+static struct rt_spi_bus spi3_bus = 
+{
+    .parent.user_data = &spi3
+}; 
+#endif
+
+#if defined(RT_USING_SPIBUS4)
+static struct rt1050_spi spi4 = 
+{
+    .base = LPSPI4
+}; 
+static struct rt_spi_bus spi4_bus = 
+{
+    .parent.user_data = &spi4
+}; 
+#endif
+
+static struct rt_spi_ops rt1050_spi_ops = 
+{
+    .configure = spi_configure, 
+    .xfer      = spixfer
+}; 
+ 
+int rt_hw_spi_bus_init(void)
+{
+    CLOCK_SetMux(kCLOCK_LpspiMux, LPSPI_CLK_SOURCE);
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, LPSPI_CLK_SOURCE_DIVIDER-1); 
+    
+    CLOCK_EnableClock(kCLOCK_Iomuxc); 
+    
+#if defined(RT_USING_SPIBUS1)
+    rt_spi_bus_register(&spi1_bus, "spi1", &rt1050_spi_ops); 
+#endif
+    
+#if defined(RT_USING_SPIBUS2)
+    rt_spi_bus_register(&spi2_bus, "spi2", &rt1050_spi_ops); 
+#endif
+    
+#if defined(RT_USING_SPIBUS3)
+    rt_spi_bus_register(&spi3_bus, "spi3", &rt1050_spi_ops); 
+#endif
+    
+#if defined(RT_USING_SPIBUS4)
+    rt_spi_bus_register(&spi4_bus, "spi4", &rt1050_spi_ops); 
+#endif
+    
+    return RT_EOK; 
+}
+INIT_BOARD_EXPORT(rt_hw_spi_bus_init); 
+
+#endif

bsp/imxrt1052-evk/drivers/drv_spi_bus.h

@@ -0,0 +1,24 @@
+/*
+ * File      : drv_spi_bus.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-03-27     Liuguang     the first version.
+ */
+ 
+#ifndef __DRV_SPI_BUS_H__ 
+#define __DRV_SPI_BUS_H__ 
+
+#include <rtthread.h> 
+#include <rtdevice.h> 
+
+int rt_hw_spi_bus_init(void);
+rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin); 
+
+#endif

bsp/imxrt1052-evk/drivers/drv_spi_flash.c

@@ -0,0 +1,51 @@
+/*
+ * File      : drv_spi_flash.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-04-02     Liuguang     the first version.
+ */
+ 
+#include "drv_spi_flash.h" 
+
+#include "spi_flash.h" 
+#include "spi_flash_sfud.h" 
+
+#ifndef SPI_FLASH_USING_SPIBUS_NAME 
+#define SPI_FLASH_USING_SPIBUS_NAME "spi4" 
+#endif
+#ifndef SPI_FLASH_NAME 
+#define SPI_FLASH_NAME "flash0" 
+#endif
+#ifndef SPI_FLASH_USING_CS_PIN 
+#define SPI_FLASH_USING_CS_PIN (79) 
+#endif
+
+int rt_hw_spi_flash_init(void)
+{
+    rt_err_t ret; 
+    
+    extern rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, 
+        const char *device_name, rt_uint32_t pin); 
+    
+    ret = rt1050_spi_bus_attach_device(SPI_FLASH_USING_SPIBUS_NAME, 
+        SPI_FLASH_USING_SPIBUS_NAME "0", SPI_FLASH_USING_CS_PIN); 
+    if(ret != RT_EOK) 
+    {
+        return ret; 
+    }
+    
+    if(rt_sfud_flash_probe(SPI_FLASH_NAME, SPI_FLASH_USING_SPIBUS_NAME "0") == RT_NULL) 
+    {
+        return RT_ERROR;
+    }
+
+    return RT_EOK; 
+}
+INIT_DEVICE_EXPORT(rt_hw_spi_flash_init); 

bsp/imxrt1052-evk/drivers/drv_spi_flash.h

@@ -0,0 +1,23 @@
+/*
+ * File      : drv_spi_flash.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-04-02     Liuguang     the first version.
+ */
+ 
+#ifndef __DRV_SPI_FLASH_H_ 
+#define __DRV_SPI_FLASH_H_ 
+
+#include <rtthread.h> 
+#include <rtdevice.h> 
+
+int rt_hw_spi_flash_init(void); 
+
+#endif /* __DRV_SPI_FLASH_H_ */ 

bsp/imxrt1052-evk/drivers/drv_uart.c

@@ -21,7 +21,6 @@
 
 #ifdef RT_USING_SERIAL
 
-/* GPIO外设时钟会在LPUART_Init中自动配置, 如果定义了以下宏则不会自动配置 */
 #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
 #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
 #endif
@@ -41,10 +40,10 @@
 /* imxrt uart driver */
 struct imxrt_uart
 {
-    LPUART_Type * uart_base;
+    LPUART_Type *uart_base;
     IRQn_Type irqn;
 
-    struct rt_serial_device * serial;
+    struct rt_serial_device *serial;
     char *device_name;
 };
 
@@ -129,7 +128,8 @@ void LPUART8_IRQHandler(void)
 
 #endif /* RT_USING_UART8 */
 
-static const struct imxrt_uart uarts[] = {
+static const struct imxrt_uart uarts[] =
+{
 #ifdef RT_USING_UART1
     {
         LPUART1,
@@ -198,7 +198,7 @@ static const struct imxrt_uart uarts[] = {
 };
 
 /* Get debug console frequency. */
-uint32_t BOARD_DebugConsoleSrcFreq(void)
+uint32_t GetUartSrcFreq(void)
 {
     uint32_t freq;
 
@@ -231,7 +231,6 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
     if (uart->uart_base != RT_NULL)
     {
 #ifdef RT_USING_UART1
-        CLOCK_EnableClock(kCLOCK_Iomuxc);           /* iomuxc clock (iomuxc_clk_enable): 0x03u */
 
         IOMUXC_SetPinMux(
             IOMUXC_GPIO_AD_B0_12_LPUART1_TX,        /* GPIO_AD_B0_12 is configured as LPUART1_TX */
@@ -261,7 +260,6 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
                                                      Hyst. Enable Field: Hysteresis Disabled */
 #endif
 #ifdef RT_USING_UART2
-        CLOCK_EnableClock(kCLOCK_Iomuxc);
 
         IOMUXC_SetPinMux(
             IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
@@ -272,15 +270,12 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
         IOMUXC_SetPinConfig(
             IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
             0x10B0u);
-
-
         IOMUXC_SetPinConfig(
             IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
             0x10B0u);
 
 #endif
 #ifdef RT_USING_UART3
-        CLOCK_EnableClock(kCLOCK_Iomuxc);
 
         IOMUXC_SetPinMux(
             IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
@@ -291,13 +286,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
         IOMUXC_SetPinConfig(
             IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
             0x10B0u);
-
         IOMUXC_SetPinConfig(
             IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
             0x10B0u);
 #endif
 #ifdef RT_USING_UART4
-        CLOCK_EnableClock(kCLOCK_Iomuxc);
 
         IOMUXC_SetPinMux(
             IOMUXC_GPIO_B1_00_LPUART4_TX,
@@ -308,13 +301,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
         IOMUXC_SetPinConfig(
             IOMUXC_GPIO_B1_00_LPUART4_TX,
             0x10B0u);
-
         IOMUXC_SetPinConfig(
             IOMUXC_GPIO_B1_01_LPUART4_RX,
             0x10B0u);
 #endif
 #ifdef RT_USING_UART5
-        CLOCK_EnableClock(kCLOCK_Iomuxc);
 
         IOMUXC_SetPinMux(
             IOMUXC_GPIO_B1_12_LPUART5_TX,
@@ -325,13 +316,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
         IOMUXC_SetPinConfig(
             IOMUXC_GPIO_B1_12_LPUART5_TX,
             0x10B0u);
-
         IOMUXC_SetPinConfig(
             IOMUXC_GPIO_B1_13_LPUART5_RX,
             0x10B0u);
 #endif
 #ifdef RT_USING_UART6
-        CLOCK_EnableClock(kCLOCK_Iomuxc);
 
         IOMUXC_SetPinMux(
             IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
@@ -342,13 +331,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
         IOMUXC_SetPinConfig(
             IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
             0x10B0u);
-
         IOMUXC_SetPinConfig(
             IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
             0x10B0u);
 #endif
 #ifdef RT_USING_UART7
-        CLOCK_EnableClock(kCLOCK_Iomuxc);
 
         IOMUXC_SetPinMux(
             IOMUXC_GPIO_EMC_31_LPUART7_TX,
@@ -359,13 +346,11 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
         IOMUXC_SetPinConfig(
             IOMUXC_GPIO_EMC_31_LPUART7_TX,
             0x10B0u);
-
         IOMUXC_SetPinConfig(
             IOMUXC_GPIO_EMC_32_LPUART7_RX,
             0x10B0u);
 #endif
 #ifdef RT_USING_UART8
-        CLOCK_EnableClock(kCLOCK_Iomuxc);
 
         IOMUXC_SetPinMux(
             IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
@@ -376,7 +361,6 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
         IOMUXC_SetPinConfig(
             IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
             0x10B0u);
-
         IOMUXC_SetPinConfig(
             IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
             0x10B0u);
@@ -440,8 +424,7 @@ static rt_err_t imxrt_configure(struct rt_serial_device *serial, struct serial_c
     config.enableTx = true;
     config.enableRx = true;
 
-    LPUART_Init(uart->uart_base, &config, BOARD_DebugConsoleSrcFreq());
-
+    LPUART_Init(uart->uart_base, &config, GetUartSrcFreq());
 
     return RT_EOK;
 }
@@ -481,7 +464,7 @@ static int imxrt_putc(struct rt_serial_device *serial, char ch)
     uart = (struct imxrt_uart *)serial->parent.user_data;
 
     LPUART_WriteByte(uart->uart_base, ch);
-    while(!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag));
+    while (!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag));
 
     return 1;
 }
@@ -546,16 +529,21 @@ static const struct rt_uart_ops imxrt_uart_ops =
     imxrt_getc,
 };
 
-int imxrt_hw_usart_init(void)
+int imxrt_hw_uart_init(void)
 {
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
     int i;
+
+    /* Configure UART divider to default */
+    CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
+
     for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
     {
         uarts[i].serial->ops    = &imxrt_uart_ops;
         uarts[i].serial->config = config;
 
-        /* register UART1 device */
+        /* register UART device */
         rt_hw_serial_register(uarts[i].serial,
                               uarts[i].device_name,
                               RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
@@ -564,6 +552,6 @@ int imxrt_hw_usart_init(void)
 
     return 0;
 }
-INIT_BOARD_EXPORT(imxrt_hw_usart_init);
+INIT_BOARD_EXPORT(imxrt_hw_uart_init);
 
 #endif /*RT_USING_SERIAL */

bsp/imxrt1052-evk/drivers/drv_uart.h

@@ -12,12 +12,11 @@
  * 2017-10-10     Tanek        the first version
  */
 
-#ifndef __DRV_USART_H__
-#define __DRV_USART_H__
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
 
 #include <rthw.h>
 #include <rtthread.h>
 
-int rt_hw_usart_init(void);
 
 #endif

bsp/imxrt1052-evk/drivers/drv_usbd.c

@@ -23,7 +23,7 @@
 #error Can not using 2 controller as usb device
 #endif
 #endif
-
+#define FSL_USB_HS
 
 /* USB PHY condfiguration */
 #define BOARD_USB_PHY_D_CAL (0x0CU)
@@ -81,6 +81,27 @@ void USB_DeviceClockInit(uint8_t controllerId)
 #endif
 }
 #ifdef RT_USING_EHCI0_AS_DEVICE
+#ifdef FSL_USB_HS
+static struct ep_id _ehci0_ep_pool[] =
+{
+    {0x0,  USB_EP_ATTR_CONTROL,     USB_DIR_INOUT,  64, ID_ASSIGNED  },
+    {0x1,  USB_EP_ATTR_BULK,        USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x1,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x2,  USB_EP_ATTR_INT,         USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x2,  USB_EP_ATTR_INT,         USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x3,  USB_EP_ATTR_BULK,        USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x3,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x4,  USB_EP_ATTR_INT,         USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x4,  USB_EP_ATTR_INT,         USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x5,  USB_EP_ATTR_BULK,        USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x5,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x6,  USB_EP_ATTR_INT,         USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x6,  USB_EP_ATTR_INT,         USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x7,  USB_EP_ATTR_BULK,        USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x7,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0xFF, USB_EP_ATTR_TYPE_MASK,   USB_DIR_MASK,   0,  ID_ASSIGNED  },
+};
+#else
 static struct ep_id _ehci0_ep_pool[] =
 {
     {0x0,  USB_EP_ATTR_CONTROL,     USB_DIR_INOUT,  64, ID_ASSIGNED  },
@@ -100,6 +121,7 @@ static struct ep_id _ehci0_ep_pool[] =
     {0x7,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    64, ID_UNASSIGNED},
     {0xFF, USB_EP_ATTR_TYPE_MASK,   USB_DIR_MASK,   0,  ID_ASSIGNED  },
 };
+#endif
 void USB_OTG1_IRQHandler(void)
 {
     /* enter interrupt */
@@ -133,6 +155,7 @@ static rt_err_t _ehci0_ep_enable(uep_t ep)
 {
     usb_device_endpoint_init_struct_t ep_init;
     usb_device_endpoint_callback_struct_t ep_callback;
+    rt_uint32_t param = ep->ep_desc->bEndpointAddress;
     RT_ASSERT(ep != RT_NULL);
     RT_ASSERT(ep->ep_desc != RT_NULL);
     ep_init.maxPacketSize = ep->ep_desc->wMaxPacketSize;
@@ -140,7 +163,7 @@ static rt_err_t _ehci0_ep_enable(uep_t ep)
     ep_init.transferType = ep->ep_desc->bmAttributes;
     ep_init.zlt = 0;
     ep_callback.callbackFn = usb_device_endpoint_callback;
-    ep_callback.callbackParam = (void *)ep_init.endpointAddress;
+    ep_callback.callbackParam = (void *)param;
     ep_callback.isBusy = 0;
     USB_DeviceInitEndpoint(ehci0_handle,&ep_init,&ep_callback);
     return RT_EOK;
@@ -220,6 +243,27 @@ static rt_err_t drv_ehci0_usbd_init(rt_device_t device)
 }
 #endif
 #ifdef RT_USING_EHCI1_AS_DEVICE
+#ifdef FSL_USB_HS
+static struct ep_id _ehci1_ep_pool[] =
+{
+    {0x0,  USB_EP_ATTR_CONTROL,     USB_DIR_INOUT,  64, ID_ASSIGNED  },
+    {0x1,  USB_EP_ATTR_BULK,        USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x1,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x2,  USB_EP_ATTR_INT,         USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x2,  USB_EP_ATTR_INT,         USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x3,  USB_EP_ATTR_BULK,        USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x3,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x4,  USB_EP_ATTR_INT,         USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x4,  USB_EP_ATTR_INT,         USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x5,  USB_EP_ATTR_BULK,        USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x5,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x6,  USB_EP_ATTR_INT,         USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x6,  USB_EP_ATTR_INT,         USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0x7,  USB_EP_ATTR_BULK,        USB_DIR_IN,     512, ID_UNASSIGNED},
+    {0x7,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    512, ID_UNASSIGNED},
+    {0xFF, USB_EP_ATTR_TYPE_MASK,   USB_DIR_MASK,   0,  ID_ASSIGNED  },
+};
+#else
 static struct ep_id _ehci1_ep_pool[] =
 {
     {0x0,  USB_EP_ATTR_CONTROL,     USB_DIR_INOUT,  64, ID_ASSIGNED  },
@@ -239,6 +283,7 @@ static struct ep_id _ehci1_ep_pool[] =
     {0x7,  USB_EP_ATTR_BULK,        USB_DIR_OUT,    64, ID_UNASSIGNED},
     {0xFF, USB_EP_ATTR_TYPE_MASK,   USB_DIR_MASK,   0,  ID_ASSIGNED  },
 };
+#endif
 void USB_OTG2_IRQHandler(void)
 {
     /* enter interrupt */
@@ -373,6 +418,11 @@ static int rt_usbd_init(void)
     /* Register endpoint infomation */
     _fsl_udc_0.ep_pool = _ehci0_ep_pool;
     _fsl_udc_0.ep0.id = &_ehci0_ep_pool[0];
+    #ifdef FSL_USB_HS
+    _fsl_udc_0.device_is_hs = RT_TRUE;
+    #else
+    _fsl_udc_0.device_is_hs = RT_FALSE;
+    #endif
     rt_device_register((rt_device_t)&_fsl_udc_0, "usbd", 0);
     rt_usb_device_init();
     #endif
@@ -384,6 +434,11 @@ static int rt_usbd_init(void)
     /* Register endpoint infomation */
     _fsl_udc_1.ep_pool = _ehci1_ep_pool;
     _fsl_udc_1.ep0.id = &_ehci1_ep_pool[0];
+    #ifdef FSL_USB_HS
+    _fsl_udc_1.device_is_hs = RT_TRUE;
+    #else
+    _fsl_udc_1.device_is_hs = RT_FALSE;
+    #endif
     rt_device_register((rt_device_t)&_fsl_udc_1, "usbd", 0);
     rt_usb_device_init();
     #endif
@@ -410,6 +465,7 @@ static usb_status_t usb_device_endpoint_callback(usb_device_handle handle, usb_d
     }
     if(message->isSetup)
     {
+        //rt_kprintf("1udcd:%#08X\n",udcd);
         rt_usbd_ep0_setup_handler(udcd, (struct urequest*)message->buffer);
     }
     else if(ep_addr == 0x00)
@@ -423,6 +479,7 @@ static usb_status_t usb_device_endpoint_callback(usb_device_handle handle, usb_d
                 USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
             }
         }
+        //rt_kprintf("2udcd:%#08X\n",udcd);
         rt_usbd_ep0_out_handler(udcd,message->length);
     }
     else if(ep_addr == 0x80)
@@ -436,6 +493,7 @@ static usb_status_t usb_device_endpoint_callback(usb_device_handle handle, usb_d
                 USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state);
             }
         }
+        //rt_kprintf("3udcd:%#08X\n",udcd);
         rt_usbd_ep0_in_handler(udcd);
     }
     else if(ep_addr&0x80)

bsp/imxrt1052-evk/project.ewp

@@ -308,7 +308,7 @@
           <state>$PROJ_DIR$\Libraries\drivers</state>
           <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include</state>
           <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src</state>
-          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\posix</state>
+          <state>$PROJ_DIR$\drivers</state>
           <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\ipv4</state>
           <state>$PROJ_DIR$\.</state>
           <state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m7</state>
@@ -316,10 +316,11 @@
           <state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
           <state>$PROJ_DIR$\Libraries\CMSIS\Include</state>
           <state>$PROJ_DIR$\Libraries\utilities</state>
+          <state>$PROJ_DIR$\..\..\components\drivers\spi</state>
           <state>$PROJ_DIR$\applications</state>
           <state>$PROJ_DIR$\..\..\components\finsh</state>
           <state>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat</state>
-          <state>$PROJ_DIR$\drivers</state>
+          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\posix</state>
           <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\arch\include</state>
         </option>
         <option>
@@ -1247,7 +1248,7 @@
           <state>$PROJ_DIR$\Libraries\drivers</state>
           <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include</state>
           <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src</state>
-          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\posix</state>
+          <state>$PROJ_DIR$\drivers</state>
           <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\ipv4</state>
           <state>$PROJ_DIR$\.</state>
           <state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m7</state>
@@ -1255,10 +1256,11 @@
           <state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
           <state>$PROJ_DIR$\Libraries\CMSIS\Include</state>
           <state>$PROJ_DIR$\Libraries\utilities</state>
+          <state>$PROJ_DIR$\..\..\components\drivers\spi</state>
           <state>$PROJ_DIR$\applications</state>
           <state>$PROJ_DIR$\..\..\components\finsh</state>
           <state>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat</state>
-          <state>$PROJ_DIR$\drivers</state>
+          <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\posix</state>
           <state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\arch\include</state>
         </option>
         <option>
@@ -1898,7 +1900,7 @@
       <name>$PROJ_DIR$\drivers\drv_uart.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\drivers\hyper_flash_boot.c</name>
+      <name>$PROJ_DIR$\drivers\drv_cache.c</name>
     </file>
     <file>
       <name>$PROJ_DIR$\drivers\drv_sdram.c</name>
@@ -1907,7 +1909,13 @@
       <name>$PROJ_DIR$\drivers\drv_pin.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\drivers\drv_hp_rtc.c</name>
+      <name>$PROJ_DIR$\drivers\drv_rtc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\drivers\drv_spi_bus.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\drivers\hyper_flash_boot.c</name>
     </file>
     <file>
       <name>$PROJ_DIR$\drivers\drv_eth.c</name>
@@ -2227,6 +2235,12 @@
     <file>
       <name>$PROJ_DIR$\..\..\components\drivers\serial\serial.c</name>
     </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\drivers\spi\spi_core.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\drivers\spi\spi_dev.c</name>
+    </file>
     <file>
       <name>$PROJ_DIR$\..\..\components\drivers\src\completion.c</name>
     </file>

bsp/imxrt1052-evk/rtconfig.h

@@ -8,9 +8,7 @@
 
 #define RT_NAME_MAX 8
 #define RT_ALIGN_SIZE 4
-/* RT_THREAD_PRIORITY_8 is not set */
 #define RT_THREAD_PRIORITY_32
-/* RT_THREAD_PRIORITY_256 is not set */
 #define RT_THREAD_PRIORITY_MAX 32
 #define RT_TICK_PER_SECOND 100
 #define RT_DEBUG
@@ -19,7 +17,6 @@
 #define RT_DEBUG_THREAD 0
 #define RT_USING_HOOK
 #define IDLE_THREAD_STACK_SIZE 256
-/* RT_USING_TIMER_SOFT is not set */
 
 /* Inter-Thread communication */
 
@@ -28,26 +25,19 @@
 #define RT_USING_EVENT
 #define RT_USING_MAILBOX
 #define RT_USING_MESSAGEQUEUE
-/* RT_USING_SIGNALS is not set */
 
 /* Memory Management */
 
-/* RT_USING_MEMPOOL is not set */
 #define RT_USING_MEMHEAP
-/* RT_USING_NOHEAP is not set */
-/* RT_USING_SMALL_MEM is not set */
-/* RT_USING_SLAB is not set */
 #define RT_USING_MEMHEAP_AS_HEAP
 #define RT_USING_HEAP
 
 /* Kernel Device Object */
 
 #define RT_USING_DEVICE
-/* RT_USING_INTERRUPT_INFO is not set */
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart1"
-/* RT_USING_MODULE is not set */
 #define ARCH_ARM
 #define ARCH_ARM_CORTEX_M
 #define ARCH_ARM_CORTEX_M7
@@ -60,7 +50,6 @@
 
 /* C++ features */
 
-/* RT_USING_CPLUSPLUS is not set */
 
 /* Command shell */
 
@@ -73,10 +62,8 @@
 #define FINSH_THREAD_PRIORITY 20
 #define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_CMD_SIZE 80
-/* FINSH_USING_AUTH is not set */
 #define FINSH_USING_MSH
 #define FINSH_USING_MSH_DEFAULT
-/* FINSH_USING_MSH_ONLY is not set */
 
 /* Device virtual file system */
 
@@ -91,67 +78,39 @@
 
 #define RT_DFS_ELM_CODE_PAGE 437
 #define RT_DFS_ELM_WORD_ACCESS
-/* RT_DFS_ELM_USE_LFN_0 is not set */
-/* RT_DFS_ELM_USE_LFN_1 is not set */
-/* RT_DFS_ELM_USE_LFN_2 is not set */
 #define RT_DFS_ELM_USE_LFN_3
 #define RT_DFS_ELM_USE_LFN 3
 #define RT_DFS_ELM_MAX_LFN 255
 #define RT_DFS_ELM_DRIVES 2
 #define RT_DFS_ELM_MAX_SECTOR_SIZE 512
-/* RT_DFS_ELM_USE_ERASE is not set */
 #define RT_DFS_ELM_REENTRANT
 #define RT_USING_DFS_DEVFS
-/* RT_USING_DFS_NET is not set */
-/* RT_USING_DFS_ROMFS is not set */
-/* RT_USING_DFS_RAMFS is not set */
-/* RT_USING_DFS_UFFS is not set */
-/* RT_USING_DFS_JFFS2 is not set */
-/* RT_USING_DFS_NFS is not set */
 
 /* Device Drivers */
 
 #define RT_USING_DEVICE_IPC
 #define RT_USING_SERIAL
-/* RT_USING_CAN is not set */
-/* RT_USING_HWTIMER is not set */
-/* RT_USING_CPUTIME is not set */
 #define RT_USING_I2C
 #define RT_USING_I2C_BITOPS
 #define RT_USING_PIN
-/* RT_USING_MTD_NOR is not set */
-/* RT_USING_MTD_NAND is not set */
 #define RT_USING_RTC
-/* RT_USING_SOFT_RTC is not set */
-/* RTC_SYNC_USING_NTP is not set */
 #define RT_USING_SDIO
-/* RT_USING_SPI is not set */
-/* RT_USING_WDT is not set */
-/* RT_USING_WIFI is not set */
+#define RT_USING_SPI
 
 /* Using USB */
 
-/* RT_USING_USB_HOST is not set */
-/* RT_USING_USB_DEVICE is not set */
 
 /* POSIX layer and C standard library */
 
 #define RT_USING_LIBC
-/* RT_USING_PTHREADS is not set */
-/* RT_USING_POSIX is not set */
-/* HAVE_SYS_SIGNALS is not set */
 
 /* Network stack */
 
 /* light weight TCP/IP stack */
 
 #define RT_USING_LWIP
-/* RT_USING_LWIP141 is not set */
 #define RT_USING_LWIP202
-/* RT_USING_LWIP_IPV6 is not set */
-/* RT_LWIP_IGMP is not set */
 #define RT_LWIP_ICMP
-/* RT_LWIP_SNMP is not set */
 #define RT_LWIP_DNS
 #define RT_LWIP_DHCP
 #define IP_SOF_BROADCAST 1
@@ -164,8 +123,6 @@
 #define RT_LWIP_MSKADDR "255.255.255.0"
 #define RT_LWIP_UDP
 #define RT_LWIP_TCP
-/* RT_LWIP_RAW is not set */
-/* RT_LWIP_PPP is not set */
 #define RT_MEMP_NUM_NETCONN 8
 #define RT_LWIP_PBUF_NUM 16
 #define RT_LWIP_RAW_PCB_NUM 4
@@ -180,33 +137,24 @@
 #define RT_LWIP_ETHTHREAD_PRIORITY 12
 #define RT_LWIP_ETHTHREAD_STACKSIZE 1024
 #define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
-/* RT_LWIP_REASSEMBLY_FRAG is not set */
 #define LWIP_NETIF_STATUS_CALLBACK 1
 #define SO_REUSE 1
 #define LWIP_SO_RCVTIMEO 1
 #define LWIP_SO_SNDTIMEO 1
 #define LWIP_SO_RCVBUF 1
-/* RT_LWIP_NETIF_LOOPBACK is not set */
 #define LWIP_NETIF_LOOPBACK 0
 
 /* Modbus master and slave stack */
 
-/* RT_USING_MODBUS is not set */
-/* LWIP_USING_DHCPD is not set */
 
 /* VBUS(Virtual Software BUS) */
 
-/* RT_USING_VBUS is not set */
 
 /* Utilities */
 
-/* RT_USING_LOGTRACE is not set */
-/* RT_USING_RYM is not set */
 
 /* ARM CMSIS */
 
-/* RT_USING_CMSIS_OS is not set */
-/* RT_USING_RTT_CMSIS is not set */
 
 /* RT-Thread online packages */
 
@@ -214,72 +162,75 @@
 
 /* RT-Thread GUI Engine */
 
-/* PKG_USING_GUIENGINE is not set */
-/* PKG_USING_PERSIMMON is not set */
-/* PKG_USING_LWEXT4 is not set */
-/* PKG_USING_PARTITION is not set */
-/* PKG_USING_SQLITE is not set */
-/* PKG_USING_RTI is not set */
 
 /* IoT - internet of things */
 
-/* PKG_USING_PAHOMQTT is not set */
-/* PKG_USING_WEBCLIENT is not set */
-/* PKG_USING_MONGOOSE is not set */
-/* PKG_USING_WEBTERMINAL is not set */
-/* PKG_USING_CJSON is not set */
-/* PKG_USING_LJSON is not set */
-/* PKG_USING_EZXML is not set */
-/* PKG_USING_NANOPB is not set */
-/* PKG_USING_GAGENT_CLOUD is not set */
 
 /* Wi-Fi */
 
 /* Marvell WiFi */
 
-/* PKG_USING_WLANMARVELL is not set */
 
 /* Wiced WiFi */
 
-/* PKG_USING_WLAN_WICED is not set */
-/* PKG_USING_COAP is not set */
-/* PKG_USING_NOPOLL is not set */
-/* PKG_USING_NETUTILS is not set */
 
 /* security packages */
 
-/* PKG_USING_MBEDTLS is not set */
-/* PKG_USING_libsodium is not set */
-/* PKG_USING_TINYCRYPT is not set */
 
 /* language packages */
 
-/* PKG_USING_JERRYSCRIPT is not set */
-/* PKG_USING_MICROPYTHON is not set */
 
 /* multimedia packages */
 
-/* PKG_USING_OPENMV is not set */
 
 /* tools packages */
 
-/* PKG_USING_CMBACKTRACE is not set */
-/* PKG_USING_EASYLOGGER is not set */
-/* PKG_USING_SYSTEMVIEW is not set */
-/* PKG_USING_IPERF is not set */
 
 /* miscellaneous packages */
 
-/* PKG_USING_FASTLZ is not set */
-/* PKG_USING_MINILZO is not set */
-/* PKG_USING_QUICKLZ is not set */
 
 /* example package: hello */
 
-/* PKG_USING_HELLO is not set */
-/* PKG_USING_MULTIBUTTON is not set */
 #define SOC_IMXRT1052
+#define BOARD_RT1050_EVK
+
+/* RT1050 Bsp Config */
+
+/* Select uart drivers */
+
 #define RT_USING_UART1
-#define RT_USING_HP_RTC
+
+/* Select spi bus and dev drivers */
+
+#define LPSPI_CLK_SOURCE_FROM_PLL3PFD1
+#define LPSPI_CLK_SOURCE 0
+#define LPSPI_CLK_SOURCE_DIVIDER 8
+#define RT_USING_SPIBUS4
+#define LPSPI4_SCK_GPIO_1
+#define LPSPI4_SDO_GPIO_1
+#define LPSPI4_SDI_GPIO_1
+
+/* Select iic bus drivers */
+
+#define RT_USING_HW_I2C1
+#define HW_I2C1_BADURATE_100kHZ
+
+/* Select lcd driver */
+
+/* Notice: Evk Board para: 480*272 4 4 8 2 40 10 106 45 */
+
+#define RT_USING_LCD
+#define LCD_WIDTH 480
+#define LCD_HEIGHT 272
+#define LCD_HFP 4
+#define LCD_VFP 4
+#define LCD_HBP 8
+#define LCD_VBP 2
+#define LCD_HSW 40
+#define LCD_VSW 10
+#define LCD_BL_PIN 106
+#define LCD_RST_PIN 45
+#define RT_USING_SDRAM
+#define RT_USING_RTC_HP
 
 #endif

bsp/imxrt1052-evk/rtconfig.py

@@ -18,7 +18,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil_v5'
 elif CROSS_TOOL == 'iar':
     PLATFORM 	= 'iar'
-    IAR_PATH    = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
+    EXEC_PATH    = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
 
 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -43,7 +43,7 @@ if PLATFORM == 'gcc':
     DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections'
     CFLAGS = DEVICE + ' -std=c99 -Wall -DUSE_HAL_DRIVER -D__ASSEMBLY__ -D__FPU_PRESENT -eentry'
     AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
-    LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=imxrt1052_sdram.map,-cref,-u,Reset_Handler -T ./Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld'
+    LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread-imxrt-gcc.map,-cref,-u,Reset_Handler -T ./Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld'
 
     CPATH = ''
     LPATH = ''
@@ -55,7 +55,7 @@ if PLATFORM == 'gcc':
     else:
         CFLAGS += ' -O2 -Os'
 
-    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+    POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
 
     # module setting 
     CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
@@ -77,7 +77,7 @@ elif PLATFORM == 'armcc':
     DEVICE = ' --cpu Cortex-M7.fp.sp'
     CFLAGS = DEVICE + ' --apcs=interwork'
     AFLAGS = DEVICE
-    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-imxrt.map --scatter ./Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf'
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-imxrt-mdk.map --scatter ./Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf'
 
     CFLAGS += ' --diag_suppress=66,1296,186'
     CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
@@ -121,7 +121,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --cpu=Cortex-M7'
     CFLAGS += ' -e'
     CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
     CFLAGS += ' -Ol'
     CFLAGS += ' --use_c++_inline'
 
@@ -137,5 +137,5 @@ elif PLATFORM == 'iar':
     LFLAGS += ' --redirect _Scanf=_ScanfSmall'
     LFLAGS += ' --entry __iar_program_start'
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = ''

bsp/lpc176x/rtconfig.py

@@ -16,7 +16,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
+	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
 
 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -105,7 +105,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --cpu=Cortex-M3' 
     CFLAGS += ' -e' 
     CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
     CFLAGS += ' -Ol'    
     CFLAGS += ' --use_c++_inline'
         
@@ -120,6 +120,6 @@ elif PLATFORM == 'iar':
     LFLAGS += ' --semihosting' 
     LFLAGS += ' --entry __iar_program_start'    
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     RT_USING_MINILIBC = False
     POST_ACTION = ''

bsp/lpc43xx/M0/rtconfig.py

@@ -25,7 +25,7 @@ elif CROSS_TOOL == 'keil':
     EXEC_PATH = r'D:/Keil'
 elif CROSS_TOOL == 'iar':
     PLATFORM = 'iar'
-    IAR_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0'
+    EXEC_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0'
 
 if os.getenv('RTT_EXEC_PATH'):
         EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -113,7 +113,7 @@ elif PLATFORM == 'iar':
     else:
         CFLAGS += ' --cpu=Cortex-M0'
     CFLAGS += ' -e' 
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
     CFLAGS += ' -Ol'    
     CFLAGS += ' --use_c++_inline'
         
@@ -132,5 +132,5 @@ elif PLATFORM == 'iar':
     LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
     LFLAGS += ' --entry __iar_program_start'    
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = ''

bsp/lpc43xx/M4/rtconfig.py

@@ -29,7 +29,7 @@ elif CROSS_TOOL == 'keil':
     EXEC_PATH = r'D:/Keil'
 elif CROSS_TOOL == 'iar':
     PLATFORM = 'iar'
-    IAR_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0'
+    EXEC_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 6.0'
 
 if os.getenv('RTT_EXEC_PATH'):
         EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -117,7 +117,7 @@ elif PLATFORM == 'iar':
     else:
         CFLAGS += ' --cpu=Cortex-M0'
     CFLAGS += ' -e' 
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
     CFLAGS += ' -Ol'    
     CFLAGS += ' --use_c++_inline'
         
@@ -136,5 +136,5 @@ elif PLATFORM == 'iar':
     LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
     LFLAGS += ' --entry __iar_program_start'    
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = ''

bsp/lpc824/rtconfig.py

@@ -19,7 +19,7 @@ elif CROSS_TOOL == 'keil':
     EXEC_PATH 	= 'C:/keil_v5'
 elif CROSS_TOOL == 'iar':
     PLATFORM 	= 'iar'
-    IAR_PATH    = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
+    EXEC_PATH    = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
 
 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -105,7 +105,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --cpu=Cortex-M0'
     CFLAGS += ' -e'
     CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
     CFLAGS += ' -Ol'
     CFLAGS += ' --use_c++_inline'
 
@@ -121,5 +121,5 @@ elif PLATFORM == 'iar':
     LFLAGS += ' --redirect _Scanf=_ScanfSmall'
     LFLAGS += ' --entry __iar_program_start'
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = ''

bsp/m16c62p/rtconfig.py

@@ -14,7 +14,7 @@ if  CROSS_TOOL == 'gcc':
 	EXEC_PATH 	= 'C:/Program Files/Renesas/Hew/Tools/KPIT Cummins/GNUM16CM32C-ELF/v11.01/m32c-elf/bin'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench Evaluation 6.0'
+	EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench Evaluation 6.0'
 #	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench Evaluation 6.0'
 elif CROSS_TOOL == 'keil':
     print('================ERROR============================')
@@ -65,16 +65,14 @@ elif PLATFORM == 'iar':
     
     DEVICE = '--cpu M16C'
     
-    EXEC_PATH = IAR_PATH + '/m16c/bin'
-    
     AFLAGS = '-s+'
 #    AFLAGS += ' -M<>' 
     AFLAGS += ' -w+' 
     AFLAGS += ' -r' 
-    AFLAGS += ' -I"' + IAR_PATH + '/m16c/INC"'
+    AFLAGS += ' -I"' + EXEC_PATH + '/m16c/INC"'
         
     LFLAGS = '-xms'
-    LFLAGS += ' -I"' + IAR_PATH + '/m16c/LIB"' 
+    LFLAGS += ' -I"' + EXEC_PATH + '/m16c/LIB"' 
     LFLAGS += ' -rt' 
     LFLAGS += ' -s __program_start' 
     LFLAGS += ' -D_CSTACK_SIZE=80' 
@@ -82,7 +80,7 @@ elif PLATFORM == 'iar':
     LFLAGS += ' -D_DATA16_HEAP_SIZE=1000' 
     LFLAGS += ' -D_FAR_HEAP_SIZE=400'
     LFLAGS += ' -D_DATA20_HEAP_SIZE=400'
-    LFLAGS += ' "' + IAR_PATH + '/m16c/LIB/CLIB/clm16cfnffwc.r34"' 
+    LFLAGS += ' "' + EXEC_PATH + '/m16c/LIB/CLIB/clm16cfnffwc.r34"' 
     LFLAGS += ' -e_small_write=_formatted_write' 
     LFLAGS += ' -e_medium_read=_formatted_read'
     
@@ -95,13 +93,15 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --debug' 
     CFLAGS += ' -e' 
     CFLAGS += ' --align_func 1' 
-    CFLAGS += ' -I"' + IAR_PATH + '/m16c/INC"'
-    CFLAGS += ' -I"' + IAR_PATH + '/m16c/INC/CLIB"' 
+    CFLAGS += ' -I"' + EXEC_PATH + '/m16c/INC"'
+    CFLAGS += ' -I"' + EXEC_PATH + '/m16c/INC/CLIB"' 
     CFLAGS += ' -Ol' 
     CFLAGS += ' --no_cse' 
     CFLAGS += ' --no_unroll' 
     CFLAGS += ' --no_inline' 
     CFLAGS += ' --no_code_motion' 
     CFLAGS += ' --no_tbaa'    
+	
+	EXEC_PATH = EXEC_PATH + '/m16c/bin'
    
     POST_ACTION = ''

bsp/mb9bf500r/rtconfig.py

@@ -19,7 +19,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
+	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
 
 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -102,7 +102,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --cpu=Cortex-M3' 
     CFLAGS += ' -e' 
     CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
     CFLAGS += ' -Ol'    
     CFLAGS += ' --use_c++_inline'    
         
@@ -112,11 +112,11 @@ elif PLATFORM == 'iar':
     AFLAGS += ' -r' 
     AFLAGS += ' --cpu Cortex-M3' 
     AFLAGS += ' --fpu None' 
-    AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"'
+    AFLAGS += ' -I"' + EXEC_PATH + '/arm/INC"'
 
     LFLAGS = ' --config mb9bf500r.icf'
     LFLAGS += ' --semihosting' 
     LFLAGS += ' --entry __iar_program_start'    
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec'

bsp/mb9bf506r/rtconfig.py

@@ -19,7 +19,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
+	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
 
 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -101,7 +101,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --cpu=Cortex-M3' 
     CFLAGS += ' -e' 
     CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
     CFLAGS += ' -Ol'    
     CFLAGS += ' --use_c++_inline'    
         
@@ -111,11 +111,11 @@ elif PLATFORM == 'iar':
     AFLAGS += ' -r' 
     AFLAGS += ' --cpu Cortex-M3' 
     AFLAGS += ' --fpu None' 
-    AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"'
+    AFLAGS += ' -I"' + EXEC_PATH + '/arm/INC"'
 
     LFLAGS = ' --config rtthread-mb9bf506.icf'
     LFLAGS += ' --semihosting' 
     LFLAGS += ' --entry __iar_program_start'    
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' 

bsp/mb9bf618s/rtconfig.py

@@ -24,7 +24,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= r'E:/Keil'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= r'C:\Program Files\IAR Systems\Embedded Workbench 6.0 Evaluation'
+	EXEC_PATH 	= r'C:\Program Files\IAR Systems\Embedded Workbench 6.0 Evaluation'
 
 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -106,7 +106,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --cpu=Cortex-M3' 
     CFLAGS += ' -e' 
     CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
     CFLAGS += ' -Ol'    
     CFLAGS += ' --use_c++_inline'    
         
@@ -116,11 +116,11 @@ elif PLATFORM == 'iar':
     AFLAGS += ' -r' 
     AFLAGS += ' --cpu Cortex-M3' 
     AFLAGS += ' --fpu None' 
-    AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"'
+    AFLAGS += ' -I"' + EXEC_PATH + '/arm/INC"'
 
     LFLAGS = ' --config rtthread-fm3.icf'
     LFLAGS += ' --semihosting' 
     LFLAGS += ' --entry __iar_program_start'    
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' 

bsp/nuvoton_m05x/rtconfig.py

@@ -103,7 +103,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --cpu=Cortex-M0' 
     CFLAGS += ' -e' 
     CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
     CFLAGS += ' -Ol'    
     CFLAGS += ' --use_c++_inline'
         
@@ -119,5 +119,5 @@ elif PLATFORM == 'iar':
     LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
     LFLAGS += ' --entry __iar_program_start'    
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = ''

bsp/nuvoton_m451/rtconfig.py

@@ -105,7 +105,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --cpu=Cortex-M4' 
     CFLAGS += ' -e' 
     CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
     CFLAGS += ' -Ol'    
     CFLAGS += ' --use_c++_inline'
         
@@ -121,5 +121,5 @@ elif PLATFORM == 'iar':
     LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
     LFLAGS += ' --entry __iar_program_start'    
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = ''

bsp/nuvoton_nuc472/Libraries/Device/Nuvoton/NUC472_442/Source/GCC/startup.c

@@ -150,9 +150,9 @@ extern unsigned char  _sdata;
 // End address for the .data section// defined in linker script
 extern unsigned char  _edata;
 // Begin address for the .bss section// defined in linker script
-extern unsigned char  __bss_start__;
+extern unsigned char  __bss_start;
 // End address for the .bss section// defined in linker script
-extern unsigned char  __bss_end__;
+extern unsigned char  __bss_end;
 
 extern int entry(void);
 
@@ -333,7 +333,7 @@ pHandler g_pfnVectors[] =
 void _start()
 {
     memcpy(&_sdata, &_sidata, &_edata - &_sdata);
-    memset(&__bss_start__, 0, &__bss_end__ - &__bss_start__);
+    memset(&__bss_start, 0, &__bss_end - &__bss_start);
 }
 
 static void Reset_Handler(void)

bsp/nuvoton_nuc472/README.md

@@ -3,7 +3,7 @@
     NuTiny-EVB-NUC472
 
 ## note:
-    support the GCC MDK5 IAR
+    support the GCC MDK4 MDK5 IAR
 
 **TODO**
 

bsp/nuvoton_nuc472/drivers/board.c

@@ -22,7 +22,7 @@ extern int Image$$RW_IRAM1$$ZI$$Limit;
 #elif __ICCARM__
 #pragma section="HEAP"
 #else
-extern int __bss_end__;
+extern int __bss_end;
 #endif
 
 /**
@@ -80,7 +80,7 @@ void rt_hw_board_init(void)
     rt_system_heap_init(__segment_end("HEAP"), (void*)SRAM_END);
 #else
     /* init memory system */
-    rt_system_heap_init((void*)&__bss_end__, (void*)SRAM_END);
+    rt_system_heap_init((void*)&__bss_end, (void*)SRAM_END);
 #endif
 #endif /* RT_USING_HEAP */
 

bsp/nuvoton_nuc472/drivers/nuc472_eth.c

@@ -181,7 +181,7 @@ static void init_rx_desc(rt_nuc472_emac_t emac)
         emac->rx_desc[i].status1 = OWNERSHIP_EMAC;
         emac->rx_desc[i].buf = &emac->rx_buf[i][0];
         emac->rx_desc[i].status2 = 0;
-        emac->rx_desc[i].next = &emac->rx_desc[(i + 1) % TX_DESCRIPTOR_NUM];
+        emac->rx_desc[i].next = &emac->rx_desc[(i + 1) % RX_DESCRIPTOR_NUM];
     }
     emac_base->RXDSA = (unsigned int)&emac->rx_desc[0];
     return;
@@ -205,8 +205,8 @@ static void set_mac_addr(rt_nuc472_emac_t emac, rt_uint8_t *addr)
 
 void EMAC_init(rt_nuc472_emac_t emac, rt_uint8_t *mac_addr)
 {
+    EMAC_T *emac_base = emac->emac_base;  
     RT_ASSERT(emac->dev_addr != RT_NULL);
-    EMAC_T *emac_base = emac->emac_base;
 
     CLK_EnableModuleClock(EMAC_MODULE);
 
@@ -445,12 +445,12 @@ rt_err_t rt_nuc472_emac_tx(rt_device_t dev, struct pbuf* p)
 struct pbuf *rt_nuc472_emac_rx(rt_device_t dev)
 {
     rt_nuc472_emac_t emac = (rt_nuc472_emac_t)dev;
+    unsigned int status;
     struct pbuf* p;
 
     /* init p pointer */
     p = RT_NULL;
 
-    unsigned int status;
     status = emac->cur_rx_desc_ptr->status1;
 
     if(status & OWNERSHIP_EMAC)

bsp/nuvoton_nuc472/ldscripts/libs.ld

@@ -1,8 +0,0 @@
-
-/*
- * Placeholder to list other libraries required by the application.
- 
-GROUP(
-)
-
- */

bsp/nuvoton_nuc472/ldscripts/mem.ld

@@ -1,25 +0,0 @@
-/*
- * Memory Spaces Definitions.
- *
- * Need modifying for a specific board. 
- *   FLASH.ORIGIN: starting address of flash
- *   FLASH.LENGTH: length of flash
- *   RAM.ORIGIN: starting address of RAM bank 0
- *   RAM.LENGTH: length of RAM bank 0
- *
- * The values below can be addressed in further linker scripts
- * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'.
- */
-
-MEMORY
-{
-  RAM (xrw)  : ORIGIN = 0x20000000, LENGTH =  64K
-  FLASH (rx) : ORIGIN = 0x00000000, LENGTH =  512K /*4K*/
-}
-
-/*
- * For external ram use something like:
-
-  RAM (xrw) : ORIGIN = 0x68000000, LENGTH = 8K
-
- */

bsp/nuvoton_nuc472/ldscripts/sections.ld

@@ -1,129 +1,32 @@
 /*
- * Default linker script for Cortex-M 
- * 
- * To make use of the multi-region initialisations, define
- * OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS for the _startup.c file.
+ * linker script for STM32F10x with GNU ld
+ * bernard.xiong 2009-10-14
  */
 
-/*
- * The '__stack' definition is required by crt0, do not remove it.
- */
-__stack = ORIGIN(RAM) + LENGTH(RAM);
-
-_estack = __stack; 	/* STM specific definition */
-
-/*
- * Default stack sizes.
- * These are used by the startup in order to allocate stacks 
- * for the different modes.
- */
-
-__Main_Stack_Size = 1024 ;
-
-PROVIDE ( _Main_Stack_Size = __Main_Stack_Size ) ;
-
-__Main_Stack_Limit = __stack  - __Main_Stack_Size ;
-
-/* "PROVIDE" allows to easily override these values from an 
- * object file or the command line. */
-PROVIDE ( _Main_Stack_Limit = __Main_Stack_Limit ) ;
-
-/*
- * There will be a link error if there is not this amount of 
- * RAM free at the end. 
- */
-_Minimum_Stack_Size = 256 ;
-
-/*
- * Default heap definitions.
- * The heap start immediately after the last statically allocated 
- * .sbss/.noinit section, and extends up to the main stack limit.
- */
-PROVIDE ( _Heap_Begin = _end_noinit ) ;
-PROVIDE ( _Heap_Limit = __stack - __Main_Stack_Size ) ;
-
-/* 
- * The entry point is informative, for debuggers and simulators,
- * since the Cortex-M vector points to it anyway.
- */
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x00000000, LENGTH = 512k /* 128K sram */
+    DATA (rw) : ORIGIN = 0x20000000, LENGTH =  64k /* 512KB flash */
+}
 ENTRY(_start)
-
-
-/* Sections Definitions */
+_system_stack_size = 0x400;
 
 SECTIONS
 {
-    /*
-     * For Cortex-M devices, the beginning of the startup code is stored in
-     * the .isr_vector section, which goes to FLASH. 
-     */
-    .isr_vector : ALIGN(4)
-    {
-        FILL(0xFF)
-        
-        __vectors_start = ABSOLUTE(.) ;
-        __vectors_start__ = ABSOLUTE(.) ; /* STM specific definition */
-        KEEP(*(.isr_vector))     	/* Interrupt vectors */
-        
-		KEEP(*(.cfmconfig))			/* Freescale configuration words */   
-		     
-        /* 
-         * This section is here for convenience, to store the
-         * startup code at the beginning of the flash area, hoping that
-         * this will increase the readability of the listing.
-         */
-        *(.after_vectors .after_vectors.*)	/* Startup code and ISR */
-
-    } >FLASH
-
-    .inits : ALIGN(4)
+    .text :
     {
-        /* 
-         * Memory regions initialisation arrays.
-         *
-         * Thee are two kinds of arrays for each RAM region, one for 
-         * data and one for bss. Each is iterrated at startup and the   
-         * region initialisation is performed.
-         * 
-         * The data array includes:
-         * - from (LOADADDR())
-         * - region_begin (ADDR())
-         * - region_end (ADDR()+SIZEOF())
-         *
-         * The bss array includes:
-         * - region_begin (ADDR())
-         * - region_end (ADDR()+SIZEOF())
-         *
-         * WARNING: It is mandatory that the regions are word aligned, 
-         * since the initialisation code works only on words.
-         */
-         
-        __data_regions_array_start = .;
-        
-        LONG(LOADADDR(.data));
-        LONG(ADDR(.data));
-        LONG(ADDR(.data)+SIZEOF(.data));
-        
-        __data_regions_array_end = .;
-        
-        __bss_regions_array_start = .;
-        
-        LONG(ADDR(.bss));
-        LONG(ADDR(.bss)+SIZEOF(.bss));
-        
-        
-        __bss_regions_array_end = .;
-
-        /* End of memory regions initialisation arrays. */
-    
-        /*
-         * These are the old initialisation sections, intended to contain
-         * naked code, with the prologue/epilogue added by crti.o/crtn.o
-         * when linking with startup files. The standalone startup code
-         * currently does not run these, better use the init arrays below.
-         */
-		KEEP(*(.init))
-		KEEP(*(.fini))
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
 
         /* section information for finsh shell */
         . = ALIGN(4);
@@ -135,7 +38,7 @@ SECTIONS
         KEEP(*(VSymTab))
         __vsymtab_end = .;
         . = ALIGN(4);
-    
+
         /* section information for initial. */
         . = ALIGN(4);
         __rt_init_start = .;
@@ -143,212 +46,67 @@ SECTIONS
         __rt_init_end = .;
         . = ALIGN(4);
 
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE = 0
 
-		/*
-         * The preinit code, i.e. an array of pointers to initialisation 
-         * functions to be performed before constructors.
-         */
-		PROVIDE_HIDDEN (__preinit_array_start = .);
-        
-        /*
-         * Used to run the SystemInit() before anything else.
-         */
-		KEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*))
-        
-        /* 
-         * Used for other platform inits.
-         */
-		KEEP(*(.preinit_array_platform .preinit_array_platform.*))
-        
-        /*
-         * The application inits. If you need to enforce some order in 
-         * execution, create new sections, as before.
-         */
-		KEEP(*(.preinit_array .preinit_array.*))
-
-		PROVIDE_HIDDEN (__preinit_array_end = .);
-
-		. = ALIGN(4);
-
-		/*
-         * The init code, i.e. an array of pointers to static constructors.
-         */
-		PROVIDE_HIDDEN (__init_array_start = .);
-		KEEP(*(SORT(.init_array.*)))
-		KEEP(*(.init_array))
-		PROVIDE_HIDDEN (__init_array_end = .);
-
-		. = ALIGN(4);
-
-		/*
-         * The fini code, i.e. an array of pointers to static destructors.
-         */
-		PROVIDE_HIDDEN (__fini_array_start = .);
-		KEEP(*(SORT(.fini_array.*)))
-		KEEP(*(.fini_array))
-		PROVIDE_HIDDEN (__fini_array_end = .);
-
-    } >FLASH
-
-    /*
-     * For some STRx devices, the beginning of the startup code
-     * is stored in the .flashtext section, which goes to FLASH.
-     */
-    .flashtext : ALIGN(4)
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
     {
-        *(.flashtext .flashtext.*)	/* Startup code */
-    } >FLASH
- 
-    
-    /*
-     * The program code is stored in the .text section, 
-     * which goes to FLASH.
-     */
-    .text : ALIGN(4)
-    {
-        *(.text .text.*)			/* all remaining code */
- 
- 		/* read-only data (constants) */
-        *(.rodata .rodata.* .constdata .constdata.*) 		
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
 
-        *(vtable)					/* C++ virtual tables */
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
 
-		KEEP(*(.eh_frame*))
+    /* .data section which is used for initialized data */
 
-		/*
-		 * Stub sections generated by the linker, to glue together 
-		 * ARM and Thumb code. .glue_7 is used for ARM code calling 
-		 * Thumb code, and .glue_7t is used for Thumb code calling 
-		 * ARM code. Apparently always generated by the linker, for some
-		 * architectures, so better leave them here.
-		 */
-        *(.glue_7)
-        *(.glue_7t)
-        
-    	KEEP (*(.init))
-    	KEEP (*(.fini))
-        
-    } >FLASH
-
-	/* ARM magic sections */
-	.ARM.extab : ALIGN(4)
-   	{
-       *(.ARM.extab* .gnu.linkonce.armextab.*)
-   	} > FLASH
-   	
-    . = ALIGN(4);
-   	__exidx_start = .;   	
-   	.ARM.exidx : ALIGN(4)
-   	{
-       *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-   	} > FLASH
-   	__exidx_end = .;
-   	
-    . = ALIGN(4);
-    _etext = .;
-    __etext = .;
-    
-    /* MEMORY_ARRAY */
-    /*
-    .ROarraySection :
+    .data : AT (_sidata)
     {
-     	*(.ROarraySection .ROarraySection.*)                          
-    } >MEMORY_ARRAY
-    */
-    
-	/* 
-     * This address is used by the startup code to 
-     * initialise the .data section.
-     */
-    _sidata = LOADADDR(.data);
-
-    /*
-     * The initialised data section.
-     *
-     * The program executes knowing that the data is in the RAM
-     * but the loader puts the initial values in the FLASH (inidata).
-     * It is one task of the startup to copy the initial values from 
-     * FLASH to RAM.
-     */
-    .data : ALIGN(4)
-    {
-    	FILL(0xFF)
-        /* This is used by the startup code to initialise the .data section */
-        _sdata = . ;        	/* STM specific definition */
-        __data_start__ = . ;
-		*(.data_begin .data_begin.*)
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
 
-		*(.data .data.*)
-		
-		*(.data_end .data_end.*)
-	    . = ALIGN(4);
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
 
-	    /* This is used by the startup code to initialise the .data section */
-        _edata = . ;        	/* STM specific definition */
-        __data_end__ = . ;
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
 
-    } >RAM AT>FLASH
-    
-    /*
-     * The uninitialised data sections. NOLOAD is used to avoid
-     * the "section `.bss' type changed to PROGBITS" warning
-     */
+    .stack : 
+    {
+	_sstack = .;
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >DATA
 
-    /* The primary uninitialised data section. */
-    .bss (NOLOAD) : ALIGN(4)
+    __bss_start = .;
+    .bss :
     {
-        __bss_start__ = .;     	/* standard newlib definition */
-        _sbss = .;              /* STM specific definition */
-        *(.bss_begin .bss_begin.*)
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
 
-        *(.bss .bss.*)
+        *(.bss)
+        *(.bss.*)
         *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
         
-        *(.bss_end .bss_end.*)
-	    . = ALIGN(4);
-        __bss_end__ = .;        /* standard newlib definition */
-        _ebss = . ;             /* STM specific definition */
-    } >RAM
-    
-    .noinit (NOLOAD) : ALIGN(4)
-    {
-        _noinit = .;
-        
-        *(.noinit .noinit.*) 
-        
-         . = ALIGN(4) ;
-        _end_noinit = .;   
-    } > RAM
-    
-    /* Mandatory to be word aligned, _sbrk assumes this */
-    PROVIDE ( end = _end_noinit ); /* was _ebss */
-    PROVIDE ( _end = _end_noinit );
-    PROVIDE ( __end = _end_noinit );
-    PROVIDE ( __end__ = _end_noinit );
-    
-    /*
-     * Used for validation only, do not allocate anything here!
-     *
-     * This is just to check that there is enough RAM left for the Main
-     * stack. It should generate an error if it's full.
-     */
-    ._check_stack : ALIGN(4)
-    {
-        . = . + _Minimum_Stack_Size ;
-    } >RAM
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
 
-    /* After that there are only debugging sections. */
-    
-    /* This can remove the debugging information from the standard libraries */    
-    /* 
-    DISCARD :
-    {
-     libc.a ( * )
-     libm.a ( * )
-     libgcc.a ( * )
-     }
-     */
-  
     /* Stabs debugging sections.  */
     .stab          0 : { *(.stab) }
     .stabstr       0 : { *(.stabstr) }
@@ -357,11 +115,9 @@ SECTIONS
     .stab.index    0 : { *(.stab.index) }
     .stab.indexstr 0 : { *(.stab.indexstr) }
     .comment       0 : { *(.comment) }
-    /*
-     * DWARF debug sections.
+    /* DWARF debug sections.
      * Symbols in the DWARF debugging sections are relative to the beginning
-     * of the section so we begin them at 0.  
-     */
+     * of the section so we begin them at 0.  */
     /* DWARF 1 */
     .debug          0 : { *(.debug) }
     .line           0 : { *(.line) }
@@ -383,5 +139,5 @@ SECTIONS
     .debug_weaknames 0 : { *(.debug_weaknames) }
     .debug_funcnames 0 : { *(.debug_funcnames) }
     .debug_typenames 0 : { *(.debug_typenames) }
-    .debug_varnames  0 : { *(.debug_varnames) }    
+    .debug_varnames  0 : { *(.debug_varnames) }
 }

bsp/nuvoton_nuc472/project.uvproj

@@ -0,0 +1,1153 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+  <SchemaVersion>1.1</SchemaVersion>
+  <Header>### uVision Project, (C) Keil Software</Header>
+  <Targets>
+    <Target>
+      <TargetName>rtthread-nuc472</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>NUC472HI8AE</Device>
+          <Vendor>Nuvoton</Vendor>
+          <Cpu>IRAM(0x20000000-0x2000FFFF) IROM(0-0x7FFFF) CLOCK(84000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
+          <FlashUtilSpec />
+          <StartupFile>undefined</StartupFile>
+          <FlashDriverDll />
+          <DeviceId>0</DeviceId>
+          <RegisterFile />
+          <MemoryEnv />
+          <Cmp />
+          <Asm />
+          <Linker />
+          <OHString />
+          <InfinionOptionDll />
+          <SLE66CMisc />
+          <SLE66AMisc />
+          <SLE66LinkerMisc />
+          <SFDFile>SFD\Nuvoton\NUC400_v1.SFR</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath />
+          <IncludePath />
+          <LibPath />
+          <RegisterFilePath />
+          <DBRegisterFilePath />
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>template</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>1</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name />
+            <UserProg2Name />
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name />
+            <UserProg2Name />
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name />
+            <UserProg2Name />
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString />
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument />
+          <IncludeLibraryModules />
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments />
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments />
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments />
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments />
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>1</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>0</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+            <UsePdscDebugDescription>1</UsePdscDebugDescription>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>-1</TargetSelection>
+          <SimDlls>
+            <CpuDll />
+            <CpuDllArguments />
+            <PeripheralDll />
+            <PeripheralDllArguments />
+            <InitializationFile />
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll />
+            <CpuDllArguments />
+            <PeripheralDll />
+            <PeripheralDllArguments />
+            <InitializationFile />
+            <Driver />
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>0</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>0</Capability>
+            <DriverSelection>-1</DriverSelection>
+          </Flash1>
+          <bUseTDR>0</bUseTDR>
+          <Flash2 />
+          <Flash3 />
+          <Flash4 />
+          <pFcarmOut />
+          <pFcarmGrp />
+          <pFcArmRoot />
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName />
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
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+          <Files>
+            <File>
+              <FileName>tcpip.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\api\tcpip.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>def.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\def.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>dns.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\dns.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>inet_chksum.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>init.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\init.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>ip.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\ip.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>memp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\memp.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>netif.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\netif.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>pbuf.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\pbuf.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>raw.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\raw.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>stats.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\stats.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>sys.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\sys.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>tcp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\tcp.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>tcp_in.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\tcp_in.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>tcp_out.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\tcp_out.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>timeouts.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\timeouts.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>udp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\udp.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>ethernet.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\netif\ethernet.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>ethernetif.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>lowpan6.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>autoip.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>dhcp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>etharp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>icmp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>igmp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>ip4.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>ip4_addr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>ip4_frag.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+</Project>

bsp/nuvoton_nuc472/rtconfig.py

@@ -19,7 +19,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:\Keil_v5'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.5'
+	EXEC_PATH 	= 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.5'
 
 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -105,7 +105,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --cpu=Cortex-M4' 
     CFLAGS += ' -e' 
     CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
     CFLAGS += ' -Ol'    
     CFLAGS += ' --use_c++_inline'
         
@@ -121,5 +121,5 @@ elif PLATFORM == 'iar':
     LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
     LFLAGS += ' --entry __iar_program_start'    
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = ''

bsp/nuvoton_nuc472/template.uvproj

@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rtthread-nuc472</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>NUC472HI8AE</Device>
+          <Vendor>Nuvoton</Vendor>
+          <Cpu>IRAM(0x20000000-0x2000FFFF) IROM(0-0x7FFFF) CLOCK(84000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>undefined</StartupFile>
+          <FlashDriverDll></FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile></RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\Nuvoton\NUC400_v1.SFR</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>template</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>1</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments></SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments></TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>1</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>0</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+            <UsePdscDebugDescription>1</UsePdscDebugDescription>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>-1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver></Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>0</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>0</Capability>
+            <DriverSelection>-1</DriverSelection>
+          </Flash1>
+          <bUseTDR>0</bUseTDR>
+          <Flash2></Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>

bsp/nv32f100x/rtconfig.py

@@ -106,7 +106,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --cpu=Cortex-M0'
     CFLAGS += ' -e'
     CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
     CFLAGS += ' -Ol'
     CFLAGS += ' --use_c++_inline'
 
@@ -122,5 +122,5 @@ elif PLATFORM == 'iar':
     LFLAGS += ' --redirect _Scanf=_ScanfSmall'
     LFLAGS += ' --entry __iar_program_start'
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = ''

bsp/qemu-vexpress-a9/rtconfig.py

@@ -8,12 +8,8 @@ CROSS_TOOL='gcc'
 if os.getenv('RTT_CC'):
     CROSS_TOOL = os.getenv('RTT_CC')
 
-if  CROSS_TOOL == 'gcc':
-    PLATFORM    = 'gcc'
-    EXEC_PATH   = '/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
-elif CROSS_TOOL == 'keil':
-    PLATFORM    = 'armcc'
-    EXEC_PATH   = 'C:/Keil'
+PLATFORM    = 'gcc'
+EXEC_PATH   = '/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
 
 if os.getenv('RTT_EXEC_PATH'):
     EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -32,6 +28,7 @@ if PLATFORM == 'gcc':
     SIZE = PREFIX + 'size'
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY = PREFIX + 'objcopy'
+    STRIP = PREFIX + 'strip'
 
     DEVICE = ' -march=armv7-a -marm -msoft-float'
     CFLAGS = DEVICE + ' -Wall'
@@ -52,52 +49,13 @@ if PLATFORM == 'gcc':
     else:
         CFLAGS += ' -O2'
 
-    CXXFLAGS = CFLAGS
+    CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti'
+
+    M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC '
+    M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC'
+    M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\
+                                    ' -shared -fPIC -nostartfiles -nostdlib -static-libgcc'
+    M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
 
     POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
                   SIZE + ' $TARGET \n'
-
-elif PLATFORM == 'armcc':
-    # toolchains
-    CC = 'armcc'
-    CXX = 'armcc'
-    AS = 'armasm'
-    AR = 'armar'
-    LINK = 'armlink'
-    TARGET_EXT = 'axf'
-
-    DEVICE = ' --device DARMP'
-    CFLAGS = DEVICE + ' --apcs=interwork'
-    AFLAGS = DEVICE
-    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter rtthread.sct'
-
-    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
-    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
-
-    EXEC_PATH += '/arm/bin40/'
-
-    if BUILD == 'debug':
-        CFLAGS += ' -g -O0'
-        AFLAGS += ' -g'
-    else:
-        CFLAGS += ' -O2'
-
-    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
-
-elif PLATFORM == 'iar':
-    # toolchains
-    CC = 'iccarm'
-    AS = 'iasmarm'
-    AR = 'iarchive'
-    LINK = 'ilinkarm'
-    TARGET_EXT = 'out'
-
-    DEVICE = ' --cpu DARMP'
-
-    CFLAGS = ''
-    AFLAGS = ''
-    LFLAGS = ' --config rtthread.icf'
-
-    EXEC_PATH += '/arm/bin/'
-    RT_USING_MINILIBC = False
-    POST_ACTION = ''

bsp/sam7x/drivers/SConscript

@@ -7,7 +7,7 @@ src = Glob('*.c')
 if GetDepend('RT_USING_LWIP') == False:
     SrcRemove(src, 'sam7x_emac.c')
 if GetDepend('RT_USING_DFS') == False:
-    SrcRemove(src, 'ssd.c')
+    SrcRemove(src, 'sd.c')
 
 CPPPATH = [cwd]
 

bsp/stm32f0x/rtconfig.py

@@ -107,7 +107,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --cpu=Cortex-M0' 
     CFLAGS += ' -e' 
     CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
     CFLAGS += ' -Ol'    
     CFLAGS += ' --use_c++_inline'
         
@@ -123,5 +123,5 @@ elif PLATFORM == 'iar':
     LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
     LFLAGS += ' --entry __iar_program_start'    
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = ''

bsp/stm32f107/rtconfig.py

@@ -19,7 +19,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
+	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
 
 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -105,7 +105,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --cpu=Cortex-M3' 
     CFLAGS += ' -e' 
     CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
     CFLAGS += ' -Ol'    
         
     AFLAGS = ''
@@ -118,5 +118,5 @@ elif PLATFORM == 'iar':
     LFLAGS = ' --config stm32_rom.icf'
     LFLAGS += ' --entry __iar_program_start'    
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = ''

bsp/stm32f10x-HAL/applications/main.c

@@ -15,6 +15,6 @@
 
 int main(void)
 {
-  /* user app entry */
-  return 0;
+    /* user app entry */
+    return 0;
 }

bsp/stm32f10x-HAL/drivers/board.c

@@ -24,12 +24,9 @@
 
 /*@{*/
 
-
 void HAL_MspInit(void)
 {
-
     HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
     /* System interrupt init*/
     __HAL_RCC_AFIO_CLK_ENABLE();
     /* MemoryManagement_IRQn interrupt configuration */
@@ -46,16 +43,14 @@ void HAL_MspInit(void)
     HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
     /* SysTick_IRQn interrupt configuration */
     HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
-
     /**DISABLE: JTAG-DP Disabled and SW-DP Disabled**/
     __HAL_AFIO_REMAP_SWJ_NOJTAG();
 }
+
 void SystemClock_Config(void)
 {
-
     RCC_OscInitTypeDef RCC_OscInitStruct;
     RCC_ClkInitTypeDef RCC_ClkInitStruct;
-
     /**Initializes the CPU, AHB and APB busses clocks
       */
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
@@ -73,22 +68,17 @@ void SystemClock_Config(void)
     RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
     RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
     RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-
     RT_ASSERT(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) == HAL_OK);
-
     /**Configure the Systick interrupt time
       */
     HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / RT_TICK_PER_SECOND);
-
     /**Configure the Systick
       */
     HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
-
     /* SysTick_IRQn interrupt configuration */
     HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
 }
 
-
 /**
  * This is the timer interrupt service routine.
  *
@@ -97,10 +87,8 @@ void SysTick_Handler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
-
     HAL_IncTick();
     rt_tick_increase();
-
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -115,15 +103,10 @@ void rt_hw_board_init(void)
 #ifdef RT_USING_HEAP
     rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
 #endif
-
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
-
 #ifdef RT_USING_CONSOLE
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
-
 }
-
-/*@}*/

bsp/stm32f10x-HAL/drivers/board.h

@@ -197,7 +197,6 @@
 #define STM32_SRAM_SIZE 64
 //#define STM32F107xC
 #endif
-
 /* whether use board external SRAM memory */
 // <e>Use external SRAM memory on the board
 // 	<i>Enable External SRAM memory
@@ -209,10 +208,8 @@
 //		<i>Default: 0x68080000
 #define STM32_EXT_SRAM_END 0x68080000 /* the end address of external SRAM */
 // </e>
-
 // <o> Internal SRAM memory size[Kbytes] <8-64>
 //	<i>Default: 64
-
 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
 #ifdef __CC_ARM
 extern int Image$$RW_IRAM1$$ZI$$Limit;

bsp/stm32f10x-HAL/drivers/drv_gpio.c

@@ -18,7 +18,6 @@
 #include <board.h>
 #include <rtthread.h>
 #ifdef RT_USING_PIN
-
 #define __STM32_PIN(index, gpio, gpio_index) {index, GPIO##gpio##_CLK_ENABLE, GPIO##gpio, GPIO_PIN_##gpio_index}
 #define __STM32_PIN_DEFAULT  {-1, 0, 0, 0}
 
@@ -35,49 +34,49 @@ static void GPIOB_CLK_ENABLE(void)
 #endif
 }
 #if (STM32F10X_PIN_NUMBERS >36)
-    static void GPIOC_CLK_ENABLE(void)
-    {
-    #ifdef __HAL_RCC_GPIOC_CLK_ENABLE
-        __HAL_RCC_GPIOC_CLK_ENABLE();
-    #endif
-    }
-    #if (STM32F10X_PIN_NUMBERS >48)
+static void GPIOC_CLK_ENABLE(void)
+{
+#ifdef __HAL_RCC_GPIOC_CLK_ENABLE
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+#endif
+}
+#if (STM32F10X_PIN_NUMBERS >48)
 
-        static void GPIOD_CLK_ENABLE(void)
-        {
-        #ifdef __HAL_RCC_GPIOD_CLK_ENABLE
-            __HAL_RCC_GPIOD_CLK_ENABLE();
-        #endif
-        }
-        #if (STM32F10X_PIN_NUMBERS >64)
-            static void GPIOE_CLK_ENABLE(void)
-            {
-            #ifdef __HAL_RCC_GPIOE_CLK_ENABLE
-                __HAL_RCC_GPIOE_CLK_ENABLE();
-            #endif
-            }
-            #if (STM32F10X_PIN_NUMBERS >100)
-                static void GPIOF_CLK_ENABLE(void)
-                {
-                #ifdef __HAL_RCC_GPIOF_CLK_ENABLE
-                    __HAL_RCC_GPIOF_CLK_ENABLE();
-                #endif
-                }
-                static void GPIOG_CLK_ENABLE(void)
-                {
-                #ifdef __HAL_RCC_GPIOG_CLK_ENABLE
-                    __HAL_RCC_GPIOG_CLK_ENABLE();
-                #endif
-                }
-                static void GPIOH_CLK_ENABLE(void)
-                {
-                #ifdef __HAL_RCC_GPIOH_CLK_ENABLE
-                    __HAL_RCC_GPIOH_CLK_ENABLE();
-                #endif
-                }
-            #endif
-        #endif
-    #endif
+static void GPIOD_CLK_ENABLE(void)
+{
+#ifdef __HAL_RCC_GPIOD_CLK_ENABLE
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+#endif
+}
+#if (STM32F10X_PIN_NUMBERS >64)
+static void GPIOE_CLK_ENABLE(void)
+{
+#ifdef __HAL_RCC_GPIOE_CLK_ENABLE
+    __HAL_RCC_GPIOE_CLK_ENABLE();
+#endif
+}
+#if (STM32F10X_PIN_NUMBERS >100)
+static void GPIOF_CLK_ENABLE(void)
+{
+#ifdef __HAL_RCC_GPIOF_CLK_ENABLE
+    __HAL_RCC_GPIOF_CLK_ENABLE();
+#endif
+}
+static void GPIOG_CLK_ENABLE(void)
+{
+#ifdef __HAL_RCC_GPIOG_CLK_ENABLE
+    __HAL_RCC_GPIOG_CLK_ENABLE();
+#endif
+}
+static void GPIOH_CLK_ENABLE(void)
+{
+#ifdef __HAL_RCC_GPIOH_CLK_ENABLE
+    __HAL_RCC_GPIOH_CLK_ENABLE();
+#endif
+}
+#endif
+#endif
+#endif
 #endif
 /* STM32 GPIO driver */
 struct pin_index
@@ -549,7 +548,6 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
 const struct pin_index *get_pin(uint8_t pin)
 {
     const struct pin_index *index;
-
     if (pin < ITEM_NUM(pins))
     {
         index = &pins[pin];
@@ -560,20 +558,17 @@ const struct pin_index *get_pin(uint8_t pin)
     {
         index = RT_NULL;
     }
-
     return index;
 };
 
 void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
 {
     const struct pin_index *index;
-
     index = get_pin(pin);
     if (index == RT_NULL)
     {
         return;
     }
-
     HAL_GPIO_WritePin(index->gpio, index->pin, (GPIO_PinState)value);
 }
 
@@ -581,17 +576,13 @@ int stm32_pin_read(rt_device_t dev, rt_base_t pin)
 {
     int value;
     const struct pin_index *index;
-
     value = PIN_LOW;
-
     index = get_pin(pin);
     if (index == RT_NULL)
     {
         return value;
     }
-
     value = HAL_GPIO_ReadPin(index->gpio, index->pin);
-
     return value;
 }
 
@@ -599,22 +590,18 @@ void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 {
     const struct pin_index *index;
     GPIO_InitTypeDef GPIO_InitStruct;
-
     index = get_pin(pin);
     if (index == RT_NULL)
     {
         return;
     }
-
     /* GPIO Periph clock enable */
     index->rcc();
-
     /* Configure GPIO_InitStructure */
     GPIO_InitStruct.Pin = index->pin;
     GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-
     if (mode == PIN_MODE_OUTPUT)
     {
         /* output setting */
@@ -645,9 +632,9 @@ void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
         GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
         GPIO_InitStruct.Pull = GPIO_NOPULL;
     }
-
     HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
 }
+
 rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
 {
     int i;
@@ -660,6 +647,7 @@ rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
     }
     return -1;
 }
+
 rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
 {
     rt_int32_t mapindex = bit2bitno(pinbit);
@@ -675,7 +663,6 @@ rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     const struct pin_index *index;
     rt_base_t level;
     rt_int32_t irqindex = -1;
-
     index = get_pin(pin);
     if (index == RT_NULL)
     {
@@ -686,7 +673,6 @@ rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     {
         return RT_ENOSYS;
     }
-
     level = rt_hw_interrupt_disable();
     if (pin_irq_hdr_tab[irqindex].pin == pin &&
             pin_irq_hdr_tab[irqindex].hdr == hdr &&
@@ -706,15 +692,14 @@ rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     pin_irq_hdr_tab[irqindex].mode = mode;
     pin_irq_hdr_tab[irqindex].args = args;
     rt_hw_interrupt_enable(level);
-
     return RT_EOK;
 }
+
 rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
     rt_int32_t irqindex = -1;
-
     index = get_pin(pin);
     if (index == RT_NULL)
     {
@@ -725,7 +710,6 @@ rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
     {
         return RT_ENOSYS;
     }
-
     level = rt_hw_interrupt_disable();
     if (pin_irq_hdr_tab[irqindex].pin == -1)
     {
@@ -737,9 +721,9 @@ rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
     pin_irq_hdr_tab[irqindex].mode = 0;
     pin_irq_hdr_tab[irqindex].args = RT_NULL;
     rt_hw_interrupt_enable(level);
-
     return RT_EOK;
 }
+
 rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
                               rt_uint32_t enabled)
 {
@@ -748,7 +732,6 @@ rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
     rt_base_t level;
     rt_int32_t irqindex = -1;
     GPIO_InitTypeDef GPIO_InitStruct;
-
     index = get_pin(pin);
     if (index == RT_NULL)
     {
@@ -806,9 +789,9 @@ rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
     {
         return RT_ENOSYS;
     }
-
     return RT_EOK;
 }
+
 const static struct rt_pin_ops _stm32_pin_ops =
 {
     stm32_pin_mode,
@@ -822,7 +805,6 @@ const static struct rt_pin_ops _stm32_pin_ops =
 int rt_hw_pin_init(void)
 {
     int result;
-
     result = rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL);
     return result;
 }
@@ -840,36 +822,42 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
 {
     pin_irq_hdr(bit2bitno(GPIO_Pin));
 }
+
 void EXTI0_IRQHandler(void)
 {
     rt_interrupt_enter();
     HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
     rt_interrupt_leave();
 }
+
 void EXTI1_IRQHandler(void)
 {
     rt_interrupt_enter();
     HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
     rt_interrupt_leave();
 }
+
 void EXTI2_IRQHandler(void)
 {
     rt_interrupt_enter();
     HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
     rt_interrupt_leave();
 }
+
 void EXTI3_IRQHandler(void)
 {
     rt_interrupt_enter();
     HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
     rt_interrupt_leave();
 }
+
 void EXTI4_IRQHandler(void)
 {
     rt_interrupt_enter();
     HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
     rt_interrupt_leave();
 }
+
 void EXTI9_5_IRQHandler(void)
 {
     rt_interrupt_enter();
@@ -880,6 +868,7 @@ void EXTI9_5_IRQHandler(void)
     HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
     rt_interrupt_leave();
 }
+
 void EXTI15_10_IRQHandler(void)
 {
     rt_interrupt_enter();
@@ -891,5 +880,4 @@ void EXTI15_10_IRQHandler(void)
     HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
     rt_interrupt_leave();
 }
-
 #endif

bsp/stm32f10x-HAL/drivers/drv_gpio.h

@@ -14,18 +14,12 @@
  */
 #ifndef GPIO_H__
 #define GPIO_H__
-
-
 struct stm32_hw_pin_userdata
 {
     int pin;
     uint32_t mode;
 };
-
 #define PIN_USERDATA_END {-1,0}
-
 extern struct stm32_hw_pin_userdata stm32_pins[];
-
 int rt_hw_pin_init(void);
-
 #endif

bsp/stm32f10x-HAL/drivers/drv_sdcard.c

@@ -21,18 +21,15 @@
  * Date           Author         Notes
  * 2018-01-13     Liu2guang      the first version.
  */
-#include <rtthread.h>  
-#include <rtdevice.h> 
+#include <rtthread.h>
+#include <rtdevice.h>
 #include "board.h"
 #include "drv_sdcard.h"
-
 #ifndef SDIO_CLK_DIV
-#define SDIO_CLK_DIV 2
+    #define SDIO_CLK_DIV 2
 #endif
-
 #define SDIO_TIMEOUT ((uint32_t)0x100000)
-
-static SD_HandleTypeDef hsdcard; 
+static SD_HandleTypeDef hsdcard;
 static DMA_HandleTypeDef hdma;
 static struct rt_semaphore sd_lock;
 
@@ -43,11 +40,11 @@ void SDIO_IRQHandler(void)
     rt_interrupt_leave();
 }
 
-#if defined(USING_SD_RX_DMA) || defined(USING_SD_TX_DMA) 
+#if defined(USING_SD_RX_DMA) || defined(USING_SD_TX_DMA)
 void DMA2_Channel4_5_IRQHandler(void)
 {
     rt_interrupt_enter();
-    HAL_DMA_IRQHandler(&hdma); 
+    HAL_DMA_IRQHandler(&hdma);
     rt_interrupt_leave();
 }
 #endif
@@ -57,47 +54,42 @@ rt_err_t stm32_read_blocks(uint32_t *data, uint32_t addr, uint32_t num)
     uint32_t timeout = 0;
     HAL_SD_StateTypeDef state_return;
     HAL_SD_CardStateTypeDef sd_card_state_return;
-    
-#if defined(USING_SD_RX_DMA) && defined(USING_SD_TX_DMA) 
+#if defined(USING_SD_RX_DMA) && defined(USING_SD_TX_DMA)
     hdma.Init.Direction = DMA_PERIPH_TO_MEMORY;
-    hdma.Init.PeriphInc = DMA_PINC_DISABLE; 
-    hdma.Init.MemInc    = DMA_MINC_ENABLE; 
+    hdma.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma.Init.MemInc    = DMA_MINC_ENABLE;
     HAL_DMA_DeInit(&hdma);
-    HAL_DMA_Init(&hdma); 
+    HAL_DMA_Init(&hdma);
 #endif
-
 #if defined(USING_SD_RX_DMA)
-    if(HAL_SD_ReadBlocks_DMA(&hsdcard, (uint8_t *)data, addr, num) != HAL_OK)
+    if (HAL_SD_ReadBlocks_DMA(&hsdcard, (uint8_t *)data, addr, num) != HAL_OK)
 #else
-    if(HAL_SD_ReadBlocks(&hsdcard, (uint8_t *)data, addr, num, SDIO_TIMEOUT) != HAL_OK)
+    if (HAL_SD_ReadBlocks(&hsdcard, (uint8_t *)data, addr, num, SDIO_TIMEOUT) != HAL_OK)
 #endif
     {
         return RT_EIO;
     }
-    
     do
     {
         state_return = HAL_SD_GetState(&hsdcard);
         timeout++;
-    }while((HAL_SD_STATE_BUSY == state_return) && (SDIO_TIMEOUT > timeout));
-    
-    if(HAL_SD_STATE_READY != state_return)
+    }
+    while ((HAL_SD_STATE_BUSY == state_return) && (SDIO_TIMEOUT > timeout));
+    if (HAL_SD_STATE_READY != state_return)
     {
-        return RT_ERROR; 
+        return RT_ERROR;
     }
-    
     do
     {
         sd_card_state_return = HAL_SD_GetCardState(&hsdcard);
         timeout++;
-    }while((HAL_SD_CARD_TRANSFER != sd_card_state_return) && (SDIO_TIMEOUT > timeout));
-    
-    if(SDIO_TIMEOUT <= timeout)
+    }
+    while ((HAL_SD_CARD_TRANSFER != sd_card_state_return) && (SDIO_TIMEOUT > timeout));
+    if (SDIO_TIMEOUT <= timeout)
     {
-        return RT_ETIMEOUT; 
+        return RT_ETIMEOUT;
     }
-
-    return RT_EOK; 
+    return RT_EOK;
 }
 
 rt_err_t stm32_write_blocks(uint32_t *data, uint32_t addr, uint32_t num)
@@ -105,220 +97,185 @@ rt_err_t stm32_write_blocks(uint32_t *data, uint32_t addr, uint32_t num)
     uint32_t timeout = 0;
     HAL_SD_StateTypeDef state_return;
     HAL_SD_CardStateTypeDef sd_card_state_return;
-    
-#if defined(USING_SD_RX_DMA) && defined(USING_SD_TX_DMA) 
+#if defined(USING_SD_RX_DMA) && defined(USING_SD_TX_DMA)
     hdma.Init.Direction = DMA_MEMORY_TO_PERIPH;
-    hdma.Init.PeriphInc = DMA_MINC_ENABLE; 
-    hdma.Init.MemInc    = DMA_PINC_DISABLE; 
+    hdma.Init.PeriphInc = DMA_MINC_ENABLE;
+    hdma.Init.MemInc    = DMA_PINC_DISABLE;
     HAL_DMA_DeInit(&hdma);
-    HAL_DMA_Init(&hdma); 
+    HAL_DMA_Init(&hdma);
 #endif
-    
 #if defined(USING_SD_TX_DMA)
-    if(HAL_SD_WriteBlocks_DMA(&hsdcard, (uint8_t *)data, addr, num) != HAL_OK)
+    if (HAL_SD_WriteBlocks_DMA(&hsdcard, (uint8_t *)data, addr, num) != HAL_OK)
 #else
-    if(HAL_SD_WriteBlocks(&hsdcard, (uint8_t *)data, addr, num, SDIO_TIMEOUT) != HAL_OK)
+    if (HAL_SD_WriteBlocks(&hsdcard, (uint8_t *)data, addr, num, SDIO_TIMEOUT) != HAL_OK)
 #endif
     {
         return RT_ERROR;
     }
-    
     do
     {
         state_return = HAL_SD_GetState(&hsdcard);
         timeout++;
-    }while((HAL_SD_STATE_BUSY == state_return) && (SDIO_TIMEOUT > timeout));
-    
-    if(HAL_SD_STATE_READY != state_return)
+    }
+    while ((HAL_SD_STATE_BUSY == state_return) && (SDIO_TIMEOUT > timeout));
+    if (HAL_SD_STATE_READY != state_return)
     {
-        return RT_ERROR; 
+        return RT_ERROR;
     }
-    
     do
     {
         sd_card_state_return = HAL_SD_GetCardState(&hsdcard);
         timeout++;
-    }while((HAL_SD_CARD_TRANSFER != sd_card_state_return) && (SDIO_TIMEOUT > timeout));
-    
-    if(SDIO_TIMEOUT <= timeout)
+    }
+    while ((HAL_SD_CARD_TRANSFER != sd_card_state_return) && (SDIO_TIMEOUT > timeout));
+    if (SDIO_TIMEOUT <= timeout)
     {
-        return RT_ETIMEOUT; 
+        return RT_ETIMEOUT;
     }
-    
-    return RT_EOK; 
+    return RT_EOK;
 }
 
 static rt_err_t stm32_sdcard_init(rt_device_t dev)
 {
     GPIO_InitTypeDef GPIO_InitStruct;
-    
-    if(rt_sem_init(&sd_lock, "sdlock", 1, RT_IPC_FLAG_FIFO) != RT_EOK)
+    if (rt_sem_init(&sd_lock, "sdlock", 1, RT_IPC_FLAG_FIFO) != RT_EOK)
     {
         return RT_ERROR;
     }
-    
     __HAL_RCC_GPIOD_CLK_ENABLE();
     __HAL_RCC_GPIOC_CLK_ENABLE();
-    
-    GPIO_InitStruct.Pin   = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | 
+    GPIO_InitStruct.Pin   = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 |
                             GPIO_PIN_12;
-    GPIO_InitStruct.Mode  = GPIO_MODE_AF_PP; 
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 
-    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 
-    
+    GPIO_InitStruct.Mode  = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
     GPIO_InitStruct.Pin   = GPIO_PIN_2;
     HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
-    
-#if defined(USING_SD_RX_DMA) || defined(USING_SD_TX_DMA) 
+#if defined(USING_SD_RX_DMA) || defined(USING_SD_TX_DMA)
     __HAL_RCC_DMA2_CLK_ENABLE();
-
-    hdma.Instance                 = DMA2_Channel4; 
-    hdma.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; 
-    hdma.Init.MemDataAlignment    = DMA_MDATAALIGN_WORD; 
-    hdma.Init.Mode                = DMA_NORMAL; 
-    hdma.Init.Priority            = DMA_PRIORITY_HIGH; 
-    
+    hdma.Instance                 = DMA2_Channel4;
+    hdma.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
+    hdma.Init.MemDataAlignment    = DMA_MDATAALIGN_WORD;
+    hdma.Init.Mode                = DMA_NORMAL;
+    hdma.Init.Priority            = DMA_PRIORITY_HIGH;
 #if defined(USING_SD_RX_DMA)
-    hdma.Init.Direction           = DMA_PERIPH_TO_MEMORY; 
-    hdma.Init.PeriphInc           = DMA_PINC_DISABLE; 
-    hdma.Init.MemInc              = DMA_MINC_ENABLE; 
-    __HAL_LINKDMA(&hsdcard, hdmarx, hdma); 
+    hdma.Init.Direction           = DMA_PERIPH_TO_MEMORY;
+    hdma.Init.PeriphInc           = DMA_PINC_DISABLE;
+    hdma.Init.MemInc              = DMA_MINC_ENABLE;
+    __HAL_LINKDMA(&hsdcard, hdmarx, hdma);
 #endif
-
 #if defined(USING_SD_TX_DMA)
     hdma.Init.Direction           = DMA_MEMORY_TO_PERIPH;
     hdma.Init.PeriphInc           = DMA_MINC_ENABLE;
-    hdma.Init.MemInc              = DMA_PINC_DISABLE; 
-    __HAL_LINKDMA(&hsdcard, hdmatx, hdma); 
+    hdma.Init.MemInc              = DMA_PINC_DISABLE;
+    __HAL_LINKDMA(&hsdcard, hdmatx, hdma);
 #endif
-    
     HAL_DMA_DeInit(&hdma);
-    if(HAL_DMA_Init(&hdma) != HAL_OK)
+    if (HAL_DMA_Init(&hdma) != HAL_OK)
     {
         rt_kprintf("HAL_DMA_Init error\n");
         return RT_EIO;
     }
 #endif
-    
     HAL_NVIC_SetPriority(DMA2_Channel4_5_IRQn, 3, 0);
-    HAL_NVIC_EnableIRQ(DMA2_Channel4_5_IRQn); 
-    
-    __HAL_RCC_SDIO_CLK_ENABLE(); 
-    
-    hsdcard.Instance                 = SDIO; 
-    hsdcard.Init.ClockEdge           = SDIO_CLOCK_EDGE_RISING; 
+    HAL_NVIC_EnableIRQ(DMA2_Channel4_5_IRQn);
+    __HAL_RCC_SDIO_CLK_ENABLE();
+    hsdcard.Instance                 = SDIO;
+    hsdcard.Init.ClockEdge           = SDIO_CLOCK_EDGE_RISING;
     hsdcard.Init.ClockBypass         = SDIO_CLOCK_BYPASS_DISABLE;
     hsdcard.Init.ClockPowerSave      = SDIO_CLOCK_POWER_SAVE_DISABLE;
     hsdcard.Init.BusWide             = SDIO_BUS_WIDE_1B;
     hsdcard.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_ENABLE;
-    hsdcard.Init.ClockDiv            = SDIO_CLK_DIV; 
-    
+    hsdcard.Init.ClockDiv            = SDIO_CLK_DIV;
     HAL_SD_DeInit(&hsdcard);
-    if(HAL_SD_Init(&hsdcard) != HAL_OK)
+    if (HAL_SD_Init(&hsdcard) != HAL_OK)
     {
         rt_kprintf("HAL_SD_Init error\n");
-        return RT_EIO; 
+        return RT_EIO;
     }
-    
     HAL_NVIC_SetPriority(SDIO_IRQn, 1, 0);
     HAL_NVIC_EnableIRQ(SDIO_IRQn);
-    
-    if(HAL_SD_ConfigWideBusOperation(&hsdcard, SDIO_BUS_WIDE_4B) != HAL_OK) 
+    if (HAL_SD_ConfigWideBusOperation(&hsdcard, SDIO_BUS_WIDE_4B) != HAL_OK)
     {
         rt_kprintf("HAL_SD_ConfigWideBusOperation error\n");
         return RT_EIO;
     }
-    
-    return RT_EOK; 
+    return RT_EOK;
 }
 
 static rt_err_t stm32_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
 {
-    return RT_EOK; 
+    return RT_EOK;
 }
 
-static rt_err_t stm32_sdcard_close(rt_device_t dev) 
+static rt_err_t stm32_sdcard_close(rt_device_t dev)
 {
-    return RT_EOK; 
-} 
+    return RT_EOK;
+}
 
-static rt_size_t stm32_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+static rt_size_t stm32_sdcard_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
 {
-    int ret = RT_EOK; 
-    
+    int ret = RT_EOK;
     rt_sem_take(&sd_lock, RT_WAITING_FOREVER);
-    ret = stm32_read_blocks((uint32_t *)buffer, pos, size); 
+    ret = stm32_read_blocks((uint32_t *)buffer, pos, size);
     rt_sem_release(&sd_lock);
-    
-    if(ret != RT_EOK)
+    if (ret != RT_EOK)
     {
-        return 0; 
+        return 0;
     }
-    
-    return size; 
-} 
+    return size;
+}
 
-static rt_size_t stm32_sdcard_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+static rt_size_t stm32_sdcard_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
 {
     int ret = RT_EOK;
-    
     rt_sem_take(&sd_lock, RT_WAITING_FOREVER);
-    ret = stm32_write_blocks((uint32_t *)buffer, pos, size); 
+    ret = stm32_write_blocks((uint32_t *)buffer, pos, size);
     rt_sem_release(&sd_lock);
-    
-    if(ret != RT_EOK)
+    if (ret != RT_EOK)
     {
-        return 0; 
+        return 0;
     }
-    
-    return size; 
-} 
+    return size;
+}
 
 static rt_err_t stm32_sdcard_control(rt_device_t dev, int cmd, void *args)
 {
     RT_ASSERT(dev != RT_NULL);
-    
-    // RT_DEVICE_CTRL_BLK_GETGEOME 
-    if(cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
+    // RT_DEVICE_CTRL_BLK_GETGEOME
+    if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
     {
         HAL_SD_CardInfoTypeDef sdcard_info;
         struct rt_device_blk_geometry *geometry;
-        
         HAL_SD_GetCardInfo(&hsdcard, &sdcard_info);
-        
         geometry = (struct rt_device_blk_geometry *)args;
-
         geometry->bytes_per_sector = sdcard_info.BlockSize;
         geometry->block_size       = sdcard_info.BlockSize;
         geometry->sector_count     = sdcard_info.BlockNbr;
     }
-
     return RT_EOK;
-} 
+}
 
-static struct rt_device device; 
+static struct rt_device device;
 
 int rt_hw_sdcard_init(void)
 {
-    rt_err_t ret = RT_EOK; 
-
+    rt_err_t ret = RT_EOK;
     device.type    = RT_Device_Class_Block;
     device.init    = stm32_sdcard_init;
-    device.open    = stm32_sdcard_open; 
+    device.open    = stm32_sdcard_open;
     device.read    = stm32_sdcard_read;
     device.write   = stm32_sdcard_write;
     device.control = stm32_sdcard_control;
     device.close   = stm32_sdcard_close;
-    
-    ret = rt_device_register(&device, "sd0", 
-                             RT_DEVICE_FLAG_REMOVABLE | 
-                             RT_DEVICE_FLAG_RDWR      | 
-                             RT_DEVICE_FLAG_STANDALONE); 
-    if(ret != RT_EOK)
+    ret = rt_device_register(&device, "sd0",
+                             RT_DEVICE_FLAG_REMOVABLE |
+                             RT_DEVICE_FLAG_RDWR      |
+                             RT_DEVICE_FLAG_STANDALONE);
+    if (ret != RT_EOK)
     {
-        return ret; 
+        return ret;
     }
-    
-    return RT_EOK; 
+    return RT_EOK;
 }
-INIT_DEVICE_EXPORT(rt_hw_sdcard_init); 
+INIT_DEVICE_EXPORT(rt_hw_sdcard_init);

bsp/stm32f10x-HAL/drivers/drv_sdcard.h

@@ -22,9 +22,9 @@
  * 2018-01-13     Liu2guang      the first version.
  */
 
-#ifndef __DRV_SDCARD_H_ 
-#define __DRV_SDCARD_H_ 
+#ifndef __DRV_SDCARD_H_
+#define __DRV_SDCARD_H_
 
-int rt_hw_sdcard_init(void); 
+int rt_hw_sdcard_init(void);
 
 #endif

bsp/stm32f10x-HAL/drivers/drv_spi.c

@@ -16,30 +16,25 @@
 #include <board.h>
 #include <drv_spi.h>
 #ifdef RT_USING_SPI
-
 #define SPIRXEVENT 0x01
 #define SPITXEVENT 0x02
 #define SPITIMEOUT 2
 #define SPICRCEN 0
-
 struct stm32_hw_spi_cs
 {
     rt_uint32_t pin;
 };
 
-
 struct stm32_spi
 {
     SPI_TypeDef *Instance;
     struct rt_spi_configuration *cfg;
 };
 
-
 static rt_err_t stm32_spi_init(SPI_TypeDef *spix, struct rt_spi_configuration *cfg)
 {
     SPI_HandleTypeDef hspi;
     hspi.Instance = spix;
-
     if (cfg->mode & RT_SPI_SLAVE)
     {
         hspi.Init.Mode = SPI_MODE_SLAVE;
@@ -145,6 +140,7 @@ static rt_err_t stm32_spi_init(SPI_TypeDef *spix, struct rt_spi_configuration *c
     __HAL_SPI_ENABLE(&hspi);
     return RT_EOK;
 }
+
 #define SPISTEP(datalen) (((datalen) == 8) ? 1 : 2)
 #define SPISEND_1(reg, ptr, datalen)       \
     do                                     \
@@ -195,6 +191,7 @@ static rt_err_t spitxrx1b(struct stm32_spi *hspi, void *rcvb, const void *sndb)
     SPIRECV_1(hspi->Instance->DR, rcvb, hspi->cfg->data_width);
     return RT_EOK;
 }
+
 static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
 {
     rt_err_t res;
@@ -203,7 +200,6 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
     RT_ASSERT(device->bus->parent.user_data != RT_NULL);
     struct stm32_spi *hspi = (struct stm32_spi *)device->bus->parent.user_data;
     struct stm32_hw_spi_cs *cs = device->parent.user_data;
-
     if (message->cs_take)
     {
         rt_pin_write(cs->pin, 0);
@@ -238,7 +234,6 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
     return message->length - length;
 }
 
-
 rt_err_t spi_configure(struct rt_spi_device *device,
                        struct rt_spi_configuration *configuration)
 {
@@ -378,34 +373,3 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *spiHandle)
     }
 }
 #endif /*RT_USING_SPI*/
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

bsp/stm32f10x-HAL/drivers/drv_spi.h

@@ -18,21 +18,7 @@
 #include <rtthread.h>
 #include <rthw.h>
 #include <rtdevice.h>
-
-
-
-extern int stm32_spi_register_bus(SPI_TypeDef * SPIx,const char * name);
-extern rt_err_t stm32_spi_bus_attach_device(rt_uint32_t pin,const char * bus_name,const char * device_name);
+extern int stm32_spi_register_bus(SPI_TypeDef *SPIx, const char *name);
+extern rt_err_t stm32_spi_bus_attach_device(rt_uint32_t pin, const char *bus_name, const char *device_name);
 extern int stm32_hw_spi_init(void);
-
-
-
 #endif
-
-
-
-
-
-
-
-

bsp/stm32f10x-HAL/drivers/drv_usart.c

@@ -23,7 +23,6 @@
 #include <rtdevice.h>
 #include <drv_usart.h>
 
-
 /* STM32 uart driver */
 struct stm32_uart
 {
@@ -34,17 +33,13 @@ struct stm32_uart
 static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
 {
     struct stm32_uart *uart;
-
     RT_ASSERT(serial != RT_NULL);
     RT_ASSERT(cfg != RT_NULL);
-
     uart = (struct stm32_uart *)serial->parent.user_data;
-
     uart->huart.Init.BaudRate   = cfg->baud_rate;
     uart->huart.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
     uart->huart.Init.Mode       = UART_MODE_TX_RX;
     uart->huart.Init.OverSampling = UART_OVERSAMPLING_16;
-
     switch (cfg->data_bits)
     {
     case DATA_BITS_8:
@@ -84,23 +79,18 @@ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_c
         uart->huart.Init.Parity     = UART_PARITY_NONE;
         break;
     }
-
     if (HAL_UART_Init(&uart->huart) != HAL_OK)
     {
         return RT_ERROR;
     }
-
     return RT_EOK;
 }
 
 static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
 {
     struct stm32_uart *uart;
-//    rt_uint32_t ctrl_arg = (rt_uint32_t)(arg);
-
     RT_ASSERT(serial != RT_NULL);
     uart = (struct stm32_uart *)serial->parent.user_data;
-
     switch (cmd)
     {
     /* disable interrupt */
@@ -124,7 +114,6 @@ static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *ar
 static int stm32_putc(struct rt_serial_device *serial, char c)
 {
     struct stm32_uart *uart;
-
     RT_ASSERT(serial != RT_NULL);
     uart = (struct stm32_uart *)serial->parent.user_data;
     while (__HAL_UART_GET_FLAG(&uart->huart, UART_FLAG_TXE) == RESET);
@@ -146,7 +135,6 @@ static int stm32_getc(struct rt_serial_device *serial)
     return ch;
 }
 
-
 /**
  * Uart common interrupt process. This need add to uart ISR.
  *
@@ -155,9 +143,7 @@ static int stm32_getc(struct rt_serial_device *serial)
 static void uart_isr(struct rt_serial_device *serial)
 {
     struct stm32_uart *uart = (struct stm32_uart *) serial->parent.user_data;
-
     RT_ASSERT(uart != RT_NULL);
-
     if ((__HAL_UART_GET_FLAG(&uart->huart, UART_FLAG_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(&uart->huart, UART_IT_RXNE) != RESET))
     {
         rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
@@ -186,9 +172,7 @@ void USART1_IRQHandler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
-
     uart_isr(&serial1);
-
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -250,7 +234,7 @@ int rt_hw_usart_init(void)
     MX_USART_UART_Init(&uart->huart);
     /* register UART1 device */
     rt_hw_serial_register(&serial1, "uart1",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX ,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart);
 #endif /* RT_USING_UART1 */
 
@@ -262,7 +246,7 @@ int rt_hw_usart_init(void)
     MX_USART_UART_Init(&uart->huart);
     /* register UART1 device */
     rt_hw_serial_register(&serial2, "uart2",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX ,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart);
 #endif /* RT_USING_UART1 */
 
@@ -274,14 +258,13 @@ int rt_hw_usart_init(void)
     MX_USART_UART_Init(&uart->huart);
     /* register UART1 device */
     rt_hw_serial_register(&serial3, "uart3",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX ,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart);
 #endif /* RT_USING_UART1 */
     return 0;
 }
 INIT_BOARD_EXPORT(rt_hw_usart_init);
 
-
 static void MX_USART_UART_Init(UART_HandleTypeDef *uartHandle)
 {
     uartHandle->Init.BaudRate = 115200;
@@ -296,15 +279,12 @@ static void MX_USART_UART_Init(UART_HandleTypeDef *uartHandle)
 }
 /* USART2 init function */
 
-
 void HAL_UART_MspInit(UART_HandleTypeDef *uartHandle)
 {
-
     GPIO_InitTypeDef GPIO_InitStruct;
     if (uartHandle->Instance == USART1)
     {
         /* USER CODE BEGIN USART1_MspInit 0 */
-
         /* USER CODE END USART1_MspInit 0 */
         /* USART1 clock enable */
         __HAL_RCC_USART1_CLK_ENABLE();
@@ -317,23 +297,19 @@ void HAL_UART_MspInit(UART_HandleTypeDef *uartHandle)
         GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
         GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
         HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
         GPIO_InitStruct.Pin = GPIO_PIN_10;
         GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
         GPIO_InitStruct.Pull = GPIO_NOPULL;
         HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
         /* USART1 interrupt Init */
         HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
         HAL_NVIC_EnableIRQ(USART1_IRQn);
         /* USER CODE BEGIN USART1_MspInit 1 */
-
         /* USER CODE END USART1_MspInit 1 */
     }
     else if (uartHandle->Instance == USART2)
     {
         /* USER CODE BEGIN USART2_MspInit 0 */
-
         /* USER CODE END USART2_MspInit 0 */
         /* USART2 clock enable */
         __HAL_RCC_USART2_CLK_ENABLE();
@@ -346,12 +322,10 @@ void HAL_UART_MspInit(UART_HandleTypeDef *uartHandle)
         GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
         GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
         HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
         GPIO_InitStruct.Pin = GPIO_PIN_3;
         GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
         GPIO_InitStruct.Pull = GPIO_NOPULL;
         HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
         /* USART2 interrupt Init */
         HAL_NVIC_SetPriority(USART2_IRQn, 5, 0);
         HAL_NVIC_EnableIRQ(USART2_IRQn);
@@ -362,7 +336,6 @@ void HAL_UART_MspInit(UART_HandleTypeDef *uartHandle)
     else if (uartHandle->Instance == USART3)
     {
         /* USER CODE BEGIN USART3_MspInit 0 */
-
         /* USER CODE END USART3_MspInit 0 */
         /* USART3 clock enable */
         __HAL_RCC_USART3_CLK_ENABLE();
@@ -375,86 +348,66 @@ void HAL_UART_MspInit(UART_HandleTypeDef *uartHandle)
         GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
         GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
         HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
         GPIO_InitStruct.Pin = GPIO_PIN_11;
         GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
         GPIO_InitStruct.Pull = GPIO_NOPULL;
         HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
         /* USART3 interrupt Init */
         HAL_NVIC_SetPriority(USART3_IRQn, 5, 0);
         HAL_NVIC_EnableIRQ(USART3_IRQn);
         /* USER CODE BEGIN USART3_MspInit 1 */
-
         /* USER CODE END USART3_MspInit 1 */
     }
 }
 
 void HAL_UART_MspDeInit(UART_HandleTypeDef *uartHandle)
 {
-
     if (uartHandle->Instance == USART1)
     {
         /* USER CODE BEGIN USART1_MspDeInit 0 */
-
         /* USER CODE END USART1_MspDeInit 0 */
         /* Peripheral clock disable */
         __HAL_RCC_USART1_CLK_DISABLE();
-
         /**USART1 GPIO Configuration
         PA9     ------> USART1_TX
         PA10     ------> USART1_RX
         */
         HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9 | GPIO_PIN_10);
-
         /* USART1 interrupt Deinit */
         HAL_NVIC_DisableIRQ(USART1_IRQn);
         /* USER CODE BEGIN USART1_MspDeInit 1 */
-
         /* USER CODE END USART1_MspDeInit 1 */
     }
     else if (uartHandle->Instance == USART2)
     {
         /* USER CODE BEGIN USART2_MspDeInit 0 */
-
         /* USER CODE END USART2_MspDeInit 0 */
         /* Peripheral clock disable */
         __HAL_RCC_USART2_CLK_DISABLE();
-
         /**USART2 GPIO Configuration
         PA2     ------> USART2_TX
         PA3     ------> USART2_RX
         */
         HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2 | GPIO_PIN_3);
-
         /* USART2 interrupt Deinit */
         HAL_NVIC_DisableIRQ(USART2_IRQn);
         /* USER CODE BEGIN USART2_MspDeInit 1 */
-
         /* USER CODE END USART2_MspDeInit 1 */
     }
     else if (uartHandle->Instance == USART3)
     {
         /* USER CODE BEGIN USART3_MspDeInit 0 */
-
         /* USER CODE END USART3_MspDeInit 0 */
         /* Peripheral clock disable */
         __HAL_RCC_USART3_CLK_DISABLE();
-
         /**USART3 GPIO Configuration
         PB10     ------> USART3_TX
         PB11     ------> USART3_RX
         */
         HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10 | GPIO_PIN_11);
-
         /* USART3 interrupt Deinit */
         HAL_NVIC_DisableIRQ(USART3_IRQn);
         /* USER CODE BEGIN USART3_MspDeInit 1 */
-
         /* USER CODE END USART3_MspDeInit 1 */
     }
 }
-
-
-
-

bsp/stm32f10x-HAL/drivers/drv_usart.h

@@ -11,12 +11,9 @@
  * Date           Author       Notes
  * 2009-01-05     Bernard      the first version
  */
-
 #ifndef __USART_H__
 #define __USART_H__
-
 #include <rthw.h>
 #include <rtthread.h>
 int rt_hw_usart_init(void);
-
 #endif

bsp/stm32f10x-HAL/drivers/drv_usb.c

@@ -16,9 +16,7 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 #include "board.h"
-
-#define USB_DISCONNECT_PIN                  30		//PA9
-
+#define USB_DISCONNECT_PIN                  30      //PA9
 static PCD_HandleTypeDef _stm_pcd;
 static struct udcd _stm_udc;
 static struct ep_id _ep_pool[] =
@@ -35,9 +33,7 @@ static struct ep_id _ep_pool[] =
 void USB_LP_CAN1_RX0_IRQHandler(void)
 {
     rt_interrupt_enter();
-
     HAL_PCD_IRQHandler(&_stm_pcd);
-
     rt_interrupt_leave();
 }
 
@@ -51,10 +47,9 @@ void HAL_PCD_ResetCallback(PCD_HandleTypeDef *pcd)
 
 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
 {
-    rt_usbd_ep0_setup_handler(&_stm_udc, (struct urequest*)hpcd->Setup);
+    rt_usbd_ep0_setup_handler(&_stm_udc, (struct urequest *)hpcd->Setup);
 }
 
-
 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 {
     if (epnum == 0)
@@ -63,7 +58,7 @@ void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
     }
     else
     {
-        rt_usbd_ep_in_handler(&_stm_udc, 0x80|epnum,hpcd->IN_ep[epnum].xfer_count);
+        rt_usbd_ep_in_handler(&_stm_udc, 0x80 | epnum, hpcd->IN_ep[epnum].xfer_count);
     }
 }
 
@@ -90,46 +85,43 @@ void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
     }
     else
     {
-        rt_usbd_ep0_out_handler(&_stm_udc,hpcd->OUT_ep[0].xfer_count);
+        rt_usbd_ep0_out_handler(&_stm_udc, hpcd->OUT_ep[0].xfer_count);
     }
 }
 
-
 void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
 {
-    if(state == 1)
+    if (state == 1)
     {
-        rt_pin_write(USB_DISCONNECT_PIN,PIN_HIGH);
+        rt_pin_write(USB_DISCONNECT_PIN, PIN_HIGH);
     }
     else
     {
-        rt_pin_write(USB_DISCONNECT_PIN,PIN_LOW);
-    }  
+        rt_pin_write(USB_DISCONNECT_PIN, PIN_LOW);
+    }
 }
 
-void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
+void HAL_PCD_MspInit(PCD_HandleTypeDef *pcdHandle)
 {
-    if(pcdHandle->Instance==USB)
+    if (pcdHandle->Instance == USB)
     {
         __HAL_RCC_GPIOA_CLK_ENABLE();
-        rt_pin_mode(USB_DISCONNECT_PIN,PIN_MODE_OUTPUT);
-        rt_pin_write(USB_DISCONNECT_PIN,PIN_LOW);
+        rt_pin_mode(USB_DISCONNECT_PIN, PIN_MODE_OUTPUT);
+        rt_pin_write(USB_DISCONNECT_PIN, PIN_LOW);
         /* Peripheral clock enable */
         __HAL_RCC_USB_CLK_ENABLE();
-
         /* Peripheral interrupt init */
         HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 5, 0);
         HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
     }
 }
 
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *pcdHandle)
 {
-    if(pcdHandle->Instance==USB)
+    if (pcdHandle->Instance == USB)
     {
         /* Peripheral clock disable */
         __HAL_RCC_USB_CLK_DISABLE();
-
         /* Peripheral interrupt Deinit*/
         HAL_NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn);
     }
@@ -143,7 +135,7 @@ static rt_err_t _ep_set_stall(rt_uint8_t address)
 
 static rt_err_t _ep_clear_stall(rt_uint8_t address)
 {
-    HAL_PCD_EP_ClrStall(&_stm_pcd, address);  
+    HAL_PCD_EP_ClrStall(&_stm_pcd, address);
     return RT_EOK;
 }
 
@@ -164,7 +156,6 @@ static rt_err_t _ep_enable(uep_t ep)
     RT_ASSERT(ep->ep_desc != RT_NULL);
     HAL_PCD_EP_Open(&_stm_pcd, ep->ep_desc->bEndpointAddress,
                     ep->ep_desc->wMaxPacketSize, ep->ep_desc->bmAttributes);
-
     return RT_EOK;
 }
 
@@ -196,7 +187,7 @@ static rt_size_t _ep_write(rt_uint8_t address, void *buffer, rt_size_t size)
 }
 
 static rt_err_t _ep0_send_status(void)
-{	
+{
     HAL_PCD_EP_Transmit(&_stm_pcd, 0x00, NULL, 0);
     return RT_EOK;
 }
@@ -214,10 +205,8 @@ static rt_err_t _wakeup(void)
 static rt_err_t _init(rt_device_t device)
 {
     PCD_HandleTypeDef *pcd;
-
     /* Set LL Driver parameters */
-    pcd = (PCD_HandleTypeDef*)device->user_data;
-
+    pcd = (PCD_HandleTypeDef *)device->user_data;
     pcd->Instance = USB;
     pcd->Init.dev_endpoints = 8;
     pcd->Init.speed = PCD_SPEED_FULL;
@@ -225,19 +214,16 @@ static rt_err_t _init(rt_device_t device)
     pcd->Init.low_power_enable = DISABLE;
     pcd->Init.lpm_enable = DISABLE;
     pcd->Init.battery_charging_enable = DISABLE;
-
     /* Initialize LL Driver */
     HAL_PCD_Init(pcd);
-  
-    HAL_PCDEx_PMAConfig(pcd , 0x00 , PCD_SNG_BUF, 0x18);
-    HAL_PCDEx_PMAConfig(pcd , 0x80 , PCD_SNG_BUF, 0x58);
-    HAL_PCDEx_PMAConfig(pcd , 0x81 , PCD_SNG_BUF, 0x98);    
-    HAL_PCDEx_PMAConfig(pcd , 0x01 , PCD_SNG_BUF, 0x118);
-    HAL_PCDEx_PMAConfig(pcd , 0x82 , PCD_SNG_BUF, 0xD8);   
-    HAL_PCDEx_PMAConfig(pcd , 0x02 , PCD_SNG_BUF, 0x158);
-    HAL_PCDEx_PMAConfig(pcd , 0x83 , PCD_SNG_BUF, 0x198);
+    HAL_PCDEx_PMAConfig(pcd, 0x00, PCD_SNG_BUF, 0x18);
+    HAL_PCDEx_PMAConfig(pcd, 0x80, PCD_SNG_BUF, 0x58);
+    HAL_PCDEx_PMAConfig(pcd, 0x81, PCD_SNG_BUF, 0x98);
+    HAL_PCDEx_PMAConfig(pcd, 0x01, PCD_SNG_BUF, 0x118);
+    HAL_PCDEx_PMAConfig(pcd, 0x82, PCD_SNG_BUF, 0xD8);
+    HAL_PCDEx_PMAConfig(pcd, 0x02, PCD_SNG_BUF, 0x158);
+    HAL_PCDEx_PMAConfig(pcd, 0x83, PCD_SNG_BUF, 0x198);
     HAL_PCD_Start(pcd);
-
     return RT_EOK;
 }
 
@@ -257,11 +243,9 @@ const static struct udcd_ops _udc_ops =
     _wakeup,
 };
 
-
 int stm_usbd_register(void)
 {
     rt_memset((void *)&_stm_udc, 0, sizeof(struct udcd));
-
     _stm_udc.parent.type = RT_Device_Class_USBDevice;
     _stm_udc.parent.init = _init;
     _stm_udc.parent.user_data = &_stm_pcd;
@@ -269,10 +253,9 @@ int stm_usbd_register(void)
     /* Register endpoint infomation */
     _stm_udc.ep_pool = _ep_pool;
     _stm_udc.ep0.id = &_ep_pool[0];
-
     rt_device_register((rt_device_t)&_stm_udc, "usbd", 0);
     rt_usb_device_init();
     return 0;
 }
+
 INIT_DEVICE_EXPORT(stm_usbd_register);
- 

bsp/stm32f10x-HAL/drivers/drv_usb.h

@@ -14,7 +14,5 @@
 #ifndef __STM32_USB_H__
 #define __STM32_USB_H__
 #include <rtthread.h>
-
 int stm_usbd_register(void);
-
 #endif

bsp/stm32f10x-HAL/drivers/stm32f1xx_hal_conf.h

@@ -35,17 +35,17 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F1xx_HAL_CONF_H
 #define __STM32F1xx_HAL_CONF_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 #include "rtthread.h"
-#ifndef NULL 
+#ifndef NULL
 #define NULL RT_NULL
 #endif
 /* Exported types ------------------------------------------------------------*/
@@ -53,7 +53,7 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
 #define HAL_MODULE_ENABLED
 // #define HAL_ADC_MODULE_ENABLED
@@ -75,23 +75,23 @@
 // #define HAL_NOR_MODULE_ENABLED
 // #define HAL_PCCARD_MODULE_ENABLED
 #ifdef RT_USING_USB_DEVICE
-  #define HAL_PCD_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
 #endif
 #define HAL_PWR_MODULE_ENABLED
 #define HAL_RCC_MODULE_ENABLED
 // #define HAL_RTC_MODULE_ENABLED
-#ifdef RT_USING_SDCARD 
-  #define HAL_SD_MODULE_ENABLED
+#ifdef RT_USING_SDCARD
+#define HAL_SD_MODULE_ENABLED
 #endif
 // #define HAL_SMARTCARD_MODULE_ENABLED
 #ifdef RT_USING_SPI
-  #define HAL_SPI_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
 #endif
 // #define HAL_SRAM_MODULE_ENABLED
 #define HAL_TIM_MODULE_ENABLED
 #ifdef RT_USING_SERIAL
-  #define HAL_UART_MODULE_ENABLED
-  #define HAL_USART_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
 #endif
 
 // #define HAL_WWDG_MODULE_ENABLED
@@ -101,49 +101,49 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
 #define HSE_VALUE ((unsigned int)RT_HSE_VALUE)
 
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
 #if defined(USE_STM3210C_EVAL)
-  #define HSE_VALUE    25000000U /*!< Value of the External oscillator in Hz */
+#define HSE_VALUE    25000000U /*!< Value of the External oscillator in Hz */
 #else
-  #define HSE_VALUE    8000000U /*!< Value of the External oscillator in Hz */
+#define HSE_VALUE    8000000U /*!< Value of the External oscillator in Hz */
 #endif
 #endif /* HSE_VALUE */
 
 #if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    100U      /*!< Time out for HSE start up, in ms */
+#define HSE_STARTUP_TIMEOUT    100U      /*!< Time out for HSE start up, in ms */
 #endif /* HSE_STARTUP_TIMEOUT */
 
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
-  #define HSI_VALUE              8000000U  /*!< Value of the Internal oscillator in Hz */
+#define HSI_VALUE              8000000U  /*!< Value of the Internal oscillator in Hz */
 #endif /* HSI_VALUE */
 
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE               40000U    /*!< LSI Typical Value in Hz */
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE               40000U    /*!< LSI Typical Value in Hz */
 #endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
-                                                The real value may vary depending on the variations
-                                                in voltage and temperature. */
+The real value may vary depending on the variations
+in voltage and temperature. */
 /**
   * @brief External Low Speed oscillator (LSE) value.
   *        This value is used by the UART, RTC HAL module to compute the system frequency
   */
 #if !defined  (LSE_VALUE)
- #define LSE_VALUE               32768U    /*!< Value of the External Low Speed oscillator in Hz */
+#define LSE_VALUE               32768U    /*!< Value of the External Low Speed oscillator in Hz */
 #endif /* LSE_VALUE */
 
 #if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    5000U     /*!< Time out for LSE start up, in ms */
+#define LSE_STARTUP_TIMEOUT    5000U     /*!< Time out for LSE start up, in ms */
 #endif /* LSE_STARTUP_TIMEOUT */
 
 /* Tip: To avoid modifying this file each time you need to use different HSE,
@@ -152,7 +152,7 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    3300U /*!< Value of VDD in mv */
 #define  TICK_INT_PRIORITY            0x0FU /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
@@ -160,7 +160,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -177,7 +177,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    8U                  /* 8 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -185,9 +185,9 @@
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/ 
+/* DP83848 PHY Address*/
 #define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -199,7 +199,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -214,13 +214,13 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
 #define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
 #define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
+
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
@@ -242,131 +242,131 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32f1xx_hal_rcc.h"
+#include "stm32f1xx_hal_rcc.h"
 #endif /* HAL_RCC_MODULE_ENABLED */
 
 #ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32f1xx_hal_gpio.h"
+#include "stm32f1xx_hal_gpio.h"
 #endif /* HAL_GPIO_MODULE_ENABLED */
-   
+
 #ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f1xx_hal_dma.h"
+#include "stm32f1xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f1xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */  
-   
+#include "stm32f1xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
 #ifdef HAL_CAN_MODULE_ENABLED
- #include "stm32f1xx_hal_can.h"
+#include "stm32f1xx_hal_can.h"
 #endif /* HAL_CAN_MODULE_ENABLED */
 
 #ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f1xx_hal_cec.h"
+#include "stm32f1xx_hal_cec.h"
 #endif /* HAL_CEC_MODULE_ENABLED */
 
 #ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32f1xx_hal_cortex.h"
+#include "stm32f1xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
 
 #ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32f1xx_hal_adc.h"
+#include "stm32f1xx_hal_adc.h"
 #endif /* HAL_ADC_MODULE_ENABLED */
 
 #ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32f1xx_hal_crc.h"
+#include "stm32f1xx_hal_crc.h"
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32f1xx_hal_dac.h"
+#include "stm32f1xx_hal_dac.h"
 #endif /* HAL_DAC_MODULE_ENABLED */
 
 #ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32f1xx_hal_flash.h"
+#include "stm32f1xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
 
 #ifdef HAL_SRAM_MODULE_ENABLED
- #include "stm32f1xx_hal_sram.h"
+#include "stm32f1xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
 
 #ifdef HAL_NOR_MODULE_ENABLED
- #include "stm32f1xx_hal_nor.h"
+#include "stm32f1xx_hal_nor.h"
 #endif /* HAL_NOR_MODULE_ENABLED */
 
 #ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f1xx_hal_i2c.h"
+#include "stm32f1xx_hal_i2c.h"
 #endif /* HAL_I2C_MODULE_ENABLED */
 
 #ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f1xx_hal_i2s.h"
+#include "stm32f1xx_hal_i2s.h"
 #endif /* HAL_I2S_MODULE_ENABLED */
 
 #ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f1xx_hal_iwdg.h"
+#include "stm32f1xx_hal_iwdg.h"
 #endif /* HAL_IWDG_MODULE_ENABLED */
 
 #ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f1xx_hal_pwr.h"
+#include "stm32f1xx_hal_pwr.h"
 #endif /* HAL_PWR_MODULE_ENABLED */
 
 #ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f1xx_hal_rtc.h"
+#include "stm32f1xx_hal_rtc.h"
 #endif /* HAL_RTC_MODULE_ENABLED */
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
- #include "stm32f1xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
+#include "stm32f1xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
 
 #ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f1xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */  
+#include "stm32f1xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
 
 #ifdef HAL_NAND_MODULE_ENABLED
- #include "stm32f1xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */     
+#include "stm32f1xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
 
 #ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f1xx_hal_spi.h"
+#include "stm32f1xx_hal_spi.h"
 #endif /* HAL_SPI_MODULE_ENABLED */
 
 #ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f1xx_hal_tim.h"
+#include "stm32f1xx_hal_tim.h"
 #endif /* HAL_TIM_MODULE_ENABLED */
 
 #ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f1xx_hal_uart.h"
+#include "stm32f1xx_hal_uart.h"
 #endif /* HAL_UART_MODULE_ENABLED */
 
 #ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f1xx_hal_usart.h"
+#include "stm32f1xx_hal_usart.h"
 #endif /* HAL_USART_MODULE_ENABLED */
 
 #ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f1xx_hal_irda.h"
+#include "stm32f1xx_hal_irda.h"
 #endif /* HAL_IRDA_MODULE_ENABLED */
 
 #ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f1xx_hal_smartcard.h"
+#include "stm32f1xx_hal_smartcard.h"
 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
 
 #ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f1xx_hal_wwdg.h"
+#include "stm32f1xx_hal_wwdg.h"
 #endif /* HAL_WWDG_MODULE_ENABLED */
 
 #ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f1xx_hal_pcd.h"
+#include "stm32f1xx_hal_pcd.h"
 #endif /* HAL_PCD_MODULE_ENABLED */
 
 #ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f1xx_hal_hcd.h"
+#include "stm32f1xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
 
 #ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f1xx_hal_mmc.h"
+#include "stm32f1xx_hal_mmc.h"
 #endif /* HAL_MMC_MODULE_ENABLED */
 
 /* Exported macro ------------------------------------------------------------*/
@@ -375,15 +375,15 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr: If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
 /* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
+void assert_failed(uint8_t *file, uint32_t line);
 #else
-  #define assert_param(expr) ((void)0U)
+#define assert_param(expr) ((void)0U)
 #endif /* USE_FULL_ASSERT */
 
 

bsp/stm32f10x-HAL/drivers/stm32f1xx_it.h

@@ -36,8 +36,8 @@
 #define __STM32F1xx_IT_H
 
 #ifdef __cplusplus
- extern "C" {
-#endif 
+extern "C" {
+#endif
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f1xx_hal.h"

bsp/stm32f10x-HAL/rtconfig.py

@@ -20,7 +20,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keilv5'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
+	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
 
 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -106,7 +106,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --cpu=Cortex-M3' 
     CFLAGS += ' -e' 
     CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
     CFLAGS += ' -Ol'    
     CFLAGS += ' --use_c++_inline'
         
@@ -122,5 +122,5 @@ elif PLATFORM == 'iar':
     LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
     LFLAGS += ' --entry __iar_program_start'    
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = ''

bsp/stm32f10x/project.uvprojx

@@ -212,7 +212,7 @@
             <hadIRAM2>0</hadIRAM2>
             <hadIROM2>0</hadIROM2>
             <StupSel>8</StupSel>
-            <useUlib>1</useUlib>
+            <useUlib>0</useUlib>
             <EndSel>0</EndSel>
             <uLtcg>0</uLtcg>
             <RoSelD>3</RoSelD>

bsp/stm32f10x/rtconfig.py

@@ -31,7 +31,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
+	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
 
 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -117,7 +117,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --cpu=Cortex-M3' 
     CFLAGS += ' -e' 
     CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
     CFLAGS += ' -Ol'    
     CFLAGS += ' --use_c++_inline'
         
@@ -133,5 +133,5 @@ elif PLATFORM == 'iar':
     LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
     LFLAGS += ' --entry __iar_program_start'    
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = ''

bsp/stm32f10x/template.uvprojx

@@ -215,7 +215,7 @@
             <hadIRAM2>0</hadIRAM2>
             <hadIROM2>0</hadIROM2>
             <StupSel>8</StupSel>
-            <useUlib>1</useUlib>
+            <useUlib>0</useUlib>
             <EndSel>0</EndSel>
             <uLtcg>0</uLtcg>
             <RoSelD>3</RoSelD>

bsp/stm32f20x/rtconfig.py

@@ -16,7 +16,7 @@ elif CROSS_TOOL == 'keil':
 	EXEC_PATH 	= 'C:/Keil'
 elif CROSS_TOOL == 'iar':
 	PLATFORM 	= 'iar'
-	IAR_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'	
+	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'	
 
 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -101,7 +101,7 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --cpu=Cortex-M3' 
     CFLAGS += ' -e' 
     CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
     CFLAGS += ' -Ol'    
         
     AFLAGS = ''
@@ -115,5 +115,5 @@ elif PLATFORM == 'iar':
     LFLAGS += ' --semihosting' 
     LFLAGS += ' --entry __iar_program_start'    
 
-    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = ''

bsp/stm32f40x/.config

@@ -58,7 +58,8 @@ CONFIG_ARCH_ARM_CORTEX_M4=y
 #
 # RT-Thread Components
 #
-# CONFIG_RT_USING_COMPONENTS_INIT is not set
+CONFIG_RT_USING_COMPONENTS_INIT=y
+# CONFIG_RT_USING_USER_MAIN is not set
 
 #
 # C++ features
@@ -74,6 +75,7 @@ CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
 CONFIG_FINSH_USING_SYMTAB=y
 CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
 CONFIG_FINSH_THREAD_PRIORITY=20
 CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_CMD_SIZE=80
@@ -302,12 +304,12 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_FASTLZ is not set
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
 
 #
 # example package: hello
 #
 # CONFIG_PKG_USING_HELLO is not set
-# CONFIG_PKG_USING_MULTIBUTTON is not set
 CONFIG_SOC_STM32F4=y
 CONFIG_RT_USING_UART1=y
 CONFIG_RT_USING_UART2=y

bsp/stm32f40x/applications/application.c

@@ -34,32 +34,14 @@
 
 void rt_init_thread_entry(void* parameter)
 {
+    /* initialization RT-Thread Components */
+    rt_components_init();
+	
     /* GDB STUB */
 #ifdef RT_USING_GDB
     gdb_set_device("uart6");
     gdb_start();
 #endif
-
-    /* LwIP Initialization */
-#ifdef RT_USING_LWIP
-    {
-        extern void lwip_sys_init(void);
-
-        /* register ethernetif device */
-        eth_system_device_init();
-
-        rt_hw_stm32_eth_init();
-
-        /* init lwip system */
-        lwip_sys_init();
-        rt_kprintf("TCP/IP initialized!\n");
-    }
-#endif
-
-#ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
-#endif
 }
 
 int rt_application_init()

bsp/stm32f40x/drivers/board.c

@@ -93,12 +93,11 @@ void rt_hw_board_init()
     /* Configure the SysTick */
     SysTick_Configuration();
 
-    stm32_hw_usart_init();
-    stm32_hw_pin_init();
-    
+    rt_components_board_init();
+ 
 #ifdef RT_USING_CONSOLE
     rt_console_set_device(CONSOLE_DEVICE);
-#endif
+#endif	
 }
 
 /*@}*/

bsp/stm32f40x/drivers/stm32f4xx_eth.c

@@ -4156,3 +4156,4 @@ void rt_hw_stm32_eth_init(void)
             rt_thread_startup(tid);
     }
 }
+INIT_PREV_EXPORT(rt_hw_stm32_eth_init);