[bsp][hpmicro] upgrade to bsp v1.10.0, add hpm6p00evk and hpm5e00evk support

- upgraded bsp to v1.10.0
- moved hpm_sdk to rt-thread package
- added support for hpm6p00evk and hpm5e00evk

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>

.github/ALL_BSP_COMPILE.json

@@ -424,7 +424,9 @@
         "hpmicro/hpm5300evk",
         "hpmicro/hpm5301evklite",
         "hpmicro/hpm6800evk",
-        "hpmicro/hpm6e00evk"
+        "hpmicro/hpm6e00evk",
+        "hpmicro/hpm6p00evk",
+        "hpmicro/hpm5e00evk"
       ]
     },
     {

bsp/hpmicro/.ignore_format.yml

@@ -4,11 +4,24 @@
 
 dir_path:
   - hpm6200evk/startup
+  - hpm6200evk/board
   - hpm6300evk/startup
+  - hpm6300evk/board
   - hpm6750evk/startup
+  - hpm6750evk/board
   - hpm6750evk2/startup
+  - hpm6750evk2/board
   - hpm6750evkmini/startup
+  - hpm6750evkmini/board
   - hpm5300evk/startup
+  - hpm5300evk/board
   - hpm5301evklite/startup
+  - hpm5301evklite/board
   - hpm6800evk/startup
-  - libraries/hpm_sdk
+  - hpm6800evk/board
+  - hpm6e00evk/startup
+  - hpm6e00evk/board
+  - hpm6p00evk/startup
+  - hpm6p00evk/board
+  - hpm5e00evk/startup
+  - hpm5e00evk/board

bsp/hpmicro/README.md

@@ -0,0 +1,193 @@
+# HPMicro Board Support Package (BSP) Introduction
+
+[中文页](README_zh.md) |
+
+## Introduction
+
+This document provides an overview of the HPMicro BSPs (Board Support Package) available in the RT-Thread repository. Each BSP is tailored for specific HPMicro development boards, offering necessary drivers and configurations to run RT-Thread seamlessly on RISC-V based HPMicro microcontrollers.
+
+The document consists of the following parts:
+
+- HPMicro BSP Overview
+- Available BSPs
+- Quick Start Guide
+- Common Development Environment Setup
+- References
+
+By reading the Quick Start Guide section, developers can quickly get their hands on any HPMicro BSP and run RT-Thread on the board. Each individual BSP contains detailed documentation for specific board features and advanced usage.
+
+## Available BSPs
+
+Below is a comprehensive list of HPMicro BSPs currently supported:
+
+| BSP Name | Supported Board | MCU | Description |
+|----------|-----------------|-----|-------------|
+| hpm5300evk | HPM5300EVK | HPM5361 | Development board for HPM5300 series |
+| hpm5301evklite | HPM5301EVKLITE | HPM5301 | Lite version development board for HPM5301 |
+| hpm5e00evk | HPM5E00EVK | HPM5E31 | Development board for HPM5E00 series |
+| hpm6200evk | HPM6200EVK | HPM6200 | Development board for HPM6200 series |
+| hpm6300evk | HPM6300EVK | HPM6360 | Development board for HPM6300 series with Ethernet support |
+| hpm6750evk | HPM6750EVK | HPM6750 | Development board for HPM6750 series with dual-core RISC-V |
+| hpm6750evk2 | HPM6750EVK2 | HPM6750 | Second generation development board for HPM6750 series |
+| hpm6750evkmini | HPM6750EVKMINI | HPM6750 | Mini development board for HPM6750 series |
+| hpm6800evk | HPM6800EVK | HPM6800 | Development board for HPM6800 series |
+| hpm6e00evk | HPM6E00EVK | HPM6E00 | Development board for HPM6E00 series |
+| hpm6p00evk | HPM6P00EVK | HPM6P00 | Development board for HPM6P00 series |
+
+## Quick Start Guide
+
+### Prerequisites
+
+Before getting started with any HPMicro BSP, you need to prepare the following development environment:
+
+#### 1. RT-Thread ENV
+- Download and install [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+
+#### 2. RISC-V Toolchain
+- Download the RISC-V toolchain: [riscv32-gnu-toolchain](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
+- Extract it to a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain`
+- Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin`
+  - For example: `C:\DevTools\riscv32-gnu-toolchain\bin`
+
+#### 3. OpenOCD for HPMicro
+- Download OpenOCD: [rtt-debugger-support-package](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
+- Extract it to a specified directory, for example: `C:\DevTools\openocd-hpmicro`
+- Set environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin`
+  - For example: `C:\DevTools\openocd-hpmicro\bin`
+
+### Getting Started with a Specific BSP
+
+1. **Navigate to the desired BSP directory**:
+   ```bash
+   cd rt-thread/bsp/hpmicro/<bsp_name>
+   ```
+
+2. **Configure the project**:
+   - Open RT-Thread ENV command-line
+   - Change directory to the BSP directory
+   - Run `menuconfig` to configure the project
+
+3. **Build the project**:
+   ```bash
+   scons -jN  # N equals to the number of CPU cores
+   ```
+
+4. **Hardware Connection**:
+   - Switch BOOT pin to 2'b00
+   - Connect the `PWR_DEBUG` port to PC via TYPE-C cable
+
+5. **Download and Debug**:
+   - Use the provided OpenOCD scripts for downloading and debugging
+   - Refer to individual BSP README files for specific commands
+
+### Running Results
+
+Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically.
+
+Connect the serial port of the board to the PC, communicate with it via a serial terminal tool (115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed:
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.2.2 build Aug 16 2025 18:18:18
+ 2006 - 2025 Copyright by RT-Thread team
+msh >
+```
+
+## Common Peripheral Support
+
+Most HPMicro BSPs support the following peripherals:
+
+| **On-board Peripherals** | **Support** | **Note** |
+| ------------------------ | ----------- | -------- |
+| USB                      | √           |          |
+| QSPI Flash               | √           |          |
+| GPIO                     | √           |          |
+| SPI                      | √           |          |
+| I2C                      | √           |          |
+| UART                     | √           |          |
+| PWM                      | √           |          |
+| RTC                      | √           |          |
+| On-Board Debugger        | √           | ft2232   |
+
+Additional peripherals may be supported depending on the specific board:
+- **Ethernet**: Available on 
+  - HPM6300EVK
+  - HPM6750EVK
+  - HPM6750EVK2
+  - HPM6750EVKMINI + ART-Pi Industry IO extension
+  - HPM6800EVK
+  - HPM6E00EVK
+  - HPM6P00EVK
+  - HPM5E00EVK
+- **CAN**: Available on HPM6750 series Development Boards, HPM5300EVK, HPM6800EVK, HPM6E00EVK, HPM6P00EVK and HPM5E00EVK
+- **SDIO**: Available on HPM6300EVK, HPM6750EVKMINI, HPM6750EVK, HPM6750EVK2 and HPM6800EVK
+- **Display/Audio**: Available on HPM6750EVK, HPM6800EVK, HPM6E00EVK，HPM6P00EVK
+
+## Development Environment Setup
+
+
+### Using Command Line Tools
+
+1. Set up the environment variables as described in the Prerequisites section
+2. Use `scons` for building
+3. Use OpenOCD and GDB for debugging or use the Ozone + JLink for debugging
+
+## Individual BSP Documentation
+
+Each BSP contains its own detailed README file with:
+- Board-specific hardware information
+- Peripheral configuration details
+- Specific download and debug commands
+- Advanced features and examples
+
+Please refer to the individual BSP directories for detailed documentation:
+- `hpm5300evk/README.md`
+- `hpm5301evklite/README.md`
+- `hpm5e00evk/README.md`
+- `hpm6200evk/README.md`
+- `hpm6300evk/README.md`
+- `hpm6750evk/README.md`
+- `hpm6750evk2/README.md`
+- `hpm6750evkmini/README.md`
+- `hpm6800evk/README.md`
+- `hpm6e00evk/README.md`
+- `hpm6p00evk/README.md`
+
+## Troubleshooting
+
+### Common Issues
+
+1. **Toolchain not found**: Ensure `RTT_RISCV_TOOLCHAIN` environment variable is set correctly
+2. **OpenOCD connection failed**: Check USB connection and driver installation
+3. **Build errors**: Verify all dependencies are installed and environment variables are set
+4. **Serial communication issues**: Check baud rate (115200) and COM port settings
+
+### Getting Help
+
+- Check the individual BSP README files for board-specific issues
+- Visit [RT-Thread Community](https://club.rt-thread.org/)
+- Refer to [RT-Thread Documentation](https://www.rt-thread.org/document/site/)
+
+## References
+
+- [RT-Thread Document Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
+- [RT-Thread ENV](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
+- [HPMicro Official Website](https://www.hpmicro.com/)
+- [HPMicro SDK Documentation](https://hpmicro.github.io/)
+- [RISC-V Toolchain](https://github.com/riscv/riscv-gnu-toolchain)
+
+## Contributing
+
+Contributions to enhance existing BSPs or add new ones are welcome. Please follow the RT-Thread contribution guidelines and ensure that your BSP adheres to the project's standards.
+
+For contributing to HPMicro BSPs:
+1. Fork the `RT-Thread` repository
+2. Create a feature branch
+3. Make your changes following the existing code style
+4. Test your changes thoroughly
+5. Submit a pull request with a clear description
+
+## License
+
+This BSP is released under the [RT-Thread license](https://github.com/RT-Thread/rt-thread/blob/master/LICENSE).

bsp/hpmicro/README_zh.md

@@ -0,0 +1,192 @@
+# HPMicro 板级支持包 (BSP) 介绍
+
+[English](README.md) |
+
+## 简介
+
+本文档提供了 RT-Thread 仓库中可用的 HPMicro BSP（板级支持包）的概述。每个 BSP 都针对特定的 HPMicro 开发板进行了定制，提供必要的驱动程序和配置，以便在基于 RISC-V 的 HPMicro 微控制器上无缝运行 RT-Thread。
+
+本文档包含以下部分：
+
+- HPMicro BSP 概述
+- 可用的 BSP
+- 快速开始指南
+- 通用开发环境设置
+- 参考资料
+
+通过阅读快速开始指南部分，开发者可以快速上手任何 HPMicro BSP 并在开发板上运行 RT-Thread。每个单独的 BSP 都包含特定开发板功能和高级用法的详细文档。
+
+## 可用的 BSP
+
+以下是当前支持的 HPMicro BSP 的完整列表：
+
+| BSP 名称 | 支持的开发板 | MCU | 描述 |
+|----------|-------------|-----|------|
+| hpm5300evk | HPM5300EVK | HPM5361 | HPM5300 系列开发板 |
+| hpm5301evklite | HPM5301EVKLITE | HPM5301 | HPM5301精简版开发板 |
+| hpm5e00evk | HPM5E00EVK | HPM5E31 | HPM5E00 系列开发板 |
+| hpm6200evk | HPM6200EVK | HPM6200 | HPM6200 系列开发板 |
+| hpm6300evk | HPM6300EVK | HPM6360 | HPM6300 系列开发板，支持以太网 |
+| hpm6750evk | HPM6750EVK | HPM6750 | HPM6750 系列开发板，双核 RISC-V |
+| hpm6750evk2 | HPM6750EVK2 | HPM6750 | HPM6750 系列第二代开发板 |
+| hpm6750evkmini | HPM6750EVKMINI | HPM6750 | HPM6750 系列迷你开发板 |
+| hpm6800evk | HPM6800EVK | HPM6800 | HPM6800 系列开发板 |
+| hpm6e00evk | HPM6E00EVK | HPM6E00 | HPM6E00 系列开发板 |
+| hpm6p00evk | HPM6P00EVK | HPM6P00 | HPM6P00 系列开发板 |
+
+## 快速开始指南
+
+### 前提条件
+
+在开始使用任何 HPMicro BSP 之前，您需要准备以下开发环境：
+
+#### 1. RT-Thread ENV
+- 下载并安装 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+
+#### 2. RISC-V 工具链
+- 下载 RISC-V 工具链：[riscv32-gnu-toolchain](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
+- 解压到指定目录，例如：`C:\DevTools\riscv32-gnu-toolchain`
+- 设置环境变量 `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`
+  - 例如：`C:\DevTools\riscv32-gnu-toolchain\bin`
+
+#### 3. HPMicro 专用 OpenOCD
+- 下载 OpenOCD：[rtt-debugger-support-package](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
+- 解压到指定目录，例如：`C:\DevTools\openocd-hpmicro`
+- 设置环境变量 `OPENOCD_HPMICRO` 为 `<OPENOCD_HPMICRO_DIR>\bin`
+  - 例如：`C:\DevTools\openocd-hpmicro\bin`
+
+### 使用特定 BSP 开始
+
+1. **导航到所需的 BSP 目录**：
+   ```bash
+   cd rt-thread/bsp/hpmicro/<bsp_name>
+   ```
+
+2. **配置项目**：
+   - 打开 RT-Thread ENV 命令行
+   - 切换到 BSP 目录
+   - 运行 `menuconfig` 来配置项目
+
+3. **构建项目**：
+   ```bash
+   scons -jN  # N 等于 CPU 核心数
+   ```
+
+4. **硬件连接**：
+   - 将 BOOT 引脚切换到 2'b00
+   - 通过 TYPE-C 线缆将 `PWR_DEBUG` 端口连接到 PC
+
+5. **下载和调试**：
+   - 使用提供的 OpenOCD 脚本进行下载和调试
+   - 参考各个 BSP 的 README 文件获取具体命令
+
+### 运行结果
+
+项目成功下载后，系统会自动运行。开发板上的 LED 会周期性闪烁。
+
+将开发板的串口连接到 PC，通过串口终端工具（115200-8-1-N）与其通信。重置开发板后，将观察到 RT-Thread 的启动信息：
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.2.2 build Aug 16 2025 18:18:18
+ 2006 - 2025 Copyright by RT-Thread team
+msh >
+```
+
+## 通用外设支持
+
+大多数 HPMicro BSP 支持以下外设：
+
+| **板载外设** | **支持** | **备注** |
+| ------------ | -------- | -------- |
+| USB          | √        |          |
+| QSPI Flash   | √        |          |
+| GPIO         | √        |          |
+| SPI          | √        |          |
+| I2C          | √        |          |
+| UART         | √        |          |
+| PWM          | √        |          |
+| RTC          | √        |          |
+| 板载调试器   | √        | ft2232   |
+
+根据特定开发板，可能支持其他外设：
+- **以太网**：在如下开发板上可用
+  - HPM6300EVK
+  - HPM6750EVK
+  - HPM6750EVK2
+  - HPM6750EVKMINI + ART-Pi Industry IO 扩展板
+  - HPM6800EVK
+  - HPM6E00EVK
+  - HPM6P00EVK
+  - HPM5E00EVK
+- **CAN**：HPM5300EVK、HPM6750系列开发板，HPM6300EVK，HPM6800EVK, HPM6E00EVK, HPM6P00EVK 和HPM5E00EVK
+- **SDIO**：HPM6300EVK、HPM6750EVK 系列可用
+- **显示/音频**：HPM6750EVK 系列可用
+
+## 开发环境设置
+
+### 使用命令行工具
+
+1. 按照前提条件部分所述设置环境变量
+2. 使用 `scons` 进行构建
+3. 使用 OpenOCD 和 GDB 进行调试
+
+## 各个 BSP 文档
+
+每个 BSP 都包含自己的详细 README 文件，内容包括：
+- 特定开发板的硬件信息
+- 外设配置详情
+- 具体的下载和调试命令
+- 高级功能和示例
+
+请参考各个 BSP 目录获取详细文档：
+- `hpm5300evk/README.md`
+- `hpm5301evklite/README.md`
+- `hpm5e00evk/README.md`
+- `hpm6200evk/README.md`
+- `hpm6300evk/README.md`
+- `hpm6750evk/README.md`
+- `hpm6750evk2/README.md`
+- `hpm6750evkmini/README.md`
+- `hpm6800evk/README.md`
+- `hpm6e00evk/README.md`
+- `hpm6p00evk/README.md`
+
+## 故障排除
+
+### 常见问题
+
+1. **找不到工具链**：确保 `RTT_RISCV_TOOLCHAIN` 环境变量设置正确
+2. **OpenOCD 连接失败**：检查 USB 连接和驱动程序安装
+3. **构建错误**：验证所有依赖项已安装且环境变量已设置
+4. **串口通信问题**：检查波特率（115200）和 COM 端口设置
+
+### 获取帮助
+
+- 查看各个 BSP 的 README 文件了解特定开发板的问题
+- 访问 [RT-Thread 社区](https://club.rt-thread.org/)
+- 参考 [RT-Thread 文档](https://www.rt-thread.org/document/site/)
+
+## 参考资料
+
+- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
+- [RT-Thread ENV](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
+- [HPMicro 官方网站](https://www.hpmicro.com/)
+- [HPMicro SDK 文档](https://hpmicro.github.io/)
+- [RISC-V 工具链](https://github.com/riscv/riscv-gnu-toolchain)
+
+## 贡献
+
+欢迎对增强现有 BSP 或添加新 BSP 做出贡献。请遵循 RT-Thread 贡献指南，确保您的 BSP 符合项目标准。
+
+为 HPMicro BSP 做出贡献：
+1. Fork `RT-Thread` 仓库
+2. 创建功能分支
+3. 按照现有代码风格进行更改
+4. 彻底测试您的更改
+5. 提交带有清晰描述的拉取请求
+
+## 许可证
+
+此 BSP 在 [RT-Thread 许可证](https://github.com/RT-Thread/rt-thread/blob/master/LICENSE) 下发布。

bsp/hpmicro/hpm5300evk/.config

@@ -104,8 +104,6 @@
 #
 # CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set
 # end of rt_strnlen options
-
-# CONFIG_RT_UTEST_TC_USING_KLIBC is not set
 # end of klibc options
 
 CONFIG_RT_NAME_MAX=8
@@ -183,6 +181,9 @@ CONFIG_RT_VER_NUM=0x50201
 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
 # end of RT-Thread Kernel
 
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV32=y
+
 #
 # RT-Thread Components
 #
@@ -199,6 +200,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20
 CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
+# CONFIG_FINSH_USING_WORD_OPERATION is not set
 CONFIG_FINSH_USING_SYMTAB=y
 CONFIG_FINSH_CMD_SIZE=80
 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
@@ -376,6 +378,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FREEMODBUS is not set
 # CONFIG_PKG_USING_NANOPB is not set
 # CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
+# CONFIG_PKG_USING_ESP_HOSTED is not set
 
 #
 # Wi-Fi
@@ -483,6 +486,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_QMODBUS is not set
 # CONFIG_PKG_USING_PNET is not set
 # CONFIG_PKG_USING_OPENER is not set
+# CONFIG_PKG_USING_FREEMQTT is not set
 # end of IoT - internet of things
 
 #
@@ -572,6 +576,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # tools packages
 #
 # CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_MCOREDUMP is not set
 # CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
@@ -617,6 +622,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ZDEBUG is not set
 # CONFIG_PKG_USING_RVBACKTRACE is not set
 # CONFIG_PKG_USING_HPATCHLITE is not set
+# CONFIG_PKG_USING_THREAD_METRIC is not set
 # end of tools packages
 
 #
@@ -710,6 +716,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_RMP is not set
 # CONFIG_PKG_USING_R_RHEALSTONE is not set
 # CONFIG_PKG_USING_HEARTBEAT is not set
+# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
 # end of system packages
 
 #
@@ -791,6 +798,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 
 # CONFIG_PKG_USING_NRF5X_SDK is not set
 # CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set
 # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
 # CONFIG_PKG_USING_MM32 is not set
 
@@ -833,6 +842,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # HC32 DDL Drivers
 #
+# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set
+# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set
 # end of HC32 DDL Drivers
 
 #
@@ -846,6 +859,31 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set
 # CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set
 # end of NXP HAL & SDK Drivers
+
+#
+# NUVOTON Drivers
+#
+# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set
+# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set
+# end of NUVOTON Drivers
+
+#
+# GD32 Drivers
+#
+# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set
+# end of GD32 Drivers
+
+#
+# HPMicro SDK
+#
+CONFIG_PKG_USING_HPM_SDK=y
+CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk"
+# CONFIG_PKG_USING_HPM_SDK_V110 is not set
+CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y
+CONFIG_PKG_HPM_SDK_VER="latest"
+# end of HPMicro SDK
 # end of HAL & SDK Drivers
 
 #
@@ -1017,6 +1055,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_SEAN_WS2812B is not set
 # CONFIG_PKG_USING_IC74HC165 is not set
 # CONFIG_PKG_USING_IST8310 is not set
+# CONFIG_PKG_USING_ST7789_SPI is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set
 # end of peripheral libraries and drivers
 
@@ -1355,20 +1394,28 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # end of Arduino libraries
 # end of RT-Thread online packages
 
+CONFIG_SOC_HPM5300_SERIES=y
+
 #
 # Hardware Drivers Config
 #
-CONFIG_SOC_HPM5000=y
+CONFIG_SOC_HPM5300=y
 
 #
 # On-chip Peripheral Drivers
 #
 CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_GPIO_IRQ_PRIORITY=1
 CONFIG_BSP_USING_UART=y
 CONFIG_BSP_USING_UART0=y
 CONFIG_BSP_UART0_RX_BUFSIZE=128
 CONFIG_BSP_UART0_TX_BUFSIZE=0
+CONFIG_BSP_UART0_IRQ_PRIORITY=1
 # CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+# CONFIG_BSP_USING_UART4 is not set
+# CONFIG_BSP_USING_UART5 is not set
+# CONFIG_BSP_USING_UART6 is not set
 # CONFIG_BSP_USING_UART7 is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_GPTMR is not set

bsp/hpmicro/hpm5300evk/SConstruct

@@ -55,17 +55,6 @@ GDB = rtconfig.GDB
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 
-hpm_library = 'hpm_sdk'
-rtconfig.BSP_LIBRARY_TYPE = hpm_library
-
-# include soc
-objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript')))
-
-# include libraries
-objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
-
-# include components
-objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript')))
 
 
 # includes rtt drivers

bsp/hpmicro/hpm5300evk/board/Kconfig

@@ -1,8 +1,8 @@
 menu "Hardware Drivers Config"
 
-config SOC_HPM5000
+config SOC_HPM5300
     bool
-    select SOC_SERIES_HPM5300
+    select SOC_HPM5300_SERIES
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
     default y
@@ -12,6 +12,12 @@ menu "On-chip Peripheral Drivers"
         bool "Enable GPIO"
         select RT_USING_PIN if BSP_USING_GPIO
         default n
+        if BSP_USING_GPIO
+            config BSP_GPIO_IRQ_PRIORITY
+            int "GPIO Interrupt Priority"
+            range 1 7
+            default 1
+        endif
 
     menuconfig BSP_USING_UART
         bool "Enable UART"
@@ -41,6 +47,10 @@ menu "On-chip Peripheral Drivers"
                         range 0 65535
                         depends on RT_USING_SERIAL_V2
                         default 0
+                    config BSP_UART0_IRQ_PRIORITY
+                        int "UART0 Interrupt Priority"
+                        range 1 7
+                        default 1
                 endif
             menuconfig BSP_USING_UART2
                 bool "Enable UART2"
@@ -64,6 +74,118 @@ menu "On-chip Peripheral Drivers"
                         range 0 65535
                         depends on RT_USING_SERIAL_V2
                         default 0
+                    config BSP_UART2_IRQ_PRIORITY
+                        int "UART2 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            menuconfig BSP_USING_UART3
+                bool "Enable UART3"
+                default n
+                if BSP_USING_UART3
+                    config BSP_UART3_RX_USING_DMA
+                        bool "Enable UART3 RX DMA"
+                        depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART3_TX_USING_DMA
+                        bool "Enable UART3 TX DMA"
+                        depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART3_RX_BUFSIZE
+                        int "Set UART3 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 1024
+                    config BSP_UART3_TX_BUFSIZE
+                        int "Set UART3 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                    config BSP_UART3_IRQ_PRIORITY
+                        int "UART3 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            menuconfig BSP_USING_UART4
+                bool "Enable UART4"
+                default n
+                if BSP_USING_UART4
+                    config BSP_UART4_RX_USING_DMA
+                        bool "Enable UART4 RX DMA"
+                        depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART4_TX_USING_DMA
+                        bool "Enable UART4 TX DMA"
+                        depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART4_RX_BUFSIZE
+                        int "Set UART4 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 1024
+                    config BSP_UART4_TX_BUFSIZE
+                        int "Set UART4 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                    config BSP_UART4_IRQ_PRIORITY
+                        int "UART4 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            menuconfig BSP_USING_UART5
+                bool "Enable UART5"
+                default n
+                if BSP_USING_UART5
+                    config BSP_UART5_RX_USING_DMA
+                        bool "Enable UART5 RX DMA"
+                        depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART5_TX_USING_DMA
+                        bool "Enable UART5 TX DMA"
+                        depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART5_RX_BUFSIZE
+                        int "Set UART5 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 1024
+                    config BSP_UART5_TX_BUFSIZE
+                        int "Set UART5 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                    config BSP_UART5_IRQ_PRIORITY
+                        int "UART5 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            menuconfig BSP_USING_UART6
+                bool "Enable UART6"
+                default n
+                if BSP_USING_UART6
+                    config BSP_UART6_RX_USING_DMA
+                        bool "Enable UART6 RX DMA"
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART6_TX_USING_DMA
+                        bool "Enable UART6 TX DMA"
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART6_RX_BUFSIZE
+                        int "Set UART6 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 1024
+                    config BSP_UART6_TX_BUFSIZE
+                        int "Set UART6 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                    config BSP_UART6_IRQ_PRIORITY
+                        int "UART6 Interrupt Priority"
+                        range 1 7
+                        default 1
                 endif
             menuconfig BSP_USING_UART7
                 bool "Enable UART7"
@@ -95,29 +217,125 @@ menu "On-chip Peripheral Drivers"
         default n
         select RT_USING_SPI if BSP_USING_SPI
         if BSP_USING_SPI
+            config BSP_USING_SPI0
+                bool "Enable SPI0"
+                default n
+                if BSP_USING_SPI0
+                    config BSP_SPI0_USING_DMA
+                        bool "Enable SPI0 DMA"
+                        default n
+                    config BSP_SPI0_IRQ_PRIORITY
+                        int "SPI0 Interrupt Priority"
+                        range 1 7
+                        default 1
+                    choice
+                        prompt "Select SPI0 CS TYPE"
+                        default BSP_SPI0_USING_SOFT_CS
+                        config BSP_SPI0_USING_SOFT_CS
+                            bool "Enable SPI0 software cs"
+                        config BSP_SPI0_USING_HARD_CS
+                            bool "Enable SPI0 hardware cs"
+                    endchoice
+                    choice
+                        prompt "Select SPI0 IO mode"
+                        default BSP_SPI0_USING_SINGLE_IO
+                        config BSP_SPI0_USING_SINGLE_IO
+                            bool "Enable SPI0 single IO mode"
+                        config BSP_SPI0_USING_DUAL_IO
+                            bool "Enable SPI0 dual IO mode"
+                        config BSP_SPI0_USING_QUAD_IO
+                            bool "Enable SPI0 quad IO mode"
+                    endchoice
+                endif
             config BSP_USING_SPI1
                 bool "Enable SPI1"
                 default y
                 if BSP_USING_SPI1
                     config BSP_SPI1_USING_DMA
-                    bool "Enable SPI1 DMA"
-                    default n
+                        bool "Enable SPI1 DMA"
+                        default n
+                    config BSP_SPI1_IRQ_PRIORITY
+                        int "SPI1 Interrupt Priority"
+                        range 1 7
+                        default 1
+                    choice
+                        prompt "Select SPI1 CS TYPE"
+                        default BSP_SPI1_USING_SOFT_CS
+                        config BSP_SPI1_USING_SOFT_CS
+                            bool "Enable SPI1 software cs"
+                        config BSP_SPI1_USING_HARD_CS
+                            bool "Enable SPI1 hardware cs"
+                    endchoice
+                    choice
+                        prompt "Select SPI1 IO mode"
+                        default BSP_SPI1_USING_SINGLE_IO
+                        config BSP_SPI1_USING_SINGLE_IO
+                            bool "Enable SPI1 single IO mode"
+                        config BSP_SPI1_USING_DUAL_IO
+                            bool "Enable SPI1 dual IO mode"
+                        config BSP_SPI1_USING_QUAD_IO
+                            bool "Enable SPI1 quad IO mode"
+                    endchoice
                 endif
             config BSP_USING_SPI2
                 bool "Enable SPI2"
                 default n
                 if BSP_USING_SPI2
                     config BSP_SPI2_USING_DMA
-                    bool "Enable SPI2 DMA"
-                    default n
+                        bool "Enable SPI2 DMA"
+                        default n
+                    config BSP_SPI2_IRQ_PRIORITY
+                        int "SPI2 Interrupt Priority"
+                        range 1 7
+                        default 1
+                    choice
+                        prompt "Select SPI2 CS TYPE"
+                        default BSP_SPI2_USING_SOFT_CS
+                        config BSP_SPI2_USING_SOFT_CS
+                            bool "Enable SPI2 software cs"
+                        config BSP_SPI2_USING_HARD_CS
+                            bool "Enable SPI2 hardware cs"
+                    endchoice
+                    choice
+                        prompt "Select SPI2 IO mode"
+                        default BSP_SPI2_USING_SINGLE_IO
+                        config BSP_SPI2_USING_SINGLE_IO
+                            bool "Enable SPI2 single IO mode"
+                        config BSP_SPI2_USING_DUAL_IO
+                            bool "Enable SPI2 dual IO mode"
+                        config BSP_SPI2_USING_QUAD_IO
+                            bool "Enable SPI2 quad IO mode"
+                    endchoice
                 endif
             config BSP_USING_SPI3
                 bool "Enable SPI3"
                 default n
                 if BSP_USING_SPI3
                     config BSP_SPI3_USING_DMA
-                    bool "Enable SPI3 DMA"
-                    default n
+                        bool "Enable SPI3 DMA"
+                        default n
+                    config BSP_SPI3_IRQ_PRIORITY
+                        int "SPI3 Interrupt Priority"
+                        range 1 7
+                        default 1
+                    choice
+                        prompt "Select SPI3 CS TYPE"
+                        default BSP_SPI3_USING_SOFT_CS
+                        config BSP_SPI3_USING_SOFT_CS
+                            bool "Enable SPI3 software cs"
+                        config BSP_SPI3_USING_HARD_CS
+                            bool "Enable SPI3 hardware cs"
+                    endchoice
+                    choice
+                        prompt "Select SPI3 IO mode"
+                        default BSP_SPI3_USING_SINGLE_IO
+                        config BSP_SPI3_USING_SINGLE_IO
+                            bool "Enable SPI3 single IO mode"
+                        config BSP_SPI3_USING_DUAL_IO
+                            bool "Enable SPI3 dual IO mode"
+                        config BSP_SPI3_USING_QUAD_IO
+                            bool "Enable SPI3 quad IO mode"
+                    endchoice
                 endif
         endif
 
@@ -126,35 +344,98 @@ menu "On-chip Peripheral Drivers"
         default n
         select RT_USING_HWTIMER if BSP_USING_GPTMR
         if BSP_USING_GPTMR
+            config BSP_USING_GPTMR0
+                bool "Enable GPTMR0"
+                depends on !HPM_USING_VECTOR_PREEMPTED_MODE
+                default n
+                if BSP_USING_GPTMR0
+                    config BSP_GPTMR0_IRQ_PRIORITY
+                    int "GPTMR0 Interrupt Priority"
+                    range 1 7
+                    default 1
+                endif
             config BSP_USING_GPTMR1
                 bool "Enable GPTMR1"
                 default n
+                if BSP_USING_GPTMR1
+                    config BSP_GPTMR1_IRQ_PRIORITY
+                    int "GPTMR1 Interrupt Priority"
+                    range 1 7
+                    default 1
+                endif
             config BSP_USING_GPTMR2
                 bool "Enable GPTMR2"
                 default n
+                if BSP_USING_GPTMR2
+                    config BSP_GPTMR2_IRQ_PRIORITY
+                    int "GPTMR2 Interrupt Priority"
+                    range 1 7
+                    default 1
+                endif
+            config BSP_USING_GPTMR3
+                bool "Enable GPTMR3"
+                default n
+                if BSP_USING_GPTMR3
+                    config BSP_GPTMR3_IRQ_PRIORITY
+                    int "GPTMR3 Interrupt Priority"
+                    range 1 7
+                    default 1
+                endif
         endif
 
     menuconfig BSP_USING_I2C
         bool "Enable I2C"
         default n
+        select RT_USING_I2C if BSP_USING_I2C
         if BSP_USING_I2C
             config BSP_USING_I2C0
                 bool "Enable I2C0"
                 default y
-            if BSP_USING_I2C0
-                config BSP_I2C0_USING_DMA
-                    bool "Enable I2C0 DMA"
-                    default n
-            endif
-
+                if BSP_USING_I2C0
+                    config BSP_I2C0_USING_DMA
+                        bool "Enable I2C0 DMA"
+                        default n
+                    config BSP_I2C0_IRQ_PRIORITY
+                        int "I2C0 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            config BSP_USING_I2C1
+                bool "Enable I2C1"
+                default n
+                if BSP_USING_I2C1
+                    config BSP_I2C1_USING_DMA
+                        bool "Enable I2C1 DMA"
+                        default n
+                    config BSP_I2C1_IRQ_PRIORITY
+                        int "I2C1 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            config BSP_USING_I2C2
+                bool "Enable I2C2"
+                default n
+                if BSP_USING_I2C2
+                    config BSP_I2C2_USING_DMA
+                        bool "Enable I2C2 DMA"
+                        default n
+                    config BSP_I2C2_IRQ_PRIORITY
+                        int "I2C2 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
             config BSP_USING_I2C3
                 bool "Enable I2C3"
                 default n
-            if BSP_USING_I2C3
-                config BSP_I2C3_USING_DMA
-                    bool "Enable I2C3 DMA"
-                    default n
-            endif
+                if BSP_USING_I2C3
+                    config BSP_I2C3_USING_DMA
+                        bool "Enable I2C3 DMA"
+                        default n
+                    config BSP_I2C3_IRQ_PRIORITY
+                        int "I2C3 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
         endif
 
     menuconfig BSP_USING_XPI_FLASH
@@ -165,6 +446,7 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_PWM
         bool "Enable PWM"
         default n
+        select RT_USING_PWM if BSP_USING_PWM
 
     menuconfig BSP_USING_USB
        bool "Enable USB"
@@ -172,6 +454,7 @@ menu "On-chip Peripheral Drivers"
        if BSP_USING_USB
             config BSP_USING_USB_DEVICE
                 bool "Enable USB Device"
+                select RT_USING_CACHE
                 default n
             config BSP_USING_USB_HOST
                 bool "Enable USB HOST"
@@ -200,15 +483,39 @@ menu "On-chip Peripheral Drivers"
             config BSP_USING_MCAN0
                 bool "Enable MCAN0"
                 default n
+                if BSP_USING_MCAN0
+                    config BSP_MCAN0_IRQ_PRIORITY
+                        int "MCAN0 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
             config BSP_USING_MCAN1
                 bool "Enable MCAN1"
                 default n
+                if BSP_USING_MCAN1
+                    config BSP_MCAN1_IRQ_PRIORITY
+                        int "MCAN1 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
             config BSP_USING_MCAN2
                 bool "Enable MCAN2"
                 default n
+                if BSP_USING_MCAN2
+                    config BSP_MCAN2_IRQ_PRIORITY
+                        int "MCAN2 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
             config BSP_USING_MCAN3
                 bool "Enable MCAN3"
                 default n
+                if BSP_USING_MCAN3
+                    config BSP_MCAN3_IRQ_PRIORITY
+                        int "MCAN3 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
         endif
 
     menuconfig BSP_USING_ADC
@@ -226,11 +533,7 @@ menu "On-chip Peripheral Drivers"
                 config BSP_USING_ADC1
                     bool "Enable ADC1"
                     default n
-                config BSP_USING_ADC2
-                    bool "Enable ADC2"
-                    default n
             endif
         endif
 endmenu
-
 endmenu

bsp/hpmicro/hpm5300evk/board/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023 HPMicro
+ * Copyright (c) 2023-2025 HPMicro
  * SPDX-License-Identifier: BSD-3-Clause
  *
  */
@@ -13,8 +13,8 @@
 #include "hpm_pllctlv2_drv.h"
 #include "hpm_i2c_drv.h"
 #include "hpm_pcfg_drv.h"
+#include <rtconfig.h>
 
-static board_timer_cb timer_cb;
 
 /**
  * @brief FLASH configuration option definitions:
@@ -49,7 +49,7 @@ static board_timer_cb timer_cb;
  *      2 - Internal loopback
  *      3 - External DQS
  *    [3:0] Frequency option
- *      1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+ *      1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 114MHz / 7 - 133MHz / 8 - 166MHz
  *
  * option[2] (Effective only if the bit[3:0] in option[0] > 1)
  *    [31:20]  Reserved
@@ -70,11 +70,11 @@ static board_timer_cb timer_cb;
  *      0 - 4MB / 1 - 8MB / 2 - 16MB
  */
 #if defined(FLASH_XIP) && FLASH_XIP
-__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90002, 0x00000006, 0x1000, 0x0};
+__attribute__ ((section(".nor_cfg_option"), used)) const uint32_t option[4] = {0xfcf90002, 0x00000005, 0x1000, 0x0};
 #endif
 
 #if defined(FLASH_UF2) && FLASH_UF2
-ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
+ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
 #endif
 
 void board_init_console(void)
@@ -89,8 +89,6 @@ void board_init_console(void)
      */
     init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE);
 
-    /* Configure the UART clock to 24MHz */
-    clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U);
     clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0);
 
     cfg.type = BOARD_CONSOLE_TYPE;
@@ -143,7 +141,6 @@ void board_print_clock_freq(void)
 
 void board_init(void)
 {
-    init_xtal_pins();
     init_py_pins_as_pgpio();
     board_init_usb_dp_dm_pins();
 
@@ -176,7 +173,7 @@ void board_init_usb_dp_dm_pins(void)
     } else {
         uint8_t tmp;
         tmp = sysctl_resource_target_get_mode(HPM_SYSCTL, sysctl_resource_xtal);
-        sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03);
+        sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03);    /* NOLINT */
         clock_add_to_group(clock_usb0, 0);
         usb_phy_disable_dp_dm_pulldown(HPM_USB0);
         clock_remove_from_group(clock_usb0, 0);
@@ -205,67 +202,26 @@ void board_init_clock(void)
     clock_add_to_group(clock_lmm0, 0);
     clock_add_to_group(clock_mchtmr0, 0);
     clock_add_to_group(clock_rom, 0);
-    clock_add_to_group(clock_can0, 0);
-    clock_add_to_group(clock_can1, 0);
-    clock_add_to_group(clock_can2, 0);
-    clock_add_to_group(clock_can3, 0);
-    clock_add_to_group(clock_ptpc, 0);
-    clock_add_to_group(clock_gptmr0, 0);
-    clock_add_to_group(clock_gptmr1, 0);
-    clock_add_to_group(clock_gptmr2, 0);
-    clock_add_to_group(clock_gptmr3, 0);
-    clock_add_to_group(clock_i2c0, 0);
-    clock_add_to_group(clock_i2c1, 0);
-    clock_add_to_group(clock_i2c2, 0);
-    clock_add_to_group(clock_i2c3, 0);
-    clock_add_to_group(clock_spi0, 0);
-    clock_add_to_group(clock_spi1, 0);
-    clock_add_to_group(clock_spi2, 0);
-    clock_add_to_group(clock_spi3, 0);
-    clock_add_to_group(clock_uart0, 0);
-    clock_add_to_group(clock_uart1, 0);
-    clock_add_to_group(clock_uart2, 0);
-    clock_add_to_group(clock_uart3, 0);
-    clock_add_to_group(clock_uart4, 0);
-    clock_add_to_group(clock_uart5, 0);
-    clock_add_to_group(clock_uart6, 0);
-    /* group0[1] */
-    clock_add_to_group(clock_uart7, 0);
-    clock_add_to_group(clock_watchdog0, 0);
-    clock_add_to_group(clock_watchdog1, 0);
-    clock_add_to_group(clock_mbx0, 0);
-    clock_add_to_group(clock_tsns, 0);
-    clock_add_to_group(clock_crc0, 0);
-    clock_add_to_group(clock_adc0, 0);
-    clock_add_to_group(clock_adc1, 0);
-    clock_add_to_group(clock_dac0, 0);
-    clock_add_to_group(clock_dac1, 0);
-    clock_add_to_group(clock_acmp, 0);
-    clock_add_to_group(clock_opa0, 0);
-    clock_add_to_group(clock_opa1, 0);
     clock_add_to_group(clock_mot0, 0);
-    clock_add_to_group(clock_rng, 0);
-    clock_add_to_group(clock_sdp, 0);
-    clock_add_to_group(clock_kman, 0);
     clock_add_to_group(clock_gpio, 0);
     clock_add_to_group(clock_hdma, 0);
     clock_add_to_group(clock_xpi0, 0);
-    clock_add_to_group(clock_usb0, 0);
+    clock_add_to_group(clock_ptpc, 0);
 
     /* Connect Group0 to CPU0 */
     clock_connect_group_to_cpu(0, 0);
 
-    /* Bump up DCDC voltage to 1175mv */
-    pcfg_dcdc_set_voltage(HPM_PCFG, 1175);
+    /* Bump up DCDC voltage to 1275mv */
+    pcfg_dcdc_set_voltage(HPM_PCFG, 1275);
 
     /* Configure CPU to 480MHz, AXI/AHB to 160MHz */
     sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll0_clk0, 2, 3);
     /* Configure PLL0 Post Divider */
-    pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0);    /* PLL0CLK0: 960MHz */
-    pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 1, 3);    /* PLL0CLK1: 600MHz */
-    pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 2, 7);    /* PLL0CLK2: 400MHz */
+    pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk0, pllctlv2_div_1p0);    /* PLL0CLK0: 960MHz */
+    pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk1, pllctlv2_div_1p6);    /* PLL0CLK1: 600MHz */
+    pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk2, pllctlv2_div_2p4);    /* PLL0CLK2: 400MHz */
     /* Configure PLL0 Frequency to 960MHz */
-    pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, 960000000);
+    pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll0, 960000000);
 
     clock_update_core_clock();
 
@@ -283,6 +239,9 @@ void board_delay_ms(uint32_t ms)
     clock_cpu_delay_ms(ms);
 }
 
+#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT
+static board_timer_cb timer_cb;
+SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr)
 void board_timer_isr(void)
 {
     if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
@@ -290,7 +249,6 @@ void board_timer_isr(void)
         timer_cb();
     }
 }
-SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr);
 
 void board_timer_create(uint32_t ms, board_timer_cb cb)
 {
@@ -310,6 +268,7 @@ void board_timer_create(uint32_t ms, board_timer_cb cb)
 
     gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
 }
+#endif
 
 void board_init_gpio_pins(void)
 {
@@ -323,15 +282,19 @@ void board_init_led_pins(void)
     gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level());
 }
 
-void board_init_usb_pins(void)
+void board_init_usb(USB_Type *ptr)
 {
-    init_usb_pins();
-    usb_hcd_set_power_ctrl_polarity(BOARD_USB, true);
-    /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */
-    board_delay_ms(100);
+    if (ptr == HPM_USB0) {
+        init_usb_pins(ptr);
+        clock_add_to_group(clock_usb0, 0);
+
+        usb_hcd_set_power_ctrl_polarity(ptr, true);
+        /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */
+        board_delay_ms(100);
 
-    /* As QFN32, QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */
-    /* usb_phy_using_internal_vbus(BOARD_USB); */
+        /* As QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */
+        /* usb_phy_using_internal_vbus(ptr); */
+    }
 }
 
 void board_led_write(uint8_t state)
@@ -383,18 +346,12 @@ void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
                                      GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
 }
 
-void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
-{
-    (void) usb_index;
-    (void) level;
-}
-
-uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
+uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus)
 {
     uint32_t freq = 0;
 
-    if (ptr == HPM_ADC0) {
-        if (clk_src_ahb) {
+    if (ptr == (void *)HPM_ADC0) {
+        if (clk_src_bus) {
             /* Configure the ADC clock from AHB (@200MHz by default)*/
             clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
         } else {
@@ -402,10 +359,10 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
             clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
             clock_set_source_divider(clock_ana0, clk_src_pll0_clk2, 2U);
         }
-
+        clock_add_to_group(clock_adc0, 0);
         freq = clock_get_frequency(clock_adc0);
-    } else if (ptr == HPM_ADC1) {
-        if (clk_src_ahb) {
+    } else if (ptr == (void *)HPM_ADC1) {
+        if (clk_src_bus) {
             /* Configure the ADC clock from AHB (@200MHz by default)*/
             clock_set_adc_source(clock_adc1, clk_adc_src_ahb0);
         } else {
@@ -413,7 +370,7 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
             clock_set_adc_source(clock_adc1, clk_adc_src_ana1);
             clock_set_source_divider(clock_ana1, clk_src_pll0_clk2, 2U);
         }
-
+        clock_add_to_group(clock_adc1, 0);
         freq = clock_get_frequency(clock_adc1);
     }
 
@@ -425,6 +382,17 @@ void board_init_adc16_pins(void)
     init_adc_pins();
 }
 
+void board_init_acmp_pins(void)
+{
+    init_acmp_pins();
+}
+
+void board_init_acmp_clock(ACMP_Type *ptr)
+{
+    (void)ptr;
+    clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1);
+}
+
 uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb)
 {
     uint32_t freq = 0;
@@ -438,7 +406,7 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb)
             clock_set_dac_source(clock_dac0, clk_dac_src_ana2);
             clock_set_source_divider(clock_ana2, clk_src_pll0_clk1, 2);
         }
-
+        clock_add_to_group(clock_dac0, 0);
         freq = clock_get_frequency(clock_dac0);
     } else if (ptr == HPM_DAC1) {
         if (clk_src_ahb == true) {
@@ -449,7 +417,7 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb)
             clock_set_dac_source(clock_dac1, clk_dac_src_ana3);
             clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2);
         }
-
+        clock_add_to_group(clock_dac1, 0);
         freq = clock_get_frequency(clock_dac1);
     }
 
@@ -487,17 +455,6 @@ uint32_t board_init_can_clock(MCAN_Type *ptr)
     return freq;
 }
 
-uint32_t board_init_pwm_clock(PWM_Type *ptr)
-{
-    uint32_t freq = 0;
-    (void) ptr;
-
-    clock_add_to_group(clock_mot0, 0);
-    freq = clock_get_frequency(clock_mot0);
-
-    return freq;
-}
-
 void board_init_rgb_pwm_pins(void)
 {
     init_led_pins_as_pwm();
@@ -536,26 +493,19 @@ uint32_t board_init_uart_clock(UART_Type *ptr)
 {
     uint32_t freq = 0U;
     if (ptr == HPM_UART0) {
-        clock_set_source_divider(clock_uart0, clk_src_osc24m, 1);
         clock_add_to_group(clock_uart0, 0);
         freq = clock_get_frequency(clock_uart0);
     } else if (ptr == HPM_UART1) {
-        clock_set_source_divider(clock_uart1, clk_src_osc24m, 1);
         clock_add_to_group(clock_uart1, 0);
         freq = clock_get_frequency(clock_uart1);
     } else if (ptr == HPM_UART2) {
-        clock_set_source_divider(clock_uart2, clk_src_pll0_clk2, 8);
         clock_add_to_group(clock_uart2, 0);
         freq = clock_get_frequency(clock_uart2);
     } else if (ptr == HPM_UART3) {
-        clock_set_source_divider(clock_uart3, clk_src_pll0_clk2, 8);
         clock_add_to_group(clock_uart3, 0);
         freq = clock_get_frequency(clock_uart3);
-    } else if (ptr == HPM_UART7) {
-        clock_set_source_divider(clock_uart7, clk_src_pll0_clk2, 6); /* 80MHz */
-        clock_add_to_group(clock_uart7, 0);
-        freq = clock_get_frequency(clock_uart7);
     }
+
     return freq;
 }
 
@@ -577,39 +527,51 @@ void board_i2c_bus_clear(I2C_Type *ptr)
         printf("I2C bus is ready\n");
         return;
     }
-    i2s_gen_reset_signal(ptr, 9);
+    i2c_gen_reset_signal(ptr, 9);
     board_delay_ms(100);
     printf("I2C bus is cleared\n");
 }
 
+uint32_t board_init_i2c_clock(I2C_Type *ptr)
+{
+    uint32_t freq = 0;
+
+    if (ptr == HPM_I2C0) {
+        clock_add_to_group(clock_i2c0, 0);
+        freq = clock_get_frequency(clock_i2c0);
+    } else if (ptr == HPM_I2C1) {
+        clock_add_to_group(clock_i2c1, 0);
+        freq = clock_get_frequency(clock_i2c1);
+    } else if (ptr == HPM_I2C2) {
+        clock_add_to_group(clock_i2c2, 0);
+        freq = clock_get_frequency(clock_i2c2);
+    } else if (ptr == HPM_I2C3) {
+        clock_add_to_group(clock_i2c3, 0);
+        freq = clock_get_frequency(clock_i2c3);
+    } else {
+        ;
+    }
+
+    return freq;
+}
+
 void board_init_i2c(I2C_Type *ptr)
 {
     i2c_config_t config;
     hpm_stat_t stat;
     uint32_t freq;
-    if (ptr == NULL) {
-        return;
-    }
+
+    freq = board_init_i2c_clock(ptr);
     init_i2c_pins(ptr);
     board_i2c_bus_clear(ptr);
-
-    clock_add_to_group(clock_i2c0, 0);
-    clock_add_to_group(clock_i2c1, 0);
-    clock_add_to_group(clock_i2c2, 0);
-    clock_add_to_group(clock_i2c3, 0);
-    /* Configure the I2C clock to 24MHz */
-    clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U);
-
     config.i2c_mode = i2c_mode_normal;
     config.is_10bit_addressing = false;
-    freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME);
     stat = i2c_init_master(ptr, freq, &config);
     if (stat != status_success) {
-        printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr);
+        printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr);
         while (1) {
         }
     }
-
 }
 
 void board_init_adc_qeiv2_pins(void)
@@ -629,34 +591,37 @@ void board_lin_transceiver_control(bool enable)
     }
 }
 
+void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp)
+{
+    init_gptmr_channel_pin(ptr, channel, as_comp);
+}
+
+void board_init_clk_ref_pin(void)
+{
+    init_clk_ref_pin();
+}
+
 uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
 {
-    uint32_t freq = 0;
-    clock_name_t gptmr_clock =0;
-    uint32_t HPM_GPTMR = (uint32_t)ptr;
-    bool gptmr_valid = true;
-
-    switch(HPM_GPTMR){
-        case HPM_GPTMR0_BASE:
-            gptmr_clock = clock_gptmr0;
-            break;
-        case HPM_GPTMR1_BASE:
-            gptmr_clock = clock_gptmr1;
-            break;
-        case HPM_GPTMR2_BASE:
-            gptmr_clock = clock_gptmr2;
-            break;
-        case HPM_GPTMR3_BASE:
-            gptmr_clock = clock_gptmr3;
-            break;
-        default:
-            gptmr_valid = false;
-    }
-    if(gptmr_valid)
-    {
-        clock_add_to_group(gptmr_clock, 0);
-        clock_set_source_divider(gptmr_clock, clk_src_pll1_clk1, 4);
-        freq = clock_get_frequency(gptmr_clock);
+    uint32_t freq = 0U;
+    if (ptr == HPM_GPTMR0) {
+        clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_gptmr0);
+    } else if (ptr == HPM_GPTMR1) {
+        clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_gptmr1);
+    } else if (ptr == HPM_GPTMR2) {
+        clock_add_to_group(clock_gptmr2, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_gptmr2);
+    } else if (ptr == HPM_GPTMR3) {
+        clock_add_to_group(clock_gptmr3, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_gptmr3);
+    } else if (ptr == HPM_PTMR) {
+        clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_ptmr);
+    } else {
+        /* Not supported */
     }
     return freq;
 }
+

bsp/hpmicro/hpm5300evk/board/board.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024 HPMicro
+ * Copyright (c) 2023-2025 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -23,6 +23,7 @@
 
 /* ACMP desction */
 #define BOARD_ACMP             HPM_ACMP
+#define BOARD_ACMP_CLK         clock_acmp0
 #define BOARD_ACMP_CHANNEL     ACMP_CHANNEL_CHN1
 #define BOARD_ACMP_IRQ         IRQn_ACMP_1
 #define BOARD_ACMP_PLUS_INPUT  ACMP_INPUT_DAC_OUT  /* use internal DAC */
@@ -41,14 +42,24 @@
 
 /* uart section */
 #ifndef BOARD_APP_UART_BASE
-#define BOARD_APP_UART_BASE HPM_UART2
-#define BOARD_APP_UART_IRQ  IRQn_UART2
+#define BOARD_APP_UART_BASE       HPM_UART2
+#define BOARD_APP_UART_IRQ        IRQn_UART2
 #define BOARD_APP_UART_BAUDRATE   (115200UL)
 #define BOARD_APP_UART_CLK_NAME   clock_uart2
 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART2_RX
 #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART2_TX
 #endif
 
+#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PA26
+
+/* Trigger UART: UART0~3 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG0, UART4~7 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 */
+#define BOARD_APP_UART_TRIG HPM_TRGM0_OUTPUT_SRC_UART_TRIG0
+#define BOARD_UART_TRGM                     HPM_TRGM0
+#define BOARD_UART_TRGM_GPTMR               HPM_GPTMR3
+#define BOARD_UART_TRGM_GPTMR_CLK           clock_gptmr3
+#define BOARD_UART_TRGM_GPTMR_CH            2
+#define BOARD_UART_TRGM_GPTMR_INPUT         HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2
+
 /* uart lin sample section */
 #define BOARD_UART_LIN          HPM_UART3
 #define BOARD_UART_LIN_IRQ      IRQn_UART3
@@ -56,7 +67,6 @@
 #define BOARD_UART_LIN_TX_PORT  GPIO_DI_GPIOA
 #define BOARD_UART_LIN_TX_PIN   (15U) /* PA15 should align with used pin in pinmux configuration */
 
-
 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
 #ifndef BOARD_CONSOLE_TYPE
 #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART
@@ -64,9 +74,9 @@
 
 #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
 #ifndef BOARD_CONSOLE_UART_BASE
-#define BOARD_CONSOLE_UART_BASE     HPM_UART0
-#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0
-#define BOARD_CONSOLE_UART_IRQ      IRQn_UART0
+#define BOARD_CONSOLE_UART_BASE       HPM_UART0
+#define BOARD_CONSOLE_UART_CLK_NAME   clock_uart0
+#define BOARD_CONSOLE_UART_IRQ        IRQn_UART0
 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX
 #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX
 #endif
@@ -82,6 +92,8 @@
 
 /* rtthread-nano finsh section */
 #define BOARD_RT_CONSOLE_BASE        BOARD_CONSOLE_UART_BASE
+#define BOARD_RT_CONSOLE_CLK_NAME    BOARD_CONSOLE_UART_CLK_NAME
+#define BOARD_RT_CONSOLE_IRQ         BOARD_CONSOLE_UART_IRQ
 
 /* modbus sample section */
 #define BOARD_MODBUS_UART_BASE       BOARD_APP_UART_BASE
@@ -126,13 +138,12 @@
 
 /* 12V Power Enable for lin transceiver */
 #define BOARD_SUPPORT_LIN_TRANSCEIVER_CONTROL 1
-#define BOARD_12V_EN_GPIO_CTRL  HPM_GPIO0
-#define BOARD_12V_EN_GPIO_INDEX GPIO_DI_GPIOA
-#define BOARD_12V_EN_GPIO_PIN   24
-#define BOARD_LIN_TRANSCEIVER_GPIO_CTRL  HPM_GPIO0
-#define BOARD_LIN_TRANSCEIVER_GPIO_INDEX GPIO_DI_GPIOA
-#define BOARD_LIN_TRANSCEIVER_GPIO_PIN   13
-
+#define BOARD_12V_EN_GPIO_CTRL                HPM_GPIO0
+#define BOARD_12V_EN_GPIO_INDEX               GPIO_DI_GPIOA
+#define BOARD_12V_EN_GPIO_PIN                 24
+#define BOARD_LIN_TRANSCEIVER_GPIO_CTRL       HPM_GPIO0
+#define BOARD_LIN_TRANSCEIVER_GPIO_INDEX      GPIO_DI_GPIOA
+#define BOARD_LIN_TRANSCEIVER_GPIO_PIN        13
 
 /* gpiom section */
 #define BOARD_APP_GPIOM_BASE            HPM_GPIOM
@@ -144,6 +155,7 @@
 #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOA
 #define BOARD_APP_GPIO_PIN   9
 #define BOARD_APP_GPIO_IRQ   IRQn_GPIO0_A
+#define BOARD_BUTTON_PRESSED_VALUE 0
 
 /* spi section */
 #define BOARD_APP_SPI_BASE              HPM_SPI1
@@ -164,12 +176,14 @@
 #define BOARD_APP_ADC16_IRQn     IRQn_ADC0
 #define BOARD_APP_ADC16_CH_1     (13U)
 #define BOARD_APP_ADC16_CLK_NAME (clock_adc0)
+#define BOARD_APP_ADC16_CLK_BUS  (clk_adc_src_ahb0)
 
-#define BOARD_APP_ADC16_HW_TRIG_SRC     HPM_PWM0
-#define BOARD_APP_ADC16_HW_TRGM         HPM_TRGM0
-#define BOARD_APP_ADC16_HW_TRGM_IN      HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
-#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI
-#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A
+#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_mot0
+#define BOARD_APP_ADC16_HW_TRIG_SRC          HPM_PWM0
+#define BOARD_APP_ADC16_HW_TRGM              HPM_TRGM0
+#define BOARD_APP_ADC16_HW_TRGM_IN           HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
+#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ      TRGM_TRGOCFG_ADC0_STRGI
+#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT      TRGM_TRGOCFG_ADCX_PTRGI0A
 
 #define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A
 
@@ -206,6 +220,7 @@
 #define BOARD_APP_TRGM            HPM_TRGM0
 #define BOARD_APP_PWM_IRQ         IRQn_PWM0
 #define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM0_SYNCI
+#define BOARD_APP_TRGM_PWM_INPUT  HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0
 
 /*BLDC pwm*/
 /*PWM define*/
@@ -231,15 +246,16 @@
 /*HALL define*/
 
 /*RDC*/
+#define BOARD_RDC_BASE            HPM_RDC
 #define BOARD_RDC_TRGM            HPM_TRGM0
-#define BOARD_RDC_TRGIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_RDC_TRGO_0
-#define BOARD_RDC_TRG_NUM         TRGM_TRGOCFG_MOT_GPIO0
-#define BOARD_RDC_TRG_ADC_NUM     TRGM_TRGOCFG_ADCX_PTRGI0A
+#define BOARD_RDC_TRG_IN          HPM_TRGM0_INPUT_SRC_RDC_TRGO_0
+#define BOARD_RDC_TRG_OUT         TRGM_TRGOCFG_MOT_GPIO0
+#define BOARD_RDC_TRG_ADC         TRGM_TRGOCFG_ADCX_PTRGI0A
 #define BOARD_RDC_ADC_I_BASE      HPM_ADC0
 #define BOARD_RDC_ADC_Q_BASE      HPM_ADC1
 #define BOARD_RDC_ADC_I_CHN       (5U)
 #define BOARD_RDC_ADC_Q_CHN       (6U)
-#define BOARD_RDC_ADC_IRQn        IRQn_ADC0
+#define BOARD_RDC_IRQ        IRQn_RDC
 #define BOARD_RDC_ADC_TRIG_FLAG   adc16_event_trig_complete
 #define BOARD_RDC_ADC_TRG         ADC16_CONFIG_TRG0A
 
@@ -250,16 +266,44 @@
 #define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U)
 #define BOARD_BLDC_QEI_CLOCK_SOURCE              clock_mot0
 #define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV   (4000U)
-#define BOARD_BLDC_QEI_ADC_MATRIX_ADC0           trgm_adc_matrix_output_to_qei1_adc0
-#define BOARD_BLDC_QEI_ADC_MATRIX_ADC1           trgm_adc_matrix_output_to_qei1_adc1
+
+#define BOARD_APP_QEIV2_BASE                  HPM_QEI1
+#define BOARD_APP_QEIV2_IRQ                   IRQn_QEI1
+#define BOARD_APP_QEI_CLOCK_SOURCE            clock_mot0
+#define BOARD_APP_QEI_ADC_COS_BASE            HPM_ADC0
+#define BOARD_APP_QEI_ADC_COS_CHN             (4U)
+#define BOARD_APP_QEI_ADC_SIN_BASE            HPM_ADC1
+#define BOARD_APP_QEI_ADC_SIN_CHN             (5U)
+#define BOARD_APP_QEI_ADC_MATRIX_TO_ADC0      trgm_adc_matrix_output_to_qei1_adc0
+#define BOARD_APP_QEI_ADC_MATRIX_TO_ADC1      trgm_adc_matrix_output_to_qei1_adc1
+#define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_COS trgm_adc_matrix_in_from_adc0
+#define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_SIN trgm_adc_matrix_in_from_adc1
+#define BOARD_APP_QEI_TRG_ADC                 TRGM_TRGOCFG_ADCX_PTRGI0A
 
 /*Timer define*/
 #define BOARD_BLDC_TMR_1MS    HPM_GPTMR2
 #define BOARD_BLDC_TMR_CH     0
 #define BOARD_BLDC_TMR_CMP    0
 #define BOARD_BLDC_TMR_IRQ    IRQn_GPTMR2
+#define BOARD_BLDC_TMR_CLOCK  clock_gptmr2
 #define BOARD_BLDC_TMR_RELOAD (100000U)
 
+/* BLDC PARAM */
+#define BOARD_BLDC_BLOCK_SPEED_KP (0.0005f)
+#define BOARD_BLDC_BLOCK_SPEED_KI (0.000009f)
+
+#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KP (0.0074f)
+#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KI (0.0001f)
+#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KP (0.05f)
+#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KI (0.001f)
+#define BOARD_BLDC_SW_FOC_POSITION_KP (154.7f)
+#define BOARD_BLDC_SW_FOC_POSITION_KI (0.113f)
+
+#define BOARD_BLDC_HFI_SPEED_LOOP_KP (40.0f)
+#define BOARD_BLDC_HFI_SPEED_LOOP_KI (0.015f)
+#define BOARD_BLDC_HFI_PLL_KP (10.0f)
+#define BOARD_BLDC_HFI_PLL_KI (1.0f)
+
 /*adc*/
 #define BOARD_BLDC_ADC_MODULE    (ADCX_MODULE_ADC16)
 #define BOARD_BLDC_ADC_U_BASE    HPM_ADC0
@@ -275,23 +319,38 @@
 #define BOARD_BLDC_ADC_TRG                    ADC16_CONFIG_TRG0A
 #define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN       (1U)
 #define BOARD_BLDC_PWM_TRIG_CMP_INDEX         (8U)
-#define BOARD_BLDC_TRIGMUX_IN_NUM             HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
-#define BOARD_BLDC_TRG_NUM                    TRGM_TRGOCFG_ADCX_PTRGI0A
+#define BOARD_BLDC_TRG_ADC                    TRGM_TRGOCFG_ADCX_PTRGI0A
+#define BOARD_BLDC_PWM_TRG_ADC                HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
+#define BOARD_BLDC_DMA_MUX_SRC                HPM_DMA_SRC_MOT_0
+#define BOARD_BLDC_DMA_CHN                    (0U)
+#define BOARD_BLDC_DMA_TRG_DST                TRGM_TRGOCFG_TRGM_DMA0
+#define BOARD_BLDC_DMA_TRG_SRC                HPM_TRGM0_DMA_SRC_TRGM0
+#define BOARD_BLDC_DMA_TRG_INDEX              TRGM_DMACFG_0
+#define BOARD_BLDC_DMA_TRG_CMP_INDEX          (9U)
+#define BOARD_BLDC_DMA_TRG_IN                 HPM_TRGM0_INPUT_SRC_PWM0_CH9REF
+
+/* PLB */
+#define BOARD_PLB_CLOCK_NAME           clock_mot0
 
 #define BOARD_PLB_COUNTER              HPM_PLB
 #define BOARD_PLB_PWM_BASE             HPM_PWM0
 #define BOARD_PLB_PWM_CLOCK_NAME       clock_mot0
 #define BOARD_PLB_TRGM                 HPM_TRGM0
 #define BOARD_PLB_PWM_TRG              (HPM_TRGM0_INPUT_SRC_PWM0_CH8REF)
-#define BOARD_PLB_IN_PWM_TRG_NUM       (TRGM_TRGOCFG_PLB_IN_00)
-#define BOARD_PLB_IN_PWM_PULSE_TRG_NUM (TRGM_TRGOCFG_PLB_IN_02)
-#define BOARD_PLB_OUT_TRG              (HPM_TRGM0_INPUT_SRC_PLB_OUT00)
-#define BOARD_PLB_IO_TRG_NUM           (TRGM_TRGOCFG_MOT_GPIO2)
+#define BOARD_PLB_IN_PWM_TRG           (TRGM_TRGOCFG_PLB_IN_00)
+#define BOARD_PLB_IN_PWM_PULSE_TRG     (TRGM_TRGOCFG_PLB_IN_02)
+#define BOARD_PLB_CLR_SIGNAL_INPUT     (HPM_TRGM0_INPUT_SRC_PLB_OUT16)
+#define BOARD_PLB_TO_TRG_IN            (HPM_TRGM0_INPUT_SRC_PLB_OUT00)
+#define BOARD_PLB_TRG_OUT              (HPM_TRGM0_OUTPUT_SRC_TRGM0_P2)
 #define BOARD_PLB_IO_TRG_SHIFT         (2)
 #define BOARD_PLB_PWM_CMP              (8U)
 #define BOARD_PLB_PWM_CHN              (8U)
 #define BOARD_PLB_CHN                  plb_chn0
 
+#define BOARD_PLB_FILTER_SIG_INPUT_SOURCE  HPM_TRGM0_INPUT_SRC_TRGM0_P4
+#define BOARD_PLB_FILTER_SIG_OUTUPT_SOURCE HPM_TRGM0_OUTPUT_SRC_MOT_GPIO2
+#define BOARD_PLB_FILTER_IO_TRG_SHIFT      (2)
+
 /* QEO */
 #define BOARD_QEO          HPM_QEO0
 #define BOARD_QEO_TRGM_POS trgm_pos_matrix_output_to_qeo0
@@ -302,13 +361,12 @@
 /* SEI */
 #define BOARD_SEI      HPM_SEI
 #define BOARD_SEI_CTRL SEI_CTRL_1
-#define BOARD_SEI_IRQn IRQn_SEI1
-
-/* USB */
-#define BOARD_USB HPM_USB0
+#define BOARD_SEI_IRQn IRQn_SEI0_1
+#define BOARD_SEI_CLOCK_NAME clock_mot0
 
 /* OPAMP */
-#define BOARD_APP_OPAMP HPM_OPAMP0
+#define BOARD_APP_OPAMP       HPM_OPAMP0
+#define BOARD_APP_OPAMP_CLOCK clock_opa0
 
 #ifndef BOARD_SHOW_CLOCK
 #define BOARD_SHOW_CLOCK 1
@@ -323,11 +381,62 @@
 #define BOARD_FREERTOS_TIMER_IRQ      IRQn_GPTMR2
 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr2
 
+#define BOARD_FREERTOS_TICK_SRC_PWM          HPM_PWM0
+#define BOARD_FREERTOS_TICK_SRC_PWM_IRQ      IRQn_PWM0
+#define BOARD_FREERTOS_TICK_SRC_PWM_CLK_NAME clock_mot0
+
+#define BOARD_FREERTOS_LOWPOWER_TIMER          HPM_PTMR
+#define BOARD_FREERTOS_LOWPOWER_TIMER_CHANNEL  1
+#define BOARD_FREERTOS_LOWPOWER_TIMER_IRQ      IRQn_PTMR
+#define BOARD_FREERTOS_LOWPOWER_TIMER_CLK_NAME clock_ptmr
+
 /* Threadx Definitions */
-#define BOARD_THREADX_TIMER           HPM_GPTMR2
-#define BOARD_THREADX_TIMER_CHANNEL   1
-#define BOARD_THREADX_TIMER_IRQ       IRQn_GPTMR2
-#define BOARD_THREADX_TIMER_CLK_NAME  clock_gptmr2
+#define BOARD_THREADX_TIMER          HPM_GPTMR2
+#define BOARD_THREADX_TIMER_CHANNEL  1
+#define BOARD_THREADX_TIMER_IRQ      IRQn_GPTMR2
+#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr2
+
+#define BOARD_THREADX_LOWPOWER_TIMER          HPM_PTMR
+#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL  1
+#define BOARD_THREADX_LOWPOWER_TIMER_IRQ      IRQn_PTMR
+#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr
+
+/* uC/OS-III Definitions */
+#define BOARD_UCOS_TIMER          HPM_GPTMR2
+#define BOARD_UCOS_TIMER_CHANNEL  1
+#define BOARD_UCOS_TIMER_IRQ      IRQn_GPTMR2
+#define BOARD_UCOS_TIMER_CLK_NAME clock_gptmr2
+
+/* i2s over spi Section*/
+#define BOARD_I2S_SPI_CS_GPIO_CTRL  HPM_GPIO0
+#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOA
+#define BOARD_I2S_SPI_CS_GPIO_PIN   11
+#define BOARD_I2S_SPI_CS_GPIO_PAD   IOC_PAD_PA11
+
+#define BOARD_GPTMR_I2S_MCLK          HPM_GPTMR0
+#define BOARD_GPTMR_I2S_MCLK_CHANNEL  3
+#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr0
+
+#define BOARD_GPTMR_I2S_LRCK          HPM_GPTMR0
+#define BOARD_GPTMR_I2S_LRCK_CHANNEL  1
+#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr0
+
+#define BOARD_GPTMR_I2S_BCLK          HPM_GPTMR0
+#define BOARD_GPTMR_I2S_BLCK_CHANNEL  0
+#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr0
+
+#define BOARD_GPTMR_I2S_FINSH          HPM_GPTMR0
+#define BOARD_GPTMR_I2S_FINSH_IRQ      IRQn_GPTMR0
+#define BOARD_GPTMR_I2S_FINSH_CHANNEL  2
+#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr0
+
+#define BOARD_APP_CLK_REF_PIN_NAME "P1[15] (PA30)"
+#define BOARD_APP_CLK_REF_CLK_NAME clock_ref0
+#define BOARD_APP_CLK_REF_SRC_NAME clk_src_pll1_clk1
+#define BOARD_APP_PLLCTLV2_TEST_PLL pllctlv2_pll1
+#define BOARD_APP_PLLCTLV2_TEST_PLL_CLK pllctlv2_clk1
+#define BOARD_APP_PLLCTLV2_TEST_PLL_NAME clk_pll1clk1
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
@@ -338,16 +447,17 @@ void board_init(void);
 void board_init_console(void);
 void board_init_gpio_pins(void);
 void board_init_led_pins(void);
-void board_init_usb_pins(void);
+void board_init_usb(USB_Type *ptr);
 void board_led_write(uint8_t state);
 void board_led_toggle(void);
 void board_init_uart(UART_Type *ptr);
 uint32_t board_init_spi_clock(SPI_Type *ptr);
 void board_init_spi_pins(SPI_Type *ptr);
-void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level);
-uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb);
+uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus);
 void board_init_adc16_pins(void);
 uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb);
+void board_init_acmp_pins(void);
+void board_init_acmp_clock(ACMP_Type *ptr);
 void board_init_can(MCAN_Type *ptr);
 uint32_t board_init_can_clock(MCAN_Type *ptr);
 void board_init_rgb_pwm_pins(void);
@@ -372,13 +482,17 @@ void board_init_pmp(void);
 uint32_t board_init_uart_clock(UART_Type *ptr);
 void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx);
 
+uint32_t board_init_i2c_clock(I2C_Type *ptr);
 void board_init_i2c(I2C_Type *ptr);
 
 void board_init_adc_qeiv2_pins(void);
 
 void board_lin_transceiver_control(bool enable);
+
+void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp);
+void board_init_clk_ref_pin(void);
 uint32_t board_init_gptmr_clock(GPTMR_Type *ptr);
-uint32_t board_init_pwm_clock(PWM_Type *ptr);
+
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */

bsp/hpmicro/hpm5300evk/board/linker_scripts/flash_rtt.ld → bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/flash_rtt.ld

@@ -1,5 +1,5 @@
 /*
- * Copyright 2021-2023 HPMicro
+ * Copyright 2021-2025 HPMicro
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
@@ -14,7 +14,7 @@ MEMORY
 {
     XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
     ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K
-    DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K
+    DLM (w) : ORIGIN = 0x00080300, LENGTH = 128K - 768
     AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K
 }
 
@@ -41,22 +41,25 @@ SECTIONS
     .start __app_load_addr__ : {
         . = ALIGN(8);
         KEEP(*(.start))
+        . = ALIGN(16);
     } > XPI0
 
-    __vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
+     __vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
     .vectors : AT(__vector_load_addr__) {
-        . = ALIGN(8);
+        . = ALIGN(16);
         __vector_ram_start__ = .;
         KEEP(*(.vector_table))
         KEEP(*(.isr_vector))
-        . = ALIGN(8);
+        . = ALIGN(16);
         __vector_ram_end__ = .;
     } > ILM
 
-    .fast : AT(etext + __data_end__ - __tdata_start__) {
-        . = ALIGN(8);
+    .fast : AT(__fast_load_addr__) {
+        . = ALIGN(16);
         __ramfunc_start__ = .;
         *(.fast)
+        *(.fast.*)
+        . = ALIGN(16);
 
         /* RT-Thread Core Start */
         KEEP(*context_gcc.o(.text* .rodata*))
@@ -77,12 +80,12 @@ SECTIONS
         KEEP(*mempool.o (.text .text* .rodata .rodata*))
         /* RT-Thread Core End */
 
-        . = ALIGN(8);
+        . = ALIGN(16);
         __ramfunc_end__ = .;
     } > ILM
 
-    .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
-        . = ALIGN(8);
+    .text (__vector_load_addr__ + SIZEOF(.vectors)) : {
+        . = ALIGN(16);
         *(.text)
         *(.text*)
         *(.rodata)
@@ -107,12 +110,6 @@ SECTIONS
          *      RT-Thread related sections - Start
          *
         *********************************************/
-        /* section information for utest */
-        . = ALIGN(4);
-        __rt_utest_tc_tab_start = .;
-        KEEP(*(UtestTcTab))
-        __rt_utest_tc_tab_end = .;
-
         /* section information for finsh shell */
         . = ALIGN(4);
         __fsymtab_start = .;
@@ -146,6 +143,20 @@ SECTIONS
 
     } > XPI0
 
+    .eh_frame :
+    {
+        __eh_frame_start = .;
+        KEEP(*(.eh_frame))
+        __eh_frame_end = .;
+    }  > XPI0
+
+    .eh_frame_hdr :
+    {
+        KEEP(*(.eh_frame_hdr))
+    }  > XPI0
+    __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0;
+    __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0;
+
     .rel : {
         KEEP(*(.rel*))
     } > XPI0
@@ -158,19 +169,14 @@ SECTIONS
         KEEP(*(.fast_ram))
     } > DLM
 
-    .bss(NOLOAD) : {
+    __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
+        .fast_ram.init : AT(__fast_ram_init_load_addr__) {
         . = ALIGN(8);
-        __bss_start__ = .;
-        *(.bss)
-        *(.bss*)
-        *(.sbss*)
-        *(.scommon)
-        *(.scommon*)
-        *(.dynsbss*)
-        *(COMMON)
+        __fast_ram_init_start__ = .;
+        KEEP(*(.fast_ram.init))
+        KEEP(*(.fast_ram.init.*))
+        __fast_ram_init_end__ = .;
         . = ALIGN(8);
-        _end = .;
-        __bss_end__ = .;
     } > DLM
 
     /* Note: the .tbss and .tdata section should be adjacent */
@@ -178,22 +184,26 @@ SECTIONS
         . = ALIGN(8);
         __tbss_start__ = .;
         *(.tbss*)
+        *(.gnu.linkonce.tb.*)
         *(.tcommon*)
         _end = .;
         __tbss_end__ = .;
     } > DLM
 
-    .tdata : AT(etext) {
+    __tdata_load_addr__ = etext;
+    .tdata : AT(__tdata_load_addr__) {
         . = ALIGN(8);
         __tdata_start__ = .;
         __thread_pointer = .;
         *(.tdata)
         *(.tdata*)
+        *(.gnu.linkonce.td.*)
         . = ALIGN(8);
         __tdata_end__ = .;
     } > DLM
 
-    .data : AT(etext + __tdata_end__ - __tdata_start__) {
+    __data_load_addr__ = etext + SIZEOF(.tdata);
+    .data : AT(__data_load_addr__) {
         . = ALIGN(8);
         __data_start__ = .;
         __global_pointer$ = . + 0x800;
@@ -221,10 +231,10 @@ SECTIONS
         PROVIDE(__init_array_end = .);
 
         . = ALIGN(8);
-        PROVIDE(__finit_array_start = .);
-        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
-        KEEP(*(.finit_array))
-        PROVIDE(__finit_array_end = .);
+        PROVIDE(__fini_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE(__fini_array_end = .);
 
         . = ALIGN(8);
         PROVIDE(__ctors_start__ = .);
@@ -245,6 +255,26 @@ SECTIONS
         PROVIDE (_edata = .);
         PROVIDE (edata = .);
     } > DLM
+
+    __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata);
+
+    __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr);
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > DLM
+
     __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
 
     .heap(NOLOAD) : {
@@ -265,7 +295,8 @@ SECTIONS
         PROVIDE( __rt_rvstack = . );
     } > DLM
 
-    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
+    __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
+    .noncacheable.init : AT(__noncacheable_init_load_addr__) {
         . = ALIGN(8);
         __noncacheable_init_start__ = .;
         KEEP(*(.noncacheable.init))
@@ -276,8 +307,11 @@ SECTIONS
     .noncacheable.bss (NOLOAD) : {
         . = ALIGN(8);
         KEEP(*(.noncacheable))
+        KEEP(*(.noncacheable.non_init))
+        KEEP(*(.noncacheable.non_init.*))
         __noncacheable_bss_start__ = .;
         KEEP(*(.noncacheable.bss))
+        KEEP(*(.noncacheable.bss.*))
         __noncacheable_bss_end__ = .;
         . = ALIGN(8);
     } > DLM

bsp/hpmicro/hpm5300evk/board/linker_scripts/ram_rtt.ld → bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/ram_rtt.ld

@@ -1,5 +1,5 @@
 /*
- * Copyright 2021-2023 HPMicro
+ * Copyright 2021-2025 HPMicro
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
@@ -12,9 +12,9 @@ NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x8000;
 MEMORY
 {
     ILM (wx) : ORIGIN = 0, LENGTH = 128K
-    DLM (w) : ORIGIN = 0x80000, LENGTH = 128K
+    DLM (w) : ORIGIN = 0x80300, LENGTH = 96K - 768
     NONCACHEABLE_RAM (wx) : ORIGIN = 0x98000, LENGTH = NONCACHEABLE_SIZE
-    AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
+    AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k
 }
 
 SECTIONS
@@ -30,10 +30,6 @@ SECTIONS
         KEEP(*(.vector_table))
         . = ALIGN(8);
     } > ILM
-    
-    .fast_ram (NOLOAD) : {
-        KEEP(*(.fast_ram))
-    } > ILM
 
     .text : {
         . = ALIGN(8);
@@ -56,7 +52,7 @@ SECTIONS
         KEEP (*(.init))
         KEEP (*(.fini))
         . = ALIGN(8);
-        
+
         /*********************************************
          *
          *      RT-Thread related sections - Start
@@ -92,28 +88,74 @@ SECTIONS
         __usbh_class_info_start__ = .;
         KEEP(*(.usbh_class_info))
         __usbh_class_info_end__ = .;
+        PROVIDE (__etext = .);
+        PROVIDE (_etext = .);
+        PROVIDE (etext = .);
 
     } > ILM
-    
-    PROVIDE (__etext = .);
-    PROVIDE (_etext = .);
-    PROVIDE (etext = .);
 
-    .tdata : AT(etext) {
+    .rel : {
+        KEEP(*(.rel*))
+    } > DLM
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > ILM
+
+    __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
+    .fast_ram.init : AT(__fast_ram_init_load_addr__) {
+        . = ALIGN(8);
+        __fast_ram_init_start__ = .;
+        KEEP(*(.fast_ram.init))
+        KEEP(*(.fast_ram.init.*))
+        __fast_ram_init_end__ = .;
+        . = ALIGN(8);
+    } > ILM
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > DLM
+
+    /* Note: .tbss and .tdata should be adjacent */
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.gnu.linkonce.tb.*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > DLM
+
+    __tdata_load_addr__ = etext;
+    .tdata : AT(__tdata_load_addr__) {
         . = ALIGN(8);
         __tdata_start__ = .;
         __thread_pointer = .;
         *(.tdata)
         *(.tdata*)
+        *(.gnu.linkonce.td.*)
         . = ALIGN(8);
         __tdata_end__ = .;
     } > DLM
 
-    .data : AT(etext + __tdata_end__ - __tdata_start__) {
+    __data_load_addr__ = etext + SIZEOF(.tdata);
+    .data : AT(__data_load_addr__) {
         . = ALIGN(8);
         __data_start__ = .;
         __global_pointer$ = . + 0x800;
-        
+
         *(.data)
         *(.data*)
         *(.sdata)
@@ -138,10 +180,10 @@ SECTIONS
         PROVIDE(__init_array_end = .);
 
         . = ALIGN(8);
-        PROVIDE(__finit_array_start = .);
-        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
-        KEEP(*(.finit_array))
-        PROVIDE(__finit_array_end = .);
+        PROVIDE(__fini_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE(__fini_array_end = .);
 
         . = ALIGN(8);
         PROVIDE(__ctors_start__ = .);
@@ -164,43 +206,39 @@ SECTIONS
         PROVIDE (edata = .);
     } > DLM
 
-    .fast : AT(etext + __data_end__ - __tdata_start__) {
+    __fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data);
+    .fast : AT(__fast_load_addr__) {
         . = ALIGN(8);
         PROVIDE(__ramfunc_start__ = .);
         *(.fast)
         . = ALIGN(8);
         PROVIDE(__ramfunc_end__ = .);
     } > DLM
-    
-    .rel : {
-        KEEP(*(.rel*))
-    } > DLM
 
-    .bss(NOLOAD) : {
+    __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
+    .noncacheable.init : AT(__noncacheable_init_load_addr__) {
         . = ALIGN(8);
-        __bss_start__ = .;
-        *(.bss)
-        *(.bss*)
-        *(.sbss*)
-        *(.scommon)
-        *(.scommon*)
-        *(.dynsbss*)
-        *(COMMON)
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
         . = ALIGN(8);
-        _end = .;
-        __bss_end__ = .;
-    } > DLM
+    } > NONCACHEABLE_RAM
 
-    /* Note: .tbss and .tdata should be adjacent */
-    .tbss(NOLOAD) : {
+    .noncacheable.bss (NOLOAD) : {
         . = ALIGN(8);
-        __tbss_start__ = .;
-        *(.tbss*)
-        *(.tcommon*)
-        _end = .;
-        __tbss_end__ = .;
-    } > DLM
-    
+        KEEP(*(.noncacheable))
+        KEEP(*(.noncacheable.non_init))
+        KEEP(*(.noncacheable.non_init.*))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        KEEP(*(.noncacheable.bss.*))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
+    __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
+
     .stack(NOLOAD) : {
         . = ALIGN(8);
         __stack_base__ = .;
@@ -221,24 +259,4 @@ SECTIONS
      .ahb_sram (NOLOAD) : {
         KEEP(*(.ahb_sram))
     } > AHB_SRAM
-    
-    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
-        . = ALIGN(8);
-        __noncacheable_init_start__ = .;
-        KEEP(*(.noncacheable.init))
-        __noncacheable_init_end__ = .;
-        . = ALIGN(8);
-    } > NONCACHEABLE_RAM
-
-    .noncacheable.bss (NOLOAD) : {
-        . = ALIGN(8);
-        KEEP(*(.noncacheable))
-        __noncacheable_bss_start__ = .;
-        KEEP(*(.noncacheable.bss))
-        __noncacheable_bss_end__ = .;
-        . = ALIGN(8);
-    } > NONCACHEABLE_RAM
-
-    __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
-    __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
 }

bsp/hpmicro/hpm5300evk/board/pinmux.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023 HPMicro
+ * Copyright (c) 2023-2025 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -15,15 +15,6 @@
 #include "board.h"
 #include "pinmux.h"
 
-void init_xtal_pins(void)
-{
-    /* Package QFN32 should be set PA30 and PA31 pins as analog type to enable xtal. */
-    /*
-     * HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
-     * HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
-     */
-}
-
 void init_py_pins_as_pgpio(void)
 {
     /* Set PY00-PY05 default function to PGPIO */
@@ -48,10 +39,6 @@ void init_uart_pins(UART_Type *ptr)
         /* using for uart_lin function */
         HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_UART3_RXD;
         HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_UART3_TXD;
-    } else if (ptr == HPM_UART7) {
-        /* using for uart_lin function */
-        HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_UART7_TXD;
-        HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_UART7_RXD;
     } else {
         ;
     }
@@ -115,6 +102,13 @@ void init_spi_pins(SPI_Type *ptr)
         HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
         HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO;
         HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI;
+
+        /* set max frequency slew rate(200M) */
+        HPM_IOC->PAD[IOC_PAD_PA25].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1);
+        HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PA27].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PA28].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PA29].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
     }
 }
 
@@ -126,6 +120,13 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
         HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
         HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO;
         HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI;
+
+        /* set max frequency slew rate(200M) */
+        HPM_IOC->PAD[IOC_PAD_PA25].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1);
+        HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PA27].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PA28].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PA29].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
     }
 }
 
@@ -136,6 +137,7 @@ void init_gptmr_pins(GPTMR_Type *ptr)
         HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_GPTMR0_CAPT_0;
         HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_GPTMR0_COMP_0;
         HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1;
+        HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_GPTMR0_COMP_3;
     }
 }
 
@@ -197,31 +199,27 @@ void init_adc_qeiv2_pins(void)
     HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;         /* ADC_IU:   ADC0.5 /ADC1.5  */
 }
 
-void init_usb_pins(void)
+void init_usb_pins(USB_Type *ptr)
 {
-    /* Package QFN48 and LQFP64 should be set PA24 and PA25 pins as analog type to enable USB_P and USB_N. */
-    /*
-     * HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
-     * HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
-     */
-
-    /* Package QFN32 should be set PA26 and PA27 pins as analog type to enable USB_P and USB_N. */
-    /*
-     * HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
-     * HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
-     */
+    if (ptr == HPM_USB0) {
+        /* Package QFN48 and LQFP64 should be set PA24 and PA25 pins as analog type to enable USB_P and USB_N. */
+        /*
+         * HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+         * HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+         */
+
+        /* USB0_ID */
+        HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID;
+        /* USB0_OC */
+        HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC;
+        /* USB0_PWR */
+        HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR;
 
-    /* USB0_ID */
-    HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID;
-    /* USB0_OC */
-    HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC;
-    /* USB0_PWR */
-    HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR;
-
-    /* PY port IO needs to configure PIOC as well */
-    HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00;
-    HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01;
-    HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02;
+        /* PY port IO needs to configure PIOC as well */
+        HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00;
+        HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01;
+        HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02;
+    }
 }
 
 void init_can_pins(MCAN_Type *ptr)
@@ -254,8 +252,15 @@ void init_dac_pins(DAC_Type *ptr)
     }
 }
 
-void init_plb_pins(void)
+void init_plb_pulse_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_TRGM0_P_02;
+}
+
+void init_plb_filter_pins(void)
 {
+    HPM_IOC->PAD[IOC_PAD_PA28].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0);
+    HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_TRGM0_P_04;
     HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_TRGM0_P_02;
 }
 
@@ -323,3 +328,41 @@ void init_opamp_pins(void)
     HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
     HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
 }
+
+
+/* for uart_rx_line_status case, need to a gpio pin to sent break signal */
+void init_uart_break_signal_pin(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+    HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPIO_A_26;
+}
+
+void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp)
+{
+    if (ptr == HPM_GPTMR0) {
+        if (as_comp) {
+            switch (channel) {
+            case 0:
+                HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_GPTMR0_COMP_0;
+                break;
+            case 1:
+                HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1;
+                break;
+            case 3:
+                HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_GPTMR0_COMP_3;
+                break;
+            default:
+                break;
+            }
+        } else {
+            if (channel == 0) {
+                HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_GPTMR0_CAPT_0;
+            }
+        }
+    }
+}
+
+void init_clk_ref_pin(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_SOC_REF0;
+}

bsp/hpmicro/hpm5300evk/board/pinmux.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 HPMicro
+ * Copyright (c) 2022-2025 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -11,7 +11,6 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-void init_xtal_pins(void);
 void init_py_pins_as_pgpio(void);
 void init_uart_pins(UART_Type *ptr);
 void init_uart_pin_as_gpio(UART_Type *ptr);
@@ -28,12 +27,13 @@ void init_pwm_pins(PWM_Type *ptr);
 void init_adc_pins(void);
 void init_adc_bldc_pins(void);
 void init_adc_qeiv2_pins(void);
-void init_usb_pins(void);
+void init_usb_pins(USB_Type *ptr);
 void init_can_pins(MCAN_Type *ptr);
 void init_dac_pins(DAC_Type *ptr);
 void init_led_pins_as_gpio(void);
 void init_led_pins_as_pwm(void);
-void init_plb_pins(void);
+void init_plb_pulse_pins(void);
+void init_plb_filter_pins(void);
 void init_qeo_pins(QEO_Type *ptr);
 void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx);
 void init_rdc_pin(void);
@@ -42,6 +42,10 @@ void init_qeiv2_ab_pins(QEIV2_Type *ptr);
 void init_qeiv2_abz_pins(QEIV2_Type *ptr);
 void init_opamp_pins(void);
 void init_lin_transceiver_ctrl_pin(void);
+void init_uart_break_signal_pin(void);
+void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp);
+void init_clk_ref_pin(void);
+
 #ifdef __cplusplus
 }
 #endif

bsp/hpmicro/hpm5300evk/board/rtt_board.c

@@ -52,7 +52,7 @@ void rtt_board_init(void)
     os_tick_config();
 
     /* Configure the USB pins*/
-    board_init_usb_pins();
+    board_init_usb(HPM_USB0);
 
     /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */
     rt_hw_uart_init();
@@ -63,6 +63,7 @@ void rtt_board_init(void)
 
 void app_init_led_pins(void)
 {
+    board_init_led_pins();
     gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
     gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL);
 }
@@ -95,7 +96,7 @@ void rt_hw_console_output(const char *str)
 
 void app_init_usb_pins(void)
 {
-    board_init_usb_pins();
+    board_init_usb(HPM_USB0);
 }
 
 ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
@@ -107,7 +108,7 @@ ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
 
 void rt_hw_cpu_reset(void)
 {
-    HPM_PPOR->RESET_ENABLE = (1UL << 31);
+    HPM_PPOR->RESET_ENABLE |= (1UL << 31);
 
     HPM_PPOR->SOFTWARE_RESET = 1000U;
     while(1) {
@@ -127,3 +128,50 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
     }
 }
 #endif
+
+uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
+{
+    uint32_t freq = 0;
+
+    if (ptr == HPM_ADC0) {
+        if (clk_src_ahb) {
+            /* Configure the ADC clock from AHB (@200MHz by default)*/
+            clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
+        } else {
+            /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
+            clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
+            clock_set_source_divider(clock_ana0, clk_src_pll0_clk2, 2U);
+        }
+        clock_add_to_group(clock_adc0, 0);
+        freq = clock_get_frequency(clock_adc0);
+    } else if (ptr == HPM_ADC1) {
+        if (clk_src_ahb) {
+            /* Configure the ADC clock from AHB (@200MHz by default)*/
+            clock_set_adc_source(clock_adc1, clk_adc_src_ahb0);
+        } else {
+            /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
+            clock_set_adc_source(clock_adc1, clk_adc_src_ana1);
+            clock_set_source_divider(clock_ana1, clk_src_pll0_clk2, 2U);
+        }
+        clock_add_to_group(clock_adc1, 0);
+        freq = clock_get_frequency(clock_adc1);
+    }
+
+    return freq;
+}
+
+uint32_t rtt_board_init_pwm_clock(PWM_Type *ptr)
+{
+    uint32_t freq = 0;
+    (void) ptr;
+
+    clock_add_to_group(clock_mot0, 0);
+    freq = clock_get_frequency(clock_mot0);
+
+    return freq;
+}
+
+#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER
+extern void hpm_isr_usb0(void);
+RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0)
+#endif

bsp/hpmicro/hpm5300evk/board/rtt_board.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 hpmicro
+ * Copyright (c) 2021 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -10,8 +10,10 @@
 #include "hpm_common.h"
 #include "hpm_soc.h"
 #include <drv_gpio.h>
+#include "board.h"
 
 /* gpio section */
+#define APP_LED0         (0U)
 #define APP_LED0_PIN_NUM GET_PIN(A, 23)
 #define APP_LED_ON (1)
 #define APP_LED_OFF (0)
@@ -19,6 +21,11 @@
 /* mchtimer section */
 #define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
 
+#define BOARD_OS_TIMER HPM_GPTMR0
+#define BOARD_OS_TIMER_CH       1
+#define BOARD_OS_TIMER_IRQ      IRQn_GPTMR0
+#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0)
+
 /* CAN section */
 #define BOARD_CAN_NAME                        "can0"
 #define BOARD_CAN_HWFILTER_INDEX              (0U)
@@ -31,6 +38,10 @@
 #define BOARD_PWM_NAME                        "pwm0"
 #define BOARD_PWM_CHANNEL                     (6)
 
+/* ADC section */
+#define BOARD_ADC_NAME                        BOARD_APP_ADC16_NAME
+#define BOARD_ADC_CHANNEL                     BOARD_APP_ADC16_CH_1
+
 #define IRQn_PendSV IRQn_DEBUG0
 
 /***************************************************************

bsp/hpmicro/hpm5300evk/rtconfig.h

@@ -104,6 +104,8 @@
 #define RT_VER_NUM 0x50201
 #define RT_BACKTRACE_LEVEL_MAX_NR 32
 /* end of RT-Thread Kernel */
+#define ARCH_RISCV
+#define ARCH_RISCV32
 
 /* RT-Thread Components */
 
@@ -300,6 +302,20 @@
 /* NXP HAL & SDK Drivers */
 
 /* end of NXP HAL & SDK Drivers */
+
+/* NUVOTON Drivers */
+
+/* end of NUVOTON Drivers */
+
+/* GD32 Drivers */
+
+/* end of GD32 Drivers */
+
+/* HPMicro SDK */
+
+#define PKG_USING_HPM_SDK
+#define PKG_USING_HPM_SDK_LATEST_VERSION
+/* end of HPMicro SDK */
 /* end of HAL & SDK Drivers */
 
 /* sensors drivers */
@@ -379,18 +395,21 @@
 
 /* end of Arduino libraries */
 /* end of RT-Thread online packages */
+#define SOC_HPM5300_SERIES
 
 /* Hardware Drivers Config */
 
-#define SOC_HPM5000
+#define SOC_HPM5300
 
 /* On-chip Peripheral Drivers */
 
 #define BSP_USING_GPIO
+#define BSP_GPIO_IRQ_PRIORITY 1
 #define BSP_USING_UART
 #define BSP_USING_UART0
 #define BSP_UART0_RX_BUFSIZE 128
 #define BSP_UART0_TX_BUFSIZE 0
+#define BSP_UART0_IRQ_PRIORITY 1
 /* end of On-chip Peripheral Drivers */
 /* end of Hardware Drivers Config */
 

bsp/hpmicro/hpm5300evk/rtconfig.py

@@ -1,8 +1,41 @@
-# Copyright 2021-2023 HPMicro
+# Copyright 2021-2025 HPMicro
 # SPDX-License-Identifier: BSD-3-Clause
 
 import os
 import sys
+import rtconfig
+
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+def bsp_pkg_check():
+    import subprocess
+    
+    need_update = True
+    for p in os.listdir("packages"):
+        if p.startswith("hpm_sdk-"):
+            need_update = False
+            break
+    if need_update:
+        print("\n===============================================================================")
+        print("Dependency packages missing, please running 'pkgs --update'...")
+        print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
+        print("===============================================================================")
+        exit(1)
+
+RegisterPreBuildingAction(bsp_pkg_check)
+
 
 # toolchains options
 ARCH='risc-v'
@@ -80,27 +113,27 @@ if PLATFORM == 'gcc':
         AFLAGS += ' -gdwarf-2'
         CFLAGS += ' -O0'
         LFLAGS += ' -O0'
-        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+        LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld'
     elif BUILD == 'ram_release':
         CFLAGS += ' -O2'
         LFLAGS += ' -O2'
-        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+        LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld'
     elif BUILD == 'flash_debug':
         CFLAGS += ' -gdwarf-2'
         AFLAGS += ' -gdwarf-2'
         CFLAGS += ' -O0'
         LFLAGS += ' -O0'
         CFLAGS += ' -DFLASH_XIP=1'
-        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+        LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
     elif BUILD == 'flash_release':
         CFLAGS += ' -O2'
         LFLAGS += ' -O2'
         CFLAGS += ' -DFLASH_XIP=1'
-        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+        LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
     else:
         CFLAGS += ' -O2'
         LFLAGS += ' -O2'
-        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+        LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
     LFLAGS += ' -T ' + LINKER_FILE
 
     POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c

@@ -4,125 +4,132 @@
  *
  */
 
-#include "hpm_common.h"
-#include "hpm_soc.h"
-#include "hpm_l1c_drv.h"
-#include <rtthread.h>
-
-void system_init(void);
-
-extern int entry(void);
-
-extern void __libc_init_array(void);
-extern void __libc_fini_array(void);
-
-void system_init(void)
-{
-    disable_global_irq(CSR_MSTATUS_MIE_MASK);
-    disable_irq_from_intc();
-    enable_irq_from_intc();
-    enable_global_irq(CSR_MSTATUS_MIE_MASK);
-#ifndef CONFIG_NOT_ENABLE_ICACHE
-    l1c_ic_enable();
-#endif
-#ifndef CONFIG_NOT_ENABLE_DCACHE
-    l1c_dc_enable();
-#endif
-}
-
-__attribute__((weak)) void c_startup(void)
-{
-    uint32_t i, size;
-#ifdef FLASH_XIP
-    extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
-    size = __vector_ram_end__ - __vector_ram_start__;
-    for (i = 0; i < size; i++) {
-        *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
-    }
-#endif
-
-    extern uint8_t __etext[];
-    extern uint8_t __bss_start__[], __bss_end__[];
-    extern uint8_t __tbss_start__[], __tbss_end__[];
-    extern uint8_t __tdata_start__[], __tdata_end__[];
-    extern uint8_t __data_start__[], __data_end__[];
-    extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
-    extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
-    extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
-
-    /* tbss section */
-    size = __tbss_end__ - __tbss_start__;
-    for (i = 0; i < size; i++) {
-        *(__tbss_start__ + i) = 0;
-    }
-
-    /* bss section */
-    size = __bss_end__ - __bss_start__;
-    for (i = 0; i < size; i++) {
-        *(__bss_start__ + i) = 0;
-    }
-
-    /* noncacheable bss section */
-    size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
-    for (i = 0; i < size; i++) {
-        *(__noncacheable_bss_start__ + i) = 0;
-    }
-
-    /* tdata section LMA: etext */
-    size = __tdata_end__ - __tdata_start__;
-    for (i = 0; i < size; i++) {
-        *(__tdata_start__ + i) = *(__etext + i);
-    }
-
-    /* data section LMA: etext */
-    size = __data_end__ - __data_start__;
-    for (i = 0; i < size; i++) {
-        *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i);
-    }
-
-    /* ramfunc section LMA: etext + data length */
-    size = __ramfunc_end__ - __ramfunc_start__;
-    for (i = 0; i < size; i++) {
-        *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i);
-    }
-
-    /* noncacheable init section LMA: etext + data length + ramfunc length */
-    size = __noncacheable_init_end__ - __noncacheable_init_start__;
-    for (i = 0; i < size; i++) {
-        *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
-    }
-}
-
-__attribute__((weak)) int main(void)
-{
-    while(1);
-}
-
-void reset_handler(void)
-{
-    /**
-     * Disable preemptive interrupt
-     */
-    HPM_PLIC->FEATURE = 0;
-    /*
-     * Initialize LMA/VMA sections.
-     * Relocation for any sections that need to be copied from LMA to VMA.
-     */
-    c_startup();
-
-    /* Call platform specific hardware initialization */
-    system_init();
-
-    /* Do global constructors */
-    __libc_init_array();
-
-
-
-    /* Entry function */
-    entry();
-}
-
-
-__attribute__((weak)) void _init()
-{
-}
+ #include "hpm_common.h"
+ #include "hpm_soc.h"
+ #include "hpm_l1c_drv.h"
+ #include <rtthread.h>
+ 
+ void system_init(void);
+ 
+ extern int entry(void);
+ 
+ extern void __libc_init_array(void);
+ extern void __libc_fini_array(void);
+ 
+ void system_init(void)
+ {
+     disable_global_irq(CSR_MSTATUS_MIE_MASK);
+     disable_irq_from_intc();
+     enable_irq_from_intc();
+     enable_global_irq(CSR_MSTATUS_MIE_MASK);
+ #ifndef CONFIG_NOT_ENABLE_ICACHE
+     l1c_ic_enable();
+ #endif
+ #ifndef CONFIG_NOT_ENABLE_DCACHE
+     l1c_dc_enable();
+ #endif
+ }
+ 
+ __attribute__((weak)) void c_startup(void)
+ {
+ #ifndef __SES_RISCV
+     uint32_t i, size;
+ #ifdef FLASH_XIP
+     extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
+     size = __vector_ram_end__ - __vector_ram_start__;
+     for (i = 0; i < size; i++) {
+         *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
+     }
+ #endif
+ 
+     extern uint8_t __etext[];
+     extern uint8_t __bss_start__[], __bss_end__[];
+     extern uint8_t __tbss_start__[], __tbss_end__[];
+     extern uint8_t __tdata_start__[], __tdata_end__[];
+     extern uint8_t __fast_load_addr__[];
+     extern uint8_t __noncacheable_init_load_addr__[];
+     extern uint8_t __data_load_addr__[];
+     extern uint8_t __tdata_load_addr__[];
+     extern uint8_t __data_start__[], __data_end__[];
+     extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
+     extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
+     extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
+ 
+     /* tbss section */
+     size = __tbss_end__ - __tbss_start__;
+     for (i = 0; i < size; i++) {
+         *(__tbss_start__ + i) = 0;
+     }
+ 
+     /* bss section */
+     size = __bss_end__ - __bss_start__;
+     for (i = 0; i < size; i++) {
+         *(__bss_start__ + i) = 0;
+     }
+ 
+     /* noncacheable bss section */
+     size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
+     for (i = 0; i < size; i++) {
+         *(__noncacheable_bss_start__ + i) = 0;
+     }
+ 
+     /* tdata section LMA: etext */
+     size = __tdata_end__ - __tdata_start__;
+     for (i = 0; i < size; i++) {
+         *(__tdata_start__ + i) = *(__tdata_load_addr__ + i);
+     }
+ 
+     /* data section LMA: etext */
+     size = __data_end__ - __data_start__;
+     for (i = 0; i < size; i++) {
+         *(__data_start__ + i) = *(__data_load_addr__ + i);
+     }
+ 
+     /* ramfunc section LMA: etext + data length */
+     size = __ramfunc_end__ - __ramfunc_start__;
+     for (i = 0; i < size; i++) {
+         *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i);
+     }
+ 
+     /* noncacheable init section LMA: etext + data length + ramfunc length */
+     size = __noncacheable_init_end__ - __noncacheable_init_start__;
+     for (i = 0; i < size; i++) {
+         *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i);
+     }
+ #endif
+ }
+ 
+ __attribute__((weak)) int main(void)
+ {
+     while(1);
+ }
+ 
+ void reset_handler(void)
+ {
+     /**
+      * Disable preemptive interrupt
+      */
+     HPM_PLIC->FEATURE = 0;
+     /*
+      * Initialize LMA/VMA sections.
+      * Relocation for any sections that need to be copied from LMA to VMA.
+      */
+     c_startup();
+ 
+     /* Call platform specific hardware initialization */
+     system_init();
+ 
+ #ifndef __SES_RISCV
+     /* Do global constructors */
+     __libc_init_array();
+ #endif
+ 
+     /* Entry function */
+     entry();
+ }
+ 
+ 
+ __attribute__((weak)) void _init(void)
+ {
+ }
+ 

bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/port_gcc.S

@@ -5,7 +5,7 @@
  *
  */
 #include "cpuport.h"
-
+    .section .text.entry, "ax"
     .globl rt_hw_do_after_save_above
     .type rt_hw_do_after_save_above,@function
 rt_hw_do_after_save_above:

bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S

@@ -62,7 +62,6 @@ _start:
 nmi_handler:
 1:    j 1b
 
-    .global default_irq_handler
     .weak default_irq_handler
     .align 2
 default_irq_handler:

bsp/hpmicro/hpm5301evklite/.config

@@ -104,11 +104,9 @@
 #
 # CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set
 # end of rt_strnlen options
-
-# CONFIG_RT_UTEST_TC_USING_KLIBC is not set
 # end of klibc options
 
-CONFIG_RT_NAME_MAX=8
+CONFIG_RT_NAME_MAX=16
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
 # CONFIG_RT_USING_NANO is not set
 # CONFIG_RT_USING_AMP is not set
@@ -131,7 +129,7 @@ CONFIG_RT_USING_TIMER_SOFT=y
 CONFIG_RT_TIMER_THREAD_PRIO=4
 CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024
 # CONFIG_RT_USING_TIMER_ALL_SOFT is not set
-# CONFIG_RT_USING_CPU_USAGE_TRACER is not set
+CONFIG_RT_USING_CPU_USAGE_TRACER=y
 
 #
 # kservice options
@@ -183,6 +181,9 @@ CONFIG_RT_VER_NUM=0x50201
 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
 # end of RT-Thread Kernel
 
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV32=y
+
 #
 # RT-Thread Components
 #
@@ -199,6 +200,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20
 CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
+# CONFIG_FINSH_USING_WORD_OPERATION is not set
 CONFIG_FINSH_USING_SYMTAB=y
 CONFIG_FINSH_CMD_SIZE=80
 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
@@ -376,6 +378,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FREEMODBUS is not set
 # CONFIG_PKG_USING_NANOPB is not set
 # CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
+# CONFIG_PKG_USING_ESP_HOSTED is not set
 
 #
 # Wi-Fi
@@ -483,6 +486,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_QMODBUS is not set
 # CONFIG_PKG_USING_PNET is not set
 # CONFIG_PKG_USING_OPENER is not set
+# CONFIG_PKG_USING_FREEMQTT is not set
 # end of IoT - internet of things
 
 #
@@ -572,6 +576,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # tools packages
 #
 # CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_MCOREDUMP is not set
 # CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
@@ -617,6 +622,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ZDEBUG is not set
 # CONFIG_PKG_USING_RVBACKTRACE is not set
 # CONFIG_PKG_USING_HPATCHLITE is not set
+# CONFIG_PKG_USING_THREAD_METRIC is not set
 # end of tools packages
 
 #
@@ -710,6 +716,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_RMP is not set
 # CONFIG_PKG_USING_R_RHEALSTONE is not set
 # CONFIG_PKG_USING_HEARTBEAT is not set
+# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
 # end of system packages
 
 #
@@ -791,6 +798,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 
 # CONFIG_PKG_USING_NRF5X_SDK is not set
 # CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set
 # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
 # CONFIG_PKG_USING_MM32 is not set
 
@@ -833,6 +842,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # HC32 DDL Drivers
 #
+# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set
+# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set
 # end of HC32 DDL Drivers
 
 #
@@ -846,6 +859,31 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set
 # CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set
 # end of NXP HAL & SDK Drivers
+
+#
+# NUVOTON Drivers
+#
+# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set
+# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set
+# end of NUVOTON Drivers
+
+#
+# GD32 Drivers
+#
+# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set
+# end of GD32 Drivers
+
+#
+# HPMicro SDK
+#
+CONFIG_PKG_USING_HPM_SDK=y
+CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk"
+# CONFIG_PKG_USING_HPM_SDK_V110 is not set
+CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y
+CONFIG_PKG_HPM_SDK_VER="latest"
+# end of HPMicro SDK
 # end of HAL & SDK Drivers
 
 #
@@ -1017,6 +1055,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_SEAN_WS2812B is not set
 # CONFIG_PKG_USING_IC74HC165 is not set
 # CONFIG_PKG_USING_IST8310 is not set
+# CONFIG_PKG_USING_ST7789_SPI is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set
 # end of peripheral libraries and drivers
 
@@ -1355,21 +1394,26 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # end of Arduino libraries
 # end of RT-Thread online packages
 
+CONFIG_SOC_HPM5300_SERIES=y
+
 #
 # Hardware Drivers Config
 #
-CONFIG_SOC_HPM5000=y
+CONFIG_SOC_HPM5300=y
 
 #
 # On-chip Peripheral Drivers
 #
 CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_GPIO_IRQ_PRIORITY=1
 CONFIG_BSP_USING_UART=y
 CONFIG_BSP_USING_UART0=y
 CONFIG_BSP_UART0_RX_BUFSIZE=128
 CONFIG_BSP_UART0_TX_BUFSIZE=0
+CONFIG_BSP_UART0_IRQ_PRIORITY=1
+# CONFIG_BSP_USING_UART1 is not set
 # CONFIG_BSP_USING_UART2 is not set
-# CONFIG_BSP_USING_UART6 is not set
+# CONFIG_BSP_USING_UART3 is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_GPTMR is not set
 # CONFIG_BSP_USING_I2C is not set

bsp/hpmicro/hpm5301evklite/SConstruct

@@ -55,17 +55,7 @@ GDB = rtconfig.GDB
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 
-hpm_library = 'hpm_sdk'
-rtconfig.BSP_LIBRARY_TYPE = hpm_library
 
-# include soc
-objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript')))
-
-# include libraries
-objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
-
-# include components
-objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript')))
 
 
 # includes rtt drivers

bsp/hpmicro/hpm5301evklite/board/Kconfig

@@ -1,8 +1,8 @@
 menu "Hardware Drivers Config"
 
-config SOC_HPM5000
+config SOC_HPM5300
     bool
-    select SOC_SERIES_HPM5300
+    select SOC_HPM5300_SERIES
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
     default y
@@ -12,6 +12,12 @@ menu "On-chip Peripheral Drivers"
         bool "Enable GPIO"
         select RT_USING_PIN if BSP_USING_GPIO
         default n
+        if BSP_USING_GPIO
+            config BSP_GPIO_IRQ_PRIORITY
+            int "GPIO Interrupt Priority"
+            range 1 7
+            default 1
+        endif
 
     menuconfig BSP_USING_UART
         bool "Enable UART"
@@ -41,6 +47,37 @@ menu "On-chip Peripheral Drivers"
                         range 0 65535
                         depends on RT_USING_SERIAL_V2
                         default 0
+                    config BSP_UART0_IRQ_PRIORITY
+                        int "UART0 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            menuconfig BSP_USING_UART1
+                bool "Enable UART1"
+                default n
+                if BSP_USING_UART1
+                    config BSP_UART1_RX_USING_DMA
+                        bool "Enable UART1 RX DMA"
+                        depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART1_TX_USING_DMA
+                        bool "Enable UART1 TX DMA"
+                        depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART1_RX_BUFSIZE
+                        int "Set UART1 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 1024
+                    config BSP_UART1_TX_BUFSIZE
+                        int "Set UART1 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                    config BSP_UART1_IRQ_PRIORITY
+                        int "UART1 Interrupt Priority"
+                        range 1 7
+                        default 1
                 endif
             menuconfig BSP_USING_UART2
                 bool "Enable UART2"
@@ -64,29 +101,37 @@ menu "On-chip Peripheral Drivers"
                         range 0 65535
                         depends on RT_USING_SERIAL_V2
                         default 0
+                    config BSP_UART2_IRQ_PRIORITY
+                        int "UART2 Interrupt Priority"
+                        range 1 7
+                        default 1
                 endif
-            menuconfig BSP_USING_UART6
-                bool "Enable UART6"
+            menuconfig BSP_USING_UART3
+                bool "Enable UART3"
                 default n
-                if BSP_USING_UART6
-                    config BSP_UART6_RX_USING_DMA
-                        bool "Enable UART6 RX DMA"
-                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                if BSP_USING_UART3
+                    config BSP_UART3_RX_USING_DMA
+                        bool "Enable UART3 RX DMA"
+                        depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
                         default n
-                    config BSP_UART6_TX_USING_DMA
-                        bool "Enable UART6 TX DMA"
-                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                    config BSP_UART3_TX_USING_DMA
+                        bool "Enable UART3 TX DMA"
+                        depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
                         default n
-                    config BSP_UART6_RX_BUFSIZE
-                        int "Set UART6 RX buffer size"
+                    config BSP_UART3_RX_BUFSIZE
+                        int "Set UART3 RX buffer size"
                         range 64 65535
                         depends on RT_USING_SERIAL_V2
                         default 1024
-                    config BSP_UART6_TX_BUFSIZE
-                        int "Set UART6 TX buffer size"
+                    config BSP_UART3_TX_BUFSIZE
+                        int "Set UART3 TX buffer size"
                         range 0 65535
                         depends on RT_USING_SERIAL_V2
                         default 0
+                    config BSP_UART3_IRQ_PRIORITY
+                        int "UART3 Interrupt Priority"
+                        range 1 7
+                        default 1
                 endif
         endif
 
@@ -95,48 +140,225 @@ menu "On-chip Peripheral Drivers"
         default n
         select RT_USING_SPI if BSP_USING_SPI
         if BSP_USING_SPI
+            config BSP_USING_SPI0
+                bool "Enable SPI0"
+                default n
+                if BSP_USING_SPI0
+                    config BSP_SPI0_USING_DMA
+                        bool "Enable SPI0 DMA"
+                        default n
+                    config BSP_SPI0_IRQ_PRIORITY
+                        int "SPI0 Interrupt Priority"
+                        range 1 7
+                        default 1
+                    choice
+                        prompt "Select SPI0 CS TYPE"
+                        default BSP_SPI0_USING_SOFT_CS
+                        config BSP_SPI0_USING_SOFT_CS
+                            bool "Enable SPI0 software cs"
+                        config BSP_SPI0_USING_HARD_CS
+                            bool "Enable SPI0 hardware cs"
+                    endchoice
+                    choice
+                        prompt "Select SPI0 IO mode"
+                        default BSP_SPI0_USING_SINGLE_IO
+                        config BSP_SPI0_USING_SINGLE_IO
+                            bool "Enable SPI0 single IO mode"
+                        config BSP_SPI0_USING_DUAL_IO
+                            bool "Enable SPI0 dual IO mode"
+                        config BSP_SPI0_USING_QUAD_IO
+                            bool "Enable SPI0 quad IO mode"
+                    endchoice
+                endif
             config BSP_USING_SPI1
                 bool "Enable SPI1"
                 default y
+                if BSP_USING_SPI1
+                    config BSP_SPI1_USING_DMA
+                        bool "Enable SPI1 DMA"
+                        default n
+                    config BSP_SPI1_IRQ_PRIORITY
+                        int "SPI1 Interrupt Priority"
+                        range 1 7
+                        default 1
+                    choice
+                        prompt "Select SPI1 CS TYPE"
+                        default BSP_SPI1_USING_SOFT_CS
+                        config BSP_SPI1_USING_SOFT_CS
+                            bool "Enable SPI1 software cs"
+                        config BSP_SPI1_USING_HARD_CS
+                            bool "Enable SPI1 hardware cs"
+                    endchoice
+                    choice
+                        prompt "Select SPI1 IO mode"
+                        default BSP_SPI1_USING_SINGLE_IO
+                        config BSP_SPI1_USING_SINGLE_IO
+                            bool "Enable SPI1 single IO mode"
+                        config BSP_SPI1_USING_DUAL_IO
+                            bool "Enable SPI1 dual IO mode"
+                        config BSP_SPI1_USING_QUAD_IO
+                            bool "Enable SPI1 quad IO mode"
+                    endchoice
+                endif
             config BSP_USING_SPI2
                 bool "Enable SPI2"
                 default n
+                if BSP_USING_SPI2
+                    config BSP_SPI2_USING_DMA
+                        bool "Enable SPI2 DMA"
+                        default n
+                    config BSP_SPI2_IRQ_PRIORITY
+                        int "SPI2 Interrupt Priority"
+                        range 1 7
+                        default 1
+                    choice
+                        prompt "Select SPI2 CS TYPE"
+                        default BSP_SPI2_USING_SOFT_CS
+                        config BSP_SPI2_USING_SOFT_CS
+                            bool "Enable SPI2 software cs"
+                        config BSP_SPI2_USING_HARD_CS
+                            bool "Enable SPI2 hardware cs"
+                    endchoice
+                    choice
+                        prompt "Select SPI2 IO mode"
+                        default BSP_SPI2_USING_SINGLE_IO
+                        config BSP_SPI2_USING_SINGLE_IO
+                            bool "Enable SPI2 single IO mode"
+                        config BSP_SPI2_USING_DUAL_IO
+                            bool "Enable SPI2 dual IO mode"
+                        config BSP_SPI2_USING_QUAD_IO
+                            bool "Enable SPI2 quad IO mode"
+                    endchoice
+                endif
             config BSP_USING_SPI3
                 bool "Enable SPI3"
                 default n
+                if BSP_USING_SPI3
+                    config BSP_SPI3_USING_DMA
+                        bool "Enable SPI3 DMA"
+                        default n
+                    config BSP_SPI3_IRQ_PRIORITY
+                        int "SPI3 Interrupt Priority"
+                        range 1 7
+                        default 1
+                    choice
+                        prompt "Select SPI3 CS TYPE"
+                        default BSP_SPI3_USING_SOFT_CS
+                        config BSP_SPI3_USING_SOFT_CS
+                            bool "Enable SPI3 software cs"
+                        config BSP_SPI3_USING_HARD_CS
+                            bool "Enable SPI3 hardware cs"
+                    endchoice
+                    choice
+                        prompt "Select SPI3 IO mode"
+                        default BSP_SPI3_USING_SINGLE_IO
+                        config BSP_SPI3_USING_SINGLE_IO
+                            bool "Enable SPI3 single IO mode"
+                        config BSP_SPI3_USING_DUAL_IO
+                            bool "Enable SPI3 dual IO mode"
+                        config BSP_SPI3_USING_QUAD_IO
+                            bool "Enable SPI3 quad IO mode"
+                    endchoice
+                endif
         endif
 
+
     menuconfig BSP_USING_GPTMR
         bool "Enable GPTMR"
         default n
         select RT_USING_HWTIMER if BSP_USING_GPTMR
         if BSP_USING_GPTMR
+            config BSP_USING_GPTMR0
+                bool "Enable GPTMR0"
+                default n
+                if BSP_USING_GPTMR0
+                    config BSP_GPTMR0_IRQ_PRIORITY
+                    int "GPTMR0 Interrupt Priority"
+                    range 1 7
+                    default 1
+                endif
             config BSP_USING_GPTMR1
                 bool "Enable GPTMR1"
                 default n
+                if BSP_USING_GPTMR1
+                    config BSP_GPTMR1_IRQ_PRIORITY
+                    int "GPTMR1 Interrupt Priority"
+                    range 1 7
+                    default 1
+                endif
+            config BSP_USING_GPTMR2
+                bool "Enable GPTMR2"
+                default n
+                if BSP_USING_GPTMR2
+                    config BSP_GPTMR2_IRQ_PRIORITY
+                    int "GPTMR2 Interrupt Priority"
+                    range 1 7
+                    default 1
+                endif
+            config BSP_USING_GPTMR3
+                bool "Enable GPTMR3"
+                default n
+                if BSP_USING_GPTMR3
+                    config BSP_GPTMR3_IRQ_PRIORITY
+                    int "GPTMR3 Interrupt Priority"
+                    range 1 7
+                    default 1
+                endif
         endif
 
     menuconfig BSP_USING_I2C
         bool "Enable I2C"
         default n
+        select RT_USING_I2C if BSP_USING_I2C
         if BSP_USING_I2C
             config BSP_USING_I2C0
                 bool "Enable I2C0"
                 default y
-            if BSP_USING_I2C0
-                config BSP_I2C0_USING_DMA
-                    bool "Enable I2C0 DMA"
-                    default n
-            endif
-
+                if BSP_USING_I2C0
+                    config BSP_I2C0_USING_DMA
+                        bool "Enable I2C0 DMA"
+                        default n
+                    config BSP_I2C0_IRQ_PRIORITY
+                        int "I2C0 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            config BSP_USING_I2C1
+                bool "Enable I2C1"
+                default n
+                if BSP_USING_I2C1
+                    config BSP_I2C1_USING_DMA
+                        bool "Enable I2C1 DMA"
+                        default n
+                    config BSP_I2C1_IRQ_PRIORITY
+                        int "I2C1 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            config BSP_USING_I2C2
+                bool "Enable I2C2"
+                default n
+                if BSP_USING_I2C2
+                    config BSP_I2C2_USING_DMA
+                        bool "Enable I2C2 DMA"
+                        default n
+                    config BSP_I2C2_IRQ_PRIORITY
+                        int "I2C2 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
             config BSP_USING_I2C3
                 bool "Enable I2C3"
                 default n
-            if BSP_USING_I2C3
-                config BSP_I2C3_USING_DMA
-                    bool "Enable I2C3 DMA"
-                    default n
-            endif
+                if BSP_USING_I2C3
+                    config BSP_I2C3_USING_DMA
+                        bool "Enable I2C3 DMA"
+                        default n
+                    config BSP_I2C3_IRQ_PRIORITY
+                        int "I2C3 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
         endif
 
     menuconfig BSP_USING_XPI_FLASH
@@ -150,6 +372,7 @@ menu "On-chip Peripheral Drivers"
        if BSP_USING_USB
             config BSP_USING_USB_DEVICE
                 bool "Enable USB Device"
+                select RT_USING_CACHE
                 default n
             config BSP_USING_USB_HOST
                 bool "Enable USB HOST"

bsp/hpmicro/hpm5301evklite/board/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023 HPMicro
+ * Copyright (c) 2023-2025 HPMicro
  * SPDX-License-Identifier: BSD-3-Clause
  *
  */
@@ -13,8 +13,7 @@
 #include "hpm_pllctlv2_drv.h"
 #include "hpm_i2c_drv.h"
 #include "hpm_pcfg_drv.h"
-
-static board_timer_cb timer_cb;
+#include <rtconfig.h>
 
 /**
  * @brief FLASH configuration option definitions:
@@ -49,7 +48,7 @@ static board_timer_cb timer_cb;
  *      2 - Internal loopback
  *      3 - External DQS
  *    [3:0] Frequency option
- *      1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+ *      1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 114MHz / 7 - 133MHz / 8 - 166MHz
  *
  * option[2] (Effective only if the bit[3:0] in option[0] > 1)
  *    [31:20]  Reserved
@@ -70,11 +69,11 @@ static board_timer_cb timer_cb;
  *      0 - 4MB / 1 - 8MB / 2 - 16MB
  */
 #if defined(FLASH_XIP) && FLASH_XIP
-__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90002, 0x00000006, 0x1000, 0x0};
+__attribute__ ((section(".nor_cfg_option"), used)) const uint32_t option[4] = {0xfcf90002, 0x00000005, 0x1000, 0x0};
 #endif
 
 #if defined(FLASH_UF2) && FLASH_UF2
-ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
+ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
 #endif
 
 void board_init_console(void)
@@ -89,8 +88,6 @@ void board_init_console(void)
      */
     init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE);
 
-    /* Configure the UART clock to 24MHz */
-    clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U);
     clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0);
 
     cfg.type = BOARD_CONSOLE_TYPE;
@@ -143,7 +140,6 @@ void board_print_clock_freq(void)
 
 void board_init(void)
 {
-    init_xtal_pins();
     init_py_pins_as_pgpio();
     board_init_usb_dp_dm_pins();
 
@@ -176,7 +172,7 @@ void board_init_usb_dp_dm_pins(void)
     } else {
         uint8_t tmp;
         tmp = sysctl_resource_target_get_mode(HPM_SYSCTL, sysctl_resource_xtal);
-        sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03);
+        sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03);    /* NOLINT */
         clock_add_to_group(clock_usb0, 0);
         usb_phy_disable_dp_dm_pulldown(HPM_USB0);
         clock_remove_from_group(clock_usb0, 0);
@@ -199,31 +195,20 @@ void board_init_clock(void)
         sysctl_clock_set_preset(HPM_SYSCTL, 2);
     }
 
+    /* select XTAL as pll ref clock */
+    pllctlv2_select_reference_clock(HPM_PLLCTLV2, pllctlv2_pll0, 0);
+    pllctlv2_select_reference_clock(HPM_PLLCTLV2, pllctlv2_pll1, 0);
+
     /* group0[0] */
     clock_add_to_group(clock_cpu0, 0);
     clock_add_to_group(clock_ahb, 0);
     clock_add_to_group(clock_lmm0, 0);
     clock_add_to_group(clock_mchtmr0, 0);
     clock_add_to_group(clock_rom, 0);
-    clock_add_to_group(clock_gptmr0, 0);
-    clock_add_to_group(clock_gptmr1, 0);
-    clock_add_to_group(clock_i2c2, 0);
-    clock_add_to_group(clock_spi1, 0);
-    clock_add_to_group(clock_uart0, 0);
-    clock_add_to_group(clock_uart3, 0);
-
-    clock_add_to_group(clock_watchdog0, 0);
-    clock_add_to_group(clock_watchdog1, 0);
-    clock_add_to_group(clock_mbx0, 0);
-    clock_add_to_group(clock_tsns, 0);
-    clock_add_to_group(clock_crc0, 0);
-    clock_add_to_group(clock_adc0, 0);
-    clock_add_to_group(clock_acmp, 0);
-    clock_add_to_group(clock_kman, 0);
+    clock_add_to_group(clock_mot0, 0); /* for trgm and synt peripheral */
     clock_add_to_group(clock_gpio, 0);
     clock_add_to_group(clock_hdma, 0);
     clock_add_to_group(clock_xpi0, 0);
-    clock_add_to_group(clock_usb0, 0);
 
     /* Connect Group0 to CPU0 */
     clock_connect_group_to_cpu(0, 0);
@@ -234,11 +219,11 @@ void board_init_clock(void)
     /* Configure CPU to 360MHz, AXI/AHB to 120MHz */
     sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll0_clk0, 2, 3);
     /* Configure PLL0 Post Divider */
-    pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0);    /* PLL0CLK0: 720MHz */
-    pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 1, 3);    /* PLL0CLK1: 450MHz */
-    pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 2, 7);    /* PLL0CLK2: 300MHz */
+    pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk0, pllctlv2_div_1p0);    /* PLL0CLK0: 720MHz */
+    pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk1, pllctlv2_div_1p2);    /* PLL0CLK1: 600MHz */
+    pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk2, pllctlv2_div_1p8);    /* PLL0CLK2: 400MHz */
     /* Configure PLL0 Frequency to 720MHz */
-    pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, 720000000);
+    pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll0, 720000000);
 
     clock_update_core_clock();
 
@@ -246,32 +231,6 @@ void board_init_clock(void)
     clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
 }
 
-uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
-{
-    uint32_t freq = 0;
-    clock_name_t gptmr_clock =0;
-    uint32_t HPM_GPTMR = (uint32_t)ptr;
-    bool gptmr_valid = true;
-
-    switch(HPM_GPTMR){
-        case HPM_GPTMR0_BASE:
-            gptmr_clock = clock_gptmr0;
-            break;
-        case HPM_GPTMR1_BASE:
-            gptmr_clock = clock_gptmr1;
-            break;
-        default:
-            gptmr_valid = false;
-    }
-    if(gptmr_valid)
-    {
-        clock_add_to_group(gptmr_clock, 0);
-        clock_set_source_divider(gptmr_clock, clk_src_pll1_clk1, 4);
-        freq = clock_get_frequency(gptmr_clock);
-    }
-    return freq;
-}
-
 void board_delay_us(uint32_t us)
 {
     clock_cpu_delay_us(us);
@@ -282,6 +241,17 @@ void board_delay_ms(uint32_t ms)
     clock_cpu_delay_ms(ms);
 }
 
+#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT
+static board_timer_cb timer_cb;
+SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr)
+void board_timer_isr(void)
+{
+    if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
+        gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH));
+        timer_cb();
+    }
+}
+
 void board_timer_create(uint32_t ms, board_timer_cb cb)
 {
     uint32_t gptmr_freq;
@@ -300,6 +270,7 @@ void board_timer_create(uint32_t ms, board_timer_cb cb)
 
     gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
 }
+#endif
 
 void board_init_gpio_pins(void)
 {
@@ -313,15 +284,19 @@ void board_init_led_pins(void)
     gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level());
 }
 
-void board_init_usb_pins(void)
+void board_init_usb(USB_Type *ptr)
 {
-    init_usb_pins();
-    usb_hcd_set_power_ctrl_polarity(BOARD_USB, true);
-    /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */
-    board_delay_ms(100);
+    if (ptr == HPM_USB0) {
+        init_usb_pins(ptr);
+        clock_add_to_group(clock_usb0, 0);
 
-    /* As QFN32, QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */
-    usb_phy_using_internal_vbus(BOARD_USB);
+        usb_hcd_set_power_ctrl_polarity(ptr, true);
+        /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */
+        board_delay_ms(100);
+
+        /* As QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */
+        usb_phy_using_internal_vbus(ptr);
+    }
 }
 
 void board_led_write(uint8_t state)
@@ -373,18 +348,12 @@ void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
                                      GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
 }
 
-void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
-{
-    (void) usb_index;
-    (void) level;
-}
-
-uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
+uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus)
 {
     uint32_t freq = 0;
 
-    if (ptr == HPM_ADC0) {
-        if (clk_src_ahb) {
+    if (ptr == (void *)HPM_ADC0) {
+        if (clk_src_bus) {
             /* Configure the ADC clock from AHB (@200MHz by default)*/
             clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
         } else {
@@ -404,6 +373,17 @@ void board_init_adc16_pins(void)
     init_adc_pins();
 }
 
+void board_init_acmp_clock(ACMP_Type *ptr)
+{
+    (void)ptr;
+    clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1);
+}
+
+void board_init_acmp_pins(void)
+{
+    init_acmp_pins();
+}
+
 void board_disable_output_rgb_led(uint8_t color)
 {
     (void) color;
@@ -427,15 +407,9 @@ uint32_t board_init_uart_clock(UART_Type *ptr)
 {
     uint32_t freq = 0U;
     if (ptr == HPM_UART0) {
-        clock_set_source_divider(clock_uart0, clk_src_osc24m, 1);
         clock_add_to_group(clock_uart0, 0);
         freq = clock_get_frequency(clock_uart0);
-    } else if (ptr == HPM_UART2) {
-        clock_set_source_divider(clock_uart2, clk_src_pll0_clk2, 6);
-        clock_add_to_group(clock_uart2, 0);
-        freq = clock_get_frequency(clock_uart2);
     } else if (ptr == HPM_UART3) {
-        clock_set_source_divider(clock_uart3, clk_src_pll0_clk2, 6); /* 50MHz */
         clock_add_to_group(clock_uart3, 0);
         freq = clock_get_frequency(clock_uart3);
     }
@@ -456,35 +430,78 @@ void board_i2c_bus_clear(I2C_Type *ptr)
         printf("I2C bus is ready\n");
         return;
     }
-    i2s_gen_reset_signal(ptr, 9);
+    i2c_gen_reset_signal(ptr, 9);
     board_delay_ms(100);
     printf("I2C bus is cleared\n");
 }
 
+uint32_t board_init_i2c_clock(I2C_Type *ptr)
+{
+    uint32_t freq = 0;
+
+    if (ptr == HPM_I2C0) {
+        clock_add_to_group(clock_i2c0, 0);
+        freq = clock_get_frequency(clock_i2c0);
+    } else if (ptr == HPM_I2C1) {
+        clock_add_to_group(clock_i2c1, 0);
+        freq = clock_get_frequency(clock_i2c1);
+    } else if (ptr == HPM_I2C2) {
+        clock_add_to_group(clock_i2c2, 0);
+        freq = clock_get_frequency(clock_i2c2);
+    } else if (ptr == HPM_I2C3) {
+        clock_add_to_group(clock_i2c3, 0);
+        freq = clock_get_frequency(clock_i2c3);
+    } else {
+        ;
+    }
+
+    return freq;
+}
+
 void board_init_i2c(I2C_Type *ptr)
 {
     i2c_config_t config;
     hpm_stat_t stat;
     uint32_t freq;
-    if (ptr == NULL) {
-        return;
-    }
+
+    freq = board_init_i2c_clock(ptr);
     init_i2c_pins(ptr);
     board_i2c_bus_clear(ptr);
-
-    clock_add_to_group(clock_i2c2, 0);
-    /* Configure the I2C clock to 24MHz */
-    clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U);
-
     config.i2c_mode = i2c_mode_normal;
     config.is_10bit_addressing = false;
-    freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME);
     stat = i2c_init_master(ptr, freq, &config);
     if (stat != status_success) {
-        printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr);
+        printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr);
         while (1) {
         }
     }
+}
+
+void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp)
+{
+    init_gptmr_channel_pin(ptr, channel, as_comp);
+}
+
+void board_init_clk_ref_pin(void)
+{
+    init_clk_ref_pin();
+}
 
+uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
+{
+    uint32_t freq = 0U;
+    if (ptr == HPM_GPTMR0) {
+        clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_gptmr0);
+    } else if (ptr == HPM_GPTMR1) {
+        clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_gptmr1);
+    } else if (ptr == HPM_PTMR) {
+        clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_ptmr);
+    } else {
+        /* Not supported */
+    }
+    return freq;
 }
 

bsp/hpmicro/hpm5301evklite/board/board.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023 HPMicro
+ * Copyright (c) 2023-2025 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -23,6 +23,7 @@
 
 /* ACMP desction */
 #define BOARD_ACMP             HPM_ACMP
+#define BOARD_ACMP_CLK         clock_acmp0
 #define BOARD_ACMP_CHANNEL     ACMP_CHANNEL_CHN1
 #define BOARD_ACMP_IRQ         IRQn_ACMP_1
 #define BOARD_ACMP_PLUS_INPUT  ACMP_INPUT_DAC_OUT  /* use internal DAC */
@@ -39,15 +40,26 @@
 #define BOARD_RUNNING_CORE HPM_CORE0
 #endif
 
+/* uart section */
 #ifndef BOARD_APP_UART_BASE
-#define BOARD_APP_UART_BASE HPM_UART3
-#define BOARD_APP_UART_IRQ  IRQn_UART3
+#define BOARD_APP_UART_BASE       HPM_UART3
+#define BOARD_APP_UART_IRQ        IRQn_UART3
 #define BOARD_APP_UART_BAUDRATE   (115200UL)
 #define BOARD_APP_UART_CLK_NAME   clock_uart3
 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART3_RX
 #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART3_TX
 #endif
 
+#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PA26
+
+/* Trigger UART: UART0~3 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG0, UART4~7 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 */
+#define BOARD_APP_UART_TRIG                 HPM_TRGM0_OUTPUT_SRC_UART_TRIG0
+#define BOARD_UART_TRGM                     HPM_TRGM0
+#define BOARD_UART_TRGM_GPTMR               HPM_GPTMR1
+#define BOARD_UART_TRGM_GPTMR_CLK           clock_gptmr1
+#define BOARD_UART_TRGM_GPTMR_CH            2
+#define BOARD_UART_TRGM_GPTMR_INPUT         HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2
+
 /* uart lin sample section */
 #define BOARD_UART_LIN          BOARD_APP_UART_BASE
 #define BOARD_UART_LIN_IRQ      BOARD_APP_UART_IRQ
@@ -55,7 +67,6 @@
 #define BOARD_UART_LIN_TX_PORT  GPIO_DI_GPIOB
 #define BOARD_UART_LIN_TX_PIN   (15U) /* PB15 should align with used pin in pinmux configuration */
 
-
 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
 #ifndef BOARD_CONSOLE_TYPE
 #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART
@@ -63,9 +74,9 @@
 
 #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
 #ifndef BOARD_CONSOLE_UART_BASE
-#define BOARD_CONSOLE_UART_BASE     HPM_UART0
-#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0
-#define BOARD_CONSOLE_UART_IRQ      IRQn_UART0
+#define BOARD_CONSOLE_UART_BASE       HPM_UART0
+#define BOARD_CONSOLE_UART_CLK_NAME   clock_uart0
+#define BOARD_CONSOLE_UART_IRQ        IRQn_UART0
 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX
 #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX
 #endif
@@ -81,6 +92,8 @@
 
 /* rtthread-nano finsh section */
 #define BOARD_RT_CONSOLE_BASE        BOARD_CONSOLE_UART_BASE
+#define BOARD_RT_CONSOLE_CLK_NAME    BOARD_CONSOLE_UART_CLK_NAME
+#define BOARD_RT_CONSOLE_IRQ         BOARD_CONSOLE_UART_IRQ
 
 /* modbus sample section */
 #define BOARD_MODBUS_UART_BASE       BOARD_APP_UART_BASE
@@ -93,26 +106,26 @@
 #define BOARD_FLASH_SIZE         (SIZE_1MB)
 
 /* i2c section */
-#define BOARD_APP_I2C_BASE     HPM_I2C2
-#define BOARD_APP_I2C_IRQ      IRQn_I2C2
-#define BOARD_APP_I2C_CLK_NAME clock_i2c2
+#define BOARD_APP_I2C_BASE     HPM_I2C3
+#define BOARD_APP_I2C_IRQ      IRQn_I2C3
+#define BOARD_APP_I2C_CLK_NAME clock_i2c3
 #define BOARD_APP_I2C_DMA      HPM_HDMA
 #define BOARD_APP_I2C_DMAMUX   HPM_DMAMUX
-#define BOARD_APP_I2C_DMA_SRC  HPM_DMA_SRC_I2C2
+#define BOARD_APP_I2C_DMA_SRC  HPM_DMA_SRC_I2C3
 
 /* gptmr section */
 #define BOARD_GPTMR                   HPM_GPTMR0
 #define BOARD_GPTMR_IRQ               IRQn_GPTMR0
-#define BOARD_GPTMR_CHANNEL           0
-#define BOARD_GPTMR_DMA_SRC           HPM_DMA_SRC_GPTMR0_0
+#define BOARD_GPTMR_CHANNEL           1
+#define BOARD_GPTMR_DMA_SRC           HPM_DMA_SRC_GPTMR0_1
 #define BOARD_GPTMR_CLK_NAME          clock_gptmr0
 #define BOARD_GPTMR_PWM               HPM_GPTMR0
-#define BOARD_GPTMR_PWM_CHANNEL       0
-#define BOARD_GPTMR_PWM_DMA_SRC       HPM_DMA_SRC_GPTMR0_0
+#define BOARD_GPTMR_PWM_CHANNEL       1
+#define BOARD_GPTMR_PWM_DMA_SRC       HPM_DMA_SRC_GPTMR0_1
 #define BOARD_GPTMR_PWM_CLK_NAME      clock_gptmr0
 #define BOARD_GPTMR_PWM_IRQ           IRQn_GPTMR0
 #define BOARD_GPTMR_PWM_SYNC          HPM_GPTMR0
-#define BOARD_GPTMR_PWM_SYNC_CHANNEL  1
+#define BOARD_GPTMR_PWM_SYNC_CHANNEL  2
 #define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr0
 
 /* User LED */
@@ -121,91 +134,94 @@
 #define BOARD_LED_GPIO_PIN   10
 
 #define BOARD_LED_OFF_LEVEL 1
-#define BOARD_LED_ON_LEVEL 0
+#define BOARD_LED_ON_LEVEL  0
 
 /* 12V Power Enable*/
-#define BOARD_12V_EN_GPIO_CTRL HPM_GPIO0
+#define BOARD_12V_EN_GPIO_CTRL  HPM_GPIO0
 #define BOARD_12V_EN_GPIO_INDEX GPIO_DI_GPIOA
-#define BOARD_12V_EN_GPIO_PIN 24
+#define BOARD_12V_EN_GPIO_PIN   24
 
 /* gpiom section */
 #define BOARD_APP_GPIOM_BASE            HPM_GPIOM
 #define BOARD_APP_GPIOM_USING_CTRL      HPM_FGPIO
 #define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast
 
-/* GPIO read value macro,spec for sample cherryusb on board hpm5301evklite*/
-#define BOARD_BUTTON_PRESSED_VALUE 1
-
 /* tinyuf2 button on hpm5301evklite*/
 #define BOARD_BUTTON_TINYUF2_PIN 9
 
 /* User button */
-#define BOARD_APP_GPIO_CTRL HPM_GPIO0
+#define BOARD_APP_GPIO_CTRL  HPM_GPIO0
 #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOA
-#define BOARD_APP_GPIO_PIN 3
-#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_A
+#define BOARD_APP_GPIO_PIN   3
+#define BOARD_APP_GPIO_IRQ   IRQn_GPIO0_A
+#define BOARD_BUTTON_PRESSED_VALUE 1
 
 /* spi section */
-#define BOARD_APP_SPI_BASE HPM_SPI1
+#define BOARD_APP_SPI_BASE              HPM_SPI1
 #define BOARD_APP_SPI_CLK_NAME          clock_spi1
 #define BOARD_APP_SPI_IRQ               IRQn_SPI1
 #define BOARD_APP_SPI_SCLK_FREQ         (20000000UL)
 #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U)
 #define BOARD_APP_SPI_DATA_LEN_IN_BITS  (8U)
-#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI1_RX
-#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI1_TX
-#define BOARD_SPI_CS_GPIO_CTRL           HPM_GPIO0
-#define BOARD_SPI_CS_PIN                 IOC_PAD_PA26
-#define BOARD_SPI_CS_ACTIVE_LEVEL        (0U)
+#define BOARD_APP_SPI_RX_DMA            HPM_DMA_SRC_SPI1_RX
+#define BOARD_APP_SPI_TX_DMA            HPM_DMA_SRC_SPI1_TX
+#define BOARD_SPI_CS_GPIO_CTRL          HPM_GPIO0
+#define BOARD_SPI_CS_PIN                IOC_PAD_PA26
+#define BOARD_SPI_CS_ACTIVE_LEVEL       (0U)
 
 /* ADC section */
-#define BOARD_APP_ADC16_NAME      "ADC0"
-#define BOARD_APP_ADC16_BASE      HPM_ADC0
-#define BOARD_APP_ADC16_IRQn      IRQn_ADC0
-#define BOARD_APP_ADC16_CH_1      (11U)
-#define BOARD_APP_ADC16_CLK_NAME  (clock_adc0)
-
-#define BOARD_APP_ADC16_PMT_TRIG_CH        ADC16_CONFIG_TRG0A
+#define BOARD_APP_ADC16_NAME     "ADC0"
+#define BOARD_APP_ADC16_BASE     HPM_ADC0
+#define BOARD_APP_ADC16_IRQn     IRQn_ADC0
+#define BOARD_APP_ADC16_CH_1     (2U)
+#define BOARD_APP_ADC16_CLK_NAME (clock_adc0)
+#define BOARD_APP_ADC16_CLK_BUS  (clk_adc_src_ahb0)
+#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A
 
 /* Flash section */
-#define BOARD_APP_XPI_NOR_XPI_BASE            (HPM_XPI0)
-#define BOARD_APP_XPI_NOR_CFG_OPT_HDR         (0xfcf90002U)
-#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0        (0x00000006U)
-#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1        (0x00001000U)
+#define BOARD_APP_XPI_NOR_XPI_BASE     (HPM_XPI0)
+#define BOARD_APP_XPI_NOR_CFG_OPT_HDR  (0xfcf90002U)
+#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000006U)
+#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U)
 
 /* CALLBACK TIMER section */
-#define BOARD_CALLBACK_TIMER (HPM_GPTMR1)
-#define BOARD_CALLBACK_TIMER_CH 0
-#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR1
+#define BOARD_CALLBACK_TIMER          (HPM_GPTMR1)
+#define BOARD_CALLBACK_TIMER_CH       0
+#define BOARD_CALLBACK_TIMER_IRQ      IRQn_GPTMR1
 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr1)
 
 /*Timer define*/
-#define BOARD_BLDC_TMR_1MS                       HPM_GPTMR2
-#define BOARD_BLDC_TMR_CH                        0
-#define BOARD_BLDC_TMR_CMP                       0
-#define BOARD_BLDC_TMR_IRQ                       IRQn_GPTMR2
-#define BOARD_BLDC_TMR_RELOAD                    (100000U)
+#define BOARD_BLDC_TMR_1MS    HPM_GPTMR2
+#define BOARD_BLDC_TMR_CH     0
+#define BOARD_BLDC_TMR_CMP    0
+#define BOARD_BLDC_TMR_IRQ    IRQn_GPTMR2
+#define BOARD_BLDC_TMR_CLOCK  clock_gptmr2
+#define BOARD_BLDC_TMR_RELOAD (100000U)
 
 /*adc*/
-#define BOARD_BLDC_ADC_MODULE                  (ADCX_MODULE_ADC16)
-#define BOARD_BLDC_ADC_U_BASE                  HPM_ADC0
-#define BOARD_BLDC_ADC_V_BASE                  HPM_ADC1
-#define BOARD_BLDC_ADC_W_BASE                  HPM_ADC1
-#define BOARD_BLDC_ADC_TRIG_FLAG               adc16_event_trig_complete
-
-#define BOARD_BLDC_ADC_CH_U                    (5U)
-#define BOARD_BLDC_ADC_CH_V                    (6U)
-#define BOARD_BLDC_ADC_CH_W                    (4U)
-#define BOARD_BLDC_ADC_IRQn                    IRQn_ADC0
-#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES  (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES)
+#define BOARD_BLDC_ADC_MODULE    (ADCX_MODULE_ADC16)
+#define BOARD_BLDC_ADC_U_BASE    HPM_ADC0
+#define BOARD_BLDC_ADC_V_BASE    HPM_ADC1
+#define BOARD_BLDC_ADC_W_BASE    HPM_ADC1
+#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete
+
+#define BOARD_BLDC_ADC_CH_U                   (5U)
+#define BOARD_BLDC_ADC_CH_V                   (6U)
+#define BOARD_BLDC_ADC_CH_W                   (4U)
+#define BOARD_BLDC_ADC_IRQn                   IRQn_ADC0
+#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES)
 #define BOARD_BLDC_ADC_TRG                    ADC16_CONFIG_TRG0A
-#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN        (1U)
-#define BOARD_BLDC_PWM_TRIG_CMP_INDEX          (8U)
-#define BOARD_BLDC_TRIGMUX_IN_NUM              HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
-#define BOARD_BLDC_TRG_NUM                     TRGM_TRGOCFG_ADCX_PTRGI0A
-
-/* USB */
-#define BOARD_USB HPM_USB0
+#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN       (1U)
+#define BOARD_BLDC_PWM_TRIG_CMP_INDEX         (8U)
+#define BOARD_BLDC_TRG_ADC                    TRGM_TRGOCFG_ADCX_PTRGI0A
+#define BOARD_BLDC_PWM_TRG_ADC                HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
+#define BOARD_BLDC_DMA_MUX_SRC                HPM_DMA_SRC_MOT_0
+#define BOARD_BLDC_DMA_CHN                    (0U)
+#define BOARD_BLDC_DMA_TRG_DST                TRGM_TRGOCFG_TRGM_DMA0
+#define BOARD_BLDC_DMA_TRG_SRC                HPM_TRGM0_DMA_SRC_TRGM0
+#define BOARD_BLDC_DMA_TRG_INDEX              TRGM_DMACFG_0
+#define BOARD_BLDC_DMA_TRG_CMP_INDEX          (9U)
+#define BOARD_BLDC_DMA_TRG_IN                 HPM_TRGM0_INPUT_SRC_PWM0_CH9REF
 
 #ifndef BOARD_SHOW_CLOCK
 #define BOARD_SHOW_CLOCK 1
@@ -220,29 +236,77 @@
 #define BOARD_FREERTOS_TIMER_IRQ      IRQn_GPTMR0
 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr0
 
+#define BOARD_FREERTOS_TICK_SRC_PWM          HPM_PWM0
+#define BOARD_FREERTOS_TICK_SRC_PWM_IRQ      IRQn_PWM0
+#define BOARD_FREERTOS_TICK_SRC_PWM_CLK_NAME clock_mot0
+
+#define BOARD_FREERTOS_LOWPOWER_TIMER          HPM_PTMR
+#define BOARD_FREERTOS_LOWPOWER_TIMER_CHANNEL  1
+#define BOARD_FREERTOS_LOWPOWER_TIMER_IRQ      IRQn_PTMR
+#define BOARD_FREERTOS_LOWPOWER_TIMER_CLK_NAME clock_ptmr
+
 /* Threadx Definitions */
-#define BOARD_THREADX_TIMER           HPM_GPTMR0
-#define BOARD_THREADX_TIMER_CHANNEL   1
-#define BOARD_THREADX_TIMER_IRQ       IRQn_GPTMR0
-#define BOARD_THREADX_TIMER_CLK_NAME  clock_gptmr0
+#define BOARD_THREADX_TIMER          HPM_GPTMR0
+#define BOARD_THREADX_TIMER_CHANNEL  1
+#define BOARD_THREADX_TIMER_IRQ      IRQn_GPTMR0
+#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr0
+
+#define BOARD_THREADX_LOWPOWER_TIMER          HPM_PTMR
+#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL  1
+#define BOARD_THREADX_LOWPOWER_TIMER_IRQ      IRQn_PTMR
+#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr
+
+/* uC/OS-III Definitions */
+#define BOARD_UCOS_TIMER          HPM_GPTMR0
+#define BOARD_UCOS_TIMER_CHANNEL  1
+#define BOARD_UCOS_TIMER_IRQ      IRQn_GPTMR0
+#define BOARD_UCOS_TIMER_CLK_NAME clock_gptmr0
+
+/* i2s over spi Section*/
+#define BOARD_I2S_SPI_CS_GPIO_CTRL  HPM_GPIO0
+#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOA
+#define BOARD_I2S_SPI_CS_GPIO_PIN   31
+#define BOARD_I2S_SPI_CS_GPIO_PAD   IOC_PAD_PA31
+
+#define BOARD_GPTMR_I2S_MCLK          HPM_GPTMR1
+#define BOARD_GPTMR_I2S_MCLK_CHANNEL  1
+#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr1
+
+#define BOARD_GPTMR_I2S_LRCK          HPM_GPTMR0
+#define BOARD_GPTMR_I2S_LRCK_CHANNEL  2
+#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr0
+
+#define BOARD_GPTMR_I2S_BCLK          HPM_GPTMR0
+#define BOARD_GPTMR_I2S_BLCK_CHANNEL  3
+#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr0
+
+#define BOARD_GPTMR_I2S_FINSH          HPM_GPTMR0
+#define BOARD_GPTMR_I2S_FINSH_IRQ      IRQn_GPTMR0
+#define BOARD_GPTMR_I2S_FINSH_CHANNEL  0
+#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr0
+
+#define BOARD_APP_CLK_REF_PIN_NAME "J3[32] (PA09)"
+#define BOARD_APP_CLK_REF_CLK_NAME clock_ref0
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
 
 typedef void (*board_timer_cb)(void);
 
-void board_init_console(void);
 void board_init_gpio_pins(void);
 void board_init_led_pins(void);
-void board_init_usb_pins(void);
+void board_init_usb(USB_Type *ptr);
 void board_led_write(uint8_t state);
 void board_led_toggle(void);
+void board_init_console(void);
 void board_init_uart(UART_Type *ptr);
 uint32_t board_init_spi_clock(SPI_Type *ptr);
 void board_init_spi_pins(SPI_Type *ptr);
-void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level);
-uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb);
+uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus);
 void board_init_adc16_pins(void);
+void board_init_acmp_pins(void);
+void board_init_acmp_clock(ACMP_Type *ptr);
 void board_disable_output_rgb_led(uint8_t color);
 void board_enable_output_rgb_led(uint8_t color);
 void board_write_spi_cs(uint32_t pin, uint8_t state);
@@ -251,7 +315,6 @@ void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr);
 void board_init(void);
 void board_init_usb_dp_dm_pins(void);
 void board_init_clock(void);
-uint32_t board_init_gptmr_clock(GPTMR_Type *ptr);
 void board_delay_us(uint32_t us);
 void board_delay_ms(uint32_t ms);
 void board_timer_create(uint32_t ms, board_timer_cb cb);
@@ -263,7 +326,13 @@ void board_init_pmp(void);
 
 uint32_t board_init_uart_clock(UART_Type *ptr);
 
+uint32_t board_init_i2c_clock(I2C_Type *ptr);
 void board_init_i2c(I2C_Type *ptr);
+
+void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp);
+void board_init_clk_ref_pin(void);
+uint32_t board_init_gptmr_clock(GPTMR_Type *ptr);
+
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */

bsp/hpmicro/hpm5301evklite/board/linker_scripts/flash_rtt.ld → bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/flash_rtt.ld

@@ -1,5 +1,5 @@
 /*
- * Copyright 2021-2023 HPMicro
+ * Copyright 2021-2025 HPMicro
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
@@ -14,7 +14,7 @@ MEMORY
 {
     XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
     ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K
-    DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K
+    DLM (w) : ORIGIN = 0x00080300, LENGTH = 128K - 768
     AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K
 }
 
@@ -41,22 +41,25 @@ SECTIONS
     .start __app_load_addr__ : {
         . = ALIGN(8);
         KEEP(*(.start))
+        . = ALIGN(16);
     } > XPI0
 
-    __vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
+     __vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
     .vectors : AT(__vector_load_addr__) {
-        . = ALIGN(8);
+        . = ALIGN(16);
         __vector_ram_start__ = .;
         KEEP(*(.vector_table))
         KEEP(*(.isr_vector))
-        . = ALIGN(8);
+        . = ALIGN(16);
         __vector_ram_end__ = .;
     } > ILM
 
-    .fast : AT(etext + __data_end__ - __tdata_start__) {
-        . = ALIGN(8);
+    .fast : AT(__fast_load_addr__) {
+        . = ALIGN(16);
         __ramfunc_start__ = .;
         *(.fast)
+        *(.fast.*)
+        . = ALIGN(16);
 
         /* RT-Thread Core Start */
         KEEP(*context_gcc.o(.text* .rodata*))
@@ -77,12 +80,12 @@ SECTIONS
         KEEP(*mempool.o (.text .text* .rodata .rodata*))
         /* RT-Thread Core End */
 
-        . = ALIGN(8);
+        . = ALIGN(16);
         __ramfunc_end__ = .;
     } > ILM
 
-    .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
-        . = ALIGN(8);
+    .text (__vector_load_addr__ + SIZEOF(.vectors)) : {
+        . = ALIGN(16);
         *(.text)
         *(.text*)
         *(.rodata)
@@ -107,12 +110,6 @@ SECTIONS
          *      RT-Thread related sections - Start
          *
         *********************************************/
-        /* section information for utest */
-        . = ALIGN(4);
-        __rt_utest_tc_tab_start = .;
-        KEEP(*(UtestTcTab))
-        __rt_utest_tc_tab_end = .;
-
         /* section information for finsh shell */
         . = ALIGN(4);
         __fsymtab_start = .;
@@ -146,6 +143,20 @@ SECTIONS
 
     } > XPI0
 
+    .eh_frame :
+    {
+        __eh_frame_start = .;
+        KEEP(*(.eh_frame))
+        __eh_frame_end = .;
+    }  > XPI0
+
+    .eh_frame_hdr :
+    {
+        KEEP(*(.eh_frame_hdr))
+    }  > XPI0
+    __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0;
+    __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0;
+
     .rel : {
         KEEP(*(.rel*))
     } > XPI0
@@ -158,19 +169,14 @@ SECTIONS
         KEEP(*(.fast_ram))
     } > DLM
 
-    .bss(NOLOAD) : {
+    __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
+        .fast_ram.init : AT(__fast_ram_init_load_addr__) {
         . = ALIGN(8);
-        __bss_start__ = .;
-        *(.bss)
-        *(.bss*)
-        *(.sbss*)
-        *(.scommon)
-        *(.scommon*)
-        *(.dynsbss*)
-        *(COMMON)
+        __fast_ram_init_start__ = .;
+        KEEP(*(.fast_ram.init))
+        KEEP(*(.fast_ram.init.*))
+        __fast_ram_init_end__ = .;
         . = ALIGN(8);
-        _end = .;
-        __bss_end__ = .;
     } > DLM
 
     /* Note: the .tbss and .tdata section should be adjacent */
@@ -178,22 +184,26 @@ SECTIONS
         . = ALIGN(8);
         __tbss_start__ = .;
         *(.tbss*)
+        *(.gnu.linkonce.tb.*)
         *(.tcommon*)
         _end = .;
         __tbss_end__ = .;
     } > DLM
 
-    .tdata : AT(etext) {
+    __tdata_load_addr__ = etext;
+    .tdata : AT(__tdata_load_addr__) {
         . = ALIGN(8);
         __tdata_start__ = .;
         __thread_pointer = .;
         *(.tdata)
         *(.tdata*)
+        *(.gnu.linkonce.td.*)
         . = ALIGN(8);
         __tdata_end__ = .;
     } > DLM
 
-    .data : AT(etext + __tdata_end__ - __tdata_start__) {
+    __data_load_addr__ = etext + SIZEOF(.tdata);
+    .data : AT(__data_load_addr__) {
         . = ALIGN(8);
         __data_start__ = .;
         __global_pointer$ = . + 0x800;
@@ -221,10 +231,10 @@ SECTIONS
         PROVIDE(__init_array_end = .);
 
         . = ALIGN(8);
-        PROVIDE(__finit_array_start = .);
-        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
-        KEEP(*(.finit_array))
-        PROVIDE(__finit_array_end = .);
+        PROVIDE(__fini_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE(__fini_array_end = .);
 
         . = ALIGN(8);
         PROVIDE(__ctors_start__ = .);
@@ -245,6 +255,26 @@ SECTIONS
         PROVIDE (_edata = .);
         PROVIDE (edata = .);
     } > DLM
+
+    __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata);
+
+    __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr);
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > DLM
+
     __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
 
     .heap(NOLOAD) : {
@@ -265,7 +295,8 @@ SECTIONS
         PROVIDE( __rt_rvstack = . );
     } > DLM
 
-    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
+    __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
+    .noncacheable.init : AT(__noncacheable_init_load_addr__) {
         . = ALIGN(8);
         __noncacheable_init_start__ = .;
         KEEP(*(.noncacheable.init))
@@ -276,8 +307,11 @@ SECTIONS
     .noncacheable.bss (NOLOAD) : {
         . = ALIGN(8);
         KEEP(*(.noncacheable))
+        KEEP(*(.noncacheable.non_init))
+        KEEP(*(.noncacheable.non_init.*))
         __noncacheable_bss_start__ = .;
         KEEP(*(.noncacheable.bss))
+        KEEP(*(.noncacheable.bss.*))
         __noncacheable_bss_end__ = .;
         . = ALIGN(8);
     } > DLM

bsp/hpmicro/hpm5301evklite/board/linker_scripts/ram_rtt.ld → bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/ram_rtt.ld

@@ -1,5 +1,5 @@
 /*
- * Copyright 2021-2023 HPMicro
+ * Copyright 2021-2025 HPMicro
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
@@ -12,9 +12,9 @@ NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x8000;
 MEMORY
 {
     ILM (wx) : ORIGIN = 0, LENGTH = 128K
-    DLM (w) : ORIGIN = 0x80000, LENGTH = 128K
+    DLM (w) : ORIGIN = 0x80300, LENGTH = 96K - 768
     NONCACHEABLE_RAM (wx) : ORIGIN = 0x98000, LENGTH = NONCACHEABLE_SIZE
-    AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
+    AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k
 }
 
 SECTIONS
@@ -30,10 +30,6 @@ SECTIONS
         KEEP(*(.vector_table))
         . = ALIGN(8);
     } > ILM
-    
-    .fast_ram (NOLOAD) : {
-        KEEP(*(.fast_ram))
-    } > ILM
 
     .text : {
         . = ALIGN(8);
@@ -56,7 +52,7 @@ SECTIONS
         KEEP (*(.init))
         KEEP (*(.fini))
         . = ALIGN(8);
-        
+
         /*********************************************
          *
          *      RT-Thread related sections - Start
@@ -92,28 +88,74 @@ SECTIONS
         __usbh_class_info_start__ = .;
         KEEP(*(.usbh_class_info))
         __usbh_class_info_end__ = .;
+        PROVIDE (__etext = .);
+        PROVIDE (_etext = .);
+        PROVIDE (etext = .);
 
     } > ILM
-    
-    PROVIDE (__etext = .);
-    PROVIDE (_etext = .);
-    PROVIDE (etext = .);
 
-    .tdata : AT(etext) {
+    .rel : {
+        KEEP(*(.rel*))
+    } > DLM
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > ILM
+
+    __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
+    .fast_ram.init : AT(__fast_ram_init_load_addr__) {
+        . = ALIGN(8);
+        __fast_ram_init_start__ = .;
+        KEEP(*(.fast_ram.init))
+        KEEP(*(.fast_ram.init.*))
+        __fast_ram_init_end__ = .;
+        . = ALIGN(8);
+    } > ILM
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > DLM
+
+    /* Note: .tbss and .tdata should be adjacent */
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.gnu.linkonce.tb.*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > DLM
+
+    __tdata_load_addr__ = etext;
+    .tdata : AT(__tdata_load_addr__) {
         . = ALIGN(8);
         __tdata_start__ = .;
         __thread_pointer = .;
         *(.tdata)
         *(.tdata*)
+        *(.gnu.linkonce.td.*)
         . = ALIGN(8);
         __tdata_end__ = .;
     } > DLM
 
-    .data : AT(etext + __tdata_end__ - __tdata_start__) {
+    __data_load_addr__ = etext + SIZEOF(.tdata);
+    .data : AT(__data_load_addr__) {
         . = ALIGN(8);
         __data_start__ = .;
         __global_pointer$ = . + 0x800;
-        
+
         *(.data)
         *(.data*)
         *(.sdata)
@@ -138,10 +180,10 @@ SECTIONS
         PROVIDE(__init_array_end = .);
 
         . = ALIGN(8);
-        PROVIDE(__finit_array_start = .);
-        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
-        KEEP(*(.finit_array))
-        PROVIDE(__finit_array_end = .);
+        PROVIDE(__fini_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE(__fini_array_end = .);
 
         . = ALIGN(8);
         PROVIDE(__ctors_start__ = .);
@@ -164,43 +206,39 @@ SECTIONS
         PROVIDE (edata = .);
     } > DLM
 
-    .fast : AT(etext + __data_end__ - __tdata_start__) {
+    __fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data);
+    .fast : AT(__fast_load_addr__) {
         . = ALIGN(8);
         PROVIDE(__ramfunc_start__ = .);
         *(.fast)
         . = ALIGN(8);
         PROVIDE(__ramfunc_end__ = .);
     } > DLM
-    
-    .rel : {
-        KEEP(*(.rel*))
-    } > DLM
 
-    .bss(NOLOAD) : {
+    __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
+    .noncacheable.init : AT(__noncacheable_init_load_addr__) {
         . = ALIGN(8);
-        __bss_start__ = .;
-        *(.bss)
-        *(.bss*)
-        *(.sbss*)
-        *(.scommon)
-        *(.scommon*)
-        *(.dynsbss*)
-        *(COMMON)
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
         . = ALIGN(8);
-        _end = .;
-        __bss_end__ = .;
-    } > DLM
+    } > NONCACHEABLE_RAM
 
-    /* Note: .tbss and .tdata should be adjacent */
-    .tbss(NOLOAD) : {
+    .noncacheable.bss (NOLOAD) : {
         . = ALIGN(8);
-        __tbss_start__ = .;
-        *(.tbss*)
-        *(.tcommon*)
-        _end = .;
-        __tbss_end__ = .;
-    } > DLM
-    
+        KEEP(*(.noncacheable))
+        KEEP(*(.noncacheable.non_init))
+        KEEP(*(.noncacheable.non_init.*))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        KEEP(*(.noncacheable.bss.*))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
+    __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
+
     .stack(NOLOAD) : {
         . = ALIGN(8);
         __stack_base__ = .;
@@ -221,24 +259,4 @@ SECTIONS
      .ahb_sram (NOLOAD) : {
         KEEP(*(.ahb_sram))
     } > AHB_SRAM
-    
-    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
-        . = ALIGN(8);
-        __noncacheable_init_start__ = .;
-        KEEP(*(.noncacheable.init))
-        __noncacheable_init_end__ = .;
-        . = ALIGN(8);
-    } > NONCACHEABLE_RAM
-
-    .noncacheable.bss (NOLOAD) : {
-        . = ALIGN(8);
-        KEEP(*(.noncacheable))
-        __noncacheable_bss_start__ = .;
-        KEEP(*(.noncacheable.bss))
-        __noncacheable_bss_end__ = .;
-        . = ALIGN(8);
-    } > NONCACHEABLE_RAM
-
-    __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
-    __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
 }

bsp/hpmicro/hpm5301evklite/board/pinmux.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023 HPMicro
+ * Copyright (c) 2023,2025 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -15,15 +15,6 @@
 #include "board.h"
 #include "pinmux.h"
 
-void init_xtal_pins(void)
-{
-    /* Package QFN32 should be set PA30 and PA31 pins as analog type to enable xtal. */
-    /*
-     * HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
-     * HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
-     */
-}
-
 void init_py_pins_as_pgpio(void)
 {
     /* Set PY00-PY05 default function to PGPIO */
@@ -40,10 +31,6 @@ void init_uart_pins(UART_Type *ptr)
     if (ptr == HPM_UART0) {
         HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD;
         HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD;
-    } else if (ptr == HPM_UART2) {
-        HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_UART2_TXD;
-        HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_UART2_RXD;
-        HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_UART2_DE;
     } else if (ptr == HPM_UART3) {
         HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_UART3_TXD;
         HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_UART3_RXD;
@@ -73,8 +60,11 @@ void init_i2c_pins(I2C_Type *ptr)
         HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_I2C2_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
         HPM_IOC->PAD[IOC_PAD_PB08].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
         HPM_IOC->PAD[IOC_PAD_PB09].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
-    } else {
-        ;
+    } else if (ptr == HPM_I2C3) {
+        HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_I2C3_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_I2C3_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+        HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
     }
 }
 
@@ -96,6 +86,12 @@ void init_spi_pins(SPI_Type *ptr)
         HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
         HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO;
         HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI;
+
+        /* set max frequency slew rate(200M) */
+        HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1);
+        HPM_IOC->PAD[IOC_PAD_PA27].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PA28].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PA29].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
     }
 }
 
@@ -106,13 +102,26 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
         HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
         HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO;
         HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI;
+
+        /* set max frequency slew rate(200M) */
+        HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1);
+        HPM_IOC->PAD[IOC_PAD_PA27].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PA28].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PA29].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
     }
 }
 
 
 void init_gptmr_pins(GPTMR_Type *ptr)
 {
-    (void) ptr;
+    if (ptr == HPM_GPTMR0) {
+        HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPTMR0_COMP_2;
+        HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_GPTMR0_COMP_3;
+        HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPTMR0_CAPT_1;
+        HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1;
+    } else if (ptr == HPM_GPTMR1) {
+        HPM_IOC->PAD[IOC_PAD_PA02].FUNC_CTL = IOC_PA02_FUNC_CTL_GPTMR1_COMP_1;
+    }
 }
 
 void init_butn_pins(void)
@@ -152,22 +161,24 @@ void init_adc_bldc_pins(void)
     HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;         /* ADC_IV:   ADC0.6 /ADC1.6  */
 }
 
-void init_usb_pins(void)
+void init_usb_pins(USB_Type *ptr)
 {
-    HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
-    HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
-
-    /* USB0_ID */
-    HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID;
-    /* USB0_OC */
-    HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC;
-    /* USB0_PWR */
-    HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR;
-
-    /* PY port IO needs to configure PIOC as well */
-    HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00;
-    HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01;
-    HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02;
+    if (ptr == HPM_USB0) {
+        HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+        HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+
+        /* USB0_ID */
+        HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID;
+        /* USB0_OC */
+        HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC;
+        /* USB0_PWR */
+        HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR;
+
+        /* PY port IO needs to configure PIOC as well */
+        HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00;
+        HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01;
+        HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02;
+    }
 }
 
 void init_led_pins_as_gpio(void)
@@ -175,3 +186,43 @@ void init_led_pins_as_gpio(void)
     HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_GPIO_A_10;
 }
 
+/* for uart_rx_line_status case, need to a gpio pin to sent break signal */
+void init_uart_break_signal_pin(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+    HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPIO_A_26;
+}
+
+void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp)
+{
+    if (ptr == HPM_GPTMR0) {
+        if (as_comp) {
+            switch (channel) {
+            case 1:
+                HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1;
+                break;
+            case 2:
+                HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPTMR0_COMP_2;
+                break;
+            case 3:
+                HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_GPTMR0_COMP_3;
+                break;
+            default:
+                break;
+            }
+        } else {
+            if (channel == 1) {
+                HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPTMR0_CAPT_1;
+            }
+        }
+    } else if (ptr == HPM_GPTMR1) {
+        if ((as_comp == true) && (channel == 3)) {
+            HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPTMR1_COMP_3;
+        }
+    }
+}
+
+void init_clk_ref_pin(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_SOC_REF0;
+}

bsp/hpmicro/hpm5301evklite/board/pinmux.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023 HPMicro
+ * Copyright (c) 2023,2025 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -11,9 +11,9 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-void init_xtal_pins(void);
 void init_py_pins_as_pgpio(void);
 void init_uart_pins(UART_Type *ptr);
+void init_uart_pin_as_gpio(UART_Type *ptr);
 void init_i2c_pins(I2C_Type *ptr);
 void init_gpio_pins(void);
 void init_spi_pins(SPI_Type *ptr);
@@ -23,8 +23,12 @@ void init_butn_pins(void);
 void init_acmp_pins(void);
 void init_adc_pins(void);
 void init_adc_bldc_pins(void);
-void init_usb_pins(void);
+void init_usb_pins(USB_Type *ptr);
 void init_led_pins_as_gpio(void);
+void init_uart_break_signal_pin(void);
+void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp);
+void init_clk_ref_pin(void);
+
 #ifdef __cplusplus
 }
 #endif

bsp/hpmicro/hpm5301evklite/board/rtt_board.c

@@ -52,7 +52,7 @@ void rtt_board_init(void)
     os_tick_config();
 
     /* Configure the USB pins*/
-    board_init_usb_pins();
+    board_init_usb(HPM_USB0);
 
     /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */
     rt_hw_uart_init();
@@ -63,6 +63,7 @@ void rtt_board_init(void)
 
 void app_init_led_pins(void)
 {
+    board_init_led_pins();
     gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
     gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL);
 }
@@ -96,7 +97,7 @@ void rt_hw_console_output(const char *str)
 
 void app_init_usb_pins(void)
 {
-    board_init_usb_pins();
+    board_init_usb(HPM_USB0);
 }
 
 ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
@@ -108,7 +109,7 @@ ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
 
 void rt_hw_cpu_reset(void)
 {
-    HPM_PPOR->RESET_ENABLE = (1UL << 31);
+    HPM_PPOR->RESET_ENABLE |= (1UL << 31);
 
     HPM_PPOR->SOFTWARE_RESET = 1000U;
     while(1) {
@@ -117,3 +118,39 @@ void rt_hw_cpu_reset(void)
 }
 
 MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);
+
+#ifdef RT_USING_CACHE
+void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
+{
+    if (ops == RT_HW_CACHE_FLUSH) {
+        l1c_dc_flush((uint32_t)addr, size);
+    } else {
+        l1c_dc_invalidate((uint32_t)addr, size);
+    }
+}
+#endif
+
+uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
+{
+    uint32_t freq = 0;
+
+    if (ptr == HPM_ADC0) {
+        if (clk_src_ahb) {
+            /* Configure the ADC clock from AHB (@200MHz by default)*/
+            clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
+        } else {
+            /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
+            clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
+            clock_set_source_divider(clock_ana0, clk_src_pll0_clk2, 2U);
+        }
+        clock_add_to_group(clock_adc0, 0);
+        freq = clock_get_frequency(clock_adc0);
+    }
+
+    return freq;
+}
+
+#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER
+extern void hpm_isr_usb0(void);
+RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0)
+#endif

bsp/hpmicro/hpm5301evklite/board/rtt_board.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 hpmicro
+ * Copyright (c) 2021 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -10,8 +10,10 @@
 #include "hpm_common.h"
 #include "hpm_soc.h"
 #include <drv_gpio.h>
+#include "board.h"
 
 /* gpio section */
+#define APP_LED0         (0U)
 #define APP_LED0_PIN_NUM GET_PIN(A, 10)
 #define APP_LED_ON (1)
 #define APP_LED_OFF (0)
@@ -21,13 +23,23 @@
 /* mchtimer section */
 #define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
 
+/* gptmr as os_tick */
+#define BOARD_OS_TIMER HPM_GPTMR0
+#define BOARD_OS_TIMER_CH       1
+#define BOARD_OS_TIMER_IRQ      IRQn_GPTMR0
+#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0)
+
 /* CAN section */
 #define BOARD_CAN_NAME                        "can0"
 #define BOARD_CAN_HWFILTER_INDEX              (0U)
 
 /* UART section */
-#define BOARD_UART_NAME                        "uart2"
-#define BOARD_UART_RX_BUFFER_SIZE              BSP_UART2_RX_BUFSIZE
+#define BOARD_UART_NAME                        "uart3"
+#define BOARD_UART_RX_BUFFER_SIZE              BSP_UART3_RX_BUFSIZE
+
+/* ADC section */
+#define BOARD_ADC_NAME                        BOARD_APP_ADC16_NAME
+#define BOARD_ADC_CHANNEL                     BOARD_APP_ADC16_CH_1
 
 #define IRQn_PendSV IRQn_DEBUG0
 

bsp/hpmicro/hpm5301evklite/rtconfig.h

@@ -61,7 +61,7 @@
 
 /* end of rt_strnlen options */
 /* end of klibc options */
-#define RT_NAME_MAX 8
+#define RT_NAME_MAX 16
 #define RT_CPUS_NR 1
 #define RT_ALIGN_SIZE 8
 #define RT_THREAD_PRIORITY_32
@@ -76,6 +76,7 @@
 #define RT_USING_TIMER_SOFT
 #define RT_TIMER_THREAD_PRIO 4
 #define RT_TIMER_THREAD_STACK_SIZE 1024
+#define RT_USING_CPU_USAGE_TRACER
 
 /* kservice options */
 
@@ -104,6 +105,8 @@
 #define RT_VER_NUM 0x50201
 #define RT_BACKTRACE_LEVEL_MAX_NR 32
 /* end of RT-Thread Kernel */
+#define ARCH_RISCV
+#define ARCH_RISCV32
 
 /* RT-Thread Components */
 
@@ -300,6 +303,20 @@
 /* NXP HAL & SDK Drivers */
 
 /* end of NXP HAL & SDK Drivers */
+
+/* NUVOTON Drivers */
+
+/* end of NUVOTON Drivers */
+
+/* GD32 Drivers */
+
+/* end of GD32 Drivers */
+
+/* HPMicro SDK */
+
+#define PKG_USING_HPM_SDK
+#define PKG_USING_HPM_SDK_LATEST_VERSION
+/* end of HPMicro SDK */
 /* end of HAL & SDK Drivers */
 
 /* sensors drivers */
@@ -379,18 +396,21 @@
 
 /* end of Arduino libraries */
 /* end of RT-Thread online packages */
+#define SOC_HPM5300_SERIES
 
 /* Hardware Drivers Config */
 
-#define SOC_HPM5000
+#define SOC_HPM5300
 
 /* On-chip Peripheral Drivers */
 
 #define BSP_USING_GPIO
+#define BSP_GPIO_IRQ_PRIORITY 1
 #define BSP_USING_UART
 #define BSP_USING_UART0
 #define BSP_UART0_RX_BUFSIZE 128
 #define BSP_UART0_TX_BUFSIZE 0
+#define BSP_UART0_IRQ_PRIORITY 1
 /* end of On-chip Peripheral Drivers */
 /* end of Hardware Drivers Config */
 

bsp/hpmicro/hpm5301evklite/rtconfig.py

@@ -1,8 +1,41 @@
-# Copyright 2021-2023 HPMicro
+# Copyright 2021-2025 HPMicro
 # SPDX-License-Identifier: BSD-3-Clause
 
 import os
 import sys
+import rtconfig
+
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+def bsp_pkg_check():
+    import subprocess
+    
+    need_update = True
+    for p in os.listdir("packages"):
+        if p.startswith("hpm_sdk-"):
+            need_update = False
+            break
+    if need_update:
+        print("\n===============================================================================")
+        print("Dependency packages missing, please running 'pkgs --update'...")
+        print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
+        print("===============================================================================")
+        exit(1)
+
+RegisterPreBuildingAction(bsp_pkg_check)
+
 
 # toolchains options
 ARCH='risc-v'
@@ -80,27 +113,27 @@ if PLATFORM == 'gcc':
         AFLAGS += ' -gdwarf-2'
         CFLAGS += ' -O0'
         LFLAGS += ' -O0'
-        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+        LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld'
     elif BUILD == 'ram_release':
         CFLAGS += ' -O2'
         LFLAGS += ' -O2'
-        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+        LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld'
     elif BUILD == 'flash_debug':
         CFLAGS += ' -gdwarf-2'
         AFLAGS += ' -gdwarf-2'
         CFLAGS += ' -O0'
         LFLAGS += ' -O0'
         CFLAGS += ' -DFLASH_XIP=1'
-        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+        LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
     elif BUILD == 'flash_release':
         CFLAGS += ' -O2'
         LFLAGS += ' -O2'
         CFLAGS += ' -DFLASH_XIP=1'
-        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+        LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
     else:
         CFLAGS += ' -O2'
         LFLAGS += ' -O2'
-        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+        LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
     LFLAGS += ' -T ' + LINKER_FILE
 
     POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c

@@ -4,125 +4,132 @@
  *
  */
 
-#include "hpm_common.h"
-#include "hpm_soc.h"
-#include "hpm_l1c_drv.h"
-#include <rtthread.h>
-
-void system_init(void);
-
-extern int entry(void);
-
-extern void __libc_init_array(void);
-extern void __libc_fini_array(void);
-
-void system_init(void)
-{
-    disable_global_irq(CSR_MSTATUS_MIE_MASK);
-    disable_irq_from_intc();
-    enable_irq_from_intc();
-    enable_global_irq(CSR_MSTATUS_MIE_MASK);
-#ifndef CONFIG_NOT_ENABLE_ICACHE
-    l1c_ic_enable();
-#endif
-#ifndef CONFIG_NOT_ENABLE_DCACHE
-    l1c_dc_enable();
-#endif
-}
-
-__attribute__((weak)) void c_startup(void)
-{
-    uint32_t i, size;
-#ifdef FLASH_XIP
-    extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
-    size = __vector_ram_end__ - __vector_ram_start__;
-    for (i = 0; i < size; i++) {
-        *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
-    }
-#endif
-
-    extern uint8_t __etext[];
-    extern uint8_t __bss_start__[], __bss_end__[];
-    extern uint8_t __tbss_start__[], __tbss_end__[];
-    extern uint8_t __tdata_start__[], __tdata_end__[];
-    extern uint8_t __data_start__[], __data_end__[];
-    extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
-    extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
-    extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
-
-    /* tbss section */
-    size = __tbss_end__ - __tbss_start__;
-    for (i = 0; i < size; i++) {
-        *(__tbss_start__ + i) = 0;
-    }
-
-    /* bss section */
-    size = __bss_end__ - __bss_start__;
-    for (i = 0; i < size; i++) {
-        *(__bss_start__ + i) = 0;
-    }
-
-    /* noncacheable bss section */
-    size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
-    for (i = 0; i < size; i++) {
-        *(__noncacheable_bss_start__ + i) = 0;
-    }
-
-    /* tdata section LMA: etext */
-    size = __tdata_end__ - __tdata_start__;
-    for (i = 0; i < size; i++) {
-        *(__tdata_start__ + i) = *(__etext + i);
-    }
-
-    /* data section LMA: etext */
-    size = __data_end__ - __data_start__;
-    for (i = 0; i < size; i++) {
-        *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i);
-    }
-
-    /* ramfunc section LMA: etext + data length */
-    size = __ramfunc_end__ - __ramfunc_start__;
-    for (i = 0; i < size; i++) {
-        *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i);
-    }
-
-    /* noncacheable init section LMA: etext + data length + ramfunc length */
-    size = __noncacheable_init_end__ - __noncacheable_init_start__;
-    for (i = 0; i < size; i++) {
-        *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
-    }
-}
-
-__attribute__((weak)) int main(void)
-{
-    while(1);
-}
-
-void reset_handler(void)
-{
-    /**
-     * Disable preemptive interrupt
-     */
-    HPM_PLIC->FEATURE = 0;
-    /*
-     * Initialize LMA/VMA sections.
-     * Relocation for any sections that need to be copied from LMA to VMA.
-     */
-    c_startup();
-
-    /* Call platform specific hardware initialization */
-    system_init();
-
-    /* Do global constructors */
-    __libc_init_array();
-
-
-
-    /* Entry function */
-    entry();
-}
-
-
-__attribute__((weak)) void _init()
-{
-}
+ #include "hpm_common.h"
+ #include "hpm_soc.h"
+ #include "hpm_l1c_drv.h"
+ #include <rtthread.h>
+ 
+ void system_init(void);
+ 
+ extern int entry(void);
+ 
+ extern void __libc_init_array(void);
+ extern void __libc_fini_array(void);
+ 
+ void system_init(void)
+ {
+     disable_global_irq(CSR_MSTATUS_MIE_MASK);
+     disable_irq_from_intc();
+     enable_irq_from_intc();
+     enable_global_irq(CSR_MSTATUS_MIE_MASK);
+ #ifndef CONFIG_NOT_ENABLE_ICACHE
+     l1c_ic_enable();
+ #endif
+ #ifndef CONFIG_NOT_ENABLE_DCACHE
+     l1c_dc_enable();
+ #endif
+ }
+ 
+ __attribute__((weak)) void c_startup(void)
+ {
+ #ifndef __SES_RISCV
+     uint32_t i, size;
+ #ifdef FLASH_XIP
+     extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
+     size = __vector_ram_end__ - __vector_ram_start__;
+     for (i = 0; i < size; i++) {
+         *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
+     }
+ #endif
+ 
+     extern uint8_t __etext[];
+     extern uint8_t __bss_start__[], __bss_end__[];
+     extern uint8_t __tbss_start__[], __tbss_end__[];
+     extern uint8_t __tdata_start__[], __tdata_end__[];
+     extern uint8_t __fast_load_addr__[];
+     extern uint8_t __noncacheable_init_load_addr__[];
+     extern uint8_t __data_load_addr__[];
+     extern uint8_t __tdata_load_addr__[];
+     extern uint8_t __data_start__[], __data_end__[];
+     extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
+     extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
+     extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
+ 
+     /* tbss section */
+     size = __tbss_end__ - __tbss_start__;
+     for (i = 0; i < size; i++) {
+         *(__tbss_start__ + i) = 0;
+     }
+ 
+     /* bss section */
+     size = __bss_end__ - __bss_start__;
+     for (i = 0; i < size; i++) {
+         *(__bss_start__ + i) = 0;
+     }
+ 
+     /* noncacheable bss section */
+     size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
+     for (i = 0; i < size; i++) {
+         *(__noncacheable_bss_start__ + i) = 0;
+     }
+ 
+     /* tdata section LMA: etext */
+     size = __tdata_end__ - __tdata_start__;
+     for (i = 0; i < size; i++) {
+         *(__tdata_start__ + i) = *(__tdata_load_addr__ + i);
+     }
+ 
+     /* data section LMA: etext */
+     size = __data_end__ - __data_start__;
+     for (i = 0; i < size; i++) {
+         *(__data_start__ + i) = *(__data_load_addr__ + i);
+     }
+ 
+     /* ramfunc section LMA: etext + data length */
+     size = __ramfunc_end__ - __ramfunc_start__;
+     for (i = 0; i < size; i++) {
+         *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i);
+     }
+ 
+     /* noncacheable init section LMA: etext + data length + ramfunc length */
+     size = __noncacheable_init_end__ - __noncacheable_init_start__;
+     for (i = 0; i < size; i++) {
+         *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i);
+     }
+ #endif
+ }
+ 
+ __attribute__((weak)) int main(void)
+ {
+     while(1);
+ }
+ 
+ void reset_handler(void)
+ {
+     /**
+      * Disable preemptive interrupt
+      */
+     HPM_PLIC->FEATURE = 0;
+     /*
+      * Initialize LMA/VMA sections.
+      * Relocation for any sections that need to be copied from LMA to VMA.
+      */
+     c_startup();
+ 
+     /* Call platform specific hardware initialization */
+     system_init();
+ 
+ #ifndef __SES_RISCV
+     /* Do global constructors */
+     __libc_init_array();
+ #endif
+ 
+     /* Entry function */
+     entry();
+ }
+ 
+ 
+ __attribute__((weak)) void _init(void)
+ {
+ }
+ 

bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/port_gcc.S

@@ -5,7 +5,8 @@
  *
  */
 #include "cpuport.h"
-
+    .section .text.entry, "ax"
+    .align  2
     .globl rt_hw_do_after_save_above
     .type rt_hw_do_after_save_above,@function
 rt_hw_do_after_save_above:

bsp/hpmicro/hpm5e00evk/.config

@@ -0,0 +1,1434 @@
+
+#
+# RT-Thread Kernel
+#
+
+#
+# klibc options
+#
+
+#
+# rt_vsnprintf options
+#
+# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set
+# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set
+# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set
+# end of rt_vsnprintf options
+
+#
+# rt_vsscanf options
+#
+# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set
+# end of rt_vsscanf options
+
+#
+# rt_memset options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set
+# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set
+# end of rt_memset options
+
+#
+# rt_memcpy options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set
+# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set
+# end of rt_memcpy options
+
+#
+# rt_memmove options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set
+# end of rt_memmove options
+
+#
+# rt_memcmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set
+# end of rt_memcmp options
+
+#
+# rt_strstr options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set
+# end of rt_strstr options
+
+#
+# rt_strcasecmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set
+# end of rt_strcasecmp options
+
+#
+# rt_strncpy options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set
+# end of rt_strncpy options
+
+#
+# rt_strcpy options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set
+# end of rt_strcpy options
+
+#
+# rt_strncmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set
+# end of rt_strncmp options
+
+#
+# rt_strcmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set
+# end of rt_strcmp options
+
+#
+# rt_strlen options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set
+# end of rt_strlen options
+
+#
+# rt_strnlen options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set
+# end of rt_strnlen options
+# end of klibc options
+
+CONFIG_RT_NAME_MAX=16
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_NANO is not set
+# CONFIG_RT_USING_AMP is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_CPUS_NR=1
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=1024
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024
+# CONFIG_RT_USING_TIMER_ALL_SOFT is not set
+CONFIG_RT_USING_CPU_USAGE_TRACER=y
+
+#
+# kservice options
+#
+# CONFIG_RT_USING_TINY_FFS is not set
+# end of kservice options
+
+# CONFIG_RT_USING_DEBUG is not set
+# CONFIG_RT_USING_CI_ACTION is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
+# CONFIG_RT_USING_SIGNALS is not set
+# end of Inter-Thread communication
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+# end of Memory Management
+
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50201
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
+# end of RT-Thread Kernel
+
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV32=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+CONFIG_RT_USING_LEGACY=y
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+# CONFIG_FINSH_USING_WORD_OPERATION is not set
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+CONFIG_FINSH_USING_OPTION_COMPLETION=y
+
+#
+# DFS: device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+# end of DFS: device virtual file system
+
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_USING_SERIAL_V1 is not set
+CONFIG_RT_USING_SERIAL_V2=y
+# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set
+CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y
+CONFIG_RT_SERIAL_USING_DMA=y
+# CONFIG_RT_USING_SERIAL_BYPASS is not set
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PHY_V2 is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_BLK is not set
+# CONFIG_RT_USING_VIRTIO is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_KTIME is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CHERRYUSB is not set
+# end of Device Drivers
+
+#
+# C/C++ and POSIX layer
+#
+
+#
+# ISO-ANSI C layer
+#
+
+#
+# Timezone and Daylight Saving Time
+#
+# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
+CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
+CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
+CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
+CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
+# end of Timezone and Daylight Saving Time
+# end of ISO-ANSI C layer
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# end of Interprocess Communication (IPC)
+# end of POSIX (Portable Operating System Interface) layer
+
+# CONFIG_RT_USING_CPLUSPLUS is not set
+# end of C/C++ and POSIX layer
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+# end of Network
+
+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+# end of Memory protection
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RESOURCE_ID is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# end of Utilities
+
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Using USB legacy version
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+# end of Using USB legacy version
+
+# CONFIG_RT_USING_FDT is not set
+# end of RT-Thread Components
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+# end of RT-Thread Utestcases
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
+# CONFIG_PKG_USING_ESP_HOSTED is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+# end of Marvell WiFi
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# end of Wiced WiFi
+
+# CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+# end of CYW43012 WiFi
+
+#
+# BL808 WiFi
+#
+# CONFIG_PKG_USING_WLAN_BL808 is not set
+# end of BL808 WiFi
+
+#
+# CYW43439 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43439 is not set
+# end of CYW43439 WiFi
+# end of Wi-Fi
+
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# end of IoT Cloud
+
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_BT_CYW43012 is not set
+# CONFIG_PKG_USING_CYW43XX is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
+# CONFIG_PKG_USING_LHC_MODBUS is not set
+# CONFIG_PKG_USING_QMODBUS is not set
+# CONFIG_PKG_USING_PNET is not set
+# CONFIG_PKG_USING_OPENER is not set
+# CONFIG_PKG_USING_FREEMQTT is not set
+# end of IoT - internet of things
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+# end of security packages
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+# CONFIG_PKG_USING_RYAN_JSON is not set
+# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# end of XML: Extensible Markup Language
+
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+# end of language packages
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+# end of LVGL: powerful and easy-to-use embedded GUI library
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# end of u8g2: a monochrome graphic library
+
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+# end of multimedia packages
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_MCOREDUMP is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_ZDEBUG is not set
+# CONFIG_PKG_USING_RVBACKTRACE is not set
+# CONFIG_PKG_USING_HPATCHLITE is not set
+# CONFIG_PKG_USING_THREAD_METRIC is not set
+# end of tools packages
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# end of enhanced kernel services
+
+# CONFIG_PKG_USING_AUNITY is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# end of acceleration: Assembly language or algorithmic acceleration packages
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_CORE is not set
+# CONFIG_PKG_USING_CMSIS_NN is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# end of Micrium: Micrium software products porting for RT-Thread
+
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FILEX is not set
+# CONFIG_PKG_USING_LEVELX is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RPMSG_LITE is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+# CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_UART_FRAMEWORK is not set
+# CONFIG_PKG_USING_SFDB is not set
+# CONFIG_PKG_USING_RTP is not set
+# CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_RMP is not set
+# CONFIG_PKG_USING_R_RHEALSTONE is not set
+# CONFIG_PKG_USING_HEARTBEAT is not set
+# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
+# end of system packages
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# HAL & SDK Drivers
+#
+
+#
+# STM32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set
+# end of STM32 HAL & SDK Drivers
+
+#
+# Infineon HAL Packages
+#
+# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
+# CONFIG_PKG_USING_INFINEON_CMSIS is not set
+# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
+# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
+# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
+# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
+# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
+# CONFIG_PKG_USING_INFINEON_USBDEV is not set
+# end of Infineon HAL Packages
+
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# end of Kendryte SDK
+
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_MM32 is not set
+
+#
+# WCH HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_CH32V20x_SDK is not set
+# CONFIG_PKG_USING_CH32V307_SDK is not set
+# end of WCH HAL & SDK Drivers
+
+#
+# AT32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set
+# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set
+# end of AT32 HAL & SDK Drivers
+
+#
+# HC32 DDL Drivers
+#
+# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set
+# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set
+# end of HC32 DDL Drivers
+
+#
+# NXP HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set
+# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set
+# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set
+# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set
+# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set
+# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set
+# end of NXP HAL & SDK Drivers
+
+#
+# NUVOTON Drivers
+#
+# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set
+# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set
+# end of NUVOTON Drivers
+
+#
+# GD32 Drivers
+#
+# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set
+# end of GD32 Drivers
+
+#
+# HPMicro SDK
+#
+CONFIG_PKG_USING_HPM_SDK=y
+CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk"
+# CONFIG_PKG_USING_HPM_SDK_V110 is not set
+CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y
+CONFIG_PKG_HPM_SDK_VER="latest"
+# end of HPMicro SDK
+# end of HAL & SDK Drivers
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_MAX31855 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90382 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90394 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+# CONFIG_PKG_USING_P3T1755 is not set
+# CONFIG_PKG_USING_QMI8658 is not set
+# CONFIG_PKG_USING_ICM20948 is not set
+# end of sensors drivers
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_CST816X is not set
+# CONFIG_PKG_USING_CST812T is not set
+# end of touch drivers
+
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_AIP650 is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_BT_ECB02C is not set
+# CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_VS1003 is not set
+# CONFIG_PKG_USING_X9555 is not set
+# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
+# CONFIG_PKG_USING_BT_MX01 is not set
+# CONFIG_PKG_USING_RGPOWER is not set
+# CONFIG_PKG_USING_BT_MX02 is not set
+# CONFIG_PKG_USING_GC9A01 is not set
+# CONFIG_PKG_USING_IK485 is not set
+# CONFIG_PKG_USING_SERVO is not set
+# CONFIG_PKG_USING_SEAN_WS2812B is not set
+# CONFIG_PKG_USING_IC74HC165 is not set
+# CONFIG_PKG_USING_IST8310 is not set
+# CONFIG_PKG_USING_ST7789_SPI is not set
+# CONFIG_PKG_USING_SPI_TOOLS is not set
+# end of peripheral libraries and drivers
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+# CONFIG_PKG_USING_R_TINYMAIX is not set
+# CONFIG_PKG_USING_LLMCHAT is not set
+# end of AI packages
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_APID is not set
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_QPID is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_KISSFFT is not set
+# end of Signal Processing and Control Algorithm Packages
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+# end of project laboratory
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# end of samples: kernel and components samples
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# end of entertainment: terminal games and other interesting software packages
+
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_RALARAM is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LIBCRC is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+# CONFIG_PKG_USING_DRMP is not set
+# end of miscellaneous packages
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects and Demos
+#
+# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set
+# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+# end of Projects and Demos
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set
+# end of Sensors
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+# end of Display
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+# CONFIG_PKG_USING_ARDUINO_TICKER is not set
+# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
+# end of Timing
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
+# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set
+# end of Data Processing
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+# end of Communication
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# end of Device Control
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# end of Other
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+# end of Signal IO
+
+#
+# Uncategorized
+#
+# end of Arduino libraries
+# end of RT-Thread online packages
+
+CONFIG_SOC_HPM5E00_SERIES=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_HPM5E00=y
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_GPIO_IRQ_PRIORITY=1
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART0=y
+# CONFIG_BSP_UART0_RX_USING_DMA is not set
+# CONFIG_BSP_UART0_TX_USING_DMA is not set
+CONFIG_BSP_UART0_RX_BUFSIZE=128
+CONFIG_BSP_UART0_TX_BUFSIZE=0
+CONFIG_BSP_UART0_IRQ_PRIORITY=1
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+# CONFIG_BSP_USING_UART4 is not set
+# CONFIG_BSP_USING_UART5 is not set
+# CONFIG_BSP_USING_UART6 is not set
+# CONFIG_BSP_USING_UART7 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_ETH is not set
+# CONFIG_BSP_USING_GPTMR is not set
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_XPI_FLASH is not set
+# CONFIG_BSP_USING_USB is not set
+# CONFIG_BSP_USING_EWDG is not set
+# CONFIG_BSP_USING_PWMV2 is not set
+# CONFIG_BSP_USING_MCAN is not set
+# CONFIG_BSP_USING_ADC is not set
+# end of On-chip Peripheral Drivers
+# end of Hardware Drivers Config

bsp/hpmicro/hpm5e00evk/.project

@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+  <name>blink_led</name>
+  <comment />
+  <projects>
+    </projects>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments>
+            </arguments>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments>
+            </arguments>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.rt-thread.studio.rttnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+</projectDescription>

bsp/hpmicro/hpm5e00evk/.settings/org.eclipse.core.runtime.prefs

@@ -0,0 +1,3 @@
+content-types/enabled=true
+content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
+eclipse.preferences.version=1

bsp/hpmicro/hpm5e00evk/.settings/projcfg.ini

@@ -0,0 +1,20 @@
+#RT-Thread Studio Project Configuration
+# Fri Apr 25 13:53:29 2025
+cfg_version=v3.0
+
+board_name=
+bsp_version=
+bsp_path=
+chip_name=
+project_base_rtt_bsp=true
+is_use_scons_build=true
+hardware_adapter=
+selected_rtt_version=latest
+board_base_nano_proj=false
+is_base_example_project=false
+example_name=
+project_type=rt-thread
+os_branch=master
+os_version=latest
+project_name=blink_led
+output_project_path=D:\oss\rt-thread\bsp\hpmicro\hpm6e00evk

bsp/hpmicro/hpm5e00evk/Kconfig

@@ -0,0 +1,12 @@
+mainmenu "RT-Thread Configuration"
+
+BSP_DIR := .
+
+RTT_DIR := ../../..
+
+PKGS_DIR := packages
+
+source "$(RTT_DIR)/Kconfig"
+osource "$PKGS_DIR/Kconfig"
+rsource "../libraries/Kconfig"
+rsource "board/Kconfig"

bsp/hpmicro/hpm5e00evk/README.md

@@ -0,0 +1,114 @@
+# HPMicro HPM5E00EVK BSP(Board Support Package) Introduction
+
+[中文页](README_zh.md) |
+
+## Introduction
+
+This document provides brief introduction of the BSP (board support package) for the HPM5E00EVK development board.
+
+The document consists of the following parts:
+
+- HPM5E00EVK Board Resources Introduction
+- Quickly Getting Started
+- Refreences
+
+By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
+
+## Board Resources Introduction
+
+HPM5E00EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for Connectivity, motor control，etc.
+![board](figures/board.png)
+
+
+## Peripheral Condition
+
+Each peripheral supporting condition for this BSP is as follows:
+
+
+| **On-board Peripherals** | **Support** | **Note**                              |
+| ------------------------ | ----------- | ------------------------------------- |
+| USB                      | √           |                                       |
+| QSPI Flash               | √           |                                       |
+| Ethernet                 | √           |                                       |
+| GPIO                     | √           |                                       |
+| SPI                      | √           |                                       |
+| I2C                      | √           |                                       |
+| PWM                      | √           |                                       |
+| On-Board Debugger        | √           | ft2232                                |
+
+
+## Execution Instruction
+
+### Quickly Getting Started
+
+The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command
+
+#### Parpare Environment
+- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
+    - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain`
+- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin`
+    - For example: `C:\DevTools\riscv32-gnu-toolchain\bin`
+- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
+  - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro`
+  - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin`
+    - For example: `C:\DevTools\openocd-hpmicro\bin`
+
+#### Configure and Build project
+
+Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can:
+
+- Configure the project via `menuconfig` in `RT-Thread ENV`
+- Build the project using `scons -jN`, `N` equals to the number of CPU cores
+- Clean the project using `scons -c`
+
+#### Hardware Connection
+
+- Switch BOOT pin to 2'b00
+- Connect the `PWR_DEBUG` port to PC via TYPE-C cable
+
+
+#### Dowload / Debug
+
+- Users can download the project via the below command:
+  ```console
+  %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5e00.cfg -f boards\debug_scripts\boards\hpm5e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
+  ```
+
+- Users can debug the project via the below command:
+
+  - Connect debugger via `OpenOCD`:
+
+```console
+%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5e00.cfg -f boards\debug_scripts\boards\hpm5e00evk.cfg
+```
+  - Start Debugger via `GDB`:
+
+```console
+%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
+```
+  - In the `gdb shell`, type the following commands:
+
+```console
+load
+c
+```
+
+### **Running Results**
+
+Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically.
+
+Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed:
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.2.2 build Aug 16 2025 18:18:18
+ 2006 - 2025 Copyright by RT-Thread team
+```
+
+## **References**
+
+- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
+- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
+- [HPM5E00EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm5e00evk)

bsp/hpmicro/hpm5e00evk/README_zh.md

@@ -0,0 +1,113 @@
+# 先楫 HPM5E00EVK BSP(板级支持包)说明
+
+[English](README.md) |
+
+## 简介
+
+本文档为 HPM5E00EVK 的 BSP (板级支持包) 说明。
+
+本文包含如下部分:
+
+- HPM5E00EVK 板级资源介绍
+- 快速上手指南
+- 参考链接
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 板级资源介绍
+
+HPM5E00EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于网络互联和电机控制等应用。
+
+开发板外观如下图所示：
+
+![board](figures/board.png)
+
+
+## 板载外设
+
+本 BSP 目前对外设的支持情况如下:
+
+
+| **板载外设** | **支持情况** | **备注**                              |
+| ------------------------ | ----------- | ------------------------------------- |
+| USB                      | √           |                                       |
+| QSPI Flash               | √           |                                       |
+| 以太网                    | √           |                                       |
+| GPIO                     | √           |                                       |
+| SPI                      | √           |                                       |
+| I2C                      | √           |                                       |
+| PWM                      | √           |                                       |
+| 板载调试器                | √           | ft2232                                |
+
+
+## 使用说明
+
+### 快速开始
+
+本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。
+
+#### 准备环境
+- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
+    - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain`
+- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin`
+- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
+  - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro`
+  - 将 `OPENOCD_HPMICRO`环境变量设置为 `<OPENOCD_HPMICRO_DIR>\bin`，如： `C:\DevTools\openocd-hpmicro\bin`
+
+#### 配置和构建工程
+
+通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以:
+
+- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能
+- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数
+- 通过 `scons -c` 命令清除构建
+
+#### 硬件连接
+
+- 将BOOT 引脚拨到2'b00
+- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑
+
+#### 下载 和 调试
+
+- 通过如下命令完成下载:
+  ```console
+  %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5e00.cfg -f boards\debug_scripts\boards\hpm5e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
+  ```
+
+- 通过如下命令实现调试:
+
+  - 通过 `OpenOCD` 来连接开发板:
+```console
+%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5e00.cfg -f boards\debug_scripts\boards\hpm5e00evk.cfg
+```
+  - 通过 `GDB` 实现调试:
+```console
+%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
+```
+
+  - 在`GDB Shell`中使用如下命令来加载和运行:
+
+```console
+load
+c
+```
+
+### **运行结果**
+
+一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。
+
+配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志：
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.2.2 build Aug 16 2025 18:18:18
+ 2006 - 2025 Copyright by RT-Thread team
+```
+
+## **参考链接**
+
+- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
+- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
+- [HPM5E00EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm5e00evk)

bsp/hpmicro/hpm5e00evk/SConscript

@@ -0,0 +1,17 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+ASFLAGS = ' -I' + cwd
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/hpmicro/hpm5e00evk/SConstruct

@@ -0,0 +1,65 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+AddOption('--run',
+        dest = 'run',
+        type='string',
+        nargs=1,
+        action = 'store',
+        default = "",
+        help = 'Upload or debug application using openocd')
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
+    CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
+
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(os.path.join(SDK_ROOT, 'libraries')):
+    libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries')
+else:
+    libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries')
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+
+GDB = rtconfig.GDB
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+
+
+
+# includes rtt drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers',  'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/hpmicro/hpm5e00evk/applications/SConscript

@@ -0,0 +1,14 @@
+import rtconfig
+
+from building import *
+
+cwd = GetCurrentDir()
+
+src = Glob('*.c')
+
+CPPDEFINES=[]
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
+
+Return('group')

bsp/hpmicro/hpm5e00evk/applications/main.c

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2021-2024 HPMicro
+ *
+ * Change Logs:
+ * Date         Author          Notes
+ * 2021-08-13   Fan YANG        first version
+ *
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "rtt_board.h"
+
+void thread_entry(void *arg);
+
+int main(void)
+{
+    app_init_led_pins();
+
+    static uint32_t led_thread_arg = 0;
+    rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10);
+    rt_thread_startup(led_thread);
+
+    return 0;
+}
+
+void thread_entry(void *arg)
+{
+    while(1){
+        app_led_write(0, APP_LED_ON);
+        rt_thread_mdelay(500);
+        app_led_write(0, APP_LED_OFF);
+        rt_thread_mdelay(500);
+        app_led_write(1, APP_LED_ON);
+        rt_thread_mdelay(500);
+        app_led_write(1, APP_LED_OFF);
+        rt_thread_mdelay(500);
+        app_led_write(2, APP_LED_ON);
+        rt_thread_mdelay(500);
+        app_led_write(2, APP_LED_OFF);
+        rt_thread_mdelay(500);
+    }
+}

bsp/hpmicro/hpm5e00evk/board/Kconfig

@@ -0,0 +1,606 @@
+menu "Hardware Drivers Config"
+
+config SOC_HPM5E00
+    bool
+    select SOC_HPM5E00_SERIES
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+config BSP_USING_ENET_PHY_RTL8211
+    bool
+    default n
+
+if BSP_USING_ETH
+    config LWIP_SUPPORT_CUSTOM_PBUF
+    int
+    default 1
+endif
+
+menu "On-chip Peripheral Drivers"
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN if BSP_USING_GPIO
+        default n
+        if BSP_USING_GPIO
+            config BSP_GPIO_IRQ_PRIORITY
+            int "GPIO Interrupt Priority"
+            range 1 7
+            default 1
+        endif
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            menuconfig BSP_USING_UART0
+                bool "Enable UART0 (Debugger)"
+                default y
+                if BSP_USING_UART0
+                    config BSP_UART0_RX_USING_DMA
+                        bool "Enable UART0 RX DMA"
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART0_TX_USING_DMA
+                        bool "Enable UART0 TX DMA"
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART0_RX_BUFSIZE
+                        int "Set UART0 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 128
+                    config BSP_UART0_TX_BUFSIZE
+                        int "Set UART0 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                    config BSP_UART0_IRQ_PRIORITY
+                        int "UART0 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            menuconfig BSP_USING_UART1
+                bool "Enable UART1"
+                default n
+                if BSP_USING_UART1
+                    config BSP_UART1_RX_USING_DMA
+                        bool "Enable UART1 RX DMA"
+                        depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART1_TX_USING_DMA
+                        bool "Enable UART1 TX DMA"
+                        depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART1_RX_BUFSIZE
+                        int "Set UART1 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 1024
+                    config BSP_UART1_TX_BUFSIZE
+                        int "Set UART1 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                    config BSP_UART1_IRQ_PRIORITY
+                        int "UART1 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            menuconfig BSP_USING_UART2
+                bool "Enable UART2"
+                default n
+                if BSP_USING_UART2
+                    config BSP_UART2_RX_USING_DMA
+                        bool "Enable UART2 RX DMA"
+                        depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART2_TX_USING_DMA
+                        bool "Enable UART2 TX DMA"
+                        depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART2_RX_BUFSIZE
+                        int "Set UART2 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 1024
+                    config BSP_UART2_TX_BUFSIZE
+                        int "Set UART2 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                    config BSP_UART2_IRQ_PRIORITY
+                        int "UART2 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            menuconfig BSP_USING_UART3
+                bool "Enable UART3"
+                default n
+                if BSP_USING_UART3
+                    config BSP_UART3_RX_USING_DMA
+                        bool "Enable UART3 RX DMA"
+                        depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART3_TX_USING_DMA
+                        bool "Enable UART3 TX DMA"
+                        depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART3_RX_BUFSIZE
+                        int "Set UART3 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 1024
+                    config BSP_UART3_TX_BUFSIZE
+                        int "Set UART3 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                    config BSP_UART3_IRQ_PRIORITY
+                        int "UART3 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            menuconfig BSP_USING_UART4
+                bool "Enable UART4"
+                default n
+                if BSP_USING_UART4
+                    config BSP_UART4_RX_USING_DMA
+                        bool "Enable UART4 RX DMA"
+                        depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART4_TX_USING_DMA
+                        bool "Enable UART4 TX DMA"
+                        depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART4_RX_BUFSIZE
+                        int "Set UART4 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 1024
+                    config BSP_UART4_TX_BUFSIZE
+                        int "Set UART4 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                    config BSP_UART4_IRQ_PRIORITY
+                        int "UART4 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            menuconfig BSP_USING_UART5
+                bool "Enable UART5"
+                default n
+                if BSP_USING_UART5
+                    config BSP_UART5_RX_USING_DMA
+                        bool "Enable UART5 RX DMA"
+                        depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART5_TX_USING_DMA
+                        bool "Enable UART5 TX DMA"
+                        depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART5_RX_BUFSIZE
+                        int "Set UART5 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 1024
+                    config BSP_UART5_TX_BUFSIZE
+                        int "Set UART5 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                    config BSP_UART5_IRQ_PRIORITY
+                        int "UART5 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            menuconfig BSP_USING_UART6
+                bool "Enable UART6"
+                default n
+                if BSP_USING_UART6
+                    config BSP_UART6_RX_USING_DMA
+                        bool "Enable UART6 RX DMA"
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART6_TX_USING_DMA
+                        bool "Enable UART6 TX DMA"
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART6_RX_BUFSIZE
+                        int "Set UART6 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 1024
+                    config BSP_UART6_TX_BUFSIZE
+                        int "Set UART6 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                    config BSP_UART6_IRQ_PRIORITY
+                        int "UART6 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            menuconfig BSP_USING_UART7
+                bool "Enable UART7"
+                default n
+                if BSP_USING_UART7
+                    config BSP_UART7_RX_USING_DMA
+                        bool "Enable UART7 RX DMA"
+                        depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART7_TX_USING_DMA
+                        bool "Enable UART7 TX DMA"
+                        depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA
+                        default n
+                    config BSP_UART7_RX_BUFSIZE
+                        int "Set UART7 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 1024
+                    config BSP_UART7_TX_BUFSIZE
+                        int "Set UART7 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                    config BSP_UART7_IRQ_PRIORITY
+                        int "UART7 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+        endif
+
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI"
+        default n
+        select RT_USING_SPI if BSP_USING_SPI
+        if BSP_USING_SPI
+            config BSP_USING_SPI0
+                bool "Enable SPI0"
+                default n
+                if BSP_USING_SPI0
+                    config BSP_SPI0_USING_DMA
+                        bool "Enable SPI0 DMA"
+                        default n
+                    config BSP_SPI0_IRQ_PRIORITY
+                        int "SPI0 Interrupt Priority"
+                        range 1 7
+                        default 1
+                    choice
+                        prompt "Select SPI0 CS TYPE"
+                        default BSP_SPI0_USING_SOFT_CS
+                        config BSP_SPI0_USING_SOFT_CS
+                            bool "Enable SPI0 software cs"
+                        config BSP_SPI0_USING_HARD_CS
+                            bool "Enable SPI0 hardware cs"
+                    endchoice
+                    choice
+                        prompt "Select SPI0 IO mode"
+                        default BSP_SPI0_USING_SINGLE_IO
+                        config BSP_SPI0_USING_SINGLE_IO
+                            bool "Enable SPI0 single IO mode"
+                        config BSP_SPI0_USING_DUAL_IO
+                            bool "Enable SPI0 dual IO mode"
+                        config BSP_SPI0_USING_QUAD_IO
+                            bool "Enable SPI0 quad IO mode"
+                    endchoice
+                endif
+            config BSP_USING_SPI1
+                bool "Enable SPI1"
+                default n
+                if BSP_USING_SPI1
+                    config BSP_SPI1_USING_DMA
+                        bool "Enable SPI1 DMA"
+                        default n
+                    config BSP_SPI1_IRQ_PRIORITY
+                        int "SPI1 Interrupt Priority"
+                        range 1 7
+                        default 1
+                    choice
+                        prompt "Select SPI1 CS TYPE"
+                        default BSP_SPI1_USING_SOFT_CS
+                        config BSP_SPI1_USING_SOFT_CS
+                            bool "Enable SPI1 software cs"
+                        config BSP_SPI1_USING_HARD_CS
+                            bool "Enable SPI1 hardware cs"
+                    endchoice
+                    choice
+                        prompt "Select SPI1 IO mode"
+                        default BSP_SPI1_USING_SINGLE_IO
+                        config BSP_SPI1_USING_SINGLE_IO
+                            bool "Enable SPI1 single IO mode"
+                        config BSP_SPI1_USING_DUAL_IO
+                            bool "Enable SPI1 dual IO mode"
+                        config BSP_SPI1_USING_QUAD_IO
+                            bool "Enable SPI1 quad IO mode"
+                    endchoice
+                endif
+            config BSP_USING_SPI2
+                bool "Enable SPI2"
+                default n
+                if BSP_USING_SPI2
+                    config BSP_SPI2_USING_DMA
+                        bool "Enable SPI2 DMA"
+                        default n
+                    config BSP_SPI2_IRQ_PRIORITY
+                        int "SPI2 Interrupt Priority"
+                        range 1 7
+                        default 1
+                    choice
+                        prompt "Select SPI2 CS TYPE"
+                        default BSP_SPI2_USING_SOFT_CS
+                        config BSP_SPI2_USING_SOFT_CS
+                            bool "Enable SPI2 software cs"
+                        config BSP_SPI2_USING_HARD_CS
+                            bool "Enable SPI2 hardware cs"
+                    endchoice
+                    choice
+                        prompt "Select SPI2 IO mode"
+                        default BSP_SPI2_USING_SINGLE_IO
+                        config BSP_SPI2_USING_SINGLE_IO
+                            bool "Enable SPI2 single IO mode"
+                        config BSP_SPI2_USING_DUAL_IO
+                            bool "Enable SPI2 dual IO mode"
+                        config BSP_SPI2_USING_QUAD_IO
+                            bool "Enable SPI2 quad IO mode"
+                    endchoice
+                endif
+            config BSP_USING_SPI3
+                bool "Enable SPI3"
+                default n
+                if BSP_USING_SPI3
+                    config BSP_SPI3_USING_DMA
+                        bool "Enable SPI3 DMA"
+                        default n
+                    config BSP_SPI3_IRQ_PRIORITY
+                        int "SPI3 Interrupt Priority"
+                        range 1 7
+                        default 1
+                    choice
+                        prompt "Select SPI3 CS TYPE"
+                        default BSP_SPI3_USING_SOFT_CS
+                        config BSP_SPI3_USING_SOFT_CS
+                            bool "Enable SPI3 software cs"
+                        config BSP_SPI3_USING_HARD_CS
+                            bool "Enable SPI3 hardware cs"
+                    endchoice
+                    choice
+                        prompt "Select SPI3 IO mode"
+                        default BSP_SPI3_USING_SINGLE_IO
+                        config BSP_SPI3_USING_SINGLE_IO
+                            bool "Enable SPI3 single IO mode"
+                        config BSP_SPI3_USING_DUAL_IO
+                            bool "Enable SPI3 dual IO mode"
+                        config BSP_SPI3_USING_QUAD_IO
+                            bool "Enable SPI3 quad IO mode"
+                    endchoice
+                endif
+        endif
+
+    menuconfig BSP_USING_ETH
+       bool "Enable Ethernet"
+       default n
+
+       select RT_USING_ETH if BSP_USING_ETH
+       select RT_USING_PHY if BSP_USING_ETH
+
+       if BSP_USING_ETH
+           choice
+               prompt "ETH"
+               default BSP_USING_ETH0
+
+               config BSP_USING_ETH0
+               bool "Enable ETH0"
+               select BSP_USING_ENET_PHY_RTL8211
+           endchoice
+       endif
+
+    menuconfig BSP_USING_GPTMR
+        bool "Enable GPTMR"
+        default n
+        select RT_USING_HWTIMER if BSP_USING_GPTMR
+        if BSP_USING_GPTMR
+            config BSP_USING_GPTMR0
+                bool "Enable GPTMR0"
+                default n
+                if BSP_USING_GPTMR0
+                    config BSP_GPTMR0_IRQ_PRIORITY
+                    int "GPTMR0 Interrupt Priority"
+                    range 1 7
+                    default 1
+                endif
+            config BSP_USING_GPTMR1
+                bool "Enable GPTMR1"
+                default n
+                if BSP_USING_GPTMR1
+                    config BSP_GPTMR1_IRQ_PRIORITY
+                    int "GPTMR1 Interrupt Priority"
+                    range 1 7
+                    default 1
+                endif
+            config BSP_USING_GPTMR2
+                bool "Enable GPTMR2"
+                default n
+                if BSP_USING_GPTMR2
+                    config BSP_GPTMR2_IRQ_PRIORITY
+                    int "GPTMR2 Interrupt Priority"
+                    range 1 7
+                    default 1
+                endif
+            config BSP_USING_GPTMR3
+                bool "Enable GPTMR3"
+                default n
+                if BSP_USING_GPTMR3
+                    config BSP_GPTMR3_IRQ_PRIORITY
+                    int "GPTMR3 Interrupt Priority"
+                    range 1 7
+                    default 1
+                endif
+        endif
+
+    menuconfig BSP_USING_I2C
+        bool "Enable I2C"
+        default n
+        select RT_USING_I2C if BSP_USING_I2C
+        if BSP_USING_I2C
+            config BSP_USING_I2C0
+                bool "Enable I2C0"
+                default y
+                if BSP_USING_I2C0
+                    config BSP_I2C0_USING_DMA
+                        bool "Enable I2C0 DMA"
+                        default n
+                    config BSP_I2C0_IRQ_PRIORITY
+                        int "I2C0 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            config BSP_USING_I2C1
+                bool "Enable I2C1"
+                default n
+                if BSP_USING_I2C1
+                    config BSP_I2C1_USING_DMA
+                        bool "Enable I2C1 DMA"
+                        default n
+                    config BSP_I2C1_IRQ_PRIORITY
+                        int "I2C1 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            config BSP_USING_I2C2
+                bool "Enable I2C2"
+                default n
+                if BSP_USING_I2C2
+                    config BSP_I2C2_USING_DMA
+                        bool "Enable I2C2 DMA"
+                        default n
+                    config BSP_I2C2_IRQ_PRIORITY
+                        int "I2C2 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            config BSP_USING_I2C3
+                bool "Enable I2C3"
+                default n
+                if BSP_USING_I2C3
+                    config BSP_I2C3_USING_DMA
+                        bool "Enable I2C3 DMA"
+                        default n
+                    config BSP_I2C3_IRQ_PRIORITY
+                        int "I2C3 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+        endif
+
+
+    menuconfig BSP_USING_XPI_FLASH
+        bool "Enable XPI FLASH"
+        default n
+        select RT_USING_FAL if BSP_USING_XPI_FLASH
+
+
+    menuconfig BSP_USING_USB
+       bool "Enable USB"
+       default n
+       if BSP_USING_USB
+            config BSP_USING_USB_DEVICE
+                bool "Enable USB Device"
+                select RT_USING_CACHE
+                default n
+            config BSP_USING_USB_HOST
+                bool "Enable USB Host"
+                select RT_USING_CACHE
+                default n
+       endif
+
+
+    menuconfig BSP_USING_EWDG
+        bool "Enable EWDG"
+        default n
+        select RT_USING_WDT if BSP_USING_EWDG
+        if BSP_USING_EWDG
+            config BSP_USING_EWDG0
+                bool "Enable EWDG0"
+                default n
+            config BSP_USING_EWDG1
+                bool "Enable EWDG1"
+                default n
+        endif
+
+    menuconfig BSP_USING_PWMV2
+        bool "Enable PWM"
+        default n
+        select RT_USING_PWM if BSP_USING_PWMV2
+
+    menuconfig BSP_USING_MCAN
+        bool "Enable MCAN"
+        default n
+        select RT_USING_CAN if BSP_USING_MCAN
+        if BSP_USING_MCAN
+            config BSP_USING_MCAN0
+                bool "Enable MCAN0"
+                default n
+                if BSP_USING_MCAN0
+                    config BSP_MCAN0_IRQ_PRIORITY
+                        int "MCAN0 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            config BSP_USING_MCAN1
+                bool "Enable MCAN1"
+                default n
+                if BSP_USING_MCAN1
+                    config BSP_MCAN1_IRQ_PRIORITY
+                        int "MCAN1 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            config BSP_USING_MCAN2
+                bool "Enable MCAN2"
+                default n
+                if BSP_USING_MCAN2
+                    config BSP_MCAN2_IRQ_PRIORITY
+                        int "MCAN2 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+            config BSP_USING_MCAN3
+                bool "Enable MCAN3"
+                default n
+                if BSP_USING_MCAN3
+                    config BSP_MCAN3_IRQ_PRIORITY
+                        int "MCAN3 Interrupt Priority"
+                        range 1 7
+                        default 1
+                endif
+        endif
+
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC if BSP_USING_ADC
+        if BSP_USING_ADC
+            menuconfig BSP_USING_ADC16
+                bool "Enable ADC16"
+                default n
+                if BSP_USING_ADC16
+                    config BSP_USING_ADC0
+                        bool "Enable ADC0"
+                        default n
+                    config BSP_USING_ADC1
+                        bool "Enable ADC1"
+                        default n
+                endif
+         endif
+
+endmenu
+
+
+
+
+endmenu
+

bsp/hpmicro/hpm5e00evk/board/SConscript

@@ -0,0 +1,18 @@
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers
+src = Split("""
+    board.c
+    rtt_board.c
+    pinmux.c
+    fal_flash_port.c
+""")
+
+CPPPATH = [cwd]
+CPPDEFINES=['D45', 'HPM5E31']
+
+group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/hpmicro/hpm5e00evk/board/board.c

@@ -0,0 +1,716 @@
+/*
+ * Copyright (c) 2023-2025 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ *
+ */
+
+#include "board.h"
+#include "hpm_uart_drv.h"
+#include "hpm_gptmr_drv.h"
+#include "hpm_i2c_drv.h"
+#include "hpm_gpio_drv.h"
+#include "pinmux.h"
+#include "hpm_pmp_drv.h"
+#include "hpm_clock_drv.h"
+/* #include "hpm_sysctl_drv.h" */
+#include "hpm_pllctlv2_drv.h"
+#include "hpm_enet_drv.h"
+#include "hpm_usb_drv.h"
+#include "hpm_pcfg_drv.h"
+
+/**
+ * @brief FLASH configuration option definitions:
+ * option[0]:
+ *    [31:16] 0xfcf9 - FLASH configuration option tag
+ *    [15:4]  0 - Reserved
+ *    [3:0]   option words (exclude option[0])
+ * option[1]:
+ *    [31:28] Flash probe type
+ *      0 - SFDP SDR / 1 - SFDP DDR
+ *      2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+ *      4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+ *      6 - OctaBus DDR (SPI -> OPI DDR)
+ *      8 - Xccela DDR (SPI -> OPI DDR)
+ *      10 - EcoXiP DDR (SPI -> OPI DDR)
+ *    [27:24] Command Pads after Power-on Reset
+ *      0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+ *    [23:20] Command Pads after Configuring FLASH
+ *      0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+ *    [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+ *      0 - Not needed
+ *      1 - QE bit is at bit 6 in Status Register 1
+ *      2 - QE bit is at bit1 in Status Register 2
+ *      3 - QE bit is at bit7 in Status Register 2
+ *      4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+ *    [15:8] Dummy cycles
+ *      0 - Auto-probed / detected / default value
+ *      Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+ *    [7:4] Misc.
+ *      0 - Not used
+ *      1 - SPI mode
+ *      2 - Internal loopback
+ *      3 - External DQS
+ *    [3:0] Frequency option
+ *      1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 111MHz / 7 - 133MHz / 8 - 166MHz
+ *
+ * option[2] (Effective only if the bit[3:0] in option[0] > 1)
+ *    [31:20]  Reserved
+ *    [19:16] IO voltage
+ *      0 - 3V / 1 - 1.8V
+ *    [15:12] Pin group
+ *      0 - 1st group / 1 - 2nd group
+ *    [11:8] Connection selection
+ *      0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+ *    [7:0] Drive Strength
+ *      0 - Default value
+ * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
+ *              JESD216)
+ *    [31:16] reserved
+ *    [15:12] Sector Erase Command Option, not required here
+ *    [11:8]  Sector Size Option, not required here
+ *    [7:0] Flash Size Option
+ *      0 - 4MB / 1 - 8MB / 2 - 16MB
+ */
+#if defined(FLASH_XIP) && FLASH_XIP
+__attribute__((section(".nor_cfg_option"), used)) const uint32_t option[4] = { 0xfcf90002, 0x00000005, 0x1000, 0x0 };
+#endif
+
+#if defined(FLASH_UF2) && FLASH_UF2
+ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
+#endif
+
+void board_init_console(void)
+{
+#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
+#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
+    console_config_t cfg;
+
+    /* uart needs to configure pin function before enabling clock, otherwise the level change of
+     * uart rx pin when configuring pin function will cause a wrong data to be received.
+     * And a uart rx dma request will be generated by default uart fifo dma trigger level.
+     */
+    init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE);
+
+    clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0);
+
+    cfg.type = BOARD_CONSOLE_TYPE;
+    cfg.base = (uint32_t) BOARD_CONSOLE_UART_BASE;
+    cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME);
+    cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE;
+
+    if (status_success != console_init(&cfg)) {
+        /* failed to  initialize debug console */
+        while (1) {
+        }
+    }
+#else
+    while (1)
+        ;
+#endif
+#endif
+}
+
+void board_print_clock_freq(void)
+{
+    printf("==============================\n");
+    printf(" %s clock summary\n", BOARD_NAME);
+    printf("==============================\n");
+    printf("cpu0:\t\t %dHz\n", clock_get_frequency(clock_cpu0));
+    printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb0));
+    printf("axif:\t\t %dHz\n", clock_get_frequency(clock_axif));
+    printf("axis:\t\t %dHz\n", clock_get_frequency(clock_axis));
+    printf("axic:\t\t %dHz\n", clock_get_frequency(clock_axic));
+    printf("xpi0:\t\t %dHz\n", clock_get_frequency(clock_xpi0));
+    printf("mchtmr0:\t %dHz\n", clock_get_frequency(clock_mchtmr0));
+    printf("==============================\n");
+}
+
+void board_init_uart(UART_Type *ptr)
+{
+    /* configure uart's pin before opening uart's clock */
+    init_uart_pins(ptr);
+    board_init_uart_clock(ptr);
+}
+
+void board_print_banner(void)
+{
+    const uint8_t banner[] = { "\n\
+----------------------------------------------------------------------\n\
+$$\\   $$\\ $$$$$$$\\  $$\\      $$\\ $$\\\n\
+$$ |  $$ |$$  __$$\\ $$$\\    $$$ |\\__|\n\
+$$ |  $$ |$$ |  $$ |$$$$\\  $$$$ |$$\\  $$$$$$$\\  $$$$$$\\   $$$$$$\\\n\
+$$$$$$$$ |$$$$$$$  |$$\\$$\\$$ $$ |$$ |$$  _____|$$  __$$\\ $$  __$$\\\n\
+$$  __$$ |$$  ____/ $$ \\$$$  $$ |$$ |$$ /      $$ |  \\__|$$ /  $$ |\n\
+$$ |  $$ |$$ |      $$ |\\$  /$$ |$$ |$$ |      $$ |      $$ |  $$ |\n\
+$$ |  $$ |$$ |      $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ |      \\$$$$$$  |\n\
+\\__|  \\__|\\__|      \\__|     \\__|\\__| \\_______|\\__|       \\______/\n\
+----------------------------------------------------------------------\n" };
+#ifdef SDK_VERSION_STRING
+    printf("hpm_sdk: %s\n", SDK_VERSION_STRING);
+#endif
+    printf("%s", banner);
+}
+
+uint8_t board_get_led_gpio_off_level(void)
+{
+    return BOARD_LED_OFF_LEVEL;
+}
+
+void board_ungate_mchtmr_at_lp_mode(void)
+{
+    /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */
+    sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock);
+}
+
+void board_init(void)
+{
+    board_init_clock();
+    board_init_console();
+    board_init_pmp();
+#if BOARD_SHOW_CLOCK
+    board_print_clock_freq();
+#endif
+#if BOARD_SHOW_BANNER
+    board_print_banner();
+#endif
+}
+
+void board_delay_us(uint32_t us)
+{
+    clock_cpu_delay_us(us);
+}
+
+void board_delay_ms(uint32_t ms)
+{
+    clock_cpu_delay_ms(ms);
+}
+
+#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT
+static board_timer_cb timer_cb;
+SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr);
+void board_timer_isr(void)
+{
+    if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
+        gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH));
+        timer_cb();
+    }
+}
+
+void board_timer_create(uint32_t ms, board_timer_cb cb)
+{
+    uint32_t gptmr_freq;
+    gptmr_channel_config_t config;
+
+    timer_cb = cb;
+    gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config);
+
+    clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0);
+    gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME);
+
+    config.reload = gptmr_freq / 1000 * ms;
+    gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false);
+    gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH));
+    intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1);
+
+    gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
+}
+#endif
+
+void board_i2c_bus_clear(I2C_Type *ptr)
+{
+    if (i2c_get_line_scl_status(ptr) == false) {
+        printf("CLK is low, please power cycle the board\n");
+        while (1) {
+        }
+    }
+    if (i2c_get_line_sda_status(ptr) == false) {
+        printf("SDA is low, try to issue I2C bus clear\n");
+    } else {
+        printf("I2C bus is ready\n");
+        return;
+    }
+    i2c_gen_reset_signal(ptr, 9);
+    board_delay_ms(100);
+    printf("I2C bus is cleared\n");
+}
+
+uint32_t board_init_i2c_clock(I2C_Type *ptr)
+{
+    uint32_t freq = 0;
+
+    if (ptr == HPM_I2C0) {
+        clock_add_to_group(clock_i2c0, 0);
+        freq = clock_get_frequency(clock_i2c0);
+    } else if (ptr == HPM_I2C1) {
+        clock_add_to_group(clock_i2c1, 0);
+        freq = clock_get_frequency(clock_i2c1);
+    } else if (ptr == HPM_I2C2) {
+        clock_add_to_group(clock_i2c2, 0);
+        freq = clock_get_frequency(clock_i2c2);
+    } else if (ptr == HPM_I2C3) {
+        clock_add_to_group(clock_i2c3, 0);
+        freq = clock_get_frequency(clock_i2c3);
+    } else {
+        ;
+    }
+
+    return freq;
+}
+
+void board_init_i2c(I2C_Type *ptr)
+{
+    i2c_config_t config;
+    hpm_stat_t stat;
+    uint32_t freq;
+
+    freq = board_init_i2c_clock(ptr);
+    init_i2c_pins(ptr);
+    board_i2c_bus_clear(ptr);
+
+    config.i2c_mode = i2c_mode_normal;
+    config.is_10bit_addressing = false;
+    stat = i2c_init_master(ptr, freq, &config);
+    if (stat != status_success) {
+        printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr);
+        while (1) {
+        }
+    }
+}
+
+uint32_t board_init_spi_clock(SPI_Type *ptr)
+{
+    if (ptr == HPM_SPI1) {
+        clock_add_to_group(clock_spi1, 0);
+        return clock_get_frequency(clock_spi1);
+    } else if (ptr == HPM_SPI3) {
+        clock_add_to_group(clock_spi3, 0);
+        return clock_get_frequency(clock_spi3);
+    } else {
+        ;
+    }
+    return 0;
+}
+
+void board_init_gpio_pins(void)
+{
+    init_gpio_pins();
+
+    /* Key A*/
+    gpio_set_pin_input(BOARD_APP_GPIO_CTRL, BOARD_APP_GPIO_INDEX, BOARD_APP_GPIO_PIN);
+}
+
+void board_init_spi_pins(SPI_Type *ptr)
+{
+    init_spi_pins(ptr);
+}
+
+void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
+{
+    init_spi_pins_with_gpio_as_cs(ptr);
+    gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN),
+                                    GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
+}
+
+void board_write_spi_cs(uint32_t pin, uint8_t state)
+{
+    gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state);
+}
+
+void board_init_led_pins(void)
+{
+    init_led_pins();
+    gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level());
+}
+
+void board_led_toggle(void)
+{
+    gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
+}
+
+void board_led_write(uint8_t state)
+{
+    gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
+}
+
+void board_init_pmp(void)
+{
+    pmp_entry_t pmp_entry[16];
+    extern uint32_t __noncacheable_start__[];
+    extern uint32_t __noncacheable_end__[];
+    volatile uint32_t axi_sram_start = 0x01200000;  /* AXI SRAM start */
+    volatile uint32_t axi_sram_end = 0x01240000;    /* AXI SRAM end */
+    uint32_t start_addr, end_addr, length;
+    uint8_t index = 0;
+    start_addr = (uint32_t) __noncacheable_start__;
+    end_addr = (uint32_t) __noncacheable_end__;
+    if ((start_addr >= axi_sram_start) && (end_addr <= axi_sram_end)) {
+        length = end_addr - start_addr;
+        if (length > 0) {
+            /* Ensure the address and the length are power of 2 aligned */
+            assert((length & (length - 1U)) == 0U);
+            assert((start_addr & (length - 1U)) == 0U);
+            pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
+            pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
+            pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
+            pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
+            index++;
+        }
+        pmp_config(&pmp_entry[0], index);
+    }
+}
+
+void board_init_clock(void)
+{
+    uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
+    if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
+        /* Configure the External OSC ramp-up time: ~9ms */
+        pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32ul * 1000ul * 9u);
+
+        /* select clock setting preset1 */
+        sysctl_clock_set_preset(HPM_SYSCTL, 2);
+    }
+    /* Add Clocks to group 0 */
+    clock_add_to_group(clock_cpu0, 0);
+    clock_add_to_group(clock_mchtmr0, 0);
+    clock_add_to_group(clock_ahb0, 0);
+    clock_add_to_group(clock_axif, 0);
+    clock_add_to_group(clock_axis, 0);
+    clock_add_to_group(clock_axic, 0);
+    clock_add_to_group(clock_rom0, 0);
+    clock_add_to_group(clock_xpi0, 0);
+    clock_add_to_group(clock_lmm0, 0);
+    clock_add_to_group(clock_ram0, 0);
+    clock_add_to_group(clock_hdma, 0);
+    clock_add_to_group(clock_xdma, 0);
+    clock_add_to_group(clock_gpio, 0);
+    clock_add_to_group(clock_ptpc, 0);
+    /* Motor Related */
+    clock_add_to_group(clock_qei0, 0);
+    clock_add_to_group(clock_plb0, 0);
+    clock_add_to_group(clock_qei1, 0);
+    clock_add_to_group(clock_qeo0, 0);
+    clock_add_to_group(clock_qeo1, 0);
+    clock_add_to_group(clock_pwm0, 0);
+    clock_add_to_group(clock_pwm1, 0);
+    clock_add_to_group(clock_emds, 0);
+    /* Connect Group0 to CPU0 */
+    clock_connect_group_to_cpu(0, 0);
+
+    /* Bump up DCDC voltage to 1275mv */
+    pcfg_dcdc_set_voltage(HPM_PCFG, 1275);
+
+    /* Configure PLL0 Post Divider */
+    pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk0, pllctlv2_div_1p0);    /* PLL0CLK0: 480MHz */
+    pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk1, pllctlv2_div_1p2);    /* PLL0CLK1: 400MHz */
+    /* Configure PLL0 Frequency to 480MHz */
+    pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll0, BOARD_CPU_FREQ);
+    /* CPU clock use clk_src_pll0_clk0 */
+    clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1);
+    clock_update_core_clock();
+
+    /* Configure mchtmr to 24MHz */
+    clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
+}
+
+uint32_t board_init_uart_clock(UART_Type *ptr)
+{
+    uint32_t freq = 0U;
+    if (ptr == HPM_UART0) {
+        clock_add_to_group(clock_uart0, 0);
+        freq = clock_get_frequency(clock_uart0);
+    } else if (ptr == HPM_UART4) {
+        clock_add_to_group(clock_uart4, 0);
+        freq = clock_get_frequency(clock_uart4);
+    } else {
+        /* Not supported */
+    }
+    return freq;
+}
+
+void board_init_usb(USB_Type *ptr)
+{
+    if (ptr == HPM_USB0) {
+        init_usb_pins(ptr);
+        clock_add_to_group(clock_usb0, 0);
+
+        usb_hcd_set_power_ctrl_polarity(ptr, true);
+        /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */
+        board_delay_ms(100);
+
+        /* As LQFP100 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */
+        /* usb_phy_using_internal_vbus(ptr); */
+    }
+}
+
+void board_init_adc16_pins(void)
+{
+    init_adc16_pins();
+}
+
+uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus)  /* motor system should be use clk_adc_src_ahb0 */
+{
+    uint32_t freq = 0;
+
+    if (ptr == (void *)HPM_ADC0) {
+        clock_add_to_group(clock_adc0, 0);
+        if (clk_src_bus) {
+            /* Configure the ADC clock from AHB (@200MHz by default)*/
+            clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
+        } else {
+            /* Configure the ADC clock from ANA (@200MHz by default)*/
+            clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
+        }
+        freq = clock_get_frequency(clock_adc0);
+    } else if (ptr == (void *)HPM_ADC1) {
+        clock_add_to_group(clock_adc1, 0);
+        if (clk_src_bus) {
+            /* Configure the ADC clock from AHB (@200MHz by default)*/
+            clock_set_adc_source(clock_adc1, clk_adc_src_ahb0);
+        } else {
+            /* Configure the ADC clock from ANA (@200MHz by default)*/
+            clock_set_adc_source(clock_adc1, clk_adc_src_ana1);
+        }
+        freq = clock_get_frequency(clock_adc1);
+    } else {
+        ;
+    }
+
+    return freq;
+}
+
+void board_init_acmp_pins(void)
+{
+    init_acmp_pins();
+}
+
+void board_init_acmp_clock(ACMP_Type *ptr)
+{
+    (void)ptr;
+    clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1);
+}
+
+void board_init_can(MCAN_Type *ptr)
+{
+    init_can_pins(ptr);
+}
+
+uint32_t board_init_can_clock(MCAN_Type *ptr)
+{
+    uint32_t freq = 0;
+    if (ptr == HPM_MCAN0) {
+        /* Set the CAN0 peripheral clock to 80MHz */
+        clock_add_to_group(clock_can0, 0);
+        clock_set_source_divider(clock_can0, clk_src_pll1_clk0, 10);
+        freq = clock_get_frequency(clock_can0);
+    } else if (ptr == HPM_MCAN1) {
+        /* Set the CAN1 peripheral clock to 80MHz */
+        clock_add_to_group(clock_can1, 0);
+        clock_set_source_divider(clock_can1, clk_src_pll1_clk0, 10);
+        freq = clock_get_frequency(clock_can1);
+    } else if (ptr == HPM_MCAN2) {
+        /* Set the CAN2 peripheral clock to 80MHz */
+        clock_add_to_group(clock_can2, 0);
+        clock_set_source_divider(clock_can2, clk_src_pll1_clk0, 10);
+        freq = clock_get_frequency(clock_can2);
+    } else if (ptr == HPM_MCAN3) {
+        /* Set the CAN3 peripheral clock to 80MHz */
+        clock_add_to_group(clock_can3, 0);
+        clock_set_source_divider(clock_can3, clk_src_pll1_clk0, 10);
+        freq = clock_get_frequency(clock_can3);
+    } else {
+        /* Invalid CAN instance */
+    }
+    return freq;
+}
+
+hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr)
+{
+    /* set clock source */
+    if (ptr == HPM_ENET0) {
+        clock_add_to_group(clock_ptp0, 0);
+        /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet0 ptp function */
+        /* clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); */ /* 100MHz */
+    } else {
+        return status_invalid_argument;
+    }
+
+    return status_success;
+}
+
+hpm_stat_t board_init_enet_pins(ENET_Type *ptr)
+{
+    init_enet_pins(ptr);
+
+    if (ptr == HPM_ENET0) {
+        gpio_set_pin_output_with_initial(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0);
+    }  else {
+        return status_invalid_argument;
+    }
+
+    return status_success;
+}
+
+hpm_stat_t board_reset_enet_phy(ENET_Type *ptr)
+{
+    if (ptr == HPM_ENET0) {
+        gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0);
+        board_delay_ms(1);
+        gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 1);
+    } else {
+        return status_invalid_argument;
+    }
+
+    return status_success;
+}
+
+uint8_t board_get_enet_dma_pbl(ENET_Type *ptr)
+{
+    (void) ptr;
+    return enet_pbl_32;
+}
+
+hpm_stat_t board_enable_enet_irq(ENET_Type *ptr)
+{
+    if (ptr == HPM_ENET0) {
+        intc_m_enable_irq(IRQn_ENET0);
+    } else {
+        return status_invalid_argument;
+    }
+
+    return status_success;
+}
+
+hpm_stat_t board_disable_enet_irq(ENET_Type *ptr)
+{
+    if (ptr == HPM_ENET0) {
+        intc_m_disable_irq(IRQn_ENET0);
+    }  else {
+        return status_invalid_argument;
+    }
+
+    return status_success;
+}
+
+void board_init_enet_pps_pins(ENET_Type *ptr)
+{
+    (void) ptr;
+    init_enet_pps_pins();
+}
+
+hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal)
+{
+    /* Configure Enet clock to output reference clock */
+    if (ptr == HPM_ENET0) {
+        clock_add_to_group(clock_eth0, 0);
+        if (internal) {
+            /* set pll output frequency at 1GHz */
+            if (pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll2, 1000000000UL) == status_success) {
+                /* set pll2_clk1 output frequency at 250MHz from PLL2 divided by 4 (1 + 15 / 5) */
+                pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll2, pllctlv2_clk1, pllctlv2_div_4p0);
+                /* set eth clock frequency at 50MHz for enet0 */
+                /* clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5); */
+            } else {
+                return status_fail;
+            }
+        }
+    } else {
+        return status_invalid_argument;
+    }
+
+    enet_rmii_enable_clock(ptr, internal);  /* defined in hpm_enet_soc_drv.h, not sure */
+
+    return status_success;
+}
+
+hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr)
+{
+    if (ptr == HPM_ENET0) {
+        clock_add_to_group(clock_eth0, BOARD_RUNNING_CORE & 0x1);
+        return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); /* defined in hpm_enet_soc_drv.h, not sure */
+    }
+
+    return status_invalid_argument;
+}
+
+void board_init_owr_pins(OWR_Type *ptr)
+{
+    init_owr_pins(ptr);
+}
+
+void board_init_ethercat(ESC_Type *ptr)
+{
+    (void)ptr;
+
+    clock_add_to_group(clock_esc0, 0);
+
+    init_esc_pins();
+    /* PHY reset pin */
+    gpio_set_pin_output_with_initial(HPM_GPIO0, BOARD_ECAT_PHY0_RESET_GPIO_PORT_INDEX, BOARD_ECAT_PHY0_RESET_PIN_INDEX, 0);
+#if BOARD_ECAT_SUPPORT_PORT1
+    gpio_set_pin_output_with_initial(HPM_GPIO0, BOARD_ECAT_PHY1_RESET_GPIO_PORT_INDEX, BOARD_ECAT_PHY1_RESET_PIN_INDEX, 0);
+#endif
+#if BOARD_ECAT_SUPPORT_PORT2
+    gpio_set_pin_output_with_initial(HPM_GPIO0, BOARD_ECAT_PHY2_RESET_GPIO_PORT_INDEX, BOARD_ECAT_PHY2_RESET_PIN_INDEX, 0);
+#endif
+}
+
+/* switch and led pin for ethercat io test */
+void board_init_switch_led(void)
+{
+    init_esc_in_out_pin();
+
+    gpio_set_pin_input(BOARD_ECAT_IN1_GPIO, BOARD_ECAT_IN1_GPIO_PORT_INDEX, BOARD_ECAT_IN1_GPIO_PIN_INDEX);
+    gpio_set_pin_input(BOARD_ECAT_IN2_GPIO, BOARD_ECAT_IN2_GPIO_PORT_INDEX, BOARD_ECAT_IN2_GPIO_PIN_INDEX);
+
+    gpio_set_pin_output_with_initial(BOARD_ECAT_OUT1_GPIO, BOARD_ECAT_OUT1_GPIO_PORT_INDEX, BOARD_ECAT_OUT1_GPIO_PIN_INDEX, 0);
+    gpio_set_pin_output_with_initial(BOARD_ECAT_OUT2_GPIO, BOARD_ECAT_OUT2_GPIO_PORT_INDEX, BOARD_ECAT_OUT2_GPIO_PIN_INDEX, 0);
+}
+
+
+void board_init_adc_qeiv2_pins(void)
+{
+    init_adc_qeiv2_pins();
+}
+
+void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp)
+{
+    init_gptmr_channel_pin(ptr, channel, as_comp);
+}
+
+void board_init_owr_clock(OWR_Type *ptr)
+{
+    (void) ptr;
+
+    clock_add_to_group(BOARD_OWR_CLK_NAME, 0);
+}
+
+void board_init_clk_ref_pin(void)
+{
+    init_clk_ref_pins();
+}
+
+uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
+{
+    uint32_t freq = 0U;
+    if (ptr == HPM_GPTMR0) {
+        clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_gptmr0);
+    } else if (ptr == HPM_GPTMR1) {
+        clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_gptmr1);
+    } else if (ptr == HPM_GPTMR2) {
+        clock_add_to_group(clock_gptmr2, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_gptmr2);
+    } else if (ptr == HPM_GPTMR3) {
+        clock_add_to_group(clock_gptmr3, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_gptmr3);
+    } else if (ptr == HPM_PTMR) {
+        clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_ptmr);
+    } else {
+        /* Not supported */
+    }
+    return freq;
+}
+

bsp/hpmicro/hpm5e00evk/board/board.h

@@ -0,0 +1,662 @@
+/*
+ * Copyright (c) 2025 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _HPM_BOARD_H
+#define _HPM_BOARD_H
+#include <stdio.h>
+#include "hpm_common.h"
+#include "hpm_soc.h"
+#include "hpm_soc_feature.h"
+#include "hpm_clock_drv.h"
+#include "pinmux.h"
+#include "hpm_trgm_drv.h"
+#include "hpm_gptmr_drv.h"
+#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
+#include "hpm_debug_console.h"
+#endif
+
+#define BOARD_NAME          "hpm5e00evk"
+#define BOARD_UF2_SIGNATURE (0x0A4D5048UL)
+#define BOARD_CPU_FREQ      (480000000UL)
+
+#define SEC_CORE_IMG_START CORE1_ILM_LOCAL_BASE
+
+#ifndef BOARD_RUNNING_CORE
+#define BOARD_RUNNING_CORE HPM_CORE0
+#endif
+
+/* ACMP desction */
+#define BOARD_ACMP             HPM_ACMP0
+#define BOARD_ACMP_CLK         clock_acmp0
+#define BOARD_ACMP_CHANNEL     ACMP_CHANNEL_CHN1
+#define BOARD_ACMP_IRQ         IRQn_ACMP0_1
+#define BOARD_ACMP_PLUS_INPUT  ACMP_INPUT_DAC_OUT  /* use internal DAC */
+#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */
+
+/* uart section */
+#define BOARD_APP_UART_BASE       HPM_UART4
+#define BOARD_APP_UART_IRQ        IRQn_UART4
+#define BOARD_APP_UART_BAUDRATE   (115200UL)
+#define BOARD_APP_UART_CLK_NAME   clock_uart4
+#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART4_RX
+#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART4_TX
+
+#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PD13
+
+/* Trigger UART: UART0~3 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG0, UART4~7 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 */
+#define BOARD_APP_UART_TRIG         HPM_TRGM0_OUTPUT_SRC_UART_TRIG1
+#define BOARD_UART_TRGM             HPM_TRGM0
+#define BOARD_UART_TRGM_GPTMR       HPM_GPTMR3
+#define BOARD_UART_TRGM_GPTMR_CLK   clock_gptmr3
+#define BOARD_UART_TRGM_GPTMR_CH    2
+#define BOARD_UART_TRGM_GPTMR_INPUT HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2
+
+/* uart rx idle demo section */
+#define BOARD_UART_IDLE            BOARD_APP_UART_BASE
+#define BOARD_UART_IDLE_IRQ        BOARD_APP_UART_IRQ
+#define BOARD_UART_IDLE_CLK_NAME   BOARD_APP_UART_CLK_NAME
+#define BOARD_UART_IDLE_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ
+#define BOARD_UART_IDLE_DMA_SRC    BOARD_APP_UART_RX_DMA_REQ
+
+#define BOARD_UART_IDLE_GPTMR          HPM_GPTMR3
+#define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr3
+#define BOARD_UART_IDLE_GPTMR_IRQ      IRQn_GPTMR3
+#define BOARD_UART_IDLE_GPTMR_CMP_CH   0
+#define BOARD_UART_IDLE_GPTMR_CAP_CH   2
+
+/* uart microros sample section */
+#define BOARD_MICROROS_UART_BASE     BOARD_APP_UART_BASE
+#define BOARD_MICROROS_UART_IRQ      BOARD_APP_UART_IRQ
+#define BOARD_MICROROS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME
+
+/* usb cdc acm uart section */
+#define BOARD_USB_CDC_ACM_UART            BOARD_APP_UART_BASE
+#define BOARD_USB_CDC_ACM_UART_CLK_NAME   BOARD_APP_UART_CLK_NAME
+#define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ
+#define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ
+
+/* uart lin sample section */
+#define BOARD_UART_LIN                 BOARD_APP_UART_BASE
+#define BOARD_UART_LIN_IRQ             BOARD_APP_UART_IRQ
+#define BOARD_UART_LIN_CLK_NAME        BOARD_APP_UART_CLK_NAME
+#define BOARD_UART_LIN_TX_PORT         GPIO_DI_GPIOC
+#define BOARD_UART_LIN_TX_PIN          (16U)                         /* PC16 should align with used pin in pinmux configuration */
+#define BOARD_UART_LIN_PLB_TRGM_IN_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P05 /* align with used pin in pinmux configuration */
+
+/* plb lin baudrate detection */
+#define BOARD_PLB_TRGM_FILTER_GPIO_INPUT0 HPM_TRGM0_FILTER_SRC_TRGM0_P00
+#define BOARD_PLB_TRGM_DMA_REQ0           HPM_TRGM0_DMA_SRC_TRGM_0
+
+#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
+#ifndef BOARD_CONSOLE_TYPE
+#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART
+#endif
+
+#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
+#ifndef BOARD_CONSOLE_UART_BASE
+#if BOARD_RUNNING_CORE == HPM_CORE0
+#define BOARD_CONSOLE_UART_BASE       HPM_UART0
+#define BOARD_CONSOLE_UART_CLK_NAME   clock_uart0
+#define BOARD_CONSOLE_UART_IRQ        IRQn_UART0
+#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX
+#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX
+#else
+#define BOARD_CONSOLE_UART_BASE       HPM_UART11
+#define BOARD_CONSOLE_UART_CLK_NAME   clock_uart11
+#define BOARD_CONSOLE_UART_IRQ        IRQn_UART11
+#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART11_TX
+#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART11_RX
+#endif
+#endif
+#define BOARD_CONSOLE_UART_BAUDRATE (115200UL)
+#endif
+#endif
+
+/* rtthread-nano finsh section */
+#define BOARD_RT_CONSOLE_BASE     BOARD_CONSOLE_UART_BASE
+#define BOARD_RT_CONSOLE_CLK_NAME BOARD_CONSOLE_UART_CLK_NAME
+#define BOARD_RT_CONSOLE_IRQ      BOARD_CONSOLE_UART_IRQ
+
+/* modbus sample section */
+#define BOARD_MODBUS_UART_BASE       BOARD_APP_UART_BASE
+#define BOARD_MODBUS_UART_CLK_NAME   BOARD_APP_UART_CLK_NAME
+#define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ
+#define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ
+
+#define BOARD_FEMC_ASYNC_SRAM_CS_INDEX    0
+#define BOARD_FEMC_ASYNC_SRAM_AD_MUX_MODE false
+#define BOARD_FEMC_ASYNC_SRAM_SIZE        (128 * SIZE_1KB)
+
+/* nor flash section */
+#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL)
+#define BOARD_FLASH_SIZE         (1 * SIZE_1MB)
+
+/* i2c section */
+#define BOARD_APP_I2C_BASE     HPM_I2C0
+#define BOARD_APP_I2C_IRQ      IRQn_I2C0
+#define BOARD_APP_I2C_CLK_NAME clock_i2c0
+#define BOARD_APP_I2C_DMA      HPM_HDMA
+#define BOARD_APP_I2C_DMAMUX   HPM_DMAMUX
+#define BOARD_APP_I2C_DMA_SRC  HPM_DMA_SRC_I2C0
+
+/* dma section */
+#define BOARD_APP_XDMA      HPM_XDMA
+#define BOARD_APP_HDMA      HPM_HDMA
+#define BOARD_APP_XDMA_IRQ  IRQn_XDMA
+#define BOARD_APP_HDMA_IRQ  IRQn_HDMA
+#define BOARD_APP_DMAMUX    HPM_DMAMUX
+#define TEST_DMA_CONTROLLER HPM_XDMA
+#define TEST_DMA_IRQ        IRQn_XDMA
+
+/* APP PWM */
+#define BOARD_APP_PWM              HPM_PWM0
+#define BOARD_APP_PWM_CLOCK_NAME   clock_pwm0
+#define BOARD_APP_PWM_OUT1         pwm_channel_0
+#define BOARD_APP_PWM_OUT2         pwm_channel_1
+#define BOARD_APP_PWM_OUT3         pwm_channel_2
+#define BOARD_APP_PWM_OUT4         pwm_channel_3
+#define BOARD_APP_PWM_OUT5         pwm_channel_4
+#define BOARD_APP_PWM_OUT6         pwm_channel_5
+#define BOARD_APP_PWM_FAULT_PIN    (5)
+#define BOARD_APP_TRGM             HPM_TRGM0
+#define BOARD_APP_PWM_IRQ          IRQn_PWM0
+#define BOARD_APP_TRGM_PWM_OUTPUT  HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN_0
+#define BOARD_APP_TRGM_PWM_OUTPUT1 HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN_1
+#define BOARD_APP_TRGM_PWM_OUTPUT2 HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN_2
+#define BOARD_APP_TRGM_PWM_INPUT   HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0
+
+/* gptmr section */
+#define BOARD_GPTMR                   HPM_GPTMR0
+#define BOARD_GPTMR_IRQ               IRQn_GPTMR0
+#define BOARD_GPTMR_CHANNEL           2
+#define BOARD_GPTMR_DMA_SRC           HPM_DMA_SRC_GPTMR0_2
+#define BOARD_GPTMR_CLK_NAME          clock_gptmr0
+#define BOARD_GPTMR_PWM               HPM_GPTMR0
+#define BOARD_GPTMR_PWM_CHANNEL       2
+#define BOARD_GPTMR_PWM_DMA_SRC       HPM_DMA_SRC_GPTMR0_2
+#define BOARD_GPTMR_PWM_CLK_NAME      clock_gptmr0
+#define BOARD_GPTMR_PWM_IRQ           IRQn_GPTMR0
+#define BOARD_GPTMR_PWM_SYNC          HPM_GPTMR0
+#define BOARD_GPTMR_PWM_SYNC_CHANNEL  3
+#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr0
+
+#define BOARD_GPTMR_QEI          HPM_GPTMR1
+#define BOARD_GPTMR_QEI_CLK_NAME clock_gptmr1
+#define BOARD_GPTMR_QEI_CH_GROUP gptmr_qei_ch_group_23
+#define BOARD_GPTMR_QEI_PHMAX    4000
+
+/* User button */
+#define BOARD_APP_GPIO_CTRL        HPM_GPIO0
+#define BOARD_APP_GPIO_INDEX       GPIO_DI_GPIOC
+#define BOARD_APP_GPIO_PIN         21
+#define BOARD_APP_GPIO_IRQ         IRQn_GPIO0_C
+#define BOARD_BUTTON_PRESSED_VALUE 0
+
+/* gpiom section */
+#define BOARD_APP_GPIOM_BASE            HPM_GPIOM
+#define BOARD_APP_GPIOM_USING_CTRL      HPM_FGPIO
+#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast
+
+/* spi section */
+#define BOARD_APP_SPI_BASE              HPM_SPI1
+#define BOARD_APP_SPI_CLK_NAME          clock_spi1
+#define BOARD_APP_SPI_IRQ               IRQn_SPI1
+#define BOARD_APP_SPI_SCLK_FREQ         (20000000UL)
+#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U)
+#define BOARD_APP_SPI_DATA_LEN_IN_BITS  (8U)
+#define BOARD_APP_SPI_RX_DMA            HPM_DMA_SRC_SPI1_RX
+#define BOARD_APP_SPI_TX_DMA            HPM_DMA_SRC_SPI1_TX
+#define BOARD_SPI_CS_GPIO_CTRL          HPM_GPIO0
+#define BOARD_SPI_CS_PIN                IOC_PAD_PC11
+#define BOARD_SPI_CS_ACTIVE_LEVEL       (0U)
+
+/* Flash section */
+#define BOARD_APP_XPI_NOR_XPI_BASE     (HPM_XPI0)
+#define BOARD_APP_XPI_NOR_CFG_OPT_HDR  (0xfcf90002U)
+#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000006U)
+#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U)
+
+/* ADC section */
+#define BOARD_APP_ADC16_NAME     "ADC0"
+#define BOARD_APP_ADC16_BASE     HPM_ADC0
+#define BOARD_APP_ADC16_IRQn     IRQn_ADC0
+#define BOARD_APP_ADC16_CH_1     (1U)
+#define BOARD_APP_ADC16_CLK_NAME (clock_adc0)
+#define BOARD_APP_ADC16_CLK_BUS  (clk_adc_src_ahb0)
+
+#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_pwm0
+#define BOARD_APP_ADC16_HW_TRIG_SRC          HPM_PWM0
+#define BOARD_APP_ADC16_HW_TRGM              HPM_TRGM0
+#define BOARD_APP_ADC16_HW_TRGM_IN           HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0
+#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ      TRGM_TRGOCFG_ADC0_STRGI
+#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT      TRGM_TRGOCFG_ADCX_PTRGI0A
+
+#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A
+
+/* CAN section */
+#define BOARD_APP_CAN_BASE HPM_MCAN1
+#define BOARD_APP_CAN_IRQn IRQn_MCAN1
+
+/*
+ * timer for board delay
+ */
+#define BOARD_DELAY_TIMER          (HPM_GPTMR3)
+#define BOARD_DELAY_TIMER_CH       0
+#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr3)
+
+#define BOARD_CALLBACK_TIMER          (HPM_GPTMR3)
+#define BOARD_CALLBACK_TIMER_CH       1
+#define BOARD_CALLBACK_TIMER_IRQ      IRQn_GPTMR3
+#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3)
+
+/* LED */
+#define BOARD_LED_GPIO_CTRL  HPM_GPIO0
+#define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOC
+#define BOARD_LED_GPIO_PIN   28
+#define BOARD_LED_OFF_LEVEL  0
+#define BOARD_LED_ON_LEVEL   1
+
+#ifndef BOARD_SHOW_CLOCK
+#define BOARD_SHOW_CLOCK 1
+#endif
+#ifndef BOARD_SHOW_BANNER
+#define BOARD_SHOW_BANNER 1
+#endif
+
+/* enet section */
+#define BOARD_ENET_RGMII_RST_GPIO       HPM_GPIO0
+#define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOC
+#define BOARD_ENET_RGMII_RST_GPIO_PIN   (19U)
+
+#define BOARD_ENET_RGMII        HPM_ENET0
+#define BOARD_ENET_RGMII_TX_DLY (0U)
+#define BOARD_ENET_RGMII_RX_DLY (0U)
+
+#define BOARD_ENET_RGMII_PTP_CLOCK   (clock_ptp0)
+#define BOARD_ENET_RGMII_PPS0_PINOUT (0)
+
+/* MOTOR */
+#define BOARD_MOTOR_CLK_NAME clock_mot0
+
+/*BLDC PWM */
+#define BOARD_BLDCPWM              HPM_PWM0
+#define BOARD_BLDC_UH_PWM_OUTPIN   (0U)
+#define BOARD_BLDC_UL_PWM_OUTPIN   (1U)
+#define BOARD_BLDC_VH_PWM_OUTPIN   (2U)
+#define BOARD_BLDC_VL_PWM_OUTPIN   (3U)
+#define BOARD_BLDC_WH_PWM_OUTPIN   (4U)
+#define BOARD_BLDC_WL_PWM_OUTPIN   (5U)
+#define BOARD_BLDCPWM_TRGM         HPM_TRGM0
+#define BOARD_BLDCAPP_PWM_IRQ      IRQn_PWM0
+#define BOARD_BLDCPWM_CMP_INDEX_0  (0U)
+#define BOARD_BLDCPWM_CMP_INDEX_1  (1U)
+#define BOARD_BLDCPWM_CMP_INDEX_2  (2U)
+#define BOARD_BLDCPWM_CMP_INDEX_3  (3U)
+#define BOARD_BLDCPWM_CMP_INDEX_4  (4U)
+#define BOARD_BLDCPWM_CMP_INDEX_5  (5U)
+#define BOARD_BLDCPWM_CMP_INDEX_6  (6U)
+#define BOARD_BLDCPWM_CMP_INDEX_7  (7U)
+#define BOARD_BLDCPWM_CMP_TRIG_CMP (20U)
+
+/* BLDC ADC */
+#define BOARD_BLDC_ADC_MODULE    ADCX_MODULE_ADC16
+#define BOARD_BLDC_ADC_U_BASE    HPM_ADC0
+#define BOARD_BLDC_ADC_V_BASE    HPM_ADC1
+#define BOARD_BLDC_ADC_W_BASE    HPM_ADC0
+#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete
+
+#define BOARD_BLDC_ADC_CH_U                   (5U)
+#define BOARD_BLDC_ADC_CH_V                   (4U)
+#define BOARD_BLDC_ADC_CH_W                   (6U)
+#define BOARD_BLDC_ADC_IRQn                   IRQn_ADC0
+#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES)
+#define BOARD_BLDC_ADC_TRG                    ADC16_CONFIG_TRG0A
+#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN       (1U)
+#define BOARD_BLDC_PWM_TRIG_OUT_CHN           (0U)
+
+/* BLDC TRGM */
+#define BOARD_BLDC_PWM_TRG_ADC HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0
+#define BOARD_BLDC_TRG_ADC     HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A
+
+/* BLDC TIMER */
+#define BOARD_BLDC_TMR_1MS    HPM_GPTMR2
+#define BOARD_BLDC_TMR_BASE   HPM_GPTMR2
+#define BOARD_BLDC_TMR_CH     0
+#define BOARD_BLDC_TMR_CMP    0
+#define BOARD_BLDC_TMR_IRQ    IRQn_GPTMR2
+#define BOARD_BLDC_TMR_CLOCK  clock_gptmr2
+#define BOARD_BLDC_TMR_RELOAD (100000U)
+
+/* BLDC PARAM */
+#define BOARD_BLDC_BLOCK_SPEED_KP (0.0005f)
+#define BOARD_BLDC_BLOCK_SPEED_KI (0.000009f)
+
+#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KP (0.0074f)
+#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KI (0.0001f)
+#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KP (0.05f)
+#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KI (0.001f)
+#define BOARD_BLDC_SW_FOC_POSITION_KP (154.7f)
+#define BOARD_BLDC_SW_FOC_POSITION_KI (0.113f)
+
+#define BOARD_BLDC_HFI_SPEED_LOOP_KP (40.0f)
+#define BOARD_BLDC_HFI_SPEED_LOOP_KI (0.015f)
+#define BOARD_BLDC_HFI_PLL_KP (10.0f)
+#define BOARD_BLDC_HFI_PLL_KI (1.0f)
+
+/* QEIV2 */
+#define BOARD_BLDC_QEI_TRGM                      HPM_TRGM0
+#define BOARD_BLDC_QEIV2_BASE                    HPM_QEI0
+#define BOARD_BLDC_QEIV2_IRQ                     IRQn_QEI0
+#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U)
+#define BOARD_BLDC_QEI_CLOCK_SOURCE              clock_qei0
+#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV   (4000U)
+
+#define BOARD_APP_QEIV2_BASE                  HPM_QEI0
+#define BOARD_APP_QEIV2_IRQ                   IRQn_QEI0
+#define BOARD_APP_QEI_CLOCK_SOURCE            clock_qei0
+#define BOARD_APP_QEI_ADC_COS_BASE            HPM_ADC0
+#define BOARD_APP_QEI_ADC_COS_CHN             (6U)
+#define BOARD_APP_QEI_ADC_SIN_BASE            HPM_ADC1
+#define BOARD_APP_QEI_ADC_SIN_CHN             (5U)
+#define BOARD_APP_QEI_ADC_MATRIX_TO_ADC0      trgm_adc_matrix_output_to_qei0_adc0
+#define BOARD_APP_QEI_ADC_MATRIX_TO_ADC1      trgm_adc_matrix_output_to_qei0_adc1
+#define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_COS trgm_adc_matrix_in_from_adc0
+#define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_SIN trgm_adc_matrix_in_from_adc1
+#define BOARD_APP_QEI_TRG_ADC                 HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A
+
+/* PLB */
+#define BOARD_PLB_CLOCK_NAME clock_plb0
+
+#define BOARD_PLB_COUNTER          HPM_PLB
+#define BOARD_PLB_PWM_BASE         HPM_PWM0
+#define BOARD_PLB_PWM_CLOCK_NAME   clock_mot0
+#define BOARD_PLB_TRGM             HPM_TRGM0
+#define BOARD_PLB_PWM_TRG          (HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0)
+#define BOARD_PLB_IN_PWM_TRG       (TRGM_TRGOCFG_PLB_IN_00)
+#define BOARD_PLB_IN_PWM_PULSE_TRG (TRGM_TRGOCFG_PLB_IN_02)
+#define BOARD_PLB_CLR_SIGNAL_INPUT (HPM_TRGM0_INPUT_SRC_PLB_OUT32)
+#define BOARD_PLB_TYPEB_INPUT0     (TRGM_TRGOCFG_PLB_IN_32)
+#define BOARD_PLB_TO_TRG_IN        (HPM_TRGM0_INPUT_SRC_PLB_OUT00)
+#define BOARD_PLB_TRG_OUT          (HPM_TRGM0_OUTPUT_SRC_TRGM0_P05)
+#define BOARD_PLB_IO_TRG_SHIFT     (5)
+#define BOARD_PLB_PWM_CMP          (8U)
+#define BOARD_PLB_PWM_CHN          (8U)
+#define BOARD_PLB_CHN              plb_chn0
+
+#define BOARD_PLB_PHASE_COUNT_DEFAULT   (4000)
+#define BOARD_PLB_FILTER_LENGTH_DEFAULT (100)
+#define BOARD_PLB_QEI_A_PIN_SOURCE      HPM_TRGM0_INPUT_SRC_TRGM0_P07
+#define BOARD_PLB_QEI_B_PIN_SOURCE      HPM_TRGM0_INPUT_SRC_TRGM0_P06
+#define BOARD_PLB_QEI_Z_PIN_SOURCE      HPM_TRGM0_INPUT_SRC_TRGM0_P05
+
+#define BOARD_PLB_FILTER_SIG_INPUT_SOURCE  HPM_TRGM0_INPUT_SRC_TRGM0_P02
+#define BOARD_PLB_FILTER_SIG_OUTUPT_SOURCE HPM_TRGM0_OUTPUT_SRC_TRGM0_P04
+#define BOARD_PLB_FILTER_IO_TRG_SHIFT      (4)
+
+/* QEO ABZ */
+#define BOARD_QEO             HPM_QEO1
+#define BOARD_QEO_TRGM_POS    trgm_pos_matrix_output_to_qeo1
+#define BOARD_QEO_TRGM_POS_IN trgm_pos_matrix_in_from_qei0
+/* QEO PWM */
+#define BOARD_QEO_PWM             HPM_QEO0 /*QEO instance should align with PWM instance, such as QEO1 -> PWM1 */
+#define BOARD_QEO_TRGM_POS_PWM    trgm_pos_matrix_output_to_qeo0
+#define BOARD_QEO_PWM_TRGM_POS_IN trgm_pos_matrix_in_from_qei0
+#define BOARD_QEO_PWM_SAFETY_TRGM HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN_1
+
+#ifndef BOARD_SHOW_CLOCK
+#define BOARD_SHOW_CLOCK 1
+#endif
+#ifndef BOARD_SHOW_BANNER
+#define BOARD_SHOW_BANNER 1
+#endif
+
+/* FreeRTOS Definitions */
+#define BOARD_FREERTOS_TIMER          HPM_GPTMR1
+#define BOARD_FREERTOS_TIMER_CHANNEL  1
+#define BOARD_FREERTOS_TIMER_IRQ      IRQn_GPTMR1
+#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr1
+
+#define BOARD_FREERTOS_TICK_SRC_PWM          HPM_PWM0
+#define BOARD_FREERTOS_TICK_SRC_PWM_IRQ      IRQn_PWM0
+#define BOARD_FREERTOS_TICK_SRC_PWM_CLK_NAME clock_mot0
+#define BOARD_FREERTOS_TICK_SRC_PWM_COUNTER  pwm_counter_0
+#define BOARD_FREERTOS_TICK_SRC_PWM_SHADOW   PWMV2_SHADOW_INDEX(0)
+
+/* Threadx Definitions */
+#define BOARD_THREADX_TIMER          HPM_GPTMR1
+#define BOARD_THREADX_TIMER_CHANNEL  1
+#define BOARD_THREADX_TIMER_IRQ      IRQn_GPTMR1
+#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr1
+
+#define BOARD_THREADX_LOWPOWER_TIMER          HPM_PTMR
+#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL  1
+#define BOARD_THREADX_LOWPOWER_TIMER_IRQ      IRQn_PTMR
+#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr
+
+/* uC/OS-III Definitions */
+#define BOARD_UCOS_TIMER          HPM_GPTMR1
+#define BOARD_UCOS_TIMER_CHANNEL  1
+#define BOARD_UCOS_TIMER_IRQ      IRQn_GPTMR1
+#define BOARD_UCOS_TIMER_CLK_NAME clock_gptmr1
+
+/* EtherCAT definitions */
+/* ECAT PORT0 must support */
+#define BOARD_ECAT_SUPPORT_PORT1 (1)
+#define BOARD_ECAT_SUPPORT_PORT2 (1) /* require expansion board */
+
+#define BOARD_ECAT_SUPPORT_RUN_ERROR_LED (0) /* board not supports RUN/ERROR led */
+
+/* invert esc port link signal, require low level for linkup */
+#define BOARD_ECAT_PORT0_LINK_INVERT true  /* depend on hardware */
+#define BOARD_ECAT_PORT1_LINK_INVERT false /* depend on hardware */
+#define BOARD_ECAT_PORT2_LINK_INVERT false /* depend on hardware */
+
+#define BOARD_ECAT_PHY0_RESET_GPIO            HPM_GPIO0
+#define BOARD_ECAT_PHY0_RESET_GPIO_PORT_INDEX GPIO_DO_GPIOB
+#define BOARD_ECAT_PHY0_RESET_PIN_INDEX       (24)
+
+#define BOARD_ECAT_PHY1_RESET_GPIO            HPM_GPIO0
+#define BOARD_ECAT_PHY1_RESET_GPIO_PORT_INDEX GPIO_DO_GPIOB
+#define BOARD_ECAT_PHY1_RESET_PIN_INDEX       (24)
+
+#define BOARD_ECAT_PHY2_RESET_GPIO            HPM_GPIO0
+#define BOARD_ECAT_PHY2_RESET_GPIO_PORT_INDEX GPIO_DO_GPIOB
+#define BOARD_ECAT_PHY2_RESET_PIN_INDEX       (24)
+#define BOARD_ECAT_PHY_RESET_LEVEL            (0)
+
+#define BOARD_ECAT_IN1_GPIO            HPM_GPIO0
+#define BOARD_ECAT_IN1_GPIO_PORT_INDEX GPIO_DO_GPIOD
+#define BOARD_ECAT_IN1_GPIO_PIN_INDEX  (6U)
+
+#define BOARD_ECAT_IN2_GPIO            HPM_GPIO0
+#define BOARD_ECAT_IN2_GPIO_PORT_INDEX GPIO_DO_GPIOD
+#define BOARD_ECAT_IN2_GPIO_PIN_INDEX  (12U)
+
+#define BOARD_ECAT_OUT1_GPIO            HPM_GPIO0
+#define BOARD_ECAT_OUT1_GPIO_PORT_INDEX GPIO_DO_GPIOC
+#define BOARD_ECAT_OUT1_GPIO_PIN_INDEX  (24U)
+
+#define BOARD_ECAT_OUT2_GPIO            HPM_GPIO0
+#define BOARD_ECAT_OUT2_GPIO_PORT_INDEX GPIO_DO_GPIOC
+#define BOARD_ECAT_OUT2_GPIO_PIN_INDEX  (23)
+
+#define BOARD_ECAT_OUT_ON_LEVEL (1)
+
+#define BOARD_ECAT_NMII_LINK0_CTRL_INDEX 2
+#define BOARD_ECAT_NMII_LINK1_CTRL_INDEX 5
+#define BOARD_ECAT_NMII_LINK2_CTRL_INDEX 6
+
+/* ECAT PHY address definition */
+#define BOARD_ECAT_PHY_ADDR_OFFSET (1U)
+#define BOARD_ECAT_PORT0_PHY_ADDR  (0U) /* actual PHY address = BOARD_ECAT_PHY_ADDR_OFFSET + BOARD_ECAT_PORT0_PHY_ADDR */
+#define BOARD_ECAT_PORT1_PHY_ADDR  (1U) /* actual PHY address = BOARD_ECAT_PHY_ADDR_OFFSET + BOARD_ECAT_PORT1_PHY_ADDR */
+#define BOARD_ECAT_PORT2_PHY_ADDR  (2U) /* actual PHY address = BOARD_ECAT_PHY_ADDR_OFFSET + BOARD_ECAT_PORT2_PHY_ADDR */
+
+/* the address of ecat flash emulate eeprom component in flash */
+#define BOARD_ECAT_FLASH_EMULATE_EEPROM_ADDR (0x80000) /* offset 512K */
+
+/* sdm section */
+#define BOARD_SDM                 HPM_SDM0
+#define BOARD_SDM_IRQ             IRQn_SDM0
+#define BOARD_SDM_CHANNEL         0
+#define BOARD_SDM_TRGM            HPM_TRGM0
+#define BOARD_SDM_TRGM_GPTMR      HPM_GPTMR3
+#define BOARD_SDM_TRGM_GPTMR_CLK  clock_gptmr3
+#define BOARD_SDM_TRGM_GPTMR_CH   2
+#define BOARD_SDM_TRGM_INPUT_SRC  HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2
+#define BOARD_SDM_TRGM_OUTPUT_DST HPM_TRGM0_OUTPUT_SRC_SDM0_PWM_SOC15
+#define BOARD_SDM_TRGM_SYNC_SRC   (15)
+/* need to provide clock to sdm sensor */
+#define BOARD_SDM_SENSOR_REQUIRE_CLK true
+#define BOARD_SDM_CLK_PWM            HPM_PWM1
+#define BOARD_SDM_CLK_PWM_CLK_NAME   clock_pwm1
+#define BOARD_SDM_CLK_PWM_OUT        (7)
+
+/* LOBS */
+#define BOARD_LOBS_TRIG_GROUP lobs_signal_group_PC
+#define BOARD_LOBS_TRIG_PIN_0 11
+#define BOARD_LOBS_TRIG_PIN_1 10
+
+/* PPI */
+#define BOARD_PPI_ASYNC_SRAM_AD_MUX_MODE  true
+#define BOARD_PPI_ASYNC_SRAM_CS_INDEX     0
+#define BOARD_PPI_ASYNC_SRAM_SIG_DQ0_7    ppi_dq_pins_16_23
+#define BOARD_PPI_ASYNC_SRAM_SIG_DQ8_15   ppi_dq_pins_24_31
+#define BOARD_PPI_ASYNC_SRAM_SIG_DQ16_23  ppi_dq_pins_0_7
+#define BOARD_PPI_ASYNC_SRAM_SIG_DQ24_31  ppi_dq_pins_8_15
+#define BOARD_PPI_ASYNC_SRAM_ADV_CTRL_PIN 0
+#define BOARD_PPI_ASYNC_SRAM_WE_CTRL_PIN  1
+#define BOARD_PPI_ASYNC_SRAM_OE_CTRL_PIN  3
+#define BOARD_PPI_ASYNC_SRAM_SIZE         (256 * SIZE_1KB)
+
+#define BOARD_PPI_ADC_CS_INDEX 1
+
+/* EUI */
+#define BOARD_EUI                    HPM_EUI1
+#define BOARD_EUI_IRQ                IRQn_EUI1
+#define BOARD_EUI_CLOCK_NAME         clock_eui1
+#define BOARD_EUI_DEDICATE_OUT_LINES eui_dedicate_output_3_lines
+#define BOARD_EUI_ESC_KEY_ROW        0
+#define BOARD_EUI_ESC_KEY_COL        0
+#define BOARD_EUI_UP_KEY_ROW         0
+#define BOARD_EUI_UP_KEY_COL         1
+#define BOARD_EUI_ENTER_KEY_ROW      0
+#define BOARD_EUI_ENTER_KEY_COL      2
+#define BOARD_EUI_LEFT_KEY_ROW       1
+#define BOARD_EUI_LEFT_KEY_COL       0
+#define BOARD_EUI_DOWN_KEY_ROW       1
+#define BOARD_EUI_DOWN_KEY_COL       1
+#define BOARD_EUI_RIGHT_KEY_ROW      1
+#define BOARD_EUI_RIGHT_KEY_COL      2
+
+/* Bit0-seg A, Bit1-seg B , Bit2-seg C, Bit3-seg D, Bit4-seg E , Bit5-seg F, Bit6-seg G, Bit7-seg DP  */
+/* Code Data: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, b, C, d, E, F  */
+#define BOARD_EUI_SEG_ENCODE_DATA { 0x3f, 0x06, 0x5b, 0x4f, 0x66, 0x6d, 0x7d, 0x07, 0x7f, 0x6f, 0x77, 0x7c, 0x39, 0x5e, 0x79, 0x71 }
+#define BOARD_EUI_SEG_DP_BIT_MASK BIT7_MASK
+
+/* i2s over spi Section*/
+#define BOARD_I2S_SPI_CS_GPIO_CTRL  HPM_GPIO0
+#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOD
+#define BOARD_I2S_SPI_CS_GPIO_PIN   24
+#define BOARD_I2S_SPI_CS_GPIO_PAD   IOC_PAD_PD24
+
+#define BOARD_GPTMR_I2S_MCLK          HPM_GPTMR1
+#define BOARD_GPTMR_I2S_MCLK_CHANNEL  3
+#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr1
+
+#define BOARD_GPTMR_I2S_LRCK          HPM_GPTMR0
+#define BOARD_GPTMR_I2S_LRCK_CHANNEL  3
+#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr0
+
+#define BOARD_GPTMR_I2S_BCLK          HPM_GPTMR0
+#define BOARD_GPTMR_I2S_BLCK_CHANNEL  2
+#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr0
+
+#define BOARD_GPTMR_I2S_FINSH          HPM_GPTMR0
+#define BOARD_GPTMR_I2S_FINSH_IRQ      IRQn_GPTMR0
+#define BOARD_GPTMR_I2S_FINSH_CHANNEL  1
+#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr0
+
+#define BOARD_OWR          HPM_OWR0
+#define BOARD_OWR_CLK_NAME clock_owire0
+#define BOARD_OWR_CLK      clock_get_frequency(BOARD_OWR_CLK_NAME);
+
+#define BOARD_APP_CLK_REF_PIN_NAME "P5[22] (PC30)"
+#define BOARD_APP_CLK_REF_CLK_NAME clock_ref1
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+typedef void (*board_timer_cb)(void);
+
+void board_init(void);
+void board_init_console(void);
+void board_init_uart(UART_Type *ptr);
+uint32_t board_init_i2c_clock(I2C_Type *ptr);
+void board_init_i2c(I2C_Type *ptr);
+void board_init_can(MCAN_Type *ptr);
+void board_init_gpio_pins(void);
+void board_init_spi_pins(SPI_Type *ptr);
+void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr);
+void board_write_spi_cs(uint32_t pin, uint8_t state);
+uint8_t board_get_led_gpio_off_level(void);
+void board_init_led_pins(void);
+void board_led_write(uint8_t state);
+void board_led_toggle(void);
+void board_init_owr_pins(OWR_Type *ptr);
+
+/* Initialize SoC overall clocks */
+void board_init_clock(void);
+uint32_t board_init_femc_clock(void);
+uint32_t board_init_uart_clock(UART_Type *ptr);
+uint32_t board_init_spi_clock(SPI_Type *ptr);
+uint32_t board_init_can_clock(MCAN_Type *ptr);
+uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus);
+void board_init_acmp_clock(ACMP_Type *ptr);
+void board_init_owr_clock(OWR_Type *ptr);
+void board_init_adc16_pins(void);
+void board_init_acmp_pins(void);
+void board_init_usb(USB_Type *ptr);
+void board_init_enet_pps_pins(ENET_Type *ptr);
+uint8_t board_get_enet_dma_pbl(ENET_Type *ptr);
+hpm_stat_t board_reset_enet_phy(ENET_Type *ptr);
+hpm_stat_t board_init_enet_pins(ENET_Type *ptr);
+hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal);
+hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr);
+hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr);
+hpm_stat_t board_enable_enet_irq(ENET_Type *ptr);
+hpm_stat_t board_disable_enet_irq(ENET_Type *ptr);
+
+/*
+ * @brief Initialize PMP and PMA for but not limited to the following purposes:
+ *      -- non-cacheable memory initialization
+ */
+void board_init_pmp(void);
+void board_delay_us(uint32_t us);
+void board_delay_ms(uint32_t ms);
+void board_timer_create(uint32_t ms, board_timer_cb cb);
+void board_ungate_mchtmr_at_lp_mode(void);
+
+/*
+ * Get GPIO pin level of onboard LED
+ */
+uint8_t board_get_led_gpio_off_level(void);
+
+void board_init_ethercat(ESC_Type *ptr);
+
+void board_init_switch_led(void);
+void board_init_adc_qeiv2_pins(void);
+void init_pwm_fault_pins(void);
+void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp);
+void board_init_clk_ref_pin(void);
+uint32_t board_init_gptmr_clock(GPTMR_Type *ptr);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+#endif /* _HPM_BOARD_H */

bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/boards/hpm5e00evk.cfg

@@ -0,0 +1,89 @@
+# Copyright (c) 2024 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+# openocd flash driver argument:
+#   - option0:
+#       [31:28] Flash probe type
+#         0 - SFDP SDR / 1 - SFDP DDR
+#         2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+#         4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+#         6 - OctaBus DDR (SPI -> OPI DDR)
+#         8 - Xccela DDR (SPI -> OPI DDR)
+#         10 - EcoXiP DDR (SPI -> OPI DDR)
+#       [27:24] Command Pads after Power-on Reset
+#         0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+#       [23:20] Command Pads after Configuring FLASH
+#         0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+#       [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+#         0 - Not needed
+#         1 - QE bit is at bit6 in Status Register 1
+#         2 - QE bit is at bit1 in Status Register 2
+#         3 - QE bit is at bit7 in Status Register 2
+#         4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+#       [15:8] Dummy cycles
+#         0 - Auto-probed / detected / default value
+#         Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+#       [7:4] Misc.
+#         0 - Not used
+#         1 - SPI mode
+#         2 - Internal loopback
+#         3 - External DQS
+#       [3:0] Frequency option
+#         1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+#   - option1:
+#       [31:20]  Reserved
+#       [19:16] IO voltage
+#         0 - 3V / 1 - 1.8V
+#       [15:12] Pin group
+#         0 - 1st group / 1 - 2nd group
+#       [11:8] Connection selection
+#         0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+#       [7:0] Drive Strength
+#         0 - Default value
+
+# xpi0 configs
+#   - flash driver:     hpm_xpi
+#   - flash ctrl index: 0xF3000000
+#   - base address:     0x80000000
+#   - flash size:       0x2000000
+#   - flash option0:    0x5
+#   - flash option1:    0x1000
+flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000
+
+# xpi0_hybrid configs
+#   - flash driver:     hpm_xpi
+#   - flash ctrl index: 0xF3000000
+#   - base address:     0xB0000000
+#   - flash size:       0x2000000
+#   - flash option0:    0x5
+#   - flash option1:    0x1000
+flash bank xpi0_hybrid hpm_xpi 0xB0000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000
+
+proc init_clock {} {
+    $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+    $::_TARGET0 riscv dmi_write 0x3C 0x1
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+    $::_TARGET0 riscv dmi_write 0x3C 0x2
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000800
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000810
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000820
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000830
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+    echo "clocks has been enabled!"
+}
+
+$_TARGET0 configure -event reset-init {
+    init_clock
+}
+
+$_TARGET0 configure -event gdb-attach {
+    reset halt
+}

bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg

@@ -0,0 +1,11 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+adapter srst delay 500
+
+source [find interface/cmsis-dap.cfg]
+
+transport select jtag
+reset_config srst_only

bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/ft2232.cfg

@@ -0,0 +1,15 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+reset_config trst_and_srst
+adapter srst delay 50
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0208 0x020b
+ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800
+

bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/ft232.cfg

@@ -0,0 +1,14 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+reset_config trst_and_srst
+adapter srst delay 50
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6014
+
+ftdi_layout_init 0x0018 0x001b
+ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800

bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/jlink.cfg

@@ -0,0 +1,11 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+adapter srst delay 500
+
+source [find interface/jlink.cfg]
+
+transport select jtag
+reset_config srst_only

bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg

@@ -0,0 +1,14 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+adapter srst delay 500
+reset_config srst_only
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x010b
+ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800

bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm5e00.cfg

@@ -0,0 +1,18 @@
+# Copyright (c) 2024 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+set _CHIP hpm5e00
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+targets $_TARGET0
+
+proc reset_soc {} {
+    $::_TARGET0 riscv dmi_write 0x39 0xF410001C
+    $::_TARGET0 riscv dmi_write 0x3C 24000000
+}

bsp/hpmicro/hpm5e00evk/board/fal_cfg.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2022 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtconfig.h>
+#include <board.h>
+
+#ifdef RT_USING_FAL
+#define NOR_FLASH_DEV_NAME             "norflash0"
+#define NOR_FLASH_MEM_BASE             0x80000000UL
+#define NOR_FLASH_SIZE_IN_BYTES        0x1000000UL
+
+/* ===================== Flash device Configuration ========================= */
+extern struct fal_flash_dev nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &nor_flash0,                                                     \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                               \
+{                                                                                    \
+    {FAL_PART_MAGIC_WORD,       "app", NOR_FLASH_DEV_NAME,         0,           256*1024,    0}, \
+    {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME,         256*1024, 256*1024,    0}, \
+    {FAL_PART_MAGIC_WORD,  "download", NOR_FLASH_DEV_NAME,         512*1024, 256*1024,    0}, \
+    {FAL_PART_MAGIC_WORD,   "flashdb", NOR_FLASH_DEV_NAME,        768*1024, 256*1024,    0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* RT_USING_FAL */
+
+#endif /* _FAL_CFG_H_ */

bsp/hpmicro/hpm5e00evk/board/fal_flash_port.c

@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) 2022 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Change Logs:
+ * Date         Author      Notes
+ * 2022-03-09   hpmicro     First implementation
+ * 2022-08-01   hpmicro     Fixed random crashing during kvdb_init
+ * 2022-08-03   hpmicro     Improved erase speed
+ * 2023-05-15   hpmicro     Disable global interrupt during FLASH operation for FLASH build
+ *
+ */
+#include <rtthread.h>
+#include <rthw.h>
+#ifdef RT_USING_FAL
+#include "fal.h"
+#include "hpm_romapi.h"
+#include "board.h"
+#include "hpm_l1c_drv.h"
+
+#if defined(FLASH_XIP) && (FLASH_XIP == 1)
+
+static rt_base_t s_interrupt_level;
+#define FAL_ENTER_CRITICAL() do {\
+        rt_exit_critical();\
+        fencei();\
+        s_interrupt_level = rt_hw_interrupt_disable();\
+    } while(0)
+
+#define FAL_EXIT_CRITICAL() do {\
+        ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\
+        fencei();\
+        rt_exit_critical();\
+        rt_hw_interrupt_enable(s_interrupt_level);\
+    } while(0)
+
+#define FAL_RAMFUNC __attribute__((section(".isr_vector")))
+
+#else
+#define FAL_ENTER_CRITICAL() rt_enter_critical()
+
+#define FAL_EXIT_CRITICAL() rt_exit_critical()
+
+#define FAL_RAMFUNC
+
+#endif
+
+/***************************************************************************************************
+ *      FAL Porting Guide
+ *
+ *      1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH
+ *         must be placed at RAM or ROM code
+ *      2. During FLASH erase/program, it is recommended to disable the interrupt, or place the
+ *         interrupt related codes to RAM
+ *
+ ***************************************************************************************************/
+
+static int init(void);
+static int read(long offset, rt_uint8_t *buf, rt_size_t size);
+static int write(long offset, const rt_uint8_t *buf, rt_size_t size);
+static int erase(long offset, rt_size_t size);
+
+static xpi_nor_config_t s_flashcfg;
+
+/**
+ * @brief FAL Flash device context
+ */
+struct fal_flash_dev nor_flash0 =
+    {
+            .name = NOR_FLASH_DEV_NAME,
+            /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */
+            .addr = NOR_FLASH_MEM_BASE,
+            .len = 8 * 1024 * 1024,
+            .blk_size = 4096,
+            .ops = { .init = init, .read = read, .write = write, .erase = erase },
+            .write_gran = 1
+    };
+
+/**
+ * @brief FAL initialization
+ *        This function probes the FLASH using the ROM API
+ */
+FAL_RAMFUNC static int init(void)
+{
+    int ret = RT_EOK;
+    xpi_nor_config_option_t cfg_option;
+    cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR;
+    cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0;
+    cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1;
+
+    FAL_ENTER_CRITICAL();
+    hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option);
+    FAL_EXIT_CRITICAL();
+    if (status != status_success)
+    {
+        ret = -RT_ERROR;
+    }
+    else
+    {
+        /* update the flash chip information */
+        rt_uint32_t sector_size;
+        rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, &sector_size);
+        rt_uint32_t flash_size;
+        rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size);
+        nor_flash0.blk_size = sector_size;
+        nor_flash0.len = flash_size;
+    }
+
+    return ret;
+}
+
+/**
+ * @brief FAL read function
+ *        Read data from FLASH
+ * @param offset FLASH offset
+ * @param buf Buffer to hold data read by this API
+ * @param size Size of data to be read
+ * @return actual read bytes
+ */
+FAL_RAMFUNC static int read(long offset, rt_uint8_t *buf, rt_size_t size)
+{
+    rt_uint32_t flash_addr = nor_flash0.addr + offset;
+    rt_uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr);
+    rt_uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size);
+    rt_uint32_t aligned_size = aligned_end - aligned_start;
+    rt_base_t level = rt_hw_interrupt_disable();
+    l1c_dc_invalidate(aligned_start, aligned_size);
+    rt_hw_interrupt_enable(level);
+
+    (void) rt_memcpy(buf, (void*) flash_addr, size);
+
+    return size;
+}
+
+/**
+ * @brief Write unaligned data to the page
+ * @param offset FLASH offset
+ * @param buf Data buffer
+ * @param size Size of data to be written
+ * @return actual size of written data or error code
+ */
+FAL_RAMFUNC static int write_unaligned_page_data(long offset, const rt_uint32_t *buf, rt_size_t size)
+{
+    hpm_stat_t status;
+
+    FAL_ENTER_CRITICAL();
+    status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size);
+    FAL_EXIT_CRITICAL();
+
+    if (status != status_success)
+    {
+        return -RT_ERROR;
+        rt_kprintf("write failed, status=%d\n", status);
+    }
+
+    return size;
+}
+
+/**
+ * @brief FAL write function
+ *        Write data to specified FLASH address
+ * @param offset FLASH offset
+ * @param buf Data buffer
+ * @param size Size of data to be written
+ * @return actual size of written data or error code
+ */
+FAL_RAMFUNC static int write(long offset, const rt_uint8_t *buf, rt_size_t size)
+{
+    rt_uint32_t *src = NULL;
+    rt_uint32_t buf_32[64];
+    rt_uint32_t write_size;
+    rt_size_t remaining_size = size;
+    int ret = (int)size;
+
+    rt_uint32_t page_size;
+    rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size);
+    rt_uint32_t offset_in_page = offset % page_size;
+    if (offset_in_page != 0)
+    {
+        rt_uint32_t write_size_in_page = page_size - offset_in_page;
+        rt_uint32_t write_page_size = MIN(write_size_in_page, size);
+        (void) rt_memcpy(buf_32, buf, write_page_size);
+        write_size = write_unaligned_page_data(offset, buf_32, write_page_size);
+        if (write_size < 0)
+        {
+            ret = -RT_ERROR;
+            goto write_quit;
+        }
+
+        remaining_size -= write_page_size;
+        offset += write_page_size;
+        buf += write_page_size;
+    }
+
+    while (remaining_size > 0)
+    {
+        write_size = MIN(remaining_size, sizeof(buf_32));
+        rt_memcpy(buf_32, buf, write_size);
+        src = &buf_32[0];
+
+        FAL_ENTER_CRITICAL();
+        hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src,
+                offset, write_size);
+        FAL_EXIT_CRITICAL();
+
+        if (status != status_success)
+        {
+            ret = -RT_ERROR;
+            rt_kprintf("write failed, status=%d\n", status);
+            break;
+        }
+
+        remaining_size -= write_size;
+        buf += write_size;
+        offset += write_size;
+    }
+
+write_quit:
+    return ret;
+}
+
+/**
+ * @brief FAL erase function
+ *        Erase specified FLASH region
+ * @param offset the start FLASH address to be erased
+ * @param size size of the region to be erased
+ * @ret RT_EOK Erase operation is successful
+ * @retval -RT_ERROR Erase operation failed
+ */
+FAL_RAMFUNC static int erase(long offset, rt_size_t size)
+{
+    rt_uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U);
+    hpm_stat_t status;
+    int ret = (int)size;
+
+    rt_uint32_t block_size;
+    rt_uint32_t sector_size;
+    (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, &sector_size);
+    (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size);
+    rt_uint32_t erase_unit;
+    while (aligned_size > 0)
+    {
+        FAL_ENTER_CRITICAL();
+        if ((offset % block_size == 0) && (aligned_size >= block_size))
+        {
+            erase_unit = block_size;
+            status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset);
+        }
+        else
+        {
+            erase_unit = sector_size;
+            status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset);
+        }
+        FAL_EXIT_CRITICAL();
+
+        if (status != status_success)
+        {
+            ret = -RT_ERROR;
+            break;
+        }
+        offset += erase_unit;
+        aligned_size -= erase_unit;
+    }
+
+    return ret;
+}
+#endif /* RT_USING_FAL */

bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c → bsp/hpmicro/hpm5e00evk/board/hpm_wm8960.c

@@ -7,6 +7,7 @@
  *
  */
 
+#include <stdio.h>
 #include "hpm_wm8960.h"
 
 #ifndef HPM_WM8960_MCLK_TOLERANCE
@@ -491,16 +492,20 @@ hpm_stat_t wm8960_config_input_to_output_mixer(wm8960_control_t *control, uint32
 
 hpm_stat_t wm8960_write_reg(wm8960_control_t *control, uint8_t reg, uint16_t val)
 {
-    uint8_t buff[2];
     /* The first 7 bits (B15 to B9) are address bits that select which control register */
     /* is accessed. The remaining 9 bits (B8 to B0) are data bits */
-    buff[0] = (reg << 1) | (uint8_t)((val >> 8U) & 0x0001U);
-    buff[1] = (uint8_t)(val & 0xFFU);
+    rt_size_t size;
+    rt_uint8_t data[2];
+    data[0] = (reg << 1) | (uint8_t)((val >> 8U) & 0x0001U);
+    data[1] = (uint8_t)(val & 0xFFU);
 
-    /* record reg val */
-    wm8960_reg_val[reg] = val;
+    size = rt_i2c_master_send(control->i2c_bus, control->slave_address, RT_I2C_WR, data, 2U);
+    if (size != 2) {
+        return status_fail;
+    }
 
-    return i2c_master_write(control->ptr, control->slave_address, buff, 2U);
+    wm8960_reg_val[reg] = val;
+    return status_success;
 }
 
 hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val)

bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.h → bsp/hpmicro/hpm5e00evk/board/hpm_wm8960.h

@@ -7,11 +7,15 @@
  *
  */
 
-#ifndef _HPM_SGTL5000_H_
-#define _HPM_SGTL5000_H_
-
-#include "hpm_i2c_drv.h"
-#include "hpm_common.h"
+#ifndef _HPM_WM8960_H_
+#define _HPM_WM8960_H_
+
+//#include "hpm_i2c_drv.h"
+//#include "hpm_common.h"
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "rtt_board.h"
+#include "drivers/dev_i2c.h"
 #include "hpm_wm8960_regs.h"
 
 #define WM8960_I2C_ADDR 0x1A
@@ -81,7 +85,7 @@ typedef struct wm8960_config {
 } wm8960_config_t;
 
 typedef struct {
-    I2C_Type *ptr;                     /* I2C bus */
+    struct rt_i2c_bus_device *i2c_bus;  /* I2C bus device */
     uint8_t slave_address;             /* code device address */
 } wm8960_control_t;
 
@@ -220,4 +224,4 @@ hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val);
 hpm_stat_t wm8960_modify_reg(wm8960_control_t *control, uint8_t reg, uint16_t mask, uint16_t val);
 
 
-#endif /* _HPM_SGTL5000_H_ */
+#endif /* _HPM_WM8960_H_ */

bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/flash_xip.ld → bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_hybrid_rtt.ld

@@ -1,33 +1,33 @@
 /*
- * Copyright (c) 2023 HPMicro
+ * Copyright 2021-2025 HPMicro
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 ENTRY(_start)
 
-STACK_SIZE = _stack_size;
-HEAP_SIZE = _heap_size;
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 64K;
+FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 1M;
 
 MEMORY
 {
-    XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size
-    ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K
-    DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K
-    AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K
+    FLASH (rx) : ORIGIN = 0xB0000000, LENGTH = FLASH_SIZE
+    ILM (wx) : ORIGIN = 0, LENGTH = 128K
+    DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K
+    AHB_SRAM (w): ORIGIN = 0xF0200000, LENGTH = 32k
 }
 
-__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
-__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000;
-__app_load_addr__ = ORIGIN(XPI0) + 0x3000;
+__nor_cfg_option_load_addr__ = ORIGIN(FLASH) + 0x400;
+__boot_header_load_addr__ = ORIGIN(FLASH) + 0x1000;
+__app_load_addr__ = ORIGIN(FLASH) + 0x3000;
 __boot_header_length__ = __boot_header_end__ - __boot_header_start__;
 __app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
 
-
 SECTIONS
 {
     .nor_cfg_option __nor_cfg_option_load_addr__ : {
         KEEP(*(.nor_cfg_option))
-    } > XPI0
+    } > FLASH
 
     .boot_header __boot_header_load_addr__ : {
         __boot_header_start__ = .;
@@ -35,27 +35,42 @@ SECTIONS
         KEEP(*(.fw_info_table))
         KEEP(*(.dc_info))
         __boot_header_end__ = .;
-    } > XPI0
+    } > FLASH
 
     .start __app_load_addr__ : {
         . = ALIGN(8);
         KEEP(*(.start))
-    } > XPI0
+        . = ALIGN(16);
+    } > FLASH
 
     __vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
-    .vectors ORIGIN(ILM) : AT(__vector_load_addr__) {
-        . = ALIGN(8);
+    .vectors : AT(__vector_load_addr__) {
+        . = ALIGN(16);
         __vector_ram_start__ = .;
         KEEP(*(.vector_table))
         KEEP(*(.isr_vector))
-        KEEP(*(.vector_s_table))
-        KEEP(*(.isr_s_vector))
-        . = ALIGN(8);
+
+        . = ALIGN(16);
         __vector_ram_end__ = .;
     } > ILM
 
+    .fast : AT(__fast_load_addr__) {
+        . = ALIGN(16);
+        __ramfunc_start__ = .;
+        *(.fast)
+        *(.fast.*)
+        . = ALIGN(16);
+
+        /* RT-Thread Core Start */
+        /* RT-Thread Core End */
+
+        /* HPMicro Driver Wrapper */
+        . = ALIGN(16);
+        __ramfunc_end__ = .;
+    } > ILM
+
     .text (__vector_load_addr__ + SIZEOF(.vectors)) : {
-        . = ALIGN(8);
+        . = ALIGN(16);
         *(.text)
         *(.text*)
         *(.rodata)
@@ -68,16 +83,18 @@ SECTIONS
         *(.gnu*)
         *(.pl*)
 
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
         KEEP (*(.init))
         KEEP (*(.fini))
-
-        /* section information for usbh class */
         . = ALIGN(8);
-        __usbh_class_info_start__ = .;
-        KEEP(*(.usbh_class_info))
-        __usbh_class_info_end__ = .;
 
-        /* RT-Thread related sections - Start */
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
         /* section information for finsh shell */
         . = ALIGN(4);
         __fsymtab_start = .;
@@ -102,33 +119,90 @@ SECTIONS
         __rtmsymtab_end = .;
 
         /* RT-Thread related sections - end */
+
+        /* section information for usbh class */
         . = ALIGN(8);
-    } > XPI0
+        __usbh_class_info_start__ = .;
+        KEEP(*(.usbh_class_info))
+        __usbh_class_info_end__ = .;
+
+    } > FLASH
 
     .eh_frame :
     {
         __eh_frame_start = .;
         KEEP(*(.eh_frame))
         __eh_frame_end = .;
-    }  > XPI0
+    }  > FLASH
 
     .eh_frame_hdr :
     {
         KEEP(*(.eh_frame_hdr))
-    }  > XPI0
+    }  > FLASH
     __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0;
     __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0;
 
-
     .rel : {
         KEEP(*(.rel*))
-    } > XPI0
+    } > FLASH
 
     PROVIDE (__etext = .);
     PROVIDE (_etext = .);
     PROVIDE (etext = .);
 
-    __data_load_addr__ = etext;
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > ILM
+
+    __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
+        .fast_ram.init : AT(__fast_ram_init_load_addr__) {
+        . = ALIGN(8);
+        __fast_ram_init_start__ = .;
+        KEEP(*(.fast_ram.init))
+        KEEP(*(.fast_ram.init.*))
+        __fast_ram_init_end__ = .;
+        . = ALIGN(8);
+    } > ILM
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > ILM
+
+    /* Note: the .tbss and .tdata section should be adjacent */
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.gnu.linkonce.tb.*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > ILM
+
+    __tdata_load_addr__ = etext;
+    .tdata : AT(__tdata_load_addr__) {
+        . = ALIGN(8);
+        __tdata_start__ = .;
+        __thread_pointer = .;
+        *(.tdata)
+        *(.tdata*)
+        *(.gnu.linkonce.td.*)
+        . = ALIGN(8);
+        __tdata_end__ = .;
+    } > ILM
+
+    __data_load_addr__ = etext + SIZEOF(.tdata);
     .data : AT(__data_load_addr__) {
         . = ALIGN(8);
         __data_start__ = .;
@@ -157,16 +231,18 @@ SECTIONS
         PROVIDE(__init_array_end = .);
 
         . = ALIGN(8);
-        PROVIDE(__finit_array_start = .);
-        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
-        KEEP(*(.finit_array))
-        PROVIDE(__finit_array_end = .);
+        PROVIDE(__fini_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE(__fini_array_end = .);
 
         . = ALIGN(8);
+        PROVIDE(__ctors_start__ = .);
         KEEP(*crtbegin*.o(.ctors))
         KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
         KEEP(*(SORT(.ctors.*)))
         KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
 
         . = ALIGN(8);
         KEEP(*crtbegin*.o(.dtors))
@@ -178,119 +254,59 @@ SECTIONS
         PROVIDE (__edata = .);
         PROVIDE (_edata = .);
         PROVIDE (edata = .);
-    } > DLM
+    } > ILM
+    __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata);
 
-    __fast_load_addr__ = etext + SIZEOF(.data);
-    .fast : AT(__fast_load_addr__) {
-        . = ALIGN(8);
-        PROVIDE(__ramfunc_start__ = .);
-        *(.fast)
-        *(.fast.*)
+    __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr);
+
+    .heap(NOLOAD) : {
         . = ALIGN(8);
-        PROVIDE(__ramfunc_end__ = .);
-    } > ILM
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+    } > DLM
 
-    __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast);
-    .tdata : AT(__tdata_load_addr__) {
+    .framebuffer (NOLOAD) : {
         . = ALIGN(8);
-        PROVIDE(__tdata_start__ = .);
-        *(.tdata)
-        *(.tdata.*)
-        *(.gnu.linkonce.td.*)
+        KEEP(*(.framebuffer))
         . = ALIGN(8);
-        PROVIDE(__tdata_end__ = .);
     } > DLM
 
-    .tbss (NOLOAD) : {
+    .stack(NOLOAD) : {
         . = ALIGN(8);
-        PROVIDE(__tbss_start__ = .);
-        __thread_pointer$ = .;
-        *(.tbss)
-        *(.tbss.*)
-        *(.gnu.linkonce.tb.*)
-        *(.tcommon)
+        __stack_base__ = .;
+        . += STACK_SIZE;
         . = ALIGN(8);
-        PROVIDE(__tbss_end__ = .);
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+        PROVIDE( __rt_rvstack = . );
     } > DLM
 
-    __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata);
+    __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
     .noncacheable.init : AT(__noncacheable_init_load_addr__) {
         . = ALIGN(8);
+        __noncacheable_start__ = .;
         __noncacheable_init_start__ = .;
         KEEP(*(.noncacheable.init))
         __noncacheable_init_end__ = .;
         . = ALIGN(8);
     } > DLM
 
-    __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
-    .fast_ram.init : AT(__fast_ram_init_load_addr__) {
-        . = ALIGN(8);
-        __fast_ram_init_start__ = .;
-        KEEP(*(.fast_ram.init))
-        __fast_ram_init_end__ = .;
-        . = ALIGN(8);
-    } > DLM
-
-    .bss (NOLOAD) : {
-        . = ALIGN(8);
-        __bss_start__ = .;
-        *(.bss)
-        *(.bss*)
-        *(.sbss*)
-        *(.scommon)
-        *(.scommon*)
-        *(.dynsbss*)
-        *(COMMON)
-        . = ALIGN(8);
-        _end = .;
-        __bss_end__ = .;
-    } > DLM
-
-    .framebuffer (NOLOAD) : {
-        . = ALIGN(8);
-        KEEP(*(.framebuffer))
-        . = ALIGN(8);
-    } > DLM
-
     .noncacheable.bss (NOLOAD) : {
         . = ALIGN(8);
         KEEP(*(.noncacheable))
+        KEEP(*(.noncacheable.non_init))
+        KEEP(*(.noncacheable.non_init.*))
         __noncacheable_bss_start__ = .;
         KEEP(*(.noncacheable.bss))
+        KEEP(*(.noncacheable.bss.*))
         __noncacheable_bss_end__ = .;
+        __noncacheable_end__ = .;
         . = ALIGN(8);
     } > DLM
 
-    .fast_ram.bss (NOLOAD) : {
-        . = ALIGN(8);
-        KEEP(*(.fast_ram))
-        __fast_ram_bss_start__ = .;
-        KEEP(*(.fast_ram.bss))
-        __fast_ram_bss_end__ = .;
-        . = ALIGN(8);
-    } > DLM
-
-    .heap (NOLOAD) : {
-        . = ALIGN(8);
-        __heap_start__ = .;
-        . += HEAP_SIZE;
-        __heap_end__ = .;
-    } > DLM
-
-    .stack (NOLOAD) : {
-        . = ALIGN(16);
-        __stack_base__ = .;
-        . += STACK_SIZE;
-        . = ALIGN(16);
-        PROVIDE (_stack = .);
-        PROVIDE (_stack_safe = .);
-    } > DLM
-
     .ahb_sram (NOLOAD) : {
         KEEP(*(.ahb_sram))
     } > AHB_SRAM
 
-    __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init);
-    __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init);
-    ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "******  FAILED! XPI0 has not enough space!  ******")
 }

bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_rtt.ld

@@ -0,0 +1,331 @@
+/*
+ * Copyright 2021-2025 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K;
+FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 1M;
+
+MEMORY
+{
+    XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
+    ILM (wx) : ORIGIN = 0, LENGTH = 128K
+    DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K
+    AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 256K
+    AHB_SRAM (w): ORIGIN = 0xF0200000, LENGTH = 32k
+}
+
+__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
+__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000;
+__app_load_addr__ = ORIGIN(XPI0) + 0x3000;
+__boot_header_length__ = __boot_header_end__ - __boot_header_start__;
+__app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
+
+SECTIONS
+{
+    .nor_cfg_option __nor_cfg_option_load_addr__ : {
+        KEEP(*(.nor_cfg_option))
+    } > XPI0
+
+    .boot_header __boot_header_load_addr__ : {
+        __boot_header_start__ = .;
+        KEEP(*(.boot_header))
+        KEEP(*(.fw_info_table))
+        KEEP(*(.dc_info))
+        __boot_header_end__ = .;
+    } > XPI0
+
+    .start __app_load_addr__ : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+        . = ALIGN(16);
+    } > XPI0
+
+    __vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
+    .vectors : AT(__vector_load_addr__) {
+        . = ALIGN(16);
+        __vector_ram_start__ = .;
+        KEEP(*(.vector_table))
+        KEEP(*(.isr_vector))
+
+        . = ALIGN(16);
+        __vector_ram_end__ = .;
+    } > ILM
+
+    .fast : AT(__fast_load_addr__) {
+        . = ALIGN(16);
+        __ramfunc_start__ = .;
+        *(.fast)
+        *(.fast.*)
+        . = ALIGN(16);
+
+        /* RT-Thread Core Start */
+        KEEP(*context_gcc.o(.text* .rodata*))
+        KEEP(*port*.o (.text .text* .rodata .rodata*))
+        KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*))
+        KEEP(*trap_common.o (.text .text* .rodata .rodata*))
+        KEEP(*irq.o (.text .text* .rodata .rodata*))
+        KEEP(*clock.o (.text .text* .rodata .rodata*))
+        KEEP(*kservice.o (.text .text* .rodata .rodata*))
+        KEEP(*scheduler.o (.text .text* .rodata .rodata*))
+        KEEP(*trap*.o (.text .text* .rodata .rodata*))
+        KEEP(*idle.o (.text .text* .rodata .rodata*))
+        KEEP(*ipc.o (.text .text* .rodata .rodata*))
+        KEEP(*thread.o (.text .text* .rodata .rodata*))
+        KEEP(*object.o (.text .text* .rodata .rodata*))
+        KEEP(*timer.o (.text .text* .rodata .rodata*))
+        KEEP(*mem.o (.text .text* .rodata .rodata*))
+        KEEP(*mempool.o (.text .text* .rodata .rodata*))
+        /* RT-Thread Core End */
+
+        /* HPMicro Driver Wrapper */
+        KEEP(*drv_*.o (.text .text* .rodata .rodata*))
+
+        . = ALIGN(16);
+        __ramfunc_end__ = .;
+    } > ILM
+
+    .text (__vector_load_addr__ + SIZEOF(.vectors)) : {
+        . = ALIGN(16);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+        /* section information for usbh class */
+        . = ALIGN(8);
+        __usbh_class_info_start__ = .;
+        KEEP(*(.usbh_class_info))
+        __usbh_class_info_end__ = .;
+
+    } > XPI0
+
+    .eh_frame :
+    {
+        __eh_frame_start = .;
+        KEEP(*(.eh_frame))
+        __eh_frame_end = .;
+    }  > XPI0
+
+    .eh_frame_hdr :
+    {
+        KEEP(*(.eh_frame_hdr))
+    }  > XPI0
+    __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0;
+    __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0;
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > XPI0
+
+    PROVIDE (__etext = .);
+    PROVIDE (_etext = .);
+    PROVIDE (etext = .);
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
+
+    __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
+        .fast_ram.init : AT(__fast_ram_init_load_addr__) {
+        . = ALIGN(8);
+        __fast_ram_init_start__ = .;
+        KEEP(*(.fast_ram.init))
+        KEEP(*(.fast_ram.init.*))
+        __fast_ram_init_end__ = .;
+        . = ALIGN(8);
+    } > DLM
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > AXI_SRAM
+
+    /* Note: the .tbss and .tdata section should be adjacent */
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.gnu.linkonce.tb.*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > AXI_SRAM
+
+    __tdata_load_addr__ = etext;
+    .tdata : AT(__tdata_load_addr__) {
+        . = ALIGN(8);
+        __tdata_start__ = .;
+        __thread_pointer = .;
+        *(.tdata)
+        *(.tdata*)
+        *(.gnu.linkonce.td.*)
+        . = ALIGN(8);
+        __tdata_end__ = .;
+    } > DLM
+
+    __data_load_addr__ = etext + SIZEOF(.tdata);
+    .data : AT(__data_load_addr__) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_except_table))
+        KEEP(*(.gcc_except_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__fini_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE(__fini_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > AXI_SRAM
+    __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata);
+
+    __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr);
+
+    .heap(NOLOAD) : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+    } > AXI_SRAM
+
+    .framebuffer (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.framebuffer))
+        . = ALIGN(8);
+    } > AXI_SRAM
+
+    .stack(NOLOAD) : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        . = ALIGN(8);
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+        PROVIDE( __rt_rvstack = . );
+    } > AXI_SRAM
+
+    __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
+    .noncacheable.init : AT(__noncacheable_init_load_addr__) {
+        . = ALIGN(8);
+        __noncacheable_start__ = .;
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        . = ALIGN(8);
+    } > DLM
+
+    .noncacheable.bss (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.noncacheable))
+        KEEP(*(.noncacheable.non_init))
+        KEEP(*(.noncacheable.non_init.*))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        KEEP(*(.noncacheable.bss.*))
+        __noncacheable_bss_end__ = .;
+        __noncacheable_end__ = .;
+        . = ALIGN(8);
+    } > DLM
+
+    .ahb_sram (NOLOAD) : {
+        KEEP(*(.ahb_sram))
+    } > AHB_SRAM
+
+}

bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_rtt_enet.ld

@@ -0,0 +1,350 @@
+/*
+ * Copyright 2021-2025 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 32K;
+FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 1M;
+
+MEMORY
+{
+    XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
+    ILM (wx) : ORIGIN = 0, LENGTH = 128K
+    DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K
+    AXI_SRAM (wx) : ORIGIN = 0x01220000, LENGTH = 256K
+    AHB_SRAM (w): ORIGIN = 0xF0200000, LENGTH = 32k
+}
+
+__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
+__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000;
+__app_load_addr__ = ORIGIN(XPI0) + 0x3000;
+__boot_header_length__ = __boot_header_end__ - __boot_header_start__;
+__app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
+
+SECTIONS
+{
+    .nor_cfg_option __nor_cfg_option_load_addr__ : {
+        KEEP(*(.nor_cfg_option))
+    } > XPI0
+
+    .boot_header __boot_header_load_addr__ : {
+        __boot_header_start__ = .;
+        KEEP(*(.boot_header))
+        KEEP(*(.fw_info_table))
+        KEEP(*(.dc_info))
+        __boot_header_end__ = .;
+    } > XPI0
+
+    .start __app_load_addr__ : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+        . = ALIGN(16);
+    } > XPI0
+
+    __vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
+    .vectors : AT(__vector_load_addr__) {
+        . = ALIGN(16);
+        __vector_ram_start__ = .;
+        KEEP(*(.vector_table))
+        KEEP(*(.isr_vector))
+
+        . = ALIGN(16);
+        __vector_ram_end__ = .;
+    } > ILM
+
+    .fast : AT(__fast_load_addr__) {
+        . = ALIGN(16);
+        __ramfunc_start__ = .;
+        *(.fast)
+        *(.fast.*)
+        . = ALIGN(16);
+
+        /* RT-Thread Core Start */
+        KEEP(*context_gcc.o(.text* .rodata*))
+        KEEP(*port*.o (.text .text* .rodata .rodata*))
+        KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*))
+        KEEP(*trap_common.o (.text .text* .rodata .rodata*))
+        KEEP(*irq.o (.text .text* .rodata .rodata*))
+        KEEP(*clock.o (.text .text* .rodata .rodata*))
+        KEEP(*kservice.o (.text .text* .rodata .rodata*))
+        KEEP(*scheduler*.o (.text .text* .rodata .rodata*))
+        KEEP(*trap*.o (.text .text* .rodata .rodata*))
+        KEEP(*idle.o (.text .text* .rodata .rodata*))
+        KEEP(*ipc.o (.text .text* .rodata .rodata*))
+        KEEP(*slab.o (.text .text* .rodata .rodata*))
+        KEEP(*thread.o (.text .text* .rodata .rodata*))
+        KEEP(*object.o (.text .text* .rodata .rodata*))
+        KEEP(*timer.o (.text .text* .rodata .rodata*))
+        KEEP(*mem.o (.text .text* .rodata .rodata*))
+        KEEP(*memheap.o (.text .text* .rodata .rodata*))
+        KEEP(*mempool.o (.text .text* .rodata .rodata*))
+        /* RT-Thread Core End */
+
+        /* HPMicro Driver Wrapper */
+        KEEP(*drv_*.o (.text .text* .rodata .rodata*))
+        KEEP(*api_lib*.o (.text .text* .rodata .rodata*))
+        KEEP(*api_msg*.o (.text .text* .rodata .rodata*))
+        KEEP(*if_api*.o (.text .text* .rodata .rodata*))
+        KEEP(*netbuf*.o (.text .text* .rodata .rodata*))
+        KEEP(*netdb*.o (.text .text* .rodata .rodata*))
+        KEEP(*netifapi*.o (.text .text* .rodata .rodata*))
+        KEEP(*sockets*.o (.text .text* .rodata .rodata*))
+        KEEP(*tcpip*.o (.text .text* .rodata .rodata*))
+        KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*))
+        KEEP(*memp*.o (.text .text* .rodata .rodata*))
+        KEEP(*netif*.o (.text .text* .rodata .rodata*))
+        KEEP(*pbuf*.o (.text .text* .rodata .rodata*))
+        KEEP(*tcp_in*.o (.text .text* .rodata .rodata*))
+        KEEP(*tcp_out*.o (.text .text* .rodata .rodata*))
+        KEEP(*tcp*.o (.text .text* .rodata .rodata*))
+        KEEP(*ethernet*.o (.text .text* .rodata .rodata*))
+        KEEP(*ethernetif*.o (.text .text* .rodata .rodata*))
+
+        . = ALIGN(16);
+        __ramfunc_end__ = .;
+    } > ILM
+
+    .text (__vector_load_addr__ + SIZEOF(.vectors)) : {
+        . = ALIGN(16);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+        /* section information for usbh class */
+        . = ALIGN(8);
+        __usbh_class_info_start__ = .;
+        KEEP(*(.usbh_class_info))
+        __usbh_class_info_end__ = .;
+
+    } > XPI0
+
+    .eh_frame :
+    {
+        __eh_frame_start = .;
+        KEEP(*(.eh_frame))
+        __eh_frame_end = .;
+    }  > XPI0
+
+    .eh_frame_hdr :
+    {
+        KEEP(*(.eh_frame_hdr))
+    }  > XPI0
+    __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0;
+    __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0;
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > XPI0
+
+    PROVIDE (__etext = .);
+    PROVIDE (_etext = .);
+    PROVIDE (etext = .);
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
+
+    __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
+        .fast_ram.init : AT(__fast_ram_init_load_addr__) {
+        . = ALIGN(8);
+        __fast_ram_init_start__ = .;
+        KEEP(*(.fast_ram.init))
+        KEEP(*(.fast_ram.init.*))
+        __fast_ram_init_end__ = .;
+        . = ALIGN(8);
+    } > DLM
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > AXI_SRAM
+
+    /* Note: the .tbss and .tdata section should be adjacent */
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.gnu.linkonce.tb.*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > AXI_SRAM
+
+    __tdata_load_addr__ = etext;
+    .tdata : AT(__tdata_load_addr__) {
+        . = ALIGN(8);
+        __tdata_start__ = .;
+        __thread_pointer = .;
+        *(.tdata)
+        *(.tdata*)
+        *(.gnu.linkonce.td.*)
+        . = ALIGN(8);
+        __tdata_end__ = .;
+    } > AXI_SRAM
+
+    __data_load_addr__ = etext + SIZEOF(.tdata);
+    .data : AT(__data_load_addr__) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_except_table))
+        KEEP(*(.gcc_except_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__fini_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE(__fini_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > AXI_SRAM
+    __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata);
+
+    __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr);
+
+    .heap(NOLOAD) : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+    } > AXI_SRAM
+
+    .framebuffer (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.framebuffer))
+        . = ALIGN(8);
+    } > AXI_SRAM
+
+    .stack(NOLOAD) : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        . = ALIGN(8);
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+        PROVIDE( __rt_rvstack = . );
+    } > AXI_SRAM
+
+    __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
+    .noncacheable.init : AT(__noncacheable_init_load_addr__) {
+        . = ALIGN(8);
+        __noncacheable_start__ = .;
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        . = ALIGN(8);
+    } > DLM
+
+    .noncacheable.bss (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.noncacheable))
+        KEEP(*(.noncacheable.non_init))
+        KEEP(*(.noncacheable.non_init.*))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        KEEP(*(.noncacheable.bss.*))
+        __noncacheable_bss_end__ = .;
+        __noncacheable_end__ = .;
+        . = ALIGN(8);
+    } > DLM
+
+    .ahb_sram (NOLOAD) : {
+        KEEP(*(.ahb_sram))
+    } > AHB_SRAM
+
+}

bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/ram_rtt.ld

@@ -0,0 +1,265 @@
+/*
+ * Copyright 2021-2025 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K;
+
+MEMORY
+{
+    ILM (wx) : ORIGIN = 0, LENGTH = 128K
+    DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K
+    AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 256K
+    AHB_SRAM (w) : ORIGIN = 0xF0200000, LENGTH = 32k
+}
+
+SECTIONS
+{
+    .start : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+    } > ILM
+
+    .vectors : {
+        . = ALIGN(8);
+        KEEP(*(.isr_vector))
+        KEEP(*(.vector_table))
+        . = ALIGN(8);
+    } > ILM
+
+    .text : {
+        . = ALIGN(8);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+        *(FalPartTable)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+        /* section information for usbh class */
+        . = ALIGN(8);
+        __usbh_class_info_start__ = .;
+        KEEP(*(.usbh_class_info))
+        __usbh_class_info_end__ = .;
+
+        PROVIDE (__etext = .);
+        PROVIDE (_etext = .);
+        PROVIDE (etext = .);
+    } > ILM
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > AXI_SRAM
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
+
+    __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
+    .fast_ram.init : AT(__fast_ram_init_load_addr__) {
+        . = ALIGN(8);
+        __fast_ram_init_start__ = .;
+        KEEP(*(.fast_ram.init))
+        KEEP(*(.fast_ram.init.*))
+        __fast_ram_init_end__ = .;
+        . = ALIGN(8);
+    } > DLM
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > DLM
+
+    /* Note: .tbss and .tdata should be adjacent */
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.gnu.linkonce.tb.*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > DLM
+
+    __tdata_load_addr__ = etext;
+    .tdata : AT(__tdata_load_addr__) {
+        . = ALIGN(8);
+        __tdata_start__ = .;
+        __thread_pointer = .;
+        *(.tdata)
+        *(.tdata*)
+        *(.gnu.linkonce.td.*)
+        . = ALIGN(8);
+        __tdata_end__ = .;
+    } > DLM
+
+
+    __data_load_addr__ = etext + SIZEOF(.tdata);
+    .data : AT(__data_load_addr__) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_except_table))
+        KEEP(*(.gcc_except_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__fini_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE(__fini_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > DLM
+
+    __fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data);
+    .fast : AT(__fast_load_addr__) {
+        . = ALIGN(8);
+        PROVIDE(__ramfunc_start__ = .);
+        *(.fast)
+        . = ALIGN(8);
+        PROVIDE(__ramfunc_end__ = .);
+    } > AXI_SRAM
+
+    __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
+    .noncacheable.init : AT(__noncacheable_init_load_addr__) {
+        . = ALIGN(8);
+        __noncacheable_start__ = .;
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        . = ALIGN(8);
+    } > DLM
+
+    .noncacheable.bss (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.noncacheable))
+        KEEP(*(.noncacheable.non_init))
+        KEEP(*(.noncacheable.non_init.*))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        KEEP(*(.noncacheable.bss.*))
+        __noncacheable_bss_end__ = .;
+        __noncacheable_end__ = .;
+        . = ALIGN(8);
+    } > DLM
+
+     .ahb_sram (NOLOAD) : {
+        KEEP(*(.ahb_sram))
+    } > AHB_SRAM
+
+    .stack(NOLOAD) : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+        PROVIDE (__rt_rvstack = .);
+    } > DLM
+
+    .framebuffer (NOLOAD) : {
+        KEEP(*(.framebuffer))
+    } > AXI_SRAM
+
+    .heap (NOLOAD) : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+
+    } > AXI_SRAM
+
+}

bsp/hpmicro/hpm5e00evk/board/pinmux.c

@@ -0,0 +1,640 @@
+/*
+ * Copyright (c) 2025 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*
+ * Note:
+ *   PY and PZ IOs: if any SOC pin function needs to be routed to these IOs,
+ *  besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that
+ *  expected SoC function can be enabled on these IOs.
+ *
+ */
+#include "board.h"
+
+void init_uart_pins(UART_Type *ptr)
+{
+    if (ptr == HPM_UART0) {
+        HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD;
+        HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD;
+    } else if (ptr == HPM_UART4) {
+        HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_UART4_TXD;
+        HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_UART4_RXD;
+    } else {
+        ;
+    }
+}
+
+void init_uart_pin_as_gpio(UART_Type *ptr)
+{
+    if (ptr == HPM_UART5) {
+        /* pull-up */
+        HPM_IOC->PAD[IOC_PAD_PC22].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+        HPM_IOC->PAD[IOC_PAD_PC23].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+
+        HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_GPIO_C_22;
+        HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_GPIO_C_23;
+    }
+}
+
+void init_i2c_pins(I2C_Type *ptr)
+{
+    if (ptr == HPM_I2C0) {
+#if 1
+        HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PC08].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+        HPM_IOC->PAD[IOC_PAD_PC09].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+#else
+        HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;    /* Codec0 */
+        HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PD09].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
+        HPM_IOC->PAD[IOC_PAD_PD08].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
+#endif
+    } else if (ptr == HPM_I2C1) { /* AT24C02 */
+    } else if (ptr == HPM_I2C2) { /* Codec1 */
+        HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_I2C2_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_I2C2_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PD03].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
+        HPM_IOC->PAD[IOC_PAD_PD02].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
+    } else {
+        ;
+    }
+}
+
+void init_ppi_pins(void)
+{
+    /* DQ Group A */
+    HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_PPI0_DQ_00;
+    HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_PPI0_DQ_01;
+    HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_PPI0_DQ_02;
+    HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_PPI0_DQ_03;
+    HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = IOC_PD27_FUNC_CTL_PPI0_DQ_04;
+    HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = IOC_PD26_FUNC_CTL_PPI0_DQ_05;
+    HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_PPI0_DQ_06;
+    HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PD25_FUNC_CTL_PPI0_DQ_07;
+    HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_PPI0_DQ_08;
+    HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = IOC_PD17_FUNC_CTL_PPI0_DQ_09;
+    HPM_IOC->PAD[IOC_PAD_PD16].FUNC_CTL = IOC_PD16_FUNC_CTL_PPI0_DQ_10;
+    HPM_IOC->PAD[IOC_PAD_PD19].FUNC_CTL = IOC_PD19_FUNC_CTL_PPI0_DQ_11;
+    HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = IOC_PD18_FUNC_CTL_PPI0_DQ_12;
+    HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = IOC_PD21_FUNC_CTL_PPI0_DQ_13;
+    HPM_IOC->PAD[IOC_PAD_PD20].FUNC_CTL = IOC_PD20_FUNC_CTL_PPI0_DQ_14;
+    HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = IOC_PD22_FUNC_CTL_PPI0_DQ_15;
+    HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_PPI0_DQ_16;
+    HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_PPI0_DQ_17;
+    HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_PPI0_DQ_18;
+    HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_PPI0_DQ_19;
+    HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_PPI0_DQ_20;
+    HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_PPI0_DQ_21;
+    HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_PPI0_DQ_22;
+    HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_PPI0_DQ_23;
+    HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_PPI0_DQ_24;
+    HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PC01_FUNC_CTL_PPI0_DQ_25;
+    HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_PPI0_DQ_26;
+    HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_PPI0_DQ_27;
+    HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_PPI0_DQ_28;
+    HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_PPI0_DQ_29;
+    HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_PPI0_DQ_30;
+    HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_PPI0_DQ_31;
+
+    /* Improve DQ pins driver strength */
+    HPM_IOC->PAD[IOC_PAD_PC16].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC16].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5);
+    HPM_IOC->PAD[IOC_PAD_PC17].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC17].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5);
+    HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5);
+    HPM_IOC->PAD[IOC_PAD_PC14].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC14].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5);
+    HPM_IOC->PAD[IOC_PAD_PC10].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC10].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5);
+    HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5);
+    HPM_IOC->PAD[IOC_PAD_PC02].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC02].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5);
+    HPM_IOC->PAD[IOC_PAD_PC09].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC09].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5);
+    HPM_IOC->PAD[IOC_PAD_PC00].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC00].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5);
+    HPM_IOC->PAD[IOC_PAD_PC01].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC01].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5);
+    HPM_IOC->PAD[IOC_PAD_PC03].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC03].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5);
+    HPM_IOC->PAD[IOC_PAD_PC04].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC04].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5);
+    HPM_IOC->PAD[IOC_PAD_PC05].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC05].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5);
+    HPM_IOC->PAD[IOC_PAD_PC06].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC06].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5);
+    HPM_IOC->PAD[IOC_PAD_PC07].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC07].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5);
+    HPM_IOC->PAD[IOC_PAD_PC08].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC08].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5);
+
+    /* DM Group A */
+    HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_PPI0_DM_0;
+    HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_PPI0_DM_1;
+    HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_PPI0_DM_2;
+    HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_PPI0_DM_3;
+
+    /* CS */
+    HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_PPI0_CS_0;
+    HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_PPI0_CS_1;
+    HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_PPI0_CS_2;
+    HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_PPI0_CS_3;
+
+    /* CTRL */
+    HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_PPI0_CTR_0;
+    HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_PPI0_CTR_1;
+    HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_PPI0_CTR_2;
+    HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_PPI0_CTR_3;
+    HPM_IOC->PAD[IOC_PAD_PE00].FUNC_CTL = IOC_PE00_FUNC_CTL_PPI0_CTR_4;
+    HPM_IOC->PAD[IOC_PAD_PE01].FUNC_CTL = IOC_PE01_FUNC_CTL_PPI0_CTR_5;
+    HPM_IOC->PAD[IOC_PAD_PE02].FUNC_CTL = IOC_PE02_FUNC_CTL_PPI0_CTR_6;
+    HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_PPI0_CTR_7;
+
+    /* CLK */
+    HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_PPI0_CLK;
+
+    /* DQ Group B */
+    /*
+     * HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_PPI0_DQ_00;
+     * HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_PPI0_DQ_01;
+     * HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_PPI0_DQ_02;
+     * HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_PPI0_DQ_03;
+     * HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_PPI0_DQ_04;
+     * HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_PPI0_DQ_05;
+     * HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_PPI0_DQ_06;
+     * HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_PPI0_DQ_07;
+     * HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_PPI0_DQ_08;
+     * HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_PPI0_DQ_09;
+     * HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_PPI0_DQ_10;
+     * HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_PPI0_DQ_11;
+     * HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_PPI0_DQ_12;
+     * HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_PPI0_DQ_13;
+     * HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_PPI0_DQ_14;
+     * HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_PPI0_DQ_15;
+     */
+
+    /* DM Group B */
+    /*
+     * HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_PPI0_DM_0;
+     * HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_PPI0_DM_1;
+     */
+}
+
+void init_sdm_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PF17].FUNC_CTL = IOC_PF17_FUNC_CTL_SDM0_CLK_0;
+    HPM_IOC->PAD[IOC_PAD_PF16].FUNC_CTL = IOC_PF16_FUNC_CTL_SDM0_DAT_0;
+}
+
+void init_pwm_pin_as_sdm_clock(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PF15].FUNC_CTL = IOC_PF15_FUNC_CTL_PWM1_P_7;
+}
+
+void init_gpio_pins(void)
+{
+    /* configure pad setting: pull enable and pull up, schmitt trigger enable */
+    /* enable schmitt trigger to eliminate jitter of pin used as button */
+
+    /* LED_G */
+    uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1);
+    HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_GPIO_C_28;
+    HPM_IOC->PAD[IOC_PAD_PC28].PAD_CTL = pad_ctl;
+
+    /* KEYA */
+    HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_GPIO_C_21;
+    HPM_IOC->PAD[IOC_PAD_PC21].PAD_CTL = pad_ctl;
+
+    /* KEYB */
+    HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_GPIO_C_25;
+    HPM_IOC->PAD[IOC_PAD_PC25].PAD_CTL = pad_ctl;
+}
+
+void init_spi_pins(SPI_Type *ptr)
+{
+    if (ptr == HPM_SPI1) {
+        HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_SPI1_CS_0;
+        HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
+        HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_SPI1_MISO;
+        HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_SPI1_MOSI;
+
+        /* set max frequency slew rate(200M) */
+        HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1);
+        HPM_IOC->PAD[IOC_PAD_PC10].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PC12].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+    } else {
+        ;
+    }
+}
+
+void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
+{
+    if (ptr == HPM_SPI1) {
+        HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_GPIO_C_11;
+        HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_SPI1_SCLK  | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
+        HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_SPI1_MISO;
+        HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_SPI1_MOSI;
+
+        /* set max frequency slew rate(200M) */
+        HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1);
+        HPM_IOC->PAD[IOC_PAD_PC10].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PC12].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+    }
+}
+
+void init_gptmr_pins(GPTMR_Type *ptr)
+{
+    trgm_output_t trgm0_io_config = {0};
+    if (ptr == HPM_GPTMR0) {
+        trgm0_io_config.invert = 0;
+        trgm0_io_config.type = trgm_output_same_as_input;
+
+        HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_TRGM_P_00;
+        trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_TRGM0_P00;
+        trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_GPTMR0_CAPT_2, &trgm0_io_config);
+
+        HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_TRGM_P_07;
+        trgm_enable_io_output(HPM_TRGM0, 1 << 7);
+        trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2;
+        trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_TRGM0_P07, &trgm0_io_config);
+
+        HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_TRGM_P_15;
+        trgm_enable_io_output(HPM_TRGM0, 1 << 15);
+        trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3;
+        trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_TRGM0_P15, &trgm0_io_config);
+    } else if (ptr == HPM_GPTMR1) {
+        HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_TRGM_P_03;
+        trgm_enable_io_output(HPM_TRGM0, 1 << 3);
+        trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2;
+        trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_TRGM0_P03, &trgm0_io_config);
+    }
+}
+
+void init_hall_trgm_pins(void)
+{
+    init_qeiv2_uvw_pins(BOARD_BLDC_QEIV2_BASE);
+}
+
+void init_qei_trgm_pins(void)
+{
+    init_qeiv2_ab_pins(BOARD_BLDC_QEIV2_BASE);
+}
+
+void init_butn_pins(void)
+{
+    /* configure pad setting: pull enable and pull up, schmitt trigger enable */
+    /* enable schmitt trigger to eliminate jitter of pin used as button */
+
+    /* Button */
+}
+
+void init_acmp_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PF26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* CMP1.INN6 */
+}
+
+void init_pwm_fault_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_TRGM_P_05;
+}
+
+void init_pwm_pins(PWMV2_Type *ptr)
+{
+    if (ptr == HPM_PWM0) {
+        HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_PWM0_P_0;
+        HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_PWM0_P_1;
+        HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_PWM0_P_2;
+        HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_PWM0_P_3;
+        HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_PWM0_P_4;
+        HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_PWM0_P_5;
+    } else {
+        ;
+    }
+}
+
+void init_usb_pins(USB_Type *ptr)
+{
+    if (ptr == HPM_USB0) {
+        /* USB0_ID */
+        HPM_IOC->PAD[IOC_PAD_PF22].FUNC_CTL = IOC_PF22_FUNC_CTL_USB0_ID;
+        /* USB0_OC */
+        HPM_IOC->PAD[IOC_PAD_PF23].FUNC_CTL = IOC_PF23_FUNC_CTL_USB0_OC;
+        /* USB0_PWR */
+        HPM_IOC->PAD[IOC_PAD_PF19].FUNC_CTL = IOC_PF19_FUNC_CTL_USB0_PWR;
+    }
+}
+
+void init_clk_obs_pins(void)
+{
+    /* HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; */
+}
+
+void init_qeo_pins(QEOV2_Type *ptr)
+{
+    if (ptr == HPM_QEO1) {
+        HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_QEO1_Z;
+        HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_QEO1_A;
+        HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_QEO1_B;
+    }
+}
+
+void init_qeiv2_uvw_pins(QEIV2_Type *ptr)
+{
+    if (ptr == HPM_QEI0) {
+        HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_QEI0_A;
+        HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_QEI0_B;
+        HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_QEI0_Z;
+    } else {
+    }
+}
+
+void init_qeiv2_ab_pins(QEIV2_Type *ptr)
+{
+    if (ptr == HPM_QEI0) {
+        HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_QEI0_A;
+        HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_QEI0_B;
+    } else {
+        ;
+    }
+}
+
+void init_qeiv2_abz_pins(QEIV2_Type *ptr)
+{
+    if (ptr == HPM_QEI0) {
+        HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_QEI0_A;
+        HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_QEI0_B;
+        HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_QEI0_Z;
+    } else {
+        ;
+    }
+}
+
+
+void init_enet_pins(ENET_Type *ptr)
+{
+    if (ptr == HPM_ENET0) {
+        HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_GPIO_C_19;
+
+        HPM_IOC->PAD[IOC_PAD_PF01].FUNC_CTL = IOC_PF01_FUNC_CTL_ETH0_MDIO;
+        HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_ETH0_MDC;
+
+        HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_ETH0_RXDV;
+        HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_ETH0_RXD_0;
+        HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_ETH0_RXD_1;
+        HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_ETH0_RXD_2;
+        HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_ETH0_RXD_3;
+        HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_ETH0_RXCK;
+
+        HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_ETH0_TXCK;
+        HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_ETH0_TXD_0;
+        HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_ETH0_TXD_1;
+        HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_ETH0_TXD_2;
+        HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_ETH0_TXD_3;
+        HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_ETH0_TXEN;
+    }
+}
+
+void init_enet_pps_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PF18].FUNC_CTL = IOC_PF18_FUNC_CTL_ETH0_EVTO_0;
+}
+
+void init_adc16_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PF26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+}
+
+void init_owr_pins(OWR_Type *ptr)
+{
+    (void) ptr;
+
+    HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_OWR0_DAT;
+}
+
+void init_adc_bldc_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PF28].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+    HPM_IOC->PAD[IOC_PAD_PF29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+}
+
+void init_adc_qeiv2_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PF30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;        /* ADC_IW: ADC0.6 / ADC1.6 : cos_ch  */
+    HPM_IOC->PAD[IOC_PAD_PF28].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;        /* ADC_IU: ADC0.5 / ADC1.5 : sin_ch  */
+}
+
+void init_can_pins(MCAN_Type *ptr)
+{
+   if (ptr == HPM_MCAN1) {
+        HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_MCAN1_TXD;
+        HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_MCAN1_RXD;
+        HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_MCAN1_STBY;
+    } else {
+        /* Invalid CAN instance */
+    }
+}
+
+void init_led_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09;
+}
+
+void init_led_pins_as_gpio(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09;
+}
+
+void init_led_pins_as_pwm(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_TRGM_P_09;
+}
+
+void init_plb_ab_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_TRGM_P_05;
+    HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_TRGM_P_06;
+    HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_TRGM_P_07;
+}
+
+void init_plb_lin_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_TRGM_P_05;
+}
+
+void init_plb_pulse_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_TRGM_P_05;
+}
+
+void init_plb_filter_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PD02].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0);
+    HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_TRGM_P_02;
+    HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_TRGM_P_04;
+}
+
+/* Pin configuration is required when ESC use actual eeprom devices */
+void init_esc_eeprom_pin(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_ESC0_SCL;
+    HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_ESC0_SDA;
+}
+
+/* Pin configuration is required when ESC use actual eeprom devices, use i2c peripheral init eeprom content */
+void init_esc_eeprom_as_i2c_pin(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+    HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+    HPM_IOC->PAD[IOC_PAD_PD08].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+    HPM_IOC->PAD[IOC_PAD_PD09].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+}
+
+void init_esc_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_ESC0_REFCK;
+    HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_ESC0_MDIO;
+    HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_ESC0_MDC;
+
+    /* ESC needs to configure these pins for specific functions, see ESC IOCFG registers */
+    HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_GPIO_B_24;  /* GPIO to reset PHY */
+    HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_ESC0_CTR_2; /* NMII_LINK0 function */
+    HPM_IOC->PAD[IOC_PAD_PC20].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); /* Internally pull up to avoid suspension */
+    HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_ESC0_CTR_5; /* NMII_LINK1 function */
+    HPM_IOC->PAD[IOC_PAD_PB25].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); /* Internally pull up to avoid suspension */
+    HPM_IOC->PAD[IOC_PAD_PE02].FUNC_CTL = IOC_PE02_FUNC_CTL_ESC0_CTR_6; /* NMII_LINK2 function */
+    HPM_IOC->PAD[IOC_PAD_PE02].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); /* Internally pull up to avoid suspension */
+
+    /* ESC port0 */
+    HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_ESC0_P0_TXCK;
+    HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_ESC0_P0_TXEN;
+    HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_ESC0_P0_TXD_0;
+    HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_ESC0_P0_TXD_1;
+    HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_ESC0_P0_TXD_2;
+    HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_ESC0_P0_TXD_3;
+    HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_ESC0_P0_RXCK;
+    HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_ESC0_P0_RXDV;
+    HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_ESC0_P0_RXER;
+    HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_ESC0_P0_RXD_0;
+    HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_ESC0_P0_RXD_1;
+    HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_ESC0_P0_RXD_2;
+    HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_ESC0_P0_RXD_3;
+
+    /* ESC port1 */
+    HPM_IOC->PAD[IOC_PAD_PF02].FUNC_CTL = IOC_PF02_FUNC_CTL_ESC0_P1_TXCK;
+    HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_ESC0_P1_TXEN;
+    HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_ESC0_P1_TXD_0;
+    HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_ESC0_P1_TXD_1;
+    HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_ESC0_P1_TXD_2;
+    HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_ESC0_P1_TXD_3;
+    HPM_IOC->PAD[IOC_PAD_PF13].FUNC_CTL = IOC_PF13_FUNC_CTL_ESC0_P1_RXCK;
+    HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_ESC0_P1_RXDV;
+    HPM_IOC->PAD[IOC_PAD_PF14].FUNC_CTL = IOC_PF14_FUNC_CTL_ESC0_P1_RXER;
+    HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_ESC0_P1_RXD_0;
+    HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_ESC0_P1_RXD_1;
+    HPM_IOC->PAD[IOC_PAD_PF11].FUNC_CTL = IOC_PF11_FUNC_CTL_ESC0_P1_RXD_2;
+    HPM_IOC->PAD[IOC_PAD_PF12].FUNC_CTL = IOC_PF12_FUNC_CTL_ESC0_P1_RXD_3;
+
+    /* ESC port2 */
+    HPM_IOC->PAD[IOC_PAD_PD16].FUNC_CTL = IOC_PD16_FUNC_CTL_ESC0_P2_RXDV;
+    HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = IOC_PD17_FUNC_CTL_ESC0_P2_RXD_0;
+    HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = IOC_PD18_FUNC_CTL_ESC0_P2_RXD_1;
+    HPM_IOC->PAD[IOC_PAD_PD19].FUNC_CTL = IOC_PD19_FUNC_CTL_ESC0_P2_RXD_2;
+    HPM_IOC->PAD[IOC_PAD_PD20].FUNC_CTL = IOC_PD20_FUNC_CTL_ESC0_P2_RXD_3;
+    HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = IOC_PD21_FUNC_CTL_ESC0_P2_RXCK;
+    HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = IOC_PD22_FUNC_CTL_ESC0_P2_RXER;
+    HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_ESC0_P2_TXCK;
+    HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_ESC0_P2_TXD_0;
+    HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PD25_FUNC_CTL_ESC0_P2_TXD_1;
+    HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = IOC_PD26_FUNC_CTL_ESC0_P2_TXD_2;
+    HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = IOC_PD27_FUNC_CTL_ESC0_P2_TXD_3;
+    HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_ESC0_P2_TXEN;
+}
+
+/* ESC input/output demo pins */
+void init_esc_in_out_pin(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_GPIO_D_06;
+    HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_GPIO_D_12;
+
+    HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_GPIO_C_23;
+    HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_GPIO_C_24;
+}
+
+/* for uart_rx_line_status case, need to a gpio pin to sent break signal */
+void init_uart_break_signal_pin(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PD13].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+    HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_GPIO_D_13;
+}
+
+void init_eui_pins(EUI_Type *ptr)
+{
+    if (ptr == HPM_EUI1) {
+        HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_EUI1_CK;
+        HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_EUI1_SH;
+        HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PB28_FUNC_CTL_EUI1_DI;
+        HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_EUI1_DO;
+    } else {
+        ;
+    }
+}
+
+void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp)
+{
+    trgm_output_t trgm0_io_config = {0};
+    if (ptr == HPM_GPTMR0) {
+        if (as_comp == true) {
+            if (channel == 2) {
+                HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_TRGM_P_07;
+                trgm_enable_io_output(HPM_TRGM0, 1 << 7);
+                trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2;
+                trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_TRGM0_P07, &trgm0_io_config);
+            } else if (channel == 3) {
+                HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_TRGM_P_15;
+                trgm_enable_io_output(HPM_TRGM0, 1 << 15);
+                trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3;
+                trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_TRGM0_P15, &trgm0_io_config);
+            } else {
+                ;
+            }
+        } else {
+            if (channel == 2) {
+                HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_TRGM_P_00;
+                trgm0_io_config.invert = 0;
+                trgm0_io_config.type = trgm_output_same_as_input;
+                trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_TRGM0_P00;
+                trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_GPTMR0_CAPT_2, &trgm0_io_config);
+            } else if (channel == 3) {
+                HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_TRGM_P_08;
+                trgm0_io_config.invert = 0;
+                trgm0_io_config.type = trgm_output_same_as_input;
+                trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_TRGM0_P08;
+                trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_GPTMR0_CAPT_3, &trgm0_io_config);
+            } else {
+                ;
+            }
+        }
+    } else if (ptr == HPM_GPTMR1) {
+        if (as_comp == true) {
+            if (channel == 2) {
+                HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_TRGM_P_03;
+                trgm_enable_io_output(HPM_TRGM0, 1 << 3);
+                trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2;
+                trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_TRGM0_P03, &trgm0_io_config);
+            }
+        } else {
+            if (channel == 2) {
+                HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_TRGM_P_00;
+                trgm0_io_config.invert = 0;
+                trgm0_io_config.type = trgm_output_same_as_input;
+                trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_TRGM0_P00;
+                trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_GPTMR1_CAPT_2, &trgm0_io_config);
+            } else if (channel == 3) {
+                HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_TRGM_P_08;
+                trgm0_io_config.invert = 0;
+                trgm0_io_config.type = trgm_output_same_as_input;
+                trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_TRGM0_P08;
+                trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_GPTMR1_CAPT_3, &trgm0_io_config);
+            } else {
+                ;
+            }
+        }
+    }
+}
+
+void init_clk_ref_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_SOC_REF1;
+}

bsp/hpmicro/hpm5e00evk/board/pinmux.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2025 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef HPM_PINMUX_H
+#define HPM_PINMUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void init_uart_pins(UART_Type *ptr);
+void init_uart_pin_as_gpio(UART_Type *ptr);
+void init_i2c_pins(I2C_Type *ptr);
+void init_ppi_pins(void);
+void init_sdm_pins(void);
+void init_pwm_pin_as_sdm_clock(void);
+void init_gpio_pins(void);
+void init_spi_pins(SPI_Type *ptr);
+void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr);
+void init_gptmr_pins(GPTMR_Type *ptr);
+void init_hall_trgm_pins(void);
+void init_qei_trgm_pins(void);
+void init_butn_pins(void);
+void init_acmp_pins(void);
+void init_pwm_pins(PWMV2_Type *ptr);
+void init_usb_pins(USB_Type *ptr);
+void init_qeo_pins(QEOV2_Type *ptr);
+void init_qeiv2_uvw_pins(QEIV2_Type *ptr);
+void init_qeiv2_ab_pins(QEIV2_Type *ptr);
+void init_qeiv2_abz_pins(QEIV2_Type *ptr);
+void init_enet_pins(ENET_Type *ptr);
+void init_enet_pps_pins(void);
+void init_adc16_pins(void);
+void init_adc_bldc_pins(void);
+void init_adc_qeiv2_pins(void);
+void init_can_pins(MCAN_Type *ptr);
+void init_led_pins(void);
+void init_led_pins_as_gpio(void);
+void init_led_pins_as_pwm(void);
+void init_plb_ab_pins(void);
+void init_plb_pulse_pins(void);
+void init_plb_filter_pins(void);
+void init_plb_lin_pins(void);
+void init_esc_pins(void);
+void init_esc_in_out_pin(void);
+void init_eui_pins(EUI_Type *ptr);
+void init_uart_break_signal_pin(void);
+void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp);
+void init_owr_pins(OWR_Type *ptr);
+void init_clk_ref_pins(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* HPM_PINMUX_H */

bsp/hpmicro/hpm5e00evk/board/rtt_board.c

@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2023-2024 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "board.h"
+#include "rtt_board.h"
+#include "hpm_uart_drv.h"
+#include "hpm_gpio_drv.h"
+#include "hpm_pmp_drv.h"
+#include "assert.h"
+#include "hpm_clock_drv.h"
+#include "hpm_sysctl_drv.h"
+#include <rthw.h>
+#include <rtthread.h>
+#include "hpm_dma_mgr.h"
+#include "hpm_mchtmr_drv.h"
+
+extern int rt_hw_uart_init(void);
+void os_tick_config(void);
+void rtt_board_init(void);
+
+void rt_hw_board_init(void)
+{
+    rtt_board_init();
+
+    /* Call the RT-Thread Component Board Initialization */
+    rt_components_board_init();
+}
+
+void os_tick_config(void)
+{
+    sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1);
+    sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0);
+    mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND);
+    enable_mchtmr_irq();
+}
+
+void rtt_board_init(void)
+{
+    board_init_clock();
+    board_init_console();
+    board_init_pmp();
+
+    dma_mgr_init();
+
+    /* initialize memory system */
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+
+    /* Configure the OS Tick */
+    os_tick_config();
+
+    /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */
+    rt_hw_uart_init();
+
+    /* Set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
+
+void app_init_led_pins(void)
+{
+    board_init_led_pins();
+    gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN);
+
+    gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, APP_LED_OFF);
+}
+
+void app_led_write(uint32_t index, bool state)
+{
+    switch (index)
+    {
+    case 0:
+        gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, state);
+        break;
+    default:
+        /* Suppress the toolchain warnings */
+        break;
+    }
+}
+
+void rt_hw_console_output(const char *str)
+{
+    while (*str != '\0')
+    {
+        uart_send_byte(BOARD_APP_UART_BASE, *str++);
+    }
+}
+
+void app_init_usb_pins(void)
+{
+    board_init_usb(HPM_USB0);
+}
+
+ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
+{
+    HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND;
+
+    rt_tick_increase();
+}
+
+void rt_hw_cpu_reset(void)
+{
+    HPM_PPOR->RESET_ENABLE |= (1UL << 31);
+    HPM_PPOR->SOFTWARE_RESET = 1000U;
+    while(1) {
+
+    }
+}
+
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);
+
+#ifdef RT_USING_CACHE
+void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
+{
+    if (ops == RT_HW_CACHE_FLUSH) {
+        l1c_dc_flush((uint32_t)addr, size);
+    } else {
+        l1c_dc_invalidate((uint32_t)addr, size);
+    }
+}
+#endif
+
+uint32_t rtt_board_init_adc16_clock(void *ptr, bool clk_src_ahb)  /* motor system should be use clk_adc_src_ahb0 */
+{
+    uint32_t freq = 0;
+
+    if (ptr == (void *)HPM_ADC0) {
+        clock_add_to_group(clock_adc0, 0);
+        if (clk_src_ahb) {
+            /* Configure the ADC clock from AHB (@200MHz by default)*/
+            clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
+        } else {
+            /* Configure the ADC clock from ANA (@200MHz by default)*/
+            clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
+            clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U);
+        }
+        freq = clock_get_frequency(clock_adc0);
+    } else if (ptr == (void *)HPM_ADC1) {
+        clock_add_to_group(clock_adc1, 0);
+        if (clk_src_ahb) {
+            /* Configure the ADC clock from AHB (@200MHz by default)*/
+            clock_set_adc_source(clock_adc1, clk_adc_src_ahb0);
+        } else {
+            /* Configure the ADC clock from ANA (@200MHz by default)*/
+            clock_set_adc_source(clock_adc1, clk_adc_src_ana1);
+            clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U);
+        }
+        freq = clock_get_frequency(clock_adc1);
+    } else {
+        ;
+    }
+
+    return freq;
+}
+
+uint32_t rtt_board_init_pwm_clock(PWMV2_Type *ptr)
+{
+    uint32_t freq = 0;
+    if (ptr == HPM_PWM0) {
+        clock_add_to_group(clock_pwm0, 0);
+        freq = clock_get_frequency(clock_pwm0);
+    } else if (ptr == HPM_PWM1) {
+        clock_add_to_group(clock_pwm1, 0);
+        freq = clock_get_frequency(clock_pwm1);
+    } else {
+
+    }
+    return freq;
+}
+
+#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER
+extern void hpm_isr_usb0(void);
+RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0)
+#endif

bsp/hpmicro/hpm5e00evk/board/rtt_board.h

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2021 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _RTT_BOARD_H
+#define _RTT_BOARD_H
+#include "hpm_common.h"
+#include "hpm_soc.h"
+#include "board.h"
+
+/* gpio section */
+#define APP_LED0         (0U)
+#define APP_LED0_GPIO_CTRL HPM_GPIO0
+#define APP_LED0_GPIO_INDEX GPIO_DI_GPIOC
+#define APP_LED0_GPIO_PIN 28
+#define APP_LED_ON (1)
+#define APP_LED_OFF (0)
+
+
+
+/* mchtimer section */
+#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
+
+/* gptmr as os_tick */
+#define BOARD_OS_TIMER HPM_GPTMR0
+#define BOARD_OS_TIMER_CH       1
+#define BOARD_OS_TIMER_IRQ      IRQn_GPTMR0
+#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0)
+
+/* CAN section */
+#define BOARD_CAN_NAME                        "can1"
+#define BOARD_CAN_HWFILTER_INDEX               (1U)
+
+/* UART section */
+#define BOARD_UART_NAME                        "uart4"
+#define BOARD_UART_RX_BUFFER_SIZE              BSP_UART4_RX_BUFSIZE
+
+/* PWM section */
+#define BOARD_PWM_NAME                        "pwm0"
+#define BOARD_PWM_CHANNEL                     (0U)
+
+/* ADC section */
+#define BOARD_ADC_NAME                        BOARD_APP_ADC16_NAME
+#define BOARD_ADC_CHANNEL                     BOARD_APP_ADC16_CH_1
+
+#define IRQn_PendSV IRQn_DEBUG0
+
+#define BOARD_ENET0_INF             (1U)  /* 0: RMII, 1: RGMII */
+#define BOARD_ENET0_INT_REF_CLK     (0U)
+#define BOARD_ENET0_PHY_RST_TIME    (30)
+#if BOARD_ENET0_INF
+#define BOARD_ENET0_TX_DLY          (0U)
+#define BOARD_ENET0_RX_DLY          (0U)
+#endif
+#if defined(__USE_ENET_PTP) && __USE_ENET_PTP
+#define BOARD_ENET0_PTP_CLOCK       (clock_ptp0)
+#endif
+
+/***************************************************************
+ *
+ * RT-Thread related definitions
+ *
+ **************************************************************/
+extern unsigned int __heap_start__;
+extern unsigned int __heap_end__;
+
+#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__)
+#define RT_HW_HEAP_END ((void*)&__heap_end__)
+
+
+typedef struct {
+    uint16_t vdd;
+    uint8_t bus_width;
+    uint8_t drive_strength;
+}sdxc_io_cfg_t;
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+
+void app_init_led_pins(void);
+void app_led_write(uint32_t index, bool state);
+void app_init_usb_pins(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+#endif /* _RTT_BOARD_H */

bsp/hpmicro/hpm5e00evk/makefile.targets

@@ -0,0 +1,6 @@
+clean2:
+	-$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS)
+	-$(RM) $(OBJS) *.elf
+	-@echo ' '
+
+*.elf: $(wildcard ../linkscripts/*/*.lds) $(wildcard ../linkscripts/*/*/*.lds)

bsp/hpmicro/hpm5e00evk/rtconfig.h

@@ -0,0 +1,418 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* RT-Thread Kernel */
+
+/* klibc options */
+
+/* rt_vsnprintf options */
+
+/* end of rt_vsnprintf options */
+
+/* rt_vsscanf options */
+
+/* end of rt_vsscanf options */
+
+/* rt_memset options */
+
+/* end of rt_memset options */
+
+/* rt_memcpy options */
+
+/* end of rt_memcpy options */
+
+/* rt_memmove options */
+
+/* end of rt_memmove options */
+
+/* rt_memcmp options */
+
+/* end of rt_memcmp options */
+
+/* rt_strstr options */
+
+/* end of rt_strstr options */
+
+/* rt_strcasecmp options */
+
+/* end of rt_strcasecmp options */
+
+/* rt_strncpy options */
+
+/* end of rt_strncpy options */
+
+/* rt_strcpy options */
+
+/* end of rt_strcpy options */
+
+/* rt_strncmp options */
+
+/* end of rt_strncmp options */
+
+/* rt_strcmp options */
+
+/* end of rt_strcmp options */
+
+/* rt_strlen options */
+
+/* end of rt_strlen options */
+
+/* rt_strnlen options */
+
+/* end of rt_strnlen options */
+/* end of klibc options */
+#define RT_NAME_MAX 16
+#define RT_CPUS_NR 1
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 1024
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 1024
+#define RT_USING_CPU_USAGE_TRACER
+
+/* kservice options */
+
+/* end of kservice options */
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+/* end of Inter-Thread communication */
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+/* end of Memory Management */
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50201
+#define RT_BACKTRACE_LEVEL_MAX_NR 32
+/* end of RT-Thread Kernel */
+#define ARCH_RISCV
+#define ARCH_RISCV32
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_LEGACY
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+#define FINSH_USING_OPTION_COMPLETION
+
+/* DFS: device virtual file system */
+
+/* end of DFS: device virtual file system */
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V2
+#define RT_SERIAL_BUF_STRATEGY_OVERWRITE
+#define RT_SERIAL_USING_DMA
+#define RT_USING_PIN
+/* end of Device Drivers */
+
+/* C/C++ and POSIX layer */
+
+/* ISO-ANSI C layer */
+
+/* Timezone and Daylight Saving Time */
+
+#define RT_LIBC_USING_LIGHT_TZ_DST
+#define RT_LIBC_TZ_DEFAULT_HOUR 8
+#define RT_LIBC_TZ_DEFAULT_MIN 0
+#define RT_LIBC_TZ_DEFAULT_SEC 0
+/* end of Timezone and Daylight Saving Time */
+/* end of ISO-ANSI C layer */
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+/* end of Interprocess Communication (IPC) */
+/* end of POSIX (Portable Operating System Interface) layer */
+/* end of C/C++ and POSIX layer */
+
+/* Network */
+
+/* end of Network */
+
+/* Memory protection */
+
+/* end of Memory protection */
+
+/* Utilities */
+
+/* end of Utilities */
+
+/* Using USB legacy version */
+
+/* end of Using USB legacy version */
+/* end of RT-Thread Components */
+
+/* RT-Thread Utestcases */
+
+/* end of RT-Thread Utestcases */
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+/* end of Marvell WiFi */
+
+/* Wiced WiFi */
+
+/* end of Wiced WiFi */
+
+/* CYW43012 WiFi */
+
+/* end of CYW43012 WiFi */
+
+/* BL808 WiFi */
+
+/* end of BL808 WiFi */
+
+/* CYW43439 WiFi */
+
+/* end of CYW43439 WiFi */
+/* end of Wi-Fi */
+
+/* IoT Cloud */
+
+/* end of IoT Cloud */
+/* end of IoT - internet of things */
+
+/* security packages */
+
+/* end of security packages */
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+/* XML: Extensible Markup Language */
+
+/* end of XML: Extensible Markup Language */
+/* end of language packages */
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+/* end of LVGL: powerful and easy-to-use embedded GUI library */
+
+/* u8g2: a monochrome graphic library */
+
+/* end of u8g2: a monochrome graphic library */
+/* end of multimedia packages */
+
+/* tools packages */
+
+/* end of tools packages */
+
+/* system packages */
+
+/* enhanced kernel services */
+
+/* end of enhanced kernel services */
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+/* end of acceleration: Assembly language or algorithmic acceleration packages */
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+/* end of Micrium: Micrium software products porting for RT-Thread */
+/* end of system packages */
+
+/* peripheral libraries and drivers */
+
+/* HAL & SDK Drivers */
+
+/* STM32 HAL & SDK Drivers */
+
+/* end of STM32 HAL & SDK Drivers */
+
+/* Infineon HAL Packages */
+
+/* end of Infineon HAL Packages */
+
+/* Kendryte SDK */
+
+/* end of Kendryte SDK */
+
+/* WCH HAL & SDK Drivers */
+
+/* end of WCH HAL & SDK Drivers */
+
+/* AT32 HAL & SDK Drivers */
+
+/* end of AT32 HAL & SDK Drivers */
+
+/* HC32 DDL Drivers */
+
+/* end of HC32 DDL Drivers */
+
+/* NXP HAL & SDK Drivers */
+
+/* end of NXP HAL & SDK Drivers */
+
+/* NUVOTON Drivers */
+
+/* end of NUVOTON Drivers */
+
+/* GD32 Drivers */
+
+/* end of GD32 Drivers */
+
+/* HPMicro SDK */
+
+#define PKG_USING_HPM_SDK
+#define PKG_USING_HPM_SDK_LATEST_VERSION
+/* end of HPMicro SDK */
+/* end of HAL & SDK Drivers */
+
+/* sensors drivers */
+
+/* end of sensors drivers */
+
+/* touch drivers */
+
+/* end of touch drivers */
+/* end of peripheral libraries and drivers */
+
+/* AI packages */
+
+/* end of AI packages */
+
+/* Signal Processing and Control Algorithm Packages */
+
+/* end of Signal Processing and Control Algorithm Packages */
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* end of project laboratory */
+
+/* samples: kernel and components samples */
+
+/* end of samples: kernel and components samples */
+
+/* entertainment: terminal games and other interesting software packages */
+
+/* end of entertainment: terminal games and other interesting software packages */
+/* end of miscellaneous packages */
+
+/* Arduino libraries */
+
+
+/* Projects and Demos */
+
+/* end of Projects and Demos */
+
+/* Sensors */
+
+/* end of Sensors */
+
+/* Display */
+
+/* end of Display */
+
+/* Timing */
+
+/* end of Timing */
+
+/* Data Processing */
+
+/* end of Data Processing */
+
+/* Data Storage */
+
+/* Communication */
+
+/* end of Communication */
+
+/* Device Control */
+
+/* end of Device Control */
+
+/* Other */
+
+/* end of Other */
+
+/* Signal IO */
+
+/* end of Signal IO */
+
+/* Uncategorized */
+
+/* end of Arduino libraries */
+/* end of RT-Thread online packages */
+#define SOC_HPM5E00_SERIES
+
+/* Hardware Drivers Config */
+
+#define SOC_HPM5E00
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_GPIO_IRQ_PRIORITY 1
+#define BSP_USING_UART
+#define BSP_USING_UART0
+#define BSP_UART0_RX_BUFSIZE 128
+#define BSP_UART0_TX_BUFSIZE 0
+#define BSP_UART0_IRQ_PRIORITY 1
+/* end of On-chip Peripheral Drivers */
+/* end of Hardware Drivers Config */
+
+#endif

bsp/hpmicro/hpm5e00evk/rtconfig.py

@@ -0,0 +1,150 @@
+# Copyright 2021-2025 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+import os
+import sys
+import rtconfig
+
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+def bsp_pkg_check():
+    import subprocess
+    
+    need_update = True
+    for p in os.listdir("packages"):
+        if p.startswith("hpm_sdk-"):
+            need_update = False
+            break
+    if need_update:
+        print("\n===============================================================================")
+        print("Dependency packages missing, please running 'pkgs --update'...")
+        print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
+        print("===============================================================================")
+        exit(1)
+
+RegisterPreBuildingAction(bsp_pkg_check)
+
+
+# toolchains options
+ARCH='risc-v'
+CPU='hpmicro'
+SOC_FAMILY='HPM5E00'
+CHIP_NAME='HPM5E31'
+
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+# Fallback toolchain info
+FALLBACK_TOOLCHAIN_VENDOR='RISC-V'
+FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32'
+FALLBACK_TOOLCHAIN_VER='2022-04-12'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+if RTT_EXEC_PATH != None:
+    folders = RTT_EXEC_PATH.split(os.sep)
+    # If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO`
+    if 'arm_gcc' in folders and 'platform' in folders:
+        RTT_EXEC_PATH = ''
+        for path in folders:
+            if path != 'platform':
+                RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep
+            else:
+                break
+        RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin')
+    # Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio
+    if 'platform' in folders:
+        os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    if os.getenv('RTT_RISCV_TOOLCHAIN'):
+        EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN')
+    else:
+        EXEC_PATH   = r'/opt/riscv-gnu-gcc/bin'
+else:
+    print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
+
+BUILD = 'flash_debug'
+
+if PLATFORM == 'gcc':
+    PREFIX = 'riscv32-unknown-elf-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    GDB = PREFIX + 'gdb'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    STRIP = PREFIX + 'strip'
+
+    ARCH_ABI = ' -mcmodel=medlow '
+    DEVICE = ARCH_ABI  + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common '
+    CFLAGS = DEVICE
+    AFLAGS = CFLAGS
+    LFLAGS  = ARCH_ABI + '  --specs=nano.specs --specs=nosys.specs  -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections '
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'ram_debug':
+        CFLAGS += ' -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -O0'
+        LFLAGS += ' -O0'
+        LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld'
+    elif BUILD == 'ram_release':
+        CFLAGS += ' -O2'
+        LFLAGS += ' -O2'
+        LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld'
+    elif BUILD == 'flash_debug':
+        CFLAGS += ' -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -O0'
+        LFLAGS += ' -O0'
+        CFLAGS += ' -DFLASH_XIP=1'
+        LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
+    elif BUILD == 'flash_release':
+        CFLAGS += ' -O2'
+        LFLAGS += ' -O2'
+        CFLAGS += ' -DFLASH_XIP=1'
+        LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
+    else:
+        CFLAGS += ' -O2'
+        LFLAGS += ' -O2'
+        LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
+    LFLAGS += ' -T ' + LINKER_FILE
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+    # module setting
+    CXXFLAGS = CFLAGS +  ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
+    CFLAGS = CFLAGS + ' -std=gnu11'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)

bsp/hpmicro/hpm5e00evk/rtconfig_preinc.h

@@ -0,0 +1,18 @@
+
+#ifndef RTCONFIG_PREINC_H__
+#define RTCONFIG_PREINC_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread pre-include file */
+
+#define D45
+#define HPM6880
+#define HPM6E80
+#define HPMSOC_HAS_HPMSDK_DMAV2
+#define RT_USING_LIBC
+#define RT_USING_NEWLIBC
+#define _POSIX_C_SOURCE 1
+#define _REENT_SMALL
+#define __RTTHREAD__
+
+#endif /*RTCONFIG_PREINC_H__*/

bsp/hpmicro/hpm5e00evk/startup/HPM5E31/SConscript

@@ -0,0 +1,19 @@
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the startup files
+
+src = Glob('*.c')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += [os.path.join('toolchains', 'gcc', 'start.S')]
+    src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')]
+
+CPPPATH = [cwd]
+CPPDEFINES=['D45', rtconfig.CHIP_NAME]
+
+group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/hpmicro/hpm5e00evk/startup/HPM5E31/startup.c

@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2021-2024 HPMicro
+ *
+ *
+ */
+
+#include "hpm_common.h"
+#include "hpm_soc.h"
+#include "hpm_l1c_drv.h"
+#include <rtthread.h>
+
+void system_init(void);
+
+extern int entry(void);
+
+extern void __libc_init_array(void);
+extern void __libc_fini_array(void);
+
+void system_init(void)
+{
+    disable_global_irq(CSR_MSTATUS_MIE_MASK);
+    disable_irq_from_intc();
+    enable_irq_from_intc();
+    enable_global_irq(CSR_MSTATUS_MIE_MASK);
+#ifndef CONFIG_NOT_ENABLE_ICACHE
+    l1c_ic_enable();
+#endif
+#ifndef CONFIG_NOT_ENABLE_DCACHE
+    l1c_dc_enable();
+#endif
+}
+
+__attribute__((weak)) void c_startup(void)
+{
+#ifndef __SES_RISCV
+    uint32_t i, size;
+#ifdef FLASH_XIP
+    extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
+    size = __vector_ram_end__ - __vector_ram_start__;
+    for (i = 0; i < size; i++) {
+        *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
+    }
+#endif
+
+    extern uint8_t __etext[];
+    extern uint8_t __bss_start__[], __bss_end__[];
+    extern uint8_t __tbss_start__[], __tbss_end__[];
+    extern uint8_t __tdata_start__[], __tdata_end__[];
+    extern uint8_t __fast_load_addr__[];
+    extern uint8_t __noncacheable_init_load_addr__[];
+    extern uint8_t __data_load_addr__[];
+    extern uint8_t __tdata_load_addr__[];
+    extern uint8_t __data_start__[], __data_end__[];
+    extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
+    extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
+    extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
+
+    /* tbss section */
+    size = __tbss_end__ - __tbss_start__;
+    for (i = 0; i < size; i++) {
+        *(__tbss_start__ + i) = 0;
+    }
+
+    /* bss section */
+    size = __bss_end__ - __bss_start__;
+    for (i = 0; i < size; i++) {
+        *(__bss_start__ + i) = 0;
+    }
+
+    /* noncacheable bss section */
+    size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
+    for (i = 0; i < size; i++) {
+        *(__noncacheable_bss_start__ + i) = 0;
+    }
+
+    /* tdata section LMA: etext */
+    size = __tdata_end__ - __tdata_start__;
+    for (i = 0; i < size; i++) {
+        *(__tdata_start__ + i) = *(__tdata_load_addr__ + i);
+    }
+
+    /* data section LMA: etext */
+    size = __data_end__ - __data_start__;
+    for (i = 0; i < size; i++) {
+        *(__data_start__ + i) = *(__data_load_addr__ + i);
+    }
+
+    /* ramfunc section LMA: etext + data length */
+    size = __ramfunc_end__ - __ramfunc_start__;
+    for (i = 0; i < size; i++) {
+        *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i);
+    }
+
+    /* noncacheable init section LMA: etext + data length + ramfunc length */
+    size = __noncacheable_init_end__ - __noncacheable_init_start__;
+    for (i = 0; i < size; i++) {
+        *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i);
+    }
+#endif
+}
+
+__attribute__((weak)) int main(void)
+{
+    while(1);
+}
+
+void reset_handler(void)
+{
+    /**
+     * Disable preemptive interrupt
+     */
+    HPM_PLIC->FEATURE = 0;
+    /*
+     * Initialize LMA/VMA sections.
+     * Relocation for any sections that need to be copied from LMA to VMA.
+     */
+    c_startup();
+
+    /* Call platform specific hardware initialization */
+    system_init();
+
+#ifndef __SES_RISCV
+    /* Do global constructors */
+    __libc_init_array();
+#endif
+
+    /* Entry function */
+    entry();
+}
+
+
+__attribute__((weak)) void _init(void)
+{
+}

bsp/hpmicro/hpm5e00evk/startup/HPM5E31/toolchains/gcc/port_gcc.S

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2021-2023 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include "cpuport.h"
+    .section .text.entry, "ax"
+    .align  2
+    .globl rt_hw_do_after_save_above
+    .type rt_hw_do_after_save_above,@function
+rt_hw_do_after_save_above:
+    addi  sp, sp,  -4
+    STORE ra,  0 * REGBYTES(sp)
+
+    csrr    t1, mcause
+    andi    t1, t1, 0x3FF
+    /* get ISR */
+    la      t2, trap_entry
+    jalr    t2
+
+    LOAD  ra,  0 * REGBYTES(sp)
+    addi  sp, sp,  4
+    ret

bsp/hpmicro/hpm5e00evk/startup/HPM5E31/toolchains/gcc/start.S

@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2021-2023 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+ #include <rtconfig.h>
+ #include "hpm_csr_regs.h"
+    .section .start, "ax"
+
+    .global _start
+    .type _start,@function
+
+_start:
+    /* Initialize global pointer */
+    .option push
+    .option norelax
+    la gp, __global_pointer$
+    la tp, __thread_pointer
+    .option pop
+
+#ifdef __riscv_flen
+    /* Enable FPU */
+    li t0, CSR_MSTATUS_FS_MASK
+    csrrs t0, mstatus, t0
+
+    /* Initialize FCSR */
+    fscsr zero
+#endif
+
+#ifdef INIT_EXT_RAM_FOR_DATA
+    la t0, _stack_in_dlm
+    mv sp, t0
+    call _init_ext_ram
+#endif
+
+    /* Initialize stack pointer */
+    la t0, _stack
+    mv sp, t0
+
+#ifdef __nds_execit
+    /* Initialize EXEC.IT table */
+    la t0, _ITB_BASE_
+    csrw uitb, t0
+#endif
+
+#ifdef __riscv_flen
+    /* Enable FPU */
+    li t0, CSR_MSTATUS_FS_MASK
+    csrrs t0, mstatus, t0
+
+    /* Initialize FCSR */
+    fscsr zero
+#endif
+
+#ifdef HPM_USING_VECTOR_PREEMPTED_MODE
+    /* Initial machine trap-vector Base */
+    la t0, __vector_table
+    csrw mtvec, t0
+    /* Enable vectored external PLIC interrupt */
+    csrsi CSR_MMISC_CTL, 2
+#else
+    /* Initial machine trap-vector Base */
+    la t0, SW_handler
+    csrw mtvec, t0
+    /* Disable vectored external PLIC interrupt */
+    csrci CSR_MMISC_CTL, 2
+#endif
+
+    /* System reset handler */
+    call reset_handler
+
+    /* Infinite loop, if returned accidently */
+1:    j 1b
+
+    .weak nmi_handler
+nmi_handler:
+1:    j 1b
+
+    .weak default_irq_handler
+    .align 2
+default_irq_handler:
+1:    j 1b
+
+    .macro IRQ_HANDLER irq
+    .weak default_isr_\irq
+    .set default_isr_\irq, default_irq_handler
+    .long default_isr_\irq
+    .endm
+
+#include "vectors.S"

bsp/hpmicro/hpm5e00evk/startup/HPM5E31/toolchains/gcc/vectors.S

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2021-2024 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+    .section .vector_table, "a"
+    .global __vector_table
+    .align 9
+__vector_table:
+    .weak default_isr_trap
+    .set default_isr_trap, SW_handler
+    .long default_isr_trap
+IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
+    IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
+    IRQ_HANDLER 3 /* GPIO0_C IRQ handler */
+    IRQ_HANDLER 4 /* GPIO0_D IRQ handler */
+    IRQ_HANDLER 5 /* GPIO0_E IRQ handler */
+    IRQ_HANDLER 6 /* GPIO0_F IRQ handler */
+    IRQ_HANDLER 7 /* GPIO0_V IRQ handler */
+    IRQ_HANDLER 8 /* GPIO0_W IRQ handler */
+    IRQ_HANDLER 9 /* GPIO0_X IRQ handler */
+    IRQ_HANDLER 10 /* GPIO0_Y IRQ handler */
+    IRQ_HANDLER 11 /* GPTMR0 IRQ handler */
+    IRQ_HANDLER 12 /* GPTMR1 IRQ handler */
+    IRQ_HANDLER 13 /* GPTMR2 IRQ handler */
+    IRQ_HANDLER 14 /* GPTMR3 IRQ handler */
+    IRQ_HANDLER 15 /* OWR0 IRQ handler */
+    IRQ_HANDLER 16 /* OWR1 IRQ handler */
+    IRQ_HANDLER 17 /* EUI0 IRQ handler */
+    IRQ_HANDLER 18 /* EUI1 IRQ handler */
+    IRQ_HANDLER 19 /* UART0 IRQ handler */
+    IRQ_HANDLER 20 /* UART1 IRQ handler */
+    IRQ_HANDLER 21 /* UART2 IRQ handler */
+    IRQ_HANDLER 22 /* UART3 IRQ handler */
+    IRQ_HANDLER 23 /* UART4 IRQ handler */
+    IRQ_HANDLER 24 /* UART5 IRQ handler */
+    IRQ_HANDLER 25 /* UART6 IRQ handler */
+    IRQ_HANDLER 26 /* UART7 IRQ handler */
+    IRQ_HANDLER 27 /* I2C0 IRQ handler */
+    IRQ_HANDLER 28 /* I2C1 IRQ handler */
+    IRQ_HANDLER 29 /* I2C2 IRQ handler */
+    IRQ_HANDLER 30 /* I2C3 IRQ handler */
+    IRQ_HANDLER 31 /* SPI0 IRQ handler */
+    IRQ_HANDLER 32 /* SPI1 IRQ handler */
+    IRQ_HANDLER 33 /* SPI2 IRQ handler */
+    IRQ_HANDLER 34 /* SPI3 IRQ handler */
+    IRQ_HANDLER 35 /* TSNS IRQ handler */
+    IRQ_HANDLER 36 /* MBX0A IRQ handler */
+    IRQ_HANDLER 37 /* MBX0B IRQ handler */
+    IRQ_HANDLER 38 /* EWDG0 IRQ handler */
+    IRQ_HANDLER 39 /* EWDG1 IRQ handler */
+    IRQ_HANDLER 40 /* HDMA IRQ handler */
+    IRQ_HANDLER 41 /* LOBS IRQ handler */
+    IRQ_HANDLER 42 /* ADC0 IRQ handler */
+    IRQ_HANDLER 43 /* ADC1 IRQ handler */
+    IRQ_HANDLER 44 /* ACMP0[0] IRQ handler */
+    IRQ_HANDLER 45 /* ACMP0[1] IRQ handler */
+    IRQ_HANDLER 46 /* MCAN0 IRQ handler */
+    IRQ_HANDLER 47 /* MCAN1 IRQ handler */
+    IRQ_HANDLER 48 /* MCAN2 IRQ handler */
+    IRQ_HANDLER 49 /* MCAN3 IRQ handler */
+    IRQ_HANDLER 50 /* PTPC IRQ handler */
+    IRQ_HANDLER 51 /* QEI0 IRQ handler */
+    IRQ_HANDLER 52 /* QEI1 IRQ handler */
+    IRQ_HANDLER 53 /* PWM0 IRQ handler */
+    IRQ_HANDLER 54 /* PWM1 IRQ handler */
+    IRQ_HANDLER 55 /* SDM0 IRQ handler */
+    IRQ_HANDLER 56 /* TRGM[0] IRQ handler */
+    IRQ_HANDLER 57 /* TRGM[1] IRQ handler */
+    IRQ_HANDLER 58 /* ENET0 IRQ handler */
+    IRQ_HANDLER 59 /* NTMR0 IRQ handler */
+    IRQ_HANDLER 60 /* USB0 IRQ handler */
+    IRQ_HANDLER 61 /* ESC IRQ handler */
+    IRQ_HANDLER 62 /* ESC_SYNC0 IRQ handler */
+    IRQ_HANDLER 63 /* ESC_SYNC1 IRQ handler */
+    IRQ_HANDLER 64 /* ESC_RESET IRQ handler */
+    IRQ_HANDLER 65 /* XPI0 IRQ handler */
+    IRQ_HANDLER 66 /* PPI IRQ handler */
+    IRQ_HANDLER 67 /* XDMA IRQ handler */
+    IRQ_HANDLER 68 /* PGPIO IRQ handler */
+    IRQ_HANDLER 69 /* PEWDG IRQ handler */
+    IRQ_HANDLER 70 /* PTMR IRQ handler */
+    IRQ_HANDLER 71 /* PUART IRQ handler */
+    IRQ_HANDLER 72 /* FUSE IRQ handler */
+    IRQ_HANDLER 73 /* DGO_PAD_WAKEUP IRQ handler */
+    IRQ_HANDLER 74 /* DGO_CNT_WAKEUP IRQ handler */
+    IRQ_HANDLER 75 /* BROWNOUT IRQ handler */
+    IRQ_HANDLER 76 /* SYSCTL IRQ handler */
+    IRQ_HANDLER 77 /* CPU0 IRQ handler */
+    IRQ_HANDLER 78 /* DEBUG0 IRQ handler */
+    IRQ_HANDLER 79 /* DEBUG1 IRQ handler */

bsp/hpmicro/hpm5e00evk/startup/HPM5E31/trap.c

@@ -0,0 +1,311 @@
+/*
+ * Copyright (c) 2021-2024 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include "hpm_common.h"
+#include "hpm_soc.h"
+#include <rtthread.h>
+#include "rt_hw_stack_frame.h"
+
+#define MCAUSE_INSTR_ADDR_MISALIGNED (0U)       //!< Instruction Address misaligned
+#define MCAUSE_INSTR_ACCESS_FAULT (1U)          //!< Instruction access fault
+#define MCAUSE_ILLEGAL_INSTR (2U)               //!< Illegal instruction
+#define MCAUSE_BREAKPOINT (3U)                  //!< Breakpoint
+#define MCAUSE_LOAD_ADDR_MISALIGNED (4U)        //!< Load address misaligned
+#define MCAUSE_LOAD_ACCESS_FAULT (5U)           //!< Load access fault
+#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U)   //!< Store/AMO address misaligned
+#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U)      //!< Store/AMO access fault
+#define MCAUSE_ECALL_FROM_USER_MODE (8U)        //!< Environment call from User mode
+#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U)  //!< Environment call from Supervisor mode
+#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U)    //!< Environment call from machine mode
+#define MCAUSE_INSTR_PAGE_FAULT (12U)           //!< Instruction page fault
+#define MCAUSE_LOAD_PAGE_FAULT (13)             //!< Load page fault
+#define MCAUSE_STORE_AMO_PAGE_FAULT (15U)       //!< Store/AMO page fault
+
+#define IRQ_S_SOFT              1
+#define IRQ_H_SOFT              2
+#define IRQ_M_SOFT              3
+#define IRQ_S_TIMER             5
+#define IRQ_H_TIMER             6
+#define IRQ_M_TIMER             7
+#define IRQ_S_EXT               9
+#define IRQ_H_EXT               10
+#define IRQ_M_EXT               11
+#define IRQ_COP                 12
+#define IRQ_HOST                13
+
+#ifdef DEBUG
+#define RT_EXCEPTION_TRACE rt_kprintf
+#else
+#define RT_EXCEPTION_TRACE(...)
+#endif
+
+typedef void (*isr_func_t)(void);
+
+static volatile rt_hw_stack_frame_t *s_stack_frame;
+
+__attribute((weak)) void mchtmr_isr(void)
+{
+}
+
+__attribute__((weak)) void mswi_isr(void)
+{
+}
+
+__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3)
+{
+}
+
+void rt_show_stack_frame(void)
+{
+    RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n");
+    RT_EXCEPTION_TRACE("ra      : 0x%08x\r\n", s_stack_frame->ra);
+    RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus
+    RT_EXCEPTION_TRACE("t0      : 0x%08x\r\n", s_stack_frame->t0);
+    RT_EXCEPTION_TRACE("t1      : 0x%08x\r\n", s_stack_frame->t1);
+    RT_EXCEPTION_TRACE("t2      : 0x%08x\r\n", s_stack_frame->t2);
+    RT_EXCEPTION_TRACE("a0      : 0x%08x\r\n", s_stack_frame->a0);
+    RT_EXCEPTION_TRACE("a1      : 0x%08x\r\n", s_stack_frame->a1);
+    RT_EXCEPTION_TRACE("a2      : 0x%08x\r\n", s_stack_frame->a2);
+    RT_EXCEPTION_TRACE("a3      : 0x%08x\r\n", s_stack_frame->a3);
+    RT_EXCEPTION_TRACE("a4      : 0x%08x\r\n", s_stack_frame->a4);
+    RT_EXCEPTION_TRACE("a5      : 0x%08x\r\n", s_stack_frame->a5);
+#ifndef __riscv_32e
+    RT_EXCEPTION_TRACE("a6      : 0x%08x\r\n", s_stack_frame->a6);
+    RT_EXCEPTION_TRACE("a7      : 0x%08x\r\n", s_stack_frame->a7);
+    RT_EXCEPTION_TRACE("t3      : 0x%08x\r\n", s_stack_frame->t3);
+    RT_EXCEPTION_TRACE("t4      : 0x%08x\r\n", s_stack_frame->t4);
+    RT_EXCEPTION_TRACE("t5      : 0x%08x\r\n", s_stack_frame->t5);
+    RT_EXCEPTION_TRACE("t6      : 0x%08x\r\n", s_stack_frame->t6);
+#endif
+}
+
+uint32_t exception_handler(uint32_t cause, uint32_t epc)
+{
+    /* Unhandled Trap */
+    uint32_t mdcause = read_csr(CSR_MDCAUSE);
+    uint32_t mtval = read_csr(CSR_MTVAL);
+    rt_uint32_t mscratch = read_csr(0x340);
+
+    s_stack_frame = (rt_hw_stack_frame_t *)mscratch;
+    rt_show_stack_frame();
+
+    switch (cause)
+    {
+    case MCAUSE_INSTR_ADDR_MISALIGNED:
+        RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval);
+        break;
+    case MCAUSE_INSTR_ACCESS_FAULT:
+        RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc);
+        switch (mdcause & 0x07)
+        {
+        case 1:
+            RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n");
+            break;
+        case 2:
+            RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n");
+            break;
+        case 3:
+            RT_EXCEPTION_TRACE("mdcause: BUS error\r\n");
+            break;
+        case 4:
+            RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n");
+            break;
+        default:
+            RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
+            break;
+        }
+        break;
+    case MCAUSE_ILLEGAL_INSTR:
+        RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval);
+        switch (mdcause & 0x07)
+        {
+        case 0:
+            RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n");
+            break;
+        case 1:
+            RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n");
+            break;
+        case 2:
+            RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n");
+            break;
+        default:
+            RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
+            break;
+        }
+        break;
+    case MCAUSE_BREAKPOINT:
+        RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval);
+        break;
+    case MCAUSE_LOAD_ADDR_MISALIGNED:
+        RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval);
+        break;
+    case MCAUSE_LOAD_ACCESS_FAULT:
+        RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause);
+        switch (mdcause & 0x07)
+        {
+        case 1:
+            RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n");
+            break;
+        case 2:
+            RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n");
+            break;
+        case 3:
+            RT_EXCEPTION_TRACE("mdcause: BUS error\r\n");
+            break;
+        case 4:
+            RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n");
+            break;
+        case 5:
+            RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n");
+            break;
+        case 6:
+            RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n");
+            break;
+        default:
+            RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
+            break;
+        }
+        break;
+    case MCAUSE_STORE_AMO_ADDR_MISALIGNED:
+        RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc);
+        break;
+    case MCAUSE_STORE_AMO_ACCESS_FAULT:
+        RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc);
+        switch (mdcause & 0x07)
+        {
+        case 1:
+            RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n");
+            break;
+        case 2:
+            RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n");
+            break;
+        case 3:
+            RT_EXCEPTION_TRACE("mdcause: BUS error\r\n");
+            break;
+        case 4:
+            RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n");
+            break;
+        case 5:
+            RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n");
+            break;
+        case 6:
+            RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n");
+            break;
+        case 7:
+            RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n");
+        default:
+            RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
+            break;
+        }
+        break;
+    default:
+        RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause);
+        break;
+    }
+
+    rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra);
+    while(1) {
+    }
+}
+
+void trap_entry(void);
+
+void trap_entry(void)
+{
+    uint32_t mcause = read_csr(CSR_MCAUSE);
+    uint32_t mepc = read_csr(CSR_MEPC);
+    uint32_t mstatus = read_csr(CSR_MSTATUS);
+
+#if SUPPORT_PFT_ARCH
+    uint32_t mxstatus = read_csr(CSR_MXSTATUS);
+#endif
+#ifdef __riscv_dsp
+    int ucode = read_csr(CSR_UCODE);
+#endif
+#ifdef __riscv_flen
+    int fcsr = read_fcsr();
+#endif
+
+    /* clobbers list for ecall */
+#ifdef __riscv_32e
+    __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3");
+#else
+    __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3");
+#endif
+
+    /* Do your trap handling */
+    uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK;
+    uint32_t irq_index;
+    if (mcause & CSR_MCAUSE_INTERRUPT_MASK)
+    {
+        switch (cause_type)
+        {
+        /* Machine timer interrupt */
+        case IRQ_M_TIMER:
+            mchtmr_isr();
+            break;
+            /* Machine EXT interrupt */
+        case IRQ_M_EXT:
+            /* Claim interrupt */
+            irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE);
+            /* Execute EXT interrupt handler */
+            if (irq_index > 0)
+            {
+                ((isr_func_t) __vector_table[irq_index])();
+                /* Complete interrupt */
+                __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index);
+            }
+            break;
+            /* Machine SWI interrupt */
+        case IRQ_M_SOFT:
+            mswi_isr();
+            intc_m_complete_swi();
+            break;
+        }
+    }
+    else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE)
+    {
+        /* Machine Syscal call */
+        __asm volatile(
+                "mv a4, a3\n"
+                "mv a3, a2\n"
+                "mv a2, a1\n"
+                "mv a1, a0\n"
+#ifdef __riscv_32e
+                "mv a0, t0\n"
+#else
+                "mv a0, a7\n"
+#endif
+                "call syscall_handler\n"
+                : : : "a4"
+        );
+        mepc += 4;
+    }
+    else
+    {
+        mepc = exception_handler(mcause, mepc);
+    }
+
+    /* Restore CSR */
+    write_csr(CSR_MSTATUS, mstatus);
+    write_csr(CSR_MEPC, mepc);
+#if SUPPORT_PFT_ARCH
+    write_csr(CSR_MXSTATUS, mxstatus);
+#endif
+#ifdef __riscv_dsp
+    write_csr(CSR_UCODE, ucode);
+#endif
+#ifdef __riscv_flen
+    write_fcsr(fcsr);
+#endif
+}
+
+/**
+ * Trap Handler
+ */
+rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp)
+{
+}

bsp/hpmicro/hpm5e00evk/startup/SConscript

@@ -0,0 +1,13 @@
+# for module compiling
+import os
+Import('rtconfig')
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+
+objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript'))
+ASFLAGS = ' -I' + cwd
+
+Return('objs')

bsp/hpmicro/hpm6200evk/.config

@@ -104,11 +104,9 @@
 #
 # CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set
 # end of rt_strnlen options
-
-# CONFIG_RT_UTEST_TC_USING_KLIBC is not set
 # end of klibc options
 
-CONFIG_RT_NAME_MAX=8
+CONFIG_RT_NAME_MAX=16
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
 # CONFIG_RT_USING_NANO is not set
 # CONFIG_RT_USING_AMP is not set
@@ -131,7 +129,7 @@ CONFIG_RT_USING_TIMER_SOFT=y
 CONFIG_RT_TIMER_THREAD_PRIO=4
 CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
 # CONFIG_RT_USING_TIMER_ALL_SOFT is not set
-# CONFIG_RT_USING_CPU_USAGE_TRACER is not set
+CONFIG_RT_USING_CPU_USAGE_TRACER=y
 
 #
 # kservice options
@@ -183,6 +181,9 @@ CONFIG_RT_VER_NUM=0x50201
 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
 # end of RT-Thread Kernel
 
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV32=y
+
 #
 # RT-Thread Components
 #
@@ -190,7 +191,7 @@ CONFIG_RT_USING_COMPONENTS_INIT=y
 CONFIG_RT_USING_USER_MAIN=y
 CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
 CONFIG_RT_MAIN_THREAD_PRIORITY=10
-# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_LEGACY=y
 CONFIG_RT_USING_MSH=y
 CONFIG_RT_USING_FINSH=y
 CONFIG_FINSH_USING_MSH=y
@@ -199,6 +200,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20
 CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
+# CONFIG_FINSH_USING_WORD_OPERATION is not set
 CONFIG_FINSH_USING_SYMTAB=y
 CONFIG_FINSH_CMD_SIZE=80
 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
@@ -211,22 +213,7 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y
 #
 # DFS: device virtual file system
 #
-CONFIG_RT_USING_DFS=y
-CONFIG_DFS_USING_POSIX=y
-CONFIG_DFS_USING_WORKDIR=y
-# CONFIG_RT_USING_DFS_MNTTABLE is not set
-CONFIG_DFS_FD_MAX=16
-CONFIG_RT_USING_DFS_V1=y
-# CONFIG_RT_USING_DFS_V2 is not set
-CONFIG_DFS_FILESYSTEMS_MAX=4
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
-# CONFIG_RT_USING_DFS_ELMFAT is not set
-CONFIG_RT_USING_DFS_DEVFS=y
-# CONFIG_RT_USING_DFS_ROMFS is not set
-# CONFIG_RT_USING_DFS_CROMFS is not set
-# CONFIG_RT_USING_DFS_RAMFS is not set
-# CONFIG_RT_USING_DFS_TMPFS is not set
-# CONFIG_RT_USING_DFS_MQUEUE is not set
+# CONFIG_RT_USING_DFS is not set
 # end of DFS: device virtual file system
 
 # CONFIG_RT_USING_FAL is not set
@@ -240,10 +227,11 @@ CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_UNAMED_PIPE_NUMBER=64
 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
-CONFIG_RT_USING_SERIAL_V1=y
-# CONFIG_RT_USING_SERIAL_V2 is not set
+# CONFIG_RT_USING_SERIAL_V1 is not set
+CONFIG_RT_USING_SERIAL_V2=y
+# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set
+CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y
 CONFIG_RT_SERIAL_USING_DMA=y
-CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_SERIAL_BYPASS is not set
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_CPUTIME is not set
@@ -390,6 +378,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FREEMODBUS is not set
 # CONFIG_PKG_USING_NANOPB is not set
 # CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
+# CONFIG_PKG_USING_ESP_HOSTED is not set
 
 #
 # Wi-Fi
@@ -497,6 +486,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_QMODBUS is not set
 # CONFIG_PKG_USING_PNET is not set
 # CONFIG_PKG_USING_OPENER is not set
+# CONFIG_PKG_USING_FREEMQTT is not set
 # end of IoT - internet of things
 
 #
@@ -586,6 +576,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # tools packages
 #
 # CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_MCOREDUMP is not set
 # CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
@@ -631,6 +622,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ZDEBUG is not set
 # CONFIG_PKG_USING_RVBACKTRACE is not set
 # CONFIG_PKG_USING_HPATCHLITE is not set
+# CONFIG_PKG_USING_THREAD_METRIC is not set
 # end of tools packages
 
 #
@@ -724,6 +716,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_RMP is not set
 # CONFIG_PKG_USING_R_RHEALSTONE is not set
 # CONFIG_PKG_USING_HEARTBEAT is not set
+# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
 # end of system packages
 
 #
@@ -805,6 +798,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 
 # CONFIG_PKG_USING_NRF5X_SDK is not set
 # CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set
 # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
 # CONFIG_PKG_USING_MM32 is not set
 
@@ -847,6 +842,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # HC32 DDL Drivers
 #
+# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set
+# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set
 # end of HC32 DDL Drivers
 
 #
@@ -860,6 +859,31 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set
 # CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set
 # end of NXP HAL & SDK Drivers
+
+#
+# NUVOTON Drivers
+#
+# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set
+# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set
+# end of NUVOTON Drivers
+
+#
+# GD32 Drivers
+#
+# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set
+# end of GD32 Drivers
+
+#
+# HPMicro SDK
+#
+CONFIG_PKG_USING_HPM_SDK=y
+CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk"
+# CONFIG_PKG_USING_HPM_SDK_V110 is not set
+CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y
+CONFIG_PKG_HPM_SDK_VER="latest"
+# end of HPMicro SDK
 # end of HAL & SDK Drivers
 
 #
@@ -1031,6 +1055,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_SEAN_WS2812B is not set
 # CONFIG_PKG_USING_IC74HC165 is not set
 # CONFIG_PKG_USING_IST8310 is not set
+# CONFIG_PKG_USING_ST7789_SPI is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set
 # end of peripheral libraries and drivers
 
@@ -1369,10 +1394,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # end of Arduino libraries
 # end of RT-Thread online packages
 
+CONFIG_SOC_HPM6200_SERIES=y
+
 #
 # Hardware Drivers Config
 #
-CONFIG_SOC_HPM6000=y
+CONFIG_SOC_HPM6200=y
 
 #
 # On-chip Peripheral Drivers
@@ -1382,6 +1409,8 @@ CONFIG_BSP_USING_UART=y
 CONFIG_BSP_USING_UART0=y
 # CONFIG_BSP_UART0_RX_USING_DMA is not set
 # CONFIG_BSP_UART0_TX_USING_DMA is not set
+CONFIG_BSP_UART0_RX_BUFSIZE=128
+CONFIG_BSP_UART0_TX_BUFSIZE=0
 # CONFIG_BSP_USING_UART2 is not set
 # CONFIG_BSP_USING_UART6 is not set
 # CONFIG_BSP_USING_SPI is not set

bsp/hpmicro/hpm6200evk/SConstruct

@@ -55,17 +55,6 @@ GDB = rtconfig.GDB
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 
-hpm_library = 'hpm_sdk'
-rtconfig.BSP_LIBRARY_TYPE = hpm_library
-
-# include soc
-objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript')))
-
-# include libraries
-objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
-
-# include components
-objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript')))
 
 
 # includes rtt drivers

bsp/hpmicro/hpm6200evk/board/Kconfig

@@ -1,8 +1,8 @@
 menu "Hardware Drivers Config"
 
-config SOC_HPM6000
+config SOC_HPM6200
     bool
-    select SOC_SERIES_HPM6000
+    select SOC_HPM6200_SERIES
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
     default y

bsp/hpmicro/hpm6200evk/board/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024 HPMicro
+ * Copyright (c) 2023-2025 HPMicro
  * SPDX-License-Identifier: BSD-3-Clause
  *
  *
@@ -19,10 +19,7 @@
 #include "hpm_trgm_drv.h"
 #include "hpm_pllctlv2_drv.h"
 #include "hpm_pcfg_drv.h"
-
-static board_timer_cb timer_cb;
-ATTR_PLACE_AT_NONCACHEABLE_BSS static bool init_delay_flag;
-
+#include <rtconfig.h>
 /**
  * @brief FLASH configuration option definitions:
  * option[0]:
@@ -77,11 +74,11 @@ ATTR_PLACE_AT_NONCACHEABLE_BSS static bool init_delay_flag;
  *      0 - 4MB / 1 - 8MB / 2 - 16MB
  */
 #if defined(FLASH_XIP) && FLASH_XIP
-__attribute__((section(".nor_cfg_option"))) const uint32_t option[4] = { 0xfcf90001, 0x00000007, 0x0, 0x0 };
+__attribute__((section(".nor_cfg_option"), used)) const uint32_t option[4] = { 0xfcf90001, 0x00000007, 0x0, 0x0 };
 #endif
 
 #if defined(FLASH_UF2) && FLASH_UF2
-ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
+ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
 #endif
 
 void board_init_console(void)
@@ -95,8 +92,6 @@ void board_init_console(void)
     And a uart rx dma request will be generated by default uart fifo dma trigger level. */
     init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE);
 
-    /* Configure the UART clock to 24MHz */
-    clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U);
     clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0);
 
     cfg.type = BOARD_CONSOLE_TYPE;
@@ -188,6 +183,7 @@ void board_init(void)
 
 void board_init_core1(void)
 {
+    clock_update_core_clock();
     board_init_console();
     board_init_pmp();
 }
@@ -202,6 +198,9 @@ void board_delay_ms(uint32_t ms)
     clock_cpu_delay_ms(ms);
 }
 
+#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT
+static board_timer_cb timer_cb;
+SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr)
 void board_timer_isr(void)
 {
     if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
@@ -209,7 +208,6 @@ void board_timer_isr(void)
         timer_cb();
     }
 }
-SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr);
 
 void board_timer_create(uint32_t ms, board_timer_cb cb)
 {
@@ -229,6 +227,7 @@ void board_timer_create(uint32_t ms, board_timer_cb cb)
 
     gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
 }
+#endif
 
 void board_i2c_bus_clear(I2C_Type *ptr)
 {
@@ -262,30 +261,43 @@ void board_i2c_bus_clear(I2C_Type *ptr)
     }
 }
 
+uint32_t board_init_i2c_clock(I2C_Type *ptr)
+{
+    uint32_t freq = 0;
+
+    if (ptr == HPM_I2C0) {
+        clock_add_to_group(clock_i2c0, 0);
+        freq = clock_get_frequency(clock_i2c0);
+    } else if (ptr == HPM_I2C1) {
+        clock_add_to_group(clock_i2c1, 0);
+        freq = clock_get_frequency(clock_i2c1);
+    } else if (ptr == HPM_I2C2) {
+        clock_add_to_group(clock_i2c2, 0);
+        freq = clock_get_frequency(clock_i2c2);
+    } else if (ptr == HPM_I2C3) {
+        clock_add_to_group(clock_i2c3, 0);
+        freq = clock_get_frequency(clock_i2c3);
+    } else {
+        ;
+    }
+
+    return freq;
+}
+
 void board_init_i2c(I2C_Type *ptr)
 {
     i2c_config_t config;
     hpm_stat_t stat;
     uint32_t freq;
-    if (ptr == NULL) {
-        return;
-    }
 
+    freq = board_init_i2c_clock(ptr);
     board_i2c_bus_clear(ptr);
     init_i2c_pins(ptr);
-    clock_add_to_group(clock_i2c0, 0);
-    clock_add_to_group(clock_i2c1, 0);
-    clock_add_to_group(clock_i2c2, 0);
-    clock_add_to_group(clock_i2c3, 0);
-    /* Configure the I2C clock to 24MHz */
-    clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U);
-
     config.i2c_mode = i2c_mode_normal;
     config.is_10bit_addressing = false;
-    freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME);
     stat = i2c_init_master(ptr, freq, &config);
     if (stat != status_success) {
-        printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr);
+        printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr);
         while (1) {
         }
     }
@@ -294,22 +306,13 @@ void board_init_i2c(I2C_Type *ptr)
 uint32_t board_init_spi_clock(SPI_Type *ptr)
 {
     if (ptr == HPM_SPI1) {
-        /* SPI1 clock configure */
         clock_add_to_group(clock_spi1, 0);
-        clock_set_source_divider(clock_spi1, clk_src_pll0_clk0, 5U); /* 80MHz */
-
         return clock_get_frequency(clock_spi1);
     } else if (ptr == HPM_SPI2) {
-        /* SPI3 clock configure */
         clock_add_to_group(clock_spi2, 0);
-        clock_set_source_divider(clock_spi2, clk_src_pll0_clk0, 5U); /* 80MHz */
-
         return clock_get_frequency(clock_spi2);
     } else if (ptr == HPM_SPI3) {
-        /* SPI3 clock configure */
         clock_add_to_group(clock_spi3, 0);
-        clock_set_source_divider(clock_spi3, clk_src_pll0_clk0, 5U); /* 80MHz */
-
         return clock_get_frequency(clock_spi3);
     }
     return 0;
@@ -397,24 +400,12 @@ void board_led_write(uint8_t state)
     gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
 }
 
-void board_init_usb_pins(void)
+void board_init_usb(USB_Type *ptr)
 {
-    /* set pull-up for USBx ID pin */
-    init_usb_pins();
-
-    /* configure USBx ID pin as input function */
-    gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN);
-}
-
-uint8_t board_get_usb_id_status(void)
-{
-    return gpio_read_pin(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN);
-}
-
-void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
-{
-    (void) usb_index;
-    (void) level;
+    if (ptr == HPM_USB0) {
+        init_usb_pins(ptr);
+        clock_add_to_group(clock_usb0, 0);
+    }
 }
 
 void board_init_pmp(void)
@@ -472,89 +463,44 @@ void board_init_clock(void)
         /* Select clock setting preset1 */
         sysctl_clock_set_preset(HPM_SYSCTL, 2);
     }
-    /* Add most Clocks to group 0 */
-    /* not open uart clock in this API, uart should configure pin function before opening clock */
+    /* Add clocks to group 0 */
     clock_add_to_group(clock_cpu0, 0);
+    clock_add_to_group(clock_mchtmr0, 0);
     clock_add_to_group(clock_ahbp, 0);
     clock_add_to_group(clock_axic, 0);
     clock_add_to_group(clock_axis, 0);
-
-    clock_add_to_group(clock_mchtmr0, 0);
     clock_add_to_group(clock_xpi0, 0);
-    clock_add_to_group(clock_gptmr0, 0);
-    clock_add_to_group(clock_gptmr1, 0);
-    clock_add_to_group(clock_gptmr2, 0);
-    clock_add_to_group(clock_gptmr3, 0);
-    clock_add_to_group(clock_i2c0, 0);
-    clock_add_to_group(clock_i2c1, 0);
-    clock_add_to_group(clock_i2c2, 0);
-    clock_add_to_group(clock_i2c3, 0);
-    clock_add_to_group(clock_lin0, 0);
-    clock_add_to_group(clock_lin1, 0);
-    clock_add_to_group(clock_lin2, 0);
-    clock_add_to_group(clock_lin3, 0);
-    clock_add_to_group(clock_spi0, 0);
-    clock_add_to_group(clock_spi1, 0);
-    clock_add_to_group(clock_spi2, 0);
-    clock_add_to_group(clock_spi3, 0);
-    clock_add_to_group(clock_can0, 0);
-    clock_add_to_group(clock_can1, 0);
-    clock_add_to_group(clock_can2, 0);
-    clock_add_to_group(clock_can3, 0);
-    clock_add_to_group(clock_ptpc, 0);
-    clock_add_to_group(clock_ref0, 0);
-    clock_add_to_group(clock_ref1, 0);
-    clock_add_to_group(clock_watchdog0, 0);
-    clock_add_to_group(clock_sdp, 0);
     clock_add_to_group(clock_xdma, 0);
+    clock_add_to_group(clock_hdma, 0);
     clock_add_to_group(clock_ram0, 0);
-    clock_add_to_group(clock_usb0, 0);
-    clock_add_to_group(clock_kman, 0);
+    clock_add_to_group(clock_lmm0, 0);
+    clock_add_to_group(clock_lmm1, 0);
     clock_add_to_group(clock_gpio, 0);
-    clock_add_to_group(clock_mbx0, 0);
-    clock_add_to_group(clock_hdma, 0);
-    clock_add_to_group(clock_rng, 0);
     clock_add_to_group(clock_mot0, 0);
     clock_add_to_group(clock_mot1, 0);
     clock_add_to_group(clock_mot2, 0);
     clock_add_to_group(clock_mot3, 0);
-    clock_add_to_group(clock_acmp, 0);
     clock_add_to_group(clock_synt, 0);
-    clock_add_to_group(clock_lmm0, 0);
-    clock_add_to_group(clock_lmm1, 0);
-
-    clock_add_to_group(clock_adc0, 0);
-    clock_add_to_group(clock_adc1, 0);
-    clock_add_to_group(clock_adc2, 0);
-
-    clock_add_to_group(clock_dac0, 0);
-    clock_add_to_group(clock_dac1, 0);
-
-    clock_add_to_group(clock_tsns, 0);
-    clock_add_to_group(clock_crc0, 0);
-    clock_add_to_group(clock_sdm0, 0);
-
+    clock_add_to_group(clock_ptpc, 0);
     /* Connect Group0 to CPU0 */
     clock_connect_group_to_cpu(0, 0);
 
-    /* Add the CPU1 clock to Group1 */
+    /* Add clocks to Group1 */
+    clock_add_to_group(clock_cpu1, 1);
     clock_add_to_group(clock_mchtmr1, 1);
-
     /* Connect Group1 to CPU1 */
     clock_connect_group_to_cpu(1, 1);
 
     /* Bump up DCDC voltage to 1275mv */
     pcfg_dcdc_set_voltage(HPM_PCFG, 1275);
 
-    /* Connect CAN2/CAN3 to pll0clk0*/
-    clock_set_source_divider(clock_can2, clk_src_pll0_clk0, 1);
-    clock_set_source_divider(clock_can3, clk_src_pll0_clk0, 1);
-
-    /* Configure CPU to 600MHz, AXI/AHB to 200MHz */
-    sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll1_clk0, 1, 3, 3);
-    /* Configure PLL1_CLK0 Post Divider to 1 */
-    pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 0);
-    pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 600000000);
+    /* Configure CPU to 600MHz, AXI/AHB to 200MHz. CPU1 clock freqency same as CPU0 */
+    sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll1_clk1, 1, 3, 3);
+    /* Configure PLL1 Post Divider */
+    pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll1, pllctlv2_clk0, pllctlv2_div_2p0);    /* PLL1CLK0: 480MHz */
+    pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll1, pllctlv2_clk1, pllctlv2_div_1p6);    /* PLL1CLK1: 600MHz */
+    /* Configure PLL1 Frequency to 960MHz */
+    pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll1, 960000000);
     clock_update_core_clock();
 
     /* Configure mchtmr to 24MHz */
@@ -562,72 +508,12 @@ void board_init_clock(void)
     clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1);
 }
 
-uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
-{
-    uint32_t freq = 0;
-
-    if (ptr == HPM_GPTMR0) {
-        clock_add_to_group(clock_gptmr0, 0);
-        clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4);
-        freq = clock_get_frequency(clock_gptmr0);
-    }
-    else if (ptr == HPM_GPTMR1) {
-        clock_add_to_group(clock_gptmr1, 0);
-        clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4);
-        freq = clock_get_frequency(clock_gptmr1);
-    }
-    else if (ptr == HPM_GPTMR2) {
-        clock_add_to_group(clock_gptmr2, 0);
-        clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4);
-        freq = clock_get_frequency(clock_gptmr2);
-    }
-    else if (ptr == HPM_GPTMR3) {
-        clock_add_to_group(clock_gptmr3, 0);
-        clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4);
-        freq = clock_get_frequency(clock_gptmr3);
-    }
-    else {
-        /* Invalid instance */
-    }
-    return freq;
-}
-
-uint32_t board_init_adc12_clock(ADC16_Type *ptr)
+uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus)
 {
     uint32_t freq = 0;
-    switch ((uint32_t)ptr) {
-    case HPM_ADC0_BASE:
-        /* Configure the ADC clock to 200MHz */
-        clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
-        clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
-        freq = clock_get_frequency(clock_adc0);
-        break;
-    case HPM_ADC1_BASE:
-        /* Configure the ADC clock to 200MHz */
-        clock_set_adc_source(clock_adc1, clk_adc_src_ana0);
-        clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
-        freq = clock_get_frequency(clock_adc1);
-        break;
-    case HPM_ADC2_BASE:
-        /* Configure the ADC clock to 200MHz */
-        clock_set_adc_source(clock_adc2, clk_adc_src_ana0);
-        clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
-        freq = clock_get_frequency(clock_adc2);
-        break;
-    default:
-        /* Invalid ADC instance */
-        break;
-    }
 
-    return freq;
-}
-
-uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
-{
-    uint32_t freq = 0;
-
-    if (ptr == HPM_ADC0) {
-        if (clk_src_ahb) {
+    if (ptr == (void *)HPM_ADC0) {
+        if (clk_src_bus) {
             /* Configure the ADC clock from AHB (@200MHz by default)*/
             clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
         } else {
@@ -635,10 +521,10 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
             clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
             clock_set_source_divider(clock_ana0, clk_src_pll0_clk0, 2U);
         }
-
+        clock_add_to_group(clock_adc0, 0);
         freq = clock_get_frequency(clock_adc0);
-    } else if (ptr == HPM_ADC1) {
-        if (clk_src_ahb) {
+    } else if (ptr == (void *)HPM_ADC1) {
+        if (clk_src_bus) {
             /* Configure the ADC clock from AHB (@200MHz by default)*/
             clock_set_adc_source(clock_adc1, clk_adc_src_ahb0);
         } else {
@@ -646,10 +532,10 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
             clock_set_adc_source(clock_adc1, clk_adc_src_ana1);
             clock_set_source_divider(clock_ana1, clk_src_pll0_clk0, 2U);
         }
-
+        clock_add_to_group(clock_adc1, 0);
         freq = clock_get_frequency(clock_adc1);
-    } else if (ptr == HPM_ADC2) {
-        if (clk_src_ahb) {
+    } else if (ptr == (void *)HPM_ADC2) {
+        if (clk_src_bus) {
             /* Configure the ADC clock from AHB (@200MHz by default)*/
             clock_set_adc_source(clock_adc2, clk_adc_src_ahb0);
         } else {
@@ -657,7 +543,7 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
             clock_set_adc_source(clock_adc2, clk_adc_src_ana2);
             clock_set_source_divider(clock_ana2, clk_src_pll0_clk0, 2U);
         }
-
+        clock_add_to_group(clock_adc2, 0);
         freq = clock_get_frequency(clock_adc2);
     }
 
@@ -677,7 +563,7 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb)
             clock_set_dac_source(clock_dac0, clk_dac_src_ana3);
             clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2);
         }
-
+        clock_add_to_group(clock_dac0, 0);
         freq = clock_get_frequency(clock_dac0);
     } else if (ptr == HPM_DAC1) {
         if (clk_src_ahb == true) {
@@ -688,7 +574,7 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb)
             clock_set_dac_source(clock_dac1, clk_dac_src_ana4);
             clock_set_source_divider(clock_ana4, clk_src_pll0_clk1, 2);
         }
-
+        clock_add_to_group(clock_dac1, 0);
         freq = clock_get_frequency(clock_dac1);
     }
 
@@ -706,18 +592,22 @@ uint32_t board_init_can_clock(MCAN_Type *ptr)
     if (ptr == HPM_MCAN0) {
         /* Set the CAN0 peripheral clock to 8MHz */
         clock_set_source_divider(clock_can0, clk_src_pll0_clk0, 5);
+        clock_add_to_group(clock_can0, 0);
         freq = clock_get_frequency(clock_can0);
     } else if (ptr == HPM_MCAN1) {
         /* Set the CAN1 peripheral clock to 8MHz */
         clock_set_source_divider(clock_can1, clk_src_pll0_clk0, 5);
+        clock_add_to_group(clock_can1, 0);
         freq = clock_get_frequency(clock_can1);
     } else if (ptr == HPM_MCAN2) {
         /* Set the CAN2 peripheral clock to 8MHz */
         clock_set_source_divider(clock_can2, clk_src_pll0_clk0, 5);
+        clock_add_to_group(clock_can2, 0);
         freq = clock_get_frequency(clock_can2);
     } else if (ptr == HPM_MCAN3) {
         /* Set the CAN2 peripheral clock to 8MHz */
         clock_set_source_divider(clock_can3, clk_src_pll0_clk0, 5);
+        clock_add_to_group(clock_can3, 0);
         freq = clock_get_frequency(clock_can3);
     } else {
         /* Invalid CAN instance */
@@ -730,6 +620,17 @@ void board_init_adc16_pins(void)
     init_adc_pins();
 }
 
+void board_init_acmp_pins(void)
+{
+    init_acmp_pins();
+}
+
+void board_init_acmp_clock(ACMP_Type *ptr)
+{
+    (void)ptr;
+    clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1);
+}
+
 void board_init_rgb_pwm_pins(void)
 {
     init_led_pins_as_pwm();
@@ -781,44 +682,51 @@ uint32_t board_init_uart_clock(UART_Type *ptr)
 {
     uint32_t freq = 0U;
     if (ptr == HPM_UART0) {
-        clock_set_source_divider(clock_uart0, clk_src_pll1_clk0, 6);
         clock_add_to_group(clock_uart0, 0);
         freq = clock_get_frequency(clock_uart0);
     } else if (ptr == HPM_UART1) {
-        clock_set_source_divider(clock_uart1, clk_src_pll1_clk0, 6);
         clock_add_to_group(clock_uart1, 0);
         freq = clock_get_frequency(clock_uart1);
     } else if (ptr == HPM_UART2) {
-        clock_set_source_divider(clock_uart2, clk_src_pll1_clk0, 6);
         clock_add_to_group(clock_uart2, 0);
         freq = clock_get_frequency(clock_uart2);
-    } else if (ptr == HPM_UART6) {
-        clock_set_source_divider(clock_uart6, clk_src_pll1_clk0, 6);
-        clock_add_to_group(clock_uart6, 0);
-        freq = clock_get_frequency(clock_uart6);
     } else {
         /* Not supported */
     }
     return freq;
 }
 
-uint32_t board_init_pwm_clock(PWM_Type *ptr)
+void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp)
 {
-    uint32_t freq = 0;
-    if (ptr == HPM_PWM0) {
-        clock_add_to_group(clock_mot0, 0);
-        freq = clock_get_frequency(clock_mot0);
-    } else if (ptr == HPM_PWM1) {
-        clock_add_to_group(clock_mot1, 0);
-        freq = clock_get_frequency(clock_mot1);
-    } else if (ptr == HPM_PWM2) {
-        clock_add_to_group(clock_mot2, 0);
-        freq = clock_get_frequency(clock_mot2);
-    } else if (ptr == HPM_PWM3) {
-        clock_add_to_group(clock_mot3, 0);
-        freq = clock_get_frequency(clock_mot3);
-    } else {
+    init_gptmr_channel_pin(ptr, channel, as_comp);
+}
+
+void board_init_clk_ref_pin(void)
+{
+    init_clk_ref_pins();
+}
 
+uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
+{
+    uint32_t freq = 0U;
+    if (ptr == HPM_GPTMR0) {
+        clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_gptmr0);
+    } else if (ptr == HPM_GPTMR1) {
+        clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_gptmr1);
+    } else if (ptr == HPM_GPTMR2) {
+        clock_add_to_group(clock_gptmr2, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_gptmr2);
+    } else if (ptr == HPM_GPTMR3) {
+        clock_add_to_group(clock_gptmr3, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_gptmr3);
+    } else if (ptr == HPM_PTMR) {
+        clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1);
+        freq = clock_get_frequency(clock_ptmr);
+    } else {
+        /* Not supported */
     }
     return freq;
 }
+

bsp/hpmicro/hpm6200evk/board/board.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023 HPMicro
+ * Copyright (c) 2023-2025 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -12,6 +12,7 @@
 #include "hpm_clock_drv.h"
 #include "hpm_soc.h"
 #include "hpm_soc_feature.h"
+#include "hpm_trgm_drv.h"
 #include "pinmux.h"
 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
 #include "hpm_debug_console.h"
@@ -22,27 +23,22 @@
 
 #define SEC_CORE_IMG_START CORE1_ILM_LOCAL_BASE
 
-/* dma section */
-#define BOARD_APP_XDMA     HPM_XDMA
-#define BOARD_APP_HDMA     HPM_HDMA
-#define BOARD_APP_XDMA_IRQ IRQn_XDMA
-#define BOARD_APP_HDMA_IRQ IRQn_HDMA
-#define BOARD_APP_DMAMUX   HPM_DMAMUX
-
 #ifndef BOARD_RUNNING_CORE
 #define BOARD_RUNNING_CORE HPM_CORE0
 #endif
 
 /* uart section */
 #ifndef BOARD_APP_UART_BASE
-#define BOARD_APP_UART_BASE HPM_UART2
-#define BOARD_APP_UART_IRQ  IRQn_UART2
+#define BOARD_APP_UART_BASE       HPM_UART2
+#define BOARD_APP_UART_IRQ        IRQn_UART2
 #define BOARD_APP_UART_BAUDRATE   (115200UL)
 #define BOARD_APP_UART_CLK_NAME   clock_uart2
 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART2_RX
 #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART2_TX
 #endif
 
+#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PB02
+
 /* uart lin sample section */
 #define BOARD_UART_LIN          BOARD_APP_UART_BASE
 #define BOARD_UART_LIN_IRQ      BOARD_APP_UART_IRQ
@@ -50,7 +46,6 @@
 #define BOARD_UART_LIN_TX_PORT  GPIO_DI_GPIOC
 #define BOARD_UART_LIN_TX_PIN   (26U) /* PC26 should align with used pin in pinmux configuration */
 
-
 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
 #ifndef BOARD_CONSOLE_TYPE
 #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART
@@ -59,15 +54,15 @@
 #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
 #ifndef BOARD_CONSOLE_UART_BASE
 #if BOARD_RUNNING_CORE == HPM_CORE0
-#define BOARD_CONSOLE_UART_BASE     HPM_UART0
-#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0
-#define BOARD_CONSOLE_UART_IRQ      IRQn_UART0
+#define BOARD_CONSOLE_UART_BASE       HPM_UART0
+#define BOARD_CONSOLE_UART_CLK_NAME   clock_uart0
+#define BOARD_CONSOLE_UART_IRQ        IRQn_UART0
 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX
 #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX
 #else
-#define BOARD_CONSOLE_UART_BASE     HPM_UART2
-#define BOARD_CONSOLE_UART_CLK_NAME clock_uart2
-#define BOARD_CONSOLE_UART_IRQ      IRQn_UART2
+#define BOARD_CONSOLE_UART_BASE       HPM_UART2
+#define BOARD_CONSOLE_UART_CLK_NAME   clock_uart2
+#define BOARD_CONSOLE_UART_IRQ        IRQn_UART2
 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART2_TX
 #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART2_RX
 #endif
@@ -83,6 +78,8 @@
 
 /* rtthread-nano finsh section */
 #define BOARD_RT_CONSOLE_BASE        BOARD_CONSOLE_UART_BASE
+#define BOARD_RT_CONSOLE_CLK_NAME    BOARD_CONSOLE_UART_CLK_NAME
+#define BOARD_RT_CONSOLE_IRQ         BOARD_CONSOLE_UART_IRQ
 
 /* usb cdc acm uart section */
 #define BOARD_USB_CDC_ACM_UART            BOARD_APP_UART_BASE
@@ -102,9 +99,11 @@
 #define BOARD_SDM_CHANNEL         3
 #define BOARD_SDM_TRGM            HPM_TRGM3
 #define BOARD_SDM_TRGM_GPTMR      HPM_GPTMR3
+#define BOARD_SDM_TRGM_GPTMR_CLK  clock_gptmr3
 #define BOARD_SDM_TRGM_GPTMR_CH   2
 #define BOARD_SDM_TRGM_INPUT_SRC  HPM_TRGM3_INPUT_SRC_GPTMR3_OUT2
 #define BOARD_SDM_TRGM_OUTPUT_DST HPM_TRGM3_OUTPUT_SRC_SDFM_TRG15
+#define BOARD_SDM_TRGM_SYNC_SRC   (15)
 
 /* lin section */
 #define BOARD_LIN          HPM_LIN0
@@ -117,13 +116,13 @@
 #define BOARD_FLASH_SIZE         (16 * SIZE_1MB)
 
 /* i2c section */
-#define BOARD_APP_I2C_BASE       HPM_I2C3
-#define BOARD_APP_I2C_IRQ        IRQn_I2C3
-#define BOARD_APP_I2C_CLK_NAME   clock_i2c3
-#define BOARD_APP_I2C_DMA        HPM_HDMA
-#define BOARD_APP_I2C_DMAMUX     HPM_DMAMUX
-#define BOARD_APP_I2C_DMA_SRC    HPM_DMA_SRC_I2C3
-#define BOARD_APP_I2C_DMAMUX_CH  DMAMUX_MUXCFG_HDMA_MUX0
+#define BOARD_APP_I2C_BASE     HPM_I2C3
+#define BOARD_APP_I2C_IRQ      IRQn_I2C3
+#define BOARD_APP_I2C_CLK_NAME clock_i2c3
+#define BOARD_APP_I2C_DMA      HPM_HDMA
+#define BOARD_APP_I2C_DMAMUX   HPM_DMAMUX
+#define BOARD_APP_I2C_DMA_SRC  HPM_DMA_SRC_I2C3
+
 #define BOARD_I2C_GPIO_CTRL      HPM_GPIO0
 #define BOARD_I2C_SCL_GPIO_INDEX GPIO_DO_GPIOB
 #define BOARD_I2C_SCL_GPIO_PIN   20
@@ -132,17 +131,20 @@
 
 /* ACMP desction */
 #define BOARD_ACMP             HPM_ACMP
+#define BOARD_ACMP_CLK         clock_acmp0
 #define BOARD_ACMP_CHANNEL     ACMP_CHANNEL_CHN1
 #define BOARD_ACMP_IRQ         IRQn_ACMP_1
 #define BOARD_ACMP_PLUS_INPUT  ACMP_INPUT_DAC_OUT  /* use internal DAC */
 #define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_5 /* align with used pin */
 
 /* dma section */
-#define BOARD_APP_XDMA     HPM_XDMA
-#define BOARD_APP_HDMA     HPM_HDMA
-#define BOARD_APP_XDMA_IRQ IRQn_XDMA
-#define BOARD_APP_HDMA_IRQ IRQn_HDMA
-#define BOARD_APP_DMAMUX   HPM_DMAMUX
+#define BOARD_APP_XDMA      HPM_XDMA
+#define BOARD_APP_HDMA      HPM_HDMA
+#define BOARD_APP_XDMA_IRQ  IRQn_XDMA
+#define BOARD_APP_HDMA_IRQ  IRQn_HDMA
+#define BOARD_APP_DMAMUX    HPM_DMAMUX
+#define TEST_DMA_CONTROLLER HPM_XDMA
+#define TEST_DMA_IRQ        IRQn_XDMA
 
 /* gptmr section */
 #define BOARD_GPTMR                   HPM_GPTMR1
@@ -199,12 +201,14 @@
 #define BOARD_APP_ADC16_IRQn     IRQn_ADC0
 #define BOARD_APP_ADC16_CH_1     (8U)
 #define BOARD_APP_ADC16_CLK_NAME (clock_adc0)
+#define BOARD_APP_ADC16_CLK_BUS  (clk_adc_src_ahb0)
 
-#define BOARD_APP_ADC16_HW_TRIG_SRC     HPM_PWM0
-#define BOARD_APP_ADC16_HW_TRGM         HPM_TRGM0
-#define BOARD_APP_ADC16_HW_TRGM_IN      HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
-#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI
-#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A
+#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_mot0
+#define BOARD_APP_ADC16_HW_TRIG_SRC          HPM_PWM0
+#define BOARD_APP_ADC16_HW_TRGM              HPM_TRGM0
+#define BOARD_APP_ADC16_HW_TRGM_IN           HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
+#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ      TRGM_TRGOCFG_ADC0_STRGI
+#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT      TRGM_TRGOCFG_ADCX_PTRGI0A
 
 #define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A
 
@@ -229,11 +233,6 @@
 #define BOARD_CALLBACK_TIMER_IRQ      IRQn_GPTMR3
 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3)
 
-/* USB section */
-#define BOARD_USB0_ID_PORT       (HPM_GPIO0)
-#define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOC)
-#define BOARD_USB0_ID_GPIO_PIN   (23)
-
 /*BLDC pwm*/
 
 /*PWM define*/
@@ -258,12 +257,14 @@
 
 /*HALL define*/
 
-#define BOARD_BLDC_HALL_BASE                      HPM_HALL0
-#define BOARD_BLDC_HALL_TRGM                      HPM_TRGM0
-#define BOARD_BLDC_HALL_IRQ                       IRQn_HALL0
-#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC           HPM_TRGM0_INPUT_SRC_TRGM0_P8
-#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC           HPM_TRGM0_INPUT_SRC_TRGM0_P7
-#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC           HPM_TRGM0_INPUT_SRC_TRGM0_P6
+#define BOARD_BLDC_HALL_BASE            HPM_HALL0
+#define BOARD_BLDC_HALL_TRGM            HPM_TRGM0
+#define BOARD_BLDC_HALL_IRQ             IRQn_HALL0
+#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P6
+#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P7
+#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P8
+/**< The default value is 0. When this value is defined, it means that the development board wiring sequence is different from the others. */
+#define BOARD_BLDC_HALL_DIR_INV                   (1)
 #define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U)
 
 /*QEI*/
@@ -283,8 +284,25 @@
 #define BOARD_BLDC_TMR_CH     0
 #define BOARD_BLDC_TMR_CMP    0
 #define BOARD_BLDC_TMR_IRQ    IRQn_GPTMR2
+#define BOARD_BLDC_TMR_CLOCK  clock_gptmr2
 #define BOARD_BLDC_TMR_RELOAD (100000U)
 
+/* BLDC PARAM */
+#define BOARD_BLDC_BLOCK_SPEED_KP (0.0005f)
+#define BOARD_BLDC_BLOCK_SPEED_KI (0.000009f)
+
+#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KP (0.0074f)
+#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KI (0.0001f)
+#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KP (0.05f)
+#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KI (0.001f)
+#define BOARD_BLDC_SW_FOC_POSITION_KP (154.7f)
+#define BOARD_BLDC_SW_FOC_POSITION_KI (0.113f)
+
+#define BOARD_BLDC_HFI_SPEED_LOOP_KP (40.0f)
+#define BOARD_BLDC_HFI_SPEED_LOOP_KI (0.015f)
+#define BOARD_BLDC_HFI_PLL_KP (10.0f)
+#define BOARD_BLDC_HFI_PLL_KI (1.0f)
+
 /*adc*/
 #define BOARD_BLDC_ADC_MODULE    ADCX_MODULE_ADC16
 #define BOARD_BLDC_ADC_U_BASE    HPM_ADC0
@@ -300,8 +318,9 @@
 #define BOARD_BLDC_ADC_TRG                    ADC16_CONFIG_TRG0A
 #define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN       (1U)
 #define BOARD_BLDC_PWM_TRIG_CMP_INDEX         (8U)
-#define BOARD_BLDC_TRIGMUX_IN_NUM             HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
-#define BOARD_BLDC_TRG_NUM                    TRGM_TRGOCFG_ADCX_PTRGI0A
+#define BOARD_BLDC_TRG_ADC                    TRGM_TRGOCFG_ADCX_PTRGI0A
+#define BOARD_BLDC_PWM_TRG_ADC                HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
+
 
 /*PLA*/
 #define BOARD_PLA_COUNTER        HPM_PLA0
@@ -315,6 +334,10 @@
 #define BOARD_PLA_PWM_CMP        (8U)
 #define BOARD_PLA_PWM_CHN        (8U)
 
+#define BOARD_PLA_PWM_IN_CHN            pla_filter1_inchn0
+#define BOARD_PLA_LEVEL1_FILTER_IN_END  pla_filter1_inchn7
+#define BOARD_PLA_LEVEL1_FILTER_OUT_END pla_filter1_outchn7
+
 /* APP PWM */
 #define BOARD_APP_PWM             HPM_PWM0
 #define BOARD_APP_PWM_CLOCK_NAME  clock_mot0
@@ -325,13 +348,17 @@
 #define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM_SYNCI
 
 /* APP HRPWM */
-#define BOARD_APP_HRPWM            HPM_PWM1
-#define BOARD_APP_HRPWM_CLOCK_NAME clock_mot1
-#define BOARD_APP_HRPWM_OUT1       0
-#define BOARD_APP_HRPWM_OUT2       2
-#define BOARD_APP_HRPWM_TRGM       HPM_TRGM1
-
-#define BOARD_CPU_FREQ (480000000UL)
+#define BOARD_APP_HRPWM                     HPM_PWM1
+#define BOARD_APP_HRPWM_CLOCK_NAME          clock_mot1
+#define BOARD_APP_HRPWM_OUT1                0
+#define BOARD_APP_HRPWM_OUT2                2
+#define BOARD_APP_HRPWM_TRGM                HPM_TRGM1
+#define BOARD_APP_HRPWM_FAULT_CAP_CMP_INDEX (15U)
+#define BOARD_APP_HRPWM_IRQ                 IRQn_PWM1
+#define BOARD_APP_HRPWM_FAULT_TRGM_SRC      HPM_TRGM0_INPUT_SRC_DEBUG_FLAG
+#define BOARD_APP_HRPWM_FAULT_TRGM_OUT      TRGM_TRGOCFG_PWM_IN15
+
+#define BOARD_CPU_FREQ (600000000UL)
 
 /* LED */
 #define BOARD_R_GPIO_CTRL  HPM_GPIO0
@@ -355,6 +382,7 @@
 /* Key Section */
 #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ
 #define BOARD_APP_GPIO_PIN   2
+#define BOARD_BUTTON_PRESSED_VALUE 0
 
 /* RGB LED Section */
 #define BOARD_RED_PWM_IRQ              IRQn_PWM3
@@ -498,15 +526,65 @@
 #define BOARD_FREERTOS_TIMER_IRQ      IRQn_GPTMR1
 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr1
 
+#define BOARD_FREERTOS_TICK_SRC_PWM          HPM_PWM0
+#define BOARD_FREERTOS_TICK_SRC_PWM_IRQ      IRQn_PWM0
+#define BOARD_FREERTOS_TICK_SRC_PWM_CLK_NAME clock_mot0
+
+#define BOARD_FREERTOS_LOWPOWER_TIMER          HPM_PTMR
+#define BOARD_FREERTOS_LOWPOWER_TIMER_CHANNEL  1
+#define BOARD_FREERTOS_LOWPOWER_TIMER_IRQ      IRQn_PTMR
+#define BOARD_FREERTOS_LOWPOWER_TIMER_CLK_NAME clock_ptmr
+
 /* Threadx Definitions */
-#define BOARD_THREADX_TIMER           HPM_GPTMR1
-#define BOARD_THREADX_TIMER_CHANNEL   1
-#define BOARD_THREADX_TIMER_IRQ       IRQn_GPTMR1
-#define BOARD_THREADX_TIMER_CLK_NAME  clock_gptmr1
+#define BOARD_THREADX_TIMER          HPM_GPTMR1
+#define BOARD_THREADX_TIMER_CHANNEL  1
+#define BOARD_THREADX_TIMER_IRQ      IRQn_GPTMR1
+#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr1
+
+#define BOARD_THREADX_LOWPOWER_TIMER          HPM_PTMR
+#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL  1
+#define BOARD_THREADX_LOWPOWER_TIMER_IRQ      IRQn_PTMR
+#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr
+
+/* uC/OS-III Definitions */
+#define BOARD_UCOS_TIMER          HPM_GPTMR1
+#define BOARD_UCOS_TIMER_CHANNEL  1
+#define BOARD_UCOS_TIMER_IRQ      IRQn_GPTMR1
+#define BOARD_UCOS_TIMER_CLK_NAME clock_gptmr1
 /* Tamper Section */
 #define BOARD_TAMP_ACTIVE_CH    4
 #define BOARD_TAMP_LOW_LEVEL_CH 6
 
+/* i2s over spi Section*/
+#define BOARD_I2S_SPI_CS_GPIO_CTRL  HPM_GPIO0
+#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOB
+#define BOARD_I2S_SPI_CS_GPIO_PIN   31
+#define BOARD_I2S_SPI_CS_GPIO_PAD   IOC_PAD_PB31
+
+#define BOARD_GPTMR_I2S_MCLK          HPM_GPTMR1
+#define BOARD_GPTMR_I2S_MCLK_CHANNEL  0
+#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr1
+
+#define BOARD_GPTMR_I2S_LRCK          HPM_GPTMR1
+#define BOARD_GPTMR_I2S_LRCK_CHANNEL  1
+#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr1
+
+#define BOARD_GPTMR_I2S_BCLK          HPM_GPTMR1
+#define BOARD_GPTMR_I2S_BLCK_CHANNEL  2
+#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr1
+
+#define BOARD_GPTMR_I2S_FINSH          HPM_GPTMR1
+#define BOARD_GPTMR_I2S_FINSH_IRQ      IRQn_GPTMR1
+#define BOARD_GPTMR_I2S_FINSH_CHANNEL  3
+#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr1
+
+/* BGPR */
+#define BOARD_BGPR HPM_BGPR
+
+#define BOARD_APP_CLK_REF_PIN_NAME "J1[4] (PA14)"
+#define BOARD_APP_CLK_REF_CLK_NAME clock_ref0
+
+
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus */
@@ -519,6 +597,7 @@ void board_init_console(void);
 void board_init_core1(void);
 
 void board_init_uart(UART_Type *ptr);
+uint32_t board_init_i2c_clock(I2C_Type *ptr);
 void board_init_i2c(I2C_Type *ptr);
 
 void board_init_can(MCAN_Type *ptr);
@@ -540,26 +619,24 @@ void board_led_toggle(void);
 /* Initialize SoC overall clocks */
 void board_init_clock(void);
 
-uint32_t board_init_gptmr_clock(GPTMR_Type *ptr);
-
 uint32_t board_init_spi_clock(SPI_Type *ptr);
 
 void board_init_lin_pins(LIN_Type *ptr);
 uint32_t board_init_lin_clock(LIN_Type *ptr);
 
-uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb);
+uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus);
+
+void board_init_acmp_clock(ACMP_Type *ptr);
 
 uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb);
 
 void board_init_adc16_pins(void);
-
+void board_init_acmp_pins(void);
 void board_init_dac_pins(DAC_Type *ptr);
 
 uint32_t board_init_can_clock(MCAN_Type *ptr);
 
-void board_init_usb_pins(void);
-void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level);
-uint8_t board_get_usb_id_status(void);
+void board_init_usb(USB_Type *ptr);
 
 /*
  * @brief Initialize PMP and PMA for but not limited to the following purposes:
@@ -576,7 +653,11 @@ void board_ungate_mchtmr_at_lp_mode(void);
 /* Initialize the UART clock */
 uint32_t board_init_uart_clock(UART_Type *ptr);
 
-uint32_t board_init_pwm_clock(PWM_Type *ptr);
+void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp);
+
+void board_init_clk_ref_pin(void);
+
+uint32_t board_init_gptmr_clock(GPTMR_Type *ptr);
 
 #if defined(__cplusplus)
 }

bsp/hpmicro/hpm6200evk/board/linker_scripts/flash_rtt.ld → bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_rtt.ld

@@ -1,5 +1,5 @@
 /*
- * Copyright 2021-2023 HPMicro
+ * Copyright 2021-2025 HPMicro
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
@@ -44,22 +44,26 @@ SECTIONS
     .start __app_load_addr__ : {
         . = ALIGN(8);
         KEEP(*(.start))
+        . = ALIGN(16);
     } > XPI0
 
     __vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
     .vectors : AT(__vector_load_addr__) {
-        . = ALIGN(8);
+        . = ALIGN(16);
         __vector_ram_start__ = .;
         KEEP(*(.vector_table))
         KEEP(*(.isr_vector))
-        . = ALIGN(8);
+
+        . = ALIGN(16);
         __vector_ram_end__ = .;
     } > ILM
 
-    .fast : AT(etext + __data_end__ - __tdata_start__) {
-        . = ALIGN(8);
+    .fast : AT(__fast_load_addr__) {
+        . = ALIGN(16);
         __ramfunc_start__ = .;
         *(.fast)
+        *(.fast.*)
+        . = ALIGN(16);
 
         /* RT-Thread Core Start */
         KEEP(*context_gcc.o(.text* .rodata*))
@@ -80,12 +84,12 @@ SECTIONS
         KEEP(*mempool.o (.text .text* .rodata .rodata*))
         /* RT-Thread Core End */
 
-        . = ALIGN(8);
+        . = ALIGN(16);
         __ramfunc_end__ = .;
     } > ILM
 
-    .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
-        . = ALIGN(8);
+    .text (__vector_load_addr__ + SIZEOF(.vectors)) : {
+        . = ALIGN(16);
         *(.text)
         *(.text*)
         *(.rodata)
@@ -110,12 +114,6 @@ SECTIONS
          *      RT-Thread related sections - Start
          *
         *********************************************/
-        /* section information for utest */
-        . = ALIGN(4);
-        __rt_utest_tc_tab_start = .;
-        KEEP(*(UtestTcTab))
-        __rt_utest_tc_tab_end = .;
-
         /* section information for finsh shell */
         . = ALIGN(4);
         __fsymtab_start = .;
@@ -149,6 +147,20 @@ SECTIONS
 
     } > XPI0
 
+    .eh_frame :
+    {
+        __eh_frame_start = .;
+        KEEP(*(.eh_frame))
+        __eh_frame_end = .;
+    }  > XPI0
+
+    .eh_frame_hdr :
+    {
+        KEEP(*(.eh_frame_hdr))
+    }  > XPI0
+    __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0;
+    __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0;
+
     .rel : {
         KEEP(*(.rel*))
     } > XPI0
@@ -161,6 +173,16 @@ SECTIONS
         KEEP(*(.fast_ram))
     } > DLM
 
+    __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
+        .fast_ram.init : AT(__fast_ram_init_load_addr__) {
+        . = ALIGN(8);
+        __fast_ram_init_start__ = .;
+        KEEP(*(.fast_ram.init))
+        KEEP(*(.fast_ram.init.*))
+        __fast_ram_init_end__ = .;
+        . = ALIGN(8);
+    } > DLM
+
     .bss(NOLOAD) : {
         . = ALIGN(8);
         __bss_start__ = .;
@@ -181,22 +203,26 @@ SECTIONS
         . = ALIGN(8);
         __tbss_start__ = .;
         *(.tbss*)
+        *(.gnu.linkonce.tb.*)
         *(.tcommon*)
         _end = .;
         __tbss_end__ = .;
     } > DLM
 
-    .tdata : AT(etext) {
+    __tdata_load_addr__ = etext;
+    .tdata : AT(__tdata_load_addr__) {
         . = ALIGN(8);
         __tdata_start__ = .;
         __thread_pointer = .;
         *(.tdata)
         *(.tdata*)
+        *(.gnu.linkonce.td.*)
         . = ALIGN(8);
         __tdata_end__ = .;
     } > DLM
 
-    .data : AT(etext + __tdata_end__ - __tdata_start__) {
+    __data_load_addr__ = etext + SIZEOF(.tdata);
+    .data : AT(__data_load_addr__) {
         . = ALIGN(8);
         __data_start__ = .;
         __global_pointer$ = . + 0x800;
@@ -224,10 +250,10 @@ SECTIONS
         PROVIDE(__init_array_end = .);
 
         . = ALIGN(8);
-        PROVIDE(__finit_array_start = .);
-        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
-        KEEP(*(.finit_array))
-        PROVIDE(__finit_array_end = .);
+        PROVIDE(__fini_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE(__fini_array_end = .);
 
         . = ALIGN(8);
         PROVIDE(__ctors_start__ = .);
@@ -248,7 +274,10 @@ SECTIONS
         PROVIDE (_edata = .);
         PROVIDE (edata = .);
     } > DLM
-    __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
+    __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata);
+
+    __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr);
+
 
     .heap(NOLOAD) : {
         . = ALIGN(8);
@@ -268,7 +297,8 @@ SECTIONS
         PROVIDE( __rt_rvstack = . );
     } > DLM
 
-    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
+    __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
+    .noncacheable.init : AT(__noncacheable_init_load_addr__) {
         . = ALIGN(8);
         __noncacheable_init_start__ = .;
         KEEP(*(.noncacheable.init))
@@ -279,8 +309,11 @@ SECTIONS
     .noncacheable.bss (NOLOAD) : {
         . = ALIGN(8);
         KEEP(*(.noncacheable))
+        KEEP(*(.noncacheable.non_init))
+        KEEP(*(.noncacheable.non_init.*))
         __noncacheable_bss_start__ = .;
         KEEP(*(.noncacheable.bss))
+        KEEP(*(.noncacheable.bss.*))
         __noncacheable_bss_end__ = .;
         . = ALIGN(8);
     } > NONCACHEABLE_RAM

bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_usb_nic.ld

@@ -0,0 +1,330 @@
+/*
+ * Copyright 2021-2025 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 144K;
+FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x4000;
+
+MEMORY
+{
+    XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
+    ILM (wx) : ORIGIN = 0, LENGTH = 128K
+    DLM (w) : ORIGIN = 0x80000, LENGTH = 128K
+    NONCACHEABLE_RAM (wx) : ORIGIN = 0x01080000, LENGTH = 64K
+    AXI_SRAM  (wx) : ORIGIN = 0x01090000, LENGTH = 176K
+    SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K
+    AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
+}
+
+__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
+__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000;
+__app_load_addr__ = ORIGIN(XPI0) + 0x3000;
+__boot_header_length__ = __boot_header_end__ - __boot_header_start__;
+__app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
+
+SECTIONS
+{
+    .nor_cfg_option __nor_cfg_option_load_addr__ : {
+        KEEP(*(.nor_cfg_option))
+    } > XPI0
+
+    .boot_header __boot_header_load_addr__ : {
+        __boot_header_start__ = .;
+        KEEP(*(.boot_header))
+        KEEP(*(.fw_info_table))
+        KEEP(*(.dc_info))
+        __boot_header_end__ = .;
+    } > XPI0
+
+    .start __app_load_addr__ : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+        . = ALIGN(16);
+    } > XPI0
+
+    __vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
+    .vectors : AT(__vector_load_addr__) {
+        . = ALIGN(16);
+        __vector_ram_start__ = .;
+        KEEP(*(.vector_table))
+        KEEP(*(.isr_vector))
+
+        . = ALIGN(16);
+        __vector_ram_end__ = .;
+    } > ILM
+
+    .fast : AT(__fast_load_addr__) {
+        . = ALIGN(16);
+        __ramfunc_start__ = .;
+        *(.fast)
+        *(.fast.*)
+        . = ALIGN(16);
+
+        /* RT-Thread Core Start */
+        KEEP(*context_gcc.o(.text* .rodata*))
+        KEEP(*port*.o (.text .text* .rodata .rodata*))
+        KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*))
+        KEEP(*trap_common.o (.text .text* .rodata .rodata*))
+        KEEP(*irq.o (.text .text* .rodata .rodata*))
+        KEEP(*clock.o (.text .text* .rodata .rodata*))
+        KEEP(*kservice.o (.text .text* .rodata .rodata*))
+        KEEP(*scheduler.o (.text .text* .rodata .rodata*))
+        KEEP(*trap*.o (.text .text* .rodata .rodata*))
+        KEEP(*idle.o (.text .text* .rodata .rodata*))
+        KEEP(*ipc.o (.text .text* .rodata .rodata*))
+        KEEP(*thread.o (.text .text* .rodata .rodata*))
+        KEEP(*object.o (.text .text* .rodata .rodata*))
+        KEEP(*timer.o (.text .text* .rodata .rodata*))
+        KEEP(*mem.o (.text .text* .rodata .rodata*))
+        KEEP(*mempool.o (.text .text* .rodata .rodata*))
+        /* RT-Thread Core End */
+
+        . = ALIGN(16);
+        __ramfunc_end__ = .;
+    } > ILM
+
+    .text (__vector_load_addr__ + SIZEOF(.vectors)) : {
+        . = ALIGN(16);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+        /* section information for usbh class */
+        . = ALIGN(8);
+        __usbh_class_info_start__ = .;
+        KEEP(*(.usbh_class_info))
+        __usbh_class_info_end__ = .;
+
+    } > XPI0
+
+    .eh_frame :
+    {
+        __eh_frame_start = .;
+        KEEP(*(.eh_frame))
+        __eh_frame_end = .;
+    }  > XPI0
+
+    .eh_frame_hdr :
+    {
+        KEEP(*(.eh_frame_hdr))
+    }  > XPI0
+    __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0;
+    __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0;
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > XPI0
+
+    PROVIDE (__etext = .);
+    PROVIDE (_etext = .);
+    PROVIDE (etext = .);
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > ILM
+
+    __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init);
+        .fast_ram.init : AT(__fast_ram_init_load_addr__) {
+        . = ALIGN(8);
+        __fast_ram_init_start__ = .;
+        KEEP(*(.fast_ram.init))
+        KEEP(*(.fast_ram.init.*))
+        __fast_ram_init_end__ = .;
+        . = ALIGN(8);
+    } > DLM
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > DLM
+
+    /* Note: the .tbss and .tdata section should be adjacent */
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.gnu.linkonce.tb.*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > DLM
+
+    __tdata_load_addr__ = etext;
+    .tdata : AT(__tdata_load_addr__) {
+        . = ALIGN(8);
+        __tdata_start__ = .;
+        __thread_pointer = .;
+        *(.tdata)
+        *(.tdata*)
+        *(.gnu.linkonce.td.*)
+        . = ALIGN(8);
+        __tdata_end__ = .;
+    } > DLM
+
+    __data_load_addr__ = etext + SIZEOF(.tdata);
+    .data : AT(__data_load_addr__) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_except_table))
+        KEEP(*(.gcc_except_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__fini_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE(__fini_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > DLM
+    __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata);
+
+    __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr);
+
+
+    .heap(NOLOAD) : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+    } > AXI_SRAM
+
+
+    .stack(NOLOAD) : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        . = ALIGN(8);
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+        PROVIDE( __rt_rvstack = . );
+    } > DLM
+
+    __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast);
+    .noncacheable.init : AT(__noncacheable_init_load_addr__) {
+        . = ALIGN(8);
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .noncacheable.bss (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.noncacheable))
+        KEEP(*(.noncacheable.non_init))
+        KEEP(*(.noncacheable.non_init.*))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        KEEP(*(.noncacheable.bss.*))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .ahb_sram (NOLOAD) : {
+        KEEP(*(.ahb_sram))
+    } > AHB_SRAM
+
+    __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
+    __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
+    __share_mem_start__ = ORIGIN(SHARE_RAM);
+    __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM);
+
+}

bsp/hpmicro/hpm6200evk/board/linker_scripts/ram_rtt.ld → bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/ram_rtt.ld

@@ -1,20 +1,20 @@
 /*
- * Copyright 2021-2023 HPMicro
+ * Copyright 2021-2025 HPMicro
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 ENTRY(_start)
 
 STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x2000;
-HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x8000;
-NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x10000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 32k;
 
 MEMORY
 {
-    ILM (wx) : ORIGIN = 0, LENGTH = 128K
-    DLM (w) : ORIGIN = 0x80000, LENGTH = 96K
-    NONCACHEABLE_RAM (wx) : ORIGIN = 0x90000, LENGTH = NONCACHEABLE_SIZE
-    AXI_SRAM  (wx) : ORIGIN = 0x01084000, LENGTH = 224K
+    ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K
+    DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K
+    NONCACHEABLE_RAM (wx) : ORIGIN = 0x01080000, LENGTH = NONCACHEABLE_SIZE
+    AXI_SRAM  (wx) : ORIGIN = 0x01088000, LENGTH = 208K
     SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K
     AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
 }
@@ -94,11 +94,11 @@ SECTIONS
         PROVIDE (__etext = .);
         PROVIDE (_etext = .);
         PROVIDE (etext = .);
-    } > AXI_SRAM
+    } > ILM
 
     .rel : {
         KEEP(*(.rel*))
-    } > AXI_SRAM
+    } > ILM
 
     .fast_ram (NOLOAD) : {
         KEEP(*(.fast_ram))
@@ -124,22 +124,26 @@ SECTIONS
         . = ALIGN(8);
         __tbss_start__ = .;
         *(.tbss*)
+        *(.gnu.linkonce.tb.*)
         *(.tcommon*)
         _end = .;
         __tbss_end__ = .;
     } > DLM
 
-    .tdata : AT(etext) {
+    __tdata_load_addr__ = etext;
+    .tdata : AT(__tdata_load_addr__) {
         . = ALIGN(8);
         __tdata_start__ = .;
         __thread_pointer = .;
         *(.tdata)
         *(.tdata*)
+        *(.gnu.linkonce.td.*)
         . = ALIGN(8);
         __tdata_end__ = .;
     } > DLM
 
-    .data : AT(etext + __tdata_end__ - __tdata_start__) {
+    __data_load_addr__ = etext + SIZEOF(.tdata);
+    .data : AT(__data_load_addr__) {
         . = ALIGN(8);
         __data_start__ = .;
         __global_pointer$ = . + 0x800;
@@ -167,10 +171,10 @@ SECTIONS
         PROVIDE(__init_array_end = .);
 
         . = ALIGN(8);
-        PROVIDE(__finit_array_start = .);
-        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
-        KEEP(*(.finit_array))
-        PROVIDE(__finit_array_end = .);
+        PROVIDE(__fini_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE(__fini_array_end = .);
 
         . = ALIGN(8);
         PROVIDE(__ctors_start__ = .);
@@ -193,7 +197,18 @@ SECTIONS
         PROVIDE (edata = .);
     } > DLM
 
-    .fast : AT(etext + __data_end__ - __tdata_start__) {
+    __fast_ram_init_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data);
+    .fast_ram.init : AT(__fast_ram_init_load_addr__) {
+        . = ALIGN(8);
+        __fast_ram_init_start__ = .;
+        KEEP(*(.fast_ram.init))
+        KEEP(*(.fast_ram.init.*))
+        __fast_ram_init_end__ = .;
+        . = ALIGN(8);
+    } > DLM
+
+    __fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data) + SIZEOF(.fast_ram.init);
+    .fast : AT(__fast_load_addr__) {
         . = ALIGN(8);
         PROVIDE(__ramfunc_start__ = .);
         *(.fast)
@@ -201,7 +216,8 @@ SECTIONS
         PROVIDE(__ramfunc_end__ = .);
     } > ILM
 
-    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
+    __noncacheable_init_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data) + SIZEOF(.fast_ram.init) + SIZEOF(.fast);
+    .noncacheable.init : AT(__noncacheable_init_load_addr__) {
         . = ALIGN(8);
         __noncacheable_init_start__ = .;
         KEEP(*(.noncacheable.init))
@@ -218,8 +234,11 @@ SECTIONS
     .noncacheable.bss (NOLOAD) : {
         . = ALIGN(8);
         KEEP(*(.noncacheable))
+        KEEP(*(.noncacheable.non_init))
+        KEEP(*(.noncacheable.non_init.*))
         __noncacheable_bss_start__ = .;
         KEEP(*(.noncacheable.bss))
+        KEEP(*(.noncacheable.bss.*))
         __noncacheable_bss_end__ = .;
         . = ALIGN(8);
     } > NONCACHEABLE_RAM
@@ -246,5 +265,6 @@ SECTIONS
         . += HEAP_SIZE;
         __heap_end__ = .;
 
-    } > DLM
+    } > AXI_SRAM
 }
+ASSERT((((__noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init) <= ORIGIN(ILM) + LENGTH(ILM)))), "******  FAILED! ILM does not have enough space!  ******")

bsp/hpmicro/hpm6200evk/board/pinmux.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023 hpmicro
+ * Copyright (c) 2023-2025 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -115,11 +115,12 @@ void init_spi_pins(SPI_Type *ptr)
         HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_SPI1_MOSI;
         HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_SPI1_MISO;
         HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
-    } else if (ptr == HPM_SPI2) {
-        HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_SPI2_CSN;
-        HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_SPI2_MISO;
-        HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_SPI2_MOSI;
-        HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
+
+        /* set max frequency slew rate(200M) */
+        HPM_IOC->PAD[IOC_PAD_PB02].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1);
+        HPM_IOC->PAD[IOC_PAD_PB05].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PB03].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PB04].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
     }
 }
 
@@ -130,11 +131,12 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
         HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_SPI1_MOSI;
         HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_SPI1_MISO;
         HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
-    } else if (ptr == HPM_SPI2) {
-        HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_GPIO_C_22;
-        HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_SPI2_MISO;
-        HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_SPI2_MOSI;
-        HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);;
+
+        /* set max frequency slew rate(200M) */
+        HPM_IOC->PAD[IOC_PAD_PB02].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1);
+        HPM_IOC->PAD[IOC_PAD_PB05].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PB03].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
+        HPM_IOC->PAD[IOC_PAD_PB04].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3);
     }
 }
 
@@ -149,8 +151,18 @@ void init_gptmr_pins(GPTMR_Type *ptr)
 {
     if (ptr == HPM_GPTMR1) {
         HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_GPTMR1_CAPT_0;
+        /* TMR1 compare 0 */
         HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_GPTMR1_COMP_0;
+        /* TMR1 compare 1 */
         HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPTMR1_COMP_1;
+        /* TMR1 compare 2 */
+        HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_TRGM1_P_00;
+        trgm_output_t trgm1_io_config0 = {0};
+        trgm1_io_config0.invert = 0;
+        trgm1_io_config0.type = trgm_output_same_as_input;
+        trgm1_io_config0.input = HPM_TRGM1_INPUT_SRC_GPTMR1_OUT2;
+        trgm_output_config(HPM_TRGM1, HPM_TRGM1_OUTPUT_SRC_TRGM1_P0, &trgm1_io_config0);
+        trgm_enable_io_output(HPM_TRGM1, 1 << 0);
     }
 }
 
@@ -214,10 +226,13 @@ void init_adc_bldc_pins(void)
    HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
 }
 
-void init_usb_pins(void)
+void init_usb_pins(USB_Type *ptr)
 {
-    HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_GPIO_C_23;
-    HPM_IOC->PAD[IOC_PAD_PC23].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1);
+    if (ptr == HPM_USB0) {
+        HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_USB0_ID;
+        HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PC01_FUNC_CTL_USB0_PWR;
+        HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_USB0_OC;
+    }
 }
 
 void  init_can_pins(MCAN_Type *ptr)
@@ -324,3 +339,46 @@ void init_tamper_pins(void)
     HPM_BIOC->PAD[IOC_PAD_PZ04].PAD_CTL &= ~IOC_PAD_PAD_CTL_OD_MASK;
     HPM_BIOC->PAD[IOC_PAD_PZ05].PAD_CTL &= ~IOC_PAD_PAD_CTL_OD_MASK;
 }
+
+/* for uart_rx_line_status case, need to a gpio pin to sent break signal */
+void init_uart_break_signal_pin(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PB02].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+    HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_GPIO_B_02;
+}
+
+void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp)
+{
+    if (ptr == HPM_GPTMR1) {
+        if (as_comp) {
+            switch (channel) {
+            case 0:
+                HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_GPTMR1_COMP_0;
+                break;
+            case 1:
+                HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPTMR1_COMP_1;
+                break;
+            case 2:
+                HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_TRGM1_P_00;
+                trgm_output_t trgm1_io_config0 = {0};
+                trgm1_io_config0.invert = 0;
+                trgm1_io_config0.type = trgm_output_same_as_input;
+                trgm1_io_config0.input = HPM_TRGM1_INPUT_SRC_GPTMR1_OUT2;
+                trgm_output_config(HPM_TRGM1, HPM_TRGM1_OUTPUT_SRC_TRGM1_P0, &trgm1_io_config0);
+                trgm_enable_io_output(HPM_TRGM1, 1 << 0);
+                break;
+            default:
+                break;
+            }
+        } else {
+            if (channel == 0) {
+                HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_GPTMR1_CAPT_0;
+            }
+        }
+    }
+}
+
+void init_clk_ref_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_SOC_REF0;
+}

bsp/hpmicro/hpm6200evk/board/pinmux.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 hpmicro
+ * Copyright (c) 2022-2025 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -27,7 +27,7 @@ void init_pwm_pins(PWM_Type *ptr);
 void init_hrpwm_pins(PWM_Type *ptr);
 void init_adc_pins(void);
 void init_dac_pins(DAC_Type *ptr);
-void init_usb_pins(void);
+void init_usb_pins(USB_Type *ptr);
 void init_can_pins(MCAN_Type *ptr);
 void init_adc_bldc_pins(void);
 void init_rgb_pwm_pins(void);
@@ -41,7 +41,9 @@ void init_sdm_pins(void);
 void init_pla_tamagawa_pins(void);
 void init_motor_over_zero_sensorless_adc_pins(void);
 void init_tamper_pins(void);
-
+void init_uart_break_signal_pin(void);
+void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp);
+void init_clk_ref_pins(void);
 #ifdef __cplusplus
 }
 #endif

bsp/hpmicro/hpm6200evk/board/rtt_board.c

@@ -60,6 +60,7 @@ void rtt_board_init(void)
 
 void app_init_led_pins(void)
 {
+    board_init_led_pins();
     gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
     gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL);
 }
@@ -93,7 +94,7 @@ void rt_hw_console_output(const char *str)
 
 void app_init_usb_pins(void)
 {
-    board_init_usb_pins();
+    board_init_usb(HPM_USB0);
 }
 
 ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
@@ -105,7 +106,7 @@ ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
 
 void rt_hw_cpu_reset(void)
 {
-    HPM_PPOR->RESET_ENABLE = (1UL << 31);
+    HPM_PPOR->RESET_ENABLE |= (1UL << 31);
     HPM_PPOR->RESET_HOT &= ~(1UL << 31);
     HPM_PPOR->RESET_COLD |= (1UL << 31);
 
@@ -127,3 +128,94 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
     }
 }
 #endif
+
+uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
+{
+    uint32_t freq = 0;
+
+    if (ptr == HPM_ADC0) {
+        if (clk_src_ahb) {
+            /* Configure the ADC clock from AHB (@200MHz by default)*/
+            clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
+        } else {
+            /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
+            clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
+            clock_set_source_divider(clock_ana0, clk_src_pll0_clk0, 2U);
+        }
+        clock_add_to_group(clock_adc0, 0);
+        freq = clock_get_frequency(clock_adc0);
+    } else if (ptr == HPM_ADC1) {
+        if (clk_src_ahb) {
+            /* Configure the ADC clock from AHB (@200MHz by default)*/
+            clock_set_adc_source(clock_adc1, clk_adc_src_ahb0);
+        } else {
+            /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
+            clock_set_adc_source(clock_adc1, clk_adc_src_ana1);
+            clock_set_source_divider(clock_ana1, clk_src_pll0_clk0, 2U);
+        }
+        clock_add_to_group(clock_adc1, 0);
+        freq = clock_get_frequency(clock_adc1);
+    } else if (ptr == HPM_ADC2) {
+        if (clk_src_ahb) {
+            /* Configure the ADC clock from AHB (@200MHz by default)*/
+            clock_set_adc_source(clock_adc2, clk_adc_src_ahb0);
+        } else {
+            /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
+            clock_set_adc_source(clock_adc2, clk_adc_src_ana2);
+            clock_set_source_divider(clock_ana2, clk_src_pll0_clk0, 2U);
+        }
+        clock_add_to_group(clock_adc2, 0);
+        freq = clock_get_frequency(clock_adc2);
+    }
+
+    return freq;
+}
+
+uint32_t rtt_board_init_pwm_clock(PWM_Type *ptr)
+{
+    uint32_t freq = 0;
+    if (ptr == HPM_PWM0) {
+        clock_add_to_group(clock_mot0, 0);
+        freq = clock_get_frequency(clock_mot0);
+    } else if (ptr == HPM_PWM1) {
+        clock_add_to_group(clock_mot1, 0);
+        freq = clock_get_frequency(clock_mot1);
+    } else if (ptr == HPM_PWM2) {
+        clock_add_to_group(clock_mot2, 0);
+        freq = clock_get_frequency(clock_mot2);
+    } else if (ptr == HPM_PWM3) {
+        clock_add_to_group(clock_mot3, 0);
+        freq = clock_get_frequency(clock_mot3);
+    } else {
+
+    }
+    return freq;
+}
+
+#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER
+extern void hpm_isr_usb0(void);
+RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0)
+#endif
+
+
+void hpm_usb_isr_enable(uint32_t base)
+{
+    if (base == HPM_USB0_BASE) {
+        intc_m_enable_irq_with_priority(IRQn_USB0, 4);
+    } else {
+#ifdef HPM_USB1_BASE
+        intc_m_enable_irq_with_priority(IRQn_USB1, 4);
+#endif
+    }
+}
+
+void hpm_usb_isr_disable(uint32_t base)
+{
+    if (base == HPM_USB0_BASE) {
+        intc_m_disable_irq(IRQn_USB0);
+    } else {
+#ifdef HPM_USB1_BASE
+        intc_m_disable_irq(IRQn_USB1);
+#endif
+    }
+}

bsp/hpmicro/hpm6200evk/board/rtt_board.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 hpmicro
+ * Copyright (c) 2021 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -10,8 +10,10 @@
 #include "hpm_common.h"
 #include "hpm_soc.h"
 #include <drv_gpio.h>
+#include "board.h"
 
 /* gpio section */
+#define APP_LED0         (0U)
 #define APP_LED0_PIN_NUM GET_PIN(B, 19)
 #define APP_LED_ON (1)
 #define APP_LED_OFF (0)
@@ -21,6 +23,12 @@
 /* mchtimer section */
 #define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
 
+/* gptmr as os_tick */
+#define BOARD_OS_TIMER HPM_GPTMR0
+#define BOARD_OS_TIMER_CH       1
+#define BOARD_OS_TIMER_IRQ      IRQn_GPTMR0
+#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0)
+
 /* CAN section */
 #define BOARD_CAN_NAME                        "can0"
 #define BOARD_CAN_HWFILTER_INDEX               (0U)
@@ -33,6 +41,10 @@
 #define BOARD_PWM_NAME                        "pwm0"
 #define BOARD_PWM_CHANNEL                     (0)
 
+/* ADC section */
+#define BOARD_ADC_NAME                        BOARD_APP_ADC16_NAME
+#define BOARD_ADC_CHANNEL                     BOARD_APP_ADC16_CH_1
+
 #define IRQn_PendSV IRQn_DEBUG_0
 
 /***************************************************************

bsp/hpmicro/hpm6200evk/rtconfig.h

@@ -61,7 +61,7 @@
 
 /* end of rt_strnlen options */
 /* end of klibc options */
-#define RT_NAME_MAX 8
+#define RT_NAME_MAX 16
 #define RT_CPUS_NR 1
 #define RT_ALIGN_SIZE 8
 #define RT_THREAD_PRIORITY_32
@@ -75,6 +75,7 @@
 #define RT_USING_TIMER_SOFT
 #define RT_TIMER_THREAD_PRIO 4
 #define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_USING_CPU_USAGE_TRACER
 
 /* kservice options */
 
@@ -103,6 +104,8 @@
 #define RT_VER_NUM 0x50201
 #define RT_BACKTRACE_LEVEL_MAX_NR 32
 /* end of RT-Thread Kernel */
+#define ARCH_RISCV
+#define ARCH_RISCV32
 
 /* RT-Thread Components */
 
@@ -110,6 +113,7 @@
 #define RT_USING_USER_MAIN
 #define RT_MAIN_THREAD_STACK_SIZE 2048
 #define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_LEGACY
 #define RT_USING_MSH
 #define RT_USING_FINSH
 #define FINSH_USING_MSH
@@ -127,14 +131,6 @@
 
 /* DFS: device virtual file system */
 
-#define RT_USING_DFS
-#define DFS_USING_POSIX
-#define DFS_USING_WORKDIR
-#define DFS_FD_MAX 16
-#define RT_USING_DFS_V1
-#define DFS_FILESYSTEMS_MAX 4
-#define DFS_FILESYSTEM_TYPES_MAX 4
-#define RT_USING_DFS_DEVFS
 /* end of DFS: device virtual file system */
 
 /* Device Drivers */
@@ -142,9 +138,9 @@
 #define RT_USING_DEVICE_IPC
 #define RT_UNAMED_PIPE_NUMBER 64
 #define RT_USING_SERIAL
-#define RT_USING_SERIAL_V1
+#define RT_USING_SERIAL_V2
+#define RT_SERIAL_BUF_STRATEGY_OVERWRITE
 #define RT_SERIAL_USING_DMA
-#define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_PIN
 /* end of Device Drivers */
 
@@ -307,6 +303,20 @@
 /* NXP HAL & SDK Drivers */
 
 /* end of NXP HAL & SDK Drivers */
+
+/* NUVOTON Drivers */
+
+/* end of NUVOTON Drivers */
+
+/* GD32 Drivers */
+
+/* end of GD32 Drivers */
+
+/* HPMicro SDK */
+
+#define PKG_USING_HPM_SDK
+#define PKG_USING_HPM_SDK_LATEST_VERSION
+/* end of HPMicro SDK */
 /* end of HAL & SDK Drivers */
 
 /* sensors drivers */
@@ -386,16 +396,19 @@
 
 /* end of Arduino libraries */
 /* end of RT-Thread online packages */
+#define SOC_HPM6200_SERIES
 
 /* Hardware Drivers Config */
 
-#define SOC_HPM6000
+#define SOC_HPM6200
 
 /* On-chip Peripheral Drivers */
 
 #define BSP_USING_GPIO
 #define BSP_USING_UART
 #define BSP_USING_UART0
+#define BSP_UART0_RX_BUFSIZE 128
+#define BSP_UART0_TX_BUFSIZE 0
 /* end of On-chip Peripheral Drivers */
 /* end of Hardware Drivers Config */
 

bsp/hpmicro/hpm6200evk/rtconfig.py

@@ -1,8 +1,41 @@
-# Copyright 2021-2023 HPMicro
+# Copyright 2021-2025 HPMicro
 # SPDX-License-Identifier: BSD-3-Clause
 
 import os
 import sys
+import rtconfig
+
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+def bsp_pkg_check():
+    import subprocess
+    
+    need_update = True
+    for p in os.listdir("packages"):
+        if p.startswith("hpm_sdk-"):
+            need_update = False
+            break
+    if need_update:
+        print("\n===============================================================================")
+        print("Dependency packages missing, please running 'pkgs --update'...")
+        print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
+        print("===============================================================================")
+        exit(1)
+
+RegisterPreBuildingAction(bsp_pkg_check)
+
 
 # toolchains options
 ARCH='risc-v'
@@ -80,27 +113,27 @@ if PLATFORM == 'gcc':
         AFLAGS += ' -gdwarf-2'
         CFLAGS += ' -O0'
         LFLAGS += ' -O0'
-        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+        LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld'
     elif BUILD == 'ram_release':
         CFLAGS += ' -O2'
         LFLAGS += ' -O2'
-        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+        LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld'
     elif BUILD == 'flash_debug':
         CFLAGS += ' -gdwarf-2'
         AFLAGS += ' -gdwarf-2'
         CFLAGS += ' -O0'
         LFLAGS += ' -O0'
         CFLAGS += ' -DFLASH_XIP=1'
-        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+        LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
     elif BUILD == 'flash_release':
         CFLAGS += ' -O2'
         LFLAGS += ' -O2'
         CFLAGS += ' -DFLASH_XIP=1'
-        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+        LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
     else:
         CFLAGS += ' -O2'
         LFLAGS += ' -O2'
-        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+        LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld'
     LFLAGS += ' -T ' + LINKER_FILE
 
     POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

bsp/hpmicro/hpm6200evk/startup/HPM6280/startup.c

@@ -1,128 +1,135 @@
 /*
- * Copyright (c) 2021-2023 HPMicro
+ * Copyright (c) 2021-2025 HPMicro
  *
  *
  */
 
-#include "hpm_common.h"
-#include "hpm_soc.h"
-#include "hpm_l1c_drv.h"
-#include <rtthread.h>
-
-void system_init(void);
-
-extern int entry(void);
-
-extern void __libc_init_array(void);
-extern void __libc_fini_array(void);
-
-void system_init(void)
-{
-    disable_global_irq(CSR_MSTATUS_MIE_MASK);
-    disable_irq_from_intc();
-    enable_irq_from_intc();
-    enable_global_irq(CSR_MSTATUS_MIE_MASK);
-#ifndef CONFIG_NOT_ENABLE_ICACHE
-    l1c_ic_enable();
-#endif
-#ifndef CONFIG_NOT_ENABLE_DCACHE
-    l1c_dc_enable();
-#endif
-}
-
-__attribute__((weak)) void c_startup(void)
-{
-    uint32_t i, size;
-#ifdef FLASH_XIP
-    extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
-    size = __vector_ram_end__ - __vector_ram_start__;
-    for (i = 0; i < size; i++) {
-        *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
-    }
-#endif
-
-    extern uint8_t __etext[];
-    extern uint8_t __bss_start__[], __bss_end__[];
-    extern uint8_t __tbss_start__[], __tbss_end__[];
-    extern uint8_t __tdata_start__[], __tdata_end__[];
-    extern uint8_t __data_start__[], __data_end__[];
-    extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
-    extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
-    extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
-
-    /* tbss section */
-    size = __tbss_end__ - __tbss_start__;
-    for (i = 0; i < size; i++) {
-        *(__tbss_start__ + i) = 0;
-    }
-
-    /* bss section */
-    size = __bss_end__ - __bss_start__;
-    for (i = 0; i < size; i++) {
-        *(__bss_start__ + i) = 0;
-    }
-
-    /* noncacheable bss section */
-    size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
-    for (i = 0; i < size; i++) {
-        *(__noncacheable_bss_start__ + i) = 0;
-    }
-
-    /* tdata section LMA: etext */
-    size = __tdata_end__ - __tdata_start__;
-    for (i = 0; i < size; i++) {
-        *(__tdata_start__ + i) = *(__etext + i);
-    }
-
-    /* data section LMA: etext */
-    size = __data_end__ - __data_start__;
-    for (i = 0; i < size; i++) {
-        *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i);
-    }
-
-    /* ramfunc section LMA: etext + data length */
-    size = __ramfunc_end__ - __ramfunc_start__;
-    for (i = 0; i < size; i++) {
-        *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i);
-    }
-
-    /* noncacheable init section LMA: etext + data length + ramfunc length */
-    size = __noncacheable_init_end__ - __noncacheable_init_start__;
-    for (i = 0; i < size; i++) {
-        *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
-    }
-}
-
-__attribute__((weak)) int main(void)
-{
-    while(1);
-}
-
-void reset_handler(void)
-{
-    /**
-     * Disable preemptive interrupt
-     */
-    HPM_PLIC->FEATURE = 0;
-    /*
-     * Initialize LMA/VMA sections.
-     * Relocation for any sections that need to be copied from LMA to VMA.
-     */
-    c_startup();
-
-    /* Call platform specific hardware initialization */
-    system_init();
-
-    /* Do global constructors */
-    __libc_init_array();
-
-
-
-    /* Entry function */
-    entry();
-}
-
-
-__attribute__((weak)) void _init()
-{
-}
+ #include "hpm_common.h"
+ #include "hpm_soc.h"
+ #include "hpm_l1c_drv.h"
+ #include <rtthread.h>
+ 
+ void system_init(void);
+ 
+ extern int entry(void);
+ 
+ extern void __libc_init_array(void);
+ extern void __libc_fini_array(void);
+ 
+ void system_init(void)
+ {
+     disable_global_irq(CSR_MSTATUS_MIE_MASK);
+     disable_irq_from_intc();
+     enable_irq_from_intc();
+     enable_global_irq(CSR_MSTATUS_MIE_MASK);
+ #ifndef CONFIG_NOT_ENABLE_ICACHE
+     l1c_ic_enable();
+ #endif
+ #ifndef CONFIG_NOT_ENABLE_DCACHE
+     l1c_dc_enable();
+ #endif
+ }
+ 
+ __attribute__((weak)) void c_startup(void)
+ {
+ #ifndef __SES_RISCV
+     uint32_t i, size;
+ #ifdef FLASH_XIP
+     extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
+     size = __vector_ram_end__ - __vector_ram_start__;
+     for (i = 0; i < size; i++) {
+         *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
+     }
+ #endif
+ 
+     extern uint8_t __etext[];
+     extern uint8_t __bss_start__[], __bss_end__[];
+     extern uint8_t __tbss_start__[], __tbss_end__[];
+     extern uint8_t __tdata_start__[], __tdata_end__[];
+     extern uint8_t __fast_load_addr__[];
+     extern uint8_t __noncacheable_init_load_addr__[];
+     extern uint8_t __data_load_addr__[];
+     extern uint8_t __tdata_load_addr__[];
+     extern uint8_t __data_start__[], __data_end__[];
+     extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
+     extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
+     extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
+ 
+     /* tbss section */
+     size = __tbss_end__ - __tbss_start__;
+     for (i = 0; i < size; i++) {
+         *(__tbss_start__ + i) = 0;
+     }
+ 
+     /* bss section */
+     size = __bss_end__ - __bss_start__;
+     for (i = 0; i < size; i++) {
+         *(__bss_start__ + i) = 0;
+     }
+ 
+     /* noncacheable bss section */
+     size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
+     for (i = 0; i < size; i++) {
+         *(__noncacheable_bss_start__ + i) = 0;
+     }
+ 
+     /* tdata section LMA: etext */
+     size = __tdata_end__ - __tdata_start__;
+     for (i = 0; i < size; i++) {
+         *(__tdata_start__ + i) = *(__tdata_load_addr__ + i);
+     }
+ 
+     /* data section LMA: etext */
+     size = __data_end__ - __data_start__;
+     for (i = 0; i < size; i++) {
+         *(__data_start__ + i) = *(__data_load_addr__ + i);
+     }
+ 
+     /* ramfunc section LMA: etext + data length */
+     size = __ramfunc_end__ - __ramfunc_start__;
+     for (i = 0; i < size; i++) {
+         *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i);
+     }
+ 
+     /* noncacheable init section LMA: etext + data length + ramfunc length */
+     size = __noncacheable_init_end__ - __noncacheable_init_start__;
+     for (i = 0; i < size; i++) {
+         *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i);
+     }
+ #endif
+ }
+ 
+ __attribute__((weak)) int main(void)
+ {
+     while(1);
+ }
+ 
+ void reset_handler(void)
+ {
+     /**
+      * Disable preemptive interrupt
+      */
+     HPM_PLIC->FEATURE = 0;
+     /*
+      * Initialize LMA/VMA sections.
+      * Relocation for any sections that need to be copied from LMA to VMA.
+      */
+     c_startup();
+ 
+     /* Call platform specific hardware initialization */
+     system_init();
+ 
+ #ifndef __SES_RISCV
+     /* Do global constructors */
+     __libc_init_array();
+ #endif
+ 
+     /* Entry function */
+     entry();
+ }
+ 
+ 
+ __attribute__((weak)) void _init(void)
+ {
+ }
+ 

bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/port_gcc.S

@@ -5,7 +5,8 @@
  *
  */
 #include "cpuport.h"
-
+    .section .text.entry, "ax"
+    .align  2
     .globl rt_hw_do_after_save_above
     .type rt_hw_do_after_save_above,@function
 rt_hw_do_after_save_above:

bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/start.S

@@ -54,7 +54,6 @@ _start:
 nmi_handler:
 1:    j 1b
 
-    .global default_irq_handler
     .weak default_irq_handler
     .align 2
 default_irq_handler: