[bsp][lpc55sxx] update NXP SDK to 2_12_0

update NXP SDK to 2_12_0

bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_armcc.h → bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armcc.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_armcc.h
  * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
- * @version  V5.0.4
- * @date     10. January 2018
+ * @version  V5.3.2
+ * @date     27. May 2021
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -46,7 +46,12 @@
 
   /* __ARM_ARCH_8M_BASE__  not applicable */
   /* __ARM_ARCH_8M_MAIN__  not applicable */
+  /* __ARM_ARCH_8_1M_MAIN__  not applicable */
 
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __ARM_FEATURE_DSP         1
+#endif
 
 /* CMSIS compiler specific defines */
 #ifndef   __ASM
@@ -58,9 +63,9 @@
 #ifndef   __STATIC_INLINE
   #define __STATIC_INLINE                        static __inline
 #endif
-#ifndef   __STATIC_FORCEINLINE                 
+#ifndef   __STATIC_FORCEINLINE
   #define __STATIC_FORCEINLINE                   static __forceinline
-#endif           
+#endif
 #ifndef   __NO_RETURN
   #define __NO_RETURN                            __declspec(noreturn)
 #endif
@@ -100,284 +105,31 @@
 #ifndef   __RESTRICT
   #define __RESTRICT                             __restrict
 #endif
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq();     */
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq();    */
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xFFU);
-}
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  register uint32_t __regBasePriMax      __ASM("basepri_max");
-  __regBasePriMax = (basePri & 0xFFU);
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1U);
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0U);
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __memory_changed()
 #endif
-}
 
+/* #########################  Startup and Lowlevel Init  ######################## */
 
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#else
-  (void)fpscr;
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
 #endif
-}
-
-#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
 
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
 
-/*@} end of CMSIS_Core_RegAccFunctions */
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
 
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
+#endif
 
 /* ##########################  Core Instruction Access  ######################### */
 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
@@ -420,35 +172,23 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
            so that all instructions following the ISB are fetched from cache or memory,
            after the instruction has been completed.
  */
-#define __ISB() do {\
-                   __schedule_barrier();\
-                   __isb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
+#define __ISB()                           __isb(0xF)
 
 /**
   \brief   Data Synchronization Barrier
   \details Acts as a special kind of Data Memory Barrier.
            It completes when all explicit memory accesses before this instruction complete.
  */
-#define __DSB() do {\
-                   __schedule_barrier();\
-                   __dsb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
+#define __DSB()                           __dsb(0xF)
 
 /**
   \brief   Data Memory Barrier
   \details Ensures the apparent order of the explicit memory operations before
            and after the instruction, without ensuring their completion.
  */
-#define __DMB() do {\
-                   __schedule_barrier();\
-                   __dmb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
+#define __DMB()                           __dmb(0xF)
+
 
-                  
 /**
   \brief   Reverse byte order (32 bit)
   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
@@ -603,187 +343,461 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 
 
 /**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+  __ISB();
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
  */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
-#else
-  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
 
 
 /**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
-#else
-  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
 
 
 /**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
  */
-#define __CLREX                           __clrex
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
 
 
 /**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
-#define __SSAT                            __ssat
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
 
 
 /**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
  */
-#define __USAT                            __usat
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
 
 
 /**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
  */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
 {
-  rrx r0, r0
-  bx lr
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
 }
-#endif
 
 
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
 /**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
  */
-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+#define __enable_fault_irq                __enable_fiq
 
 
 /**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
  */
-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+#define __disable_fault_irq               __disable_fiq
 
 
 /**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
  */
-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
 
 
 /**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
  */
-#define __STRBT(value, ptr)               __strt(value, ptr)
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
 
 
 /**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
  */
-#define __STRHT(value, ptr)               __strt(value, ptr)
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
 
 
 /**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
  */
-#define __STRT(value, ptr)                __strt(value, ptr)
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
 
-#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
            (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 
+
 /**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
  */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+__STATIC_INLINE uint32_t __get_FPSCR(void)
 {
-  if ((sat >= 1U) && (sat <= 32U))
-  {
-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
-    const int32_t min = -1 - max ;
-    if (val > max)
-    {
-      return max;
-    }
-    else if (val < min)
-    {
-      return min;
-    }
-  }
-  return val;
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
 }
 
+
 /**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 {
-  if (sat <= 31U)
-  {
-    const uint32_t max = ((1U << sat) - 1U);
-    if (val > (int32_t)max)
-    {
-      return max;
-    }
-    else if (val < 0)
-    {
-      return 0U;
-    }
-  }
-  return (uint32_t)val;
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
 }
 
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+/*@} end of CMSIS_Core_RegAccFunctions */
 
 
 /* ###################  Compiler specific Intrinsics  ########################### */
@@ -863,6 +877,10 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint
 #define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
                                                       ((int64_t)(ARG3) << 32U)     ) >> 32U))
 
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 /*@} end of group CMSIS_SIMD_intrinsics */
 

bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armclang.h

@@ -0,0 +1,1503 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.4.3
+ * @date     27. May 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL              Image$$STACKSEAL$$ZI$$Base
+#endif
+
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE      8U
+#endif
+
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
+#endif
+
+
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+  *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
+}
+#endif
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF)
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF)
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.
+     This guarantees ARM-compatible results if happening to compile on a non-ARM
+     target, and ensures the compiler doesn't decide to activate any
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+  {
+    return 32U;
+  }
+  return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+          (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+          (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+          (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+#ifndef __ARM_COMPAT_H
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+#endif
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+           Can only be executed in Privileged modes.
+ */
+#ifndef __ARM_COMPAT_H
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+  __ISB();
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+  __ISB();
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define     __SADD8                 __builtin_arm_sadd8
+#define     __QADD8                 __builtin_arm_qadd8
+#define     __SHADD8                __builtin_arm_shadd8
+#define     __UADD8                 __builtin_arm_uadd8
+#define     __UQADD8                __builtin_arm_uqadd8
+#define     __UHADD8                __builtin_arm_uhadd8
+#define     __SSUB8                 __builtin_arm_ssub8
+#define     __QSUB8                 __builtin_arm_qsub8
+#define     __SHSUB8                __builtin_arm_shsub8
+#define     __USUB8                 __builtin_arm_usub8
+#define     __UQSUB8                __builtin_arm_uqsub8
+#define     __UHSUB8                __builtin_arm_uhsub8
+#define     __SADD16                __builtin_arm_sadd16
+#define     __QADD16                __builtin_arm_qadd16
+#define     __SHADD16               __builtin_arm_shadd16
+#define     __UADD16                __builtin_arm_uadd16
+#define     __UQADD16               __builtin_arm_uqadd16
+#define     __UHADD16               __builtin_arm_uhadd16
+#define     __SSUB16                __builtin_arm_ssub16
+#define     __QSUB16                __builtin_arm_qsub16
+#define     __SHSUB16               __builtin_arm_shsub16
+#define     __USUB16                __builtin_arm_usub16
+#define     __UQSUB16               __builtin_arm_uqsub16
+#define     __UHSUB16               __builtin_arm_uhsub16
+#define     __SASX                  __builtin_arm_sasx
+#define     __QASX                  __builtin_arm_qasx
+#define     __SHASX                 __builtin_arm_shasx
+#define     __UASX                  __builtin_arm_uasx
+#define     __UQASX                 __builtin_arm_uqasx
+#define     __UHASX                 __builtin_arm_uhasx
+#define     __SSAX                  __builtin_arm_ssax
+#define     __QSAX                  __builtin_arm_qsax
+#define     __SHSAX                 __builtin_arm_shsax
+#define     __USAX                  __builtin_arm_usax
+#define     __UQSAX                 __builtin_arm_uqsax
+#define     __UHSAX                 __builtin_arm_uhsax
+#define     __USAD8                 __builtin_arm_usad8
+#define     __USADA8                __builtin_arm_usada8
+#define     __SSAT16                __builtin_arm_ssat16
+#define     __USAT16                __builtin_arm_usat16
+#define     __UXTB16                __builtin_arm_uxtb16
+#define     __UXTAB16               __builtin_arm_uxtab16
+#define     __SXTB16                __builtin_arm_sxtb16
+#define     __SXTAB16               __builtin_arm_sxtab16
+#define     __SMUAD                 __builtin_arm_smuad
+#define     __SMUADX                __builtin_arm_smuadx
+#define     __SMLAD                 __builtin_arm_smlad
+#define     __SMLADX                __builtin_arm_smladx
+#define     __SMLALD                __builtin_arm_smlald
+#define     __SMLALDX               __builtin_arm_smlaldx
+#define     __SMUSD                 __builtin_arm_smusd
+#define     __SMUSDX                __builtin_arm_smusdx
+#define     __SMLSD                 __builtin_arm_smlsd
+#define     __SMLSDX                __builtin_arm_smlsdx
+#define     __SMLSLD                __builtin_arm_smlsld
+#define     __SMLSLDX               __builtin_arm_smlsldx
+#define     __SEL                   __builtin_arm_sel
+#define     __QADD                  __builtin_arm_qadd
+#define     __QSUB                  __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */

bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_compiler.h → bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_compiler.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     cmsis_compiler.h
  * @brief    CMSIS compiler generic header file
- * @version  V5.0.4
- * @date     10. January 2018
+ * @version  V5.1.0
+ * @date     09. October 2018
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,9 +35,15 @@
 
 
 /*
- * Arm Compiler 6 (armclang)
+ * Arm Compiler 6.6 LTM (armclang)
  */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
   #include "cmsis_armclang.h"
 
 
@@ -115,8 +121,11 @@
     #define __ALIGNED(x)                           __attribute__((aligned(x)))
   #endif
   #ifndef   __RESTRICT
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
-    #define __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
   #endif
 
 
@@ -187,6 +196,10 @@
     #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
     #define __RESTRICT
   #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
 
 
 /*
@@ -255,6 +268,10 @@
     #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
     #define __RESTRICT
   #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
 
 
 #else

bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_iccarm.h → bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_iccarm.h

@@ -1,13 +1,16 @@
 /**************************************************************************//**
  * @file     cmsis_iccarm.h
  * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
- * @version  V5.0.5
- * @date     10. January 2018
+ * @version  V5.3.0
+ * @date     14. April 2021
  ******************************************************************************/
 
 //------------------------------------------------------------------------------
 //
-// Copyright (c) 2017-2018 IAR Systems
+// Copyright (c) 2017-2021 IAR Systems
+// Copyright (c) 2017-2021 Arm Limited. All rights reserved.
+//
+// SPDX-License-Identifier: Apache-2.0
 //
 // Licensed under the Apache License, Version 2.0 (the "License")
 // you may not use this file except in compliance with the License.
@@ -110,6 +113,10 @@
   #define __ASM __asm
 #endif
 
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
 #ifndef __INLINE
   #define __INLINE inline
 #endif
@@ -150,7 +157,12 @@
 #endif
 
 #ifndef   __RESTRICT
-  #define __RESTRICT            restrict
+  #if __ICCARM_V8
+    #define __RESTRICT            __restrict
+  #else
+    /* Needs IAR language extensions */
+    #define __RESTRICT            restrict
+  #endif
 #endif
 
 #ifndef   __STATIC_INLINE
@@ -226,6 +238,7 @@ __packed struct  __iar_u32 { uint32_t v; };
   #endif
 #endif
 
+#undef __WEAK                           /* undo the definition from DLib_Defaults.h */
 #ifndef   __WEAK
   #if __ICCARM_V8
     #define __WEAK __attribute__((weak))
@@ -234,6 +247,43 @@ __packed struct  __iar_u32 { uint32_t v; };
   #endif
 #endif
 
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  @".intvec"
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL              STACKSEAL$$Base
+#endif
+
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE      8U
+#endif
+
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
+#endif
+
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+  *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
+}
+#endif
 
 #ifndef __ICCARM_INTRINSICS_VERSION__
   #define __ICCARM_INTRINSICS_VERSION__  0
@@ -305,7 +355,13 @@ __packed struct  __iar_u32 { uint32_t v; };
 
   #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
   #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
-  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __arm_wsr("CONTROL", control);
+  __iar_builtin_ISB();
+}
+
   #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
   #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
 
@@ -327,7 +383,13 @@ __packed struct  __iar_u32 { uint32_t v; };
   #endif
 
   #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
-  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __arm_wsr("CONTROL_NS", control);
+  __iar_builtin_ISB();
+}
+
   #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
   #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
   #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
@@ -340,8 +402,17 @@ __packed struct  __iar_u32 { uint32_t v; };
   #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
   #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
   #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
-  #define __TZ_get_PSPLIM_NS()        (__arm_rsr("PSPLIM_NS"))
-  #define __TZ_set_PSPLIM_NS(VALUE)   (__arm_wsr("PSPLIM_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
   #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
   #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
 
@@ -558,7 +629,7 @@ __packed struct  __iar_u32 { uint32_t v; };
     __IAR_FT uint32_t __RRX(uint32_t value)
     {
       uint32_t result;
-      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      __ASM volatile("RRX      %0, %1" : "=r"(result) : "r" (value));
       return(result);
     }
 
@@ -640,6 +711,7 @@ __packed struct  __iar_u32 { uint32_t v; };
     __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
     {
       __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+      __iar_builtin_ISB();
     }
 
     __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
@@ -716,12 +788,25 @@ __packed struct  __iar_u32 { uint32_t v; };
     __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
     {
       uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
       __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
       return res;
     }
+
     __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
     {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
       __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
     }
 
     __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
@@ -784,37 +869,37 @@ __packed struct  __iar_u32 { uint32_t v; };
   __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
   {
     uint32_t res;
-    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
     return ((uint8_t)res);
   }
 
   __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
   {
     uint32_t res;
-    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
     return ((uint16_t)res);
   }
 
   __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
   {
     uint32_t res;
-    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
     return res;
   }
 
   __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
   {
-    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+    __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
   }
 
   __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
   {
-    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+    __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
   }
 
   __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
   {
-    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+    __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
   }
 
 #endif /* (__CORTEX_M >= 0x03) */
@@ -826,78 +911,78 @@ __packed struct  __iar_u32 { uint32_t v; };
   __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint8_t)res);
   }
 
   __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint16_t)res);
   }
 
   __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return res;
   }
 
   __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
   {
-    __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
   }
 
   __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
   {
-    __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
   }
 
   __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
   {
-    __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
   }
 
   __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint8_t)res);
   }
 
   __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint16_t)res);
   }
 
   __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return res;
   }
 
   __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
     return res;
   }
 
   __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
     return res;
   }
 
   __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
     return res;
   }
 
@@ -910,4 +995,8 @@ __packed struct  __iar_u32 { uint32_t v; };
 #pragma diag_default=Pe940
 #pragma diag_default=Pe177
 
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
 #endif /* __CMSIS_ICCARM_H__ */

bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_version.h → bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_version.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_version.h
  * @brief    CMSIS Core(M) Version definitions
- * @version  V5.0.2
- * @date     19. April 2017
+ * @version  V5.0.4
+ * @date     23. July 2019
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -33,7 +33,7 @@
 
 /*  CMSIS Version definitions */
 #define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
-#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION_SUB   ( 4U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
 #define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
                                    __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
 #endif

bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/mpu_armv8.h → bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/mpu_armv8.h

@@ -1,11 +1,11 @@
 /******************************************************************************
  * @file     mpu_armv8.h
- * @brief    CMSIS MPU API for Armv8-M MPU
- * @version  V5.0.4
- * @date     10. January 2018
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version  V5.1.3
+ * @date     03. February 2021
  ******************************************************************************/
 /*
- * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2017-2021 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -44,7 +44,7 @@
 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
 */
 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
-  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+  ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
 
 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
@@ -62,7 +62,7 @@
 * \param O Outer memory attributes
 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
 */
-#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
 
 /** \brief Normal memory non-shareable  */
 #define ARM_MPU_SH_NON   (0U)
@@ -77,7 +77,7 @@
 * \param RO Read-Only: Set to 1 for read-only memory.
 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
 */
-#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
 
 /** \brief Region Base Address Register value
 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
@@ -87,20 +87,35 @@
 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
 */
 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
-  ((BASE & MPU_RBAR_BASE_Pos) | \
-  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  (((BASE) & MPU_RBAR_BASE_Msk) | \
+  (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
   ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
-  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+  (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
 
 /** \brief Region Limit Address Register value
 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
 * \param IDX The attribute index to be associated with this memory region.
 */
 #define ARM_MPU_RLAR(LIMIT, IDX) \
-  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
-  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
   (MPU_RLAR_EN_Msk))
 
+#if defined(MPU_RLAR_PXN_Pos)
+  
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+  
+#endif
+
 /**
 * Struct for a single MPU Region
 */
@@ -114,24 +129,26 @@ typedef struct {
 */
 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
 {
-  __DSB();
-  __ISB();
+  __DMB();
   MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
+  __DSB();
+  __ISB();
 }
 
 /** Disable the MPU.
 */
 __STATIC_INLINE void ARM_MPU_Disable(void)
 {
-  __DSB();
-  __ISB();
+  __DMB();
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
   MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
 }
 
 #ifdef MPU_NS
@@ -140,24 +157,26 @@ __STATIC_INLINE void ARM_MPU_Disable(void)
 */
 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
 {
-  __DSB();
-  __ISB();
+  __DMB();
   MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
   SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
+  __DSB();
+  __ISB();
 }
 
 /** Disable the Non-secure MPU.
 */
 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
 {
-  __DSB();
-  __ISB();
+  __DMB();
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
   SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
   MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
 }
 #endif
 
@@ -262,12 +281,12 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t
 }
 #endif
 
-/** Memcopy with strictly ordered memory access, e.g. for register targets.
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
 * \param dst Destination data is copied to.
 * \param src Source data is copied from.
 * \param len Amount of data words to be copied.
 */
-__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
 {
   uint32_t i;
   for (i = 0U; i < len; ++i) 
@@ -287,7 +306,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
   const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
   if (cnt == 1U) {
     mpu->RNR = rnr;
-    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
   } else {
     uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
     uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
@@ -295,7 +314,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
     mpu->RNR = rnrBase;
     while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
       uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
-      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
       table += c;
       cnt -= c;
       rnrOffset = 0U;
@@ -303,7 +322,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
       mpu->RNR = rnrBase;
     }
     
-    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
   }
 }
 

bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_common_tables.h

@@ -1,121 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_common_tables.h
- * Description:  Extern declaration for common tables
- *
- * $Date:        27. January 2017
- * $Revision:    V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-extern const uint16_t armBitRevTable[1024];
-extern const q15_t armRecipTableQ15[64];
-extern const q31_t armRecipTableQ31[64];
-extern const float32_t twiddleCoef_16[32];
-extern const float32_t twiddleCoef_32[64];
-extern const float32_t twiddleCoef_64[128];
-extern const float32_t twiddleCoef_128[256];
-extern const float32_t twiddleCoef_256[512];
-extern const float32_t twiddleCoef_512[1024];
-extern const float32_t twiddleCoef_1024[2048];
-extern const float32_t twiddleCoef_2048[4096];
-extern const float32_t twiddleCoef_4096[8192];
-#define twiddleCoef twiddleCoef_4096
-extern const q31_t twiddleCoef_16_q31[24];
-extern const q31_t twiddleCoef_32_q31[48];
-extern const q31_t twiddleCoef_64_q31[96];
-extern const q31_t twiddleCoef_128_q31[192];
-extern const q31_t twiddleCoef_256_q31[384];
-extern const q31_t twiddleCoef_512_q31[768];
-extern const q31_t twiddleCoef_1024_q31[1536];
-extern const q31_t twiddleCoef_2048_q31[3072];
-extern const q31_t twiddleCoef_4096_q31[6144];
-extern const q15_t twiddleCoef_16_q15[24];
-extern const q15_t twiddleCoef_32_q15[48];
-extern const q15_t twiddleCoef_64_q15[96];
-extern const q15_t twiddleCoef_128_q15[192];
-extern const q15_t twiddleCoef_256_q15[384];
-extern const q15_t twiddleCoef_512_q15[768];
-extern const q15_t twiddleCoef_1024_q15[1536];
-extern const q15_t twiddleCoef_2048_q15[3072];
-extern const q15_t twiddleCoef_4096_q15[6144];
-extern const float32_t twiddleCoef_rfft_32[32];
-extern const float32_t twiddleCoef_rfft_64[64];
-extern const float32_t twiddleCoef_rfft_128[128];
-extern const float32_t twiddleCoef_rfft_256[256];
-extern const float32_t twiddleCoef_rfft_512[512];
-extern const float32_t twiddleCoef_rfft_1024[1024];
-extern const float32_t twiddleCoef_rfft_2048[2048];
-extern const float32_t twiddleCoef_rfft_4096[4096];
-
-/* floating-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
-#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
-#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
-#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
-#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
-#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
-
-/* fixed-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
-#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
-#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
-#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
-#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
-#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
-#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
-#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
-
-/* Tables for Fast Math Sine and Cosine */
-extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
-extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
-extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
-
-#endif /*  ARM_COMMON_TABLES_H */

bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_const_structs.h

@@ -1,66 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_const_structs.h
- * Description:  Constant structs that are initialized for user convenience.
- *               For example, some can be given as arguments to the arm_cfft_f32() function.
- *
- * $Date:        27. January 2017
- * $Revision:    V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_CONST_STRUCTS_H
-#define _ARM_CONST_STRUCTS_H
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
-
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
-
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
-
-#endif

bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_math.h

@@ -1,7160 +0,0 @@
-/******************************************************************************
- * @file     arm_math.h
- * @brief    Public header file for CMSIS DSP LibraryU
- * @version  V1.5.3
- * @date     10. January 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
-   \mainpage CMSIS DSP Software Library
-   *
-   * Introduction
-   * ------------
-   *
-   * This user manual describes the CMSIS DSP software library,
-   * a suite of common signal processing functions for use on Cortex-M processor based devices.
-   *
-   * The library is divided into a number of functions each covering a specific category:
-   * - Basic math functions
-   * - Fast math functions
-   * - Complex math functions
-   * - Filters
-   * - Matrix functions
-   * - Transforms
-   * - Motor control functions
-   * - Statistical functions
-   * - Support functions
-   * - Interpolation functions
-   *
-   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
-   * 32-bit integer and 32-bit floating-point values.
-   *
-   * Using the Library
-   * ------------
-   *
-   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
-   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
-   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
-   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
-   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
-   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
-   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
-   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
-   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
-   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
-   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
-   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
-   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
-   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
-   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
-   * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
-   * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
-   * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)
-   * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
-   * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
-   *
-   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
-   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
-   * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
-   * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
-   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
-   * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
-   * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
-   * 
-   *
-   * Examples
-   * --------
-   *
-   * The library ships with a number of examples which demonstrate how to use the library functions.
-   *
-   * Toolchain Support
-   * ------------
-   *
-   * The library has been developed and tested with MDK version 5.14.0.0
-   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
-   *
-   * Building the Library
-   * ------------
-   *
-   * The library installer contains a project file to rebuild libraries on MDK toolchain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
-   * - arm_cortexM_math.uvprojx
-   *
-   *
-   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.
-   *
-   * Preprocessor Macros
-   * ------------
-   *
-   * Each library project have different preprocessor macros.
-   *
-   * - UNALIGNED_SUPPORT_DISABLE:
-   *
-   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
-   *
-   * - ARM_MATH_BIG_ENDIAN:
-   *
-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
-   *
-   * - ARM_MATH_MATRIX_CHECK:
-   *
-   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
-   *
-   * - ARM_MATH_ROUNDING:
-   *
-   * Define macro ARM_MATH_ROUNDING for rounding on support functions
-   *
-   * - ARM_MATH_CMx:
-   *
-   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
-   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
-   * ARM_MATH_CM7 for building the library on cortex-M7.
-   *
-   * - ARM_MATH_ARMV8MxL:
-   *
-   * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library
-   * on Armv8-M Mainline target.
-   *
-   * - __FPU_PRESENT:
-   *
-   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
-   *
-   * - __DSP_PRESENT:
-   *
-   * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions.
-   *
-   * <hr>
-   * CMSIS-DSP in ARM::CMSIS Pack
-   * -----------------------------
-   *
-   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
-   * |File/Folder                   |Content                                                                 |
-   * |------------------------------|------------------------------------------------------------------------|
-   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
-   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
-   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
-   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
-   *
-   * <hr>
-   * Revision History of CMSIS-DSP
-   * ------------
-   * Please refer to \ref ChangeLog_pg.
-   *
-   * Copyright Notice
-   * ------------
-   *
-   * Copyright (C) 2010-2015 Arm Limited. All rights reserved.
-   */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures.  For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data.  The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order.  That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- *     pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure.  For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices. For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns. If the size check fails the functions return:
- * <pre>
- *     ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- *     ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- * <pre>
- *     ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings.  By default this macro is defined
- * and size checking is enabled. By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster. With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-/* Compiler specific diagnostic adjustment */
-#if   defined ( __CC_ARM )
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-
-#elif defined ( __GNUC__ )
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-
-#elif defined ( __ICCARM__ )
-
-#elif defined ( __TI_ARM__ )
-
-#elif defined ( __CSMC__ )
-
-#elif defined ( __TASKING__ )
-
-#else
-  #error Unknown compiler
-#endif
-
-
-#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
-
-#if defined(ARM_MATH_CM7)
-  #include "core_cm7.h"
-  #define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM4)
-  #include "core_cm4.h"
-  #define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM33)
-  #include "core_cm33.h"
-  #define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM3)
-  #include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
-  #include "core_cm0.h"
-  #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_CM0PLUS)
-  #include "core_cm0plus.h"
-  #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_ARMV8MBL)
-  #include "core_armv8mbl.h"
-  #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_ARMV8MML)
-  #include "core_armv8mml.h"
-  #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
-    #define ARM_MATH_DSP
-  #endif
-#else
-  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
-#endif
-
-#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
-#include "string.h"
-#include "math.h"
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-
-  /**
-   * @brief Macros required for reciprocal calculation in Normalized LMS
-   */
-
-#define DELTA_Q31          (0x100)
-#define DELTA_Q15          0x5
-#define INDEX_MASK         0x0000003F
-#ifndef PI
-  #define PI               3.14159265358979f
-#endif
-
-  /**
-   * @brief Macros required for SINE and COSINE Fast math approximations
-   */
-
-#define FAST_MATH_TABLE_SIZE  512
-#define FAST_MATH_Q31_SHIFT   (32 - 10)
-#define FAST_MATH_Q15_SHIFT   (16 - 10)
-#define CONTROLLER_Q31_SHIFT  (32 - 9)
-#define TABLE_SPACING_Q31     0x400000
-#define TABLE_SPACING_Q15     0x80
-
-  /**
-   * @brief Macros required for SINE and COSINE Controller functions
-   */
-  /* 1.31(q31) Fixed value of 2/360 */
-  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING         0xB60B61
-
-  /**
-   * @brief Macro for Unaligned Support
-   */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-    #define ALIGN4
-#else
-  #if defined  (__GNUC__)
-    #define ALIGN4 __attribute__((aligned(4)))
-  #else
-    #define ALIGN4 __align(4)
-  #endif
-#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-  /**
-   * @brief Error status returned by some functions in the library.
-   */
-
-  typedef enum
-  {
-    ARM_MATH_SUCCESS = 0,                /**< No error */
-    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
-    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
-    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
-    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
-    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
-    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
-  } arm_status;
-
-  /**
-   * @brief 8-bit fractional data type in 1.7 format.
-   */
-  typedef int8_t q7_t;
-
-  /**
-   * @brief 16-bit fractional data type in 1.15 format.
-   */
-  typedef int16_t q15_t;
-
-  /**
-   * @brief 32-bit fractional data type in 1.31 format.
-   */
-  typedef int32_t q31_t;
-
-  /**
-   * @brief 64-bit fractional data type in 1.63 format.
-   */
-  typedef int64_t q63_t;
-
-  /**
-   * @brief 32-bit floating-point type definition.
-   */
-  typedef float float32_t;
-
-  /**
-   * @brief 64-bit floating-point type definition.
-   */
-  typedef double float64_t;
-
-  /**
-   * @brief definition to read/write two 16 bit values.
-   */
-#if   defined ( __CC_ARM )
-  #define __SIMD32_TYPE int32_t __packed
-  #define CMSIS_UNUSED __attribute__((unused))
-  #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED __attribute__((unused))
-  #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __GNUC__ )
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED __attribute__((unused))
-  #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __ICCARM__ )
-  #define __SIMD32_TYPE int32_t __packed
-  #define CMSIS_UNUSED
-  #define CMSIS_INLINE
-
-#elif defined ( __TI_ARM__ )
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED __attribute__((unused))
-  #define CMSIS_INLINE
-
-#elif defined ( __CSMC__ )
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED
-  #define CMSIS_INLINE
-
-#elif defined ( __TASKING__ )
-  #define __SIMD32_TYPE __unaligned int32_t
-  #define CMSIS_UNUSED
-  #define CMSIS_INLINE
-
-#else
-  #error Unknown compiler
-#endif
-
-#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
-#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
-#define __SIMD64(addr)        (*(int64_t **) & (addr))
-
-#if !defined (ARM_MATH_DSP)
-  /**
-   * @brief definition to pack two 16 bit values.
-   */
-#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \
-                                    (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
-#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \
-                                    (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
-
-#endif /* !defined (ARM_MATH_DSP) */
-
-   /**
-   * @brief definition to pack four 8 bit values.
-   */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
-                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
-                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
-                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
-#else
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
-                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
-                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
-                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
-
-#endif
-
-
-  /**
-   * @brief Clips Q63 to Q31 values.
-   */
-  CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
-  }
-
-  /**
-   * @brief Clips Q63 to Q15 values.
-   */
-  CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
-  }
-
-  /**
-   * @brief Clips Q31 to Q7 values.
-   */
-  CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
-      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
-  }
-
-  /**
-   * @brief Clips Q31 to Q15 values.
-   */
-  CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
-  }
-
-  /**
-   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
-   */
-
-  CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
-  q63_t x,
-  q31_t y)
-  {
-    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
-            (((q63_t) (x >> 32) * y)));
-  }
-
-  /**
-   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
-   */
-
-  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
-  q31_t in,
-  q31_t * dst,
-  q31_t * pRecipTable)
-  {
-    q31_t out;
-    uint32_t tempVal;
-    uint32_t index, i;
-    uint32_t signBits;
-
-    if (in > 0)
-    {
-      signBits = ((uint32_t) (__CLZ( in) - 1));
-    }
-    else
-    {
-      signBits = ((uint32_t) (__CLZ(-in) - 1));
-    }
-
-    /* Convert input sample to 1.31 format */
-    in = (in << signBits);
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t)(in >> 24);
-    index = (index & INDEX_MASK);
-
-    /* 1.31 with exp 1 */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0U; i < 2U; i++)
-    {
-      tempVal = (uint32_t) (((q63_t) in * out) >> 31);
-      tempVal = 0x7FFFFFFFu - tempVal;
-      /*      1.31 with exp 1 */
-      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
-      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1U);
-  }
-
-
-  /**
-   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
-  q15_t in,
-  q15_t * dst,
-  q15_t * pRecipTable)
-  {
-    q15_t out = 0;
-    uint32_t tempVal = 0;
-    uint32_t index = 0, i = 0;
-    uint32_t signBits = 0;
-
-    if (in > 0)
-    {
-      signBits = ((uint32_t)(__CLZ( in) - 17));
-    }
-    else
-    {
-      signBits = ((uint32_t)(__CLZ(-in) - 17));
-    }
-
-    /* Convert input sample to 1.15 format */
-    in = (in << signBits);
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t)(in >>  8);
-    index = (index & INDEX_MASK);
-
-    /*      1.15 with exp 1  */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0U; i < 2U; i++)
-    {
-      tempVal = (uint32_t) (((q31_t) in * out) >> 15);
-      tempVal = 0x7FFFu - tempVal;
-      /*      1.15 with exp 1 */
-      out = (q15_t) (((q31_t) out * tempVal) >> 14);
-      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1);
-  }
-
-
-/*
- * @brief C custom defined intrinsic function for M3 and M0 processors
- */
-#if !defined (ARM_MATH_DSP)
-
-  /*
-   * @brief C custom defined QADD8 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s, t, u;
-
-    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
-    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
-    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
-    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
-
-    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QSUB8 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s, t, u;
-
-    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
-    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
-    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
-    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
-
-    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QADD16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
-  uint32_t x,
-  uint32_t y)
-  {
-/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
-    q31_t r = 0, s = 0;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHADD16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QSUB16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHSUB16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QASX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHASX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QSAX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHSAX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SMUSDX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
-  }
-
-  /*
-   * @brief C custom defined SMUADX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
-  }
-
-
-  /*
-   * @brief C custom defined QADD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
-  int32_t x,
-  int32_t y)
-  {
-    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
-  }
-
-
-  /*
-   * @brief C custom defined QSUB for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
-  int32_t x,
-  int32_t y)
-  {
-    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
-  }
-
-
-  /*
-   * @brief C custom defined SMLAD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
-  uint32_t x,
-  uint32_t y,
-  uint32_t sum)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLADX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
-  uint32_t x,
-  uint32_t y,
-  uint32_t sum)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLSDX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
-  uint32_t x,
-  uint32_t y,
-  uint32_t sum)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLALD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
-  uint32_t x,
-  uint32_t y,
-  uint64_t sum)
-  {
-/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
-    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ( ((q63_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLALDX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
-  uint32_t x,
-  uint32_t y,
-  uint64_t sum)
-  {
-/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
-    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q63_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMUAD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMUSD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
-  }
-
-
-  /*
-   * @brief C custom defined SXTB16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
-  uint32_t x)
-  {
-    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
-                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
-  }
-
-  /*
-   * @brief C custom defined SMMLA for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
-  int32_t x,
-  int32_t y,
-  int32_t sum)
-  {
-    return (sum + (int32_t) (((int64_t) x * y) >> 32));
-  }
-
-#endif /* !defined (ARM_MATH_DSP) */
-
-
-  /**
-   * @brief Instance structure for the Q7 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
-    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q7;
-
-  /**
-   * @brief Instance structure for the Q15 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q7 FIR filter.
-   * @param[in]  S          points to an instance of the Q7 FIR filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_q7(
-  const arm_fir_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q7 FIR filter.
-   * @param[in,out] S          points to an instance of the Q7 FIR structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed.
-   */
-  void arm_fir_init_q7(
-  arm_fir_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR filter.
-   * @param[in]  S          points to an instance of the Q15 FIR structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q15 FIR filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_fast_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR filter.
-   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed at a time.
-   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
-   * <code>numTaps</code> is not a supported value.
-   */
-  arm_status arm_fir_init_q15(
-  arm_fir_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR filter.
-   * @param[in]  S          points to an instance of the Q31 FIR filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q31 FIR structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_fast_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR filter.
-   * @param[in,out] S          points to an instance of the Q31 FIR structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed at a time.
-   */
-  void arm_fir_init_q31(
-  arm_fir_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR filter.
-   * @param[in]  S          points to an instance of the floating-point FIR structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_f32(
-  const arm_fir_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR filter.
-   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed at a time.
-   */
-  void arm_fir_init_f32(
-  arm_fir_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
-  } arm_biquad_casd_df1_inst_q15;
-
-  /**
-   * @brief Instance structure for the Q31 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
-  } arm_biquad_casd_df1_inst_q31;
-
-  /**
-   * @brief Instance structure for the floating-point Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_casd_df1_inst_f32;
-
-
-  /**
-   * @brief Processing function for the Q15 Biquad cascade filter.
-   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
-   */
-  void arm_biquad_cascade_df1_init_q15(
-  arm_biquad_casd_df1_inst_q15 * S,
-  uint8_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int8_t postShift);
-
-
-  /**
-   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_fast_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 Biquad cascade filter
-   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_fast_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
-   */
-  void arm_biquad_cascade_df1_init_q31(
-  arm_biquad_casd_df1_inst_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int8_t postShift);
-
-
-  /**
-   * @brief Processing function for the floating-point Biquad cascade filter.
-   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_f32(
-  const arm_biquad_casd_df1_inst_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_df1_init_f32(
-  arm_biquad_casd_df1_inst_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float32_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f32;
-
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float64_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f64;
-
-  /**
-   * @brief Instance structure for the Q15 matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q15_t *pData;         /**< points to the data of the matrix. */
-  } arm_matrix_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q31_t *pData;         /**< points to the data of the matrix. */
-  } arm_matrix_instance_q31;
-
-
-  /**
-   * @brief Floating-point matrix addition.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_add_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix addition.
-   * @param[in]   pSrcA  points to the first input matrix structure
-   * @param[in]   pSrcB  points to the second input matrix structure
-   * @param[out]  pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_add_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst);
-
-
-  /**
-   * @brief Q31 matrix addition.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_add_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point, complex, matrix multiplication.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_cmplx_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15, complex,  matrix multiplication.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_cmplx_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pScratch);
-
-
-  /**
-   * @brief Q31, complex, matrix multiplication.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_cmplx_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix transpose.
-   * @param[in]  pSrc  points to the input matrix
-   * @param[out] pDst  points to the output matrix
-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_trans_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix transpose.
-   * @param[in]  pSrc  points to the input matrix
-   * @param[out] pDst  points to the output matrix
-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_trans_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  arm_matrix_instance_q15 * pDst);
-
-
-  /**
-   * @brief Q31 matrix transpose.
-   * @param[in]  pSrc  points to the input matrix
-   * @param[out] pDst  points to the output matrix
-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_trans_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix multiplication
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix multiplication
-   * @param[in]  pSrcA   points to the first input matrix structure
-   * @param[in]  pSrcB   points to the second input matrix structure
-   * @param[out] pDst    points to output matrix structure
-   * @param[in]  pState  points to the array for storing intermediate results
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState);
-
-
-  /**
-   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA   points to the first input matrix structure
-   * @param[in]  pSrcB   points to the second input matrix structure
-   * @param[out] pDst    points to output matrix structure
-   * @param[in]  pState  points to the array for storing intermediate results
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_fast_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState);
-
-
-  /**
-   * @brief Q31 matrix multiplication
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_fast_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix subtraction
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_sub_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix subtraction
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_sub_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst);
-
-
-  /**
-   * @brief Q31 matrix subtraction
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_sub_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix scaling.
-   * @param[in]  pSrc   points to the input matrix
-   * @param[in]  scale  scale factor
-   * @param[out] pDst   points to the output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_scale_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  float32_t scale,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix scaling.
-   * @param[in]  pSrc        points to input matrix
-   * @param[in]  scaleFract  fractional portion of the scale factor
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_scale_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  q15_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q15 * pDst);
-
-
-  /**
-   * @brief Q31 matrix scaling.
-   * @param[in]  pSrc        points to input matrix
-   * @param[in]  scaleFract  fractional portion of the scale factor
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_scale_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  q31_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief  Q31 matrix initialization.
-   * @param[in,out] S         points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows     number of rows in the matrix.
-   * @param[in]     nColumns  number of columns in the matrix.
-   * @param[in]     pData     points to the matrix data array.
-   */
-  void arm_mat_init_q31(
-  arm_matrix_instance_q31 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q31_t * pData);
-
-
-  /**
-   * @brief  Q15 matrix initialization.
-   * @param[in,out] S         points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows     number of rows in the matrix.
-   * @param[in]     nColumns  number of columns in the matrix.
-   * @param[in]     pData     points to the matrix data array.
-   */
-  void arm_mat_init_q15(
-  arm_matrix_instance_q15 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q15_t * pData);
-
-
-  /**
-   * @brief  Floating-point matrix initialization.
-   * @param[in,out] S         points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows     number of rows in the matrix.
-   * @param[in]     nColumns  number of columns in the matrix.
-   * @param[in]     pData     points to the matrix data array.
-   */
-  void arm_mat_init_f32(
-  arm_matrix_instance_f32 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  float32_t * pData);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 PID Control.
-   */
-  typedef struct
-  {
-    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
-#if !defined (ARM_MATH_DSP)
-    q15_t A1;
-    q15_t A2;
-#else
-    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
-    q15_t state[3];     /**< The state array of length 3. */
-    q15_t Kp;           /**< The proportional gain. */
-    q15_t Ki;           /**< The integral gain. */
-    q15_t Kd;           /**< The derivative gain. */
-  } arm_pid_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 PID Control.
-   */
-  typedef struct
-  {
-    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
-    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
-    q31_t A2;            /**< The derived gain, A2 = Kd . */
-    q31_t state[3];      /**< The state array of length 3. */
-    q31_t Kp;            /**< The proportional gain. */
-    q31_t Ki;            /**< The integral gain. */
-    q31_t Kd;            /**< The derivative gain. */
-  } arm_pid_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point PID Control.
-   */
-  typedef struct
-  {
-    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
-    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
-    float32_t A2;          /**< The derived gain, A2 = Kd . */
-    float32_t state[3];    /**< The state array of length 3. */
-    float32_t Kp;          /**< The proportional gain. */
-    float32_t Ki;          /**< The integral gain. */
-    float32_t Kd;          /**< The derivative gain. */
-  } arm_pid_instance_f32;
-
-
-
-  /**
-   * @brief  Initialization function for the floating-point PID Control.
-   * @param[in,out] S               points to an instance of the PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   */
-  void arm_pid_init_f32(
-  arm_pid_instance_f32 * S,
-  int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the floating-point PID Control.
-   * @param[in,out] S  is an instance of the floating-point PID Control structure
-   */
-  void arm_pid_reset_f32(
-  arm_pid_instance_f32 * S);
-
-
-  /**
-   * @brief  Initialization function for the Q31 PID Control.
-   * @param[in,out] S               points to an instance of the Q15 PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   */
-  void arm_pid_init_q31(
-  arm_pid_instance_q31 * S,
-  int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the Q31 PID Control.
-   * @param[in,out] S   points to an instance of the Q31 PID Control structure
-   */
-
-  void arm_pid_reset_q31(
-  arm_pid_instance_q31 * S);
-
-
-  /**
-   * @brief  Initialization function for the Q15 PID Control.
-   * @param[in,out] S               points to an instance of the Q15 PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   */
-  void arm_pid_init_q15(
-  arm_pid_instance_q15 * S,
-  int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the Q15 PID Control.
-   * @param[in,out] S  points to an instance of the q15 PID Control structure
-   */
-  void arm_pid_reset_q15(
-  arm_pid_instance_q15 * S);
-
-
-  /**
-   * @brief Instance structure for the floating-point Linear Interpolate function.
-   */
-  typedef struct
-  {
-    uint32_t nValues;           /**< nValues */
-    float32_t x1;               /**< x1 */
-    float32_t xSpacing;         /**< xSpacing */
-    float32_t *pYData;          /**< pointer to the table of Y values */
-  } arm_linear_interp_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point bilinear interpolation function.
-   */
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    float32_t *pData;   /**< points to the data table. */
-  } arm_bilinear_interp_instance_f32;
-
-   /**
-   * @brief Instance structure for the Q31 bilinear interpolation function.
-   */
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q31_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q31;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q15_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q15;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q7_t *pData;        /**< points to the data table. */
-  } arm_bilinear_interp_instance_q7;
-
-
-  /**
-   * @brief Q7 vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Floating-point vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q15;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_q15(
-  arm_cfft_radix2_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_q15(
-  const arm_cfft_radix2_instance_q15 * S,
-  q15_t * pSrc);
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q15;
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_q15(
-  arm_cfft_radix4_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix4_q15(
-  const arm_cfft_radix4_instance_q15 * S,
-  q15_t * pSrc);
-
-  /**
-   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q31;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_q31(
-  arm_cfft_radix2_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_q31(
-  const arm_cfft_radix2_instance_q31 * S,
-  q31_t * pSrc);
-
-  /**
-   * @brief Instance structure for the Q31 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q31;
-
-/* Deprecated */
-  void arm_cfft_radix4_q31(
-  const arm_cfft_radix4_instance_q31 * S,
-  q31_t * pSrc);
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_q31(
-  arm_cfft_radix4_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;             /**< value of 1/fftLen. */
-  } arm_cfft_radix2_instance_f32;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_f32(
-  arm_cfft_radix2_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_f32(
-  const arm_cfft_radix2_instance_f32 * S,
-  float32_t * pSrc);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;             /**< value of 1/fftLen. */
-  } arm_cfft_radix4_instance_f32;
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_f32(
-  arm_cfft_radix4_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix4_f32(
-  const arm_cfft_radix4_instance_f32 * S,
-  float32_t * pSrc);
-
-  /**
-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_q15;
-
-void arm_cfft_q15(
-    const arm_cfft_instance_q15 * S,
-    q15_t * p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_q31;
-
-void arm_cfft_q31(
-    const arm_cfft_instance_q31 * S,
-    q31_t * p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_f32;
-
-  void arm_cfft_f32(
-  const arm_cfft_instance_f32 * S,
-  float32_t * p1,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the Q15 RFFT/RIFFT function.
-   */
-  typedef struct
-  {
-    uint32_t fftLenReal;                      /**< length of the real FFT. */
-    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
-    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
-    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q15;
-
-  arm_status arm_rfft_init_q15(
-  arm_rfft_instance_q15 * S,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_q15(
-  const arm_rfft_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst);
-
-  /**
-   * @brief Instance structure for the Q31 RFFT/RIFFT function.
-   */
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
-    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
-    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q31;
-
-  arm_status arm_rfft_init_q31(
-  arm_rfft_instance_q31 * S,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_q31(
-  const arm_rfft_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
-    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
-  } arm_rfft_instance_f32;
-
-  arm_status arm_rfft_init_f32(
-  arm_rfft_instance_f32 * S,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_f32(
-  const arm_rfft_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-typedef struct
-  {
-    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
-    uint16_t fftLenRFFT;             /**< length of the real sequence */
-    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */
-  } arm_rfft_fast_instance_f32 ;
-
-arm_status arm_rfft_fast_init_f32 (
-   arm_rfft_fast_instance_f32 * S,
-   uint16_t fftLen);
-
-void arm_rfft_fast_f32(
-  arm_rfft_fast_instance_f32 * S,
-  float32_t * p, float32_t * pOut,
-  uint8_t ifftFlag);
-
-  /**
-   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
-   */
-  typedef struct
-  {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    float32_t normalize;                 /**< normalizing factor. */
-    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    float32_t *pCosFactor;               /**< points to the cosFactor table. */
-    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_f32;
-
-
-  /**
-   * @brief  Initialization function for the floating-point DCT4/IDCT4.
-   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
-   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
-   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
-   */
-  arm_status arm_dct4_init_f32(
-  arm_dct4_instance_f32 * S,
-  arm_rfft_instance_f32 * S_RFFT,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  float32_t normalize);
-
-
-  /**
-   * @brief Processing function for the floating-point DCT4/IDCT4.
-   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
-   * @param[in]     pState         points to state buffer.
-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
-   */
-  void arm_dct4_f32(
-  const arm_dct4_instance_f32 * S,
-  float32_t * pState,
-  float32_t * pInlineBuffer);
-
-
-  /**
-   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
-   */
-  typedef struct
-  {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    q31_t normalize;                     /**< normalizing factor. */
-    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */
-    q31_t *pCosFactor;                   /**< points to the cosFactor table. */
-    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q31;
-
-
-  /**
-   * @brief  Initialization function for the Q31 DCT4/IDCT4.
-   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
-   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
-   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-  arm_status arm_dct4_init_q31(
-  arm_dct4_instance_q31 * S,
-  arm_rfft_instance_q31 * S_RFFT,
-  arm_cfft_radix4_instance_q31 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q31_t normalize);
-
-
-  /**
-   * @brief Processing function for the Q31 DCT4/IDCT4.
-   * @param[in]     S              points to an instance of the Q31 DCT4 structure.
-   * @param[in]     pState         points to state buffer.
-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
-   */
-  void arm_dct4_q31(
-  const arm_dct4_instance_q31 * S,
-  q31_t * pState,
-  q31_t * pInlineBuffer);
-
-
-  /**
-   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
-   */
-  typedef struct
-  {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    q15_t normalize;                     /**< normalizing factor. */
-    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */
-    q15_t *pCosFactor;                   /**< points to the cosFactor table. */
-    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q15;
-
-
-  /**
-   * @brief  Initialization function for the Q15 DCT4/IDCT4.
-   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
-   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
-   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-  arm_status arm_dct4_init_q15(
-  arm_dct4_instance_q15 * S,
-  arm_rfft_instance_q15 * S_RFFT,
-  arm_cfft_radix4_instance_q15 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q15_t normalize);
-
-
-  /**
-   * @brief Processing function for the Q15 DCT4/IDCT4.
-   * @param[in]     S              points to an instance of the Q15 DCT4 structure.
-   * @param[in]     pState         points to state buffer.
-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
-   */
-  void arm_dct4_q15(
-  const arm_dct4_instance_q15 * S,
-  q15_t * pState,
-  q15_t * pInlineBuffer);
-
-
-  /**
-   * @brief Floating-point vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q7 vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Floating-point vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q7 vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a floating-point vector by a scalar.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  scale      scale factor to be applied
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_scale_f32(
-  float32_t * pSrc,
-  float32_t scale,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a Q7 vector by a scalar.
-   * @param[in]  pSrc        points to the input vector
-   * @param[in]  scaleFract  fractional portion of the scale value
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to the output vector
-   * @param[in]  blockSize   number of samples in the vector
-   */
-  void arm_scale_q7(
-  q7_t * pSrc,
-  q7_t scaleFract,
-  int8_t shift,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a Q15 vector by a scalar.
-   * @param[in]  pSrc        points to the input vector
-   * @param[in]  scaleFract  fractional portion of the scale value
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to the output vector
-   * @param[in]  blockSize   number of samples in the vector
-   */
-  void arm_scale_q15(
-  q15_t * pSrc,
-  q15_t scaleFract,
-  int8_t shift,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a Q31 vector by a scalar.
-   * @param[in]  pSrc        points to the input vector
-   * @param[in]  scaleFract  fractional portion of the scale value
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to the output vector
-   * @param[in]  blockSize   number of samples in the vector
-   */
-  void arm_scale_q31(
-  q31_t * pSrc,
-  q31_t scaleFract,
-  int8_t shift,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q7 vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Floating-point vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Dot product of floating-point vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t blockSize,
-  float32_t * result);
-
-
-  /**
-   * @brief Dot product of Q7 vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  uint32_t blockSize,
-  q31_t * result);
-
-
-  /**
-   * @brief Dot product of Q15 vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t blockSize,
-  q63_t * result);
-
-
-  /**
-   * @brief Dot product of Q31 vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t blockSize,
-  q63_t * result);
-
-
-  /**
-   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_shift_q7(
-  q7_t * pSrc,
-  int8_t shiftBits,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_shift_q15(
-  q15_t * pSrc,
-  int8_t shiftBits,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_shift_q31(
-  q31_t * pSrc,
-  int8_t shiftBits,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a floating-point vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_f32(
-  float32_t * pSrc,
-  float32_t offset,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a Q7 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_q7(
-  q7_t * pSrc,
-  q7_t offset,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a Q15 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_q15(
-  q15_t * pSrc,
-  q15_t offset,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a Q31 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_q31(
-  q31_t * pSrc,
-  q31_t offset,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a floating-point vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a Q7 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a Q15 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a Q31 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a floating-point vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a Q7 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a Q15 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a Q31 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a floating-point vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_f32(
-  float32_t value,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a Q7 vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_q7(
-  q7_t value,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a Q15 vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_q15(
-  q15_t value,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a Q31 vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_q31(
-  q31_t value,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
- */
-  void arm_conv_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences.
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
-   */
-  void arm_conv_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
- */
-  void arm_conv_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_fast_q15(
-          q15_t * pSrcA,
-          uint32_t srcALen,
-          q15_t * pSrcB,
-          uint32_t srcBLen,
-          q15_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
-   */
-  void arm_conv_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Convolution of Q31 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-    /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   */
-  void arm_conv_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst);
-
-
-  /**
-   * @brief Partial convolution of floating-point sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_fast_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q7 sequences
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
-   * @brief Partial convolution of Q7 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR decimator.
-   */
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
-    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR decimator.
-   */
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
-    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR decimator.
-   */
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
-    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_f32;
-
-
-  /**
-   * @brief Processing function for the floating-point FIR decimator.
-   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_f32(
-  const arm_fir_decimate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR decimator.
-   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
-   * @param[in]     numTaps    number of coefficients in the filter.
-   * @param[in]     M          decimation factor.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-  arm_status arm_fir_decimate_init_f32(
-  arm_fir_decimate_instance_f32 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator.
-   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_fast_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR decimator.
-   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
-   * @param[in]     numTaps    number of coefficients in the filter.
-   * @param[in]     M          decimation factor.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-  arm_status arm_fir_decimate_init_q15(
-  arm_fir_decimate_instance_q15 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator.
-   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
-   * @param[in]  pSrc  points to the block of input data.
-   * @param[out] pDst  points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   */
-  void arm_fir_decimate_q31(
-  const arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_fast_q31(
-  arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR decimator.
-   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
-   * @param[in]     numTaps    number of coefficients in the filter.
-   * @param[in]     M          decimation factor.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-  arm_status arm_fir_decimate_init_q31(
-  arm_fir_decimate_instance_q31 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR interpolator.
-   */
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR interpolator.
-   */
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR interpolator.
-   */
-  typedef struct
-  {
-    uint8_t L;                     /**< upsample factor. */
-    uint16_t phaseLength;          /**< length of each polyphase filter component. */
-    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
-    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
-  } arm_fir_interpolate_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q15 FIR interpolator.
-   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_interpolate_q15(
-  const arm_fir_interpolate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR interpolator.
-   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]     L          upsample factor.
-   * @param[in]     numTaps    number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficient buffer.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-  arm_status arm_fir_interpolate_init_q15(
-  arm_fir_interpolate_instance_q15 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR interpolator.
-   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_interpolate_q31(
-  const arm_fir_interpolate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR interpolator.
-   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
-   * @param[in]     L          upsample factor.
-   * @param[in]     numTaps    number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficient buffer.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-  arm_status arm_fir_interpolate_init_q31(
-  arm_fir_interpolate_instance_q31 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR interpolator.
-   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_interpolate_f32(
-  const arm_fir_interpolate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR interpolator.
-   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
-   * @param[in]     L          upsample factor.
-   * @param[in]     numTaps    number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficient buffer.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-  arm_status arm_fir_interpolate_init_f32(
-  arm_fir_interpolate_instance_f32 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
-  } arm_biquad_cas_df1_32x64_ins_q31;
-
-
-  /**
-   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cas_df1_32x64_q31(
-  const arm_biquad_cas_df1_32x64_ins_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
-   */
-  void arm_biquad_cas_df1_32x64_init_q31(
-  arm_biquad_cas_df1_32x64_ins_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q63_t * pState,
-  uint8_t postShift);
-
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_stereo_df2T_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f64;
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  S          points to an instance of the filter data structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df2T_f32(
-  const arm_biquad_cascade_df2T_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
-   * @param[in]  S          points to an instance of the filter data structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_stereo_df2T_f32(
-  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  S          points to an instance of the filter data structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df2T_f64(
-  const arm_biquad_cascade_df2T_instance_f64 * S,
-  float64_t * pSrc,
-  float64_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the filter data structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_df2T_init_f32(
-  arm_biquad_cascade_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the filter data structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_stereo_df2T_init_f32(
-  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the filter data structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_df2T_init_f64(
-  arm_biquad_cascade_df2T_instance_f64 * S,
-  uint8_t numStages,
-  float64_t * pCoeffs,
-  float64_t * pState);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
-    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
-    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_f32;
-
-
-  /**
-   * @brief Initialization function for the Q15 FIR lattice filter.
-   * @param[in] S          points to an instance of the Q15 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] pState     points to the state buffer.  The array is of length numStages.
-   */
-  void arm_fir_lattice_init_q15(
-  arm_fir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR lattice filter.
-   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_lattice_q15(
-  const arm_fir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the Q31 FIR lattice filter.
-   * @param[in] S          points to an instance of the Q31 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] pState     points to the state buffer.   The array is of length numStages.
-   */
-  void arm_fir_lattice_init_q31(
-  arm_fir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR lattice filter.
-   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_lattice_q31(
-  const arm_fir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] S          points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
- * @param[in] pState     points to the state buffer.  The array is of length numStages.
- */
-  void arm_fir_lattice_init_f32(
-  arm_fir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR lattice filter.
-   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_lattice_f32(
-  const arm_fir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
-    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
-    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
-    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
-    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_f32;
-
-
-  /**
-   * @brief Processing function for the floating-point IIR lattice filter.
-   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_f32(
-  const arm_iir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the floating-point IIR lattice filter.
-   * @param[in] S          points to an instance of the floating-point IIR lattice structure.
-   * @param[in] numStages  number of stages in the filter.
-   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_init_f32(
-  arm_iir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pkCoeffs,
-  float32_t * pvCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 IIR lattice filter.
-   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_q31(
-  const arm_iir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the Q31 IIR lattice filter.
-   * @param[in] S          points to an instance of the Q31 IIR lattice structure.
-   * @param[in] numStages  number of stages in the filter.
-   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_init_q31(
-  arm_iir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pkCoeffs,
-  q31_t * pvCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 IIR lattice filter.
-   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_q15(
-  const arm_iir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
- * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
- * @param[in] blockSize  number of samples to process per call.
- */
-  void arm_iir_lattice_init_q15(
-  arm_iir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pkCoeffs,
-  q15_t * pvCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the floating-point LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that controls filter coefficient updates. */
-  } arm_lms_instance_f32;
-
-
-  /**
-   * @brief Processing function for floating-point LMS filter.
-   * @param[in]  S          points to an instance of the floating-point LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_f32(
-  const arm_lms_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for floating-point LMS filter.
-   * @param[in] S          points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to the coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_lms_init_f32(
-  arm_lms_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-  } arm_lms_instance_q15;
-
-
-  /**
-   * @brief Initialization function for the Q15 LMS filter.
-   * @param[in] S          points to an instance of the Q15 LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to the coefficient buffer.
-   * @param[in] pState     points to the state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_init_q15(
-  arm_lms_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint32_t postShift);
-
-
-  /**
-   * @brief Processing function for Q15 LMS filter.
-   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_q15(
-  const arm_lms_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-  } arm_lms_instance_q31;
-
-
-  /**
-   * @brief Processing function for Q31 LMS filter.
-   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_q31(
-  const arm_lms_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q31 LMS filter.
-   * @param[in] S          points to an instance of the Q31 LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_init_q31(
-  arm_lms_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint32_t postShift);
-
-
-  /**
-   * @brief Instance structure for the floating-point normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;         /**< step size that control filter coefficient updates. */
-    float32_t energy;     /**< saves previous frame energy. */
-    float32_t x0;         /**< saves previous input sample. */
-  } arm_lms_norm_instance_f32;
-
-
-  /**
-   * @brief Processing function for floating-point normalized LMS filter.
-   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_norm_f32(
-  arm_lms_norm_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for floating-point normalized LMS filter.
-   * @param[in] S          points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_lms_norm_init_f32(
-  arm_lms_norm_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
-    q31_t energy;         /**< saves previous frame energy. */
-    q31_t x0;             /**< saves previous input sample. */
-  } arm_lms_norm_instance_q31;
-
-
-  /**
-   * @brief Processing function for Q31 normalized LMS filter.
-   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_norm_q31(
-  arm_lms_norm_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q31 normalized LMS filter.
-   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_norm_init_q31(
-  arm_lms_norm_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint8_t postShift);
-
-
-  /**
-   * @brief Instance structure for the Q15 normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< Number of coefficients in the filter. */
-    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */
-    q15_t energy;         /**< saves previous frame energy. */
-    q15_t x0;             /**< saves previous input sample. */
-  } arm_lms_norm_instance_q15;
-
-
-  /**
-   * @brief Processing function for Q15 normalized LMS filter.
-   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_norm_q15(
-  arm_lms_norm_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q15 normalized LMS filter.
-   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_norm_init_q15(
-  arm_lms_norm_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint8_t postShift);
-
-
-  /**
-   * @brief Correlation of floating-point sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst);
-
-
-   /**
-   * @brief Correlation of Q15 sequences
-   * @param[in]  pSrcA     points to the first input sequence.
-   * @param[in]  srcALen   length of the first input sequence.
-   * @param[in]  pSrcB     points to the second input sequence.
-   * @param[in]  srcBLen   length of the second input sequence.
-   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   */
-  void arm_correlate_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch);
-
-
-  /**
-   * @brief Correlation of Q15 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-
-  void arm_correlate_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-
-  void arm_correlate_fast_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in]  pSrcA     points to the first input sequence.
-   * @param[in]  srcALen   length of the first input sequence.
-   * @param[in]  pSrcB     points to the second input sequence.
-   * @param[in]  srcBLen   length of the second input sequence.
-   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   */
-  void arm_correlate_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch);
-
-
-  /**
-   * @brief Correlation of Q31 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-  /**
-   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
- /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   */
-  void arm_correlate_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst);
-
-
-  /**
-   * @brief Instance structure for the floating-point sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_f32;
-
-  /**
-   * @brief Instance structure for the Q31 sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q31;
-
-  /**
-   * @brief Instance structure for the Q15 sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q7 sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q7;
-
-
-  /**
-   * @brief Processing function for the floating-point sparse FIR filter.
-   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
-   * @param[in]  pSrc        points to the block of input data.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   */
-  void arm_fir_sparse_f32(
-  arm_fir_sparse_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  float32_t * pScratchIn,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point sparse FIR filter.
-   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_f32(
-  arm_fir_sparse_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 sparse FIR filter.
-   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
-   * @param[in]  pSrc        points to the block of input data.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   */
-  void arm_fir_sparse_q31(
-  arm_fir_sparse_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  q31_t * pScratchIn,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 sparse FIR filter.
-   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_q31(
-  arm_fir_sparse_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 sparse FIR filter.
-   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
-   * @param[in]  pSrc         points to the block of input data.
-   * @param[out] pDst         points to the block of output data
-   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
-   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   */
-  void arm_fir_sparse_q15(
-  arm_fir_sparse_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  q15_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 sparse FIR filter.
-   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_q15(
-  arm_fir_sparse_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q7 sparse FIR filter.
-   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
-   * @param[in]  pSrc         points to the block of input data.
-   * @param[out] pDst         points to the block of output data
-   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
-   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   */
-  void arm_fir_sparse_q7(
-  arm_fir_sparse_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  q7_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q7 sparse FIR filter.
-   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_q7(
-  arm_fir_sparse_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Floating-point sin_cos function.
-   * @param[in]  theta   input value in degrees
-   * @param[out] pSinVal  points to the processed sine output.
-   * @param[out] pCosVal  points to the processed cos output.
-   */
-  void arm_sin_cos_f32(
-  float32_t theta,
-  float32_t * pSinVal,
-  float32_t * pCosVal);
-
-
-  /**
-   * @brief  Q31 sin_cos function.
-   * @param[in]  theta    scaled input value in degrees
-   * @param[out] pSinVal  points to the processed sine output.
-   * @param[out] pCosVal  points to the processed cosine output.
-   */
-  void arm_sin_cos_q31(
-  q31_t theta,
-  q31_t * pSinVal,
-  q31_t * pCosVal);
-
-
-  /**
-   * @brief  Floating-point complex conjugate.
-   * @param[in]  pSrc        points to the input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_conj_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex conjugate.
-   * @param[in]  pSrc        points to the input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_conj_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex conjugate.
-   * @param[in]  pSrc        points to the input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_conj_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Floating-point complex magnitude squared
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_squared_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex magnitude squared
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_squared_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex magnitude squared
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_squared_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
- /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup PID PID Motor Control
-   *
-   * A Proportional Integral Derivative (PID) controller is a generic feedback control
-   * loop mechanism widely used in industrial control systems.
-   * A PID controller is the most commonly used type of feedback controller.
-   *
-   * This set of functions implements (PID) controllers
-   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
-   * of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
-   * is the input sample value. The functions return the output value.
-   *
-   * \par Algorithm:
-   * <pre>
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd  </pre>
-   *
-   * \par
-   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
-   *
-   * \par
-   * \image html PID.gif "Proportional Integral Derivative Controller"
-   *
-   * \par
-   * The PID controller calculates an "error" value as the difference between
-   * the measured output and the reference input.
-   * The controller attempts to minimize the error by adjusting the process control inputs.
-   * The proportional value determines the reaction to the current error,
-   * the integral value determines the reaction based on the sum of recent errors,
-   * and the derivative value determines the reaction based on the rate at which the error has been changing.
-   *
-   * \par Instance Structure
-   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
-   * A separate instance structure must be defined for each PID Controller.
-   * There are separate instance structure declarations for each of the 3 supported data types.
-   *
-   * \par Reset Functions
-   * There is also an associated reset function for each data type which clears the state array.
-   *
-   * \par Initialization Functions
-   * There is also an associated initialization function for each data type.
-   * The initialization function performs the following operations:
-   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
-   * - Zeros out the values in the state buffer.
-   *
-   * \par
-   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
-   *
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the fixed-point versions of the PID Controller functions.
-   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup PID
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point PID Control.
-   * @param[in,out] S   is an instance of the floating-point PID Control structure
-   * @param[in]     in  input sample to process
-   * @return out processed output sample.
-   */
-  CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
-  arm_pid_instance_f32 * S,
-  float32_t in)
-  {
-    float32_t out;
-
-    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
-    out = (S->A0 * in) +
-      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @brief  Process function for the Q31 PID Control.
-   * @param[in,out] S  points to an instance of the Q31 PID Control structure
-   * @param[in]     in  input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 64-bit accumulator.
-   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
-   * Thus, if the accumulator result overflows it wraps around rather than clip.
-   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
-   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
-   */
-  CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
-  arm_pid_instance_q31 * S,
-  q31_t in)
-  {
-    q63_t acc;
-    q31_t out;
-
-    /* acc = A0 * x[n]  */
-    acc = (q63_t) S->A0 * in;
-
-    /* acc += A1 * x[n-1] */
-    acc += (q63_t) S->A1 * S->state[0];
-
-    /* acc += A2 * x[n-2]  */
-    acc += (q63_t) S->A2 * S->state[1];
-
-    /* convert output to 1.31 format to add y[n-1] */
-    out = (q31_t) (acc >> 31U);
-
-    /* out += y[n-1] */
-    out += S->state[2];
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-  }
-
-
-  /**
-   * @brief  Process function for the Q15 PID Control.
-   * @param[in,out] S   points to an instance of the Q15 PID Control structure
-   * @param[in]     in  input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using a 64-bit internal accumulator.
-   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
-   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
-   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
-   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
-   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
-   */
-  CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
-  arm_pid_instance_q15 * S,
-  q15_t in)
-  {
-    q63_t acc;
-    q15_t out;
-
-#if defined (ARM_MATH_DSP)
-    __SIMD32_TYPE *vstate;
-
-    /* Implementation of PID controller */
-
-    /* acc = A0 * x[n]  */
-    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    vstate = __SIMD32_CONST(S->state);
-    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
-#else
-    /* acc = A0 * x[n]  */
-    acc = ((q31_t) S->A0) * in;
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    acc += (q31_t) S->A1 * S->state[0];
-    acc += (q31_t) S->A2 * S->state[1];
-#endif
-
-    /* acc += y[n-1] */
-    acc += (q31_t) S->state[2] << 15;
-
-    /* saturate the output */
-    out = (q15_t) (__SSAT((acc >> 15), 16));
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-  }
-
-  /**
-   * @} end of PID group
-   */
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  src   points to the instance of the input floating-point matrix structure.
-   * @param[out] dst   points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-  arm_status arm_mat_inverse_f32(
-  const arm_matrix_instance_f32 * src,
-  arm_matrix_instance_f32 * dst);
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  src   points to the instance of the input floating-point matrix structure.
-   * @param[out] dst   points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-  arm_status arm_mat_inverse_f64(
-  const arm_matrix_instance_f64 * src,
-  arm_matrix_instance_f64 * dst);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup clarke Vector Clarke Transform
-   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
-   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
-   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
-   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
-   * \image html clarke.gif Stator current space vector and its components in (a,b).
-   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
-   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeFormula.gif
-   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
-   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup clarke
-   * @{
-   */
-
-  /**
-   *
-   * @brief  Floating-point Clarke transform
-   * @param[in]  Ia       input three-phase coordinate <code>a</code>
-   * @param[in]  Ib       input three-phase coordinate <code>b</code>
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
-  float32_t Ia,
-  float32_t Ib,
-  float32_t * pIalpha,
-  float32_t * pIbeta)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
-    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
-  }
-
-
-  /**
-   * @brief  Clarke transform for Q31 version
-   * @param[in]  Ia       input three-phase coordinate <code>a</code>
-   * @param[in]  Ib       input three-phase coordinate <code>b</code>
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
-  q31_t Ia,
-  q31_t Ib,
-  q31_t * pIalpha,
-  q31_t * pIbeta)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
-    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
-    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
-    /* pIbeta is calculated by adding the intermediate products */
-    *pIbeta = __QADD(product1, product2);
-  }
-
-  /**
-   * @} end of clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q31 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_q7_to_q31(
-  q7_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_clarke Vector Inverse Clarke Transform
-   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeInvFormula.gif
-   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
-   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_clarke
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Clarke transform
-   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
-   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pIa,
-  float32_t * pIb)
-  {
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
-    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
-  }
-
-
-  /**
-   * @brief  Inverse Clarke transform for Q31 version
-   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
-   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the subtraction, hence there is no risk of overflow.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pIa,
-  q31_t * pIb)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
-    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
-    /* pIb is calculated by subtracting the products */
-    *pIb = __QSUB(product2, product1);
-  }
-
-  /**
-   * @} end of inv_clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q15 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_q7_to_q15(
-  q7_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup park Vector Park Transform
-   *
-   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
-   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
-   * from the stationary to the moving reference frame and control the spatial relationship between
-   * the stator vector current and rotor flux vector.
-   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
-   * current vector and the relationship from the two reference frames:
-   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkFormula.gif
-   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
-   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup park
-   * @{
-   */
-
-  /**
-   * @brief Floating-point Park transform
-   * @param[in]  Ialpha  input two-phase vector coordinate alpha
-   * @param[in]  Ibeta   input two-phase vector coordinate beta
-   * @param[out] pId     points to output   rotor reference frame d
-   * @param[out] pIq     points to output   rotor reference frame q
-   * @param[in]  sinVal  sine value of rotation angle theta
-   * @param[in]  cosVal  cosine value of rotation angle theta
-   *
-   * The function implements the forward Park transform.
-   *
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pId,
-  float32_t * pIq,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
-    *pId = Ialpha * cosVal + Ibeta * sinVal;
-
-    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
-    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
-  }
-
-
-  /**
-   * @brief  Park transform for Q31 version
-   * @param[in]  Ialpha  input two-phase vector coordinate alpha
-   * @param[in]  Ibeta   input two-phase vector coordinate beta
-   * @param[out] pId     points to output rotor reference frame d
-   * @param[out] pIq     points to output rotor reference frame q
-   * @param[in]  sinVal  sine value of rotation angle theta
-   * @param[in]  cosVal  cosine value of rotation angle theta
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pId,
-  q31_t * pIq,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Ialpha * cosVal) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * sinVal) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Ialpha * sinVal) */
-    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * cosVal) */
-    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
-    /* Calculate pId by adding the two intermediate products 1 and 2 */
-    *pId = __QADD(product1, product2);
-
-    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
-    *pIq = __QSUB(product4, product3);
-  }
-
-  /**
-   * @} end of park group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q7_to_float(
-  q7_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_park Vector Inverse Park transform
-   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkInvFormula.gif
-   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
-   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_park
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Park transform
-   * @param[in]  Id       input coordinate of rotor reference frame d
-   * @param[in]  Iq       input coordinate of rotor reference frame q
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]  sinVal   sine value of rotation angle theta
-   * @param[in]  cosVal   cosine value of rotation angle theta
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
-  float32_t Id,
-  float32_t Iq,
-  float32_t * pIalpha,
-  float32_t * pIbeta,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
-    *pIalpha = Id * cosVal - Iq * sinVal;
-
-    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
-    *pIbeta = Id * sinVal + Iq * cosVal;
-  }
-
-
-  /**
-   * @brief  Inverse Park transform for   Q31 version
-   * @param[in]  Id       input coordinate of rotor reference frame d
-   * @param[in]  Iq       input coordinate of rotor reference frame q
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]  sinVal   sine value of rotation angle theta
-   * @param[in]  cosVal   cosine value of rotation angle theta
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
-  q31_t Id,
-  q31_t Iq,
-  q31_t * pIalpha,
-  q31_t * pIbeta,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Id * cosVal) */
-    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * sinVal) */
-    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Id * sinVal) */
-    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * cosVal) */
-    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
-    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
-    *pIalpha = __QSUB(product1, product2);
-
-    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
-    *pIbeta = __QADD(product4, product3);
-  }
-
-  /**
-   * @} end of Inverse park group
-   */
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q31_to_float(
-  q31_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup LinearInterpolate Linear Interpolation
-   *
-   * Linear interpolation is a method of curve fitting using linear polynomials.
-   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
-   *
-   * \par
-   * \image html LinearInterp.gif "Linear interpolation"
-   *
-   * \par
-   * A  Linear Interpolate function calculates an output value(y), for the input(x)
-   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
-   *
-   * \par Algorithm:
-   * <pre>
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   * </pre>
-   *
-   * \par
-   * This set of functions implements Linear interpolation process
-   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
-   * sample of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
-   * <code>x</code> is the input sample value. The functions returns the output value.
-   *
-   * \par
-   * if x is outside of the table boundary, Linear interpolation returns first value of the table
-   * if x is below input range and returns last value of table if x is above range.
-   */
-
-  /**
-   * @addtogroup LinearInterpolate
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point Linear Interpolation Function.
-   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
-   * @param[in]     x  input sample to process
-   * @return y processed output sample.
-   *
-   */
-  CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
-  arm_linear_interp_instance_f32 * S,
-  float32_t x)
-  {
-    float32_t y;
-    float32_t x0, x1;                            /* Nearest input values */
-    float32_t y0, y1;                            /* Nearest output values */
-    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
-    int32_t i;                                   /* Index variable */
-    float32_t *pYData = S->pYData;               /* pointer to output table */
-
-    /* Calculation of index */
-    i = (int32_t) ((x - S->x1) / xSpacing);
-
-    if (i < 0)
-    {
-      /* Iniatilize output for below specified range as least output value of table */
-      y = pYData[0];
-    }
-    else if ((uint32_t)i >= S->nValues)
-    {
-      /* Iniatilize output for above specified range as last output value of table */
-      y = pYData[S->nValues - 1];
-    }
-    else
-    {
-      /* Calculation of nearest input values */
-      x0 = S->x1 +  i      * xSpacing;
-      x1 = S->x1 + (i + 1) * xSpacing;
-
-      /* Read of nearest output values */
-      y0 = pYData[i];
-      y1 = pYData[i + 1];
-
-      /* Calculation of output */
-      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
-    }
-
-    /* returns output value */
-    return (y);
-  }
-
-
-   /**
-   *
-   * @brief  Process function for the Q31 Linear Interpolation Function.
-   * @param[in] pYData   pointer to Q31 Linear Interpolation table
-   * @param[in] x        input sample to process
-   * @param[in] nValues  number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-  CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
-  q31_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q31_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & (q31_t)0xFFF00000) >> 20);
-
-    if (index >= (int32_t)(nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if (index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* shift left by 11 to keep fract in 1.31 format */
-      fract = (x & 0x000FFFFF) << 11;
-
-      /* Read two nearest output values from the index in 1.31(q31) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1];
-
-      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
-      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
-      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
-      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
-      /* Convert y to 1.31 format */
-      return (y << 1U);
-    }
-  }
-
-
-  /**
-   *
-   * @brief  Process function for the Q15 Linear Interpolation Function.
-   * @param[in] pYData   pointer to Q15 Linear Interpolation table
-   * @param[in] x        input sample to process
-   * @param[in] nValues  number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-  CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
-  q15_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q63_t y;                                     /* output */
-    q15_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & (int32_t)0xFFF00000) >> 20);
-
-    if (index >= (int32_t)(nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if (index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index */
-      y0 = pYData[index];
-      y1 = pYData[index + 1];
-
-      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
-      y = ((q63_t) y0 * (0xFFFFF - fract));
-
-      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
-      y += ((q63_t) y1 * (fract));
-
-      /* convert y to 1.15 format */
-      return (q15_t) (y >> 20);
-    }
-  }
-
-
-  /**
-   *
-   * @brief  Process function for the Q7 Linear Interpolation Function.
-   * @param[in] pYData   pointer to Q7 Linear Interpolation table
-   * @param[in] x        input sample to process
-   * @param[in] nValues  number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   */
-  CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
-  q7_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q7_t y0, y1;                                 /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    uint32_t index;                              /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    if (x < 0)
-    {
-      return (pYData[0]);
-    }
-    index = (x >> 20) & 0xfff;
-
-    if (index >= (nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index and are in 1.7(q7) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1];
-
-      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
-      y = ((y0 * (0xFFFFF - fract)));
-
-      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
-      y += (y1 * fract);
-
-      /* convert y to 1.7(q7) format */
-      return (q7_t) (y >> 20);
-     }
-  }
-
-  /**
-   * @} end of LinearInterpolate group
-   */
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
-   * @param[in] x  input value in radians.
-   * @return  sin(x).
-   */
-  float32_t arm_sin_f32(
-  float32_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  sin(x).
-   */
-  q31_t arm_sin_q31(
-  q31_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  sin(x).
-   */
-  q15_t arm_sin_q15(
-  q15_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
-   * @param[in] x  input value in radians.
-   * @return  cos(x).
-   */
-  float32_t arm_cos_f32(
-  float32_t x);
-
-
-  /**
-   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  cos(x).
-   */
-  q31_t arm_cos_q31(
-  q31_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  cos(x).
-   */
-  q15_t arm_cos_q15(
-  q15_t x);
-
-
-  /**
-   * @ingroup groupFastMath
-   */
-
-
-  /**
-   * @defgroup SQRT Square Root
-   *
-   * Computes the square root of a number.
-   * There are separate functions for Q15, Q31, and floating-point data types.
-   * The square root function is computed using the Newton-Raphson algorithm.
-   * This is an iterative algorithm of the form:
-   * <pre>
-   *      x1 = x0 - f(x0)/f'(x0)
-   * </pre>
-   * where <code>x1</code> is the current estimate,
-   * <code>x0</code> is the previous estimate, and
-   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
-   * For the square root function, the algorithm reduces to:
-   * <pre>
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   * </pre>
-   */
-
-
-  /**
-   * @addtogroup SQRT
-   * @{
-   */
-
-  /**
-   * @brief  Floating-point square root function.
-   * @param[in]  in    input value.
-   * @param[out] pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
-  float32_t in,
-  float32_t * pOut)
-  {
-    if (in >= 0.0f)
-    {
-
-#if   (__FPU_USED == 1) && defined ( __CC_ARM   )
-      *pOut = __sqrtf(in);
-#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
-      *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined(__GNUC__)
-      *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
-      __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
-#else
-      *pOut = sqrtf(in);
-#endif
-
-      return (ARM_MATH_SUCCESS);
-    }
-    else
-    {
-      *pOut = 0.0f;
-      return (ARM_MATH_ARGUMENT_ERROR);
-    }
-  }
-
-
-  /**
-   * @brief Q31 square root function.
-   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
-   * @param[out] pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q31(
-  q31_t in,
-  q31_t * pOut);
-
-
-  /**
-   * @brief  Q15 square root function.
-   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
-   * @param[out] pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q15(
-  q15_t in,
-  q15_t * pOut);
-
-  /**
-   * @} end of SQRT group
-   */
-
-
-  /**
-   * @brief floating-point Circular write function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const int32_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0U;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if (wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-  }
-
-
-
-  /**
-   * @brief floating-point Circular Read function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  int32_t * dst,
-  int32_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0U;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if (dst == (int32_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value  */
-      rOffset += bufferInc;
-
-      if (rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief Q15 Circular write function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q15_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0U;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if (wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-  }
-
-
-  /**
-   * @brief Q15 Circular Read function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q15_t * dst,
-  q15_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if (dst == (q15_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if (rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief Q7 Circular write function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q7_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0U;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if (wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-  }
-
-
-  /**
-   * @brief Q7 Circular Read function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q7_t * dst,
-  q7_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0U)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if (dst == (q7_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if (rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Variance of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_var_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Variance of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_var_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Variance of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_var_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-
-  /**
-   * @brief  Root Mean Square of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_rms_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_rms_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_rms_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-
-  /**
-   * @brief  Standard deviation of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_std_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Standard deviation of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_std_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Standard deviation of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_std_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-
-  /**
-   * @brief  Floating-point complex magnitude
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex magnitude
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex magnitude
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex dot product
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   * @param[out] realResult  real part of the result returned here
-   * @param[out] imagResult  imaginary part of the result returned here
-   */
-  void arm_cmplx_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t numSamples,
-  q31_t * realResult,
-  q31_t * imagResult);
-
-
-  /**
-   * @brief  Q31 complex dot product
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   * @param[out] realResult  real part of the result returned here
-   * @param[out] imagResult  imaginary part of the result returned here
-   */
-  void arm_cmplx_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t numSamples,
-  q63_t * realResult,
-  q63_t * imagResult);
-
-
-  /**
-   * @brief  Floating-point complex dot product
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   * @param[out] realResult  real part of the result returned here
-   * @param[out] imagResult  imaginary part of the result returned here
-   */
-  void arm_cmplx_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t numSamples,
-  float32_t * realResult,
-  float32_t * imagResult);
-
-
-  /**
-   * @brief  Q15 complex-by-real multiplication
-   * @param[in]  pSrcCmplx   points to the complex input vector
-   * @param[in]  pSrcReal    points to the real input vector
-   * @param[out] pCmplxDst   points to the complex output vector
-   * @param[in]  numSamples  number of samples in each vector
-   */
-  void arm_cmplx_mult_real_q15(
-  q15_t * pSrcCmplx,
-  q15_t * pSrcReal,
-  q15_t * pCmplxDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex-by-real multiplication
-   * @param[in]  pSrcCmplx   points to the complex input vector
-   * @param[in]  pSrcReal    points to the real input vector
-   * @param[out] pCmplxDst   points to the complex output vector
-   * @param[in]  numSamples  number of samples in each vector
-   */
-  void arm_cmplx_mult_real_q31(
-  q31_t * pSrcCmplx,
-  q31_t * pSrcReal,
-  q31_t * pCmplxDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Floating-point complex-by-real multiplication
-   * @param[in]  pSrcCmplx   points to the complex input vector
-   * @param[in]  pSrcReal    points to the real input vector
-   * @param[out] pCmplxDst   points to the complex output vector
-   * @param[in]  numSamples  number of samples in each vector
-   */
-  void arm_cmplx_mult_real_f32(
-  float32_t * pSrcCmplx,
-  float32_t * pSrcReal,
-  float32_t * pCmplxDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Minimum value of a Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] result     is output pointer
-   * @param[in]  index      is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * result,
-  uint32_t * index);
-
-
-  /**
-   * @brief  Minimum value of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output pointer
-   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex);
-
-
-  /**
-   * @brief  Minimum value of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output pointer
-   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex);
-
-
-  /**
-   * @brief  Minimum value of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output pointer
-   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult,
-  uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex);
-
-
-  /**
-   * @brief  Q15 complex-by-complex multiplication
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_mult_cmplx_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex-by-complex multiplication
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_mult_cmplx_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Floating-point complex-by-complex multiplication
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_mult_cmplx_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q31 vector.
-   * @param[in]  pSrc       points to the floating-point input vector
-   * @param[out] pDst       points to the Q31 output vector
-   * @param[in]  blockSize  length of the input vector
-   */
-  void arm_float_to_q31(
-  float32_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q15 vector.
-   * @param[in]  pSrc       points to the floating-point input vector
-   * @param[out] pDst       points to the Q15 output vector
-   * @param[in]  blockSize  length of the input vector
-   */
-  void arm_float_to_q15(
-  float32_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q7 vector.
-   * @param[in]  pSrc       points to the floating-point input vector
-   * @param[out] pDst       points to the Q7 output vector
-   * @param[in]  blockSize  length of the input vector
-   */
-  void arm_float_to_q7(
-  float32_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q31_to_q15(
-  q31_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q31_to_q7(
-  q31_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q15_to_float(
-  q15_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q15_to_q31(
-  q15_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q15_to_q7(
-  q15_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup BilinearInterpolate Bilinear Interpolation
-   *
-   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
-   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
-   * determines values between the grid points.
-   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
-   * Bilinear interpolation is often used in image processing to rescale images.
-   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
-   *
-   * <b>Algorithm</b>
-   * \par
-   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
-   * For floating-point, the instance structure is defined as:
-   * <pre>
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   * </pre>
-   *
-   * \par
-   * where <code>numRows</code> specifies the number of rows in the table;
-   * <code>numCols</code> specifies the number of columns in the table;
-   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
-   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
-   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
-   *
-   * \par
-   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
-   * <pre>
-   *     XF = floor(x)
-   *     YF = floor(y)
-   * </pre>
-   * \par
-   * The interpolated output point is computed as:
-   * <pre>
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   * </pre>
-   * Note that the coordinates (x, y) contain integer and fractional components.
-   * The integer components specify which portion of the table to use while the
-   * fractional components control the interpolation processor.
-   *
-   * \par
-   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
-   */
-
-  /**
-   * @addtogroup BilinearInterpolate
-   * @{
-   */
-
-
-  /**
-  *
-  * @brief  Floating-point bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate.
-  * @param[in]     Y  interpolation coordinate.
-  * @return out interpolated value.
-  */
-  CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
-  const arm_bilinear_interp_instance_f32 * S,
-  float32_t X,
-  float32_t Y)
-  {
-    float32_t out;
-    float32_t f00, f01, f10, f11;
-    float32_t *pData = S->pData;
-    int32_t xIndex, yIndex, index;
-    float32_t xdiff, ydiff;
-    float32_t b1, b2, b3, b4;
-
-    xIndex = (int32_t) X;
-    yIndex = (int32_t) Y;
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* Calculation of index for two nearest points in X-direction */
-    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
-
-
-    /* Read two nearest points in X-direction */
-    f00 = pData[index];
-    f01 = pData[index + 1];
-
-    /* Calculation of index for two nearest points in Y-direction */
-    index = (xIndex - 1) + (yIndex) * S->numCols;
-
-
-    /* Read two nearest points in Y-direction */
-    f10 = pData[index];
-    f11 = pData[index + 1];
-
-    /* Calculation of intermediate values */
-    b1 = f00;
-    b2 = f01 - f00;
-    b3 = f10 - f00;
-    b4 = f00 - f01 - f10 + f11;
-
-    /* Calculation of fractional part in X */
-    xdiff = X - xIndex;
-
-    /* Calculation of fractional part in Y */
-    ydiff = Y - yIndex;
-
-    /* Calculation of bi-linear interpolated output */
-    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
-    /* return to application */
-    return (out);
-  }
-
-
-  /**
-  *
-  * @brief  Q31 bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate in 12.20 format.
-  * @param[in]     Y  interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-  CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
-  arm_bilinear_interp_instance_q31 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q31_t out;                                   /* Temporary output */
-    q31_t acc = 0;                               /* output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q31_t x1, x2, y1, y2;                        /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q31_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* shift left xfract by 11 to keep 1.31 format */
-    xfract = (X & 0x000FFFFF) << 11U;
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
-    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* shift left yfract by 11 to keep 1.31 format */
-    yfract = (Y & 0x000FFFFF) << 11U;
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
-    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
-    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
-    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
-    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
-    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* Convert acc to 1.31(q31) format */
-    return ((q31_t)(acc << 2));
-  }
-
-
-  /**
-  * @brief  Q15 bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate in 12.20 format.
-  * @param[in]     Y  interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-  CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
-  arm_bilinear_interp_instance_q15 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q15_t x1, x2, y1, y2;                        /* Nearest output values */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    int32_t rI, cI;                              /* Row and column indices */
-    q15_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
-    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
-    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
-    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
-    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
-    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);
-    acc = ((q63_t) out * (0xFFFFF - yfract));
-
-    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);
-    acc += ((q63_t) out * (xfract));
-
-    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);
-    acc += ((q63_t) out * (yfract));
-
-    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
-    acc += ((q63_t) out * (yfract));
-
-    /* acc is in 13.51 format and down shift acc by 36 times */
-    /* Convert out to 1.15 format */
-    return ((q15_t)(acc >> 36));
-  }
-
-
-  /**
-  * @brief  Q7 bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate in 12.20 format.
-  * @param[in]     Y  interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-  CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
-  arm_bilinear_interp_instance_q7 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q7_t x1, x2, y1, y2;                         /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q7_t *pYData = S->pData;                     /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & (q31_t)0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
-    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & (q31_t)0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
-    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
-    out = ((x1 * (0xFFFFF - xfract)));
-    acc = (((q63_t) out * (0xFFFFF - yfract)));
-
-    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
-    out = ((x2 * (0xFFFFF - yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y1 * (0xFFFFF - xfract)));
-    acc += (((q63_t) out * (yfract)));
-
-    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y2 * (yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
-    return ((q7_t)(acc >> 40));
-  }
-
-  /**
-   * @} end of BilinearInterpolate group
-   */
-
-
-/* SMMLAR */
-#define multAcc_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMLSR */
-#define multSub_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMULR */
-#define mult_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
-
-/* SMMLA */
-#define multAcc_32x32_keep32(a, x, y) \
-    a += (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMLS */
-#define multSub_32x32_keep32(a, x, y) \
-    a -= (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMUL */
-#define mult_32x32_keep32(a, x, y) \
-    a = (q31_t) (((q63_t) x * y ) >> 32)
-
-
-#if   defined ( __CC_ARM )
-  /* Enter low optimization region - place directly above function definition */
-  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
-    #define LOW_OPTIMIZATION_ENTER \
-       _Pragma ("push")         \
-       _Pragma ("O1")
-  #else
-    #define LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-    #define LOW_OPTIMIZATION_EXIT \
-       _Pragma ("pop")
-  #else
-    #define LOW_OPTIMIZATION_EXIT
-  #endif
-
-  /* Enter low optimization region - place directly above function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __GNUC__ )
-  #define LOW_OPTIMIZATION_ENTER \
-       __attribute__(( optimize("-O1") ))
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __ICCARM__ )
-  /* Enter low optimization region - place directly above function definition */
-  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-    #define LOW_OPTIMIZATION_ENTER \
-       _Pragma ("optimize=low")
-  #else
-    #define LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define LOW_OPTIMIZATION_EXIT
-
-  /* Enter low optimization region - place directly above function definition */
-  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
-       _Pragma ("optimize=low")
-  #else
-    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TI_ARM__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __CSMC__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TASKING__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#endif
-
-
-#ifdef   __cplusplus
-}
-#endif
-
-/* Compiler specific diagnostic adjustment */
-#if   defined ( __CC_ARM )
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-
-#elif defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-
-#elif defined ( __ICCARM__ )
-
-#elif defined ( __TI_ARM__ )
-
-#elif defined ( __CSMC__ )
-
-#elif defined ( __TASKING__ )
-
-#else
-  #error Unknown compiler
-#endif
-
-#endif /* _ARM_MATH_H */
-
-/**
- *
- * End of file.
- */

bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mbl.h

@@ -1,1896 +0,0 @@
-/**************************************************************************//**
- * @file     core_armv8mbl.h
- * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
- * @version  V5.0.4
- * @date     10. January 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_ARMV8MBL_H_GENERIC
-#define __CORE_ARMV8MBL_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_ARMv8MBL
-  @{
- */
- 
-#include "cmsis_version.h"
-
-/*  CMSIS definitions */
-#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
-                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MBL_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_ARMV8MBL_H_DEPENDANT
-#define __CORE_ARMV8MBL_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __ARMv8MBL_REV
-    #define __ARMv8MBL_REV               0x0000U
-    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __SAUREGION_PRESENT
-    #define __SAUREGION_PRESENT       0U
-    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0U
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-
-  #ifndef __ETM_PRESENT
-    #define __ETM_PRESENT             0U
-    #warning "__ETM_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MTB_PRESENT
-    #define __MTB_PRESENT             0U
-    #warning "__MTB_PRESENT not defined in device header file; using default!"
-  #endif
-
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv8MBL */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[16U];
-  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[16U];
-  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[16U];
-  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[16U];
-  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[16U];
-  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-        uint32_t RESERVED5[16U];
-  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-#else
-        uint32_t RESERVED0;
-#endif
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-        uint32_t RESERVED0[6U];
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-        uint32_t RESERVED3[1U];
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-        uint32_t RESERVED5[1U];
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED6[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-        uint32_t RESERVED7[1U];
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-        uint32_t RESERVED9[1U];
-  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-        uint32_t RESERVED10[1U];
-  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-        uint32_t RESERVED11[1U];
-  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-        uint32_t RESERVED12[1U];
-  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-        uint32_t RESERVED13[1U];
-  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-        uint32_t RESERVED14[1U];
-  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-        uint32_t RESERVED15[1U];
-  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-        uint32_t RESERVED16[1U];
-  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-        uint32_t RESERVED17[1U];
-  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-        uint32_t RESERVED18[1U];
-  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-        uint32_t RESERVED19[1U];
-  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-        uint32_t RESERVED20[1U];
-  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-        uint32_t RESERVED21[1U];
-  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-        uint32_t RESERVED22[1U];
-  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-        uint32_t RESERVED23[1U];
-  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-        uint32_t RESERVED24[1U];
-  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-        uint32_t RESERVED25[1U];
-  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-        uint32_t RESERVED26[1U];
-  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-        uint32_t RESERVED27[1U];
-  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-        uint32_t RESERVED28[1U];
-  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-        uint32_t RESERVED29[1U];
-  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-        uint32_t RESERVED30[1U];
-  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-        uint32_t RESERVED31[1U];
-  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-        uint32_t RESERVED0[7U];
-  union {
-  __IOM uint32_t MAIR[2];
-  struct {
-  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-  };
-  };
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES                  1U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#endif
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-
-  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-  #endif
-
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-  #endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-  #endif
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Armv8-M Baseline */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Armv8-M Baseline */
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-           If VTOR is not present address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-  uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-  uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ##########################  MPU functions  #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv8.h"
-
-#endif
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                         /* Reload value impossible */
-  }
-
-  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                      SysTick_CTRL_TICKINT_Msk   |
-                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mml.h

@@ -1,2960 +0,0 @@
-/**************************************************************************//**
- * @file     core_armv8mml.h
- * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
- * @version  V5.0.4
- * @date     10. January 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_ARMV8MML_H_GENERIC
-#define __CORE_ARMV8MML_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_ARMv8MML
-  @{
- */
-
-#include "cmsis_version.h"
- 
-/*  CMSIS Armv8MML definitions */
-#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
-                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-  #if defined(__ARM_FEATURE_DSP)
-    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
-      #define __DSP_USED       1U
-    #else
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U    
-    #endif
-  #else
-    #define __DSP_USED         0U
-  #endif
-  
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-  #if defined(__ARM_FEATURE_DSP)
-    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
-      #define __DSP_USED       1U
-    #else
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U    
-    #endif
-  #else
-    #define __DSP_USED         0U
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-  
-  #if defined(__ARM_FEATURE_DSP)
-    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
-      #define __DSP_USED       1U
-    #else
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U    
-    #endif
-  #else
-    #define __DSP_USED         0U
-  #endif
-  
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-  #if defined(__ARM_FEATURE_DSP)
-    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
-      #define __DSP_USED       1U
-    #else
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U    
-    #endif
-  #else
-    #define __DSP_USED         0U
-  #endif
-  
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MML_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_ARMV8MML_H_DEPENDANT
-#define __CORE_ARMV8MML_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __ARMv8MML_REV
-    #define __ARMv8MML_REV               0x0000U
-    #warning "__ARMv8MML_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __SAUREGION_PRESENT
-    #define __SAUREGION_PRESENT       0U
-    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __DSP_PRESENT
-    #define __DSP_PRESENT             0U
-    #warning "__DSP_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv8MML */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
-    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
-    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
-    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
-#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
-
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[16U];
-  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[16U];
-  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[16U];
-  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[16U];
-  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[16U];
-  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-        uint32_t RESERVED5[16U];
-  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED6[580U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
-  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
-  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
-  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
-        uint32_t RESERVED3[92U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
-        uint32_t RESERVED4[15U];
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
-        uint32_t RESERVED5[1U];
-  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
-        uint32_t RESERVED6[1U];
-  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
-  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
-  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
-  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
-  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
-  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
-  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
-  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
-        uint32_t RESERVED7[6U];
-  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
-  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
-  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
-  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
-  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
-#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
-
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
-#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
-#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Non-Secure Access Control Register Definitions */
-#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
-#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
-
-#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
-#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
-
-#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
-#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[1U];
-  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
-        uint32_t RESERVED6[4U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Stimulus Port Register Definitions */
-#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
-#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
-
-#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
-#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
-#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
-
-#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
-#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-        uint32_t RESERVED3[1U];
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-        uint32_t RESERVED5[1U];
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED6[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-        uint32_t RESERVED7[1U];
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-        uint32_t RESERVED9[1U];
-  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-        uint32_t RESERVED10[1U];
-  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-        uint32_t RESERVED11[1U];
-  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-        uint32_t RESERVED12[1U];
-  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-        uint32_t RESERVED13[1U];
-  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-        uint32_t RESERVED14[1U];
-  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-        uint32_t RESERVED15[1U];
-  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-        uint32_t RESERVED16[1U];
-  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-        uint32_t RESERVED17[1U];
-  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-        uint32_t RESERVED18[1U];
-  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-        uint32_t RESERVED19[1U];
-  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-        uint32_t RESERVED20[1U];
-  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-        uint32_t RESERVED21[1U];
-  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-        uint32_t RESERVED22[1U];
-  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-        uint32_t RESERVED23[1U];
-  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-        uint32_t RESERVED24[1U];
-  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-        uint32_t RESERVED25[1U];
-  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-        uint32_t RESERVED26[1U];
-  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-        uint32_t RESERVED27[1U];
-  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-        uint32_t RESERVED28[1U];
-  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-        uint32_t RESERVED29[1U];
-  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-        uint32_t RESERVED30[1U];
-  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-        uint32_t RESERVED31[1U];
-  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-        uint32_t RESERVED32[934U];
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
-        uint32_t RESERVED33[1U];
-  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
-#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
-  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
-  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
-  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
-        uint32_t RESERVED0[1];
-  union {
-  __IOM uint32_t MAIR[2];
-  struct {
-  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-  };
-  };
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES                  4U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#else
-        uint32_t RESERVED0[3];
-#endif
-  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
-  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/* Secure Fault Status Register Definitions */
-#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
-#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
-
-#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
-#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
-
-#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
-#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
-
-#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
-#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
-
-#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
-#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
-
-#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
-#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
-
-#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
-#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
-
-#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
-#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
-#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
-
-#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
-#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
-
-#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
-#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
-
-#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
-#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
-
-#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
-#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
-
-#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
-#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
-#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
-#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
-  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
-  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
-  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-  #endif
-
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-  #endif
-
-  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
-  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
-  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-  #endif
-
-  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
-  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Set Priority Grouping (non-secure)
-  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB_NS->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping (non-secure)
-  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
-{
-  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ##########################  MPU functions  #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv8.h"
-
-#endif
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-  uint32_t mvfr0;
-
-  mvfr0 = FPU->MVFR0;
-  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
-  {
-    return 2U;           /* Double + Single precision FPU */
-  }
-  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
-  {
-    return 1U;           /* Single precision FPU */
-  }
-  else
-  {
-    return 0U;           /* No FPU */
-  }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                         /* Reload value impossible */
-  }
-
-  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                      SysTick_CTRL_TICKINT_Msk   |
-                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MML_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_dsp.h

@@ -1,74 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_xcc.h
- * @brief    CMSIS DSP Core Peripheral Access Layer Header File
- * @version  V1.0
- * @date     20. January 2019
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CORE_DSP_H_GENERIC
-#define __CORE_DSP_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-#define __STATIC_INLINE static inline
-
-#define __BKPT(value) do {} while(0)
-#define __NOP() do {} while(0)
-
-#define NVIC_SetPriorityGrouping(value) do {} while(0)
-#define NVIC_GetPriorityGrouping() do {} while(0)
-#define NVIC_EnableIRQ(value) do {} while(0)
-#define NVIC_GetEnableIRQ(value) do {} while(0)
-#define NVIC_DisableIRQ(value) do {} while(0)
-#define NVIC_GetPendingIRQ(value) do {} while(0)
-#define NVIC_SetPendingIRQ(value) do {} while(0)
-#define NVIC_ClearPendingIRQ(value) do {} while(0)
-#define NVIC_GetActive(value) do {} while(0)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_DSP_H_GENERIC */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0_features.h

@@ -1,13 +1,13 @@
 /*
 ** ###################################################################
-**     Version:             rev. 1.0, 2018-08-22
-**     Build:               b190418
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b220303
 **
 **     Abstract:
 **         Chip specific module features.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2019 NXP
+**     Copyright 2016-2022 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -18,6 +18,8 @@
 **     Revisions:
 **     - rev. 1.0 (2018-08-22)
 **         Initial version based on v0.2UM
+**     - rev. 1.1 (2019-05-16)
+**         Initial A1 version based on v1.3UM
 **
 ** ###################################################################
 */
@@ -73,7 +75,7 @@
 #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
 /* @brief PUF availability on the SoC. */
 #define FSL_FEATURE_SOC_PUF_COUNT (1)
-/* @brief RNG1 availability on the SoC. */
+/* @brief LPC_RNG1 availability on the SoC. */
 #define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
 /* @brief RTC availability on the SoC. */
 #define FSL_FEATURE_SOC_RTC_COUNT (1)
@@ -136,18 +138,66 @@
 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
 /* @brief Has offset trim (register OFSTRIM). */
 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
+/* @brief Has Trigger status register. */
+#define FSL_FEATURE_LPADC_HAS_TSTAT (1)
+/* @brief Has power select (bitfield CFG[PWRSEL]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1)
+/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0)
+/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0)
+/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0)
+/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
+/* @brief Conversion averaged bitfiled width. */
+#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3)
+/* @brief Has internal temperature sensor. */
+#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1)
+/* @brief Temperature sensor parameter A (slope). */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f)
+/* @brief Temperature sensor parameter B (offset). */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f)
+/* @brief Temperature sensor parameter Alpha. */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f)
+/* @brief the buffer size of temperature sensor. */
+#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U)
+
+/* ANALOGCTRL module features */
+
+/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */
+#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1)
+/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */
+#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0)
+/* @brief Has auxiliary bias(register AUX_BIAS). */
+#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1)
 
 /* CASPER module features */
 
 /* @brief Base address of the CASPER dedicated RAM */
 #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)
-/* @brief Interleaving of the CASPER dedicated RAM */
+/* @brief SW interleaving of the CASPER dedicated RAM */
 #define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)
+/* @brief CASPER dedicated RAM offset */
+#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE)
+
+/* CTIMER module features */
+
+/* @brief CTIMER has no capture channel. */
+#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0)
+/* @brief CTIMER has no capture 2 interrupt. */
+#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0)
+/* @brief CTIMER capture 3 interrupt. */
+#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
+/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */
+#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0)
+/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */
+#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
 
 /* DMA module features */
 
 /* @brief Number of channels */
-#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23)
 /* @brief Align size of DMA descriptor */
 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
 /* @brief DMA head link descriptor table align size */
@@ -155,6 +205,72 @@
 
 /* FLEXCOMM module features */
 
+/* @brief FLEXCOMM0 USART INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_USART_INDEX  (0)
+/* @brief FLEXCOMM0 SPI INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX  (0)
+/* @brief FLEXCOMM0 I2C INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX  (0)
+/* @brief FLEXCOMM0 I2S INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX  (0)
+/* @brief FLEXCOMM1 USART INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_USART_INDEX  (1)
+/* @brief FLEXCOMM1 SPI INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX  (1)
+/* @brief FLEXCOMM1 I2C INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX  (1)
+/* @brief FLEXCOMM1 I2S INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX  (1)
+/* @brief FLEXCOMM2 USART INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_USART_INDEX  (2)
+/* @brief FLEXCOMM2 SPI INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX  (2)
+/* @brief FLEXCOMM2 I2C INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX  (2)
+/* @brief FLEXCOMM2 I2S INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX  (2)
+/* @brief FLEXCOMM3 USART INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_USART_INDEX  (3)
+/* @brief FLEXCOMM3 SPI INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX  (3)
+/* @brief FLEXCOMM3 I2C INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX  (3)
+/* @brief FLEXCOMM3 I2S INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX  (3)
+/* @brief FLEXCOMM4 USART INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_USART_INDEX  (4)
+/* @brief FLEXCOMM4 SPI INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX  (4)
+/* @brief FLEXCOMM4 I2C INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX  (4)
+/* @brief FLEXCOMM4 I2S INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX  (4)
+/* @brief FLEXCOMM5 USART INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_USART_INDEX  (5)
+/* @brief FLEXCOMM5 SPI INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX  (5)
+/* @brief FLEXCOMM5 I2C INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX  (5)
+/* @brief FLEXCOMM5 I2S INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX  (5)
+/* @brief FLEXCOMM6 USART INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_USART_INDEX  (6)
+/* @brief FLEXCOMM6 SPI INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX  (6)
+/* @brief FLEXCOMM6 I2C INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX  (6)
+/* @brief FLEXCOMM6 I2S INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX  (6)
+/* @brief FLEXCOMM7 USART INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_USART_INDEX  (7)
+/* @brief FLEXCOMM7 SPI INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX  (7)
+/* @brief FLEXCOMM7 I2C INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX  (7)
+/* @brief FLEXCOMM7 I2S INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX  (7)
+/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX  (8)
 /* @brief I2S has DMIC interconnection */
 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0)
 
@@ -166,9 +282,9 @@
 /* I2S module features */
 
 /* @brief I2S support dual channel transfer. */
-#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
-/* @brief I2S has DMIC interconnection. */
-#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION  (0)
+#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0)
+/* @brief I2S has DMIC interconnection */
+#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0)
 
 /* IOCON module features */
 
@@ -190,10 +306,22 @@
 /* @brief Number of connected outputs */
 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
 
+/* PLU module features */
+
+/* @brief Has WAKEINT_CTRL register. */
+#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1)
+
+/* PMC module features */
+
+/* @brief UTICK does not support PD configure. */
+#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
+/* @brief WDT OSC does not support PD configure. */
+#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
+
 /* POWERLIB module features */
 
-/* @brief LPC55XX's Powerlib API is different with other LPC series devices. */
-#define FSL_FEATURE_POWERLIB_LPC55XX_EXTEND (1)
+/* @brief Powerlib API is different with other LPC series devices. */
+#define FSL_FEATURE_POWERLIB_EXTEND (1)
 
 /* POWERQUAD module features */
 
@@ -207,6 +335,10 @@
 /* @brief the shift status value */
 #define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
 
+/* RTC module features */
+
+/* No feature definitions */
+
 /* SCT module features */
 
 /* @brief Number of events */
@@ -221,13 +353,13 @@
 /* SDIF module features */
 
 /* @brief FIFO depth, every location is a WORD */
-#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS  (64)
+#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
 /* @brief Max DMA buffer size */
-#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE  (4096)
+#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
 /* @brief Max source clock in HZ */
-#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK  (52000000)
+#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
 /* @brief support 2 cards */
-#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD  (1)
+#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)
 
 /* SECPINT module features */
 
@@ -236,18 +368,22 @@
 
 /* SYSCON module features */
 
-/* @brief Pointer to ROM IAP entry functions */
-#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
 /* @brief Flash page size in bytes */
 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
 /* @brief Flash sector size in bytes */
 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
 /* @brief Flash size in bytes */
-#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592)
+#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (645120)
 /* @brief Has Power Down mode */
 #define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)
 /* @brief CCM_ANALOG availability on the SoC.  */
 #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
+/* @brief Starter register discontinuous. */
+#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
+
+/* SYSCTL1 module features */
+
+/* No feature definitions */
 
 /* USB module features */
 
@@ -289,17 +425,23 @@
 /* @brief USBHSH version */
 #define FSL_FEATURE_USBHSH_VERSION (300)
 
-/* UTICK module features */
+/* USBPHY module features */
 
-/* @brief UTICK does not support PD configure. */
-#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBHSD version */
+#define FSL_FEATURE_USBPHY_VERSION (300)
+/* @brief Number of the endpoint in USB HS */
+#define FSL_FEATURE_USBPHY_EP_NUM (6)
 
 /* WWDT module features */
 
+/* @brief Has no RESET register. */
+#define FSL_FEATURE_WWDT_HAS_NO_RESET (1)
 /* @brief WWDT does not support oscillator lock. */
 #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
-/* @brief WWDT does not support power down configure */
-#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
 
 #endif /* _LPC55S69_cm33_core0_FEATURES_H_ */
 

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1_features.h

@@ -1,13 +1,13 @@
 /*
 ** ###################################################################
-**     Version:             rev. 1.0, 2018-08-22
-**     Build:               b190418
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b220303
 **
 **     Abstract:
 **         Chip specific module features.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2019 NXP
+**     Copyright 2016-2022 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -18,6 +18,8 @@
 **     Revisions:
 **     - rev. 1.0 (2018-08-22)
 **         Initial version based on v0.2UM
+**     - rev. 1.1 (2019-05-16)
+**         Initial A1 version based on v1.3UM
 **
 ** ###################################################################
 */
@@ -73,7 +75,7 @@
 #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
 /* @brief PUF availability on the SoC. */
 #define FSL_FEATURE_SOC_PUF_COUNT (1)
-/* @brief RNG1 availability on the SoC. */
+/* @brief LPC_RNG1 availability on the SoC. */
 #define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
 /* @brief RTC availability on the SoC. */
 #define FSL_FEATURE_SOC_RTC_COUNT (1)
@@ -136,18 +138,66 @@
 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
 /* @brief Has offset trim (register OFSTRIM). */
 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
+/* @brief Has Trigger status register. */
+#define FSL_FEATURE_LPADC_HAS_TSTAT (1)
+/* @brief Has power select (bitfield CFG[PWRSEL]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1)
+/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0)
+/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0)
+/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0)
+/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
+/* @brief Conversion averaged bitfiled width. */
+#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3)
+/* @brief Has internal temperature sensor. */
+#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1)
+/* @brief Temperature sensor parameter A (slope). */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f)
+/* @brief Temperature sensor parameter B (offset). */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f)
+/* @brief Temperature sensor parameter Alpha. */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f)
+/* @brief the buffer size of temperature sensor. */
+#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U)
+
+/* ANALOGCTRL module features */
+
+/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */
+#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1)
+/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */
+#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0)
+/* @brief Has auxiliary bias(register AUX_BIAS). */
+#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1)
 
 /* CASPER module features */
 
 /* @brief Base address of the CASPER dedicated RAM */
 #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)
-/* @brief Interleaving of the CASPER dedicated RAM */
+/* @brief SW interleaving of the CASPER dedicated RAM */
 #define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)
+/* @brief CASPER dedicated RAM offset */
+#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE)
+
+/* CTIMER module features */
+
+/* @brief CTIMER has no capture channel. */
+#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0)
+/* @brief CTIMER has no capture 2 interrupt. */
+#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0)
+/* @brief CTIMER capture 3 interrupt. */
+#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
+/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */
+#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0)
+/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */
+#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
 
 /* DMA module features */
 
 /* @brief Number of channels */
-#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23)
 /* @brief Align size of DMA descriptor */
 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
 /* @brief DMA head link descriptor table align size */
@@ -155,6 +205,72 @@
 
 /* FLEXCOMM module features */
 
+/* @brief FLEXCOMM0 USART INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_USART_INDEX  (0)
+/* @brief FLEXCOMM0 SPI INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX  (0)
+/* @brief FLEXCOMM0 I2C INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX  (0)
+/* @brief FLEXCOMM0 I2S INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX  (0)
+/* @brief FLEXCOMM1 USART INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_USART_INDEX  (1)
+/* @brief FLEXCOMM1 SPI INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX  (1)
+/* @brief FLEXCOMM1 I2C INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX  (1)
+/* @brief FLEXCOMM1 I2S INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX  (1)
+/* @brief FLEXCOMM2 USART INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_USART_INDEX  (2)
+/* @brief FLEXCOMM2 SPI INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX  (2)
+/* @brief FLEXCOMM2 I2C INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX  (2)
+/* @brief FLEXCOMM2 I2S INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX  (2)
+/* @brief FLEXCOMM3 USART INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_USART_INDEX  (3)
+/* @brief FLEXCOMM3 SPI INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX  (3)
+/* @brief FLEXCOMM3 I2C INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX  (3)
+/* @brief FLEXCOMM3 I2S INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX  (3)
+/* @brief FLEXCOMM4 USART INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_USART_INDEX  (4)
+/* @brief FLEXCOMM4 SPI INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX  (4)
+/* @brief FLEXCOMM4 I2C INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX  (4)
+/* @brief FLEXCOMM4 I2S INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX  (4)
+/* @brief FLEXCOMM5 USART INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_USART_INDEX  (5)
+/* @brief FLEXCOMM5 SPI INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX  (5)
+/* @brief FLEXCOMM5 I2C INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX  (5)
+/* @brief FLEXCOMM5 I2S INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX  (5)
+/* @brief FLEXCOMM6 USART INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_USART_INDEX  (6)
+/* @brief FLEXCOMM6 SPI INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX  (6)
+/* @brief FLEXCOMM6 I2C INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX  (6)
+/* @brief FLEXCOMM6 I2S INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX  (6)
+/* @brief FLEXCOMM7 USART INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_USART_INDEX  (7)
+/* @brief FLEXCOMM7 SPI INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX  (7)
+/* @brief FLEXCOMM7 I2C INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX  (7)
+/* @brief FLEXCOMM7 I2S INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX  (7)
+/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX  (8)
 /* @brief I2S has DMIC interconnection */
 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0)
 
@@ -166,9 +282,9 @@
 /* I2S module features */
 
 /* @brief I2S support dual channel transfer. */
-#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
-/* @brief I2S has DMIC interconnection. */
-#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION  (0)
+#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0)
+/* @brief I2S has DMIC interconnection */
+#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0)
 
 /* IOCON module features */
 
@@ -190,10 +306,22 @@
 /* @brief Number of connected outputs */
 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
 
+/* PLU module features */
+
+/* @brief Has WAKEINT_CTRL register. */
+#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1)
+
+/* PMC module features */
+
+/* @brief UTICK does not support PD configure. */
+#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
+/* @brief WDT OSC does not support PD configure. */
+#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
+
 /* POWERLIB module features */
 
-/* @brief LPC55XX's Powerlib API is different with other LPC series devices. */
-#define FSL_FEATURE_POWERLIB_LPC55XX_EXTEND (1)
+/* @brief Powerlib API is different with other LPC series devices. */
+#define FSL_FEATURE_POWERLIB_EXTEND (1)
 
 /* POWERQUAD module features */
 
@@ -207,6 +335,10 @@
 /* @brief the shift status value */
 #define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
 
+/* RTC module features */
+
+/* No feature definitions */
+
 /* SCT module features */
 
 /* @brief Number of events */
@@ -221,13 +353,13 @@
 /* SDIF module features */
 
 /* @brief FIFO depth, every location is a WORD */
-#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS  (64)
+#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
 /* @brief Max DMA buffer size */
-#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE  (4096)
+#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
 /* @brief Max source clock in HZ */
-#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK  (52000000)
+#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
 /* @brief support 2 cards */
-#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD  (1)
+#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)
 
 /* SECPINT module features */
 
@@ -236,18 +368,22 @@
 
 /* SYSCON module features */
 
-/* @brief Pointer to ROM IAP entry functions */
-#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
 /* @brief Flash page size in bytes */
 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
 /* @brief Flash sector size in bytes */
 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
 /* @brief Flash size in bytes */
-#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592)
+#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (645120)
 /* @brief Has Power Down mode */
 #define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)
 /* @brief CCM_ANALOG availability on the SoC.  */
 #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
+/* @brief Starter register discontinuous. */
+#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
+
+/* SYSCTL1 module features */
+
+/* No feature definitions */
 
 /* USB module features */
 
@@ -289,17 +425,23 @@
 /* @brief USBHSH version */
 #define FSL_FEATURE_USBHSH_VERSION (300)
 
-/* UTICK module features */
+/* USBPHY module features */
 
-/* @brief UTICK does not support PD configure. */
-#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBHSD version */
+#define FSL_FEATURE_USBPHY_VERSION (300)
+/* @brief Number of the endpoint in USB HS */
+#define FSL_FEATURE_USBPHY_EP_NUM (6)
 
 /* WWDT module features */
 
+/* @brief Has no RESET register. */
+#define FSL_FEATURE_WWDT_HAS_NO_RESET (1)
 /* @brief WWDT does not support oscillator lock. */
 #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
-/* @brief WWDT does not support power down configure */
-#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
 
 #endif /* _LPC55S69_cm33_core1_FEATURES_H_ */
 

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash.scf

@@ -2,18 +2,19 @@
 /*
 ** ###################################################################
 **     Processors:          LPC55S69JBD100_cm33_core0
-**                          LPC55S69JET98_cm33_core0
+**                          LPC55S69JBD64_cm33_core0
+**                          LPC55S69JEV98_cm33_core0
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.2  15 Aug 2018
-**     Version:             rev. 1.0, 2018-08-22
-**     Build:               b181008
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b210928
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2021 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -47,7 +48,7 @@
 #define  m_text_size                   0x00071E00
 
 #define  m_core1_image_start           0x00072000
-#define  m_core1_image_size            0x00026000
+#define  m_core1_image_size            0x0002B800
 
 #if (defined(__use_shmem__))
   #define  m_data_start                0x20000000
@@ -66,12 +67,12 @@
 LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region
 
   VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
-    * (RESET,+FIRST)
+    * (.isr_vector,+FIRST)
   }
 
   ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
     * (InRoot$$Sections)
-    * (+RO)
+    .ANY (+RO)
   }
 
 #if (defined(__use_shmem__))
@@ -81,7 +82,7 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region siz
 #endif
 
   RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
-    * (+RW +ZI)
+    .ANY (+RW +ZI)
   }
   ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
   }
@@ -89,16 +90,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region siz
   }
 
   RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
-    * (m_usb_bdt)
+    * (*m_usb_bdt)
   }
 
   RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
-    * (m_usb_global)
+    * (*m_usb_global)
   }
 }
 
 LR_CORE1_IMAGE m_core1_image_start {
   CORE1_REGION m_core1_image_start m_core1_image_size {
-    *(M0CODE)
+    * (.core1_code)
   }
 }

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_ns.scf

@@ -2,18 +2,19 @@
 /*
 ** ###################################################################
 **     Processors:          LPC55S69JBD100_cm33_core0
-**                          LPC55S69JET98_cm33_core0
+**                          LPC55S69JBD64_cm33_core0
+**                          LPC55S69JEV98_cm33_core0
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.2  15 Aug 2018
-**     Version:             rev. 1.0, 2018-08-22
-**     Build:               b180921
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b190923
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2019 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -42,18 +43,18 @@
 
 /* The first 64kB of FLASH is used as secure memory. The rest of FLASH memory is non-secure memory. */
 #define  m_interrupts_start            0x00010000
-#define  m_interrupts_size             0x00000140
+#define  m_interrupts_size             0x00000200
 
-#define  m_text_start                  0x00010140
-#define  m_text_size                   0x00061EC0
+#define  m_text_start                  0x00010200
+#define  m_text_size                   0x00061E00
 
 #define  m_core1_image_start           0x00072000
-#define  m_core1_image_size            0x00026000
+#define  m_core1_image_size            0x0002B800
 
 /* The first 32kB of data RAM is used as secure memory. The rest of data RAM memory is non-secure memory. */
 #if (defined(__use_shmem__))
   #define  m_data_start                0x20008000
-  #define  m_data_size                 0x00028000
+  #define  m_data_size                 0x00029000
   #define  m_rpmsg_sh_mem_start        0x20031800
   #define  m_rpmsg_sh_mem_size         0x00001800
 #else
@@ -65,10 +66,15 @@
 #define  m_usb_sram_size               0x00004000
 
 
-LR_m_text m_text_start m_text_size {   ; load region size_region
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region
+
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (.isr_vector,+FIRST)
+  }
+
   ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
     * (InRoot$$Sections)
-    * (+RO)
+    .ANY (+RO)
   }
 
 #if (defined(__use_shmem__))
@@ -78,34 +84,24 @@ LR_m_text m_text_start m_text_size {   ; load region size_region
 #endif
 
   RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
-    * (+RW +ZI)
+    .ANY (+RW +ZI)
   }
   ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
   }
   ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
   }
-}
-
-LR_m_interrupts m_interrupts_start m_interrupts_size {
-  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
-    * (RESET,+FIRST)
-  }
-}
 
-LR_m_usb_bdt m_usb_sram_start usb_bdt_size {
-  ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
-    * (m_usb_bdt)
+  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+    * (*m_usb_bdt)
   }
-}
 
-LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) {
-  ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
-    * (m_usb_global)
+  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+    * (*m_usb_global)
   }
 }
 
 LR_CORE1_IMAGE m_core1_image_start {
   CORE1_REGION m_core1_image_start m_core1_image_size {
-    *(M0CODE)
+    * (.core1_code)
   }
 }

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_s.scf

@@ -2,18 +2,19 @@
 /*
 ** ###################################################################
 **     Processors:          LPC55S69JBD100_cm33_core0
-**                          LPC55S69JET98_cm33_core0
+**                          LPC55S69JBD64_cm33_core0
+**                          LPC55S69JEV98_cm33_core0
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.2  15 Aug 2018
-**     Version:             rev. 1.0, 2018-08-22
-**     Build:               b180921
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b190923
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2019 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -42,13 +43,13 @@
 
 /* Only the first 64kB of flash is used as secure memory. */
 #define  m_interrupts_start            0x10000000
-#define  m_interrupts_size             0x00000140
+#define  m_interrupts_size             0x00000200
 
-#define  m_text_start                  0x10000140
-#define  m_text_size                   0x0000FCC0
+#define  m_text_start                  0x10000200
+#define  m_text_size                   0x0000FC00
 
 #define  m_core1_image_start           0x10072000
-#define  m_core1_image_size            0x00026000
+#define  m_core1_image_size            0x0002B800
 
 /* Only first 32kB of data RAM is used as secure memory. */
 #if (defined(__use_shmem__))
@@ -70,10 +71,15 @@
 #define  m_usb_sram_size               0x00004000
 
 
-LR_m_text m_text_start m_text_size {   ; load region size_region
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size+m_veneer_table_size {   ; load region size_region
+
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (.isr_vector,+FIRST)
+  }
+
   ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
     * (InRoot$$Sections)
-    * (+RO)
+    .ANY (+RO)
   }
 
 #if (defined(__use_shmem__))
@@ -83,40 +89,28 @@ LR_m_text m_text_start m_text_size {   ; load region size_region
 #endif
 
   RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
-    * (+RW +ZI)
+    .ANY (+RW +ZI)
   }
   ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
   }
   ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
   }
-}
 
-LR_m_interrupts m_interrupts_start m_interrupts_size {
-  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
-    * (RESET,+FIRST)
-  }
-}
-
-LR_m_veneer_table m_veneer_table_start m_veneer_table_size {
-  ER_m_veneer_table m_veneer_table_start m_veneer_table_size {; veneer table
+  ER_m_veneer_table m_veneer_table_start FIXED m_veneer_table_size {; veneer table
     *(Veneer$$CMSE)
   }
-}
 
-LR_m_usb_bdt m_usb_sram_start usb_bdt_size {
-  ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
-    * (m_usb_bdt)
+  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+    * (*m_usb_bdt)
   }
-}
 
-LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) {
-  ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
-    * (m_usb_global)
+  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+    * (*m_usb_global)
   }
 }
 
 LR_CORE1_IMAGE m_core1_image_start {
   CORE1_REGION m_core1_image_start m_core1_image_size {
-    *(M0CODE)
+    * (.core1_code)
   }
 }

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_ram.scf

@@ -2,18 +2,19 @@
 /*
 ** ###################################################################
 **     Processors:          LPC55S69JBD100_cm33_core0
-**                          LPC55S69JET98_cm33_core0
+**                          LPC55S69JBD64_cm33_core0
+**                          LPC55S69JEV98_cm33_core0
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.2  15 Aug 2018
-**     Version:             rev. 1.0, 2018-08-22
-**     Build:               b181008
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b200722
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2020 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -47,7 +48,7 @@
 #define  m_text_size                   0x00007E00
 
 #define  m_core1_image_start           0x20033000
-#define  m_core1_image_size            0x00008800
+#define  m_core1_image_size            0x0000C800
 
 #if (defined(__use_shmem__))
   #define  m_data_start                0x20000000
@@ -66,12 +67,12 @@
 LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region
 
   VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
-    * (RESET,+FIRST)
+    * (.isr_vector,+FIRST)
   }
 
   ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
     * (InRoot$$Sections)
-    * (+RO)
+    .ANY (+RO)
   }
 
 #if (defined(__use_shmem__))
@@ -81,7 +82,7 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region siz
 #endif
 
   RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
-    * (+RW +ZI)
+    .ANY (+RW +ZI)
   }
   ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
   }
@@ -89,16 +90,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region siz
   }
 
   RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
-    * (m_usb_bdt)
+    * (*m_usb_bdt)
   }
 
   RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
-    * (m_usb_global)
+    * (*m_usb_global)
   }
 }
 
 LR_CORE1_IMAGE m_core1_image_start {
   CORE1_REGION m_core1_image_start m_core1_image_size {
-    *(M0CODE)
+    * (.core1_code)
   }
 }

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_flash.scf

@@ -2,18 +2,19 @@
 /*
 ** ###################################################################
 **     Processors:          LPC55S69JBD100_cm33_core1
-**                          LPC55S69JET98_cm33_core1
+**                          LPC55S69JBD64_cm33_core1
+**                          LPC55S69JEV98_cm33_core1
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.2  15 Aug 2018
-**     Version:             rev. 1.0, 2018-08-22
-**     Build:               b181008
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b210928
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2021 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -44,7 +45,7 @@
 #define  m_interrupts_size             0x00000200
 
 #define  m_text_start                  0x00072200
-#define  m_text_size                   0x00025E00
+#define  m_text_size                   0x0002B600
 
 
 #define  m_data_start                  0x20033000
@@ -62,17 +63,17 @@
 LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region
 
   VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
-    * (RESET,+FIRST)
+    * (.isr_vector,+FIRST)
   }
 
   ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
     * (InRoot$$Sections)
-    * (+RO)
+    .ANY (+RO)
   }
 
 
   RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
-    * (+RW +ZI)
+    .ANY (+RW +ZI)
   }
   ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
   }
@@ -80,11 +81,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region siz
   }
 
   RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
-    * (m_usb_bdt)
+    * (*m_usb_bdt)
   }
 
   RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
-    * (m_usb_global)
+    * (*m_usb_global)
+  }
+  #if (defined(__use_shmem__))
+  RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
+    * (rpmsg_sh_mem_section)
+  }
+  #endif
   }
-}
 

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram.scf

@@ -2,18 +2,19 @@
 /*
 ** ###################################################################
 **     Processors:          LPC55S69JBD100_cm33_core1
-**                          LPC55S69JET98_cm33_core1
+**                          LPC55S69JBD64_cm33_core1
+**                          LPC55S69JEV98_cm33_core1
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.2  15 Aug 2018
-**     Version:             rev. 1.0, 2018-08-22
-**     Build:               b181008
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b200722
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2020 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -44,11 +45,11 @@
 #define  m_interrupts_size             0x00000200
 
 #define  m_text_start                  0x20033200
-#define  m_text_size                   0x0000B600
+#define  m_text_size                   0x0000C600
 
 
-#define  m_data_start                  0x2003E800
-#define  m_data_size                   0x00005800
+#define  m_data_start                  0x2003F800
+#define  m_data_size                   0x00004800
 
 #if (defined(__use_shmem__))
   #define  m_rpmsg_sh_mem_start        0x20031800
@@ -62,17 +63,17 @@
 LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region
 
   VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
-    * (RESET,+FIRST)
+    * (.isr_vector,+FIRST)
   }
 
   ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
     * (InRoot$$Sections)
-    * (+RO)
+    .ANY (+RO)
   }
 
 
   RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
-    * (+RW +ZI)
+    .ANY (+RW +ZI)
   }
   ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
   }
@@ -80,16 +81,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region siz
   }
 
   RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
-    * (m_usb_bdt)
+    * (*m_usb_bdt)
   }
 
   RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
-    * (m_usb_global)
+    * (*m_usb_global)
   }
-#if (defined(__use_shmem__))   
+  #if (defined(__use_shmem__))
   RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
     * (rpmsg_sh_mem_section)
   }
-#endif
-}
+  #endif
+  }
 

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram_s.scf

@@ -2,18 +2,19 @@
 /*
 ** ###################################################################
 **     Processors:          LPC55S69JBD100_cm33_core1
-**                          LPC55S69JET98_cm33_core1
+**                          LPC55S69JBD64_cm33_core1
+**                          LPC55S69JEV98_cm33_core1
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.2  15 Aug 2018
-**     Version:             rev. 1.0, 2018-08-22
-**     Build:               b181008
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b190923
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2019 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -44,11 +45,11 @@
 #define  m_interrupts_size             0x00000200
 
 #define  m_text_start                  0x30033200
-#define  m_text_size                   0x0000B600
+#define  m_text_size                   0x0000C600
 
 
-#define  m_data_start                  0x3003E800
-#define  m_data_size                   0x00005800
+#define  m_data_start                  0x3003F800
+#define  m_data_size                   0x00004800
 
 #if (defined(__use_shmem__))
   #define  m_rpmsg_sh_mem_start        0x30031800
@@ -62,17 +63,17 @@
 LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region
 
   VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
-    * (RESET,+FIRST)
+    * (.isr_vector,+FIRST)
   }
 
   ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
     * (InRoot$$Sections)
-    * (+RO)
+    .ANY (+RO)
   }
 
 
   RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
-    * (+RW +ZI)
+    .ANY (+RW +ZI)
   }
   ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
   }
@@ -80,11 +81,11 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region siz
   }
 
   RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
-    * (m_usb_bdt)
+    * (*m_usb_bdt)
   }
 
   RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
-    * (m_usb_global)
+    * (*m_usb_global)
   }
 #if (defined(__use_shmem__))   
   RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0.s

@@ -1,732 +1,801 @@
-;/*****************************************************************************
-; * @file:    startup_LPC55S69_cm33_core0.s
-; * @purpose: CMSIS Cortex-M33 Core Device Startup File for the
-; *           LPC55S69_cm33_core0
-; * @version: 1.1
-; * @date:    2019-5-16
-; *
-; * Copyright 1997-2016 Freescale Semiconductor, Inc.
-; * Copyright 2016-2019 NXP
-; * All rights reserved.
-; *
-; * SPDX-License-Identifier: BSD-3-Clause
-; *
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; *****************************************************************************/
-
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
-
-__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-
-                DCD     NMI_Handler
-                DCD     HardFault_Handler
-                DCD     MemManage_Handler
-                DCD     BusFault_Handler
-                DCD     UsageFault_Handler
-__vector_table_0x1c
-                DCD     SecureFault_Handler
-                DCD     0
-                DCD     0                         ; Enhanced image marker, set to 0x0 for legacy boot
-                DCD     0                         ; Pointer to enhanced boot block, set to 0x0 for legacy boot
-                DCD     SVC_Handler
-                DCD     DebugMon_Handler
-                DCD     0
-                DCD     PendSV_Handler
-                DCD     SysTick_Handler
-
-                ; External Interrupts
-                DCD     WDT_BOD_IRQHandler  ; Windowed watchdog timer, Brownout detect, Flash interrupt
-                DCD     DMA0_IRQHandler  ; DMA0 controller
-                DCD     GINT0_IRQHandler  ; GPIO group 0
-                DCD     GINT1_IRQHandler  ; GPIO group 1
-                DCD     PIN_INT0_IRQHandler  ; Pin interrupt 0 or pattern match engine slice 0
-                DCD     PIN_INT1_IRQHandler  ; Pin interrupt 1or pattern match engine slice 1
-                DCD     PIN_INT2_IRQHandler  ; Pin interrupt 2 or pattern match engine slice 2
-                DCD     PIN_INT3_IRQHandler  ; Pin interrupt 3 or pattern match engine slice 3
-                DCD     UTICK0_IRQHandler  ; Micro-tick Timer
-                DCD     MRT0_IRQHandler  ; Multi-rate timer
-                DCD     CTIMER0_IRQHandler  ; Standard counter/timer CTIMER0
-                DCD     CTIMER1_IRQHandler  ; Standard counter/timer CTIMER1
-                DCD     SCT0_IRQHandler  ; SCTimer/PWM
-                DCD     CTIMER3_IRQHandler  ; Standard counter/timer CTIMER3
-                DCD     FLEXCOMM0_IRQHandler  ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM1_IRQHandler  ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM2_IRQHandler  ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM3_IRQHandler  ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM4_IRQHandler  ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM5_IRQHandler  ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM6_IRQHandler  ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM7_IRQHandler  ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     ADC0_IRQHandler  ; ADC0
-                DCD     Reserved39_IRQHandler  ; Reserved interrupt
-                DCD     ACMP_IRQHandler  ; ACMP  interrupts
-                DCD     Reserved41_IRQHandler  ; Reserved interrupt
-                DCD     Reserved42_IRQHandler  ; Reserved interrupt
-                DCD     USB0_NEEDCLK_IRQHandler  ; USB Activity Wake-up Interrupt
-                DCD     USB0_IRQHandler  ; USB device
-                DCD     RTC_IRQHandler  ; RTC alarm and wake-up interrupts
-                DCD     Reserved46_IRQHandler  ; Reserved interrupt
-                DCD     MAILBOX_IRQHandler  ; WAKEUP,Mailbox interrupt (present on selected devices)
-                DCD     PIN_INT4_IRQHandler  ; Pin interrupt 4 or pattern match engine slice 4 int
-                DCD     PIN_INT5_IRQHandler  ; Pin interrupt 5 or pattern match engine slice 5 int
-                DCD     PIN_INT6_IRQHandler  ; Pin interrupt 6 or pattern match engine slice 6 int
-                DCD     PIN_INT7_IRQHandler  ; Pin interrupt 7 or pattern match engine slice 7 int
-                DCD     CTIMER2_IRQHandler  ; Standard counter/timer CTIMER2
-                DCD     CTIMER4_IRQHandler  ; Standard counter/timer CTIMER4
-                DCD     OS_EVENT_IRQHandler  ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts
-                DCD     Reserved55_IRQHandler  ; Reserved interrupt
-                DCD     Reserved56_IRQHandler  ; Reserved interrupt
-                DCD     Reserved57_IRQHandler  ; Reserved interrupt
-                DCD     SDIO_IRQHandler  ; SD/MMC
-                DCD     Reserved59_IRQHandler  ; Reserved interrupt
-                DCD     Reserved60_IRQHandler  ; Reserved interrupt
-                DCD     Reserved61_IRQHandler  ; Reserved interrupt
-                DCD     USB1_UTMI_IRQHandler  ; USB1_UTMI
-                DCD     USB1_IRQHandler  ; USB1 interrupt
-                DCD     USB1_NEEDCLK_IRQHandler  ; USB1 activity
-                DCD     SEC_HYPERVISOR_CALL_IRQHandler  ; SEC_HYPERVISOR_CALL interrupt
-                DCD     SEC_GPIO_INT0_IRQ0_IRQHandler  ; SEC_GPIO_INT0_IRQ0 interrupt
-                DCD     SEC_GPIO_INT0_IRQ1_IRQHandler  ; SEC_GPIO_INT0_IRQ1 interrupt
-                DCD     PLU_IRQHandler  ; PLU interrupt
-                DCD     SEC_VIO_IRQHandler  ; SEC_VIO interrupt
-                DCD     HASHCRYPT_IRQHandler  ; HASHCRYPT interrupt
-                DCD     CASER_IRQHandler  ; CASPER interrupt
-                DCD     PUF_IRQHandler  ; PUF interrupt
-                DCD     PQ_IRQHandler  ; PQ interrupt
-                DCD     DMA1_IRQHandler  ; DMA1 interrupt
-                DCD     FLEXCOMM8_IRQHandler  ; Flexcomm Interface 8 (SPI, , FLEXCOMM)
-
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset Handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler               [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Base|
-
-                CPSID   I               ; Mask interrupts
-                LDR     R0, =|Image$$ARM_LIB_STACK$$ZI$$Base|
-                MSR     MSPLIM, R0
-                LDR     R0, =SystemInit
-                BLX     R0
-                CPSIE   I               ; Unmask interrupts
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-
-HardFault_Handler \
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-
-MemManage_Handler     PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-
-BusFault_Handler PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-
-UsageFault_Handler PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-
-SecureFault_Handler PROC
-                EXPORT  SecureFault_Handler       [WEAK]
-                B       .
-                ENDP
-
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-
-DebugMon_Handler PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-WDT_BOD_IRQHandler\
-                PROC
-                EXPORT     WDT_BOD_IRQHandler        [WEAK]
-                LDR        R0, =WDT_BOD_DriverIRQHandler
-                BX         R0
-                ENDP
-
-DMA0_IRQHandler\
-                PROC
-                EXPORT     DMA0_IRQHandler        [WEAK]
-                LDR        R0, =DMA0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-GINT0_IRQHandler\
-                PROC
-                EXPORT     GINT0_IRQHandler        [WEAK]
-                LDR        R0, =GINT0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-GINT1_IRQHandler\
-                PROC
-                EXPORT     GINT1_IRQHandler        [WEAK]
-                LDR        R0, =GINT1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT0_IRQHandler\
-                PROC
-                EXPORT     PIN_INT0_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT1_IRQHandler\
-                PROC
-                EXPORT     PIN_INT1_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT2_IRQHandler\
-                PROC
-                EXPORT     PIN_INT2_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT2_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT3_IRQHandler\
-                PROC
-                EXPORT     PIN_INT3_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT3_DriverIRQHandler
-                BX         R0
-                ENDP
-
-UTICK0_IRQHandler\
-                PROC
-                EXPORT     UTICK0_IRQHandler        [WEAK]
-                LDR        R0, =UTICK0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-MRT0_IRQHandler\
-                PROC
-                EXPORT     MRT0_IRQHandler        [WEAK]
-                LDR        R0, =MRT0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER0_IRQHandler\
-                PROC
-                EXPORT     CTIMER0_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER1_IRQHandler\
-                PROC
-                EXPORT     CTIMER1_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SCT0_IRQHandler\
-                PROC
-                EXPORT     SCT0_IRQHandler        [WEAK]
-                LDR        R0, =SCT0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER3_IRQHandler\
-                PROC
-                EXPORT     CTIMER3_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER3_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM0_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM0_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM1_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM1_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM2_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM2_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM2_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM3_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM3_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM3_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM4_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM4_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM4_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM5_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM5_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM5_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM6_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM6_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM6_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM7_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM7_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM7_DriverIRQHandler
-                BX         R0
-                ENDP
-
-ADC0_IRQHandler\
-                PROC
-                EXPORT     ADC0_IRQHandler        [WEAK]
-                LDR        R0, =ADC0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved39_IRQHandler\
-                PROC
-                EXPORT     Reserved39_IRQHandler        [WEAK]
-                LDR        R0, =Reserved39_DriverIRQHandler
-                BX         R0
-                ENDP
-
-ACMP_IRQHandler\
-                PROC
-                EXPORT     ACMP_IRQHandler        [WEAK]
-                LDR        R0, =ACMP_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved41_IRQHandler\
-                PROC
-                EXPORT     Reserved41_IRQHandler        [WEAK]
-                LDR        R0, =Reserved41_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved42_IRQHandler\
-                PROC
-                EXPORT     Reserved42_IRQHandler        [WEAK]
-                LDR        R0, =Reserved42_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB0_NEEDCLK_IRQHandler\
-                PROC
-                EXPORT     USB0_NEEDCLK_IRQHandler        [WEAK]
-                LDR        R0, =USB0_NEEDCLK_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB0_IRQHandler\
-                PROC
-                EXPORT     USB0_IRQHandler        [WEAK]
-                LDR        R0, =USB0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-RTC_IRQHandler\
-                PROC
-                EXPORT     RTC_IRQHandler        [WEAK]
-                LDR        R0, =RTC_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved46_IRQHandler\
-                PROC
-                EXPORT     Reserved46_IRQHandler        [WEAK]
-                LDR        R0, =Reserved46_DriverIRQHandler
-                BX         R0
-                ENDP
-
-MAILBOX_IRQHandler\
-                PROC
-                EXPORT     MAILBOX_IRQHandler        [WEAK]
-                LDR        R0, =MAILBOX_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT4_IRQHandler\
-                PROC
-                EXPORT     PIN_INT4_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT4_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT5_IRQHandler\
-                PROC
-                EXPORT     PIN_INT5_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT5_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT6_IRQHandler\
-                PROC
-                EXPORT     PIN_INT6_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT6_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT7_IRQHandler\
-                PROC
-                EXPORT     PIN_INT7_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT7_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER2_IRQHandler\
-                PROC
-                EXPORT     CTIMER2_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER2_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER4_IRQHandler\
-                PROC
-                EXPORT     CTIMER4_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER4_DriverIRQHandler
-                BX         R0
-                ENDP
-
-OS_EVENT_IRQHandler\
-                PROC
-                EXPORT     OS_EVENT_IRQHandler        [WEAK]
-                LDR        R0, =OS_EVENT_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved55_IRQHandler\
-                PROC
-                EXPORT     Reserved55_IRQHandler        [WEAK]
-                LDR        R0, =Reserved55_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved56_IRQHandler\
-                PROC
-                EXPORT     Reserved56_IRQHandler        [WEAK]
-                LDR        R0, =Reserved56_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved57_IRQHandler\
-                PROC
-                EXPORT     Reserved57_IRQHandler        [WEAK]
-                LDR        R0, =Reserved57_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SDIO_IRQHandler\
-                PROC
-                EXPORT     SDIO_IRQHandler        [WEAK]
-                LDR        R0, =SDIO_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved59_IRQHandler\
-                PROC
-                EXPORT     Reserved59_IRQHandler        [WEAK]
-                LDR        R0, =Reserved59_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved60_IRQHandler\
-                PROC
-                EXPORT     Reserved60_IRQHandler        [WEAK]
-                LDR        R0, =Reserved60_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved61_IRQHandler\
-                PROC
-                EXPORT     Reserved61_IRQHandler        [WEAK]
-                LDR        R0, =Reserved61_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB1_UTMI_IRQHandler\
-                PROC
-                EXPORT     USB1_UTMI_IRQHandler        [WEAK]
-                LDR        R0, =USB1_UTMI_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB1_IRQHandler\
-                PROC
-                EXPORT     USB1_IRQHandler        [WEAK]
-                LDR        R0, =USB1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB1_NEEDCLK_IRQHandler\
-                PROC
-                EXPORT     USB1_NEEDCLK_IRQHandler        [WEAK]
-                LDR        R0, =USB1_NEEDCLK_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SEC_HYPERVISOR_CALL_IRQHandler\
-                PROC
-                EXPORT     SEC_HYPERVISOR_CALL_IRQHandler        [WEAK]
-                LDR        R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SEC_GPIO_INT0_IRQ0_IRQHandler\
-                PROC
-                EXPORT     SEC_GPIO_INT0_IRQ0_IRQHandler        [WEAK]
-                LDR        R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SEC_GPIO_INT0_IRQ1_IRQHandler\
-                PROC
-                EXPORT     SEC_GPIO_INT0_IRQ1_IRQHandler        [WEAK]
-                LDR        R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PLU_IRQHandler\
-                PROC
-                EXPORT     PLU_IRQHandler        [WEAK]
-                LDR        R0, =PLU_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SEC_VIO_IRQHandler\
-                PROC
-                EXPORT     SEC_VIO_IRQHandler        [WEAK]
-                LDR        R0, =SEC_VIO_DriverIRQHandler
-                BX         R0
-                ENDP
-
-HASHCRYPT_IRQHandler\
-                PROC
-                EXPORT     HASHCRYPT_IRQHandler        [WEAK]
-                LDR        R0, =HASHCRYPT_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CASER_IRQHandler\
-                PROC
-                EXPORT     CASER_IRQHandler        [WEAK]
-                LDR        R0, =CASER_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PUF_IRQHandler\
-                PROC
-                EXPORT     PUF_IRQHandler        [WEAK]
-                LDR        R0, =PUF_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PQ_IRQHandler\
-                PROC
-                EXPORT     PQ_IRQHandler        [WEAK]
-                LDR        R0, =PQ_DriverIRQHandler
-                BX         R0
-                ENDP
-
-DMA1_IRQHandler\
-                PROC
-                EXPORT     DMA1_IRQHandler        [WEAK]
-                LDR        R0, =DMA1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM8_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM8_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM8_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Default_Handler PROC
-                EXPORT     WDT_BOD_DriverIRQHandler        [WEAK]
-                EXPORT     DMA0_DriverIRQHandler        [WEAK]
-                EXPORT     GINT0_DriverIRQHandler        [WEAK]
-                EXPORT     GINT1_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT0_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT1_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT2_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT3_DriverIRQHandler        [WEAK]
-                EXPORT     UTICK0_DriverIRQHandler        [WEAK]
-                EXPORT     MRT0_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER0_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER1_DriverIRQHandler        [WEAK]
-                EXPORT     SCT0_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER3_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM0_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM1_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM2_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM3_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM4_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM5_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM6_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM7_DriverIRQHandler        [WEAK]
-                EXPORT     ADC0_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved39_DriverIRQHandler        [WEAK]
-                EXPORT     ACMP_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved41_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved42_DriverIRQHandler        [WEAK]
-                EXPORT     USB0_NEEDCLK_DriverIRQHandler        [WEAK]
-                EXPORT     USB0_DriverIRQHandler        [WEAK]
-                EXPORT     RTC_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved46_DriverIRQHandler        [WEAK]
-                EXPORT     MAILBOX_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT4_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT5_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT6_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT7_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER2_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER4_DriverIRQHandler        [WEAK]
-                EXPORT     OS_EVENT_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved55_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved56_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved57_DriverIRQHandler        [WEAK]
-                EXPORT     SDIO_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved59_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved60_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved61_DriverIRQHandler        [WEAK]
-                EXPORT     USB1_UTMI_DriverIRQHandler        [WEAK]
-                EXPORT     USB1_DriverIRQHandler        [WEAK]
-                EXPORT     USB1_NEEDCLK_DriverIRQHandler        [WEAK]
-                EXPORT     SEC_HYPERVISOR_CALL_DriverIRQHandler        [WEAK]
-                EXPORT     SEC_GPIO_INT0_IRQ0_DriverIRQHandler        [WEAK]
-                EXPORT     SEC_GPIO_INT0_IRQ1_DriverIRQHandler        [WEAK]
-                EXPORT     PLU_DriverIRQHandler        [WEAK]
-                EXPORT     SEC_VIO_DriverIRQHandler        [WEAK]
-                EXPORT     HASHCRYPT_DriverIRQHandler        [WEAK]
-                EXPORT     CASER_DriverIRQHandler        [WEAK]
-                EXPORT     PUF_DriverIRQHandler        [WEAK]
-                EXPORT     PQ_DriverIRQHandler        [WEAK]
-                EXPORT     DMA1_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM8_DriverIRQHandler        [WEAK]
-
-WDT_BOD_DriverIRQHandler
-DMA0_DriverIRQHandler
-GINT0_DriverIRQHandler
-GINT1_DriverIRQHandler
-PIN_INT0_DriverIRQHandler
-PIN_INT1_DriverIRQHandler
-PIN_INT2_DriverIRQHandler
-PIN_INT3_DriverIRQHandler
-UTICK0_DriverIRQHandler
-MRT0_DriverIRQHandler
-CTIMER0_DriverIRQHandler
-CTIMER1_DriverIRQHandler
-SCT0_DriverIRQHandler
-CTIMER3_DriverIRQHandler
-FLEXCOMM0_DriverIRQHandler
-FLEXCOMM1_DriverIRQHandler
-FLEXCOMM2_DriverIRQHandler
-FLEXCOMM3_DriverIRQHandler
-FLEXCOMM4_DriverIRQHandler
-FLEXCOMM5_DriverIRQHandler
-FLEXCOMM6_DriverIRQHandler
-FLEXCOMM7_DriverIRQHandler
-ADC0_DriverIRQHandler
-Reserved39_DriverIRQHandler
-ACMP_DriverIRQHandler
-Reserved41_DriverIRQHandler
-Reserved42_DriverIRQHandler
-USB0_NEEDCLK_DriverIRQHandler
-USB0_DriverIRQHandler
-RTC_DriverIRQHandler
-Reserved46_DriverIRQHandler
-MAILBOX_DriverIRQHandler
-PIN_INT4_DriverIRQHandler
-PIN_INT5_DriverIRQHandler
-PIN_INT6_DriverIRQHandler
-PIN_INT7_DriverIRQHandler
-CTIMER2_DriverIRQHandler
-CTIMER4_DriverIRQHandler
-OS_EVENT_DriverIRQHandler
-Reserved55_DriverIRQHandler
-Reserved56_DriverIRQHandler
-Reserved57_DriverIRQHandler
-SDIO_DriverIRQHandler
-Reserved59_DriverIRQHandler
-Reserved60_DriverIRQHandler
-Reserved61_DriverIRQHandler
-USB1_UTMI_DriverIRQHandler
-USB1_DriverIRQHandler
-USB1_NEEDCLK_DriverIRQHandler
-SEC_HYPERVISOR_CALL_DriverIRQHandler
-SEC_GPIO_INT0_IRQ0_DriverIRQHandler
-SEC_GPIO_INT0_IRQ1_DriverIRQHandler
-PLU_DriverIRQHandler
-SEC_VIO_DriverIRQHandler
-HASHCRYPT_DriverIRQHandler
-CASER_DriverIRQHandler
-PUF_DriverIRQHandler
-PQ_DriverIRQHandler
-DMA1_DriverIRQHandler
-FLEXCOMM8_DriverIRQHandler
-
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-                END
-
+/* ---------------------------------------------------------------------------------------
+ * @file:    startup_LPC55S69_cm33_core0.s
+ * @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S69_cm33_core0
+ * @version: 1.1
+ * @date:    2019-5-16
+ * ---------------------------------------------------------------------------------------*/
+/*
+ * Copyright 1997-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+
+    .syntax unified
+    .arch armv8-m.main
+    .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __Vectors
+
+__Vectors:
+    .long    Image$$ARM_LIB_STACK$$ZI$$Limit                /* Top of Stack */
+    .long    Reset_Handler                                   /* Reset Handler */
+    .long    NMI_Handler                                     /* NMI Handler*/
+    .long    HardFault_Handler                               /* Hard Fault Handler*/
+    .long    MemManage_Handler                               /* MPU Fault Handler*/
+    .long    BusFault_Handler                                /* Bus Fault Handler*/
+    .long    UsageFault_Handler                              /* Usage Fault Handler*/
+    .long    SecureFault_Handler                             /* Secure Fault Handler*/
+    .long    0                                               /* Reserved*/
+    .long    0                                               /* Reserved*/
+    .long    0                                               /* Reserved*/
+    .long    SVC_Handler                                     /* SVCall Handler*/
+    .long    DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long    0                                               /* Reserved*/
+    .long    PendSV_Handler                                  /* PendSV Handler*/
+    .long    SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long    WDT_BOD_IRQHandler                              /* Windowed watchdog timer, Brownout detect, Flash interrupt */
+    .long    DMA0_IRQHandler                              /* DMA0 controller */
+    .long    GINT0_IRQHandler                              /* GPIO group 0 */
+    .long    GINT1_IRQHandler                              /* GPIO group 1 */
+    .long    PIN_INT0_IRQHandler                              /* Pin interrupt 0 or pattern match engine slice 0 */
+    .long    PIN_INT1_IRQHandler                              /* Pin interrupt 1or pattern match engine slice 1 */
+    .long    PIN_INT2_IRQHandler                              /* Pin interrupt 2 or pattern match engine slice 2 */
+    .long    PIN_INT3_IRQHandler                              /* Pin interrupt 3 or pattern match engine slice 3 */
+    .long    UTICK0_IRQHandler                              /* Micro-tick Timer */
+    .long    MRT0_IRQHandler                              /* Multi-rate timer */
+    .long    CTIMER0_IRQHandler                              /* Standard counter/timer CTIMER0 */
+    .long    CTIMER1_IRQHandler                              /* Standard counter/timer CTIMER1 */
+    .long    SCT0_IRQHandler                              /* SCTimer/PWM */
+    .long    CTIMER3_IRQHandler                              /* Standard counter/timer CTIMER3 */
+    .long    FLEXCOMM0_IRQHandler                              /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM1_IRQHandler                              /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM2_IRQHandler                              /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM3_IRQHandler                              /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM4_IRQHandler                              /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM5_IRQHandler                              /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM6_IRQHandler                              /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM7_IRQHandler                              /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    ADC0_IRQHandler                              /* ADC0  */
+    .long    Reserved39_IRQHandler                              /* Reserved interrupt */
+    .long    ACMP_IRQHandler                              /* ACMP  interrupts */
+    .long    Reserved41_IRQHandler                              /* Reserved interrupt */
+    .long    Reserved42_IRQHandler                              /* Reserved interrupt */
+    .long    USB0_NEEDCLK_IRQHandler                              /* USB Activity Wake-up Interrupt */
+    .long    USB0_IRQHandler                              /* USB device */
+    .long    RTC_IRQHandler                              /* RTC alarm and wake-up interrupts */
+    .long    Reserved46_IRQHandler                              /* Reserved interrupt */
+    .long    MAILBOX_IRQHandler                              /* WAKEUP,Mailbox interrupt (present on selected devices) */
+    .long    PIN_INT4_IRQHandler                              /* Pin interrupt 4 or pattern match engine slice 4 int */
+    .long    PIN_INT5_IRQHandler                              /* Pin interrupt 5 or pattern match engine slice 5 int */
+    .long    PIN_INT6_IRQHandler                              /* Pin interrupt 6 or pattern match engine slice 6 int */
+    .long    PIN_INT7_IRQHandler                              /* Pin interrupt 7 or pattern match engine slice 7 int */
+    .long    CTIMER2_IRQHandler                              /* Standard counter/timer CTIMER2 */
+    .long    CTIMER4_IRQHandler                              /* Standard counter/timer CTIMER4 */
+    .long    OS_EVENT_IRQHandler                              /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
+    .long    Reserved55_IRQHandler                              /* Reserved interrupt */
+    .long    Reserved56_IRQHandler                              /* Reserved interrupt */
+    .long    Reserved57_IRQHandler                              /* Reserved interrupt */
+    .long    SDIO_IRQHandler                              /* SD/MMC  */
+    .long    Reserved59_IRQHandler                              /* Reserved interrupt */
+    .long    Reserved60_IRQHandler                              /* Reserved interrupt */
+    .long    Reserved61_IRQHandler                              /* Reserved interrupt */
+    .long    USB1_PHY_IRQHandler                              /* USB1_PHY */
+    .long    USB1_IRQHandler                              /* USB1 interrupt */
+    .long    USB1_NEEDCLK_IRQHandler                              /* USB1 activity */
+    .long    SEC_HYPERVISOR_CALL_IRQHandler                              /* SEC_HYPERVISOR_CALL interrupt */
+    .long    SEC_GPIO_INT0_IRQ0_IRQHandler                              /* SEC_GPIO_INT0_IRQ0 interrupt */
+    .long    SEC_GPIO_INT0_IRQ1_IRQHandler                              /* SEC_GPIO_INT0_IRQ1 interrupt */
+    .long    PLU_IRQHandler                              /* PLU interrupt */
+    .long    SEC_VIO_IRQHandler                              /* SEC_VIO interrupt */
+    .long    HASHCRYPT_IRQHandler                              /* HASHCRYPT interrupt */
+    .long    CASER_IRQHandler                              /* CASPER interrupt */
+    .long    PUF_IRQHandler                              /* PUF interrupt */
+    .long    PQ_IRQHandler                              /* PQ interrupt */
+    .long    DMA1_IRQHandler                              /* DMA1 interrupt */
+    .long    FLEXCOMM8_IRQHandler                              /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */
+    .size    __Vectors, . - __Vectors
+
+    .text
+    .thumb
+
+/* Reset Handler */
+    .thumb_func
+    .align 2
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+    .equ    VTOR, 0xE000ED08
+    ldr     r0, =VTOR
+    ldr     r1, =__Vectors
+    str     r1, [r0]
+    ldr     r2, [r1]
+    msr     msp, r2
+    ldr     R0, =Image$$ARM_LIB_STACK$$ZI$$Base
+    msr     msplim, R0
+    ldr     r0,=SystemInit
+    blx     r0
+    cpsie   i               /* Unmask interrupts */
+    ldr     r0,=__main
+    bx      r0
+
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+    .align 1
+    .thumb_func
+    .weak NMI_Handler
+    .type NMI_Handler, %function
+NMI_Handler:
+    ldr   r0,=NMI_Handler
+    bx    r0
+    .size NMI_Handler, . - NMI_Handler
+
+    .align 1
+    .thumb_func
+    .weak HardFault_Handler
+    .type HardFault_Handler, %function
+HardFault_Handler:
+    ldr   r0,=HardFault_Handler
+    bx    r0
+    .size HardFault_Handler, . - HardFault_Handler
+
+    .align 1
+    .thumb_func
+    .weak SVC_Handler
+    .type SVC_Handler, %function
+SVC_Handler:
+    ldr   r0,=SVC_Handler
+    bx    r0
+    .size SVC_Handler, . - SVC_Handler
+
+    .align 1
+    .thumb_func
+    .weak PendSV_Handler
+    .type PendSV_Handler, %function
+PendSV_Handler:
+    ldr   r0,=PendSV_Handler
+    bx    r0
+    .size PendSV_Handler, . - PendSV_Handler
+
+    .align 1
+    .thumb_func
+    .weak SysTick_Handler
+    .type SysTick_Handler, %function
+SysTick_Handler:
+    ldr   r0,=SysTick_Handler
+    bx    r0
+    .size SysTick_Handler, . - SysTick_Handler
+    .align 1
+    .thumb_func
+    .weak WDT_BOD_IRQHandler
+    .type WDT_BOD_IRQHandler, %function
+WDT_BOD_IRQHandler:
+    ldr   r0,=WDT_BOD_DriverIRQHandler
+    bx    r0
+    .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA0_IRQHandler
+    .type DMA0_IRQHandler, %function
+DMA0_IRQHandler:
+    ldr   r0,=DMA0_DriverIRQHandler
+    bx    r0
+    .size DMA0_IRQHandler, . - DMA0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak GINT0_IRQHandler
+    .type GINT0_IRQHandler, %function
+GINT0_IRQHandler:
+    ldr   r0,=GINT0_DriverIRQHandler
+    bx    r0
+    .size GINT0_IRQHandler, . - GINT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak GINT1_IRQHandler
+    .type GINT1_IRQHandler, %function
+GINT1_IRQHandler:
+    ldr   r0,=GINT1_DriverIRQHandler
+    bx    r0
+    .size GINT1_IRQHandler, . - GINT1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT0_IRQHandler
+    .type PIN_INT0_IRQHandler, %function
+PIN_INT0_IRQHandler:
+    ldr   r0,=PIN_INT0_DriverIRQHandler
+    bx    r0
+    .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT1_IRQHandler
+    .type PIN_INT1_IRQHandler, %function
+PIN_INT1_IRQHandler:
+    ldr   r0,=PIN_INT1_DriverIRQHandler
+    bx    r0
+    .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT2_IRQHandler
+    .type PIN_INT2_IRQHandler, %function
+PIN_INT2_IRQHandler:
+    ldr   r0,=PIN_INT2_DriverIRQHandler
+    bx    r0
+    .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT3_IRQHandler
+    .type PIN_INT3_IRQHandler, %function
+PIN_INT3_IRQHandler:
+    ldr   r0,=PIN_INT3_DriverIRQHandler
+    bx    r0
+    .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak UTICK0_IRQHandler
+    .type UTICK0_IRQHandler, %function
+UTICK0_IRQHandler:
+    ldr   r0,=UTICK0_DriverIRQHandler
+    bx    r0
+    .size UTICK0_IRQHandler, . - UTICK0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak MRT0_IRQHandler
+    .type MRT0_IRQHandler, %function
+MRT0_IRQHandler:
+    ldr   r0,=MRT0_DriverIRQHandler
+    bx    r0
+    .size MRT0_IRQHandler, . - MRT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER0_IRQHandler
+    .type CTIMER0_IRQHandler, %function
+CTIMER0_IRQHandler:
+    ldr   r0,=CTIMER0_DriverIRQHandler
+    bx    r0
+    .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER1_IRQHandler
+    .type CTIMER1_IRQHandler, %function
+CTIMER1_IRQHandler:
+    ldr   r0,=CTIMER1_DriverIRQHandler
+    bx    r0
+    .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SCT0_IRQHandler
+    .type SCT0_IRQHandler, %function
+SCT0_IRQHandler:
+    ldr   r0,=SCT0_DriverIRQHandler
+    bx    r0
+    .size SCT0_IRQHandler, . - SCT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER3_IRQHandler
+    .type CTIMER3_IRQHandler, %function
+CTIMER3_IRQHandler:
+    ldr   r0,=CTIMER3_DriverIRQHandler
+    bx    r0
+    .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM0_IRQHandler
+    .type FLEXCOMM0_IRQHandler, %function
+FLEXCOMM0_IRQHandler:
+    ldr   r0,=FLEXCOMM0_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM1_IRQHandler
+    .type FLEXCOMM1_IRQHandler, %function
+FLEXCOMM1_IRQHandler:
+    ldr   r0,=FLEXCOMM1_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM2_IRQHandler
+    .type FLEXCOMM2_IRQHandler, %function
+FLEXCOMM2_IRQHandler:
+    ldr   r0,=FLEXCOMM2_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM3_IRQHandler
+    .type FLEXCOMM3_IRQHandler, %function
+FLEXCOMM3_IRQHandler:
+    ldr   r0,=FLEXCOMM3_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM4_IRQHandler
+    .type FLEXCOMM4_IRQHandler, %function
+FLEXCOMM4_IRQHandler:
+    ldr   r0,=FLEXCOMM4_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM5_IRQHandler
+    .type FLEXCOMM5_IRQHandler, %function
+FLEXCOMM5_IRQHandler:
+    ldr   r0,=FLEXCOMM5_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM6_IRQHandler
+    .type FLEXCOMM6_IRQHandler, %function
+FLEXCOMM6_IRQHandler:
+    ldr   r0,=FLEXCOMM6_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM7_IRQHandler
+    .type FLEXCOMM7_IRQHandler, %function
+FLEXCOMM7_IRQHandler:
+    ldr   r0,=FLEXCOMM7_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ADC0_IRQHandler
+    .type ADC0_IRQHandler, %function
+ADC0_IRQHandler:
+    ldr   r0,=ADC0_DriverIRQHandler
+    bx    r0
+    .size ADC0_IRQHandler, . - ADC0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved39_IRQHandler
+    .type Reserved39_IRQHandler, %function
+Reserved39_IRQHandler:
+    ldr   r0,=Reserved39_DriverIRQHandler
+    bx    r0
+    .size Reserved39_IRQHandler, . - Reserved39_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ACMP_IRQHandler
+    .type ACMP_IRQHandler, %function
+ACMP_IRQHandler:
+    ldr   r0,=ACMP_DriverIRQHandler
+    bx    r0
+    .size ACMP_IRQHandler, . - ACMP_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved41_IRQHandler
+    .type Reserved41_IRQHandler, %function
+Reserved41_IRQHandler:
+    ldr   r0,=Reserved41_DriverIRQHandler
+    bx    r0
+    .size Reserved41_IRQHandler, . - Reserved41_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved42_IRQHandler
+    .type Reserved42_IRQHandler, %function
+Reserved42_IRQHandler:
+    ldr   r0,=Reserved42_DriverIRQHandler
+    bx    r0
+    .size Reserved42_IRQHandler, . - Reserved42_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB0_NEEDCLK_IRQHandler
+    .type USB0_NEEDCLK_IRQHandler, %function
+USB0_NEEDCLK_IRQHandler:
+    ldr   r0,=USB0_NEEDCLK_DriverIRQHandler
+    bx    r0
+    .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB0_IRQHandler
+    .type USB0_IRQHandler, %function
+USB0_IRQHandler:
+    ldr   r0,=USB0_DriverIRQHandler
+    bx    r0
+    .size USB0_IRQHandler, . - USB0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak RTC_IRQHandler
+    .type RTC_IRQHandler, %function
+RTC_IRQHandler:
+    ldr   r0,=RTC_DriverIRQHandler
+    bx    r0
+    .size RTC_IRQHandler, . - RTC_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved46_IRQHandler
+    .type Reserved46_IRQHandler, %function
+Reserved46_IRQHandler:
+    ldr   r0,=Reserved46_DriverIRQHandler
+    bx    r0
+    .size Reserved46_IRQHandler, . - Reserved46_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak MAILBOX_IRQHandler
+    .type MAILBOX_IRQHandler, %function
+MAILBOX_IRQHandler:
+    ldr   r0,=MAILBOX_DriverIRQHandler
+    bx    r0
+    .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT4_IRQHandler
+    .type PIN_INT4_IRQHandler, %function
+PIN_INT4_IRQHandler:
+    ldr   r0,=PIN_INT4_DriverIRQHandler
+    bx    r0
+    .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT5_IRQHandler
+    .type PIN_INT5_IRQHandler, %function
+PIN_INT5_IRQHandler:
+    ldr   r0,=PIN_INT5_DriverIRQHandler
+    bx    r0
+    .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT6_IRQHandler
+    .type PIN_INT6_IRQHandler, %function
+PIN_INT6_IRQHandler:
+    ldr   r0,=PIN_INT6_DriverIRQHandler
+    bx    r0
+    .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT7_IRQHandler
+    .type PIN_INT7_IRQHandler, %function
+PIN_INT7_IRQHandler:
+    ldr   r0,=PIN_INT7_DriverIRQHandler
+    bx    r0
+    .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER2_IRQHandler
+    .type CTIMER2_IRQHandler, %function
+CTIMER2_IRQHandler:
+    ldr   r0,=CTIMER2_DriverIRQHandler
+    bx    r0
+    .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER4_IRQHandler
+    .type CTIMER4_IRQHandler, %function
+CTIMER4_IRQHandler:
+    ldr   r0,=CTIMER4_DriverIRQHandler
+    bx    r0
+    .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak OS_EVENT_IRQHandler
+    .type OS_EVENT_IRQHandler, %function
+OS_EVENT_IRQHandler:
+    ldr   r0,=OS_EVENT_DriverIRQHandler
+    bx    r0
+    .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved55_IRQHandler
+    .type Reserved55_IRQHandler, %function
+Reserved55_IRQHandler:
+    ldr   r0,=Reserved55_DriverIRQHandler
+    bx    r0
+    .size Reserved55_IRQHandler, . - Reserved55_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved56_IRQHandler
+    .type Reserved56_IRQHandler, %function
+Reserved56_IRQHandler:
+    ldr   r0,=Reserved56_DriverIRQHandler
+    bx    r0
+    .size Reserved56_IRQHandler, . - Reserved56_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved57_IRQHandler
+    .type Reserved57_IRQHandler, %function
+Reserved57_IRQHandler:
+    ldr   r0,=Reserved57_DriverIRQHandler
+    bx    r0
+    .size Reserved57_IRQHandler, . - Reserved57_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SDIO_IRQHandler
+    .type SDIO_IRQHandler, %function
+SDIO_IRQHandler:
+    ldr   r0,=SDIO_DriverIRQHandler
+    bx    r0
+    .size SDIO_IRQHandler, . - SDIO_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved59_IRQHandler
+    .type Reserved59_IRQHandler, %function
+Reserved59_IRQHandler:
+    ldr   r0,=Reserved59_DriverIRQHandler
+    bx    r0
+    .size Reserved59_IRQHandler, . - Reserved59_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved60_IRQHandler
+    .type Reserved60_IRQHandler, %function
+Reserved60_IRQHandler:
+    ldr   r0,=Reserved60_DriverIRQHandler
+    bx    r0
+    .size Reserved60_IRQHandler, . - Reserved60_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved61_IRQHandler
+    .type Reserved61_IRQHandler, %function
+Reserved61_IRQHandler:
+    ldr   r0,=Reserved61_DriverIRQHandler
+    bx    r0
+    .size Reserved61_IRQHandler, . - Reserved61_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB1_PHY_IRQHandler
+    .type USB1_PHY_IRQHandler, %function
+USB1_PHY_IRQHandler:
+    ldr   r0,=USB1_PHY_DriverIRQHandler
+    bx    r0
+    .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB1_IRQHandler
+    .type USB1_IRQHandler, %function
+USB1_IRQHandler:
+    ldr   r0,=USB1_DriverIRQHandler
+    bx    r0
+    .size USB1_IRQHandler, . - USB1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB1_NEEDCLK_IRQHandler
+    .type USB1_NEEDCLK_IRQHandler, %function
+USB1_NEEDCLK_IRQHandler:
+    ldr   r0,=USB1_NEEDCLK_DriverIRQHandler
+    bx    r0
+    .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SEC_HYPERVISOR_CALL_IRQHandler
+    .type SEC_HYPERVISOR_CALL_IRQHandler, %function
+SEC_HYPERVISOR_CALL_IRQHandler:
+    ldr   r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler
+    bx    r0
+    .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SEC_GPIO_INT0_IRQ0_IRQHandler
+    .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function
+SEC_GPIO_INT0_IRQ0_IRQHandler:
+    ldr   r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler
+    bx    r0
+    .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SEC_GPIO_INT0_IRQ1_IRQHandler
+    .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function
+SEC_GPIO_INT0_IRQ1_IRQHandler:
+    ldr   r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler
+    bx    r0
+    .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PLU_IRQHandler
+    .type PLU_IRQHandler, %function
+PLU_IRQHandler:
+    ldr   r0,=PLU_DriverIRQHandler
+    bx    r0
+    .size PLU_IRQHandler, . - PLU_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SEC_VIO_IRQHandler
+    .type SEC_VIO_IRQHandler, %function
+SEC_VIO_IRQHandler:
+    ldr   r0,=SEC_VIO_DriverIRQHandler
+    bx    r0
+    .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak HASHCRYPT_IRQHandler
+    .type HASHCRYPT_IRQHandler, %function
+HASHCRYPT_IRQHandler:
+    ldr   r0,=HASHCRYPT_DriverIRQHandler
+    bx    r0
+    .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CASER_IRQHandler
+    .type CASER_IRQHandler, %function
+CASER_IRQHandler:
+    ldr   r0,=CASER_DriverIRQHandler
+    bx    r0
+    .size CASER_IRQHandler, . - CASER_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PUF_IRQHandler
+    .type PUF_IRQHandler, %function
+PUF_IRQHandler:
+    ldr   r0,=PUF_DriverIRQHandler
+    bx    r0
+    .size PUF_IRQHandler, . - PUF_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PQ_IRQHandler
+    .type PQ_IRQHandler, %function
+PQ_IRQHandler:
+    ldr   r0,=PQ_DriverIRQHandler
+    bx    r0
+    .size PQ_IRQHandler, . - PQ_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA1_IRQHandler
+    .type DMA1_IRQHandler, %function
+DMA1_IRQHandler:
+    ldr   r0,=DMA1_DriverIRQHandler
+    bx    r0
+    .size DMA1_IRQHandler, . - DMA1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM8_IRQHandler
+    .type FLEXCOMM8_IRQHandler, %function
+FLEXCOMM8_IRQHandler:
+    ldr   r0,=FLEXCOMM8_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler  handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+/* Exception Handlers */
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SecureFault_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    WDT_BOD_DriverIRQHandler              /* Windowed watchdog timer, Brownout detect, Flash interrupt */
+    def_irq_handler    DMA0_DriverIRQHandler              /* DMA0 controller */
+    def_irq_handler    GINT0_DriverIRQHandler              /* GPIO group 0 */
+    def_irq_handler    GINT1_DriverIRQHandler              /* GPIO group 1 */
+    def_irq_handler    PIN_INT0_DriverIRQHandler              /* Pin interrupt 0 or pattern match engine slice 0 */
+    def_irq_handler    PIN_INT1_DriverIRQHandler              /* Pin interrupt 1or pattern match engine slice 1 */
+    def_irq_handler    PIN_INT2_DriverIRQHandler              /* Pin interrupt 2 or pattern match engine slice 2 */
+    def_irq_handler    PIN_INT3_DriverIRQHandler              /* Pin interrupt 3 or pattern match engine slice 3 */
+    def_irq_handler    UTICK0_DriverIRQHandler              /* Micro-tick Timer */
+    def_irq_handler    MRT0_DriverIRQHandler              /* Multi-rate timer */
+    def_irq_handler    CTIMER0_DriverIRQHandler              /* Standard counter/timer CTIMER0 */
+    def_irq_handler    CTIMER1_DriverIRQHandler              /* Standard counter/timer CTIMER1 */
+    def_irq_handler    SCT0_DriverIRQHandler              /* SCTimer/PWM */
+    def_irq_handler    CTIMER3_DriverIRQHandler              /* Standard counter/timer CTIMER3 */
+    def_irq_handler    FLEXCOMM0_DriverIRQHandler              /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM1_DriverIRQHandler              /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM2_DriverIRQHandler              /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM3_DriverIRQHandler              /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM4_DriverIRQHandler              /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM5_DriverIRQHandler              /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM6_DriverIRQHandler              /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM7_DriverIRQHandler              /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    ADC0_DriverIRQHandler              /* ADC0  */
+    def_irq_handler    Reserved39_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    ACMP_DriverIRQHandler              /* ACMP  interrupts */
+    def_irq_handler    Reserved41_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    Reserved42_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    USB0_NEEDCLK_DriverIRQHandler              /* USB Activity Wake-up Interrupt */
+    def_irq_handler    USB0_DriverIRQHandler              /* USB device */
+    def_irq_handler    RTC_DriverIRQHandler              /* RTC alarm and wake-up interrupts */
+    def_irq_handler    Reserved46_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    MAILBOX_DriverIRQHandler              /* WAKEUP,Mailbox interrupt (present on selected devices) */
+    def_irq_handler    PIN_INT4_DriverIRQHandler              /* Pin interrupt 4 or pattern match engine slice 4 int */
+    def_irq_handler    PIN_INT5_DriverIRQHandler              /* Pin interrupt 5 or pattern match engine slice 5 int */
+    def_irq_handler    PIN_INT6_DriverIRQHandler              /* Pin interrupt 6 or pattern match engine slice 6 int */
+    def_irq_handler    PIN_INT7_DriverIRQHandler              /* Pin interrupt 7 or pattern match engine slice 7 int */
+    def_irq_handler    CTIMER2_DriverIRQHandler              /* Standard counter/timer CTIMER2 */
+    def_irq_handler    CTIMER4_DriverIRQHandler              /* Standard counter/timer CTIMER4 */
+    def_irq_handler    OS_EVENT_DriverIRQHandler              /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
+    def_irq_handler    Reserved55_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    Reserved56_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    Reserved57_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    SDIO_DriverIRQHandler              /* SD/MMC  */
+    def_irq_handler    Reserved59_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    Reserved60_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    Reserved61_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    USB1_PHY_DriverIRQHandler              /* USB1_PHY */
+    def_irq_handler    USB1_DriverIRQHandler              /* USB1 interrupt */
+    def_irq_handler    USB1_NEEDCLK_DriverIRQHandler              /* USB1 activity */
+    def_irq_handler    SEC_HYPERVISOR_CALL_DriverIRQHandler              /* SEC_HYPERVISOR_CALL interrupt */
+    def_irq_handler    SEC_GPIO_INT0_IRQ0_DriverIRQHandler              /* SEC_GPIO_INT0_IRQ0 interrupt */
+    def_irq_handler    SEC_GPIO_INT0_IRQ1_DriverIRQHandler              /* SEC_GPIO_INT0_IRQ1 interrupt */
+    def_irq_handler    PLU_DriverIRQHandler              /* PLU interrupt */
+    def_irq_handler    SEC_VIO_DriverIRQHandler              /* SEC_VIO interrupt */
+    def_irq_handler    HASHCRYPT_DriverIRQHandler              /* HASHCRYPT interrupt */
+    def_irq_handler    CASER_DriverIRQHandler              /* CASPER interrupt */
+    def_irq_handler    PUF_DriverIRQHandler              /* PUF interrupt */
+    def_irq_handler    PQ_DriverIRQHandler              /* PQ interrupt */
+    def_irq_handler    DMA1_DriverIRQHandler              /* DMA1 interrupt */
+    def_irq_handler    FLEXCOMM8_DriverIRQHandler              /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */
+
+    .end

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0_ns.s

@@ -1,732 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC55S69_cm33_core0.s
-; * @purpose: CMSIS Cortex-M33 Core Device Startup File for the
-; *           LPC55S69_cm33_core0
-; * @version: 1.1
-; * @date:    2019-5-16
-; *
-; * Copyright 1997-2016 Freescale Semiconductor, Inc.
-; * Copyright 2016-2019 NXP
-; * All rights reserved.
-; *
-; * SPDX-License-Identifier: BSD-3-Clause
-; *
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; *****************************************************************************/
-
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
-
-__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-
-                DCD     NMI_Handler
-                DCD     HardFault_Handler
-                DCD     MemManage_Handler
-                DCD     BusFault_Handler
-                DCD     UsageFault_Handler
-__vector_table_0x1c
-                DCD     SecureFault_Handler
-                DCD     0
-                DCD     0                         ; Enhanced image marker, set to 0x0 for legacy boot
-                DCD     0                         ; Pointer to enhanced boot block, set to 0x0 for legacy boot
-                DCD     SVC_Handler
-                DCD     DebugMon_Handler
-                DCD     0
-                DCD     PendSV_Handler
-                DCD     SysTick_Handler
-
-                ; External Interrupts
-                DCD     WDT_BOD_IRQHandler  ; Windowed watchdog timer, Brownout detect, Flash interrupt
-                DCD     DMA0_IRQHandler  ; DMA0 controller
-                DCD     GINT0_IRQHandler  ; GPIO group 0
-                DCD     GINT1_IRQHandler  ; GPIO group 1
-                DCD     PIN_INT0_IRQHandler  ; Pin interrupt 0 or pattern match engine slice 0
-                DCD     PIN_INT1_IRQHandler  ; Pin interrupt 1or pattern match engine slice 1
-                DCD     PIN_INT2_IRQHandler  ; Pin interrupt 2 or pattern match engine slice 2
-                DCD     PIN_INT3_IRQHandler  ; Pin interrupt 3 or pattern match engine slice 3
-                DCD     UTICK0_IRQHandler  ; Micro-tick Timer
-                DCD     MRT0_IRQHandler  ; Multi-rate timer
-                DCD     CTIMER0_IRQHandler  ; Standard counter/timer CTIMER0
-                DCD     CTIMER1_IRQHandler  ; Standard counter/timer CTIMER1
-                DCD     SCT0_IRQHandler  ; SCTimer/PWM
-                DCD     CTIMER3_IRQHandler  ; Standard counter/timer CTIMER3
-                DCD     FLEXCOMM0_IRQHandler  ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM1_IRQHandler  ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM2_IRQHandler  ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM3_IRQHandler  ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM4_IRQHandler  ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM5_IRQHandler  ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM6_IRQHandler  ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM7_IRQHandler  ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     ADC0_IRQHandler  ; ADC0
-                DCD     Reserved39_IRQHandler  ; Reserved interrupt
-                DCD     ACMP_IRQHandler  ; ACMP  interrupts
-                DCD     Reserved41_IRQHandler  ; Reserved interrupt
-                DCD     Reserved42_IRQHandler  ; Reserved interrupt
-                DCD     USB0_NEEDCLK_IRQHandler  ; USB Activity Wake-up Interrupt
-                DCD     USB0_IRQHandler  ; USB device
-                DCD     RTC_IRQHandler  ; RTC alarm and wake-up interrupts
-                DCD     Reserved46_IRQHandler  ; Reserved interrupt
-                DCD     MAILBOX_IRQHandler  ; WAKEUP,Mailbox interrupt (present on selected devices)
-                DCD     PIN_INT4_IRQHandler  ; Pin interrupt 4 or pattern match engine slice 4 int
-                DCD     PIN_INT5_IRQHandler  ; Pin interrupt 5 or pattern match engine slice 5 int
-                DCD     PIN_INT6_IRQHandler  ; Pin interrupt 6 or pattern match engine slice 6 int
-                DCD     PIN_INT7_IRQHandler  ; Pin interrupt 7 or pattern match engine slice 7 int
-                DCD     CTIMER2_IRQHandler  ; Standard counter/timer CTIMER2
-                DCD     CTIMER4_IRQHandler  ; Standard counter/timer CTIMER4
-                DCD     OS_EVENT_IRQHandler  ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts
-                DCD     Reserved55_IRQHandler  ; Reserved interrupt
-                DCD     Reserved56_IRQHandler  ; Reserved interrupt
-                DCD     Reserved57_IRQHandler  ; Reserved interrupt
-                DCD     SDIO_IRQHandler  ; SD/MMC
-                DCD     Reserved59_IRQHandler  ; Reserved interrupt
-                DCD     Reserved60_IRQHandler  ; Reserved interrupt
-                DCD     Reserved61_IRQHandler  ; Reserved interrupt
-                DCD     USB1_UTMI_IRQHandler  ; USB1_UTMI
-                DCD     USB1_IRQHandler  ; USB1 interrupt
-                DCD     USB1_NEEDCLK_IRQHandler  ; USB1 activity
-                DCD     SEC_HYPERVISOR_CALL_IRQHandler  ; SEC_HYPERVISOR_CALL interrupt
-                DCD     SEC_GPIO_INT0_IRQ0_IRQHandler  ; SEC_GPIO_INT0_IRQ0 interrupt
-                DCD     SEC_GPIO_INT0_IRQ1_IRQHandler  ; SEC_GPIO_INT0_IRQ1 interrupt
-                DCD     PLU_IRQHandler  ; PLU interrupt
-                DCD     SEC_VIO_IRQHandler  ; SEC_VIO interrupt
-                DCD     HASHCRYPT_IRQHandler  ; HASHCRYPT interrupt
-                DCD     CASER_IRQHandler  ; CASPER interrupt
-                DCD     PUF_IRQHandler  ; PUF interrupt
-                DCD     PQ_IRQHandler  ; PQ interrupt
-                DCD     DMA1_IRQHandler  ; DMA1 interrupt
-                DCD     FLEXCOMM8_IRQHandler  ; Flexcomm Interface 8 (SPI, , FLEXCOMM)
-
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset Handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler               [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Base|
-
-                CPSID   I               ; Mask interrupts
-                LDR     R0, =|Image$$ARM_LIB_STACK$$ZI$$Base|
-                MSR     MSPLIM, R0
-                ;LDR     R0, =SystemInit
-                ;BLX     R0
-                CPSIE   I               ; Unmask interrupts
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-
-HardFault_Handler \
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-
-MemManage_Handler     PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-
-BusFault_Handler PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-
-UsageFault_Handler PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-
-SecureFault_Handler PROC
-                EXPORT  SecureFault_Handler       [WEAK]
-                B       .
-                ENDP
-
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-
-DebugMon_Handler PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-WDT_BOD_IRQHandler\
-                PROC
-                EXPORT     WDT_BOD_IRQHandler        [WEAK]
-                LDR        R0, =WDT_BOD_DriverIRQHandler
-                BX         R0
-                ENDP
-
-DMA0_IRQHandler\
-                PROC
-                EXPORT     DMA0_IRQHandler        [WEAK]
-                LDR        R0, =DMA0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-GINT0_IRQHandler\
-                PROC
-                EXPORT     GINT0_IRQHandler        [WEAK]
-                LDR        R0, =GINT0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-GINT1_IRQHandler\
-                PROC
-                EXPORT     GINT1_IRQHandler        [WEAK]
-                LDR        R0, =GINT1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT0_IRQHandler\
-                PROC
-                EXPORT     PIN_INT0_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT1_IRQHandler\
-                PROC
-                EXPORT     PIN_INT1_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT2_IRQHandler\
-                PROC
-                EXPORT     PIN_INT2_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT2_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT3_IRQHandler\
-                PROC
-                EXPORT     PIN_INT3_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT3_DriverIRQHandler
-                BX         R0
-                ENDP
-
-UTICK0_IRQHandler\
-                PROC
-                EXPORT     UTICK0_IRQHandler        [WEAK]
-                LDR        R0, =UTICK0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-MRT0_IRQHandler\
-                PROC
-                EXPORT     MRT0_IRQHandler        [WEAK]
-                LDR        R0, =MRT0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER0_IRQHandler\
-                PROC
-                EXPORT     CTIMER0_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER1_IRQHandler\
-                PROC
-                EXPORT     CTIMER1_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SCT0_IRQHandler\
-                PROC
-                EXPORT     SCT0_IRQHandler        [WEAK]
-                LDR        R0, =SCT0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER3_IRQHandler\
-                PROC
-                EXPORT     CTIMER3_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER3_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM0_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM0_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM1_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM1_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM2_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM2_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM2_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM3_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM3_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM3_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM4_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM4_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM4_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM5_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM5_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM5_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM6_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM6_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM6_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM7_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM7_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM7_DriverIRQHandler
-                BX         R0
-                ENDP
-
-ADC0_IRQHandler\
-                PROC
-                EXPORT     ADC0_IRQHandler        [WEAK]
-                LDR        R0, =ADC0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved39_IRQHandler\
-                PROC
-                EXPORT     Reserved39_IRQHandler        [WEAK]
-                LDR        R0, =Reserved39_DriverIRQHandler
-                BX         R0
-                ENDP
-
-ACMP_IRQHandler\
-                PROC
-                EXPORT     ACMP_IRQHandler        [WEAK]
-                LDR        R0, =ACMP_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved41_IRQHandler\
-                PROC
-                EXPORT     Reserved41_IRQHandler        [WEAK]
-                LDR        R0, =Reserved41_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved42_IRQHandler\
-                PROC
-                EXPORT     Reserved42_IRQHandler        [WEAK]
-                LDR        R0, =Reserved42_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB0_NEEDCLK_IRQHandler\
-                PROC
-                EXPORT     USB0_NEEDCLK_IRQHandler        [WEAK]
-                LDR        R0, =USB0_NEEDCLK_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB0_IRQHandler\
-                PROC
-                EXPORT     USB0_IRQHandler        [WEAK]
-                LDR        R0, =USB0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-RTC_IRQHandler\
-                PROC
-                EXPORT     RTC_IRQHandler        [WEAK]
-                LDR        R0, =RTC_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved46_IRQHandler\
-                PROC
-                EXPORT     Reserved46_IRQHandler        [WEAK]
-                LDR        R0, =Reserved46_DriverIRQHandler
-                BX         R0
-                ENDP
-
-MAILBOX_IRQHandler\
-                PROC
-                EXPORT     MAILBOX_IRQHandler        [WEAK]
-                LDR        R0, =MAILBOX_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT4_IRQHandler\
-                PROC
-                EXPORT     PIN_INT4_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT4_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT5_IRQHandler\
-                PROC
-                EXPORT     PIN_INT5_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT5_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT6_IRQHandler\
-                PROC
-                EXPORT     PIN_INT6_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT6_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT7_IRQHandler\
-                PROC
-                EXPORT     PIN_INT7_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT7_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER2_IRQHandler\
-                PROC
-                EXPORT     CTIMER2_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER2_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER4_IRQHandler\
-                PROC
-                EXPORT     CTIMER4_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER4_DriverIRQHandler
-                BX         R0
-                ENDP
-
-OS_EVENT_IRQHandler\
-                PROC
-                EXPORT     OS_EVENT_IRQHandler        [WEAK]
-                LDR        R0, =OS_EVENT_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved55_IRQHandler\
-                PROC
-                EXPORT     Reserved55_IRQHandler        [WEAK]
-                LDR        R0, =Reserved55_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved56_IRQHandler\
-                PROC
-                EXPORT     Reserved56_IRQHandler        [WEAK]
-                LDR        R0, =Reserved56_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved57_IRQHandler\
-                PROC
-                EXPORT     Reserved57_IRQHandler        [WEAK]
-                LDR        R0, =Reserved57_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SDIO_IRQHandler\
-                PROC
-                EXPORT     SDIO_IRQHandler        [WEAK]
-                LDR        R0, =SDIO_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved59_IRQHandler\
-                PROC
-                EXPORT     Reserved59_IRQHandler        [WEAK]
-                LDR        R0, =Reserved59_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved60_IRQHandler\
-                PROC
-                EXPORT     Reserved60_IRQHandler        [WEAK]
-                LDR        R0, =Reserved60_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved61_IRQHandler\
-                PROC
-                EXPORT     Reserved61_IRQHandler        [WEAK]
-                LDR        R0, =Reserved61_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB1_UTMI_IRQHandler\
-                PROC
-                EXPORT     USB1_UTMI_IRQHandler        [WEAK]
-                LDR        R0, =USB1_UTMI_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB1_IRQHandler\
-                PROC
-                EXPORT     USB1_IRQHandler        [WEAK]
-                LDR        R0, =USB1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB1_NEEDCLK_IRQHandler\
-                PROC
-                EXPORT     USB1_NEEDCLK_IRQHandler        [WEAK]
-                LDR        R0, =USB1_NEEDCLK_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SEC_HYPERVISOR_CALL_IRQHandler\
-                PROC
-                EXPORT     SEC_HYPERVISOR_CALL_IRQHandler        [WEAK]
-                LDR        R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SEC_GPIO_INT0_IRQ0_IRQHandler\
-                PROC
-                EXPORT     SEC_GPIO_INT0_IRQ0_IRQHandler        [WEAK]
-                LDR        R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SEC_GPIO_INT0_IRQ1_IRQHandler\
-                PROC
-                EXPORT     SEC_GPIO_INT0_IRQ1_IRQHandler        [WEAK]
-                LDR        R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PLU_IRQHandler\
-                PROC
-                EXPORT     PLU_IRQHandler        [WEAK]
-                LDR        R0, =PLU_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SEC_VIO_IRQHandler\
-                PROC
-                EXPORT     SEC_VIO_IRQHandler        [WEAK]
-                LDR        R0, =SEC_VIO_DriverIRQHandler
-                BX         R0
-                ENDP
-
-HASHCRYPT_IRQHandler\
-                PROC
-                EXPORT     HASHCRYPT_IRQHandler        [WEAK]
-                LDR        R0, =HASHCRYPT_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CASER_IRQHandler\
-                PROC
-                EXPORT     CASER_IRQHandler        [WEAK]
-                LDR        R0, =CASER_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PUF_IRQHandler\
-                PROC
-                EXPORT     PUF_IRQHandler        [WEAK]
-                LDR        R0, =PUF_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PQ_IRQHandler\
-                PROC
-                EXPORT     PQ_IRQHandler        [WEAK]
-                LDR        R0, =PQ_DriverIRQHandler
-                BX         R0
-                ENDP
-
-DMA1_IRQHandler\
-                PROC
-                EXPORT     DMA1_IRQHandler        [WEAK]
-                LDR        R0, =DMA1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM8_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM8_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM8_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Default_Handler PROC
-                EXPORT     WDT_BOD_DriverIRQHandler        [WEAK]
-                EXPORT     DMA0_DriverIRQHandler        [WEAK]
-                EXPORT     GINT0_DriverIRQHandler        [WEAK]
-                EXPORT     GINT1_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT0_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT1_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT2_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT3_DriverIRQHandler        [WEAK]
-                EXPORT     UTICK0_DriverIRQHandler        [WEAK]
-                EXPORT     MRT0_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER0_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER1_DriverIRQHandler        [WEAK]
-                EXPORT     SCT0_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER3_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM0_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM1_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM2_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM3_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM4_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM5_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM6_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM7_DriverIRQHandler        [WEAK]
-                EXPORT     ADC0_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved39_DriverIRQHandler        [WEAK]
-                EXPORT     ACMP_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved41_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved42_DriverIRQHandler        [WEAK]
-                EXPORT     USB0_NEEDCLK_DriverIRQHandler        [WEAK]
-                EXPORT     USB0_DriverIRQHandler        [WEAK]
-                EXPORT     RTC_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved46_DriverIRQHandler        [WEAK]
-                EXPORT     MAILBOX_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT4_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT5_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT6_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT7_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER2_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER4_DriverIRQHandler        [WEAK]
-                EXPORT     OS_EVENT_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved55_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved56_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved57_DriverIRQHandler        [WEAK]
-                EXPORT     SDIO_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved59_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved60_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved61_DriverIRQHandler        [WEAK]
-                EXPORT     USB1_UTMI_DriverIRQHandler        [WEAK]
-                EXPORT     USB1_DriverIRQHandler        [WEAK]
-                EXPORT     USB1_NEEDCLK_DriverIRQHandler        [WEAK]
-                EXPORT     SEC_HYPERVISOR_CALL_DriverIRQHandler        [WEAK]
-                EXPORT     SEC_GPIO_INT0_IRQ0_DriverIRQHandler        [WEAK]
-                EXPORT     SEC_GPIO_INT0_IRQ1_DriverIRQHandler        [WEAK]
-                EXPORT     PLU_DriverIRQHandler        [WEAK]
-                EXPORT     SEC_VIO_DriverIRQHandler        [WEAK]
-                EXPORT     HASHCRYPT_DriverIRQHandler        [WEAK]
-                EXPORT     CASER_DriverIRQHandler        [WEAK]
-                EXPORT     PUF_DriverIRQHandler        [WEAK]
-                EXPORT     PQ_DriverIRQHandler        [WEAK]
-                EXPORT     DMA1_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM8_DriverIRQHandler        [WEAK]
-
-WDT_BOD_DriverIRQHandler
-DMA0_DriverIRQHandler
-GINT0_DriverIRQHandler
-GINT1_DriverIRQHandler
-PIN_INT0_DriverIRQHandler
-PIN_INT1_DriverIRQHandler
-PIN_INT2_DriverIRQHandler
-PIN_INT3_DriverIRQHandler
-UTICK0_DriverIRQHandler
-MRT0_DriverIRQHandler
-CTIMER0_DriverIRQHandler
-CTIMER1_DriverIRQHandler
-SCT0_DriverIRQHandler
-CTIMER3_DriverIRQHandler
-FLEXCOMM0_DriverIRQHandler
-FLEXCOMM1_DriverIRQHandler
-FLEXCOMM2_DriverIRQHandler
-FLEXCOMM3_DriverIRQHandler
-FLEXCOMM4_DriverIRQHandler
-FLEXCOMM5_DriverIRQHandler
-FLEXCOMM6_DriverIRQHandler
-FLEXCOMM7_DriverIRQHandler
-ADC0_DriverIRQHandler
-Reserved39_DriverIRQHandler
-ACMP_DriverIRQHandler
-Reserved41_DriverIRQHandler
-Reserved42_DriverIRQHandler
-USB0_NEEDCLK_DriverIRQHandler
-USB0_DriverIRQHandler
-RTC_DriverIRQHandler
-Reserved46_DriverIRQHandler
-MAILBOX_DriverIRQHandler
-PIN_INT4_DriverIRQHandler
-PIN_INT5_DriverIRQHandler
-PIN_INT6_DriverIRQHandler
-PIN_INT7_DriverIRQHandler
-CTIMER2_DriverIRQHandler
-CTIMER4_DriverIRQHandler
-OS_EVENT_DriverIRQHandler
-Reserved55_DriverIRQHandler
-Reserved56_DriverIRQHandler
-Reserved57_DriverIRQHandler
-SDIO_DriverIRQHandler
-Reserved59_DriverIRQHandler
-Reserved60_DriverIRQHandler
-Reserved61_DriverIRQHandler
-USB1_UTMI_DriverIRQHandler
-USB1_DriverIRQHandler
-USB1_NEEDCLK_DriverIRQHandler
-SEC_HYPERVISOR_CALL_DriverIRQHandler
-SEC_GPIO_INT0_IRQ0_DriverIRQHandler
-SEC_GPIO_INT0_IRQ1_DriverIRQHandler
-PLU_DriverIRQHandler
-SEC_VIO_DriverIRQHandler
-HASHCRYPT_DriverIRQHandler
-CASER_DriverIRQHandler
-PUF_DriverIRQHandler
-PQ_DriverIRQHandler
-DMA1_DriverIRQHandler
-FLEXCOMM8_DriverIRQHandler
-
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-                END
-

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core1.s

@@ -1,732 +1,795 @@
-;/*****************************************************************************
-; * @file:    startup_LPC55S69_cm33_core1.s
-; * @purpose: CMSIS Cortex-M33 Core Device Startup File for the
-; *           LPC55S69_cm33_core1
-; * @version: 1.1
-; * @date:    2019-5-16
-; *
-; * Copyright 1997-2016 Freescale Semiconductor, Inc.
-; * Copyright 2016-2019 NXP
-; * All rights reserved.
-; *
-; * SPDX-License-Identifier: BSD-3-Clause
-; *
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; *****************************************************************************/
-
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
-
-__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-
-                DCD     NMI_Handler
-                DCD     HardFault_Handler
-                DCD     MemManage_Handler
-                DCD     BusFault_Handler
-                DCD     UsageFault_Handler
-__vector_table_0x1c
-                DCD     SecureFault_Handler
-                DCD     0
-                DCD     0                         ; Enhanced image marker, set to 0x0 for legacy boot
-                DCD     0                         ; Pointer to enhanced boot block, set to 0x0 for legacy boot
-                DCD     SVC_Handler
-                DCD     DebugMon_Handler
-                DCD     0
-                DCD     PendSV_Handler
-                DCD     SysTick_Handler
-
-                ; External Interrupts
-                DCD     WDT_BOD_IRQHandler  ; Windowed watchdog timer, Brownout detect, Flash interrupt
-                DCD     DMA0_IRQHandler  ; DMA0 controller
-                DCD     GINT0_IRQHandler  ; GPIO group 0
-                DCD     GINT1_IRQHandler  ; GPIO group 1
-                DCD     PIN_INT0_IRQHandler  ; Pin interrupt 0 or pattern match engine slice 0
-                DCD     PIN_INT1_IRQHandler  ; Pin interrupt 1or pattern match engine slice 1
-                DCD     PIN_INT2_IRQHandler  ; Pin interrupt 2 or pattern match engine slice 2
-                DCD     PIN_INT3_IRQHandler  ; Pin interrupt 3 or pattern match engine slice 3
-                DCD     UTICK0_IRQHandler  ; Micro-tick Timer
-                DCD     MRT0_IRQHandler  ; Multi-rate timer
-                DCD     CTIMER0_IRQHandler  ; Standard counter/timer CTIMER0
-                DCD     CTIMER1_IRQHandler  ; Standard counter/timer CTIMER1
-                DCD     SCT0_IRQHandler  ; SCTimer/PWM
-                DCD     CTIMER3_IRQHandler  ; Standard counter/timer CTIMER3
-                DCD     FLEXCOMM0_IRQHandler  ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM1_IRQHandler  ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM2_IRQHandler  ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM3_IRQHandler  ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM4_IRQHandler  ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM5_IRQHandler  ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM6_IRQHandler  ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     FLEXCOMM7_IRQHandler  ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM)
-                DCD     ADC0_IRQHandler  ; ADC0
-                DCD     Reserved39_IRQHandler  ; Reserved interrupt
-                DCD     ACMP_IRQHandler  ; ACMP  interrupts
-                DCD     Reserved41_IRQHandler  ; Reserved interrupt
-                DCD     Reserved42_IRQHandler  ; Reserved interrupt
-                DCD     USB0_NEEDCLK_IRQHandler  ; USB Activity Wake-up Interrupt
-                DCD     USB0_IRQHandler  ; USB device
-                DCD     RTC_IRQHandler  ; RTC alarm and wake-up interrupts
-                DCD     Reserved46_IRQHandler  ; Reserved interrupt
-                DCD     MAILBOX_IRQHandler  ; WAKEUP,Mailbox interrupt (present on selected devices)
-                DCD     PIN_INT4_IRQHandler  ; Pin interrupt 4 or pattern match engine slice 4 int
-                DCD     PIN_INT5_IRQHandler  ; Pin interrupt 5 or pattern match engine slice 5 int
-                DCD     PIN_INT6_IRQHandler  ; Pin interrupt 6 or pattern match engine slice 6 int
-                DCD     PIN_INT7_IRQHandler  ; Pin interrupt 7 or pattern match engine slice 7 int
-                DCD     CTIMER2_IRQHandler  ; Standard counter/timer CTIMER2
-                DCD     CTIMER4_IRQHandler  ; Standard counter/timer CTIMER4
-                DCD     OS_EVENT_IRQHandler  ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts
-                DCD     Reserved55_IRQHandler  ; Reserved interrupt
-                DCD     Reserved56_IRQHandler  ; Reserved interrupt
-                DCD     Reserved57_IRQHandler  ; Reserved interrupt
-                DCD     SDIO_IRQHandler  ; SD/MMC
-                DCD     Reserved59_IRQHandler  ; Reserved interrupt
-                DCD     Reserved60_IRQHandler  ; Reserved interrupt
-                DCD     Reserved61_IRQHandler  ; Reserved interrupt
-                DCD     USB1_UTMI_IRQHandler  ; USB1_UTMI
-                DCD     USB1_IRQHandler  ; USB1 interrupt
-                DCD     USB1_NEEDCLK_IRQHandler  ; USB1 activity
-                DCD     SEC_HYPERVISOR_CALL_IRQHandler  ; SEC_HYPERVISOR_CALL interrupt
-                DCD     SEC_GPIO_INT0_IRQ0_IRQHandler  ; SEC_GPIO_INT0_IRQ0 interrupt
-                DCD     SEC_GPIO_INT0_IRQ1_IRQHandler  ; SEC_GPIO_INT0_IRQ1 interrupt
-                DCD     PLU_IRQHandler  ; PLU interrupt
-                DCD     SEC_VIO_IRQHandler  ; SEC_VIO interrupt
-                DCD     HASHCRYPT_IRQHandler  ; HASHCRYPT interrupt
-                DCD     CASER_IRQHandler  ; CASPER interrupt
-                DCD     PUF_IRQHandler  ; PUF interrupt
-                DCD     PQ_IRQHandler  ; PQ interrupt
-                DCD     DMA1_IRQHandler  ; DMA1 interrupt
-                DCD     FLEXCOMM8_IRQHandler  ; Flexcomm Interface 8 (SPI, , FLEXCOMM)
-
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset Handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler               [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Base|
-
-                CPSID   I               ; Mask interrupts
-                LDR     R0, =|Image$$ARM_LIB_STACK$$ZI$$Base|
-                MSR     MSPLIM, R0
-                LDR     R0, =SystemInit
-                BLX     R0
-                CPSIE   I               ; Unmask interrupts
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-
-HardFault_Handler \
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-
-MemManage_Handler     PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-
-BusFault_Handler PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-
-UsageFault_Handler PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-
-SecureFault_Handler PROC
-                EXPORT  SecureFault_Handler       [WEAK]
-                B       .
-                ENDP
-
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-
-DebugMon_Handler PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-WDT_BOD_IRQHandler\
-                PROC
-                EXPORT     WDT_BOD_IRQHandler        [WEAK]
-                LDR        R0, =WDT_BOD_DriverIRQHandler
-                BX         R0
-                ENDP
-
-DMA0_IRQHandler\
-                PROC
-                EXPORT     DMA0_IRQHandler        [WEAK]
-                LDR        R0, =DMA0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-GINT0_IRQHandler\
-                PROC
-                EXPORT     GINT0_IRQHandler        [WEAK]
-                LDR        R0, =GINT0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-GINT1_IRQHandler\
-                PROC
-                EXPORT     GINT1_IRQHandler        [WEAK]
-                LDR        R0, =GINT1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT0_IRQHandler\
-                PROC
-                EXPORT     PIN_INT0_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT1_IRQHandler\
-                PROC
-                EXPORT     PIN_INT1_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT2_IRQHandler\
-                PROC
-                EXPORT     PIN_INT2_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT2_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT3_IRQHandler\
-                PROC
-                EXPORT     PIN_INT3_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT3_DriverIRQHandler
-                BX         R0
-                ENDP
-
-UTICK0_IRQHandler\
-                PROC
-                EXPORT     UTICK0_IRQHandler        [WEAK]
-                LDR        R0, =UTICK0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-MRT0_IRQHandler\
-                PROC
-                EXPORT     MRT0_IRQHandler        [WEAK]
-                LDR        R0, =MRT0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER0_IRQHandler\
-                PROC
-                EXPORT     CTIMER0_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER1_IRQHandler\
-                PROC
-                EXPORT     CTIMER1_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SCT0_IRQHandler\
-                PROC
-                EXPORT     SCT0_IRQHandler        [WEAK]
-                LDR        R0, =SCT0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER3_IRQHandler\
-                PROC
-                EXPORT     CTIMER3_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER3_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM0_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM0_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM1_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM1_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM2_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM2_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM2_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM3_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM3_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM3_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM4_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM4_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM4_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM5_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM5_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM5_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM6_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM6_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM6_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM7_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM7_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM7_DriverIRQHandler
-                BX         R0
-                ENDP
-
-ADC0_IRQHandler\
-                PROC
-                EXPORT     ADC0_IRQHandler        [WEAK]
-                LDR        R0, =ADC0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved39_IRQHandler\
-                PROC
-                EXPORT     Reserved39_IRQHandler        [WEAK]
-                LDR        R0, =Reserved39_DriverIRQHandler
-                BX         R0
-                ENDP
-
-ACMP_IRQHandler\
-                PROC
-                EXPORT     ACMP_IRQHandler        [WEAK]
-                LDR        R0, =ACMP_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved41_IRQHandler\
-                PROC
-                EXPORT     Reserved41_IRQHandler        [WEAK]
-                LDR        R0, =Reserved41_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved42_IRQHandler\
-                PROC
-                EXPORT     Reserved42_IRQHandler        [WEAK]
-                LDR        R0, =Reserved42_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB0_NEEDCLK_IRQHandler\
-                PROC
-                EXPORT     USB0_NEEDCLK_IRQHandler        [WEAK]
-                LDR        R0, =USB0_NEEDCLK_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB0_IRQHandler\
-                PROC
-                EXPORT     USB0_IRQHandler        [WEAK]
-                LDR        R0, =USB0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-RTC_IRQHandler\
-                PROC
-                EXPORT     RTC_IRQHandler        [WEAK]
-                LDR        R0, =RTC_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved46_IRQHandler\
-                PROC
-                EXPORT     Reserved46_IRQHandler        [WEAK]
-                LDR        R0, =Reserved46_DriverIRQHandler
-                BX         R0
-                ENDP
-
-MAILBOX_IRQHandler\
-                PROC
-                EXPORT     MAILBOX_IRQHandler        [WEAK]
-                LDR        R0, =MAILBOX_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT4_IRQHandler\
-                PROC
-                EXPORT     PIN_INT4_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT4_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT5_IRQHandler\
-                PROC
-                EXPORT     PIN_INT5_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT5_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT6_IRQHandler\
-                PROC
-                EXPORT     PIN_INT6_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT6_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT7_IRQHandler\
-                PROC
-                EXPORT     PIN_INT7_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT7_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER2_IRQHandler\
-                PROC
-                EXPORT     CTIMER2_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER2_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER4_IRQHandler\
-                PROC
-                EXPORT     CTIMER4_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER4_DriverIRQHandler
-                BX         R0
-                ENDP
-
-OS_EVENT_IRQHandler\
-                PROC
-                EXPORT     OS_EVENT_IRQHandler        [WEAK]
-                LDR        R0, =OS_EVENT_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved55_IRQHandler\
-                PROC
-                EXPORT     Reserved55_IRQHandler        [WEAK]
-                LDR        R0, =Reserved55_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved56_IRQHandler\
-                PROC
-                EXPORT     Reserved56_IRQHandler        [WEAK]
-                LDR        R0, =Reserved56_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved57_IRQHandler\
-                PROC
-                EXPORT     Reserved57_IRQHandler        [WEAK]
-                LDR        R0, =Reserved57_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SDIO_IRQHandler\
-                PROC
-                EXPORT     SDIO_IRQHandler        [WEAK]
-                LDR        R0, =SDIO_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved59_IRQHandler\
-                PROC
-                EXPORT     Reserved59_IRQHandler        [WEAK]
-                LDR        R0, =Reserved59_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved60_IRQHandler\
-                PROC
-                EXPORT     Reserved60_IRQHandler        [WEAK]
-                LDR        R0, =Reserved60_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved61_IRQHandler\
-                PROC
-                EXPORT     Reserved61_IRQHandler        [WEAK]
-                LDR        R0, =Reserved61_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB1_UTMI_IRQHandler\
-                PROC
-                EXPORT     USB1_UTMI_IRQHandler        [WEAK]
-                LDR        R0, =USB1_UTMI_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB1_IRQHandler\
-                PROC
-                EXPORT     USB1_IRQHandler        [WEAK]
-                LDR        R0, =USB1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB1_NEEDCLK_IRQHandler\
-                PROC
-                EXPORT     USB1_NEEDCLK_IRQHandler        [WEAK]
-                LDR        R0, =USB1_NEEDCLK_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SEC_HYPERVISOR_CALL_IRQHandler\
-                PROC
-                EXPORT     SEC_HYPERVISOR_CALL_IRQHandler        [WEAK]
-                LDR        R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SEC_GPIO_INT0_IRQ0_IRQHandler\
-                PROC
-                EXPORT     SEC_GPIO_INT0_IRQ0_IRQHandler        [WEAK]
-                LDR        R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SEC_GPIO_INT0_IRQ1_IRQHandler\
-                PROC
-                EXPORT     SEC_GPIO_INT0_IRQ1_IRQHandler        [WEAK]
-                LDR        R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PLU_IRQHandler\
-                PROC
-                EXPORT     PLU_IRQHandler        [WEAK]
-                LDR        R0, =PLU_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SEC_VIO_IRQHandler\
-                PROC
-                EXPORT     SEC_VIO_IRQHandler        [WEAK]
-                LDR        R0, =SEC_VIO_DriverIRQHandler
-                BX         R0
-                ENDP
-
-HASHCRYPT_IRQHandler\
-                PROC
-                EXPORT     HASHCRYPT_IRQHandler        [WEAK]
-                LDR        R0, =HASHCRYPT_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CASER_IRQHandler\
-                PROC
-                EXPORT     CASER_IRQHandler        [WEAK]
-                LDR        R0, =CASER_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PUF_IRQHandler\
-                PROC
-                EXPORT     PUF_IRQHandler        [WEAK]
-                LDR        R0, =PUF_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PQ_IRQHandler\
-                PROC
-                EXPORT     PQ_IRQHandler        [WEAK]
-                LDR        R0, =PQ_DriverIRQHandler
-                BX         R0
-                ENDP
-
-DMA1_IRQHandler\
-                PROC
-                EXPORT     DMA1_IRQHandler        [WEAK]
-                LDR        R0, =DMA1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM8_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM8_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM8_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Default_Handler PROC
-                EXPORT     WDT_BOD_DriverIRQHandler        [WEAK]
-                EXPORT     DMA0_DriverIRQHandler        [WEAK]
-                EXPORT     GINT0_DriverIRQHandler        [WEAK]
-                EXPORT     GINT1_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT0_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT1_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT2_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT3_DriverIRQHandler        [WEAK]
-                EXPORT     UTICK0_DriverIRQHandler        [WEAK]
-                EXPORT     MRT0_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER0_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER1_DriverIRQHandler        [WEAK]
-                EXPORT     SCT0_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER3_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM0_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM1_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM2_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM3_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM4_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM5_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM6_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM7_DriverIRQHandler        [WEAK]
-                EXPORT     ADC0_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved39_DriverIRQHandler        [WEAK]
-                EXPORT     ACMP_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved41_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved42_DriverIRQHandler        [WEAK]
-                EXPORT     USB0_NEEDCLK_DriverIRQHandler        [WEAK]
-                EXPORT     USB0_DriverIRQHandler        [WEAK]
-                EXPORT     RTC_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved46_DriverIRQHandler        [WEAK]
-                EXPORT     MAILBOX_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT4_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT5_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT6_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT7_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER2_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER4_DriverIRQHandler        [WEAK]
-                EXPORT     OS_EVENT_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved55_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved56_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved57_DriverIRQHandler        [WEAK]
-                EXPORT     SDIO_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved59_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved60_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved61_DriverIRQHandler        [WEAK]
-                EXPORT     USB1_UTMI_DriverIRQHandler        [WEAK]
-                EXPORT     USB1_DriverIRQHandler        [WEAK]
-                EXPORT     USB1_NEEDCLK_DriverIRQHandler        [WEAK]
-                EXPORT     SEC_HYPERVISOR_CALL_DriverIRQHandler        [WEAK]
-                EXPORT     SEC_GPIO_INT0_IRQ0_DriverIRQHandler        [WEAK]
-                EXPORT     SEC_GPIO_INT0_IRQ1_DriverIRQHandler        [WEAK]
-                EXPORT     PLU_DriverIRQHandler        [WEAK]
-                EXPORT     SEC_VIO_DriverIRQHandler        [WEAK]
-                EXPORT     HASHCRYPT_DriverIRQHandler        [WEAK]
-                EXPORT     CASER_DriverIRQHandler        [WEAK]
-                EXPORT     PUF_DriverIRQHandler        [WEAK]
-                EXPORT     PQ_DriverIRQHandler        [WEAK]
-                EXPORT     DMA1_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM8_DriverIRQHandler        [WEAK]
-
-WDT_BOD_DriverIRQHandler
-DMA0_DriverIRQHandler
-GINT0_DriverIRQHandler
-GINT1_DriverIRQHandler
-PIN_INT0_DriverIRQHandler
-PIN_INT1_DriverIRQHandler
-PIN_INT2_DriverIRQHandler
-PIN_INT3_DriverIRQHandler
-UTICK0_DriverIRQHandler
-MRT0_DriverIRQHandler
-CTIMER0_DriverIRQHandler
-CTIMER1_DriverIRQHandler
-SCT0_DriverIRQHandler
-CTIMER3_DriverIRQHandler
-FLEXCOMM0_DriverIRQHandler
-FLEXCOMM1_DriverIRQHandler
-FLEXCOMM2_DriverIRQHandler
-FLEXCOMM3_DriverIRQHandler
-FLEXCOMM4_DriverIRQHandler
-FLEXCOMM5_DriverIRQHandler
-FLEXCOMM6_DriverIRQHandler
-FLEXCOMM7_DriverIRQHandler
-ADC0_DriverIRQHandler
-Reserved39_DriverIRQHandler
-ACMP_DriverIRQHandler
-Reserved41_DriverIRQHandler
-Reserved42_DriverIRQHandler
-USB0_NEEDCLK_DriverIRQHandler
-USB0_DriverIRQHandler
-RTC_DriverIRQHandler
-Reserved46_DriverIRQHandler
-MAILBOX_DriverIRQHandler
-PIN_INT4_DriverIRQHandler
-PIN_INT5_DriverIRQHandler
-PIN_INT6_DriverIRQHandler
-PIN_INT7_DriverIRQHandler
-CTIMER2_DriverIRQHandler
-CTIMER4_DriverIRQHandler
-OS_EVENT_DriverIRQHandler
-Reserved55_DriverIRQHandler
-Reserved56_DriverIRQHandler
-Reserved57_DriverIRQHandler
-SDIO_DriverIRQHandler
-Reserved59_DriverIRQHandler
-Reserved60_DriverIRQHandler
-Reserved61_DriverIRQHandler
-USB1_UTMI_DriverIRQHandler
-USB1_DriverIRQHandler
-USB1_NEEDCLK_DriverIRQHandler
-SEC_HYPERVISOR_CALL_DriverIRQHandler
-SEC_GPIO_INT0_IRQ0_DriverIRQHandler
-SEC_GPIO_INT0_IRQ1_DriverIRQHandler
-PLU_DriverIRQHandler
-SEC_VIO_DriverIRQHandler
-HASHCRYPT_DriverIRQHandler
-CASER_DriverIRQHandler
-PUF_DriverIRQHandler
-PQ_DriverIRQHandler
-DMA1_DriverIRQHandler
-FLEXCOMM8_DriverIRQHandler
-
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-                END
-
+/* ---------------------------------------------------------------------------------------
+ * @file:    startup_LPC55S69_cm33_core1.s
+ * @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S69_cm33_core1
+ * @version: 1.1
+ * @date:    2019-5-16
+ * ---------------------------------------------------------------------------------------*/
+/*
+ * Copyright 1997-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+
+    .syntax unified
+    .arch armv8-m.main
+    .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __Vectors
+
+__Vectors:
+    .long    Image$$ARM_LIB_STACK$$ZI$$Limit                /* Top of Stack */
+    .long    Reset_Handler                                   /* Reset Handler */
+    .long    NMI_Handler                                     /* NMI Handler*/
+    .long    HardFault_Handler                               /* Hard Fault Handler*/
+    .long    MemManage_Handler                               /* MPU Fault Handler*/
+    .long    BusFault_Handler                                /* Bus Fault Handler*/
+    .long    UsageFault_Handler                              /* Usage Fault Handler*/
+    .long    SecureFault_Handler                             /* Secure Fault Handler*/
+    .long    0                                               /* Reserved*/
+    .long    0                                               /* Reserved*/
+    .long    0                                               /* Reserved*/
+    .long    SVC_Handler                                     /* SVCall Handler*/
+    .long    DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long    0                                               /* Reserved*/
+    .long    PendSV_Handler                                  /* PendSV Handler*/
+    .long    SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long    WDT_BOD_IRQHandler                              /* Windowed watchdog timer, Brownout detect, Flash interrupt */
+    .long    DMA0_IRQHandler                              /* DMA0 controller */
+    .long    GINT0_IRQHandler                              /* GPIO group 0 */
+    .long    GINT1_IRQHandler                              /* GPIO group 1 */
+    .long    PIN_INT0_IRQHandler                              /* Pin interrupt 0 or pattern match engine slice 0 */
+    .long    PIN_INT1_IRQHandler                              /* Pin interrupt 1or pattern match engine slice 1 */
+    .long    PIN_INT2_IRQHandler                              /* Pin interrupt 2 or pattern match engine slice 2 */
+    .long    PIN_INT3_IRQHandler                              /* Pin interrupt 3 or pattern match engine slice 3 */
+    .long    UTICK0_IRQHandler                              /* Micro-tick Timer */
+    .long    MRT0_IRQHandler                              /* Multi-rate timer */
+    .long    CTIMER0_IRQHandler                              /* Standard counter/timer CTIMER0 */
+    .long    CTIMER1_IRQHandler                              /* Standard counter/timer CTIMER1 */
+    .long    SCT0_IRQHandler                              /* SCTimer/PWM */
+    .long    CTIMER3_IRQHandler                              /* Standard counter/timer CTIMER3 */
+    .long    FLEXCOMM0_IRQHandler                              /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM1_IRQHandler                              /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM2_IRQHandler                              /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM3_IRQHandler                              /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM4_IRQHandler                              /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM5_IRQHandler                              /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM6_IRQHandler                              /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM7_IRQHandler                              /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    ADC0_IRQHandler                              /* ADC0  */
+    .long    Reserved39_IRQHandler                              /* Reserved interrupt */
+    .long    ACMP_IRQHandler                              /* ACMP  interrupts */
+    .long    Reserved41_IRQHandler                              /* Reserved interrupt */
+    .long    Reserved42_IRQHandler                              /* Reserved interrupt */
+    .long    USB0_NEEDCLK_IRQHandler                              /* USB Activity Wake-up Interrupt */
+    .long    USB0_IRQHandler                              /* USB device */
+    .long    RTC_IRQHandler                              /* RTC alarm and wake-up interrupts */
+    .long    Reserved46_IRQHandler                              /* Reserved interrupt */
+    .long    MAILBOX_IRQHandler                              /* WAKEUP,Mailbox interrupt (present on selected devices) */
+    .long    PIN_INT4_IRQHandler                              /* Pin interrupt 4 or pattern match engine slice 4 int */
+    .long    PIN_INT5_IRQHandler                              /* Pin interrupt 5 or pattern match engine slice 5 int */
+    .long    PIN_INT6_IRQHandler                              /* Pin interrupt 6 or pattern match engine slice 6 int */
+    .long    PIN_INT7_IRQHandler                              /* Pin interrupt 7 or pattern match engine slice 7 int */
+    .long    CTIMER2_IRQHandler                              /* Standard counter/timer CTIMER2 */
+    .long    CTIMER4_IRQHandler                              /* Standard counter/timer CTIMER4 */
+    .long    OS_EVENT_IRQHandler                              /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
+    .long    Reserved55_IRQHandler                              /* Reserved interrupt */
+    .long    Reserved56_IRQHandler                              /* Reserved interrupt */
+    .long    Reserved57_IRQHandler                              /* Reserved interrupt */
+    .long    SDIO_IRQHandler                              /* SD/MMC  */
+    .long    Reserved59_IRQHandler                              /* Reserved interrupt */
+    .long    Reserved60_IRQHandler                              /* Reserved interrupt */
+    .long    Reserved61_IRQHandler                              /* Reserved interrupt */
+    .long    USB1_PHY_IRQHandler                              /* USB1_PHY */
+    .long    USB1_IRQHandler                              /* USB1 interrupt */
+    .long    USB1_NEEDCLK_IRQHandler                              /* USB1 activity */
+    .long    SEC_HYPERVISOR_CALL_IRQHandler                              /* SEC_HYPERVISOR_CALL interrupt */
+    .long    SEC_GPIO_INT0_IRQ0_IRQHandler                              /* SEC_GPIO_INT0_IRQ0 interrupt */
+    .long    SEC_GPIO_INT0_IRQ1_IRQHandler                              /* SEC_GPIO_INT0_IRQ1 interrupt */
+    .long    PLU_IRQHandler                              /* PLU interrupt */
+    .long    SEC_VIO_IRQHandler                              /* SEC_VIO interrupt */
+    .long    HASHCRYPT_IRQHandler                              /* HASHCRYPT interrupt */
+    .long    CASER_IRQHandler                              /* CASPER interrupt */
+    .long    PUF_IRQHandler                              /* PUF interrupt */
+    .long    PQ_IRQHandler                              /* PQ interrupt */
+    .long    DMA1_IRQHandler                              /* DMA1 interrupt */
+    .long    FLEXCOMM8_IRQHandler                              /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */
+    .size    __Vectors, . - __Vectors
+
+    .text
+    .thumb
+
+/* Reset Handler */
+    .thumb_func
+    .align 2
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+
+Reset_Handler:
+    cpsid   i               /* mask interrupts */
+    ldr   r0, =Image$$ARM_LIB_STACK$$ZI$$Base
+    msr   msplim, r0
+    ldr   r0,=SystemInit
+    blx   r0
+    cpsie   i               /* Unmask interrupts */
+    ldr   r0,=__main
+    bx    r0
+
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+    .align 1
+    .thumb_func
+    .weak NMI_Handler
+    .type NMI_Handler, %function
+NMI_Handler:
+    ldr   r0,=NMI_Handler
+    bx    r0
+    .size NMI_Handler, . - NMI_Handler
+
+    .align 1
+    .thumb_func
+    .weak HardFault_Handler
+    .type HardFault_Handler, %function
+HardFault_Handler:
+    ldr   r0,=HardFault_Handler
+    bx    r0
+    .size HardFault_Handler, . - HardFault_Handler
+
+    .align 1
+    .thumb_func
+    .weak SVC_Handler
+    .type SVC_Handler, %function
+SVC_Handler:
+    ldr   r0,=SVC_Handler
+    bx    r0
+    .size SVC_Handler, . - SVC_Handler
+
+    .align 1
+    .thumb_func
+    .weak PendSV_Handler
+    .type PendSV_Handler, %function
+PendSV_Handler:
+    ldr   r0,=PendSV_Handler
+    bx    r0
+    .size PendSV_Handler, . - PendSV_Handler
+
+    .align 1
+    .thumb_func
+    .weak SysTick_Handler
+    .type SysTick_Handler, %function
+SysTick_Handler:
+    ldr   r0,=SysTick_Handler
+    bx    r0
+    .size SysTick_Handler, . - SysTick_Handler
+    .align 1
+    .thumb_func
+    .weak WDT_BOD_IRQHandler
+    .type WDT_BOD_IRQHandler, %function
+WDT_BOD_IRQHandler:
+    ldr   r0,=WDT_BOD_DriverIRQHandler
+    bx    r0
+    .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA0_IRQHandler
+    .type DMA0_IRQHandler, %function
+DMA0_IRQHandler:
+    ldr   r0,=DMA0_DriverIRQHandler
+    bx    r0
+    .size DMA0_IRQHandler, . - DMA0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak GINT0_IRQHandler
+    .type GINT0_IRQHandler, %function
+GINT0_IRQHandler:
+    ldr   r0,=GINT0_DriverIRQHandler
+    bx    r0
+    .size GINT0_IRQHandler, . - GINT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak GINT1_IRQHandler
+    .type GINT1_IRQHandler, %function
+GINT1_IRQHandler:
+    ldr   r0,=GINT1_DriverIRQHandler
+    bx    r0
+    .size GINT1_IRQHandler, . - GINT1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT0_IRQHandler
+    .type PIN_INT0_IRQHandler, %function
+PIN_INT0_IRQHandler:
+    ldr   r0,=PIN_INT0_DriverIRQHandler
+    bx    r0
+    .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT1_IRQHandler
+    .type PIN_INT1_IRQHandler, %function
+PIN_INT1_IRQHandler:
+    ldr   r0,=PIN_INT1_DriverIRQHandler
+    bx    r0
+    .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT2_IRQHandler
+    .type PIN_INT2_IRQHandler, %function
+PIN_INT2_IRQHandler:
+    ldr   r0,=PIN_INT2_DriverIRQHandler
+    bx    r0
+    .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT3_IRQHandler
+    .type PIN_INT3_IRQHandler, %function
+PIN_INT3_IRQHandler:
+    ldr   r0,=PIN_INT3_DriverIRQHandler
+    bx    r0
+    .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak UTICK0_IRQHandler
+    .type UTICK0_IRQHandler, %function
+UTICK0_IRQHandler:
+    ldr   r0,=UTICK0_DriverIRQHandler
+    bx    r0
+    .size UTICK0_IRQHandler, . - UTICK0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak MRT0_IRQHandler
+    .type MRT0_IRQHandler, %function
+MRT0_IRQHandler:
+    ldr   r0,=MRT0_DriverIRQHandler
+    bx    r0
+    .size MRT0_IRQHandler, . - MRT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER0_IRQHandler
+    .type CTIMER0_IRQHandler, %function
+CTIMER0_IRQHandler:
+    ldr   r0,=CTIMER0_DriverIRQHandler
+    bx    r0
+    .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER1_IRQHandler
+    .type CTIMER1_IRQHandler, %function
+CTIMER1_IRQHandler:
+    ldr   r0,=CTIMER1_DriverIRQHandler
+    bx    r0
+    .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SCT0_IRQHandler
+    .type SCT0_IRQHandler, %function
+SCT0_IRQHandler:
+    ldr   r0,=SCT0_DriverIRQHandler
+    bx    r0
+    .size SCT0_IRQHandler, . - SCT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER3_IRQHandler
+    .type CTIMER3_IRQHandler, %function
+CTIMER3_IRQHandler:
+    ldr   r0,=CTIMER3_DriverIRQHandler
+    bx    r0
+    .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM0_IRQHandler
+    .type FLEXCOMM0_IRQHandler, %function
+FLEXCOMM0_IRQHandler:
+    ldr   r0,=FLEXCOMM0_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM1_IRQHandler
+    .type FLEXCOMM1_IRQHandler, %function
+FLEXCOMM1_IRQHandler:
+    ldr   r0,=FLEXCOMM1_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM2_IRQHandler
+    .type FLEXCOMM2_IRQHandler, %function
+FLEXCOMM2_IRQHandler:
+    ldr   r0,=FLEXCOMM2_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM3_IRQHandler
+    .type FLEXCOMM3_IRQHandler, %function
+FLEXCOMM3_IRQHandler:
+    ldr   r0,=FLEXCOMM3_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM4_IRQHandler
+    .type FLEXCOMM4_IRQHandler, %function
+FLEXCOMM4_IRQHandler:
+    ldr   r0,=FLEXCOMM4_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM5_IRQHandler
+    .type FLEXCOMM5_IRQHandler, %function
+FLEXCOMM5_IRQHandler:
+    ldr   r0,=FLEXCOMM5_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM6_IRQHandler
+    .type FLEXCOMM6_IRQHandler, %function
+FLEXCOMM6_IRQHandler:
+    ldr   r0,=FLEXCOMM6_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM7_IRQHandler
+    .type FLEXCOMM7_IRQHandler, %function
+FLEXCOMM7_IRQHandler:
+    ldr   r0,=FLEXCOMM7_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ADC0_IRQHandler
+    .type ADC0_IRQHandler, %function
+ADC0_IRQHandler:
+    ldr   r0,=ADC0_DriverIRQHandler
+    bx    r0
+    .size ADC0_IRQHandler, . - ADC0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved39_IRQHandler
+    .type Reserved39_IRQHandler, %function
+Reserved39_IRQHandler:
+    ldr   r0,=Reserved39_DriverIRQHandler
+    bx    r0
+    .size Reserved39_IRQHandler, . - Reserved39_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ACMP_IRQHandler
+    .type ACMP_IRQHandler, %function
+ACMP_IRQHandler:
+    ldr   r0,=ACMP_DriverIRQHandler
+    bx    r0
+    .size ACMP_IRQHandler, . - ACMP_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved41_IRQHandler
+    .type Reserved41_IRQHandler, %function
+Reserved41_IRQHandler:
+    ldr   r0,=Reserved41_DriverIRQHandler
+    bx    r0
+    .size Reserved41_IRQHandler, . - Reserved41_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved42_IRQHandler
+    .type Reserved42_IRQHandler, %function
+Reserved42_IRQHandler:
+    ldr   r0,=Reserved42_DriverIRQHandler
+    bx    r0
+    .size Reserved42_IRQHandler, . - Reserved42_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB0_NEEDCLK_IRQHandler
+    .type USB0_NEEDCLK_IRQHandler, %function
+USB0_NEEDCLK_IRQHandler:
+    ldr   r0,=USB0_NEEDCLK_DriverIRQHandler
+    bx    r0
+    .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB0_IRQHandler
+    .type USB0_IRQHandler, %function
+USB0_IRQHandler:
+    ldr   r0,=USB0_DriverIRQHandler
+    bx    r0
+    .size USB0_IRQHandler, . - USB0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak RTC_IRQHandler
+    .type RTC_IRQHandler, %function
+RTC_IRQHandler:
+    ldr   r0,=RTC_DriverIRQHandler
+    bx    r0
+    .size RTC_IRQHandler, . - RTC_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved46_IRQHandler
+    .type Reserved46_IRQHandler, %function
+Reserved46_IRQHandler:
+    ldr   r0,=Reserved46_DriverIRQHandler
+    bx    r0
+    .size Reserved46_IRQHandler, . - Reserved46_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak MAILBOX_IRQHandler
+    .type MAILBOX_IRQHandler, %function
+MAILBOX_IRQHandler:
+    ldr   r0,=MAILBOX_DriverIRQHandler
+    bx    r0
+    .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT4_IRQHandler
+    .type PIN_INT4_IRQHandler, %function
+PIN_INT4_IRQHandler:
+    ldr   r0,=PIN_INT4_DriverIRQHandler
+    bx    r0
+    .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT5_IRQHandler
+    .type PIN_INT5_IRQHandler, %function
+PIN_INT5_IRQHandler:
+    ldr   r0,=PIN_INT5_DriverIRQHandler
+    bx    r0
+    .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT6_IRQHandler
+    .type PIN_INT6_IRQHandler, %function
+PIN_INT6_IRQHandler:
+    ldr   r0,=PIN_INT6_DriverIRQHandler
+    bx    r0
+    .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT7_IRQHandler
+    .type PIN_INT7_IRQHandler, %function
+PIN_INT7_IRQHandler:
+    ldr   r0,=PIN_INT7_DriverIRQHandler
+    bx    r0
+    .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER2_IRQHandler
+    .type CTIMER2_IRQHandler, %function
+CTIMER2_IRQHandler:
+    ldr   r0,=CTIMER2_DriverIRQHandler
+    bx    r0
+    .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER4_IRQHandler
+    .type CTIMER4_IRQHandler, %function
+CTIMER4_IRQHandler:
+    ldr   r0,=CTIMER4_DriverIRQHandler
+    bx    r0
+    .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak OS_EVENT_IRQHandler
+    .type OS_EVENT_IRQHandler, %function
+OS_EVENT_IRQHandler:
+    ldr   r0,=OS_EVENT_DriverIRQHandler
+    bx    r0
+    .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved55_IRQHandler
+    .type Reserved55_IRQHandler, %function
+Reserved55_IRQHandler:
+    ldr   r0,=Reserved55_DriverIRQHandler
+    bx    r0
+    .size Reserved55_IRQHandler, . - Reserved55_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved56_IRQHandler
+    .type Reserved56_IRQHandler, %function
+Reserved56_IRQHandler:
+    ldr   r0,=Reserved56_DriverIRQHandler
+    bx    r0
+    .size Reserved56_IRQHandler, . - Reserved56_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved57_IRQHandler
+    .type Reserved57_IRQHandler, %function
+Reserved57_IRQHandler:
+    ldr   r0,=Reserved57_DriverIRQHandler
+    bx    r0
+    .size Reserved57_IRQHandler, . - Reserved57_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SDIO_IRQHandler
+    .type SDIO_IRQHandler, %function
+SDIO_IRQHandler:
+    ldr   r0,=SDIO_DriverIRQHandler
+    bx    r0
+    .size SDIO_IRQHandler, . - SDIO_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved59_IRQHandler
+    .type Reserved59_IRQHandler, %function
+Reserved59_IRQHandler:
+    ldr   r0,=Reserved59_DriverIRQHandler
+    bx    r0
+    .size Reserved59_IRQHandler, . - Reserved59_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved60_IRQHandler
+    .type Reserved60_IRQHandler, %function
+Reserved60_IRQHandler:
+    ldr   r0,=Reserved60_DriverIRQHandler
+    bx    r0
+    .size Reserved60_IRQHandler, . - Reserved60_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved61_IRQHandler
+    .type Reserved61_IRQHandler, %function
+Reserved61_IRQHandler:
+    ldr   r0,=Reserved61_DriverIRQHandler
+    bx    r0
+    .size Reserved61_IRQHandler, . - Reserved61_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB1_PHY_IRQHandler
+    .type USB1_PHY_IRQHandler, %function
+USB1_PHY_IRQHandler:
+    ldr   r0,=USB1_PHY_DriverIRQHandler
+    bx    r0
+    .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB1_IRQHandler
+    .type USB1_IRQHandler, %function
+USB1_IRQHandler:
+    ldr   r0,=USB1_DriverIRQHandler
+    bx    r0
+    .size USB1_IRQHandler, . - USB1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB1_NEEDCLK_IRQHandler
+    .type USB1_NEEDCLK_IRQHandler, %function
+USB1_NEEDCLK_IRQHandler:
+    ldr   r0,=USB1_NEEDCLK_DriverIRQHandler
+    bx    r0
+    .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SEC_HYPERVISOR_CALL_IRQHandler
+    .type SEC_HYPERVISOR_CALL_IRQHandler, %function
+SEC_HYPERVISOR_CALL_IRQHandler:
+    ldr   r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler
+    bx    r0
+    .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SEC_GPIO_INT0_IRQ0_IRQHandler
+    .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function
+SEC_GPIO_INT0_IRQ0_IRQHandler:
+    ldr   r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler
+    bx    r0
+    .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SEC_GPIO_INT0_IRQ1_IRQHandler
+    .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function
+SEC_GPIO_INT0_IRQ1_IRQHandler:
+    ldr   r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler
+    bx    r0
+    .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PLU_IRQHandler
+    .type PLU_IRQHandler, %function
+PLU_IRQHandler:
+    ldr   r0,=PLU_DriverIRQHandler
+    bx    r0
+    .size PLU_IRQHandler, . - PLU_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SEC_VIO_IRQHandler
+    .type SEC_VIO_IRQHandler, %function
+SEC_VIO_IRQHandler:
+    ldr   r0,=SEC_VIO_DriverIRQHandler
+    bx    r0
+    .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak HASHCRYPT_IRQHandler
+    .type HASHCRYPT_IRQHandler, %function
+HASHCRYPT_IRQHandler:
+    ldr   r0,=HASHCRYPT_DriverIRQHandler
+    bx    r0
+    .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CASER_IRQHandler
+    .type CASER_IRQHandler, %function
+CASER_IRQHandler:
+    ldr   r0,=CASER_DriverIRQHandler
+    bx    r0
+    .size CASER_IRQHandler, . - CASER_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PUF_IRQHandler
+    .type PUF_IRQHandler, %function
+PUF_IRQHandler:
+    ldr   r0,=PUF_DriverIRQHandler
+    bx    r0
+    .size PUF_IRQHandler, . - PUF_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PQ_IRQHandler
+    .type PQ_IRQHandler, %function
+PQ_IRQHandler:
+    ldr   r0,=PQ_DriverIRQHandler
+    bx    r0
+    .size PQ_IRQHandler, . - PQ_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA1_IRQHandler
+    .type DMA1_IRQHandler, %function
+DMA1_IRQHandler:
+    ldr   r0,=DMA1_DriverIRQHandler
+    bx    r0
+    .size DMA1_IRQHandler, . - DMA1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM8_IRQHandler
+    .type FLEXCOMM8_IRQHandler, %function
+FLEXCOMM8_IRQHandler:
+    ldr   r0,=FLEXCOMM8_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler  handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+/* Exception Handlers */
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SecureFault_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    WDT_BOD_DriverIRQHandler              /* Windowed watchdog timer, Brownout detect, Flash interrupt */
+    def_irq_handler    DMA0_DriverIRQHandler              /* DMA0 controller */
+    def_irq_handler    GINT0_DriverIRQHandler              /* GPIO group 0 */
+    def_irq_handler    GINT1_DriverIRQHandler              /* GPIO group 1 */
+    def_irq_handler    PIN_INT0_DriverIRQHandler              /* Pin interrupt 0 or pattern match engine slice 0 */
+    def_irq_handler    PIN_INT1_DriverIRQHandler              /* Pin interrupt 1or pattern match engine slice 1 */
+    def_irq_handler    PIN_INT2_DriverIRQHandler              /* Pin interrupt 2 or pattern match engine slice 2 */
+    def_irq_handler    PIN_INT3_DriverIRQHandler              /* Pin interrupt 3 or pattern match engine slice 3 */
+    def_irq_handler    UTICK0_DriverIRQHandler              /* Micro-tick Timer */
+    def_irq_handler    MRT0_DriverIRQHandler              /* Multi-rate timer */
+    def_irq_handler    CTIMER0_DriverIRQHandler              /* Standard counter/timer CTIMER0 */
+    def_irq_handler    CTIMER1_DriverIRQHandler              /* Standard counter/timer CTIMER1 */
+    def_irq_handler    SCT0_DriverIRQHandler              /* SCTimer/PWM */
+    def_irq_handler    CTIMER3_DriverIRQHandler              /* Standard counter/timer CTIMER3 */
+    def_irq_handler    FLEXCOMM0_DriverIRQHandler              /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM1_DriverIRQHandler              /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM2_DriverIRQHandler              /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM3_DriverIRQHandler              /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM4_DriverIRQHandler              /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM5_DriverIRQHandler              /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM6_DriverIRQHandler              /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM7_DriverIRQHandler              /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    ADC0_DriverIRQHandler              /* ADC0  */
+    def_irq_handler    Reserved39_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    ACMP_DriverIRQHandler              /* ACMP  interrupts */
+    def_irq_handler    Reserved41_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    Reserved42_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    USB0_NEEDCLK_DriverIRQHandler              /* USB Activity Wake-up Interrupt */
+    def_irq_handler    USB0_DriverIRQHandler              /* USB device */
+    def_irq_handler    RTC_DriverIRQHandler              /* RTC alarm and wake-up interrupts */
+    def_irq_handler    Reserved46_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    MAILBOX_DriverIRQHandler              /* WAKEUP,Mailbox interrupt (present on selected devices) */
+    def_irq_handler    PIN_INT4_DriverIRQHandler              /* Pin interrupt 4 or pattern match engine slice 4 int */
+    def_irq_handler    PIN_INT5_DriverIRQHandler              /* Pin interrupt 5 or pattern match engine slice 5 int */
+    def_irq_handler    PIN_INT6_DriverIRQHandler              /* Pin interrupt 6 or pattern match engine slice 6 int */
+    def_irq_handler    PIN_INT7_DriverIRQHandler              /* Pin interrupt 7 or pattern match engine slice 7 int */
+    def_irq_handler    CTIMER2_DriverIRQHandler              /* Standard counter/timer CTIMER2 */
+    def_irq_handler    CTIMER4_DriverIRQHandler              /* Standard counter/timer CTIMER4 */
+    def_irq_handler    OS_EVENT_DriverIRQHandler              /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
+    def_irq_handler    Reserved55_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    Reserved56_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    Reserved57_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    SDIO_DriverIRQHandler              /* SD/MMC  */
+    def_irq_handler    Reserved59_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    Reserved60_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    Reserved61_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    USB1_PHY_DriverIRQHandler              /* USB1_PHY */
+    def_irq_handler    USB1_DriverIRQHandler              /* USB1 interrupt */
+    def_irq_handler    USB1_NEEDCLK_DriverIRQHandler              /* USB1 activity */
+    def_irq_handler    SEC_HYPERVISOR_CALL_DriverIRQHandler              /* SEC_HYPERVISOR_CALL interrupt */
+    def_irq_handler    SEC_GPIO_INT0_IRQ0_DriverIRQHandler              /* SEC_GPIO_INT0_IRQ0 interrupt */
+    def_irq_handler    SEC_GPIO_INT0_IRQ1_DriverIRQHandler              /* SEC_GPIO_INT0_IRQ1 interrupt */
+    def_irq_handler    PLU_DriverIRQHandler              /* PLU interrupt */
+    def_irq_handler    SEC_VIO_DriverIRQHandler              /* SEC_VIO interrupt */
+    def_irq_handler    HASHCRYPT_DriverIRQHandler              /* HASHCRYPT interrupt */
+    def_irq_handler    CASER_DriverIRQHandler              /* CASPER interrupt */
+    def_irq_handler    PUF_DriverIRQHandler              /* PUF interrupt */
+    def_irq_handler    PQ_DriverIRQHandler              /* PQ interrupt */
+    def_irq_handler    DMA1_DriverIRQHandler              /* DMA1 interrupt */
+    def_irq_handler    FLEXCOMM8_DriverIRQHandler              /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */
+
+    .end

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_i2c_LPC55S69_cm33_core0.cmake

@@ -0,0 +1,17 @@
+include_guard()
+message("driver_cmsis_flexcomm_i2c component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/fsl_i2c_cmsis.c
+)
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_flexcomm_i2c_dma_LPC55S69_cm33_core0)
+
+include(CMSIS_Driver_Include_I2C_LPC55S69_cm33_core0)
+

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_spi_LPC55S69_cm33_core0.cmake

@@ -0,0 +1,17 @@
+include_guard()
+message("driver_cmsis_flexcomm_spi component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/fsl_spi_cmsis.c
+)
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_flexcomm_spi_dma_LPC55S69_cm33_core0)
+
+include(CMSIS_Driver_Include_SPI_LPC55S69_cm33_core0)
+

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_usart_LPC55S69_cm33_core0.cmake

@@ -0,0 +1,17 @@
+include_guard()
+message("driver_cmsis_flexcomm_usart component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/fsl_usart_cmsis.c
+)
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_flexcomm_usart_dma_LPC55S69_cm33_core0)
+
+include(CMSIS_Driver_Include_USART_LPC55S69_cm33_core0)
+

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_i2c_cmsis.c

@@ -0,0 +1,3279 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
+ * Copyright 2016-2020,2022 NXP. Not a Contribution.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "fsl_i2c_cmsis.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_cmsis"
+#endif
+
+#if ((defined(RTE_I2C0) && RTE_I2C0) || (defined(RTE_I2C1) && RTE_I2C1) || (defined(RTE_I2C2) && RTE_I2C2) ||     \
+     (defined(RTE_I2C3) && RTE_I2C3) || (defined(RTE_I2C4) && RTE_I2C4) || (defined(RTE_I2C5) && RTE_I2C5) ||     \
+     (defined(RTE_I2C6) && RTE_I2C6) || (defined(RTE_I2C7) && RTE_I2C7) || (defined(RTE_I2C8) && RTE_I2C8) ||     \
+     (defined(RTE_I2C9) && RTE_I2C9) || (defined(RTE_I2C10) && RTE_I2C10) || (defined(RTE_I2C11) && RTE_I2C11) || \
+     (defined(RTE_I2C12) && RTE_I2C12) || (defined(RTE_I2C13) && RTE_I2C13))
+
+#define ARM_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (3))
+
+/*
+ * ARMCC does not support split the data section automatically, so the driver
+ * needs to split the data to separate sections explicitly, to reduce codesize.
+ */
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#define ARMCC_SECTION(section_name) __attribute__((section(section_name)))
+#endif
+
+typedef const struct _cmsis_i2c_resource
+{
+    I2C_Type *base;            /*!< I2C peripheral base address.      */
+    uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */
+
+} cmsis_i2c_resource_t;
+
+typedef union _cmsis_i2c_handle
+{
+    i2c_master_handle_t master_handle; /*!< master Interupt transfer handle. */
+    i2c_slave_handle_t slave_handle;   /*!< slave Interupt transfer handle. */
+} cmsis_i2c_handle_t;
+
+typedef struct _cmsis_i2c_interrupt_driver_state
+{
+    cmsis_i2c_resource_t *resource; /*!< Basic I2C resource. */
+    cmsis_i2c_handle_t *handle;
+    ARM_I2C_SignalEvent_t cb_event; /*!< Callback function.     */
+    uint8_t flags;                  /*!< Control and state flags. */
+} cmsis_i2c_interrupt_driver_state_t;
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+typedef const struct _cmsis_i2c_dma_resource
+{
+    DMA_Type *i2cDmaBase;   /*!< DMA peripheral base address for i2c.    */
+    uint32_t i2cDmaChannel; /*!< DMA channel for i2c.             */
+} cmsis_i2c_dma_resource_t;
+
+typedef struct _cmsis_i2c_dma_driver_state
+{
+    cmsis_i2c_resource_t *resource;             /*!< i2c basic resource.      */
+    cmsis_i2c_dma_resource_t *dmaResource;      /*!< i2c DMA resource.        */
+    i2c_master_dma_handle_t *master_dma_handle; /*!< i2c DMA transfer handle. */
+    dma_handle_t *dmaHandle;                    /*!< DMA i2c handle.          */
+    uint8_t flags;                              /*!< Control and state flags. */
+} cmsis_i2c_dma_driver_state_t;
+#endif
+
+static const ARM_DRIVER_VERSION s_i2cDriverVersion = {ARM_I2C_API_VERSION, ARM_I2C_DRV_VERSION};
+
+static const ARM_I2C_CAPABILITIES s_i2cDriverCapabilities = {
+    0, /*< supports 10-bit addressing*/
+};
+
+static ARM_DRIVER_VERSION I2Cx_GetVersion(void)
+{
+    return s_i2cDriverVersion;
+}
+
+static ARM_I2C_CAPABILITIES I2Cx_GetCapabilities(void)
+{
+    return s_i2cDriverCapabilities;
+}
+
+#endif
+
+#if ((defined(RTE_I2C0_DMA_EN) && RTE_I2C0_DMA_EN) || (defined(RTE_I2C1_DMA_EN) && RTE_I2C1_DMA_EN) ||     \
+     (defined(RTE_I2C2_DMA_EN) && RTE_I2C2_DMA_EN) || (defined(RTE_I2C3_DMA_EN) && RTE_I2C3_DMA_EN) ||     \
+     (defined(RTE_I2C4_DMA_EN) && RTE_I2C4_DMA_EN) || (defined(RTE_I2C5_DMA_EN) && RTE_I2C5_DMA_EN) ||     \
+     (defined(RTE_I2C6_DMA_EN) && RTE_I2C6_DMA_EN) || (defined(RTE_I2C7_DMA_EN) && RTE_I2C7_DMA_EN) ||     \
+     (defined(RTE_I2C8_DMA_EN) && RTE_I2C8_DMA_EN) || (defined(RTE_I2C9_DMA_EN) && RTE_I2C9_DMA_EN) ||     \
+     (defined(RTE_I2C10_DMA_EN) && RTE_I2C10_DMA_EN) || (defined(RTE_I2C11_DMA_EN) && RTE_I2C11_DMA_EN) || \
+     (defined(RTE_I2C12_DMA_EN) && RTE_I2C12_DMA_EN) || (defined(RTE_I2C13_DMA_EN) && RTE_I2C13_DMA_EN))
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+static void KSDK_I2C_MASTER_DmaCallback(I2C_Type *base,
+                                        i2c_master_dma_handle_t *handle,
+                                        status_t status,
+                                        void *userData)
+{
+    uint32_t event = 0U;
+
+    if (status == kStatus_Success) /* Occurs after Master Transmit/Receive operation has finished. */
+    {
+        event = ARM_I2C_EVENT_TRANSFER_DONE;
+    }
+    else if (status == kStatus_I2C_Nak) /* Slave nacks master before all data are transmitted */
+    {
+        event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE;
+    }
+    else if (status == kStatus_I2C_Addr_Nak) /* Failed during slave probing */
+    {
+        event = ARM_I2C_EVENT_ADDRESS_NACK;
+    }
+    else if (status == kStatus_I2C_ArbitrationLost) /* Arbitration lost */
+    {
+        event = ARM_I2C_EVENT_ARBITRATION_LOST;
+    }
+    else /* kStatus_I2C_UnexpectedState, kStatus_I2C_Busy and kStatus_I2C_StartStopError */
+    {
+        event = ARM_I2C_EVENT_BUS_ERROR;
+    }
+
+    if (userData != NULL)
+    {
+        ((ARM_I2C_SignalEvent_t)userData)(event);
+    }
+}
+
+static int32_t I2C_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_dma_driver_state_t *i2c)
+{
+    if (0U == (i2c->flags & (uint8_t)I2C_FLAG_INIT))
+    {
+        DMA_EnableChannel(i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel);
+        DMA_CreateHandle(i2c->dmaHandle, i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel);
+
+        I2C_MasterTransferCreateHandleDMA(i2c->resource->base, i2c->master_dma_handle, KSDK_I2C_MASTER_DmaCallback,
+                                          (void *)cb_event, i2c->dmaHandle);
+        i2c->flags = (uint8_t)I2C_FLAG_INIT;
+    }
+    return ARM_DRIVER_OK;
+}
+
+static int32_t I2C_Master_DmaUninitialize(cmsis_i2c_dma_driver_state_t *i2c)
+{
+    i2c->flags = (uint8_t)I2C_FLAG_UNINIT;
+    return ARM_DRIVER_OK;
+}
+
+static int32_t I2C_Master_DmaTransmit(
+    uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_dma_driver_state_t *i2c)
+{
+    int32_t status;
+    int32_t ret;
+    i2c_master_transfer_t masterXfer;
+
+    /* Check if the I2C bus is idle - if not return busy status. */
+    if (i2c->master_dma_handle->state != 0U)
+    {
+        return ARM_DRIVER_ERROR_BUSY;
+    }
+
+    masterXfer.slaveAddress   = (uint8_t)addr;                      /*7-bit slave address.*/
+    masterXfer.direction      = kI2C_Write;                         /*Transfer direction.*/
+    masterXfer.subaddress     = 0U;                                 /*Sub address*/
+    masterXfer.subaddressSize = 0U;                                 /*Size of command buffer.*/
+    masterXfer.data           = (void *)data;                       /*Transfer buffer.*/
+    masterXfer.dataSize       = num;                                /*Transfer size.*/
+    masterXfer.flags          = (uint32_t)kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/
+
+    if (xfer_pending)
+    {
+        masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag;
+    }
+
+    status = I2C_MasterTransferDMA(i2c->resource->base, i2c->master_dma_handle, &masterXfer);
+    switch (status)
+    {
+        case kStatus_Success:
+            ret = ARM_DRIVER_OK;
+            break;
+        case kStatus_I2C_Busy:
+            ret = ARM_DRIVER_ERROR_BUSY;
+            break;
+        default:
+            ret = ARM_DRIVER_ERROR;
+            break;
+    }
+
+    return ret;
+}
+
+static int32_t I2C_Master_DmaReceive(
+    uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_dma_driver_state_t *i2c)
+{
+    int32_t status;
+    int32_t ret;
+    i2c_master_transfer_t masterXfer;
+
+    /* Check if the I2C bus is idle - if not return busy status. */
+    if (i2c->master_dma_handle->state != 0U)
+    {
+        return ARM_DRIVER_ERROR_BUSY;
+    }
+
+    masterXfer.slaveAddress   = (uint8_t)addr;                      /*7-bit slave address.*/
+    masterXfer.direction      = kI2C_Read;                          /*Transfer direction.*/
+    masterXfer.subaddress     = 0U;                                 /*Sub address*/
+    masterXfer.subaddressSize = 0U;                                 /*Size of command buffer.*/
+    masterXfer.data           = (uint8_t *)data;                    /*Transfer buffer.*/
+    masterXfer.dataSize       = num;                                /*Transfer size.*/
+    masterXfer.flags          = (uint32_t)kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/
+
+    if (xfer_pending)
+    {
+        masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag;
+    }
+
+    status = I2C_MasterTransferDMA(i2c->resource->base, i2c->master_dma_handle, &masterXfer);
+    switch (status)
+    {
+        case kStatus_Success:
+            ret = ARM_DRIVER_OK;
+            break;
+        case kStatus_I2C_Busy:
+            ret = ARM_DRIVER_ERROR_BUSY;
+            break;
+        default:
+            ret = ARM_DRIVER_ERROR;
+            break;
+    }
+
+    return ret;
+}
+
+static int32_t I2C_Master_DmaGetDataCount(cmsis_i2c_dma_driver_state_t *i2c)
+{
+    size_t cnt; /*the number of currently transferred data bytes*/
+
+    (void)I2C_MasterTransferGetCountDMA(i2c->resource->base, i2c->master_dma_handle, &cnt);
+    return (int32_t)cnt;
+}
+
+static int32_t I2C_Master_DmaControl(uint32_t control, uint32_t arg, cmsis_i2c_dma_driver_state_t *i2c)
+{
+    uint32_t baudRate_Bps = 0;
+    int32_t result        = ARM_DRIVER_OK;
+    switch (control)
+    {
+        /* Not supported */
+        case ARM_I2C_OWN_ADDRESS:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+        /*Set Bus Speed; arg = bus speed*/
+        case ARM_I2C_BUS_SPEED:
+            switch (arg)
+            {
+                case ARM_I2C_BUS_SPEED_STANDARD:
+                    baudRate_Bps = 100000;
+                    break;
+                case ARM_I2C_BUS_SPEED_FAST:
+                    baudRate_Bps = 400000;
+                    break;
+                case ARM_I2C_BUS_SPEED_FAST_PLUS:
+                    baudRate_Bps = 1000000;
+                    break;
+                default:
+                    result = ARM_DRIVER_ERROR_UNSUPPORTED;
+                    break;
+            }
+            I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, i2c->resource->GetFreq());
+            break;
+        /* Not supported */
+        case ARM_I2C_BUS_CLEAR:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+        /*Aborts the data transfer  when Master for Transmit or Receive*/
+        case ARM_I2C_ABORT_TRANSFER:
+            /*disable dma*/
+            I2C_MasterTransferAbortDMA(i2c->resource->base, i2c->master_dma_handle);
+
+            i2c->master_dma_handle->transferCount     = 0;
+            i2c->master_dma_handle->transfer.data     = NULL;
+            i2c->master_dma_handle->transfer.dataSize = 0;
+            break;
+        default:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+    }
+    return result;
+}
+
+static int32_t I2C_Master_DmaPowerControl(ARM_POWER_STATE state, cmsis_i2c_dma_driver_state_t *i2c)
+{
+    int32_t result = ARM_DRIVER_OK;
+    switch (state)
+    {
+        /*terminates any pending data transfers, disable i2c moduole and i2c clock and related dma*/
+        case ARM_POWER_OFF:
+            if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U)
+            {
+                (void)I2C_Master_DmaControl(ARM_I2C_ABORT_TRANSFER, 0, i2c);
+                I2C_MasterDeinit(i2c->resource->base);
+                DMA_DisableChannel(i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel);
+                i2c->flags = (uint8_t)I2C_FLAG_INIT;
+            }
+            break;
+        /* Not supported */
+        case ARM_POWER_LOW:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+        /*enable i2c moduole and i2c clock*/
+        case ARM_POWER_FULL:
+            if (i2c->flags == (uint8_t)I2C_FLAG_UNINIT)
+            {
+                return ARM_DRIVER_ERROR;
+            }
+
+            if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U)
+            {
+                /* Driver already powered */
+                break;
+            }
+            (void)FLEXCOMM_Init(i2c->resource->base, FLEXCOMM_PERIPH_I2C);
+            I2C_MasterEnable(i2c->resource->base, true);
+            i2c->flags |= (uint8_t)I2C_FLAG_POWER;
+            break;
+        default:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+    }
+    return result;
+}
+
+static ARM_I2C_STATUS I2C_Master_DmaGetStatus(cmsis_i2c_dma_driver_state_t *i2c)
+{
+    ARM_I2C_STATUS stat      = {0};
+    uint32_t ksdk_i2c_status = I2C_GetStatusFlags(i2c->resource->base);
+
+    stat.busy      = (uint32_t)(0UL == (ksdk_i2c_status & (uint32_t)I2C_STAT_MSTPENDING_MASK)); /*Busy flag.*/
+    stat.direction = (uint32_t)i2c->master_dma_handle->transfer.direction; /*Direction: 0=Transmitter, 1=Receiver.*/
+    stat.mode      = 1UL;                                                  /*Mode: 0=Slave, 1=Master.*/
+    stat.arbitration_lost = (uint32_t)((ksdk_i2c_status & (uint32_t)I2C_STAT_MSTARBLOSS_MASK) != 0U);
+    /*Master lost arbitration (cleared on start of next Master operation)*/
+
+    return stat;
+}
+
+#endif
+
+#endif
+
+#if ((defined(RTE_I2C0) && RTE_I2C0 && !(defined(RTE_I2C0_DMA_EN) && RTE_I2C0_DMA_EN)) ||     \
+     (defined(RTE_I2C1) && RTE_I2C1 && !(defined(RTE_I2C1_DMA_EN) && RTE_I2C1_DMA_EN)) ||     \
+     (defined(RTE_I2C2) && RTE_I2C2 && !(defined(RTE_I2C2_DMA_EN) && RTE_I2C2_DMA_EN)) ||     \
+     (defined(RTE_I2C3) && RTE_I2C3 && !(defined(RTE_I2C3_DMA_EN) && RTE_I2C3_DMA_EN)) ||     \
+     (defined(RTE_I2C4) && RTE_I2C4 && !(defined(RTE_I2C4_DMA_EN) && RTE_I2C4_DMA_EN)) ||     \
+     (defined(RTE_I2C5) && RTE_I2C5 && !(defined(RTE_I2C5_DMA_EN) && RTE_I2C5_DMA_EN)) ||     \
+     (defined(RTE_I2C6) && RTE_I2C6 && !(defined(RTE_I2C6_DMA_EN) && RTE_I2C6_DMA_EN)) ||     \
+     (defined(RTE_I2C7) && RTE_I2C7 && !(defined(RTE_I2C7_DMA_EN) && RTE_I2C7_DMA_EN)) ||     \
+     (defined(RTE_I2C8) && RTE_I2C8 && !(defined(RTE_I2C8_DMA_EN) && RTE_I2C8_DMA_EN)) ||     \
+     (defined(RTE_I2C9) && RTE_I2C9 && !(defined(RTE_I2C9_DMA_EN) && RTE_I2C9_DMA_EN)) ||     \
+     (defined(RTE_I2C10) && RTE_I2C10 && !(defined(RTE_I2C10_DMA_EN) && RTE_I2C10_DMA_EN)) || \
+     (defined(RTE_I2C11) && RTE_I2C11 && !(defined(RTE_I2C11_DMA_EN) && RTE_I2C11_DMA_EN)) || \
+     (defined(RTE_I2C12) && RTE_I2C12 && !(defined(RTE_I2C12_DMA_EN) && RTE_I2C12_DMA_EN)) || \
+     (defined(RTE_I2C13) && RTE_I2C13 && !(defined(RTE_I2C13_DMA_EN) && RTE_I2C13_DMA_EN)))
+
+static void KSDK_I2C_SLAVE_InterruptCallback(I2C_Type *base, volatile i2c_slave_transfer_t *xfer, void *param)
+{
+    uint32_t event;
+
+    switch (xfer->event)
+    {
+        case kI2C_SlaveCompletionEvent: /* Occurs after Slave Transmit/Receive operation has finished. */
+            event = ARM_I2C_EVENT_TRANSFER_DONE;
+            break;
+        default:
+            event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE;
+            break;
+    }
+
+    if (param != NULL)
+    {
+        ((ARM_I2C_SignalEvent_t)param)(event);
+    }
+}
+
+static void KSDK_I2C_MASTER_InterruptCallback(I2C_Type *base,
+                                              i2c_master_handle_t *handle,
+                                              status_t status,
+                                              void *userData)
+{
+    uint32_t event;
+
+    switch (status)
+    {
+        case kStatus_Success: /* Occurs after Master Transmit/Receive operation has finished. */
+            event = ARM_I2C_EVENT_TRANSFER_DONE;
+            break;
+        case kStatus_I2C_ArbitrationLost: /*Occurs in master mode when arbitration is lost.*/
+            event = ARM_I2C_EVENT_ARBITRATION_LOST;
+            break;
+        case kStatus_I2C_Nak: /* Slave nacks master before all data are transmitted */
+            event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE;
+            break;
+        case kStatus_I2C_Addr_Nak: /* Failed during slave probing */
+            event = ARM_I2C_EVENT_ADDRESS_NACK;
+            break;
+        default:
+            event = ARM_I2C_EVENT_BUS_ERROR;
+            break;
+    }
+
+    /* User data is actually CMSIS driver callback. */
+    if (userData != NULL)
+    {
+        ((ARM_I2C_SignalEvent_t)userData)(event);
+    }
+}
+
+static int32_t I2C_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_interrupt_driver_state_t *i2c)
+{
+    if (0U == (i2c->flags & (uint8_t)I2C_FLAG_INIT))
+    {
+        i2c->cb_event = cb_event; /* cb_event is CMSIS driver callback. */
+        i2c->flags    = (uint8_t)I2C_FLAG_INIT;
+    }
+
+    return ARM_DRIVER_OK;
+}
+
+static int32_t I2C_InterruptUninitialize(cmsis_i2c_interrupt_driver_state_t *i2c)
+{
+    i2c->flags = (uint8_t)I2C_FLAG_UNINIT;
+    return ARM_DRIVER_OK;
+}
+
+static int32_t I2C_Master_InterruptTransmit(
+    uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c)
+{
+    int32_t status;
+    int32_t ret;
+    i2c_master_transfer_t masterXfer;
+
+    /* Check if the I2C bus is idle - if not return busy status. */
+    if (i2c->handle->master_handle.state != 0U)
+    {
+        return ARM_DRIVER_ERROR_BUSY;
+    }
+
+    I2C_MasterEnable(i2c->resource->base, true);
+
+    /*create master_handle*/
+    I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle),
+                                   KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event);
+
+    masterXfer.slaveAddress   = (uint8_t)addr;                      /*7-bit slave address.*/
+    masterXfer.direction      = kI2C_Write;                         /*Transfer direction.*/
+    masterXfer.subaddress     = 0U;                                 /*Sub address*/
+    masterXfer.subaddressSize = 0U;                                 /*Size of command buffer.*/
+    masterXfer.data           = (uint8_t *)data;                    /*Transfer buffer.*/
+    masterXfer.dataSize       = num;                                /*Transfer size.*/
+    masterXfer.flags          = (uint32_t)kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/
+
+    if (xfer_pending)
+    {
+        masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag;
+    }
+
+    status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer);
+    switch (status)
+    {
+        case kStatus_Success:
+            ret = ARM_DRIVER_OK;
+            break;
+        case kStatus_I2C_Busy:
+            ret = ARM_DRIVER_ERROR_BUSY;
+            break;
+        default:
+            ret = ARM_DRIVER_ERROR;
+            break;
+    }
+
+    return ret;
+}
+
+static int32_t I2C_Master_InterruptReceive(
+    uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c)
+{
+    int32_t status;
+    int32_t ret;
+    i2c_master_transfer_t masterXfer;
+
+    /* Check if the I2C bus is idle - if not return busy status. */
+    if (i2c->handle->master_handle.state != 0U)
+    {
+        return ARM_DRIVER_ERROR_BUSY;
+    }
+
+    I2C_MasterEnable(i2c->resource->base, true);
+
+    /*create master_handle*/
+    I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle),
+                                   KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event);
+
+    masterXfer.slaveAddress   = (uint8_t)addr;                      /*7-bit slave address.*/
+    masterXfer.direction      = kI2C_Read;                          /*Transfer direction.*/
+    masterXfer.subaddress     = 0U;                                 /*Sub address*/
+    masterXfer.subaddressSize = 0U;                                 /*Size of command buffer.*/
+    masterXfer.data           = data;                               /*Transfer buffer.*/
+    masterXfer.dataSize       = num;                                /*Transfer size.*/
+    masterXfer.flags          = (uint32_t)kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/
+
+    if (xfer_pending)
+    {
+        masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag;
+    }
+
+    status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer);
+    switch (status)
+    {
+        case kStatus_Success:
+            ret = ARM_DRIVER_OK;
+            break;
+        case kStatus_I2C_Busy:
+            ret = ARM_DRIVER_ERROR_BUSY;
+            break;
+        default:
+            ret = ARM_DRIVER_ERROR;
+            break;
+    }
+
+    return ret;
+}
+
+static int32_t I2C_Slave_InterruptTransmit(const uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c)
+{
+    int32_t status;
+    int32_t ret;
+
+    /* set Slave enable */
+    I2C_SlaveEnable(i2c->resource->base, true);
+
+    /*create slave_handle*/
+    I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback,
+                                  (void *)i2c->cb_event);
+
+    status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle),
+                                          (uint32_t)kI2C_SlaveCompletionEvent);
+
+    i2c->handle->slave_handle.transfer.txData =
+        (uint8_t *)data;                             /*Pointer to buffer with data to transmit to I2C Master*/
+    i2c->handle->slave_handle.transfer.txSize = num; /*Number of data bytes to transmit*/
+    i2c->handle->slave_handle.transfer.transferredCount =
+        0U; /*Number of bytes actually transferred since start or last repeated start. */
+
+    switch (status)
+    {
+        case kStatus_Success:
+            ret = ARM_DRIVER_OK;
+            break;
+        case kStatus_I2C_Busy:
+            ret = ARM_DRIVER_ERROR_BUSY;
+            break;
+        default:
+            ret = ARM_DRIVER_ERROR;
+            break;
+    }
+
+    return ret;
+}
+
+static int32_t I2C_Slave_InterruptReceive(uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c)
+{
+    int32_t status;
+    int32_t ret;
+
+    /* set Slave enable */
+    I2C_SlaveEnable(i2c->resource->base, true);
+
+    /*create slave_handle*/
+    I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback,
+                                  (void *)i2c->cb_event);
+
+    status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle),
+                                          (uint32_t)kI2C_SlaveCompletionEvent);
+
+    i2c->handle->slave_handle.transfer.rxData = data; /*Pointer to buffer with data to transmit to I2C Master*/
+    i2c->handle->slave_handle.transfer.rxSize = num;  /*Number of data bytes to transmit*/
+    i2c->handle->slave_handle.transfer.transferredCount =
+        0U; /*Number of bytes actually transferred since start or last repeated start. */
+
+    switch (status)
+    {
+        case kStatus_Success:
+            ret = ARM_DRIVER_OK;
+            break;
+        case kStatus_I2C_Busy:
+            ret = ARM_DRIVER_ERROR_BUSY;
+            break;
+        default:
+            ret = ARM_DRIVER_ERROR;
+            break;
+    }
+
+    return ret;
+}
+
+static int32_t I2C_InterruptGetDataCount(cmsis_i2c_interrupt_driver_state_t *i2c)
+{
+    uint32_t cnt = 0; /*the number of currently transferred data bytes*/
+
+    if ((i2c->resource->base->CFG & (uint8_t)I2C_CFG_MSTEN_MASK) != 0U)
+    {
+        cnt = i2c->handle->master_handle.transferCount;
+    }
+    else
+    {
+        cnt = i2c->handle->slave_handle.transfer.transferredCount;
+    }
+
+    return (int32_t)cnt;
+}
+
+static int32_t I2C_InterruptControl(uint32_t control, uint32_t arg, cmsis_i2c_interrupt_driver_state_t *i2c)
+{
+    uint32_t baudRate_Bps;
+    uint32_t clkDiv;
+    int32_t result = ARM_DRIVER_OK;
+    switch (control)
+    {
+        /*Set Own Slave Address; arg = slave address*/
+        case ARM_I2C_OWN_ADDRESS:
+            /* Use as slave, set CLKDIV for clock stretching, ensure data set up time for standard mode 250ns. */
+            /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */
+            clkDiv                      = i2c->resource->GetFreq() / 1000U;
+            clkDiv                      = (clkDiv * 250U) / 1000000U;
+            i2c->resource->base->CLKDIV = clkDiv & I2C_CLKDIV_DIVVAL_MASK;
+
+            /* Set slave address. */
+            I2C_SlaveSetAddress(i2c->resource->base, kI2C_SlaveAddressRegister0, (uint8_t)arg, false);
+            /* set Slave address 0 qual */
+            i2c->resource->base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(0) | I2C_SLVQUAL0_SLVQUAL0(0);
+            break;
+        /*Set Bus Speed; arg = bus speed*/
+        case ARM_I2C_BUS_SPEED:
+            switch (arg)
+            {
+                case ARM_I2C_BUS_SPEED_STANDARD:
+                    baudRate_Bps = 100000;
+                    break;
+                case ARM_I2C_BUS_SPEED_FAST:
+                    baudRate_Bps = 400000;
+                    break;
+                case ARM_I2C_BUS_SPEED_FAST_PLUS:
+                    baudRate_Bps = 1000000;
+                    break;
+                default:
+                    result = ARM_DRIVER_ERROR_UNSUPPORTED;
+                    break;
+            }
+            if (result == ARM_DRIVER_OK)
+            {
+                I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, i2c->resource->GetFreq());
+            }
+            break;
+        // Not supported
+        case ARM_I2C_BUS_CLEAR:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+        /*Aborts the data transfer between Master and Slave for Transmit or Receive*/
+        case ARM_I2C_ABORT_TRANSFER:
+            if ((i2c->resource->base->CFG & (uint8_t)I2C_CFG_MSTEN_MASK) != 0U)
+            {
+                /*disable master interrupt and send STOP signal*/
+                (void)I2C_MasterTransferAbort(i2c->resource->base, &(i2c->handle->master_handle));
+
+                i2c->handle->master_handle.transferCount     = 0;
+                i2c->handle->master_handle.transfer.data     = NULL;
+                i2c->handle->master_handle.transfer.dataSize = 0;
+            }
+            /*if slave receive*/
+            if (((i2c->resource->base->CFG & (uint32_t)I2C_CFG_SLVEN_MASK) != 0U) &&
+                ((i2c->handle->slave_handle.slaveFsm) == kI2C_SlaveFsmReceive))
+            {
+                /*disable slave interrupt*/
+                I2C_SlaveTransferAbort(i2c->resource->base, &(i2c->handle->slave_handle));
+
+                i2c->handle->slave_handle.transfer.transferredCount = 0;
+                i2c->handle->slave_handle.transfer.txData           = NULL;
+                i2c->handle->slave_handle.transfer.rxData           = NULL;
+            }
+            break;
+        default:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+    }
+    return result;
+}
+
+static int32_t I2C_InterruptPowerControl(ARM_POWER_STATE state, cmsis_i2c_interrupt_driver_state_t *i2c)
+{
+    int32_t result = ARM_DRIVER_OK;
+    switch (state)
+    {
+        /*terminates any pending data transfers, disable i2c moduole and i2c clock*/
+        case ARM_POWER_OFF:
+            if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U)
+            {
+                (void)I2C_InterruptControl(ARM_I2C_ABORT_TRANSFER, 0, i2c);
+                I2C_MasterDeinit(i2c->resource->base);
+                I2C_SlaveDeinit(i2c->resource->base);
+                i2c->flags = (uint8_t)I2C_FLAG_INIT;
+            }
+            break;
+        /* Not supported */
+        case ARM_POWER_LOW:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+        /*enable i2c moduole and i2c clock*/
+        case ARM_POWER_FULL:
+            if (i2c->flags == (uint8_t)I2C_FLAG_UNINIT)
+            {
+                return ARM_DRIVER_ERROR;
+            }
+
+            if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U)
+            {
+                /* Driver already powered */
+                break;
+            }
+            (void)FLEXCOMM_Init(i2c->resource->base, FLEXCOMM_PERIPH_I2C);
+            i2c->flags |= (uint8_t)I2C_FLAG_POWER;
+            break;
+        default:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+    }
+    return result;
+}
+
+static ARM_I2C_STATUS I2C_InterruptGetStatus(cmsis_i2c_interrupt_driver_state_t *i2c)
+{
+    ARM_I2C_STATUS stat      = {0};
+    uint32_t ksdk_i2c_status = I2C_GetStatusFlags(i2c->resource->base);
+
+    if ((i2c->resource->base->CFG & (uint32_t)I2C_CFG_MSTEN_MASK) != 0U)
+    {
+        stat.busy = (uint32_t)(0UL == (ksdk_i2c_status & (uint32_t)I2C_STAT_MSTPENDING_MASK)); /*Busy flag.*/
+        stat.direction =
+            (uint32_t)i2c->handle->master_handle.transfer.direction; /*Direction: 0=Transmitter, 1=Receiver.*/
+        stat.mode             = 1UL;                                 /*Mode: 0=Slave, 1=Master.*/
+        stat.arbitration_lost = (uint32_t)((ksdk_i2c_status & (uint32_t)I2C_STAT_MSTARBLOSS_MASK) != 0U);
+        /*Master lost arbitration (cleared on start of next Master operation)*/
+    }
+
+    if ((i2c->resource->base->CFG & (uint32_t)I2C_CFG_SLVEN_MASK) != 0U)
+    {
+        stat.busy = (uint32_t)(0UL == (ksdk_i2c_status & (uint32_t)I2C_STAT_SLVPENDING_MASK)); /*Busy flag.*/
+        if (i2c->handle->slave_handle.slaveFsm == kI2C_SlaveFsmReceive)
+        {
+            stat.direction = 1; /*Direction: 0=Transmitter, 1=Receiver.*/
+        }
+        else
+        {
+            stat.direction = 0; /*Direction: 0=Transmitter, 1=Receiver.*/
+        }
+        stat.mode = 0; /*Mode: 0=Slave, 1=Master.*/
+    }
+
+    return stat;
+}
+
+#endif
+
+#if defined(I2C0) && defined(RTE_I2C0) && RTE_I2C0
+/* User needs to provide the implementation for I2C0_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t I2C0_GetFreq(void);
+
+static cmsis_i2c_resource_t I2C0_Resource = {I2C0, I2C0_GetFreq};
+
+#if (defined(RTE_I2C0_DMA_EN) && RTE_I2C0_DMA_EN)
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_i2c_dma_resource_t I2C0_DmaResource = {RTE_I2C0_Master_DMA_BASE, RTE_I2C0_Master_DMA_CH};
+
+static i2c_master_dma_handle_t I2C0_DmaHandle;
+static dma_handle_t I2C0_DmaTxRxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c0_dma_driver_state")
+static cmsis_i2c_dma_driver_state_t I2C0_DmaDriverState = {
+#else
+static cmsis_i2c_dma_driver_state_t I2C0_DmaDriverState  = {
+#endif
+    &I2C0_Resource,
+    &I2C0_DmaResource,
+    &I2C0_DmaHandle,
+    &I2C0_DmaTxRxHandle,
+};
+
+static int32_t I2C0_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C0_PIN_INIT
+    RTE_I2C0_PIN_INIT();
+#endif
+    return I2C_Master_DmaInitialize(cb_event, &I2C0_DmaDriverState);
+}
+
+static int32_t I2C0_Master_DmaUninitialize(void)
+{
+#ifdef RTE_I2C0_PIN_DEINIT
+    RTE_I2C0_PIN_DEINIT();
+#endif
+    return I2C_Master_DmaUninitialize(&I2C0_DmaDriverState);
+}
+
+static int32_t I2C0_Master_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_Master_DmaPowerControl(state, &I2C0_DmaDriverState);
+}
+
+static int32_t I2C0_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C0_DmaDriverState);
+}
+
+static int32_t I2C0_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C0_DmaDriverState);
+}
+
+static int32_t I2C0_Master_DmaGetDataCount(void)
+{
+    return I2C_Master_DmaGetDataCount(&I2C0_DmaDriverState);
+}
+
+static int32_t I2C0_Master_DmaControl(uint32_t control, uint32_t arg)
+{
+    return I2C_Master_DmaControl(control, arg, &I2C0_DmaDriverState);
+}
+
+static ARM_I2C_STATUS I2C0_Master_DmaGetStatus(void)
+{
+    return I2C_Master_DmaGetStatus(&I2C0_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_i2c_handle_t I2C0_handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c0_interrupt_driver_state")
+static cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = {
+#else
+static cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState  = {
+#endif
+    &I2C0_Resource,
+    &I2C0_handle,
+
+};
+
+static int32_t I2C0_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C0_PIN_INIT
+    RTE_I2C0_PIN_INIT();
+#endif
+    return I2C_InterruptInitialize(cb_event, &I2C0_InterruptDriverState);
+}
+
+static int32_t I2C0_InterruptUninitialize(void)
+{
+#ifdef RTE_I2C0_PIN_DEINIT
+    RTE_I2C0_PIN_DEINIT();
+#endif
+    return I2C_InterruptUninitialize(&I2C0_InterruptDriverState);
+}
+
+static int32_t I2C0_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_InterruptPowerControl(state, &I2C0_InterruptDriverState);
+}
+
+static int32_t I2C0_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C0_InterruptDriverState);
+}
+
+static int32_t I2C0_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C0_InterruptDriverState);
+}
+
+static int32_t I2C0_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptTransmit(data, num, &I2C0_InterruptDriverState);
+}
+
+static int32_t I2C0_Slave_InterruptReceive(uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptReceive(data, num, &I2C0_InterruptDriverState);
+}
+
+static int32_t I2C0_InterruptGetDataCount(void)
+{
+    return I2C_InterruptGetDataCount(&I2C0_InterruptDriverState);
+}
+
+static int32_t I2C0_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return I2C_InterruptControl(control, arg, &I2C0_InterruptDriverState);
+}
+
+static ARM_I2C_STATUS I2C0_InterruptGetStatus(void)
+{
+    return I2C_InterruptGetStatus(&I2C0_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_I2C Driver_I2C0 = {I2Cx_GetVersion,
+                              I2Cx_GetCapabilities,
+#if defined(RTE_I2C0_DMA_EN) && RTE_I2C0_DMA_EN
+                              I2C0_Master_DmaInitialize,
+                              I2C0_Master_DmaUninitialize,
+                              I2C0_Master_DmaPowerControl,
+                              I2C0_Master_DmaTransmit,
+                              I2C0_Master_DmaReceive,
+                              NULL,
+                              NULL,
+                              I2C0_Master_DmaGetDataCount,
+                              I2C0_Master_DmaControl,
+                              I2C0_Master_DmaGetStatus
+#else
+                              I2C0_InterruptInitialize,
+                              I2C0_InterruptUninitialize,
+                              I2C0_InterruptPowerControl,
+                              I2C0_Master_InterruptTransmit,
+                              I2C0_Master_InterruptReceive,
+                              I2C0_Slave_InterruptTransmit,
+                              I2C0_Slave_InterruptReceive,
+                              I2C0_InterruptGetDataCount,
+                              I2C0_InterruptControl,
+                              I2C0_InterruptGetStatus
+#endif
+};
+
+#endif
+
+#if defined(I2C1) && defined(RTE_I2C1) && RTE_I2C1
+
+/* User needs to provide the implementation for I2C1_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t I2C1_GetFreq(void);
+
+static cmsis_i2c_resource_t I2C1_Resource = {I2C1, I2C1_GetFreq};
+
+#if (defined(RTE_I2C1_DMA_EN) && RTE_I2C1_DMA_EN)
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_i2c_dma_resource_t I2C1_DmaResource = {RTE_I2C1_Master_DMA_BASE, RTE_I2C1_Master_DMA_CH};
+
+static i2c_master_dma_handle_t I2C1_DmaHandle;
+static dma_handle_t I2C1_DmaTxRxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c1_dma_driver_state")
+static cmsis_i2c_dma_driver_state_t I2C1_DmaDriverState = {
+#else
+static cmsis_i2c_dma_driver_state_t I2C1_DmaDriverState  = {
+#endif
+    &I2C1_Resource,
+    &I2C1_DmaResource,
+    &I2C1_DmaHandle,
+    &I2C1_DmaTxRxHandle,
+};
+
+static int32_t I2C1_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C1_PIN_INIT
+    RTE_I2C1_PIN_INIT();
+#endif
+    return I2C_Master_DmaInitialize(cb_event, &I2C1_DmaDriverState);
+}
+
+static int32_t I2C1_Master_DmaUninitialize(void)
+{
+#ifdef RTE_I2C1_PIN_DEINIT
+    RTE_I2C1_PIN_DEINIT();
+#endif
+    return I2C_Master_DmaUninitialize(&I2C1_DmaDriverState);
+}
+
+static int32_t I2C1_Master_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_Master_DmaPowerControl(state, &I2C1_DmaDriverState);
+}
+
+static int32_t I2C1_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C1_DmaDriverState);
+}
+
+static int32_t I2C1_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C1_DmaDriverState);
+}
+
+static int32_t I2C1_Master_DmaGetDataCount(void)
+{
+    return I2C_Master_DmaGetDataCount(&I2C1_DmaDriverState);
+}
+
+static int32_t I2C1_Master_DmaControl(uint32_t control, uint32_t arg)
+{
+    return I2C_Master_DmaControl(control, arg, &I2C1_DmaDriverState);
+}
+
+static ARM_I2C_STATUS I2C1_Master_DmaGetStatus(void)
+{
+    return I2C_Master_DmaGetStatus(&I2C1_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_i2c_handle_t I2C1_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c1_interrupt_driver_state")
+static cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = {
+#else
+static cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState  = {
+#endif
+    &I2C1_Resource,
+    &I2C1_Handle,
+};
+
+static int32_t I2C1_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C1_PIN_INIT
+    RTE_I2C1_PIN_INIT();
+#endif
+    return I2C_InterruptInitialize(cb_event, &I2C1_InterruptDriverState);
+}
+
+static int32_t I2C1_InterruptUninitialize(void)
+{
+#ifdef RTE_I2C1_PIN_DEINIT
+    RTE_I2C1_PIN_DEINIT();
+#endif
+    return I2C_InterruptUninitialize(&I2C1_InterruptDriverState);
+}
+
+static int32_t I2C1_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_InterruptPowerControl(state, &I2C1_InterruptDriverState);
+}
+
+static int32_t I2C1_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C1_InterruptDriverState);
+}
+
+static int32_t I2C1_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C1_InterruptDriverState);
+}
+
+static int32_t I2C1_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptTransmit(data, num, &I2C1_InterruptDriverState);
+}
+
+static int32_t I2C1_Slave_InterruptReceive(uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptReceive(data, num, &I2C1_InterruptDriverState);
+}
+
+static int32_t I2C1_InterruptGetDataCount(void)
+{
+    return I2C_InterruptGetDataCount(&I2C1_InterruptDriverState);
+}
+
+static int32_t I2C1_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return I2C_InterruptControl(control, arg, &I2C1_InterruptDriverState);
+}
+
+static ARM_I2C_STATUS I2C1_InterruptGetStatus(void)
+{
+    return I2C_InterruptGetStatus(&I2C1_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_I2C Driver_I2C1 = {I2Cx_GetVersion,
+                              I2Cx_GetCapabilities,
+#if defined(RTE_I2C1_DMA_EN) && RTE_I2C1_DMA_EN
+                              I2C1_Master_DmaInitialize,
+                              I2C1_Master_DmaUninitialize,
+                              I2C1_Master_DmaPowerControl,
+                              I2C1_Master_DmaTransmit,
+                              I2C1_Master_DmaReceive,
+                              NULL,
+                              NULL,
+                              I2C1_Master_DmaGetDataCount,
+                              I2C1_Master_DmaControl,
+                              I2C1_Master_DmaGetStatus
+#else
+                              I2C1_InterruptInitialize,
+                              I2C1_InterruptUninitialize,
+                              I2C1_InterruptPowerControl,
+                              I2C1_Master_InterruptTransmit,
+                              I2C1_Master_InterruptReceive,
+                              I2C1_Slave_InterruptTransmit,
+                              I2C1_Slave_InterruptReceive,
+                              I2C1_InterruptGetDataCount,
+                              I2C1_InterruptControl,
+                              I2C1_InterruptGetStatus
+#endif
+};
+
+#endif
+
+#if defined(I2C2) && defined(RTE_I2C2) && RTE_I2C2
+
+/* User needs to provide the implementation for I2C2_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t I2C2_GetFreq(void);
+
+static cmsis_i2c_resource_t I2C2_Resource = {I2C2, I2C2_GetFreq};
+
+#if (defined(RTE_I2C2_DMA_EN) && RTE_I2C2_DMA_EN)
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_i2c_dma_resource_t I2C2_DmaResource = {RTE_I2C2_Master_DMA_BASE, RTE_I2C2_Master_DMA_CH};
+
+static i2c_master_dma_handle_t I2C2_DmaHandle;
+static dma_handle_t I2C2_DmaTxRxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c2_dma_driver_state")
+static cmsis_i2c_dma_driver_state_t I2C2_DmaDriverState = {
+#else
+static cmsis_i2c_dma_driver_state_t I2C2_DmaDriverState  = {
+#endif
+    &I2C2_Resource,
+    &I2C2_DmaResource,
+    &I2C2_DmaHandle,
+    &I2C2_DmaTxRxHandle,
+};
+
+static int32_t I2C2_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C2_PIN_INIT
+    RTE_I2C2_PIN_INIT();
+#endif
+    return I2C_Master_DmaInitialize(cb_event, &I2C2_DmaDriverState);
+}
+
+static int32_t I2C2_Master_DmaUninitialize(void)
+{
+#ifdef RTE_I2C2_PIN_DEINIT
+    RTE_I2C2_PIN_DEINIT();
+#endif
+    return I2C_Master_DmaUninitialize(&I2C2_DmaDriverState);
+}
+
+static int32_t I2C2_Master_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_Master_DmaPowerControl(state, &I2C2_DmaDriverState);
+}
+
+static int32_t I2C2_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C2_DmaDriverState);
+}
+
+static int32_t I2C2_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C2_DmaDriverState);
+}
+
+static int32_t I2C2_Master_DmaGetDataCount(void)
+{
+    return I2C_Master_DmaGetDataCount(&I2C2_DmaDriverState);
+}
+
+static int32_t I2C2_Master_DmaControl(uint32_t control, uint32_t arg)
+{
+    return I2C_Master_DmaControl(control, arg, &I2C2_DmaDriverState);
+}
+
+static ARM_I2C_STATUS I2C2_Master_DmaGetStatus(void)
+{
+    return I2C_Master_DmaGetStatus(&I2C2_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_i2c_handle_t I2C2_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c2_interrupt_driver_state")
+static cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = {
+#else
+static cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState  = {
+#endif
+    &I2C2_Resource,
+    &I2C2_Handle,
+
+};
+
+static int32_t I2C2_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C2_PIN_INIT
+    RTE_I2C2_PIN_INIT();
+#endif
+    return I2C_InterruptInitialize(cb_event, &I2C2_InterruptDriverState);
+}
+
+static int32_t I2C2_InterruptUninitialize(void)
+{
+#ifdef RTE_I2C2_PIN_DEINIT
+    RTE_I2C2_PIN_DEINIT();
+#endif
+    return I2C_InterruptUninitialize(&I2C2_InterruptDriverState);
+}
+
+static int32_t I2C2_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_InterruptPowerControl(state, &I2C2_InterruptDriverState);
+}
+
+static int32_t I2C2_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C2_InterruptDriverState);
+}
+
+static int32_t I2C2_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C2_InterruptDriverState);
+}
+
+static int32_t I2C2_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptTransmit(data, num, &I2C2_InterruptDriverState);
+}
+
+static int32_t I2C2_Slave_InterruptReceive(uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptReceive(data, num, &I2C2_InterruptDriverState);
+}
+
+static int32_t I2C2_InterruptGetDataCount(void)
+{
+    return I2C_InterruptGetDataCount(&I2C2_InterruptDriverState);
+}
+
+static int32_t I2C2_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return I2C_InterruptControl(control, arg, &I2C2_InterruptDriverState);
+}
+
+static ARM_I2C_STATUS I2C2_InterruptGetStatus(void)
+{
+    return I2C_InterruptGetStatus(&I2C2_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_I2C Driver_I2C2 = {I2Cx_GetVersion,
+                              I2Cx_GetCapabilities,
+#if defined(RTE_I2C2_DMA_EN) && (RTE_I2C2_DMA_EN)
+                              I2C2_Master_DmaInitialize,
+                              I2C2_Master_DmaUninitialize,
+                              I2C2_Master_DmaPowerControl,
+                              I2C2_Master_DmaTransmit,
+                              I2C2_Master_DmaReceive,
+                              NULL,
+                              NULL,
+                              I2C2_Master_DmaGetDataCount,
+                              I2C2_Master_DmaControl,
+                              I2C2_Master_DmaGetStatus
+#else
+                              I2C2_InterruptInitialize,
+                              I2C2_InterruptUninitialize,
+                              I2C2_InterruptPowerControl,
+                              I2C2_Master_InterruptTransmit,
+                              I2C2_Master_InterruptReceive,
+                              I2C2_Slave_InterruptTransmit,
+                              I2C2_Slave_InterruptReceive,
+                              I2C2_InterruptGetDataCount,
+                              I2C2_InterruptControl,
+                              I2C2_InterruptGetStatus
+#endif
+};
+
+#endif
+
+#if defined(I2C3) && defined(RTE_I2C3) && RTE_I2C3
+
+/* User needs to provide the implementation for I2C3_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t I2C3_GetFreq(void);
+
+static cmsis_i2c_resource_t I2C3_Resource = {I2C3, I2C3_GetFreq};
+
+#if (defined(RTE_I2C3_DMA_EN) && RTE_I2C3_DMA_EN)
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_i2c_dma_resource_t I2C3_DmaResource = {RTE_I2C3_Master_DMA_BASE, RTE_I2C3_Master_DMA_CH};
+
+static i2c_master_dma_handle_t I2C3_DmaHandle;
+static dma_handle_t I2C3_DmaTxRxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c3_dma_driver_state")
+static cmsis_i2c_dma_driver_state_t I2C3_DmaDriverState = {
+#else
+static cmsis_i2c_dma_driver_state_t I2C3_DmaDriverState  = {
+#endif
+    &I2C3_Resource,
+    &I2C3_DmaResource,
+    &I2C3_DmaHandle,
+    &I2C3_DmaTxRxHandle,
+};
+
+static int32_t I2C3_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C3_PIN_INIT
+    RTE_I2C3_PIN_INIT();
+#endif
+    return I2C_Master_DmaInitialize(cb_event, &I2C3_DmaDriverState);
+}
+
+static int32_t I2C3_Master_DmaUninitialize(void)
+{
+#ifdef RTE_I2C3_PIN_DEINIT
+    RTE_I2C3_PIN_DEINIT();
+#endif
+    return I2C_Master_DmaUninitialize(&I2C3_DmaDriverState);
+}
+
+static int32_t I2C3_Master_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_Master_DmaPowerControl(state, &I2C3_DmaDriverState);
+}
+
+static int32_t I2C3_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C3_DmaDriverState);
+}
+
+static int32_t I2C3_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C3_DmaDriverState);
+}
+
+static int32_t I2C3_Master_DmaGetDataCount(void)
+{
+    return I2C_Master_DmaGetDataCount(&I2C3_DmaDriverState);
+}
+
+static int32_t I2C3_Master_DmaControl(uint32_t control, uint32_t arg)
+{
+    return I2C_Master_DmaControl(control, arg, &I2C3_DmaDriverState);
+}
+
+static ARM_I2C_STATUS I2C3_Master_DmaGetStatus(void)
+{
+    return I2C_Master_DmaGetStatus(&I2C3_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_i2c_handle_t I2C3_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c3_interrupt_driver_state")
+static cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = {
+#else
+static cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState  = {
+#endif
+    &I2C3_Resource,
+    &I2C3_Handle,
+};
+
+static int32_t I2C3_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C3_PIN_INIT
+    RTE_I2C3_PIN_INIT();
+#endif
+    return I2C_InterruptInitialize(cb_event, &I2C3_InterruptDriverState);
+}
+
+static int32_t I2C3_InterruptUninitialize(void)
+{
+#ifdef RTE_I2C3_PIN_DEINIT
+    RTE_I2C3_PIN_DEINIT();
+#endif
+    return I2C_InterruptUninitialize(&I2C3_InterruptDriverState);
+}
+
+static int32_t I2C3_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_InterruptPowerControl(state, &I2C3_InterruptDriverState);
+}
+
+static int32_t I2C3_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C3_InterruptDriverState);
+}
+
+static int32_t I2C3_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C3_InterruptDriverState);
+}
+
+static int32_t I2C3_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptTransmit(data, num, &I2C3_InterruptDriverState);
+}
+
+static int32_t I2C3_Slave_InterruptReceive(uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptReceive(data, num, &I2C3_InterruptDriverState);
+}
+
+static int32_t I2C3_InterruptGetDataCount(void)
+{
+    return I2C_InterruptGetDataCount(&I2C3_InterruptDriverState);
+}
+
+static int32_t I2C3_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return I2C_InterruptControl(control, arg, &I2C3_InterruptDriverState);
+}
+
+static ARM_I2C_STATUS I2C3_InterruptGetStatus(void)
+{
+    return I2C_InterruptGetStatus(&I2C3_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_I2C Driver_I2C3 = {I2Cx_GetVersion,
+                              I2Cx_GetCapabilities,
+#if defined(RTE_I2C3_DMA_EN) && RTE_I2C3_DMA_EN
+                              I2C3_Master_DmaInitialize,
+                              I2C3_Master_DmaUninitialize,
+                              I2C3_Master_DmaPowerControl,
+                              I2C3_Master_DmaTransmit,
+                              I2C3_Master_DmaReceive,
+                              NULL,
+                              NULL,
+                              I2C3_Master_DmaGetDataCount,
+                              I2C3_Master_DmaControl,
+                              I2C3_Master_DmaGetStatus
+#else
+                              I2C3_InterruptInitialize,
+                              I2C3_InterruptUninitialize,
+                              I2C3_InterruptPowerControl,
+                              I2C3_Master_InterruptTransmit,
+                              I2C3_Master_InterruptReceive,
+                              I2C3_Slave_InterruptTransmit,
+                              I2C3_Slave_InterruptReceive,
+                              I2C3_InterruptGetDataCount,
+                              I2C3_InterruptControl,
+                              I2C3_InterruptGetStatus
+#endif
+};
+
+#endif
+
+#if defined(I2C4) && defined(RTE_I2C4) && RTE_I2C4
+/* User needs to provide the implementation for I2C4_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t I2C4_GetFreq(void);
+
+static cmsis_i2c_resource_t I2C4_Resource = {I2C4, I2C4_GetFreq};
+
+#if (defined(RTE_I2C4_DMA_EN) && RTE_I2C4_DMA_EN)
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_i2c_dma_resource_t I2C4_DmaResource = {RTE_I2C4_Master_DMA_BASE, RTE_I2C4_Master_DMA_CH};
+
+static i2c_master_dma_handle_t I2C4_DmaHandle;
+static dma_handle_t I2C4_DmaTxRxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c4_dma_driver_state")
+static cmsis_i2c_dma_driver_state_t I2C4_DmaDriverState = {
+#else
+static cmsis_i2c_dma_driver_state_t I2C4_DmaDriverState  = {
+#endif
+    &I2C4_Resource,
+    &I2C4_DmaResource,
+    &I2C4_DmaHandle,
+    &I2C4_DmaTxRxHandle,
+};
+
+static int32_t I2C4_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C4_PIN_INIT
+    RTE_I2C4_PIN_INIT();
+#endif
+    return I2C_Master_DmaInitialize(cb_event, &I2C4_DmaDriverState);
+}
+
+static int32_t I2C4_Master_DmaUninitialize(void)
+{
+#ifdef RTE_I2C4_PIN_DEINIT
+    RTE_I2C4_PIN_DEINIT();
+#endif
+    return I2C_Master_DmaUninitialize(&I2C4_DmaDriverState);
+}
+
+static int32_t I2C4_Master_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_Master_DmaPowerControl(state, &I2C4_DmaDriverState);
+}
+
+static int32_t I2C4_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C4_DmaDriverState);
+}
+
+static int32_t I2C4_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C4_DmaDriverState);
+}
+
+static int32_t I2C4_Master_DmaGetDataCount(void)
+{
+    return I2C_Master_DmaGetDataCount(&I2C4_DmaDriverState);
+}
+
+static int32_t I2C4_Master_DmaControl(uint32_t control, uint32_t arg)
+{
+    return I2C_Master_DmaControl(control, arg, &I2C4_DmaDriverState);
+}
+
+static ARM_I2C_STATUS I2C4_Master_DmaGetStatus(void)
+{
+    return I2C_Master_DmaGetStatus(&I2C4_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_i2c_handle_t I2C4_handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c4_interrupt_driver_state")
+static cmsis_i2c_interrupt_driver_state_t I2C4_InterruptDriverState = {
+#else
+static cmsis_i2c_interrupt_driver_state_t I2C4_InterruptDriverState  = {
+#endif
+    &I2C4_Resource,
+    &I2C4_handle,
+
+};
+
+static int32_t I2C4_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C4_PIN_INIT
+    RTE_I2C4_PIN_INIT();
+#endif
+    return I2C_InterruptInitialize(cb_event, &I2C4_InterruptDriverState);
+}
+
+static int32_t I2C4_InterruptUninitialize(void)
+{
+#ifdef RTE_I2C4_PIN_DEINIT
+    RTE_I2C4_PIN_DEINIT();
+#endif
+    return I2C_InterruptUninitialize(&I2C4_InterruptDriverState);
+}
+
+static int32_t I2C4_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_InterruptPowerControl(state, &I2C4_InterruptDriverState);
+}
+
+static int32_t I2C4_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C4_InterruptDriverState);
+}
+
+static int32_t I2C4_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C4_InterruptDriverState);
+}
+
+static int32_t I2C4_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptTransmit(data, num, &I2C4_InterruptDriverState);
+}
+
+static int32_t I2C4_Slave_InterruptReceive(uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptReceive(data, num, &I2C4_InterruptDriverState);
+}
+
+static int32_t I2C4_InterruptGetDataCount(void)
+{
+    return I2C_InterruptGetDataCount(&I2C4_InterruptDriverState);
+}
+
+static int32_t I2C4_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return I2C_InterruptControl(control, arg, &I2C4_InterruptDriverState);
+}
+
+static ARM_I2C_STATUS I2C4_InterruptGetStatus(void)
+{
+    return I2C_InterruptGetStatus(&I2C4_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_I2C Driver_I2C4 = {I2Cx_GetVersion,
+                              I2Cx_GetCapabilities,
+#if defined(RTE_I2C4_DMA_EN) && RTE_I2C4_DMA_EN
+                              I2C4_Master_DmaInitialize,
+                              I2C4_Master_DmaUninitialize,
+                              I2C4_Master_DmaPowerControl,
+                              I2C4_Master_DmaTransmit,
+                              I2C4_Master_DmaReceive,
+                              NULL,
+                              NULL,
+                              I2C4_Master_DmaGetDataCount,
+                              I2C4_Master_DmaControl,
+                              I2C4_Master_DmaGetStatus
+#else
+                              I2C4_InterruptInitialize,
+                              I2C4_InterruptUninitialize,
+                              I2C4_InterruptPowerControl,
+                              I2C4_Master_InterruptTransmit,
+                              I2C4_Master_InterruptReceive,
+                              I2C4_Slave_InterruptTransmit,
+                              I2C4_Slave_InterruptReceive,
+                              I2C4_InterruptGetDataCount,
+                              I2C4_InterruptControl,
+                              I2C4_InterruptGetStatus
+#endif
+};
+
+#endif
+
+#if defined(I2C5) && defined(RTE_I2C5) && RTE_I2C5
+/* User needs to provide the implementation for I2C5_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t I2C5_GetFreq(void);
+
+static cmsis_i2c_resource_t I2C5_Resource = {I2C5, I2C5_GetFreq};
+
+#if (defined(RTE_I2C5_DMA_EN) && RTE_I2C5_DMA_EN)
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_i2c_dma_resource_t I2C5_DmaResource = {RTE_I2C5_Master_DMA_BASE, RTE_I2C5_Master_DMA_CH};
+
+static i2c_master_dma_handle_t I2C5_DmaHandle;
+static dma_handle_t I2C5_DmaTxRxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c5_dma_driver_state")
+static cmsis_i2c_dma_driver_state_t I2C5_DmaDriverState = {
+#else
+static cmsis_i2c_dma_driver_state_t I2C5_DmaDriverState  = {
+#endif
+    &I2C5_Resource,
+    &I2C5_DmaResource,
+    &I2C5_DmaHandle,
+    &I2C5_DmaTxRxHandle,
+};
+
+static int32_t I2C5_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C5_PIN_INIT
+    RTE_I2C5_PIN_INIT();
+#endif
+    return I2C_Master_DmaInitialize(cb_event, &I2C5_DmaDriverState);
+}
+
+static int32_t I2C5_Master_DmaUninitialize(void)
+{
+#ifdef RTE_I2C5_PIN_DEINIT
+    RTE_I2C5_PIN_DEINIT();
+#endif
+    return I2C_Master_DmaUninitialize(&I2C5_DmaDriverState);
+}
+
+static int32_t I2C5_Master_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_Master_DmaPowerControl(state, &I2C5_DmaDriverState);
+}
+
+static int32_t I2C5_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C5_DmaDriverState);
+}
+
+static int32_t I2C5_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C5_DmaDriverState);
+}
+
+static int32_t I2C5_Master_DmaGetDataCount(void)
+{
+    return I2C_Master_DmaGetDataCount(&I2C5_DmaDriverState);
+}
+
+static int32_t I2C5_Master_DmaControl(uint32_t control, uint32_t arg)
+{
+    return I2C_Master_DmaControl(control, arg, &I2C5_DmaDriverState);
+}
+
+static ARM_I2C_STATUS I2C5_Master_DmaGetStatus(void)
+{
+    return I2C_Master_DmaGetStatus(&I2C5_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_i2c_handle_t I2C5_handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c5_interrupt_driver_state")
+static cmsis_i2c_interrupt_driver_state_t I2C5_InterruptDriverState = {
+#else
+static cmsis_i2c_interrupt_driver_state_t I2C5_InterruptDriverState  = {
+#endif
+    &I2C5_Resource,
+    &I2C5_handle,
+
+};
+
+static int32_t I2C5_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C5_PIN_INIT
+    RTE_I2C5_PIN_INIT();
+#endif
+    return I2C_InterruptInitialize(cb_event, &I2C5_InterruptDriverState);
+}
+
+static int32_t I2C5_InterruptUninitialize(void)
+{
+#ifdef RTE_I2C5_PIN_DEINIT
+    RTE_I2C5_PIN_DEINIT();
+#endif
+    return I2C_InterruptUninitialize(&I2C5_InterruptDriverState);
+}
+
+static int32_t I2C5_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_InterruptPowerControl(state, &I2C5_InterruptDriverState);
+}
+
+static int32_t I2C5_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C5_InterruptDriverState);
+}
+
+static int32_t I2C5_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C5_InterruptDriverState);
+}
+
+static int32_t I2C5_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptTransmit(data, num, &I2C5_InterruptDriverState);
+}
+
+static int32_t I2C5_Slave_InterruptReceive(uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptReceive(data, num, &I2C5_InterruptDriverState);
+}
+
+static int32_t I2C5_InterruptGetDataCount(void)
+{
+    return I2C_InterruptGetDataCount(&I2C5_InterruptDriverState);
+}
+
+static int32_t I2C5_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return I2C_InterruptControl(control, arg, &I2C5_InterruptDriverState);
+}
+
+static ARM_I2C_STATUS I2C5_InterruptGetStatus(void)
+{
+    return I2C_InterruptGetStatus(&I2C5_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_I2C Driver_I2C5 = {I2Cx_GetVersion,
+                              I2Cx_GetCapabilities,
+#if defined(RTE_I2C5_DMA_EN) && RTE_I2C5_DMA_EN
+                              I2C5_Master_DmaInitialize,
+                              I2C5_Master_DmaUninitialize,
+                              I2C5_Master_DmaPowerControl,
+                              I2C5_Master_DmaTransmit,
+                              I2C5_Master_DmaReceive,
+                              NULL,
+                              NULL,
+                              I2C5_Master_DmaGetDataCount,
+                              I2C5_Master_DmaControl,
+                              I2C5_Master_DmaGetStatus
+#else
+                              I2C5_InterruptInitialize,
+                              I2C5_InterruptUninitialize,
+                              I2C5_InterruptPowerControl,
+                              I2C5_Master_InterruptTransmit,
+                              I2C5_Master_InterruptReceive,
+                              I2C5_Slave_InterruptTransmit,
+                              I2C5_Slave_InterruptReceive,
+                              I2C5_InterruptGetDataCount,
+                              I2C5_InterruptControl,
+                              I2C5_InterruptGetStatus
+#endif
+};
+
+#endif
+
+#if defined(I2C6) && defined(RTE_I2C6) && RTE_I2C6
+/* User needs to provide the implementation for I2C6_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t I2C6_GetFreq(void);
+
+static cmsis_i2c_resource_t I2C6_Resource = {I2C6, I2C6_GetFreq};
+
+#if (defined(RTE_I2C6_DMA_EN) && RTE_I2C6_DMA_EN)
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_i2c_dma_resource_t I2C6_DmaResource = {RTE_I2C6_Master_DMA_BASE, RTE_I2C6_Master_DMA_CH};
+
+static i2c_master_dma_handle_t I2C6_DmaHandle;
+static dma_handle_t I2C6_DmaTxRxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c6_dma_driver_state")
+static cmsis_i2c_dma_driver_state_t I2C6_DmaDriverState = {
+#else
+static cmsis_i2c_dma_driver_state_t I2C6_DmaDriverState  = {
+#endif
+    &I2C6_Resource,
+    &I2C6_DmaResource,
+    &I2C6_DmaHandle,
+    &I2C6_DmaTxRxHandle,
+};
+
+static int32_t I2C6_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C6_PIN_INIT
+    RTE_I2C6_PIN_INIT();
+#endif
+    return I2C_Master_DmaInitialize(cb_event, &I2C6_DmaDriverState);
+}
+
+static int32_t I2C6_Master_DmaUninitialize(void)
+{
+#ifdef RTE_I2C6_PIN_DEINIT
+    RTE_I2C6_PIN_DEINIT();
+#endif
+    return I2C_Master_DmaUninitialize(&I2C6_DmaDriverState);
+}
+
+static int32_t I2C6_Master_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_Master_DmaPowerControl(state, &I2C6_DmaDriverState);
+}
+
+static int32_t I2C6_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C6_DmaDriverState);
+}
+
+static int32_t I2C6_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C6_DmaDriverState);
+}
+
+static int32_t I2C6_Master_DmaGetDataCount(void)
+{
+    return I2C_Master_DmaGetDataCount(&I2C6_DmaDriverState);
+}
+
+static int32_t I2C6_Master_DmaControl(uint32_t control, uint32_t arg)
+{
+    return I2C_Master_DmaControl(control, arg, &I2C6_DmaDriverState);
+}
+
+static ARM_I2C_STATUS I2C6_Master_DmaGetStatus(void)
+{
+    return I2C_Master_DmaGetStatus(&I2C6_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_i2c_handle_t I2C6_handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c6_interrupt_driver_state")
+static cmsis_i2c_interrupt_driver_state_t I2C6_InterruptDriverState = {
+#else
+static cmsis_i2c_interrupt_driver_state_t I2C6_InterruptDriverState  = {
+#endif
+    &I2C6_Resource,
+    &I2C6_handle,
+
+};
+
+static int32_t I2C6_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C6_PIN_INIT
+    RTE_I2C6_PIN_INIT();
+#endif
+    return I2C_InterruptInitialize(cb_event, &I2C6_InterruptDriverState);
+}
+
+static int32_t I2C6_InterruptUninitialize(void)
+{
+#ifdef RTE_I2C6_PIN_DEINIT
+    RTE_I2C6_PIN_DEINIT();
+#endif
+    return I2C_InterruptUninitialize(&I2C6_InterruptDriverState);
+}
+
+static int32_t I2C6_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_InterruptPowerControl(state, &I2C6_InterruptDriverState);
+}
+
+static int32_t I2C6_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C6_InterruptDriverState);
+}
+
+static int32_t I2C6_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C6_InterruptDriverState);
+}
+
+static int32_t I2C6_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptTransmit(data, num, &I2C6_InterruptDriverState);
+}
+
+static int32_t I2C6_Slave_InterruptReceive(uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptReceive(data, num, &I2C6_InterruptDriverState);
+}
+
+static int32_t I2C6_InterruptGetDataCount(void)
+{
+    return I2C_InterruptGetDataCount(&I2C6_InterruptDriverState);
+}
+
+static int32_t I2C6_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return I2C_InterruptControl(control, arg, &I2C6_InterruptDriverState);
+}
+
+static ARM_I2C_STATUS I2C6_InterruptGetStatus(void)
+{
+    return I2C_InterruptGetStatus(&I2C6_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_I2C Driver_I2C6 = {I2Cx_GetVersion,
+                              I2Cx_GetCapabilities,
+#if defined(RTE_I2C6_DMA_EN) && RTE_I2C6_DMA_EN
+                              I2C6_Master_DmaInitialize,
+                              I2C6_Master_DmaUninitialize,
+                              I2C6_Master_DmaPowerControl,
+                              I2C6_Master_DmaTransmit,
+                              I2C6_Master_DmaReceive,
+                              NULL,
+                              NULL,
+                              I2C6_Master_DmaGetDataCount,
+                              I2C6_Master_DmaControl,
+                              I2C6_Master_DmaGetStatus
+#else
+                              I2C6_InterruptInitialize,
+                              I2C6_InterruptUninitialize,
+                              I2C6_InterruptPowerControl,
+                              I2C6_Master_InterruptTransmit,
+                              I2C6_Master_InterruptReceive,
+                              I2C6_Slave_InterruptTransmit,
+                              I2C6_Slave_InterruptReceive,
+                              I2C6_InterruptGetDataCount,
+                              I2C6_InterruptControl,
+                              I2C6_InterruptGetStatus
+#endif
+};
+
+#endif
+
+#if defined(I2C7) && defined(RTE_I2C7) && RTE_I2C7
+/* User needs to provide the implementation for I2C7_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t I2C7_GetFreq(void);
+
+static cmsis_i2c_resource_t I2C7_Resource = {I2C7, I2C7_GetFreq};
+
+#if (defined(RTE_I2C7_DMA_EN) && RTE_I2C7_DMA_EN)
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_i2c_dma_resource_t I2C7_DmaResource = {RTE_I2C7_Master_DMA_BASE, RTE_I2C7_Master_DMA_CH};
+
+static i2c_master_dma_handle_t I2C7_DmaHandle;
+static dma_handle_t I2C7_DmaTxRxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c7_dma_driver_state")
+static cmsis_i2c_dma_driver_state_t I2C7_DmaDriverState = {
+#else
+static cmsis_i2c_dma_driver_state_t I2C7_DmaDriverState  = {
+#endif
+    &I2C7_Resource,
+    &I2C7_DmaResource,
+    &I2C7_DmaHandle,
+    &I2C7_DmaTxRxHandle,
+};
+
+static int32_t I2C7_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C7_PIN_INIT
+    RTE_I2C7_PIN_INIT();
+#endif
+    return I2C_Master_DmaInitialize(cb_event, &I2C7_DmaDriverState);
+}
+
+static int32_t I2C7_Master_DmaUninitialize(void)
+{
+#ifdef RTE_I2C7_PIN_DEINIT
+    RTE_I2C7_PIN_DEINIT();
+#endif
+    return I2C_Master_DmaUninitialize(&I2C7_DmaDriverState);
+}
+
+static int32_t I2C7_Master_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_Master_DmaPowerControl(state, &I2C7_DmaDriverState);
+}
+
+static int32_t I2C7_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C7_DmaDriverState);
+}
+
+static int32_t I2C7_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C7_DmaDriverState);
+}
+
+static int32_t I2C7_Master_DmaGetDataCount(void)
+{
+    return I2C_Master_DmaGetDataCount(&I2C7_DmaDriverState);
+}
+
+static int32_t I2C7_Master_DmaControl(uint32_t control, uint32_t arg)
+{
+    return I2C_Master_DmaControl(control, arg, &I2C7_DmaDriverState);
+}
+
+static ARM_I2C_STATUS I2C7_Master_DmaGetStatus(void)
+{
+    return I2C_Master_DmaGetStatus(&I2C7_DmaDriverState);
+}
+
+#endif
+
+#else
+static cmsis_i2c_handle_t I2C7_handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c7_interrupt_driver_state")
+static cmsis_i2c_interrupt_driver_state_t I2C7_InterruptDriverState = {
+#else
+static cmsis_i2c_interrupt_driver_state_t I2C7_InterruptDriverState  = {
+#endif
+    &I2C7_Resource,
+    &I2C7_handle,
+
+};
+
+static int32_t I2C7_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C7_PIN_INIT
+    RTE_I2C7_PIN_INIT();
+#endif
+    return I2C_InterruptInitialize(cb_event, &I2C7_InterruptDriverState);
+}
+
+static int32_t I2C7_InterruptUninitialize(void)
+{
+#ifdef RTE_I2C7_PIN_DEINIT
+    RTE_I2C7_PIN_DEINIT();
+#endif
+    return I2C_InterruptUninitialize(&I2C7_InterruptDriverState);
+}
+
+static int32_t I2C7_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_InterruptPowerControl(state, &I2C7_InterruptDriverState);
+}
+
+static int32_t I2C7_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C7_InterruptDriverState);
+}
+
+static int32_t I2C7_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C7_InterruptDriverState);
+}
+
+static int32_t I2C7_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptTransmit(data, num, &I2C7_InterruptDriverState);
+}
+
+static int32_t I2C7_Slave_InterruptReceive(uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptReceive(data, num, &I2C7_InterruptDriverState);
+}
+
+static int32_t I2C7_InterruptGetDataCount(void)
+{
+    return I2C_InterruptGetDataCount(&I2C7_InterruptDriverState);
+}
+
+static int32_t I2C7_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return I2C_InterruptControl(control, arg, &I2C7_InterruptDriverState);
+}
+
+static ARM_I2C_STATUS I2C7_InterruptGetStatus(void)
+{
+    return I2C_InterruptGetStatus(&I2C7_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_I2C Driver_I2C7 = {I2Cx_GetVersion,
+                              I2Cx_GetCapabilities,
+#if defined(RTE_I2C7_DMA_EN) && RTE_I2C7_DMA_EN
+                              I2C7_Master_DmaInitialize,
+                              I2C7_Master_DmaUninitialize,
+                              I2C7_Master_DmaPowerControl,
+                              I2C7_Master_DmaTransmit,
+                              I2C7_Master_DmaReceive,
+                              NULL,
+                              NULL,
+                              I2C7_Master_DmaGetDataCount,
+                              I2C7_Master_DmaControl,
+                              I2C7_Master_DmaGetStatus
+#else
+                              I2C7_InterruptInitialize,
+                              I2C7_InterruptUninitialize,
+                              I2C7_InterruptPowerControl,
+                              I2C7_Master_InterruptTransmit,
+                              I2C7_Master_InterruptReceive,
+                              I2C7_Slave_InterruptTransmit,
+                              I2C7_Slave_InterruptReceive,
+                              I2C7_InterruptGetDataCount,
+                              I2C7_InterruptControl,
+                              I2C7_InterruptGetStatus
+#endif
+};
+
+#endif
+
+#if defined(I2C8) && defined(RTE_I2C8) && RTE_I2C8
+/* User needs to provide the implementation for I2C8_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t I2C8_GetFreq(void);
+
+static cmsis_i2c_resource_t I2C8_Resource = {I2C8, I2C8_GetFreq};
+
+#if (defined(RTE_I2C8_DMA_EN) && RTE_I2C8_DMA_EN)
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_i2c_dma_resource_t I2C8_DmaResource = {RTE_I2C8_Master_DMA_BASE, RTE_I2C8_Master_DMA_CH};
+
+static i2c_master_dma_handle_t I2C8_DmaHandle;
+static dma_handle_t I2C8_DmaTxRxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c8_dma_driver_state")
+static cmsis_i2c_dma_driver_state_t I2C8_DmaDriverState = {
+#else
+static cmsis_i2c_dma_driver_state_t I2C8_DmaDriverState  = {
+#endif
+    &I2C8_Resource,
+    &I2C8_DmaResource,
+    &I2C8_DmaHandle,
+    &I2C8_DmaTxRxHandle,
+};
+
+static int32_t I2C8_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C8_PIN_INIT
+    RTE_I2C8_PIN_INIT();
+#endif
+    return I2C_Master_DmaInitialize(cb_event, &I2C8_DmaDriverState);
+}
+
+static int32_t I2C8_Master_DmaUninitialize(void)
+{
+#ifdef RTE_I2C8_PIN_DEINIT
+    RTE_I2C8_PIN_DEINIT();
+#endif
+    return I2C_Master_DmaUninitialize(&I2C8_DmaDriverState);
+}
+
+static int32_t I2C8_Master_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_Master_DmaPowerControl(state, &I2C8_DmaDriverState);
+}
+
+static int32_t I2C8_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C8_DmaDriverState);
+}
+
+static int32_t I2C8_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C8_DmaDriverState);
+}
+
+static int32_t I2C8_Master_DmaGetDataCount(void)
+{
+    return I2C_Master_DmaGetDataCount(&I2C8_DmaDriverState);
+}
+
+static int32_t I2C8_Master_DmaControl(uint32_t control, uint32_t arg)
+{
+    return I2C_Master_DmaControl(control, arg, &I2C8_DmaDriverState);
+}
+
+static ARM_I2C_STATUS I2C8_Master_DmaGetStatus(void)
+{
+    return I2C_Master_DmaGetStatus(&I2C8_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_i2c_handle_t I2C8_handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c8_interrupt_driver_state")
+static cmsis_i2c_interrupt_driver_state_t I2C8_InterruptDriverState = {
+#else
+static cmsis_i2c_interrupt_driver_state_t I2C8_InterruptDriverState  = {
+#endif
+    &I2C8_Resource,
+    &I2C8_handle,
+
+};
+
+static int32_t I2C8_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C8_PIN_INIT
+    RTE_I2C8_PIN_INIT();
+#endif
+    return I2C_InterruptInitialize(cb_event, &I2C8_InterruptDriverState);
+}
+
+static int32_t I2C8_InterruptUninitialize(void)
+{
+#ifdef RTE_I2C8_PIN_DEINIT
+    RTE_I2C8_PIN_DEINIT();
+#endif
+    return I2C_InterruptUninitialize(&I2C8_InterruptDriverState);
+}
+
+static int32_t I2C8_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_InterruptPowerControl(state, &I2C8_InterruptDriverState);
+}
+
+static int32_t I2C8_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C8_InterruptDriverState);
+}
+
+static int32_t I2C8_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C8_InterruptDriverState);
+}
+
+static int32_t I2C8_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptTransmit(data, num, &I2C8_InterruptDriverState);
+}
+
+static int32_t I2C8_Slave_InterruptReceive(uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptReceive(data, num, &I2C8_InterruptDriverState);
+}
+
+static int32_t I2C8_InterruptGetDataCount(void)
+{
+    return I2C_InterruptGetDataCount(&I2C8_InterruptDriverState);
+}
+
+static int32_t I2C8_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return I2C_InterruptControl(control, arg, &I2C8_InterruptDriverState);
+}
+
+static ARM_I2C_STATUS I2C8_InterruptGetStatus(void)
+{
+    return I2C_InterruptGetStatus(&I2C8_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_I2C Driver_I2C8 = {I2Cx_GetVersion,
+                              I2Cx_GetCapabilities,
+#if defined(RTE_I2C8_DMA_EN) && RTE_I2C8_DMA_EN
+                              I2C8_Master_DmaInitialize,
+                              I2C8_Master_DmaUninitialize,
+                              I2C8_Master_DmaPowerControl,
+                              I2C8_Master_DmaTransmit,
+                              I2C8_Master_DmaReceive,
+                              NULL,
+                              NULL,
+                              I2C8_Master_DmaGetDataCount,
+                              I2C8_Master_DmaControl,
+                              I2C8_Master_DmaGetStatus
+#else
+                              I2C8_InterruptInitialize,
+                              I2C8_InterruptUninitialize,
+                              I2C8_InterruptPowerControl,
+                              I2C8_Master_InterruptTransmit,
+                              I2C8_Master_InterruptReceive,
+                              I2C8_Slave_InterruptTransmit,
+                              I2C8_Slave_InterruptReceive,
+                              I2C8_InterruptGetDataCount,
+                              I2C8_InterruptControl,
+                              I2C8_InterruptGetStatus
+#endif
+};
+
+#endif
+
+#if defined(I2C9) && defined(RTE_I2C9) && RTE_I2C9
+/* User needs to provide the implementation for I2C9_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t I2C9_GetFreq(void);
+
+static cmsis_i2c_resource_t I2C9_Resource = {I2C9, I2C9_GetFreq};
+
+#if (defined(RTE_I2C9_DMA_EN) && RTE_I2C9_DMA_EN)
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_i2c_dma_resource_t I2C9_DmaResource = {RTE_I2C9_Master_DMA_BASE, RTE_I2C9_Master_DMA_CH};
+
+static i2c_master_dma_handle_t I2C9_DmaHandle;
+static dma_handle_t I2C9_DmaTxRxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c9_dma_driver_state")
+static cmsis_i2c_dma_driver_state_t I2C9_DmaDriverState = {
+#else
+static cmsis_i2c_dma_driver_state_t I2C9_DmaDriverState  = {
+#endif
+    &I2C9_Resource,
+    &I2C9_DmaResource,
+    &I2C9_DmaHandle,
+    &I2C9_DmaTxRxHandle,
+};
+
+static int32_t I2C9_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C9_PIN_INIT
+    RTE_I2C9_PIN_INIT();
+#endif
+    return I2C_Master_DmaInitialize(cb_event, &I2C9_DmaDriverState);
+}
+
+static int32_t I2C9_Master_DmaUninitialize(void)
+{
+#ifdef RTE_I2C9_PIN_DEINIT
+    RTE_I2C9_PIN_DEINIT();
+#endif
+    return I2C_Master_DmaUninitialize(&I2C9_DmaDriverState);
+}
+
+static int32_t I2C9_Master_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_Master_DmaPowerControl(state, &I2C9_DmaDriverState);
+}
+
+static int32_t I2C9_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C9_DmaDriverState);
+}
+
+static int32_t I2C9_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C9_DmaDriverState);
+}
+
+static int32_t I2C9_Master_DmaGetDataCount(void)
+{
+    return I2C_Master_DmaGetDataCount(&I2C9_DmaDriverState);
+}
+
+static int32_t I2C9_Master_DmaControl(uint32_t control, uint32_t arg)
+{
+    return I2C_Master_DmaControl(control, arg, &I2C9_DmaDriverState);
+}
+
+static ARM_I2C_STATUS I2C9_Master_DmaGetStatus(void)
+{
+    return I2C_Master_DmaGetStatus(&I2C9_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_i2c_handle_t I2C9_handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c9_interrupt_driver_state")
+static cmsis_i2c_interrupt_driver_state_t I2C9_InterruptDriverState = {
+#else
+static cmsis_i2c_interrupt_driver_state_t I2C9_InterruptDriverState  = {
+#endif
+    &I2C9_Resource,
+    &I2C9_handle,
+
+};
+
+static int32_t I2C9_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C9_PIN_INIT
+    RTE_I2C9_PIN_INIT();
+#endif
+    return I2C_InterruptInitialize(cb_event, &I2C9_InterruptDriverState);
+}
+
+static int32_t I2C9_InterruptUninitialize(void)
+{
+#ifdef RTE_I2C9_PIN_DEINIT
+    RTE_I2C9_PIN_DEINIT();
+#endif
+    return I2C_InterruptUninitialize(&I2C9_InterruptDriverState);
+}
+
+static int32_t I2C9_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_InterruptPowerControl(state, &I2C9_InterruptDriverState);
+}
+
+static int32_t I2C9_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C9_InterruptDriverState);
+}
+
+static int32_t I2C9_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C9_InterruptDriverState);
+}
+
+static int32_t I2C9_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptTransmit(data, num, &I2C9_InterruptDriverState);
+}
+
+static int32_t I2C9_Slave_InterruptReceive(uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptReceive(data, num, &I2C9_InterruptDriverState);
+}
+
+static int32_t I2C9_InterruptGetDataCount(void)
+{
+    return I2C_InterruptGetDataCount(&I2C9_InterruptDriverState);
+}
+
+static int32_t I2C9_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return I2C_InterruptControl(control, arg, &I2C9_InterruptDriverState);
+}
+
+static ARM_I2C_STATUS I2C9_InterruptGetStatus(void)
+{
+    return I2C_InterruptGetStatus(&I2C9_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_I2C Driver_I2C9 = {I2Cx_GetVersion,
+                              I2Cx_GetCapabilities,
+#if defined(RTE_I2C9_DMA_EN) && RTE_I2C9_DMA_EN
+                              I2C9_Master_DmaInitialize,
+                              I2C9_Master_DmaUninitialize,
+                              I2C9_Master_DmaPowerControl,
+                              I2C9_Master_DmaTransmit,
+                              I2C9_Master_DmaReceive,
+                              NULL,
+                              NULL,
+                              I2C9_Master_DmaGetDataCount,
+                              I2C9_Master_DmaControl,
+                              I2C9_Master_DmaGetStatus
+#else
+                              I2C9_InterruptInitialize,
+                              I2C9_InterruptUninitialize,
+                              I2C9_InterruptPowerControl,
+                              I2C9_Master_InterruptTransmit,
+                              I2C9_Master_InterruptReceive,
+                              I2C9_Slave_InterruptTransmit,
+                              I2C9_Slave_InterruptReceive,
+                              I2C9_InterruptGetDataCount,
+                              I2C9_InterruptControl,
+                              I2C9_InterruptGetStatus
+#endif
+};
+
+#endif
+
+#if defined(I2C10) && defined(RTE_I2C10) && RTE_I2C10
+
+/* User needs to provide the implementation for I2C10_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t I2C10_GetFreq(void);
+
+static cmsis_i2c_resource_t I2C10_Resource = {I2C10, I2C10_GetFreq};
+
+#if (defined(RTE_I2C10_DMA_EN) && RTE_I2C10_DMA_EN)
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_i2c_dma_resource_t I2C10_DmaResource = {RTE_I2C10_Master_DMA_BASE, RTE_I2C10_Master_DMA_CH};
+
+static i2c_master_dma_handle_t I2C10_DmaHandle;
+static dma_handle_t I2C10_DmaTxRxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c10_dma_driver_state")
+static cmsis_i2c_dma_driver_state_t I2C10_DmaDriverState = {
+#else
+static cmsis_i2c_dma_driver_state_t I2C10_DmaDriverState = {
+#endif
+    &I2C10_Resource,
+    &I2C10_DmaResource,
+    &I2C10_DmaHandle,
+    &I2C10_DmaTxRxHandle,
+};
+
+static int32_t I2C10_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C10_PIN_INIT
+    RTE_I2C10_PIN_INIT();
+#endif
+    return I2C_Master_DmaInitialize(cb_event, &I2C10_DmaDriverState);
+}
+
+static int32_t I2C10_Master_DmaUninitialize(void)
+{
+#ifdef RTE_I2C10_PIN_DEINIT
+    RTE_I2C10_PIN_DEINIT();
+#endif
+    return I2C_Master_DmaUninitialize(&I2C10_DmaDriverState);
+}
+
+static int32_t I2C10_Master_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_Master_DmaPowerControl(state, &I2C10_DmaDriverState);
+}
+
+static int32_t I2C10_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C10_DmaDriverState);
+}
+
+static int32_t I2C10_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C10_DmaDriverState);
+}
+
+static int32_t I2C10_Master_DmaGetDataCount(void)
+{
+    return I2C_Master_DmaGetDataCount(&I2C10_DmaDriverState);
+}
+
+static int32_t I2C10_Master_DmaControl(uint32_t control, uint32_t arg)
+{
+    return I2C_Master_DmaControl(control, arg, &I2C10_DmaDriverState);
+}
+
+static ARM_I2C_STATUS I2C10_Master_DmaGetStatus(void)
+{
+    return I2C_Master_DmaGetStatus(&I2C10_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_i2c_handle_t I2C10_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c10_interrupt_driver_state")
+static cmsis_i2c_interrupt_driver_state_t I2C10_InterruptDriverState = {
+#else
+static cmsis_i2c_interrupt_driver_state_t I2C10_InterruptDriverState = {
+#endif
+    &I2C10_Resource,
+    &I2C10_Handle,
+};
+
+static int32_t I2C10_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C10_PIN_INIT
+    RTE_I2C10_PIN_INIT();
+#endif
+    return I2C_InterruptInitialize(cb_event, &I2C10_InterruptDriverState);
+}
+
+static int32_t I2C10_InterruptUninitialize(void)
+{
+#ifdef RTE_I2C10_PIN_DEINIT
+    RTE_I2C10_PIN_DEINIT();
+#endif
+    return I2C_InterruptUninitialize(&I2C10_InterruptDriverState);
+}
+
+static int32_t I2C10_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_InterruptPowerControl(state, &I2C10_InterruptDriverState);
+}
+
+static int32_t I2C10_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C10_InterruptDriverState);
+}
+
+static int32_t I2C10_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C10_InterruptDriverState);
+}
+
+static int32_t I2C10_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptTransmit(data, num, &I2C10_InterruptDriverState);
+}
+
+static int32_t I2C10_Slave_InterruptReceive(uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptReceive(data, num, &I2C10_InterruptDriverState);
+}
+
+static int32_t I2C10_InterruptGetDataCount(void)
+{
+    return I2C_InterruptGetDataCount(&I2C10_InterruptDriverState);
+}
+
+static int32_t I2C10_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return I2C_InterruptControl(control, arg, &I2C10_InterruptDriverState);
+}
+
+static ARM_I2C_STATUS I2C10_InterruptGetStatus(void)
+{
+    return I2C_InterruptGetStatus(&I2C10_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_I2C Driver_I2C10 = {I2Cx_GetVersion,
+                               I2Cx_GetCapabilities,
+#if defined(RTE_I2C10_DMA_EN) && RTE_I2C10_DMA_EN
+                               I2C10_Master_DmaInitialize,
+                               I2C10_Master_DmaUninitialize,
+                               I2C10_Master_DmaPowerControl,
+                               I2C10_Master_DmaTransmit,
+                               I2C10_Master_DmaReceive,
+                               NULL,
+                               NULL,
+                               I2C10_Master_DmaGetDataCount,
+                               I2C10_Master_DmaControl,
+                               I2C10_Master_DmaGetStatus
+#else
+                               I2C10_InterruptInitialize,
+                               I2C10_InterruptUninitialize,
+                               I2C10_InterruptPowerControl,
+                               I2C10_Master_InterruptTransmit,
+                               I2C10_Master_InterruptReceive,
+                               I2C10_Slave_InterruptTransmit,
+                               I2C10_Slave_InterruptReceive,
+                               I2C10_InterruptGetDataCount,
+                               I2C10_InterruptControl,
+                               I2C10_InterruptGetStatus
+#endif
+};
+
+#endif
+
+#if defined(I2C11) && defined(RTE_I2C11) && RTE_I2C11
+
+/* User needs to provide the implementation for I2C1_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t I2C11_GetFreq(void);
+
+static cmsis_i2c_resource_t I2C11_Resource = {I2C11, I2C11_GetFreq};
+
+#if (defined(RTE_I2C11_DMA_EN) && RTE_I2C11_DMA_EN)
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_i2c_dma_resource_t I2C11_DmaResource = {RTE_I2C11_Master_DMA_BASE, RTE_I2C11_Master_DMA_CH};
+
+static i2c_master_dma_handle_t I2C11_DmaHandle;
+static dma_handle_t I2C11_DmaTxRxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c11_dma_driver_state")
+static cmsis_i2c_dma_driver_state_t I2C11_DmaDriverState = {
+#else
+static cmsis_i2c_dma_driver_state_t I2C11_DmaDriverState = {
+#endif
+    &I2C11_Resource,
+    &I2C11_DmaResource,
+    &I2C11_DmaHandle,
+    &I2C11_DmaTxRxHandle,
+};
+
+static int32_t I2C11_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C11_PIN_INIT
+    RTE_I2C11_PIN_INIT();
+#endif
+    return I2C_Master_DmaInitialize(cb_event, &I2C11_DmaDriverState);
+}
+
+static int32_t I2C11_Master_DmaUninitialize(void)
+{
+#ifdef RTE_I2C11_PIN_DEINIT
+    RTE_I2C11_PIN_DEINIT();
+#endif
+    return I2C_Master_DmaUninitialize(&I2C11_DmaDriverState);
+}
+
+static int32_t I2C11_Master_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_Master_DmaPowerControl(state, &I2C11_DmaDriverState);
+}
+
+static int32_t I2C11_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C11_DmaDriverState);
+}
+
+static int32_t I2C11_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C11_DmaDriverState);
+}
+
+static int32_t I2C11_Master_DmaGetDataCount(void)
+{
+    return I2C_Master_DmaGetDataCount(&I2C11_DmaDriverState);
+}
+
+static int32_t I2C11_Master_DmaControl(uint32_t control, uint32_t arg)
+{
+    return I2C_Master_DmaControl(control, arg, &I2C11_DmaDriverState);
+}
+
+static ARM_I2C_STATUS I2C11_Master_DmaGetStatus(void)
+{
+    return I2C_Master_DmaGetStatus(&I2C11_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_i2c_handle_t I2C11_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c11_interrupt_driver_state")
+static cmsis_i2c_interrupt_driver_state_t I2C11_InterruptDriverState = {
+#else
+static cmsis_i2c_interrupt_driver_state_t I2C11_InterruptDriverState = {
+#endif
+    &I2C11_Resource,
+    &I2C11_Handle,
+};
+
+static int32_t I2C11_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C11_PIN_INIT
+    RTE_I2C11_PIN_INIT();
+#endif
+    return I2C_InterruptInitialize(cb_event, &I2C11_InterruptDriverState);
+}
+
+static int32_t I2C11_InterruptUninitialize(void)
+{
+#ifdef RTE_I2C11_PIN_DEINIT
+    RTE_I2C11_PIN_DEINIT();
+#endif
+    return I2C_InterruptUninitialize(&I2C11_InterruptDriverState);
+}
+
+static int32_t I2C11_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_InterruptPowerControl(state, &I2C11_InterruptDriverState);
+}
+
+static int32_t I2C11_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C11_InterruptDriverState);
+}
+
+static int32_t I2C11_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C11_InterruptDriverState);
+}
+
+static int32_t I2C11_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptTransmit(data, num, &I2C11_InterruptDriverState);
+}
+
+static int32_t I2C11_Slave_InterruptReceive(uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptReceive(data, num, &I2C11_InterruptDriverState);
+}
+
+static int32_t I2C11_InterruptGetDataCount(void)
+{
+    return I2C_InterruptGetDataCount(&I2C11_InterruptDriverState);
+}
+
+static int32_t I2C11_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return I2C_InterruptControl(control, arg, &I2C11_InterruptDriverState);
+}
+
+static ARM_I2C_STATUS I2C11_InterruptGetStatus(void)
+{
+    return I2C_InterruptGetStatus(&I2C11_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_I2C Driver_I2C11 = {I2Cx_GetVersion,
+                               I2Cx_GetCapabilities,
+#if defined(RTE_I2C11_DMA_EN) && RTE_I2C11_DMA_EN
+                               I2C11_Master_DmaInitialize,
+                               I2C11_Master_DmaUninitialize,
+                               I2C11_Master_DmaPowerControl,
+                               I2C11_Master_DmaTransmit,
+                               I2C11_Master_DmaReceive,
+                               NULL,
+                               NULL,
+                               I2C11_Master_DmaGetDataCount,
+                               I2C11_Master_DmaControl,
+                               I2C11_Master_DmaGetStatus
+#else
+                               I2C11_InterruptInitialize,
+                               I2C11_InterruptUninitialize,
+                               I2C11_InterruptPowerControl,
+                               I2C11_Master_InterruptTransmit,
+                               I2C11_Master_InterruptReceive,
+                               I2C11_Slave_InterruptTransmit,
+                               I2C11_Slave_InterruptReceive,
+                               I2C11_InterruptGetDataCount,
+                               I2C11_InterruptControl,
+                               I2C11_InterruptGetStatus
+#endif
+};
+
+#endif
+
+#if defined(I2C12) && defined(RTE_I2C12) && RTE_I2C12
+
+/* User needs to provide the implementation for I2C1_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t I2C12_GetFreq(void);
+
+static cmsis_i2c_resource_t I2C12_Resource = {I2C12, I2C12_GetFreq};
+
+#if (defined(RTE_I2C12_DMA_EN) && RTE_I2C12_DMA_EN)
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_i2c_dma_resource_t I2C12_DmaResource = {RTE_I2C12_Master_DMA_BASE, RTE_I2C12_Master_DMA_CH};
+
+static i2c_master_dma_handle_t I2C12_DmaHandle;
+static dma_handle_t I2C12_DmaTxRxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c12_dma_driver_state")
+static cmsis_i2c_dma_driver_state_t I2C12_DmaDriverState = {
+#else
+static cmsis_i2c_dma_driver_state_t I2C12_DmaDriverState = {
+#endif
+    &I2C12_Resource,
+    &I2C12_DmaResource,
+    &I2C12_DmaHandle,
+    &I2C12_DmaTxRxHandle,
+};
+
+static int32_t I2C12_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C12_PIN_INIT
+    RTE_I2C12_PIN_INIT();
+#endif
+    return I2C_Master_DmaInitialize(cb_event, &I2C12_DmaDriverState);
+}
+
+static int32_t I2C12_Master_DmaUninitialize(void)
+{
+#ifdef RTE_I2C12_PIN_DEINIT
+    RTE_I2C12_PIN_DEINIT();
+#endif
+    return I2C_Master_DmaUninitialize(&I2C12_DmaDriverState);
+}
+
+static int32_t I2C12_Master_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_Master_DmaPowerControl(state, &I2C12_DmaDriverState);
+}
+
+static int32_t I2C12_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C12_DmaDriverState);
+}
+
+static int32_t I2C12_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C12_DmaDriverState);
+}
+
+static int32_t I2C12_Master_DmaGetDataCount(void)
+{
+    return I2C_Master_DmaGetDataCount(&I2C12_DmaDriverState);
+}
+
+static int32_t I2C12_Master_DmaControl(uint32_t control, uint32_t arg)
+{
+    return I2C_Master_DmaControl(control, arg, &I2C12_DmaDriverState);
+}
+
+static ARM_I2C_STATUS I2C12_Master_DmaGetStatus(void)
+{
+    return I2C_Master_DmaGetStatus(&I2C12_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_i2c_handle_t I2C12_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c12_interrupt_driver_state")
+static cmsis_i2c_interrupt_driver_state_t I2C12_InterruptDriverState = {
+#else
+static cmsis_i2c_interrupt_driver_state_t I2C12_InterruptDriverState = {
+#endif
+    &I2C12_Resource,
+    &I2C12_Handle,
+};
+
+static int32_t I2C12_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C12_PIN_INIT
+    RTE_I2C12_PIN_INIT();
+#endif
+    return I2C_InterruptInitialize(cb_event, &I2C12_InterruptDriverState);
+}
+
+static int32_t I2C12_InterruptUninitialize(void)
+{
+#ifdef RTE_I2C12_PIN_DEINIT
+    RTE_I2C12_PIN_DEINIT();
+#endif
+    return I2C_InterruptUninitialize(&I2C12_InterruptDriverState);
+}
+
+static int32_t I2C12_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_InterruptPowerControl(state, &I2C12_InterruptDriverState);
+}
+
+static int32_t I2C12_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C12_InterruptDriverState);
+}
+
+static int32_t I2C12_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C12_InterruptDriverState);
+}
+
+static int32_t I2C12_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptTransmit(data, num, &I2C12_InterruptDriverState);
+}
+
+static int32_t I2C12_Slave_InterruptReceive(uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptReceive(data, num, &I2C12_InterruptDriverState);
+}
+
+static int32_t I2C12_InterruptGetDataCount(void)
+{
+    return I2C_InterruptGetDataCount(&I2C12_InterruptDriverState);
+}
+
+static int32_t I2C12_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return I2C_InterruptControl(control, arg, &I2C12_InterruptDriverState);
+}
+
+static ARM_I2C_STATUS I2C12_InterruptGetStatus(void)
+{
+    return I2C_InterruptGetStatus(&I2C12_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_I2C Driver_I2C12 = {I2Cx_GetVersion,
+                               I2Cx_GetCapabilities,
+#if defined(RTE_I2C12_DMA_EN) && RTE_I2C12_DMA_EN
+                               I2C12_Master_DmaInitialize,
+                               I2C12_Master_DmaUninitialize,
+                               I2C12_Master_DmaPowerControl,
+                               I2C12_Master_DmaTransmit,
+                               I2C12_Master_DmaReceive,
+                               NULL,
+                               NULL,
+                               I2C12_Master_DmaGetDataCount,
+                               I2C12_Master_DmaControl,
+                               I2C12_Master_DmaGetStatus
+#else
+                               I2C12_InterruptInitialize,
+                               I2C12_InterruptUninitialize,
+                               I2C12_InterruptPowerControl,
+                               I2C12_Master_InterruptTransmit,
+                               I2C12_Master_InterruptReceive,
+                               I2C12_Slave_InterruptTransmit,
+                               I2C12_Slave_InterruptReceive,
+                               I2C12_InterruptGetDataCount,
+                               I2C12_InterruptControl,
+                               I2C12_InterruptGetStatus
+#endif
+};
+
+#endif
+
+#if defined(I2C13) && defined(RTE_I2C13) && RTE_I2C13
+
+/* User needs to provide the implementation for I2C1_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t I2C13_GetFreq(void);
+
+static cmsis_i2c_resource_t I2C13_Resource = {I2C13, I2C13_GetFreq};
+
+#if (defined(RTE_I2C13_DMA_EN) && RTE_I2C13_DMA_EN)
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_i2c_dma_resource_t I2C13_DmaResource = {RTE_I2C13_Master_DMA_BASE, RTE_I2C13_Master_DMA_CH};
+
+static i2c_master_dma_handle_t I2C13_DmaHandle;
+static dma_handle_t I2C13_DmaTxRxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c13_dma_driver_state")
+static cmsis_i2c_dma_driver_state_t I2C13_DmaDriverState = {
+#else
+static cmsis_i2c_dma_driver_state_t I2C13_DmaDriverState = {
+#endif
+    &I2C13_Resource,
+    &I2C13_DmaResource,
+    &I2C13_DmaHandle,
+    &I2C13_DmaTxRxHandle,
+};
+
+static int32_t I2C13_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C13_PIN_INIT
+    RTE_I2C13_PIN_INIT();
+#endif
+    return I2C_Master_DmaInitialize(cb_event, &I2C13_DmaDriverState);
+}
+
+static int32_t I2C13_Master_DmaUninitialize(void)
+{
+#ifdef RTE_I2C13_PIN_DEINIT
+    RTE_I2C13_PIN_DEINIT();
+#endif
+    return I2C_Master_DmaUninitialize(&I2C13_DmaDriverState);
+}
+
+static int32_t I2C13_Master_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_Master_DmaPowerControl(state, &I2C13_DmaDriverState);
+}
+
+static int32_t I2C13_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C13_DmaDriverState);
+}
+
+static int32_t I2C13_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C13_DmaDriverState);
+}
+
+static int32_t I2C13_Master_DmaGetDataCount(void)
+{
+    return I2C_Master_DmaGetDataCount(&I2C13_DmaDriverState);
+}
+
+static int32_t I2C13_Master_DmaControl(uint32_t control, uint32_t arg)
+{
+    return I2C_Master_DmaControl(control, arg, &I2C13_DmaDriverState);
+}
+
+static ARM_I2C_STATUS I2C13_Master_DmaGetStatus(void)
+{
+    return I2C_Master_DmaGetStatus(&I2C13_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_i2c_handle_t I2C13_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("i2c13_interrupt_driver_state")
+static cmsis_i2c_interrupt_driver_state_t I2C13_InterruptDriverState = {
+#else
+static cmsis_i2c_interrupt_driver_state_t I2C13_InterruptDriverState = {
+#endif
+    &I2C13_Resource,
+    &I2C13_Handle,
+};
+
+static int32_t I2C13_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
+{
+#ifdef RTE_I2C13_PIN_INIT
+    RTE_I2C13_PIN_INIT();
+#endif
+    return I2C_InterruptInitialize(cb_event, &I2C13_InterruptDriverState);
+}
+
+static int32_t I2C13_InterruptUninitialize(void)
+{
+#ifdef RTE_I2C13_PIN_DEINIT
+    RTE_I2C13_PIN_DEINIT();
+#endif
+    return I2C_InterruptUninitialize(&I2C13_InterruptDriverState);
+}
+
+static int32_t I2C13_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return I2C_InterruptPowerControl(state, &I2C13_InterruptDriverState);
+}
+
+static int32_t I2C13_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C13_InterruptDriverState);
+}
+
+static int32_t I2C13_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+    return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C13_InterruptDriverState);
+}
+
+static int32_t I2C13_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptTransmit(data, num, &I2C13_InterruptDriverState);
+}
+
+static int32_t I2C13_Slave_InterruptReceive(uint8_t *data, uint32_t num)
+{
+    return I2C_Slave_InterruptReceive(data, num, &I2C13_InterruptDriverState);
+}
+
+static int32_t I2C13_InterruptGetDataCount(void)
+{
+    return I2C_InterruptGetDataCount(&I2C13_InterruptDriverState);
+}
+
+static int32_t I2C13_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return I2C_InterruptControl(control, arg, &I2C13_InterruptDriverState);
+}
+
+static ARM_I2C_STATUS I2C13_InterruptGetStatus(void)
+{
+    return I2C_InterruptGetStatus(&I2C13_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_I2C Driver_I2C13 = {I2Cx_GetVersion,
+                               I2Cx_GetCapabilities,
+#if defined(RTE_I2C13_DMA_EN) && RTE_I2C13_DMA_EN
+                               I2C13_Master_DmaInitialize,
+                               I2C13_Master_DmaUninitialize,
+                               I2C13_Master_DmaPowerControl,
+                               I2C13_Master_DmaTransmit,
+                               I2C13_Master_DmaReceive,
+                               NULL,
+                               NULL,
+                               I2C13_Master_DmaGetDataCount,
+                               I2C13_Master_DmaControl,
+                               I2C13_Master_DmaGetStatus
+#else
+                               I2C13_InterruptInitialize,
+                               I2C13_InterruptUninitialize,
+                               I2C13_InterruptPowerControl,
+                               I2C13_Master_InterruptTransmit,
+                               I2C13_Master_InterruptReceive,
+                               I2C13_Slave_InterruptTransmit,
+                               I2C13_Slave_InterruptReceive,
+                               I2C13_InterruptGetDataCount,
+                               I2C13_InterruptControl,
+                               I2C13_InterruptGetStatus
+#endif
+};
+
+#endif

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_i2c_cmsis.h

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
+ * Copyright 2016-2020 NXP. Not a Contribution.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _FSL_I2C_CMSIS_H_
+#define _FSL_I2C_CMSIS_H_
+#include "fsl_common.h"
+#include "Driver_I2C.h"
+#include "RTE_Device.h"
+#include "fsl_i2c.h"
+#include "fsl_flexcomm.h"
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+#include "fsl_i2c_dma.h"
+#endif
+
+#if defined(I2C0) && defined(RTE_I2C0) && RTE_I2C0
+extern ARM_DRIVER_I2C Driver_I2C0;
+#endif
+
+#if defined(I2C1) && defined(RTE_I2C1) && RTE_I2C1
+extern ARM_DRIVER_I2C Driver_I2C1;
+#endif
+
+#if defined(I2C2) && defined(RTE_I2C2) && RTE_I2C2
+extern ARM_DRIVER_I2C Driver_I2C2;
+#endif
+
+#if defined(I2C3) && defined(RTE_I2C3) && RTE_I2C3
+extern ARM_DRIVER_I2C Driver_I2C3;
+#endif
+
+#if defined(I2C4) && defined(RTE_I2C4) && RTE_I2C4
+extern ARM_DRIVER_I2C Driver_I2C4;
+#endif
+
+#if defined(I2C5) && defined(RTE_I2C5) && RTE_I2C5
+extern ARM_DRIVER_I2C Driver_I2C5;
+#endif
+
+#if defined(I2C6) && defined(RTE_I2C6) && RTE_I2C6
+extern ARM_DRIVER_I2C Driver_I2C6;
+#endif
+
+#if defined(I2C7) && defined(RTE_I2C7) && RTE_I2C7
+extern ARM_DRIVER_I2C Driver_I2C7;
+#endif
+
+#if defined(I2C8) && defined(RTE_I2C8) && RTE_I2C8
+extern ARM_DRIVER_I2C Driver_I2C8;
+#endif
+
+#if defined(I2C9) && defined(RTE_I2C9) && RTE_I2C9
+extern ARM_DRIVER_I2C Driver_I2C9;
+#endif
+
+#if defined(I2C10) && defined(RTE_I2C10) && RTE_I2C10
+extern ARM_DRIVER_I2C Driver_I2C10;
+#endif
+
+#if defined(I2C11) && defined(RTE_I2C11) && RTE_I2C11
+extern ARM_DRIVER_I2C Driver_I2C11;
+#endif
+
+#if defined(I2C12) && defined(RTE_I2C12) && RTE_I2C12
+extern ARM_DRIVER_I2C Driver_I2C12;
+#endif
+
+#if defined(I2C13) && defined(RTE_I2C13) && RTE_I2C13
+extern ARM_DRIVER_I2C Driver_I2C13;
+#endif
+
+/* I2C Driver state flags */
+#define I2C_FLAG_UNINIT (0UL)
+#define I2C_FLAG_INIT   (1UL << 0)
+#define I2C_FLAG_POWER  (1UL << 1)
+
+#endif

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_spi_cmsis.c

@@ -0,0 +1,3712 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
+ * Copyright 2016-2020 NXP. Not a Contribution.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "fsl_spi_cmsis.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_cmsis"
+#endif
+
+#if ((defined(RTE_SPI0) && RTE_SPI0) || (defined(RTE_SPI1) && RTE_SPI1) || (defined(RTE_SPI2) && RTE_SPI2) ||     \
+     (defined(RTE_SPI3) && RTE_SPI3) || (defined(RTE_SPI4) && RTE_SPI4) || (defined(RTE_SPI5) && RTE_SPI5) ||     \
+     (defined(RTE_SPI6) && RTE_SPI6) || (defined(RTE_SPI7) && RTE_SPI7) || (defined(RTE_SPI8) && RTE_SPI8) ||     \
+     (defined(RTE_SPI9) && RTE_SPI9) || (defined(RTE_SPI10) && RTE_SPI10) || (defined(RTE_SPI11) && RTE_SPI11) || \
+     (defined(RTE_SPI12) && RTE_SPI12) || (defined(RTE_SPI13) && RTE_SPI13))
+
+#define ARM_SPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 4) /* driver version */
+
+/*! @brief IDs of clock for each FLEXCOMM module */
+static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;
+/*
+ * ARMCC does not support split the data section automatically, so the driver
+ * needs to split the data to separate sections explicitly, to reduce codesize.
+ */
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#define ARMCC_SECTION(section_name) __attribute__((section(section_name)))
+#endif
+
+typedef const struct _cmsis_spi_resource
+{
+    SPI_Type *base;
+    uint32_t instance;
+    uint32_t (*GetFreq)(void);
+} cmsis_spi_resource_t;
+
+typedef union _cmsis_spi_handle
+{
+    spi_master_handle_t masterHandle;
+    spi_slave_handle_t slaveHandle;
+} cmsis_spi_handle_t;
+
+typedef struct _cmsis_spi_interrupt_driver_state
+{
+    cmsis_spi_resource_t *resource;
+    cmsis_spi_handle_t *handle;
+    ARM_SPI_SignalEvent_t cb_event;
+    uint32_t baudRate_Bps;
+    uint8_t flags; /*!< Control and state flags. */
+} cmsis_spi_interrupt_driver_state_t;
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+typedef const struct _cmsis_spi_dma_resource
+{
+    DMA_Type *txdmaBase;
+    uint32_t txdmaChannel;
+
+    DMA_Type *rxdmaBase;
+    uint32_t rxdmaChannel;
+} cmsis_spi_dma_resource_t;
+
+typedef union _cmsis_spi_dma_handle
+{
+    spi_dma_handle_t masterHandle;
+    spi_dma_handle_t slaveHandle;
+} cmsis_spi_dma_handle_t;
+
+typedef struct _cmsis_spi_dma_driver_state
+{
+    cmsis_spi_resource_t *resource;
+    cmsis_spi_dma_resource_t *dmaResource;
+    cmsis_spi_dma_handle_t *handle;
+    dma_handle_t *dmaRxDataHandle;
+    dma_handle_t *dmaTxDataHandle;
+
+    uint32_t baudRate_Bps;
+    ARM_SPI_SignalEvent_t cb_event;
+    uint8_t flags; /*!< Control and state flags. */
+} cmsis_spi_dma_driver_state_t;
+#endif
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION s_SPIDriverVersion = {ARM_SPI_API_VERSION, ARM_SPI_DRV_VERSION};
+
+/* Driver Capabilities */
+static const ARM_SPI_CAPABILITIES s_SPIDriverCapabilities = {
+    1, /* Simplex Mode (Master and Slave) */
+    0, /* TI Synchronous Serial Interface */
+    0, /* Microwire Interface  */
+    0  /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */
+};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void SPI_MasterCommonControl(uint32_t control,
+                                    cmsis_spi_resource_t *resource,
+                                    uint8_t *status,
+                                    spi_master_config_t *masterConfig)
+{
+    switch (resource->instance)
+    {
+        case 0:
+#if defined(RTE_SPI0_SSEL_NUM)
+            masterConfig->sselNum = RTE_SPI0_SSEL_NUM;
+#endif
+#if defined(RTE_SPI0_SSEL_POL)
+            masterConfig->sselPol = RTE_SPI0_SSEL_POL;
+#endif
+            break;
+
+        case 1:
+#if defined(RTE_SPI1_SSEL_NUM)
+            masterConfig->sselNum = RTE_SPI1_SSEL_NUM;
+#endif
+#if defined(RTE_SPI1_SSEL_POL)
+            masterConfig->sselPol = RTE_SPI1_SSEL_POL;
+#endif
+            break;
+        case 2:
+#if defined(RTE_SPI2_SSEL_NUM)
+            masterConfig->sselNum = RTE_SPI2_SSEL_NUM;
+#endif
+#if defined(RTE_SPI2_SSEL_POL)
+            masterConfig->sselPol = RTE_SPI2_SSEL_POL;
+#endif
+            break;
+
+        case 3:
+#if defined(RTE_SPI3_SSEL_NUM)
+            masterConfig->sselNum = RTE_SPI3_SSEL_NUM;
+#endif
+#if defined(RTE_SPI3_SSEL_POL)
+            masterConfig->sselPol = RTE_SPI3_SSEL_POL;
+#endif
+            break;
+
+        case 4:
+#if defined(RTE_SPI4_SSEL_NUM)
+            masterConfig->sselNum = RTE_SPI4_SSEL_NUM;
+#endif
+#if defined(RTE_SPI4_SSEL_POL)
+            masterConfig->sselPol = RTE_SPI4_SSEL_POL;
+#endif
+            break;
+
+        case 5:
+#if defined(RTE_SPI5_SSEL_NUM)
+            masterConfig->sselNum = RTE_SPI5_SSEL_NUM;
+#endif
+#if defined(RTE_SPI5_SSEL_POL)
+            masterConfig->sselPol = RTE_SPI5_SSEL_POL;
+#endif
+            break;
+
+        case 6:
+#if defined(RTE_SPI6_SSEL_NUM)
+            masterConfig->sselNum = RTE_SPI6_SSEL_NUM;
+#endif
+#if defined(RTE_SPI6_SSEL_POL)
+            masterConfig->sselPol = RTE_SPI6_SSEL_POL;
+#endif
+            break;
+
+        case 7:
+#if defined(RTE_SPI7_SSEL_NUM)
+            masterConfig->sselNum = RTE_SPI7_SSEL_NUM;
+#endif
+#if defined(RTE_SPI7_SSEL_POL)
+            masterConfig->sselPol = RTE_SPI7_SSEL_POL;
+#endif
+            break;
+
+        case 8:
+#if defined(RTE_SPI8_SSEL_NUM)
+            masterConfig->sselNum = RTE_SPI8_SSEL_NUM;
+#endif
+#if defined(RTE_SPI8_SSEL_POL)
+            masterConfig->sselPol = RTE_SPI8_SSEL_POL;
+#endif
+            break;
+
+        case 9:
+#if defined(RTE_SPI9_SSEL_NUM)
+            masterConfig->sselNum = RTE_SPI9_SSEL_NUM;
+#endif
+#if defined(RTE_SPI9_SSEL_POL)
+            masterConfig->sselPol = RTE_SPI9_SSEL_POL;
+#endif
+            break;
+
+        case 10:
+#if defined(RTE_SPI10_SSEL_NUM)
+            masterConfig->sselNum = RTE_SPI10_SSEL_NUM;
+#endif
+#if defined(RTE_SPI10_SSEL_POL)
+            masterConfig->sselPol = RTE_SPI10_SSEL_POL;
+#endif
+            break;
+
+        case 11:
+#if defined(RTE_SPI11_SSEL_NUM)
+            masterConfig->sselNum = RTE_SPI11_SSEL_NUM;
+#endif
+#if defined(RTE_SPI11_SSEL_POL)
+            masterConfig->sselPol = RTE_SPI11_SSEL_POL;
+#endif
+            break;
+
+        case 12:
+#if defined(RTE_SPI12_SSEL_NUM)
+            masterConfig->sselNum = RTE_SPI12_SSEL_NUM;
+#endif
+#if defined(RTE_SPI12_SSEL_POL)
+            masterConfig->sselPol = RTE_SPI12_SSEL_POL;
+#endif
+            break;
+
+        case 13:
+#if defined(RTE_SPI13_SSEL_NUM)
+            masterConfig->sselNum = RTE_SPI13_SSEL_NUM;
+#endif
+#if defined(RTE_SPI13_SSEL_POL)
+            masterConfig->sselPol = RTE_SPI13_SSEL_POL;
+#endif
+            break;
+
+        default:
+            /* Avoid MISRA 16.4 violation */
+            break;
+    }
+
+    switch (control & ARM_SPI_FRAME_FORMAT_Msk)
+    {
+        case ARM_SPI_CPOL0_CPHA0:
+            masterConfig->polarity = kSPI_ClockPolarityActiveHigh;
+            masterConfig->phase    = kSPI_ClockPhaseFirstEdge;
+            break;
+
+        case ARM_SPI_CPOL0_CPHA1:
+            masterConfig->polarity = kSPI_ClockPolarityActiveHigh;
+            masterConfig->phase    = kSPI_ClockPhaseSecondEdge;
+            break;
+
+        case ARM_SPI_CPOL1_CPHA0:
+            masterConfig->polarity = kSPI_ClockPolarityActiveLow;
+            masterConfig->phase    = kSPI_ClockPhaseFirstEdge;
+            break;
+
+        case ARM_SPI_CPOL1_CPHA1:
+            masterConfig->polarity = kSPI_ClockPolarityActiveLow;
+            masterConfig->phase    = kSPI_ClockPhaseSecondEdge;
+            break;
+
+        default:
+            /* Avoid MISRA 16.4 violation */
+            break;
+    }
+
+    if ((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) != 0U) /* setting Number of Data bits */
+    {
+        if ((((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) >= 4U) &&
+            (((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) <= 16U))
+        {
+            masterConfig->dataWidth =
+                (spi_data_width_t)(((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) - 1U);
+        }
+    }
+
+    switch (control & ARM_SPI_BIT_ORDER_Msk)
+    {
+        case ARM_SPI_LSB_MSB:
+            masterConfig->direction = kSPI_LsbFirst;
+            break;
+        case ARM_SPI_MSB_LSB:
+            masterConfig->direction = kSPI_MsbFirst;
+            break;
+
+        default:
+            /* Avoid MISRA 16.4 violation */
+            break;
+    }
+}
+
+static void SPI_SlaveCommonControl(uint32_t control,
+                                   cmsis_spi_resource_t *resource,
+                                   uint8_t *status,
+                                   spi_slave_config_t *slaveConfig)
+{
+    switch (resource->instance)
+    {
+        case 0:
+#if defined(RTE_SPI0_SSEL_POL)
+            slaveConfig->sselPol = RTE_SPI0_SSEL_POL;
+#endif
+            break;
+
+        case 1:
+#if defined(RTE_SPI1_SSEL_POL)
+            slaveConfig->sselPol = RTE_SPI1_SSEL_POL;
+#endif
+            break;
+        case 2:
+#if defined(RTE_SPI2_SSEL_POL)
+            slaveConfig->sselPol = RTE_SPI2_SSEL_POL;
+#endif
+            break;
+
+        case 3:
+#if defined(RTE_SPI3_SSEL_POL)
+            slaveConfig->sselPol = RTE_SPI3_SSEL_POL;
+#endif
+            break;
+
+        case 4:
+#if defined(RTE_SPI4_SSEL_POL)
+            slaveConfig->sselPol = RTE_SPI4_SSEL_POL;
+#endif
+            break;
+
+        case 5:
+#if defined(RTE_SPI5_SSEL_POL)
+            slaveConfig->sselPol = RTE_SPI5_SSEL_POL;
+#endif
+            break;
+
+        case 6:
+#if defined(RTE_SPI6_SSEL_POL)
+            slaveConfig->sselPol = RTE_SPI6_SSEL_POL;
+#endif
+            break;
+
+        case 7:
+#if defined(RTE_SPI7_SSEL_POL)
+            slaveConfig->sselPol = RTE_SPI7_SSEL_POL;
+#endif
+            break;
+
+        case 8:
+#if defined(RTE_SPI8_SSEL_POL)
+            slaveConfig->sselPol = RTE_SPI8_SSEL_POL;
+#endif
+            break;
+
+        case 9:
+#if defined(RTE_SPI9_SSEL_POL)
+            slaveConfig->sselPol = RTE_SPI9_SSEL_POL;
+#endif
+            break;
+
+        case 10:
+#if defined(RTE_SPI10_SSEL_POL)
+            slaveConfig->sselPol = RTE_SPI10_SSEL_POL;
+#endif
+            break;
+
+        case 11:
+#if defined(RTE_SPI11_SSEL_POL)
+            slaveConfig->sselPol = RTE_SPI11_SSEL_POL;
+#endif
+            break;
+
+        case 12:
+#if defined(RTE_SPI12_SSEL_POL)
+            slaveConfig->sselPol = RTE_SPI12_SSEL_POL;
+#endif
+            break;
+
+        case 13:
+#if defined(RTE_SPI13_SSEL_POL)
+            slaveConfig->sselPol = RTE_SPI13_SSEL_POL;
+#endif
+            break;
+
+        default:
+            /* Avoid MISRA 16.4 violation */
+            break;
+    }
+
+    switch (control & ARM_SPI_FRAME_FORMAT_Msk)
+    {
+        case ARM_SPI_CPOL0_CPHA0:
+            slaveConfig->polarity = kSPI_ClockPolarityActiveHigh;
+            slaveConfig->phase    = kSPI_ClockPhaseFirstEdge;
+            break;
+
+        case ARM_SPI_CPOL0_CPHA1:
+            slaveConfig->polarity = kSPI_ClockPolarityActiveHigh;
+            slaveConfig->phase    = kSPI_ClockPhaseSecondEdge;
+            break;
+
+        case ARM_SPI_CPOL1_CPHA0:
+            slaveConfig->polarity = kSPI_ClockPolarityActiveLow;
+            slaveConfig->phase    = kSPI_ClockPhaseFirstEdge;
+            break;
+
+        case ARM_SPI_CPOL1_CPHA1:
+            slaveConfig->polarity = kSPI_ClockPolarityActiveLow;
+            slaveConfig->phase    = kSPI_ClockPhaseSecondEdge;
+            break;
+
+        default:
+            /* Avoid MISRA 16.4 violation */
+            break;
+    }
+    if ((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) != 0U) /* setting Number of Data bits */
+    {
+        if ((((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) >= 4U) &&
+            (((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) <= 16U))
+        {
+            slaveConfig->dataWidth =
+                (spi_data_width_t)(((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) - 1U);
+        }
+    }
+    switch (control & ARM_SPI_BIT_ORDER_Msk)
+    {
+        case ARM_SPI_LSB_MSB:
+            slaveConfig->direction = kSPI_LsbFirst;
+            break;
+        case ARM_SPI_MSB_LSB:
+            slaveConfig->direction = kSPI_MsbFirst;
+            break;
+
+        default:
+            /* Avoid MISRA 16.4 violation */
+            break;
+    }
+}
+
+static ARM_DRIVER_VERSION SPIx_GetVersion(void)
+{
+    return s_SPIDriverVersion;
+}
+
+static ARM_SPI_CAPABILITIES SPIx_GetCapabilities(void)
+{
+    return s_SPIDriverCapabilities;
+}
+
+#endif
+
+#if ((defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN) || (defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN) ||     \
+     (defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN) || (defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN) ||     \
+     (defined(RTE_SPI4_DMA_EN) && RTE_SPI4_DMA_EN) || (defined(RTE_SPI5_DMA_EN) && RTE_SPI5_DMA_EN) ||     \
+     (defined(RTE_SPI6_DMA_EN) && RTE_SPI6_DMA_EN) || (defined(RTE_SPI7_DMA_EN) && RTE_SPI7_DMA_EN) ||     \
+     (defined(RTE_SPI8_DMA_EN) && RTE_SPI8_DMA_EN) || (defined(RTE_SPI9_DMA_EN) && RTE_SPI9_DMA_EN) ||     \
+     (defined(RTE_SPI10_DMA_EN) && RTE_SPI10_DMA_EN) || (defined(RTE_SPI11_DMA_EN) && RTE_SPI11_DMA_EN) || \
+     (defined(RTE_SPI12_DMA_EN) && RTE_SPI12_DMA_EN) || (defined(RTE_SPI13_DMA_EN) && RTE_SPI13_DMA_EN))
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static void KSDK_SPI_MasterDMACallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData)
+{
+    uint32_t event = 0;
+
+    if (kStatus_Success == status)
+    {
+        event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
+    }
+
+    if (kStatus_SPI_Error == status)
+    {
+        event = ARM_SPI_EVENT_DATA_LOST;
+    }
+
+    if (userData != NULL)
+    {
+        ((ARM_SPI_SignalEvent_t)userData)(event);
+    }
+}
+static void KSDK_SPI_SlaveDMACallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData)
+{
+    uint32_t event = 0;
+
+    if (kStatus_Success == status)
+    {
+        event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
+    }
+
+    if (kStatus_SPI_Error == status)
+    {
+        event = ARM_SPI_EVENT_DATA_LOST;
+    }
+    /* User data is actually CMSIS driver callback. */
+    if (userData != NULL)
+    {
+        ((ARM_SPI_SignalEvent_t)userData)(event);
+    }
+}
+
+static int32_t SPI_DMAInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_spi_dma_driver_state_t *spi)
+{
+    if (0U == (spi->flags & (uint8_t)SPI_FLAG_INIT))
+    {
+        spi->cb_event = cb_event;
+        spi->flags    = (uint8_t)SPI_FLAG_INIT;
+    }
+    return ARM_DRIVER_OK;
+}
+
+static int32_t SPI_DMAUninitialize(cmsis_spi_dma_driver_state_t *spi)
+{
+    spi->flags = (uint8_t)SPI_FLAG_UNINIT;
+    return ARM_DRIVER_OK;
+}
+
+static int32_t SPI_DMAPowerControl(ARM_POWER_STATE state, cmsis_spi_dma_driver_state_t *spi)
+{
+    int32_t result = ARM_DRIVER_OK;
+    switch (state)
+    {
+        case ARM_POWER_OFF:
+            if ((spi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
+            {
+                SPI_Deinit(spi->resource->base);
+
+                DMA_DisableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel);
+                DMA_DisableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel);
+                DMA_Deinit(spi->dmaResource->txdmaBase);
+                DMA_Deinit(spi->dmaResource->rxdmaBase);
+
+                spi->flags = (uint8_t)SPI_FLAG_INIT;
+            }
+            break;
+        case ARM_POWER_LOW:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+
+        case ARM_POWER_FULL:
+            if (spi->flags == (uint8_t)SPI_FLAG_UNINIT)
+            {
+                return ARM_DRIVER_ERROR;
+            }
+
+            if ((spi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
+            {
+                /* Driver already powered */
+                break;
+            }
+
+            /* Enable flexcomm clock gate */
+            CLOCK_EnableClock(s_flexcommClocks[spi->resource->instance]);
+            /* Init DMA */
+            DMA_Init(spi->dmaResource->rxdmaBase);
+            DMA_Init(spi->dmaResource->txdmaBase);
+            spi->flags |= (uint8_t)SPI_FLAG_POWER;
+            break;
+        default:
+            /* Avoid MISRA 16.4 violation */
+            break;
+    }
+    return result;
+}
+
+static int32_t SPI_DMASend(const void *data, uint32_t num, cmsis_spi_dma_driver_state_t *spi)
+{
+    int32_t ret;
+    status_t status;
+    spi_transfer_t xfer        = {0};
+    spi_config_t *spi_config_p = (spi_config_t *)SPI_GetConfig(spi->resource->base);
+
+    xfer.rxData   = NULL;
+    xfer.txData   = (uint8_t *)data;
+    xfer.dataSize = num * (((uint32_t)spi_config_p->dataWidth + 8UL) / 8UL);
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        xfer.configFlags |= (uint32_t)kSPI_FrameAssert;
+    }
+
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer);
+    }
+    else
+    {
+        status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer);
+    }
+
+    switch (status)
+    {
+        case kStatus_Success:
+            ret = ARM_DRIVER_OK;
+            break;
+        case kStatus_InvalidArgument:
+            ret = ARM_DRIVER_ERROR_PARAMETER;
+            break;
+        case kStatus_SPI_Busy:
+            ret = ARM_DRIVER_ERROR_BUSY;
+            break;
+        default:
+            ret = ARM_DRIVER_ERROR;
+            break;
+    }
+
+    return ret;
+}
+
+static int32_t SPI_DMAReceive(void *data, uint32_t num, cmsis_spi_dma_driver_state_t *spi)
+{
+    int32_t ret;
+    status_t status;
+    spi_transfer_t xfer        = {0};
+    spi_config_t *spi_config_p = (spi_config_t *)SPI_GetConfig(spi->resource->base);
+
+    xfer.txData   = NULL;
+    xfer.rxData   = (uint8_t *)data;
+    xfer.dataSize = num * (((uint32_t)spi_config_p->dataWidth + 8UL) / 8UL);
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        xfer.configFlags |= (uint32_t)kSPI_FrameAssert;
+    }
+
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer);
+    }
+    else
+    {
+        status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer);
+    }
+
+    switch (status)
+    {
+        case kStatus_Success:
+            ret = ARM_DRIVER_OK;
+            break;
+        case kStatus_InvalidArgument:
+            ret = ARM_DRIVER_ERROR_PARAMETER;
+            break;
+        case kStatus_SPI_Busy:
+            ret = ARM_DRIVER_ERROR_BUSY;
+            break;
+        default:
+            ret = ARM_DRIVER_ERROR;
+            break;
+    }
+
+    return ret;
+}
+
+static int32_t SPI_DMATransfer(const void *data_out, void *data_in, uint32_t num, cmsis_spi_dma_driver_state_t *spi)
+{
+    int32_t ret;
+    status_t status;
+    spi_transfer_t xfer        = {0};
+    spi_config_t *spi_config_p = (spi_config_t *)SPI_GetConfig(spi->resource->base);
+
+    xfer.txData   = (uint8_t *)data_out;
+    xfer.rxData   = (uint8_t *)data_in;
+    xfer.dataSize = num * (((uint32_t)spi_config_p->dataWidth + 8UL) / 8UL);
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        xfer.configFlags |= (uint32_t)kSPI_FrameAssert;
+    }
+
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer);
+    }
+    else
+    {
+        status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer);
+    }
+
+    switch (status)
+    {
+        case kStatus_Success:
+            ret = ARM_DRIVER_OK;
+            break;
+        case kStatus_InvalidArgument:
+            ret = ARM_DRIVER_ERROR_PARAMETER;
+            break;
+        case kStatus_SPI_Busy:
+            ret = ARM_DRIVER_ERROR_BUSY;
+            break;
+        default:
+            ret = ARM_DRIVER_ERROR;
+            break;
+    }
+
+    return ret;
+}
+static uint32_t SPI_DMAGetCount(cmsis_spi_dma_driver_state_t *spi)
+{
+    uint32_t cnt;
+    size_t bytes;
+    spi_config_t *spi_config_p = (spi_config_t *)SPI_GetConfig(spi->resource->base);
+
+    bytes = DMA_GetRemainingBytes(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel);
+
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        cnt = spi->handle->masterHandle.transferSize - bytes;
+    }
+    else
+    {
+        cnt = spi->handle->slaveHandle.transferSize - bytes;
+    }
+    cnt /= (((uint32_t)spi_config_p->dataWidth + 8U) / 8U);
+
+    return cnt;
+}
+
+static int32_t SPI_DMAControl(uint32_t control, uint32_t arg, cmsis_spi_dma_driver_state_t *spi)
+{
+    int32_t result  = ARM_DRIVER_OK;
+    bool isContinue = false;
+    if (0U == (spi->flags & (uint8_t)SPI_FLAG_POWER))
+    {
+        return ARM_DRIVER_ERROR;
+    }
+
+    switch (control & ARM_SPI_CONTROL_Msk)
+    {
+        case ARM_SPI_MODE_INACTIVE:
+            SPI_Enable(spi->resource->base, false);
+            isContinue = true;
+            break;
+
+        case ARM_SPI_MODE_MASTER:
+            spi->baudRate_Bps = arg;
+            spi->flags |= (uint8_t)SPI_FLAG_MASTER;
+            isContinue = true;
+            break;
+
+        case ARM_SPI_MODE_SLAVE:
+            spi->flags &= ~(uint8_t)SPI_FLAG_MASTER;
+            isContinue = true;
+            break;
+
+        case ARM_SPI_SET_BUS_SPEED:
+            if (0U == (spi->flags & (uint8_t)SPI_FLAG_MASTER))
+            {
+                return ARM_DRIVER_ERROR_UNSUPPORTED;
+            }
+
+            (void)SPI_MasterSetBaud(spi->resource->base, arg, spi->resource->GetFreq());
+            spi->baudRate_Bps = arg;
+            break;
+
+        case ARM_SPI_GET_BUS_SPEED: /* Set Bus Speed in bps; arg = value */
+            if (0U == (spi->flags & (uint8_t)SPI_FLAG_MASTER))
+            {
+                return ARM_DRIVER_ERROR_UNSUPPORTED;
+            }
+            result = (int32_t)spi->baudRate_Bps;
+            break;
+
+        case ARM_SPI_CONTROL_SS:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+
+        case ARM_SPI_ABORT_TRANSFER:
+            if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+            {
+                SPI_MasterTransferAbortDMA(spi->resource->base, &spi->handle->masterHandle);
+            }
+            else
+            {
+                SPI_SlaveTransferAbortDMA(spi->resource->base, &spi->handle->slaveHandle);
+            }
+            break;
+
+        case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */
+            SPI_SetDummyData(spi->resource->base, (uint8_t)arg);
+            result = ARM_DRIVER_OK;
+            break;
+
+        case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */
+            /* Mode is not supported by current driver. */
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+
+        case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave  (Output/Input on MISO) */
+            /* Mode is not supported by current driver. */
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+
+        default:
+            isContinue = true;
+            /* Avoid MISRA 16.4 violation */
+            break;
+    }
+
+    if (!isContinue)
+    {
+        return result;
+    }
+
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        switch (control & ARM_SPI_SS_MASTER_MODE_Msk)
+        {
+            /*
+             * Note:
+             * ARM_SPI_SS_MASTER_HW_OUTPUT is default configuration in driver, if ARM_SPI_SS_MASTER_UNUSED or
+             * ARM_SPI_SS_MASTER_SW is wanted, please disable pin function in SPIx_InitPins() which is configured
+             * by user in extern file. Besides, ARM_SPI_SS_MASTER_HW_INPUT is not supported in this driver.
+             */
+            case ARM_SPI_SS_MASTER_UNUSED: /*!< SPI Slave Select when Master: Not used */
+                break;
+            case ARM_SPI_SS_MASTER_SW: /*!< SPI Slave Select when Master: Software controlled. */
+                break;
+            case ARM_SPI_SS_MASTER_HW_OUTPUT: /*!< SPI Slave Select when Master: Hardware controlled Output */
+                break;
+            case ARM_SPI_SS_MASTER_HW_INPUT: /*!< SPI Slave Select when Master: Hardware monitored Input */
+                break;
+            default:
+                /* Avoid MISRA 16.4 violation */
+                break;
+        }
+        spi_master_config_t masterConfig;
+        SPI_MasterGetDefaultConfig(&masterConfig);
+        masterConfig.baudRate_Bps = spi->baudRate_Bps;
+        SPI_MasterCommonControl(control, spi->resource, &spi->flags, &masterConfig);
+
+        if ((spi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U)
+        {
+            SPI_Deinit(spi->resource->base);
+        }
+        (void)SPI_MasterInit(spi->resource->base, &masterConfig, spi->resource->GetFreq());
+
+        DMA_EnableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel);
+        DMA_EnableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel);
+        DMA_SetChannelPriority(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel, kDMA_ChannelPriority3);
+        DMA_SetChannelPriority(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel, kDMA_ChannelPriority2);
+        DMA_CreateHandle(spi->dmaTxDataHandle, spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel);
+        DMA_CreateHandle(spi->dmaRxDataHandle, spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel);
+
+        (void)SPI_MasterTransferCreateHandleDMA(spi->resource->base, &(spi->handle->masterHandle),
+                                                KSDK_SPI_MasterDMACallback, (void *)spi->cb_event, spi->dmaTxDataHandle,
+                                                spi->dmaRxDataHandle);
+        spi->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
+    }
+    else
+    {
+        /* The SPI slave select is controlled by hardware, software mode is not supported by current driver. */
+        switch (control & ARM_SPI_SS_SLAVE_MODE_Msk)
+        {
+            case ARM_SPI_SS_SLAVE_HW:
+                break;
+            case ARM_SPI_SS_SLAVE_SW:
+                break;
+            default:
+                /* Avoid MISRA 16.4 violation */
+                break;
+        }
+
+        spi_slave_config_t slaveConfig;
+        SPI_SlaveGetDefaultConfig(&slaveConfig);
+        SPI_SlaveCommonControl(control, spi->resource, &spi->flags, &slaveConfig);
+
+        if ((spi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U)
+        {
+            SPI_Deinit(spi->resource->base);
+        }
+        (void)SPI_SlaveInit(spi->resource->base, &slaveConfig);
+
+        DMA_EnableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel);
+        DMA_EnableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel);
+        DMA_SetChannelPriority(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel, kDMA_ChannelPriority0);
+        DMA_SetChannelPriority(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel, kDMA_ChannelPriority1);
+        DMA_CreateHandle(spi->dmaTxDataHandle, spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel);
+        DMA_CreateHandle(spi->dmaRxDataHandle, spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel);
+
+        (void)SPI_SlaveTransferCreateHandleDMA(spi->resource->base, &(spi->handle->slaveHandle),
+                                               KSDK_SPI_SlaveDMACallback, (void *)spi->cb_event, spi->dmaTxDataHandle,
+                                               spi->dmaRxDataHandle);
+
+        spi->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
+    }
+
+    return ARM_DRIVER_OK;
+}
+
+static ARM_SPI_STATUS SPI_DMAGetStatus(cmsis_spi_dma_driver_state_t *spi)
+{
+    ARM_SPI_STATUS stat = {0};
+
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        stat.busy =
+            ((spi->handle->masterHandle.txInProgress == true) || (spi->handle->masterHandle.rxInProgress == true)) ?
+                (0U) :
+                (1U);
+        stat.data_lost = ((uint8_t)kStatus_SPI_Error == spi->handle->masterHandle.state) ? (1U) : (0U);
+    }
+    else
+    {
+        stat.busy =
+            ((spi->handle->slaveHandle.txInProgress == true) || (spi->handle->slaveHandle.rxInProgress == true)) ?
+                (0U) :
+                (1U);
+        stat.data_lost = ((uint8_t)kStatus_SPI_Error == spi->handle->slaveHandle.state) ? (1U) : (0U);
+    }
+    stat.mode_fault = 0U;
+    stat.reserved   = 0U;
+
+    return stat;
+}
+#endif /* defined(FSL_FEATURE_SOC_DMA_COUNT) */
+
+#endif
+
+#if ((defined(RTE_SPI0) && RTE_SPI0 && !(defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN)) ||     \
+     (defined(RTE_SPI1) && RTE_SPI1 && !(defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN)) ||     \
+     (defined(RTE_SPI2) && RTE_SPI2 && !(defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN)) ||     \
+     (defined(RTE_SPI3) && RTE_SPI3 && !(defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN)) ||     \
+     (defined(RTE_SPI4) && RTE_SPI4 && !(defined(RTE_SPI4_DMA_EN) && RTE_SPI4_DMA_EN)) ||     \
+     (defined(RTE_SPI5) && RTE_SPI5 && !(defined(RTE_SPI5_DMA_EN) && RTE_SPI5_DMA_EN)) ||     \
+     (defined(RTE_SPI6) && RTE_SPI6 && !(defined(RTE_SPI6_DMA_EN) && RTE_SPI6_DMA_EN)) ||     \
+     (defined(RTE_SPI7) && RTE_SPI7 && !(defined(RTE_SPI7_DMA_EN) && RTE_SPI7_DMA_EN)) ||     \
+     (defined(RTE_SPI8) && RTE_SPI8 && !(defined(RTE_SPI8_DMA_EN) && RTE_SPI8_DMA_EN)) ||     \
+     (defined(RTE_SPI9) && RTE_SPI9 && !(defined(RTE_SPI9_DMA_EN) && RTE_SPI9_DMA_EN)) ||     \
+     (defined(RTE_SPI10) && RTE_SPI10 && !(defined(RTE_SPI10_DMA_EN) && RTE_SPI10_DMA_EN)) || \
+     (defined(RTE_SPI11) && RTE_SPI11 && !(defined(RTE_SPI11_DMA_EN) && RTE_SPI11_DMA_EN)) || \
+     (defined(RTE_SPI12) && RTE_SPI12 && !(defined(RTE_SPI12_DMA_EN) && RTE_SPI12_DMA_EN)) || \
+     (defined(RTE_SPI13) && RTE_SPI13 && !(defined(RTE_SPI13_DMA_EN) && RTE_SPI13_DMA_EN)))
+
+static void KSDK_SPI_MasterInterruptCallback(SPI_Type *base,
+                                             spi_master_handle_t *handle,
+                                             status_t status,
+                                             void *userData)
+{
+    uint32_t event = 0;
+
+    if ((kStatus_Success == status) || (kStatus_SPI_Idle == status))
+    {
+        event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
+    }
+
+    if (kStatus_SPI_Error == status)
+    {
+        event = ARM_SPI_EVENT_DATA_LOST;
+    }
+
+    /* User data is actually CMSIS driver callback. */
+    if (userData != NULL)
+    {
+        ((ARM_SPI_SignalEvent_t)userData)(event);
+    }
+}
+
+static void KSDK_SPI_SlaveInterruptCallback(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData)
+{
+    uint32_t event = 0;
+
+    if ((kStatus_Success == status) || (kStatus_SPI_Idle == status))
+    {
+        event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
+    }
+
+    if (kStatus_SPI_Error == status)
+    {
+        event = ARM_SPI_EVENT_DATA_LOST;
+    }
+
+    /* User data is actually CMSIS driver callback. */
+    if (userData != NULL)
+    {
+        ((ARM_SPI_SignalEvent_t)userData)(event);
+    }
+}
+
+static int32_t SPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_spi_interrupt_driver_state_t *spi)
+{
+    if (0U == (spi->flags & (uint8_t)SPI_FLAG_INIT))
+    {
+        spi->cb_event = cb_event;
+        spi->flags    = (uint8_t)SPI_FLAG_INIT;
+    }
+
+    return ARM_DRIVER_OK;
+}
+
+static int32_t SPI_InterruptUninitialize(cmsis_spi_interrupt_driver_state_t *spi)
+{
+    spi->flags = (uint8_t)SPI_FLAG_UNINIT;
+    return ARM_DRIVER_OK;
+}
+
+static int32_t SPI_InterruptPowerControl(ARM_POWER_STATE state, cmsis_spi_interrupt_driver_state_t *spi)
+{
+    int32_t result = ARM_DRIVER_OK;
+    switch (state)
+    {
+        case ARM_POWER_OFF:
+            if ((spi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
+            {
+                SPI_Deinit(spi->resource->base);
+                spi->flags = (uint8_t)SPI_FLAG_INIT;
+            }
+            break;
+
+        case ARM_POWER_LOW:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+
+        case ARM_POWER_FULL:
+            if (spi->flags == (uint8_t)SPI_FLAG_UNINIT)
+            {
+                return ARM_DRIVER_ERROR;
+            }
+
+            if ((spi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
+            {
+                /* Driver already powered */
+                break;
+            }
+
+            /* Enable flexcomm clock gate */
+            CLOCK_EnableClock(s_flexcommClocks[spi->resource->instance]);
+            spi->flags |= (uint8_t)SPI_FLAG_POWER;
+            break;
+        default:
+            /* Avoid MISRA 16.4 violation */
+            break;
+    }
+
+    return result;
+}
+
+static int32_t SPI_InterruptSend(const void *data, uint32_t num, cmsis_spi_interrupt_driver_state_t *spi)
+{
+    int32_t ret;
+    status_t status;
+    spi_transfer_t xfer = {0};
+
+    xfer.rxData = NULL;
+    xfer.txData = (uint8_t *)data;
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        xfer.configFlags |= (uint32_t)kSPI_FrameAssert;
+    }
+
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        xfer.dataSize = num * (((uint32_t)spi->handle->masterHandle.dataWidth + 8UL) / 8UL);
+        status        = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer);
+    }
+    else
+    {
+        xfer.dataSize = num * (((uint32_t)spi->handle->slaveHandle.dataWidth + 8UL) / 8UL);
+        status        = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer);
+    }
+
+    switch (status)
+    {
+        case kStatus_Success:
+            ret = ARM_DRIVER_OK;
+            break;
+        case kStatus_InvalidArgument:
+            ret = ARM_DRIVER_ERROR_PARAMETER;
+            break;
+        case kStatus_SPI_Busy:
+            ret = ARM_DRIVER_ERROR_BUSY;
+            break;
+        default:
+            ret = ARM_DRIVER_ERROR;
+            break;
+    }
+
+    return ret;
+}
+
+static int32_t SPI_InterruptReceive(void *data, uint32_t num, cmsis_spi_interrupt_driver_state_t *spi)
+{
+    int32_t ret;
+    status_t status;
+    spi_transfer_t xfer = {0};
+
+    xfer.txData = NULL;
+    xfer.rxData = (uint8_t *)data;
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        xfer.configFlags |= (uint32_t)kSPI_FrameAssert;
+    }
+
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        xfer.dataSize = num * (((uint32_t)spi->handle->masterHandle.dataWidth + 8UL) / 8UL);
+        status        = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer);
+    }
+    else
+    {
+        xfer.dataSize = num * (((uint32_t)spi->handle->slaveHandle.dataWidth + 8UL) / 8UL);
+        status        = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer);
+    }
+
+    switch (status)
+    {
+        case kStatus_Success:
+            ret = ARM_DRIVER_OK;
+            break;
+        case kStatus_InvalidArgument:
+            ret = ARM_DRIVER_ERROR_PARAMETER;
+            break;
+        case kStatus_SPI_Busy:
+            ret = ARM_DRIVER_ERROR_BUSY;
+            break;
+        default:
+            ret = ARM_DRIVER_ERROR;
+            break;
+    }
+
+    return ret;
+}
+
+static int32_t SPI_InterruptTransfer(const void *data_out,
+                                     void *data_in,
+                                     uint32_t num,
+                                     cmsis_spi_interrupt_driver_state_t *spi)
+{
+    int32_t ret;
+    status_t status;
+    spi_transfer_t xfer = {0};
+
+    xfer.txData = (uint8_t *)data_out;
+    xfer.rxData = (uint8_t *)data_in;
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        xfer.configFlags |= (uint32_t)kSPI_FrameAssert;
+    }
+
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        xfer.dataSize = num * (((uint32_t)spi->handle->masterHandle.dataWidth + 8UL) / 8UL);
+        status        = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer);
+    }
+    else
+    {
+        xfer.dataSize = num * (((uint32_t)spi->handle->slaveHandle.dataWidth + 8UL) / 8UL);
+        status        = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer);
+    }
+
+    switch (status)
+    {
+        case kStatus_Success:
+            ret = ARM_DRIVER_OK;
+            break;
+        case kStatus_InvalidArgument:
+            ret = ARM_DRIVER_ERROR_PARAMETER;
+            break;
+        case kStatus_SPI_Busy:
+            ret = ARM_DRIVER_ERROR_BUSY;
+            break;
+        default:
+            ret = ARM_DRIVER_ERROR;
+            break;
+    }
+
+    return ret;
+}
+static uint32_t SPI_InterruptGetCount(cmsis_spi_interrupt_driver_state_t *spi)
+{
+    uint32_t cnt;
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        cnt = spi->handle->masterHandle.totalByteCount - spi->handle->masterHandle.rxRemainingBytes;
+        cnt /= (((uint32_t)spi->handle->masterHandle.dataWidth + 8UL) / 8UL);
+    }
+    else
+    {
+        cnt = spi->handle->slaveHandle.totalByteCount - spi->handle->slaveHandle.rxRemainingBytes;
+        cnt /= (((uint32_t)spi->handle->slaveHandle.dataWidth + 8UL) / 8UL);
+    }
+
+    return cnt;
+}
+
+static int32_t SPI_InterruptControl(uint32_t control, uint32_t arg, cmsis_spi_interrupt_driver_state_t *spi)
+{
+    int32_t result  = ARM_DRIVER_OK;
+    bool isContinue = false;
+    if (0U == (spi->flags & (uint8_t)SPI_FLAG_POWER))
+    {
+        return ARM_DRIVER_ERROR;
+    }
+
+    switch (control & ARM_SPI_CONTROL_Msk)
+    {
+        case ARM_SPI_MODE_INACTIVE: /* SPI mode Inactive */
+            (void)FLEXCOMM_Init(spi->resource->base, FLEXCOMM_PERIPH_NONE);
+            isContinue = true;
+            break;
+
+        case ARM_SPI_MODE_MASTER: /* SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps */
+            spi->baudRate_Bps = arg;
+            spi->flags |= (uint8_t)SPI_FLAG_MASTER;
+            isContinue = true;
+            break;
+
+        case ARM_SPI_MODE_SLAVE: /* SPI Slave  (Output on MISO, Input on MOSI) */
+            spi->flags &= ~(uint8_t)SPI_FLAG_MASTER;
+            isContinue = true;
+            break;
+
+        case ARM_SPI_GET_BUS_SPEED: /* Get Bus Speed in bps */
+            if (0U == (spi->flags & (uint8_t)SPI_FLAG_MASTER))
+            {
+                return ARM_DRIVER_ERROR_UNSUPPORTED;
+            }
+            result = (int32_t)spi->baudRate_Bps;
+            break;
+
+        case ARM_SPI_SET_BUS_SPEED: /* Set Bus Speed in bps; */
+            if (0U == (spi->flags & (uint8_t)SPI_FLAG_MASTER))
+            {
+                return ARM_DRIVER_ERROR_UNSUPPORTED;
+            }
+            (void)SPI_MasterSetBaud(spi->resource->base, arg, spi->resource->GetFreq());
+            spi->baudRate_Bps = arg;
+            break;
+
+        case ARM_SPI_CONTROL_SS:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+
+        case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */
+            if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+            {
+                SPI_MasterTransferAbort(spi->resource->base, &spi->handle->masterHandle);
+            }
+            else
+            {
+                SPI_SlaveTransferAbort(spi->resource->base, &spi->handle->slaveHandle);
+            }
+            break;
+
+        case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */
+            SPI_SetDummyData(spi->resource->base, (uint8_t)arg);
+            break;
+
+        case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */
+            /* Mode is not supported by current driver. */
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+
+        case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave  (Output/Input on MISO) */
+            /* Mode is not supported by current driver. */
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+
+        default:
+            isContinue = true;
+            /* Avoid MISRA 16.4 violation */
+            break;
+    }
+
+    if (!isContinue)
+    {
+        return result;
+    }
+
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        switch (control & ARM_SPI_SS_MASTER_MODE_Msk)
+        {
+            /*
+             * Note:
+             * ARM_SPI_SS_MASTER_HW_OUTPUT is default configuration in driver, if ARM_SPI_SS_MASTER_UNUSED or
+             * ARM_SPI_SS_MASTER_SW is wanted, please disable pin function in SPIx_InitPins() which is configured
+             * by user in extern file. Besides ARM_SPI_SS_MASTER_HW_INPUT is not supported in this driver.
+             */
+            case ARM_SPI_SS_MASTER_UNUSED: /*!< SPI Slave Select when Master: Not used */
+                break;
+            case ARM_SPI_SS_MASTER_SW: /*!< SPI Slave Select when Master: Software controlled. */
+                break;
+            case ARM_SPI_SS_MASTER_HW_OUTPUT: /*!< SPI Slave Select when Master: Hardware controlled Output */
+                break;
+            case ARM_SPI_SS_MASTER_HW_INPUT: /*!< SPI Slave Select when Master: Hardware monitored Input */
+                break;
+            default:
+                /* Avoid MISRA 16.4 violation */
+                break;
+        }
+
+        spi_master_config_t masterConfig;
+        SPI_MasterGetDefaultConfig(&masterConfig);
+        masterConfig.baudRate_Bps = spi->baudRate_Bps;
+
+        SPI_MasterCommonControl(control, spi->resource, &spi->flags, &masterConfig);
+
+        if ((spi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U)
+        {
+            SPI_Deinit(spi->resource->base);
+        }
+        (void)SPI_MasterInit(spi->resource->base, &masterConfig, spi->resource->GetFreq());
+        (void)SPI_MasterTransferCreateHandle(spi->resource->base, &spi->handle->masterHandle,
+                                             KSDK_SPI_MasterInterruptCallback, (void *)spi->cb_event);
+        spi->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
+    }
+    else
+    {
+        /* The SPI slave select is controlled by hardware, software mode is not supported by current driver. */
+        switch (control & ARM_SPI_SS_SLAVE_MODE_Msk)
+        {
+            case ARM_SPI_SS_SLAVE_HW:
+                break;
+            case ARM_SPI_SS_SLAVE_SW:
+                break;
+            default:
+                /* Avoid MISRA 16.4 violation */
+                break;
+        }
+
+        spi_slave_config_t slaveConfig;
+        SPI_SlaveGetDefaultConfig(&slaveConfig);
+
+        SPI_SlaveCommonControl(control, spi->resource, &spi->flags, &slaveConfig);
+
+        if ((spi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U)
+        {
+            SPI_Deinit(spi->resource->base);
+        }
+        (void)SPI_SlaveInit(spi->resource->base, &slaveConfig);
+        (void)SPI_SlaveTransferCreateHandle(spi->resource->base, &spi->handle->slaveHandle,
+                                            KSDK_SPI_SlaveInterruptCallback, (void *)spi->cb_event);
+        spi->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
+    }
+
+    return ARM_DRIVER_OK;
+}
+
+static ARM_SPI_STATUS SPI_InterruptGetStatus(cmsis_spi_interrupt_driver_state_t *spi)
+{
+    ARM_SPI_STATUS stat = {0};
+
+    if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
+    {
+        stat.busy =
+            ((spi->handle->masterHandle.txRemainingBytes > 0U) || (spi->handle->masterHandle.rxRemainingBytes > 0U)) ?
+                (0U) :
+                (1U);
+        stat.data_lost = ((uint8_t)kStatus_SPI_Error == spi->handle->masterHandle.state) ? (1U) : (0U);
+    }
+    else
+    {
+        stat.busy =
+            ((spi->handle->slaveHandle.txRemainingBytes > 0U) || (spi->handle->slaveHandle.rxRemainingBytes > 0U)) ?
+                (0U) :
+                (1U);
+        stat.data_lost = ((uint8_t)kStatus_SPI_Error == spi->handle->slaveHandle.state) ? (1U) : (0U);
+    }
+    stat.mode_fault = 0U;
+    stat.reserved   = 0U;
+
+    return stat;
+}
+
+#endif
+
+#if defined(SPI0) && defined(RTE_SPI0) && RTE_SPI0
+
+/* User needs to provide the implementation for SPI0_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t SPI0_GetFreq(void);
+
+static cmsis_spi_resource_t SPI0_Resource = {SPI0, 0, SPI0_GetFreq};
+
+#if defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_spi_dma_resource_t SPI0_DMAResource = {RTE_SPI0_DMA_TX_DMA_BASE, RTE_SPI0_DMA_TX_CH,
+                                                    RTE_SPI0_DMA_RX_DMA_BASE, RTE_SPI0_DMA_RX_CH};
+
+static cmsis_spi_dma_handle_t SPI0_DmaHandle;
+static dma_handle_t SPI0_DmaTxDataHandle;
+static dma_handle_t SPI0_DmaRxDataHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi0_dma_driver_state")
+static cmsis_spi_dma_driver_state_t SPI0_DMADriverState = {
+#else
+static cmsis_spi_dma_driver_state_t SPI0_DMADriverState  = {
+#endif
+    &SPI0_Resource, &SPI0_DMAResource, &SPI0_DmaHandle, &SPI0_DmaTxDataHandle, &SPI0_DmaRxDataHandle,
+
+};
+
+static int32_t SPI0_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI0_PIN_INIT
+    RTE_SPI0_PIN_INIT();
+#endif
+    return SPI_DMAInitialize(cb_event, &SPI0_DMADriverState);
+}
+
+static int32_t SPI0_DMAUninitialize(void)
+{
+#ifdef RTE_SPI0_PIN_DEINIT
+    RTE_SPI0_PIN_DEINIT();
+#endif
+    return SPI_DMAUninitialize(&SPI0_DMADriverState);
+}
+
+static int32_t SPI0_DMAPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_DMAPowerControl(state, &SPI0_DMADriverState);
+}
+
+static int32_t SPI0_DMASend(const void *data, uint32_t num)
+{
+    return SPI_DMASend(data, num, &SPI0_DMADriverState);
+}
+
+static int32_t SPI0_DMAReceive(void *data, uint32_t num)
+{
+    return SPI_DMAReceive(data, num, &SPI0_DMADriverState);
+}
+
+static int32_t SPI0_DMATransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_DMATransfer(data_out, data_in, num, &SPI0_DMADriverState);
+}
+
+static uint32_t SPI0_DMAGetCount(void)
+{
+    return SPI_DMAGetCount(&SPI0_DMADriverState);
+}
+
+static int32_t SPI0_DMAControl(uint32_t control, uint32_t arg)
+{
+    return SPI_DMAControl(control, arg, &SPI0_DMADriverState);
+}
+
+static ARM_SPI_STATUS SPI0_DMAGetStatus(void)
+{
+    return SPI_DMAGetStatus(&SPI0_DMADriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_spi_handle_t SPI0_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi0_interrupt_driver_state")
+static cmsis_spi_interrupt_driver_state_t SPI0_InterruptDriverState = {
+#else
+static cmsis_spi_interrupt_driver_state_t SPI0_InterruptDriverState  = {
+#endif
+    &SPI0_Resource,
+    &SPI0_Handle,
+};
+
+static int32_t SPI0_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI0_PIN_INIT
+    RTE_SPI0_PIN_INIT();
+#endif
+    return SPI_InterruptInitialize(cb_event, &SPI0_InterruptDriverState);
+}
+
+static int32_t SPI0_InterruptUninitialize(void)
+{
+#ifdef RTE_SPI0_PIN_DEINIT
+    RTE_SPI0_PIN_DEINIT();
+#endif
+    return SPI_InterruptUninitialize(&SPI0_InterruptDriverState);
+}
+
+static int32_t SPI0_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_InterruptPowerControl(state, &SPI0_InterruptDriverState);
+}
+
+static int32_t SPI0_InterruptSend(const void *data, uint32_t num)
+{
+    return SPI_InterruptSend(data, num, &SPI0_InterruptDriverState);
+}
+
+static int32_t SPI0_InterruptReceive(void *data, uint32_t num)
+{
+    return SPI_InterruptReceive(data, num, &SPI0_InterruptDriverState);
+}
+
+static int32_t SPI0_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_InterruptTransfer(data_out, data_in, num, &SPI0_InterruptDriverState);
+}
+
+static uint32_t SPI0_InterruptGetCount(void)
+{
+    return SPI_InterruptGetCount(&SPI0_InterruptDriverState);
+}
+
+static int32_t SPI0_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return SPI_InterruptControl(control, arg, &SPI0_InterruptDriverState);
+}
+
+static ARM_SPI_STATUS SPI0_InterruptGetStatus(void)
+{
+    return SPI_InterruptGetStatus(&SPI0_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_SPI Driver_SPI0 = {SPIx_GetVersion,    SPIx_GetCapabilities,
+#if defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN
+                              SPI0_DMAInitialize, SPI0_DMAUninitialize, SPI0_DMAPowerControl, SPI0_DMASend,
+                              SPI0_DMAReceive,    SPI0_DMATransfer,     SPI0_DMAGetCount,     SPI0_DMAControl,
+                              SPI0_DMAGetStatus
+#else
+                              SPI0_InterruptInitialize,
+                              SPI0_InterruptUninitialize,
+                              SPI0_InterruptPowerControl,
+                              SPI0_InterruptSend,
+                              SPI0_InterruptReceive,
+                              SPI0_InterruptTransfer,
+                              SPI0_InterruptGetCount,
+                              SPI0_InterruptControl,
+                              SPI0_InterruptGetStatus
+#endif
+};
+
+#endif /*  SPI0  */
+
+#if defined(SPI1) && defined(RTE_SPI1) && RTE_SPI1
+/* User needs to provide the implementation for SPI1_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t SPI1_GetFreq(void);
+static cmsis_spi_resource_t SPI1_Resource = {SPI1, 1, SPI1_GetFreq};
+
+#if defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_spi_dma_resource_t SPI1_DMAResource = {RTE_SPI1_DMA_TX_DMA_BASE, RTE_SPI1_DMA_TX_CH,
+                                                    RTE_SPI1_DMA_RX_DMA_BASE, RTE_SPI1_DMA_RX_CH};
+
+static cmsis_spi_dma_handle_t SPI1_DmaHandle;
+static dma_handle_t SPI1_DmaTxDataHandle;
+static dma_handle_t SPI1_DmaRxDataHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi1_dma_driver_state")
+static cmsis_spi_dma_driver_state_t SPI1_DMADriverState = {
+#else
+static cmsis_spi_dma_driver_state_t SPI1_DMADriverState  = {
+#endif
+    &SPI1_Resource, &SPI1_DMAResource, &SPI1_DmaHandle, &SPI1_DmaRxDataHandle, &SPI1_DmaTxDataHandle,
+};
+
+static int32_t SPI1_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI1_PIN_INIT
+    RTE_SPI1_PIN_INIT();
+#endif
+    return SPI_DMAInitialize(cb_event, &SPI1_DMADriverState);
+}
+
+static int32_t SPI1_DMAUninitialize(void)
+{
+#ifdef RTE_SPI1_PIN_DEINIT
+    RTE_SPI1_PIN_DEINIT();
+#endif
+    return SPI_DMAUninitialize(&SPI1_DMADriverState);
+}
+
+static int32_t SPI1_DMAPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_DMAPowerControl(state, &SPI1_DMADriverState);
+}
+
+static int32_t SPI1_DMASend(const void *data, uint32_t num)
+{
+    return SPI_DMASend(data, num, &SPI1_DMADriverState);
+}
+
+static int32_t SPI1_DMAReceive(void *data, uint32_t num)
+{
+    return SPI_DMAReceive(data, num, &SPI1_DMADriverState);
+}
+
+static int32_t SPI1_DMATransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_DMATransfer(data_out, data_in, num, &SPI1_DMADriverState);
+}
+
+static uint32_t SPI1_DMAGetCount(void)
+{
+    return SPI_DMAGetCount(&SPI1_DMADriverState);
+}
+
+static int32_t SPI1_DMAControl(uint32_t control, uint32_t arg)
+{
+    return SPI_DMAControl(control, arg, &SPI1_DMADriverState);
+}
+
+static ARM_SPI_STATUS SPI1_DMAGetStatus(void)
+{
+    return SPI_DMAGetStatus(&SPI1_DMADriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_spi_handle_t SPI1_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi1_interrupt_driver_state")
+static cmsis_spi_interrupt_driver_state_t SPI1_InterruptDriverState = {
+#else
+static cmsis_spi_interrupt_driver_state_t SPI1_InterruptDriverState  = {
+#endif
+    &SPI1_Resource,
+    &SPI1_Handle,
+};
+
+static int32_t SPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI1_PIN_INIT
+    RTE_SPI1_PIN_INIT();
+#endif
+    return SPI_InterruptInitialize(cb_event, &SPI1_InterruptDriverState);
+}
+
+static int32_t SPI1_InterruptUninitialize(void)
+{
+#ifdef RTE_SPI1_PIN_DEINIT
+    RTE_SPI1_PIN_DEINIT();
+#endif
+    return SPI_InterruptUninitialize(&SPI1_InterruptDriverState);
+}
+
+static int32_t SPI1_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_InterruptPowerControl(state, &SPI1_InterruptDriverState);
+}
+
+static int32_t SPI1_InterruptSend(const void *data, uint32_t num)
+{
+    return SPI_InterruptSend(data, num, &SPI1_InterruptDriverState);
+}
+
+static int32_t SPI1_InterruptReceive(void *data, uint32_t num)
+{
+    return SPI_InterruptReceive(data, num, &SPI1_InterruptDriverState);
+}
+
+static int32_t SPI1_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_InterruptTransfer(data_out, data_in, num, &SPI1_InterruptDriverState);
+}
+
+static uint32_t SPI1_InterruptGetCount(void)
+{
+    return SPI_InterruptGetCount(&SPI1_InterruptDriverState);
+}
+
+static int32_t SPI1_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return SPI_InterruptControl(control, arg, &SPI1_InterruptDriverState);
+}
+
+static ARM_SPI_STATUS SPI1_InterruptGetStatus(void)
+{
+    return SPI_InterruptGetStatus(&SPI1_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_SPI Driver_SPI1 = {SPIx_GetVersion,    SPIx_GetCapabilities,
+#if defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN
+                              SPI1_DMAInitialize, SPI1_DMAUninitialize, SPI1_DMAPowerControl, SPI1_DMASend,
+                              SPI1_DMAReceive,    SPI1_DMATransfer,     SPI1_DMAGetCount,     SPI1_DMAControl,
+                              SPI1_DMAGetStatus
+#else
+                              SPI1_InterruptInitialize,
+                              SPI1_InterruptUninitialize,
+                              SPI1_InterruptPowerControl,
+                              SPI1_InterruptSend,
+                              SPI1_InterruptReceive,
+                              SPI1_InterruptTransfer,
+                              SPI1_InterruptGetCount,
+                              SPI1_InterruptControl,
+                              SPI1_InterruptGetStatus
+#endif
+};
+
+#endif /*  SPI1  */
+
+#if defined(SPI2) && defined(RTE_SPI2) && RTE_SPI2
+
+/* User needs to provide the implementation for SPI2_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t SPI2_GetFreq(void);
+
+static cmsis_spi_resource_t SPI2_Resource = {SPI2, 2, SPI2_GetFreq};
+
+#if defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_spi_dma_resource_t SPI2_DMAResource = {RTE_SPI2_DMA_TX_DMA_BASE, RTE_SPI2_DMA_TX_CH,
+                                                    RTE_SPI2_DMA_RX_DMA_BASE, RTE_SPI2_DMA_RX_CH};
+
+static cmsis_spi_dma_handle_t SPI2_DmaHandle;
+static dma_handle_t SPI2_DmaTxDataHandle;
+static dma_handle_t SPI2_DmaRxDataHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi2_dma_driver_state")
+static cmsis_spi_dma_driver_state_t SPI2_DMADriverState = {
+#else
+static cmsis_spi_dma_driver_state_t SPI2_DMADriverState  = {
+#endif
+    &SPI2_Resource, &SPI2_DMAResource, &SPI2_DmaHandle, &SPI2_DmaRxDataHandle, &SPI2_DmaTxDataHandle,
+};
+
+static int32_t SPI2_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI2_PIN_INIT
+    RTE_SPI2_PIN_INIT();
+#endif
+    return SPI_DMAInitialize(cb_event, &SPI2_DMADriverState);
+}
+
+static int32_t SPI2_DMAUninitialize(void)
+{
+#ifdef RTE_SPI2_PIN_DEINIT
+    RTE_SPI2_PIN_DEINIT();
+#endif
+    return SPI_DMAUninitialize(&SPI2_DMADriverState);
+}
+
+static int32_t SPI2_DMAPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_DMAPowerControl(state, &SPI2_DMADriverState);
+}
+
+static int32_t SPI2_DMASend(const void *data, uint32_t num)
+{
+    return SPI_DMASend(data, num, &SPI2_DMADriverState);
+}
+
+static int32_t SPI2_DMAReceive(void *data, uint32_t num)
+{
+    return SPI_DMAReceive(data, num, &SPI2_DMADriverState);
+}
+
+static int32_t SPI2_DMATransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_DMATransfer(data_out, data_in, num, &SPI2_DMADriverState);
+}
+
+static uint32_t SPI2_DMAGetCount(void)
+{
+    return SPI_DMAGetCount(&SPI2_DMADriverState);
+}
+
+static int32_t SPI2_DMAControl(uint32_t control, uint32_t arg)
+{
+    return SPI_DMAControl(control, arg, &SPI2_DMADriverState);
+}
+
+static ARM_SPI_STATUS SPI2_DMAGetStatus(void)
+{
+    return SPI_DMAGetStatus(&SPI2_DMADriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_spi_handle_t SPI2_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi2_interrupt_driver_state")
+static cmsis_spi_interrupt_driver_state_t SPI2_InterruptDriverState = {
+#else
+static cmsis_spi_interrupt_driver_state_t SPI2_InterruptDriverState  = {
+#endif
+    &SPI2_Resource,
+    &SPI2_Handle,
+};
+
+static int32_t SPI2_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI2_PIN_INIT
+    RTE_SPI2_PIN_INIT();
+#endif
+    return SPI_InterruptInitialize(cb_event, &SPI2_InterruptDriverState);
+}
+
+static int32_t SPI2_InterruptUninitialize(void)
+{
+#ifdef RTE_SPI2_PIN_DEINIT
+    RTE_SPI2_PIN_DEINIT();
+#endif
+    return SPI_InterruptUninitialize(&SPI2_InterruptDriverState);
+}
+
+static int32_t SPI2_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_InterruptPowerControl(state, &SPI2_InterruptDriverState);
+}
+
+static int32_t SPI2_InterruptSend(const void *data, uint32_t num)
+{
+    return SPI_InterruptSend(data, num, &SPI2_InterruptDriverState);
+}
+
+static int32_t SPI2_InterruptReceive(void *data, uint32_t num)
+{
+    return SPI_InterruptReceive(data, num, &SPI2_InterruptDriverState);
+}
+
+static int32_t SPI2_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_InterruptTransfer(data_out, data_in, num, &SPI2_InterruptDriverState);
+}
+
+static uint32_t SPI2_InterruptGetCount(void)
+{
+    return SPI_InterruptGetCount(&SPI2_InterruptDriverState);
+}
+
+static int32_t SPI2_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return SPI_InterruptControl(control, arg, &SPI2_InterruptDriverState);
+}
+
+static ARM_SPI_STATUS SPI2_InterruptGetStatus(void)
+{
+    return SPI_InterruptGetStatus(&SPI2_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_SPI Driver_SPI2 = {SPIx_GetVersion,    SPIx_GetCapabilities,
+#if defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN
+                              SPI2_DMAInitialize, SPI2_DMAUninitialize, SPI2_DMAPowerControl, SPI2_DMASend,
+                              SPI2_DMAReceive,    SPI2_DMATransfer,     SPI2_DMAGetCount,     SPI2_DMAControl,
+                              SPI2_DMAGetStatus
+#else
+                              SPI2_InterruptInitialize,
+                              SPI2_InterruptUninitialize,
+                              SPI2_InterruptPowerControl,
+                              SPI2_InterruptSend,
+                              SPI2_InterruptReceive,
+                              SPI2_InterruptTransfer,
+                              SPI2_InterruptGetCount,
+                              SPI2_InterruptControl,
+                              SPI2_InterruptGetStatus
+#endif
+};
+
+#endif /*  SPI2  */
+
+#if defined(SPI3) && defined(RTE_SPI3) && RTE_SPI3
+
+/* User needs to provide the implementation for SPI3_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t SPI3_GetFreq(void);
+
+static cmsis_spi_resource_t SPI3_Resource = {SPI3, 3, SPI3_GetFreq};
+
+#if defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_spi_dma_resource_t SPI3_DMAResource = {RTE_SPI3_DMA_TX_DMA_BASE, RTE_SPI3_DMA_TX_CH,
+                                                    RTE_SPI3_DMA_RX_DMA_BASE, RTE_SPI3_DMA_RX_CH};
+
+static cmsis_spi_dma_handle_t SPI3_DmaHandle;
+static dma_handle_t SPI3_DmaTxDataHandle;
+static dma_handle_t SPI3_DmaRxDataHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi3_dma_driver_state")
+static cmsis_spi_dma_driver_state_t SPI3_DMADriverState = {
+#else
+static cmsis_spi_dma_driver_state_t SPI3_DMADriverState  = {
+#endif
+    &SPI3_Resource, &SPI3_DMAResource, &SPI3_DmaHandle, &SPI3_DmaRxDataHandle, &SPI3_DmaTxDataHandle,
+};
+
+static int32_t SPI3_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI3_PIN_INIT
+    RTE_SPI3_PIN_INIT();
+#endif
+    return SPI_DMAInitialize(cb_event, &SPI3_DMADriverState);
+}
+
+static int32_t SPI3_DMAUninitialize(void)
+{
+#ifdef RTE_SPI3_PIN_DEINIT
+    RTE_SPI3_PIN_DEINIT();
+#endif
+    return SPI_DMAUninitialize(&SPI3_DMADriverState);
+}
+
+static int32_t SPI3_DMAPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_DMAPowerControl(state, &SPI3_DMADriverState);
+}
+
+static int32_t SPI3_DMASend(const void *data, uint32_t num)
+{
+    return SPI_DMASend(data, num, &SPI3_DMADriverState);
+}
+
+static int32_t SPI3_DMAReceive(void *data, uint32_t num)
+{
+    return SPI_DMAReceive(data, num, &SPI3_DMADriverState);
+}
+
+static int32_t SPI3_DMATransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_DMATransfer(data_out, data_in, num, &SPI3_DMADriverState);
+}
+
+static uint32_t SPI3_DMAGetCount(void)
+{
+    return SPI_DMAGetCount(&SPI3_DMADriverState);
+}
+
+static int32_t SPI3_DMAControl(uint32_t control, uint32_t arg)
+{
+    return SPI_DMAControl(control, arg, &SPI3_DMADriverState);
+}
+
+static ARM_SPI_STATUS SPI3_DMAGetStatus(void)
+{
+    return SPI_DMAGetStatus(&SPI3_DMADriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_spi_handle_t SPI3_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi3_interrupt_driver_state")
+static cmsis_spi_interrupt_driver_state_t SPI3_InterruptDriverState = {
+#else
+static cmsis_spi_interrupt_driver_state_t SPI3_InterruptDriverState  = {
+#endif
+    &SPI3_Resource,
+    &SPI3_Handle,
+};
+
+static int32_t SPI3_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI3_PIN_INIT
+    RTE_SPI3_PIN_INIT();
+#endif
+    return SPI_InterruptInitialize(cb_event, &SPI3_InterruptDriverState);
+}
+
+static int32_t SPI3_InterruptUninitialize(void)
+{
+#ifdef RTE_SPI3_PIN_DEINIT
+    RTE_SPI3_PIN_DEINIT();
+#endif
+    return SPI_InterruptUninitialize(&SPI3_InterruptDriverState);
+}
+
+static int32_t SPI3_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_InterruptPowerControl(state, &SPI3_InterruptDriverState);
+}
+
+static int32_t SPI3_InterruptSend(const void *data, uint32_t num)
+{
+    return SPI_InterruptSend(data, num, &SPI3_InterruptDriverState);
+}
+
+static int32_t SPI3_InterruptReceive(void *data, uint32_t num)
+{
+    return SPI_InterruptReceive(data, num, &SPI3_InterruptDriverState);
+}
+
+static int32_t SPI3_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_InterruptTransfer(data_out, data_in, num, &SPI3_InterruptDriverState);
+}
+
+static uint32_t SPI3_InterruptGetCount(void)
+{
+    return SPI_InterruptGetCount(&SPI3_InterruptDriverState);
+}
+
+static int32_t SPI3_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return SPI_InterruptControl(control, arg, &SPI3_InterruptDriverState);
+}
+
+static ARM_SPI_STATUS SPI3_InterruptGetStatus(void)
+{
+    return SPI_InterruptGetStatus(&SPI3_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_SPI Driver_SPI3 = {SPIx_GetVersion,    SPIx_GetCapabilities,
+#if defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN
+                              SPI3_DMAInitialize, SPI3_DMAUninitialize, SPI3_DMAPowerControl, SPI3_DMASend,
+                              SPI3_DMAReceive,    SPI3_DMATransfer,     SPI3_DMAGetCount,     SPI3_DMAControl,
+                              SPI3_DMAGetStatus
+#else
+                              SPI3_InterruptInitialize,
+                              SPI3_InterruptUninitialize,
+                              SPI3_InterruptPowerControl,
+                              SPI3_InterruptSend,
+                              SPI3_InterruptReceive,
+                              SPI3_InterruptTransfer,
+                              SPI3_InterruptGetCount,
+                              SPI3_InterruptControl,
+                              SPI3_InterruptGetStatus
+#endif
+};
+
+#endif /*  SPI3  */
+
+#if defined(SPI4) && defined(RTE_SPI4) && RTE_SPI4
+
+/* User needs to provide the implementation for SPI4_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t SPI4_GetFreq(void);
+
+static cmsis_spi_resource_t SPI4_Resource = {SPI4, 4, SPI4_GetFreq};
+
+#if defined(RTE_SPI4_DMA_EN) && RTE_SPI4_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_spi_dma_resource_t SPI4_DMAResource = {RTE_SPI4_DMA_TX_DMA_BASE, RTE_SPI4_DMA_TX_CH,
+                                                    RTE_SPI4_DMA_RX_DMA_BASE, RTE_SPI4_DMA_RX_CH};
+
+static cmsis_spi_dma_handle_t SPI4_DmaHandle;
+static dma_handle_t SPI4_DmaTxDataHandle;
+static dma_handle_t SPI4_DmaRxDataHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi4_dma_driver_state")
+static cmsis_spi_dma_driver_state_t SPI4_DMADriverState = {
+#else
+static cmsis_spi_dma_driver_state_t SPI4_DMADriverState  = {
+#endif
+    &SPI4_Resource, &SPI4_DMAResource, &SPI4_DmaHandle, &SPI4_DmaRxDataHandle, &SPI4_DmaTxDataHandle,
+};
+
+static int32_t SPI4_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI4_PIN_INIT
+    RTE_SPI4_PIN_INIT();
+#endif
+    return SPI_DMAInitialize(cb_event, &SPI4_DMADriverState);
+}
+
+static int32_t SPI4_DMAUninitialize(void)
+{
+#ifdef RTE_SPI4_PIN_DEINIT
+    RTE_SPI4_PIN_DEINIT();
+#endif
+    return SPI_DMAUninitialize(&SPI4_DMADriverState);
+}
+
+static int32_t SPI4_DMAPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_DMAPowerControl(state, &SPI4_DMADriverState);
+}
+
+static int32_t SPI4_DMASend(const void *data, uint32_t num)
+{
+    return SPI_DMASend(data, num, &SPI4_DMADriverState);
+}
+
+static int32_t SPI4_DMAReceive(void *data, uint32_t num)
+{
+    return SPI_DMAReceive(data, num, &SPI4_DMADriverState);
+}
+
+static int32_t SPI4_DMATransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_DMATransfer(data_out, data_in, num, &SPI4_DMADriverState);
+}
+
+static uint32_t SPI4_DMAGetCount(void)
+{
+    return SPI_DMAGetCount(&SPI4_DMADriverState);
+}
+
+static int32_t SPI4_DMAControl(uint32_t control, uint32_t arg)
+{
+    return SPI_DMAControl(control, arg, &SPI4_DMADriverState);
+}
+
+static ARM_SPI_STATUS SPI4_DMAGetStatus(void)
+{
+    return SPI_DMAGetStatus(&SPI4_DMADriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_spi_handle_t SPI4_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi4_interrupt_driver_state")
+static cmsis_spi_interrupt_driver_state_t SPI4_InterruptDriverState = {
+#else
+static cmsis_spi_interrupt_driver_state_t SPI4_InterruptDriverState  = {
+#endif
+    &SPI4_Resource,
+    &SPI4_Handle,
+};
+
+static int32_t SPI4_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI4_PIN_INIT
+    RTE_SPI4_PIN_INIT();
+#endif
+    return SPI_InterruptInitialize(cb_event, &SPI4_InterruptDriverState);
+}
+
+static int32_t SPI4_InterruptUninitialize(void)
+{
+#ifdef RTE_SPI4_PIN_DEINIT
+    RTE_SPI4_PIN_DEINIT();
+#endif
+    return SPI_InterruptUninitialize(&SPI4_InterruptDriverState);
+}
+
+static int32_t SPI4_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_InterruptPowerControl(state, &SPI4_InterruptDriverState);
+}
+
+static int32_t SPI4_InterruptSend(const void *data, uint32_t num)
+{
+    return SPI_InterruptSend(data, num, &SPI4_InterruptDriverState);
+}
+
+static int32_t SPI4_InterruptReceive(void *data, uint32_t num)
+{
+    return SPI_InterruptReceive(data, num, &SPI4_InterruptDriverState);
+}
+
+static int32_t SPI4_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_InterruptTransfer(data_out, data_in, num, &SPI4_InterruptDriverState);
+}
+
+static uint32_t SPI4_InterruptGetCount(void)
+{
+    return SPI_InterruptGetCount(&SPI4_InterruptDriverState);
+}
+
+static int32_t SPI4_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return SPI_InterruptControl(control, arg, &SPI4_InterruptDriverState);
+}
+
+static ARM_SPI_STATUS SPI4_InterruptGetStatus(void)
+{
+    return SPI_InterruptGetStatus(&SPI4_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_SPI Driver_SPI4 = {SPIx_GetVersion,    SPIx_GetCapabilities,
+#if defined(RTE_SPI4_DMA_EN) && RTE_SPI4_DMA_EN
+                              SPI4_DMAInitialize, SPI4_DMAUninitialize, SPI4_DMAPowerControl, SPI4_DMASend,
+                              SPI4_DMAReceive,    SPI4_DMATransfer,     SPI4_DMAGetCount,     SPI4_DMAControl,
+                              SPI4_DMAGetStatus
+#else
+                              SPI4_InterruptInitialize,
+                              SPI4_InterruptUninitialize,
+                              SPI4_InterruptPowerControl,
+                              SPI4_InterruptSend,
+                              SPI4_InterruptReceive,
+                              SPI4_InterruptTransfer,
+                              SPI4_InterruptGetCount,
+                              SPI4_InterruptControl,
+                              SPI4_InterruptGetStatus
+#endif
+};
+
+#endif /*  SPI4  */
+
+#if defined(SPI5) && defined(RTE_SPI5) && RTE_SPI5
+
+/* User needs to provide the implementation for SPI5_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t SPI5_GetFreq(void);
+
+static cmsis_spi_resource_t SPI5_Resource = {SPI5, 5, SPI5_GetFreq};
+
+#if defined(RTE_SPI5_DMA_EN) && RTE_SPI5_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_spi_dma_resource_t SPI5_DMAResource = {RTE_SPI5_DMA_TX_DMA_BASE, RTE_SPI5_DMA_TX_CH,
+                                                    RTE_SPI5_DMA_RX_DMA_BASE, RTE_SPI5_DMA_RX_CH};
+
+static cmsis_spi_dma_handle_t SPI5_DmaHandle;
+static dma_handle_t SPI5_DmaTxDataHandle;
+static dma_handle_t SPI5_DmaRxDataHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi5_dma_driver_state")
+static cmsis_spi_dma_driver_state_t SPI5_DMADriverState = {
+#else
+static cmsis_spi_dma_driver_state_t SPI5_DMADriverState  = {
+#endif
+    &SPI5_Resource, &SPI5_DMAResource, &SPI5_DmaHandle, &SPI5_DmaRxDataHandle, &SPI5_DmaTxDataHandle,
+};
+
+static int32_t SPI5_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI5_PIN_INIT
+    RTE_SPI5_PIN_INIT();
+#endif
+    return SPI_DMAInitialize(cb_event, &SPI5_DMADriverState);
+}
+
+static int32_t SPI5_DMAUninitialize(void)
+{
+#ifdef RTE_SPI5_PIN_DEINIT
+    RTE_SPI5_PIN_DEINIT();
+#endif
+    return SPI_DMAUninitialize(&SPI5_DMADriverState);
+}
+
+static int32_t SPI5_DMAPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_DMAPowerControl(state, &SPI5_DMADriverState);
+}
+
+static int32_t SPI5_DMASend(const void *data, uint32_t num)
+{
+    return SPI_DMASend(data, num, &SPI5_DMADriverState);
+}
+
+static int32_t SPI5_DMAReceive(void *data, uint32_t num)
+{
+    return SPI_DMAReceive(data, num, &SPI5_DMADriverState);
+}
+
+static int32_t SPI5_DMATransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_DMATransfer(data_out, data_in, num, &SPI5_DMADriverState);
+}
+
+static uint32_t SPI5_DMAGetCount(void)
+{
+    return SPI_DMAGetCount(&SPI5_DMADriverState);
+}
+
+static int32_t SPI5_DMAControl(uint32_t control, uint32_t arg)
+{
+    return SPI_DMAControl(control, arg, &SPI5_DMADriverState);
+}
+
+static ARM_SPI_STATUS SPI5_DMAGetStatus(void)
+{
+    return SPI_DMAGetStatus(&SPI5_DMADriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_spi_handle_t SPI5_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi5_interrupt_driver_state")
+static cmsis_spi_interrupt_driver_state_t SPI5_InterruptDriverState = {
+#else
+static cmsis_spi_interrupt_driver_state_t SPI5_InterruptDriverState  = {
+#endif
+    &SPI5_Resource,
+    &SPI5_Handle,
+};
+
+static int32_t SPI5_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI5_PIN_INIT
+    RTE_SPI5_PIN_INIT();
+#endif
+    return SPI_InterruptInitialize(cb_event, &SPI5_InterruptDriverState);
+}
+
+static int32_t SPI5_InterruptUninitialize(void)
+{
+#ifdef RTE_SPI5_PIN_DEINIT
+    RTE_SPI5_PIN_DEINIT();
+#endif
+    return SPI_InterruptUninitialize(&SPI5_InterruptDriverState);
+}
+
+static int32_t SPI5_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_InterruptPowerControl(state, &SPI5_InterruptDriverState);
+}
+
+static int32_t SPI5_InterruptSend(const void *data, uint32_t num)
+{
+    return SPI_InterruptSend(data, num, &SPI5_InterruptDriverState);
+}
+
+static int32_t SPI5_InterruptReceive(void *data, uint32_t num)
+{
+    return SPI_InterruptReceive(data, num, &SPI5_InterruptDriverState);
+}
+
+static int32_t SPI5_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_InterruptTransfer(data_out, data_in, num, &SPI5_InterruptDriverState);
+}
+
+static uint32_t SPI5_InterruptGetCount(void)
+{
+    return SPI_InterruptGetCount(&SPI5_InterruptDriverState);
+}
+
+static int32_t SPI5_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return SPI_InterruptControl(control, arg, &SPI5_InterruptDriverState);
+}
+
+static ARM_SPI_STATUS SPI5_InterruptGetStatus(void)
+{
+    return SPI_InterruptGetStatus(&SPI5_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_SPI Driver_SPI5 = {SPIx_GetVersion,    SPIx_GetCapabilities,
+#if defined(RTE_SPI5_DMA_EN) && RTE_SPI5_DMA_EN
+                              SPI5_DMAInitialize, SPI5_DMAUninitialize, SPI5_DMAPowerControl, SPI5_DMASend,
+                              SPI5_DMAReceive,    SPI5_DMATransfer,     SPI5_DMAGetCount,     SPI5_DMAControl,
+                              SPI5_DMAGetStatus
+#else
+                              SPI5_InterruptInitialize,
+                              SPI5_InterruptUninitialize,
+                              SPI5_InterruptPowerControl,
+                              SPI5_InterruptSend,
+                              SPI5_InterruptReceive,
+                              SPI5_InterruptTransfer,
+                              SPI5_InterruptGetCount,
+                              SPI5_InterruptControl,
+                              SPI5_InterruptGetStatus
+#endif
+};
+
+#endif /*  SPI5  */
+
+#if defined(SPI6) && defined(RTE_SPI6) && RTE_SPI6
+
+/* User needs to provide the implementation for SPI6_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t SPI6_GetFreq(void);
+
+static cmsis_spi_resource_t SPI6_Resource = {SPI6, 6, SPI6_GetFreq};
+
+#if defined(RTE_SPI6_DMA_EN) && RTE_SPI6_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_spi_dma_resource_t SPI6_DMAResource = {RTE_SPI6_DMA_TX_DMA_BASE, RTE_SPI6_DMA_TX_CH,
+                                                    RTE_SPI6_DMA_RX_DMA_BASE, RTE_SPI6_DMA_RX_CH};
+
+static cmsis_spi_dma_handle_t SPI6_DmaHandle;
+static dma_handle_t SPI6_DmaTxDataHandle;
+static dma_handle_t SPI6_DmaRxDataHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi6_dma_driver_state")
+static cmsis_spi_dma_driver_state_t SPI6_DMADriverState = {
+#else
+static cmsis_spi_dma_driver_state_t SPI6_DMADriverState  = {
+#endif
+    &SPI6_Resource, &SPI6_DMAResource, &SPI6_DmaHandle, &SPI6_DmaRxDataHandle, &SPI6_DmaTxDataHandle,
+};
+
+static int32_t SPI6_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI6_PIN_INIT
+    RTE_SPI6_PIN_INIT();
+#endif
+    return SPI_DMAInitialize(cb_event, &SPI6_DMADriverState);
+}
+
+static int32_t SPI6_DMAUninitialize(void)
+{
+#ifdef RTE_SPI6_PIN_DEINIT
+    RTE_SPI6_PIN_DEINIT();
+#endif
+    return SPI_DMAUninitialize(&SPI6_DMADriverState);
+}
+
+static int32_t SPI6_DMAPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_DMAPowerControl(state, &SPI6_DMADriverState);
+}
+
+static int32_t SPI6_DMASend(const void *data, uint32_t num)
+{
+    return SPI_DMASend(data, num, &SPI6_DMADriverState);
+}
+
+static int32_t SPI6_DMAReceive(void *data, uint32_t num)
+{
+    return SPI_DMAReceive(data, num, &SPI6_DMADriverState);
+}
+
+static int32_t SPI6_DMATransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_DMATransfer(data_out, data_in, num, &SPI6_DMADriverState);
+}
+
+static uint32_t SPI6_DMAGetCount(void)
+{
+    return SPI_DMAGetCount(&SPI6_DMADriverState);
+}
+
+static int32_t SPI6_DMAControl(uint32_t control, uint32_t arg)
+{
+    return SPI_DMAControl(control, arg, &SPI6_DMADriverState);
+}
+
+static ARM_SPI_STATUS SPI6_DMAGetStatus(void)
+{
+    return SPI_DMAGetStatus(&SPI6_DMADriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_spi_handle_t SPI6_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi6_interrupt_driver_state")
+static cmsis_spi_interrupt_driver_state_t SPI6_InterruptDriverState = {
+#else
+static cmsis_spi_interrupt_driver_state_t SPI6_InterruptDriverState  = {
+#endif
+    &SPI6_Resource,
+    &SPI6_Handle,
+};
+
+static int32_t SPI6_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI6_PIN_INIT
+    RTE_SPI6_PIN_INIT();
+#endif
+    return SPI_InterruptInitialize(cb_event, &SPI6_InterruptDriverState);
+}
+
+static int32_t SPI6_InterruptUninitialize(void)
+{
+#ifdef RTE_SPI6_PIN_DEINIT
+    RTE_SPI6_PIN_DEINIT();
+#endif
+    return SPI_InterruptUninitialize(&SPI6_InterruptDriverState);
+}
+
+static int32_t SPI6_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_InterruptPowerControl(state, &SPI6_InterruptDriverState);
+}
+
+static int32_t SPI6_InterruptSend(const void *data, uint32_t num)
+{
+    return SPI_InterruptSend(data, num, &SPI6_InterruptDriverState);
+}
+
+static int32_t SPI6_InterruptReceive(void *data, uint32_t num)
+{
+    return SPI_InterruptReceive(data, num, &SPI6_InterruptDriverState);
+}
+
+static int32_t SPI6_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_InterruptTransfer(data_out, data_in, num, &SPI6_InterruptDriverState);
+}
+
+static uint32_t SPI6_InterruptGetCount(void)
+{
+    return SPI_InterruptGetCount(&SPI6_InterruptDriverState);
+}
+
+static int32_t SPI6_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return SPI_InterruptControl(control, arg, &SPI6_InterruptDriverState);
+}
+
+static ARM_SPI_STATUS SPI6_InterruptGetStatus(void)
+{
+    return SPI_InterruptGetStatus(&SPI6_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_SPI Driver_SPI6 = {SPIx_GetVersion,    SPIx_GetCapabilities,
+#if defined(RTE_SPI6_DMA_EN) && RTE_SPI6_DMA_EN
+                              SPI6_DMAInitialize, SPI6_DMAUninitialize, SPI6_DMAPowerControl, SPI6_DMASend,
+                              SPI6_DMAReceive,    SPI6_DMATransfer,     SPI6_DMAGetCount,     SPI6_DMAControl,
+                              SPI6_DMAGetStatus
+#else
+                              SPI6_InterruptInitialize,
+                              SPI6_InterruptUninitialize,
+                              SPI6_InterruptPowerControl,
+                              SPI6_InterruptSend,
+                              SPI6_InterruptReceive,
+                              SPI6_InterruptTransfer,
+                              SPI6_InterruptGetCount,
+                              SPI6_InterruptControl,
+                              SPI6_InterruptGetStatus
+#endif
+};
+
+#endif /*  SPI6  */
+
+#if defined(SPI7) && defined(RTE_SPI7) && RTE_SPI7
+
+/* User needs to provide the implementation for SPI7_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t SPI7_GetFreq(void);
+
+static cmsis_spi_resource_t SPI7_Resource = {SPI7, 7, SPI7_GetFreq};
+
+#if defined(RTE_SPI7_DMA_EN) && RTE_SPI7_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_spi_dma_resource_t SPI7_DMAResource = {RTE_SPI7_DMA_TX_DMA_BASE, RTE_SPI7_DMA_TX_CH,
+                                                    RTE_SPI7_DMA_RX_DMA_BASE, RTE_SPI7_DMA_RX_CH};
+
+static cmsis_spi_dma_handle_t SPI7_DmaHandle;
+static dma_handle_t SPI7_DmaTxDataHandle;
+static dma_handle_t SPI7_DmaRxDataHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi7_dma_driver_state")
+static cmsis_spi_dma_driver_state_t SPI7_DMADriverState = {
+#else
+static cmsis_spi_dma_driver_state_t SPI7_DMADriverState  = {
+#endif
+    &SPI7_Resource, &SPI7_DMAResource, &SPI7_DmaHandle, &SPI7_DmaRxDataHandle, &SPI7_DmaTxDataHandle,
+};
+
+static int32_t SPI7_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI7_PIN_INIT
+    RTE_SPI7_PIN_INIT();
+#endif
+    return SPI_DMAInitialize(cb_event, &SPI7_DMADriverState);
+}
+
+static int32_t SPI7_DMAUninitialize(void)
+{
+#ifdef RTE_SPI7_PIN_DEINIT
+    RTE_SPI7_PIN_DEINIT();
+#endif
+    return SPI_DMAUninitialize(&SPI7_DMADriverState);
+}
+
+static int32_t SPI7_DMAPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_DMAPowerControl(state, &SPI7_DMADriverState);
+}
+
+static int32_t SPI7_DMASend(const void *data, uint32_t num)
+{
+    return SPI_DMASend(data, num, &SPI7_DMADriverState);
+}
+
+static int32_t SPI7_DMAReceive(void *data, uint32_t num)
+{
+    return SPI_DMAReceive(data, num, &SPI7_DMADriverState);
+}
+
+static int32_t SPI7_DMATransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_DMATransfer(data_out, data_in, num, &SPI7_DMADriverState);
+}
+
+static uint32_t SPI7_DMAGetCount(void)
+{
+    return SPI_DMAGetCount(&SPI7_DMADriverState);
+}
+
+static int32_t SPI7_DMAControl(uint32_t control, uint32_t arg)
+{
+    return SPI_DMAControl(control, arg, &SPI7_DMADriverState);
+}
+
+static ARM_SPI_STATUS SPI7_DMAGetStatus(void)
+{
+    return SPI_DMAGetStatus(&SPI7_DMADriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_spi_handle_t SPI7_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi7_interrupt_driver_state")
+static cmsis_spi_interrupt_driver_state_t SPI7_InterruptDriverState = {
+#else
+static cmsis_spi_interrupt_driver_state_t SPI7_InterruptDriverState  = {
+#endif
+    &SPI7_Resource,
+    &SPI7_Handle,
+};
+
+static int32_t SPI7_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI7_PIN_INIT
+    RTE_SPI7_PIN_INIT();
+#endif
+    return SPI_InterruptInitialize(cb_event, &SPI7_InterruptDriverState);
+}
+
+static int32_t SPI7_InterruptUninitialize(void)
+{
+#ifdef RTE_SPI7_PIN_DEINIT
+    RTE_SPI7_PIN_DEINIT();
+#endif
+    return SPI_InterruptUninitialize(&SPI7_InterruptDriverState);
+}
+
+static int32_t SPI7_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_InterruptPowerControl(state, &SPI7_InterruptDriverState);
+}
+
+static int32_t SPI7_InterruptSend(const void *data, uint32_t num)
+{
+    return SPI_InterruptSend(data, num, &SPI7_InterruptDriverState);
+}
+
+static int32_t SPI7_InterruptReceive(void *data, uint32_t num)
+{
+    return SPI_InterruptReceive(data, num, &SPI7_InterruptDriverState);
+}
+
+static int32_t SPI7_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_InterruptTransfer(data_out, data_in, num, &SPI7_InterruptDriverState);
+}
+
+static uint32_t SPI7_InterruptGetCount(void)
+{
+    return SPI_InterruptGetCount(&SPI7_InterruptDriverState);
+}
+
+static int32_t SPI7_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return SPI_InterruptControl(control, arg, &SPI7_InterruptDriverState);
+}
+
+static ARM_SPI_STATUS SPI7_InterruptGetStatus(void)
+{
+    return SPI_InterruptGetStatus(&SPI7_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_SPI Driver_SPI7 = {SPIx_GetVersion,    SPIx_GetCapabilities,
+#if defined(RTE_SPI7_DMA_EN) && RTE_SPI7_DMA_EN
+                              SPI7_DMAInitialize, SPI7_DMAUninitialize, SPI7_DMAPowerControl, SPI7_DMASend,
+                              SPI7_DMAReceive,    SPI7_DMATransfer,     SPI7_DMAGetCount,     SPI7_DMAControl,
+                              SPI7_DMAGetStatus
+#else
+                              SPI7_InterruptInitialize,
+                              SPI7_InterruptUninitialize,
+                              SPI7_InterruptPowerControl,
+                              SPI7_InterruptSend,
+                              SPI7_InterruptReceive,
+                              SPI7_InterruptTransfer,
+                              SPI7_InterruptGetCount,
+                              SPI7_InterruptControl,
+                              SPI7_InterruptGetStatus
+#endif
+};
+
+#endif /*  SPI7  */
+
+#if defined(SPI8) && defined(RTE_SPI8) && RTE_SPI8
+
+/* User needs to provide the implementation for SPI8_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t SPI8_GetFreq(void);
+
+static cmsis_spi_resource_t SPI8_Resource = {SPI8, 8, SPI8_GetFreq};
+
+#if defined(RTE_SPI8_DMA_EN) && RTE_SPI8_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_spi_dma_resource_t SPI8_DMAResource = {RTE_SPI8_DMA_TX_DMA_BASE, RTE_SPI8_DMA_TX_CH,
+                                                    RTE_SPI8_DMA_RX_DMA_BASE, RTE_SPI8_DMA_RX_CH};
+
+static cmsis_spi_dma_handle_t SPI8_DmaHandle;
+static dma_handle_t SPI8_DmaTxDataHandle;
+static dma_handle_t SPI8_DmaRxDataHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi8_dma_driver_state")
+static cmsis_spi_dma_driver_state_t SPI8_DMADriverState = {
+#else
+static cmsis_spi_dma_driver_state_t SPI8_DMADriverState  = {
+#endif
+    &SPI8_Resource, &SPI8_DMAResource, &SPI8_DmaHandle, &SPI8_DmaRxDataHandle, &SPI8_DmaTxDataHandle,
+};
+
+static int32_t SPI8_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI8_PIN_INIT
+    RTE_SPI8_PIN_INIT();
+#endif
+    return SPI_DMAInitialize(cb_event, &SPI8_DMADriverState);
+}
+
+static int32_t SPI8_DMAUninitialize(void)
+{
+#ifdef RTE_SPI8_PIN_DEINIT
+    RTE_SPI8_PIN_DEINIT();
+#endif
+    return SPI_DMAUninitialize(&SPI8_DMADriverState);
+}
+
+static int32_t SPI8_DMAPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_DMAPowerControl(state, &SPI8_DMADriverState);
+}
+
+static int32_t SPI8_DMASend(const void *data, uint32_t num)
+{
+    return SPI_DMASend(data, num, &SPI8_DMADriverState);
+}
+
+static int32_t SPI8_DMAReceive(void *data, uint32_t num)
+{
+    return SPI_DMAReceive(data, num, &SPI8_DMADriverState);
+}
+
+static int32_t SPI8_DMATransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_DMATransfer(data_out, data_in, num, &SPI8_DMADriverState);
+}
+
+static uint32_t SPI8_DMAGetCount(void)
+{
+    return SPI_DMAGetCount(&SPI8_DMADriverState);
+}
+
+static int32_t SPI8_DMAControl(uint32_t control, uint32_t arg)
+{
+    return SPI_DMAControl(control, arg, &SPI8_DMADriverState);
+}
+
+static ARM_SPI_STATUS SPI8_DMAGetStatus(void)
+{
+    return SPI_DMAGetStatus(&SPI8_DMADriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_spi_handle_t SPI8_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi8_interrupt_driver_state")
+static cmsis_spi_interrupt_driver_state_t SPI8_InterruptDriverState = {
+#else
+static cmsis_spi_interrupt_driver_state_t SPI8_InterruptDriverState  = {
+#endif
+    &SPI8_Resource,
+    &SPI8_Handle,
+};
+
+static int32_t SPI8_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI8_PIN_INIT
+    RTE_SPI8_PIN_INIT();
+#endif
+    return SPI_InterruptInitialize(cb_event, &SPI8_InterruptDriverState);
+}
+
+static int32_t SPI8_InterruptUninitialize(void)
+{
+#ifdef RTE_SPI8_PIN_DEINIT
+    RTE_SPI8_PIN_DEINIT();
+#endif
+    return SPI_InterruptUninitialize(&SPI8_InterruptDriverState);
+}
+
+static int32_t SPI8_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_InterruptPowerControl(state, &SPI8_InterruptDriverState);
+}
+
+static int32_t SPI8_InterruptSend(const void *data, uint32_t num)
+{
+    return SPI_InterruptSend(data, num, &SPI8_InterruptDriverState);
+}
+
+static int32_t SPI8_InterruptReceive(void *data, uint32_t num)
+{
+    return SPI_InterruptReceive(data, num, &SPI8_InterruptDriverState);
+}
+
+static int32_t SPI8_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_InterruptTransfer(data_out, data_in, num, &SPI8_InterruptDriverState);
+}
+
+static uint32_t SPI8_InterruptGetCount(void)
+{
+    return SPI_InterruptGetCount(&SPI8_InterruptDriverState);
+}
+
+static int32_t SPI8_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return SPI_InterruptControl(control, arg, &SPI8_InterruptDriverState);
+}
+
+static ARM_SPI_STATUS SPI8_InterruptGetStatus(void)
+{
+    return SPI_InterruptGetStatus(&SPI8_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_SPI Driver_SPI8 = {SPIx_GetVersion,    SPIx_GetCapabilities,
+#if defined(RTE_SPI8_DMA_EN) && RTE_SPI8_DMA_EN
+                              SPI8_DMAInitialize, SPI8_DMAUninitialize, SPI8_DMAPowerControl, SPI8_DMASend,
+                              SPI8_DMAReceive,    SPI8_DMATransfer,     SPI8_DMAGetCount,     SPI8_DMAControl,
+                              SPI8_DMAGetStatus
+#else
+                              SPI8_InterruptInitialize,
+                              SPI8_InterruptUninitialize,
+                              SPI8_InterruptPowerControl,
+                              SPI8_InterruptSend,
+                              SPI8_InterruptReceive,
+                              SPI8_InterruptTransfer,
+                              SPI8_InterruptGetCount,
+                              SPI8_InterruptControl,
+                              SPI8_InterruptGetStatus
+#endif
+};
+
+#endif /*  SPI8  */
+
+#if defined(SPI9) && defined(RTE_SPI9) && RTE_SPI9
+
+/* User needs to provide the implementation for SPI9_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t SPI9_GetFreq(void);
+
+static cmsis_spi_resource_t SPI9_Resource = {SPI9, 9, SPI9_GetFreq};
+
+#if defined(RTE_SPI9_DMA_EN) && RTE_SPI9_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_spi_dma_resource_t SPI9_DMAResource = {RTE_SPI9_DMA_TX_DMA_BASE, RTE_SPI9_DMA_TX_CH,
+                                                    RTE_SPI9_DMA_RX_DMA_BASE, RTE_SPI9_DMA_RX_CH};
+
+static cmsis_spi_dma_handle_t SPI9_DmaHandle;
+static dma_handle_t SPI9_DmaTxDataHandle;
+static dma_handle_t SPI9_DmaRxDataHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi9_dma_driver_state")
+static cmsis_spi_dma_driver_state_t SPI9_DMADriverState = {
+#else
+static cmsis_spi_dma_driver_state_t SPI9_DMADriverState  = {
+#endif
+    &SPI9_Resource, &SPI9_DMAResource, &SPI9_DmaHandle, &SPI9_DmaRxDataHandle, &SPI9_DmaTxDataHandle,
+};
+
+static int32_t SPI9_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI9_PIN_INIT
+    RTE_SPI9_PIN_INIT();
+#endif
+    return SPI_DMAInitialize(cb_event, &SPI9_DMADriverState);
+}
+
+static int32_t SPI9_DMAUninitialize(void)
+{
+#ifdef RTE_SPI9_PIN_DEINIT
+    RTE_SPI9_PIN_DEINIT();
+#endif
+    return SPI_DMAUninitialize(&SPI9_DMADriverState);
+}
+
+static int32_t SPI9_DMAPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_DMAPowerControl(state, &SPI9_DMADriverState);
+}
+
+static int32_t SPI9_DMASend(const void *data, uint32_t num)
+{
+    return SPI_DMASend(data, num, &SPI9_DMADriverState);
+}
+
+static int32_t SPI9_DMAReceive(void *data, uint32_t num)
+{
+    return SPI_DMAReceive(data, num, &SPI9_DMADriverState);
+}
+
+static int32_t SPI9_DMATransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_DMATransfer(data_out, data_in, num, &SPI9_DMADriverState);
+}
+
+static uint32_t SPI9_DMAGetCount(void)
+{
+    return SPI_DMAGetCount(&SPI9_DMADriverState);
+}
+
+static int32_t SPI9_DMAControl(uint32_t control, uint32_t arg)
+{
+    return SPI_DMAControl(control, arg, &SPI9_DMADriverState);
+}
+
+static ARM_SPI_STATUS SPI9_DMAGetStatus(void)
+{
+    return SPI_DMAGetStatus(&SPI9_DMADriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_spi_handle_t SPI9_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi9_interrupt_driver_state")
+static cmsis_spi_interrupt_driver_state_t SPI9_InterruptDriverState = {
+#else
+static cmsis_spi_interrupt_driver_state_t SPI9_InterruptDriverState  = {
+#endif
+    &SPI9_Resource,
+    &SPI9_Handle,
+};
+
+static int32_t SPI9_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI9_PIN_INIT
+    RTE_SPI9_PIN_INIT();
+#endif
+    return SPI_InterruptInitialize(cb_event, &SPI9_InterruptDriverState);
+}
+
+static int32_t SPI9_InterruptUninitialize(void)
+{
+#ifdef RTE_SPI9_PIN_DEINIT
+    RTE_SPI9_PIN_DEINIT();
+#endif
+    return SPI_InterruptUninitialize(&SPI9_InterruptDriverState);
+}
+
+static int32_t SPI9_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_InterruptPowerControl(state, &SPI9_InterruptDriverState);
+}
+
+static int32_t SPI9_InterruptSend(const void *data, uint32_t num)
+{
+    return SPI_InterruptSend(data, num, &SPI9_InterruptDriverState);
+}
+
+static int32_t SPI9_InterruptReceive(void *data, uint32_t num)
+{
+    return SPI_InterruptReceive(data, num, &SPI9_InterruptDriverState);
+}
+
+static int32_t SPI9_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_InterruptTransfer(data_out, data_in, num, &SPI9_InterruptDriverState);
+}
+
+static uint32_t SPI9_InterruptGetCount(void)
+{
+    return SPI_InterruptGetCount(&SPI9_InterruptDriverState);
+}
+
+static int32_t SPI9_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return SPI_InterruptControl(control, arg, &SPI9_InterruptDriverState);
+}
+
+static ARM_SPI_STATUS SPI9_InterruptGetStatus(void)
+{
+    return SPI_InterruptGetStatus(&SPI9_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_SPI Driver_SPI9 = {SPIx_GetVersion,    SPIx_GetCapabilities,
+#if defined(RTE_SPI9_DMA_EN) && RTE_SPI9_DMA_EN
+                              SPI9_DMAInitialize, SPI9_DMAUninitialize, SPI9_DMAPowerControl, SPI9_DMASend,
+                              SPI9_DMAReceive,    SPI9_DMATransfer,     SPI9_DMAGetCount,     SPI9_DMAControl,
+                              SPI9_DMAGetStatus
+#else
+                              SPI9_InterruptInitialize,
+                              SPI9_InterruptUninitialize,
+                              SPI9_InterruptPowerControl,
+                              SPI9_InterruptSend,
+                              SPI9_InterruptReceive,
+                              SPI9_InterruptTransfer,
+                              SPI9_InterruptGetCount,
+                              SPI9_InterruptControl,
+                              SPI9_InterruptGetStatus
+#endif
+};
+
+#endif /*  SPI9  */
+
+#if defined(SPI10) && defined(RTE_SPI10) && RTE_SPI10
+/* User needs to provide the implementation for SPI10_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t SPI10_GetFreq(void);
+static cmsis_spi_resource_t SPI10_Resource = {SPI10, 1, SPI10_GetFreq};
+
+#if RTE_SPI10_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_spi_dma_resource_t SPI10_DMAResource = {RTE_SPI10_DMA_TX_DMA_BASE, RTE_SPI10_DMA_TX_CH,
+                                                     RTE_SPI10_DMA_RX_DMA_BASE, RTE_SPI10_DMA_RX_CH};
+
+static cmsis_spi_dma_handle_t SPI10_DmaHandle;
+static dma_handle_t SPI10_DmaTxDataHandle;
+static dma_handle_t SPI10_DmaRxDataHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi10_dma_driver_state")
+static cmsis_spi_dma_driver_state_t SPI10_DMADriverState = {
+#else
+static cmsis_spi_dma_driver_state_t SPI10_DMADriverState = {
+#endif
+    &SPI10_Resource, &SPI10_DMAResource, &SPI10_DmaHandle, &SPI10_DmaRxDataHandle, &SPI10_DmaTxDataHandle,
+};
+
+static int32_t SPI10_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI10_PIN_INIT
+    RTE_SPI10_PIN_INIT();
+#endif
+    return SPI_DMAInitialize(cb_event, &SPI10_DMADriverState);
+}
+
+static int32_t SPI10_DMAUninitialize(void)
+{
+#ifdef RTE_SPI10_PIN_DEINIT
+    RTE_SPI10_PIN_DEINIT();
+#endif
+    return SPI_DMAUninitialize(&SPI10_DMADriverState);
+}
+
+static int32_t SPI10_DMAPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_DMAPowerControl(state, &SPI10_DMADriverState);
+}
+
+static int32_t SPI10_DMASend(const void *data, uint32_t num)
+{
+    return SPI_DMASend(data, num, &SPI10_DMADriverState);
+}
+
+static int32_t SPI10_DMAReceive(void *data, uint32_t num)
+{
+    return SPI_DMAReceive(data, num, &SPI10_DMADriverState);
+}
+
+static int32_t SPI10_DMATransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_DMATransfer(data_out, data_in, num, &SPI10_DMADriverState);
+}
+
+static uint32_t SPI10_DMAGetCount(void)
+{
+    return SPI_DMAGetCount(&SPI10_DMADriverState);
+}
+
+static int32_t SPI10_DMAControl(uint32_t control, uint32_t arg)
+{
+    return SPI_DMAControl(control, arg, &SPI10_DMADriverState);
+}
+
+static ARM_SPI_STATUS SPI10_DMAGetStatus(void)
+{
+    return SPI_DMAGetStatus(&SPI10_DMADriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_spi_handle_t SPI10_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi10_interrupt_driver_state")
+static cmsis_spi_interrupt_driver_state_t SPI10_InterruptDriverState = {
+#else
+static cmsis_spi_interrupt_driver_state_t SPI10_InterruptDriverState = {
+#endif
+    &SPI10_Resource,
+    &SPI10_Handle,
+};
+
+static int32_t SPI10_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI10_PIN_INIT
+    RTE_SPI10_PIN_INIT();
+#endif
+    return SPI_InterruptInitialize(cb_event, &SPI10_InterruptDriverState);
+}
+
+static int32_t SPI10_InterruptUninitialize(void)
+{
+#ifdef RTE_SPI10_PIN_DEINIT
+    RTE_SPI10_PIN_DEINIT();
+#endif
+    return SPI_InterruptUninitialize(&SPI10_InterruptDriverState);
+}
+
+static int32_t SPI10_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_InterruptPowerControl(state, &SPI10_InterruptDriverState);
+}
+
+static int32_t SPI10_InterruptSend(const void *data, uint32_t num)
+{
+    return SPI_InterruptSend(data, num, &SPI10_InterruptDriverState);
+}
+
+static int32_t SPI10_InterruptReceive(void *data, uint32_t num)
+{
+    return SPI_InterruptReceive(data, num, &SPI10_InterruptDriverState);
+}
+
+static int32_t SPI10_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_InterruptTransfer(data_out, data_in, num, &SPI10_InterruptDriverState);
+}
+
+static uint32_t SPI10_InterruptGetCount(void)
+{
+    return SPI_InterruptGetCount(&SPI10_InterruptDriverState);
+}
+
+static int32_t SPI10_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return SPI_InterruptControl(control, arg, &SPI10_InterruptDriverState);
+}
+
+static ARM_SPI_STATUS SPI10_InterruptGetStatus(void)
+{
+    return SPI_InterruptGetStatus(&SPI10_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_SPI Driver_SPI10 = {SPIx_GetVersion,     SPIx_GetCapabilities,
+#if defined(RTE_SPI10_DMA_EN) && RTE_SPI10_DMA_EN
+                               SPI10_DMAInitialize, SPI10_DMAUninitialize, SPI10_DMAPowerControl, SPI10_DMASend,
+                               SPI10_DMAReceive,    SPI10_DMATransfer,     SPI10_DMAGetCount,     SPI10_DMAControl,
+                               SPI10_DMAGetStatus
+#else
+                               SPI10_InterruptInitialize,
+                               SPI10_InterruptUninitialize,
+                               SPI10_InterruptPowerControl,
+                               SPI10_InterruptSend,
+                               SPI10_InterruptReceive,
+                               SPI10_InterruptTransfer,
+                               SPI10_InterruptGetCount,
+                               SPI10_InterruptControl,
+                               SPI10_InterruptGetStatus
+#endif
+};
+
+#endif /*  SPI10  */
+
+#if defined(SPI11) && defined(RTE_SPI11) && RTE_SPI11
+/* User needs to provide the implementation for SPI11_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t SPI11_GetFreq(void);
+static cmsis_spi_resource_t SPI11_Resource = {SPI11, 1, SPI11_GetFreq};
+
+#if defined(RTE_SPI11_DMA_EN) && RTE_SPI11_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_spi_dma_resource_t SPI11_DMAResource = {RTE_SPI11_DMA_TX_DMA_BASE, RTE_SPI11_DMA_TX_CH,
+                                                     RTE_SPI11_DMA_RX_DMA_BASE, RTE_SPI11_DMA_RX_CH};
+
+static cmsis_spi_dma_handle_t SPI11_DmaHandle;
+static dma_handle_t SPI11_DmaTxDataHandle;
+static dma_handle_t SPI11_DmaRxDataHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi11_dma_driver_state")
+static cmsis_spi_dma_driver_state_t SPI11_DMADriverState = {
+#else
+static cmsis_spi_dma_driver_state_t SPI11_DMADriverState = {
+#endif
+    &SPI11_Resource, &SPI11_DMAResource, &SPI11_DmaHandle, &SPI11_DmaRxDataHandle, &SPI11_DmaTxDataHandle,
+};
+
+static int32_t SPI11_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI11_PIN_INIT
+    RTE_SPI11_PIN_INIT();
+#endif
+    return SPI_DMAInitialize(cb_event, &SPI11_DMADriverState);
+}
+
+static int32_t SPI11_DMAUninitialize(void)
+{
+#ifdef RTE_SPI11_PIN_DEINIT
+    RTE_SPI11_PIN_DEINIT();
+#endif
+    return SPI_DMAUninitialize(&SPI11_DMADriverState);
+}
+
+static int32_t SPI11_DMAPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_DMAPowerControl(state, &SPI11_DMADriverState);
+}
+
+static int32_t SPI11_DMASend(const void *data, uint32_t num)
+{
+    return SPI_DMASend(data, num, &SPI11_DMADriverState);
+}
+
+static int32_t SPI11_DMAReceive(void *data, uint32_t num)
+{
+    return SPI_DMAReceive(data, num, &SPI11_DMADriverState);
+}
+
+static int32_t SPI11_DMATransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_DMATransfer(data_out, data_in, num, &SPI11_DMADriverState);
+}
+
+static uint32_t SPI11_DMAGetCount(void)
+{
+    return SPI_DMAGetCount(&SPI11_DMADriverState);
+}
+
+static int32_t SPI11_DMAControl(uint32_t control, uint32_t arg)
+{
+    return SPI_DMAControl(control, arg, &SPI11_DMADriverState);
+}
+
+static ARM_SPI_STATUS SPI11_DMAGetStatus(void)
+{
+    return SPI_DMAGetStatus(&SPI11_DMADriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_spi_handle_t SPI11_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi11_interrupt_driver_state")
+static cmsis_spi_interrupt_driver_state_t SPI11_InterruptDriverState = {
+#else
+static cmsis_spi_interrupt_driver_state_t SPI11_InterruptDriverState = {
+#endif
+    &SPI11_Resource,
+    &SPI11_Handle,
+};
+
+static int32_t SPI11_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI11_PIN_INIT
+    RTE_SPI11_PIN_INIT();
+#endif
+    return SPI_InterruptInitialize(cb_event, &SPI11_InterruptDriverState);
+}
+
+static int32_t SPI11_InterruptUninitialize(void)
+{
+#ifdef RTE_SPI11_PIN_DEINIT
+    RTE_SPI11_PIN_DEINIT();
+#endif
+    return SPI_InterruptUninitialize(&SPI11_InterruptDriverState);
+}
+
+static int32_t SPI11_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_InterruptPowerControl(state, &SPI11_InterruptDriverState);
+}
+
+static int32_t SPI11_InterruptSend(const void *data, uint32_t num)
+{
+    return SPI_InterruptSend(data, num, &SPI11_InterruptDriverState);
+}
+
+static int32_t SPI11_InterruptReceive(void *data, uint32_t num)
+{
+    return SPI_InterruptReceive(data, num, &SPI11_InterruptDriverState);
+}
+
+static int32_t SPI11_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_InterruptTransfer(data_out, data_in, num, &SPI11_InterruptDriverState);
+}
+
+static uint32_t SPI11_InterruptGetCount(void)
+{
+    return SPI_InterruptGetCount(&SPI11_InterruptDriverState);
+}
+
+static int32_t SPI11_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return SPI_InterruptControl(control, arg, &SPI11_InterruptDriverState);
+}
+
+static ARM_SPI_STATUS SPI11_InterruptGetStatus(void)
+{
+    return SPI_InterruptGetStatus(&SPI11_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_SPI Driver_SPI11 = {SPIx_GetVersion,     SPIx_GetCapabilities,
+#if defined(RTE_SPI11_DMA_EN) && RTE_SPI11_DMA_EN
+                               SPI11_DMAInitialize, SPI11_DMAUninitialize, SPI11_DMAPowerControl, SPI11_DMASend,
+                               SPI11_DMAReceive,    SPI11_DMATransfer,     SPI11_DMAGetCount,     SPI11_DMAControl,
+                               SPI11_DMAGetStatus
+#else
+                               SPI11_InterruptInitialize,
+                               SPI11_InterruptUninitialize,
+                               SPI11_InterruptPowerControl,
+                               SPI11_InterruptSend,
+                               SPI11_InterruptReceive,
+                               SPI11_InterruptTransfer,
+                               SPI11_InterruptGetCount,
+                               SPI11_InterruptControl,
+                               SPI11_InterruptGetStatus
+#endif
+};
+
+#endif /*  SPI11  */
+
+#if defined(SPI12) && defined(RTE_SPI12) && RTE_SPI12
+/* User needs to provide the implementation for SPI12_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t SPI12_GetFreq(void);
+static cmsis_spi_resource_t SPI12_Resource = {SPI12, 1, SPI12_GetFreq};
+
+#if defined(RTE_SPI12_DMA_EN) && RTE_SPI12_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_spi_dma_resource_t SPI12_DMAResource = {RTE_SPI12_DMA_TX_DMA_BASE, RTE_SPI12_DMA_TX_CH,
+                                                     RTE_SPI12_DMA_RX_DMA_BASE, RTE_SPI12_DMA_RX_CH};
+
+static cmsis_spi_dma_handle_t SPI12_DmaHandle;
+static dma_handle_t SPI12_DmaTxDataHandle;
+static dma_handle_t SPI12_DmaRxDataHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi12_dma_driver_state")
+static cmsis_spi_dma_driver_state_t SPI12_DMADriverState = {
+#else
+static cmsis_spi_dma_driver_state_t SPI12_DMADriverState = {
+#endif
+    &SPI12_Resource, &SPI12_DMAResource, &SPI12_DmaHandle, &SPI12_DmaRxDataHandle, &SPI12_DmaTxDataHandle,
+};
+
+static int32_t SPI12_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI12_PIN_INIT
+    RTE_SPI12_PIN_INIT();
+#endif
+    return SPI_DMAInitialize(cb_event, &SPI12_DMADriverState);
+}
+
+static int32_t SPI12_DMAUninitialize(void)
+{
+#ifdef RTE_SPI12_PIN_DEINIT
+    RTE_SPI12_PIN_DEINIT();
+#endif
+    return SPI_DMAUninitialize(&SPI12_DMADriverState);
+}
+
+static int32_t SPI12_DMAPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_DMAPowerControl(state, &SPI12_DMADriverState);
+}
+
+static int32_t SPI12_DMASend(const void *data, uint32_t num)
+{
+    return SPI_DMASend(data, num, &SPI12_DMADriverState);
+}
+
+static int32_t SPI12_DMAReceive(void *data, uint32_t num)
+{
+    return SPI_DMAReceive(data, num, &SPI12_DMADriverState);
+}
+
+static int32_t SPI12_DMATransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_DMATransfer(data_out, data_in, num, &SPI12_DMADriverState);
+}
+
+static uint32_t SPI12_DMAGetCount(void)
+{
+    return SPI_DMAGetCount(&SPI12_DMADriverState);
+}
+
+static int32_t SPI12_DMAControl(uint32_t control, uint32_t arg)
+{
+    return SPI_DMAControl(control, arg, &SPI12_DMADriverState);
+}
+
+static ARM_SPI_STATUS SPI12_DMAGetStatus(void)
+{
+    return SPI_DMAGetStatus(&SPI12_DMADriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_spi_handle_t SPI12_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi12_interrupt_driver_state")
+static cmsis_spi_interrupt_driver_state_t SPI12_InterruptDriverState = {
+#else
+static cmsis_spi_interrupt_driver_state_t SPI12_InterruptDriverState = {
+#endif
+    &SPI12_Resource,
+    &SPI12_Handle,
+};
+
+static int32_t SPI12_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI12_PIN_INIT
+    RTE_SPI12_PIN_INIT();
+#endif
+    return SPI_InterruptInitialize(cb_event, &SPI12_InterruptDriverState);
+}
+
+static int32_t SPI12_InterruptUninitialize(void)
+{
+#ifdef RTE_SPI12_PIN_DEINIT
+    RTE_SPI12_PIN_DEINIT();
+#endif
+    return SPI_InterruptUninitialize(&SPI12_InterruptDriverState);
+}
+
+static int32_t SPI12_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_InterruptPowerControl(state, &SPI12_InterruptDriverState);
+}
+
+static int32_t SPI12_InterruptSend(const void *data, uint32_t num)
+{
+    return SPI_InterruptSend(data, num, &SPI12_InterruptDriverState);
+}
+
+static int32_t SPI12_InterruptReceive(void *data, uint32_t num)
+{
+    return SPI_InterruptReceive(data, num, &SPI12_InterruptDriverState);
+}
+
+static int32_t SPI12_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_InterruptTransfer(data_out, data_in, num, &SPI12_InterruptDriverState);
+}
+
+static uint32_t SPI12_InterruptGetCount(void)
+{
+    return SPI_InterruptGetCount(&SPI12_InterruptDriverState);
+}
+
+static int32_t SPI12_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return SPI_InterruptControl(control, arg, &SPI12_InterruptDriverState);
+}
+
+static ARM_SPI_STATUS SPI12_InterruptGetStatus(void)
+{
+    return SPI_InterruptGetStatus(&SPI12_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_SPI Driver_SPI12 = {SPIx_GetVersion,     SPIx_GetCapabilities,
+#if defined(RTE_SPI12_DMA_EN) && RTE_SPI12_DMA_EN
+                               SPI12_DMAInitialize, SPI12_DMAUninitialize, SPI12_DMAPowerControl, SPI12_DMASend,
+                               SPI12_DMAReceive,    SPI12_DMATransfer,     SPI12_DMAGetCount,     SPI12_DMAControl,
+                               SPI12_DMAGetStatus
+#else
+                               SPI12_InterruptInitialize,
+                               SPI12_InterruptUninitialize,
+                               SPI12_InterruptPowerControl,
+                               SPI12_InterruptSend,
+                               SPI12_InterruptReceive,
+                               SPI12_InterruptTransfer,
+                               SPI12_InterruptGetCount,
+                               SPI12_InterruptControl,
+                               SPI12_InterruptGetStatus
+#endif
+};
+
+#endif /*  SPI12  */
+
+#if defined(SPI13) && defined(RTE_SPI13) && RTE_SPI13
+/* User needs to provide the implementation for SPI13_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t SPI13_GetFreq(void);
+static cmsis_spi_resource_t SPI13_Resource = {SPI13, 1, SPI13_GetFreq};
+
+#if defined(RTE_SPI13_DMA_EN) && RTE_SPI13_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_spi_dma_resource_t SPI13_DMAResource = {RTE_SPI13_DMA_TX_DMA_BASE, RTE_SPI13_DMA_TX_CH,
+                                                     RTE_SPI13_DMA_RX_DMA_BASE, RTE_SPI13_DMA_RX_CH};
+
+static cmsis_spi_dma_handle_t SPI13_DmaHandle;
+static dma_handle_t SPI13_DmaTxDataHandle;
+static dma_handle_t SPI13_DmaRxDataHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi13_dma_driver_state")
+static cmsis_spi_dma_driver_state_t SPI13_DMADriverState = {
+#else
+static cmsis_spi_dma_driver_state_t SPI13_DMADriverState = {
+#endif
+    &SPI13_Resource, &SPI13_DMAResource, &SPI13_DmaHandle, &SPI13_DmaRxDataHandle, &SPI13_DmaTxDataHandle,
+};
+
+static int32_t SPI13_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI13_PIN_INIT
+    RTE_SPI13_PIN_INIT();
+#endif
+    return SPI_DMAInitialize(cb_event, &SPI13_DMADriverState);
+}
+
+static int32_t SPI13_DMAUninitialize(void)
+{
+#ifdef RTE_SPI13_PIN_DEINIT
+    RTE_SPI13_PIN_DEINIT();
+#endif
+    return SPI_DMAUninitialize(&SPI13_DMADriverState);
+}
+
+static int32_t SPI13_DMAPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_DMAPowerControl(state, &SPI13_DMADriverState);
+}
+
+static int32_t SPI13_DMASend(const void *data, uint32_t num)
+{
+    return SPI_DMASend(data, num, &SPI13_DMADriverState);
+}
+
+static int32_t SPI13_DMAReceive(void *data, uint32_t num)
+{
+    return SPI_DMAReceive(data, num, &SPI13_DMADriverState);
+}
+
+static int32_t SPI13_DMATransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_DMATransfer(data_out, data_in, num, &SPI13_DMADriverState);
+}
+
+static uint32_t SPI13_DMAGetCount(void)
+{
+    return SPI_DMAGetCount(&SPI13_DMADriverState);
+}
+
+static int32_t SPI13_DMAControl(uint32_t control, uint32_t arg)
+{
+    return SPI_DMAControl(control, arg, &SPI13_DMADriverState);
+}
+
+static ARM_SPI_STATUS SPI13_DMAGetStatus(void)
+{
+    return SPI_DMAGetStatus(&SPI13_DMADriverState);
+}
+
+#endif
+
+#else
+
+static cmsis_spi_handle_t SPI13_Handle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("spi13_interrupt_driver_state")
+static cmsis_spi_interrupt_driver_state_t SPI13_InterruptDriverState = {
+#else
+static cmsis_spi_interrupt_driver_state_t SPI13_InterruptDriverState = {
+#endif
+    &SPI13_Resource,
+    &SPI13_Handle,
+};
+
+static int32_t SPI13_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
+{
+#ifdef RTE_SPI13_PIN_INIT
+    RTE_SPI13_PIN_INIT();
+#endif
+    return SPI_InterruptInitialize(cb_event, &SPI13_InterruptDriverState);
+}
+
+static int32_t SPI13_InterruptUninitialize(void)
+{
+#ifdef RTE_SPI13_PIN_DEINIT
+    RTE_SPI13_PIN_DEINIT();
+#endif
+    return SPI_InterruptUninitialize(&SPI13_InterruptDriverState);
+}
+
+static int32_t SPI13_InterruptPowerControl(ARM_POWER_STATE state)
+{
+    return SPI_InterruptPowerControl(state, &SPI13_InterruptDriverState);
+}
+
+static int32_t SPI13_InterruptSend(const void *data, uint32_t num)
+{
+    return SPI_InterruptSend(data, num, &SPI13_InterruptDriverState);
+}
+
+static int32_t SPI13_InterruptReceive(void *data, uint32_t num)
+{
+    return SPI_InterruptReceive(data, num, &SPI13_InterruptDriverState);
+}
+
+static int32_t SPI13_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return SPI_InterruptTransfer(data_out, data_in, num, &SPI13_InterruptDriverState);
+}
+
+static uint32_t SPI13_InterruptGetCount(void)
+{
+    return SPI_InterruptGetCount(&SPI13_InterruptDriverState);
+}
+
+static int32_t SPI13_InterruptControl(uint32_t control, uint32_t arg)
+{
+    return SPI_InterruptControl(control, arg, &SPI13_InterruptDriverState);
+}
+
+static ARM_SPI_STATUS SPI13_InterruptGetStatus(void)
+{
+    return SPI_InterruptGetStatus(&SPI13_InterruptDriverState);
+}
+
+#endif
+
+ARM_DRIVER_SPI Driver_SPI13 = {SPIx_GetVersion,     SPIx_GetCapabilities,
+#if defined(RTE_SPI13_DMA_EN) && RTE_SPI13_DMA_EN
+                               SPI13_DMAInitialize, SPI13_DMAUninitialize, SPI13_DMAPowerControl, SPI13_DMASend,
+                               SPI13_DMAReceive,    SPI13_DMATransfer,     SPI13_DMAGetCount,     SPI13_DMAControl,
+                               SPI13_DMAGetStatus
+#else
+                               SPI13_InterruptInitialize,
+                               SPI13_InterruptUninitialize,
+                               SPI13_InterruptPowerControl,
+                               SPI13_InterruptSend,
+                               SPI13_InterruptReceive,
+                               SPI13_InterruptTransfer,
+                               SPI13_InterruptGetCount,
+                               SPI13_InterruptControl,
+                               SPI13_InterruptGetStatus
+#endif
+};
+
+#endif /*  SPI13  */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_spi_cmsis.h

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
+ * Copyright 2016-2020 NXP. Not a Contribution.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _FSL_SPI_CMSIS_H_
+#define _FSL_SPI_CMSIS_H_
+
+#include "fsl_spi.h"
+#include "RTE_Device.h"
+#include "Driver_SPI.h"
+#if defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT)
+#include "fsl_spi_dma.h"
+#endif
+
+#if defined(SPI0) && defined(RTE_SPI0) && RTE_SPI0
+extern ARM_DRIVER_SPI Driver_SPI0;
+#endif /* SPI0 */
+
+#if defined(SPI1) && defined(RTE_SPI1) && RTE_SPI1
+extern ARM_DRIVER_SPI Driver_SPI1;
+#endif /* SPI1 */
+
+#if defined(SPI2) && defined(RTE_SPI2) && RTE_SPI2
+extern ARM_DRIVER_SPI Driver_SPI2;
+#endif /* SPI2 */
+
+#if defined(SPI3) && defined(RTE_SPI3) && RTE_SPI3
+extern ARM_DRIVER_SPI Driver_SPI3;
+#endif /* SPI3 */
+
+#if defined(SPI4) && defined(RTE_SPI4) && RTE_SPI4
+extern ARM_DRIVER_SPI Driver_SPI4;
+#endif /* SPI4 */
+
+#if defined(SPI5) && defined(RTE_SPI5) && RTE_SPI5
+extern ARM_DRIVER_SPI Driver_SPI5;
+#endif /* SPI5 */
+
+#if defined(SPI6) && defined(RTE_SPI6) && RTE_SPI6
+extern ARM_DRIVER_SPI Driver_SPI6;
+#endif /* SPI6 */
+
+#if defined(SPI7) && defined(RTE_SPI7) && RTE_SPI7
+extern ARM_DRIVER_SPI Driver_SPI7;
+#endif /* SPI7 */
+
+#if defined(SPI8) && defined(RTE_SPI8) && RTE_SPI8
+extern ARM_DRIVER_SPI Driver_SPI8;
+#endif /* SPI8 */
+
+#if defined(SPI9) && defined(RTE_SPI9) && RTE_SPI9
+extern ARM_DRIVER_SPI Driver_SPI9;
+#endif /* SPI9 */
+
+#if defined(SPI10) && defined(RTE_SPI10) && RTE_SPI10
+extern ARM_DRIVER_SPI Driver_SPI10;
+#endif /* SPI10 */
+
+#if defined(SPI11) && defined(RTE_SPI11) && RTE_SPI11
+extern ARM_DRIVER_SPI Driver_SPI11;
+#endif /* SPI11 */
+
+#if defined(SPI12) && defined(RTE_SPI12) && RTE_SPI12
+extern ARM_DRIVER_SPI Driver_SPI12;
+#endif /* SPI12 */
+
+#if defined(SPI13) && defined(RTE_SPI13) && RTE_SPI13
+extern ARM_DRIVER_SPI Driver_SPI13;
+#endif /* SPI13 */
+
+#define SPI_FLAG_UNINIT     (0UL)
+#define SPI_FLAG_INIT       (1UL << 0)
+#define SPI_FLAG_POWER      (1UL << 1)
+#define SPI_FLAG_CONFIGURED (1UL << 2)
+#define SPI_FLAG_MASTER     (1UL << 3)
+
+#endif

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_usart_cmsis.c

@@ -0,0 +1,3743 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
+ * Copyright 2016-2017, 2020 NXP. Not a Contribution.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "fsl_usart_cmsis.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_cmsis"
+#endif
+
+#if ((defined(RTE_USART0) && RTE_USART0) || (defined(RTE_USART1) && RTE_USART1) ||     \
+     (defined(RTE_USART2) && RTE_USART2) || (defined(RTE_USART3) && RTE_USART3) ||     \
+     (defined(RTE_USART4) && RTE_USART4) || (defined(RTE_USART5) && RTE_USART5) ||     \
+     (defined(RTE_USART6) && RTE_USART6) || (defined(RTE_USART7) && RTE_USART7) ||     \
+     (defined(RTE_USART8) && RTE_USART8) || (defined(RTE_USART9) && RTE_USART9) ||     \
+     (defined(RTE_USART10) && RTE_USART10) || (defined(RTE_USART11) && RTE_USART11) || \
+     (defined(RTE_USART12) && RTE_USART12) || (defined(RTE_USART13) && RTE_USART13))
+
+#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (3))
+
+/*
+ * ARMCC does not support split the data section automatically, so the driver
+ * needs to split the data to separate sections explicitly, to reduce codesize.
+ */
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#define ARMCC_SECTION(section_name) __attribute__((section(section_name)))
+#endif
+
+typedef const struct _cmsis_usart_resource
+{
+    USART_Type *base;          /*!< usart peripheral base address.       */
+    uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */
+} cmsis_usart_resource_t;
+
+typedef struct _cmsis_usart_non_blocking_driver_state
+{
+    cmsis_usart_resource_t *resource; /*!< Basic usart resource.      */
+    usart_handle_t *handle;           /*!< Interupt transfer handle.  */
+    ARM_USART_SignalEvent_t cb_event; /*!< Callback function.         */
+    uint8_t flags;                    /*!< Control and state flags. */
+} cmsis_usart_non_blocking_driver_state_t;
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+typedef const struct _cmsis_usart_dma_resource
+{
+    DMA_Type *txDmaBase;   /*!< DMA peripheral base address for TX.   */
+    uint32_t txDmaChannel; /*!< DMA channel for usart TX.             */
+
+    DMA_Type *rxDmaBase;   /*!< DMA peripheral base address for RX.   */
+    uint32_t rxDmaChannel; /*!< DMA channel for usart RX.             */
+} cmsis_usart_dma_resource_t;
+
+typedef struct _cmsis_usart_dma_driver_state
+{
+    cmsis_usart_resource_t *resource;        /*!< usart basic resource.       */
+    cmsis_usart_dma_resource_t *dmaResource; /*!< usart DMA resource.         */
+    usart_dma_handle_t *handle;              /*!< usart DMA transfer handle.  */
+    dma_handle_t *rxHandle;                  /*!< DMA RX handle.              */
+    dma_handle_t *txHandle;                  /*!< DMA TX handle.              */
+    ARM_USART_SignalEvent_t cb_event;        /*!< Callback function.          */
+    uint8_t flags;                           /*!< Control and state flags. */
+} cmsis_usart_dma_driver_state_t;
+#endif
+
+enum _usart_transfer_states
+{
+    kUSART_TxIdle, /*!< TX idle. */
+    kUSART_TxBusy, /*!< TX busy. */
+    kUSART_RxIdle, /*!< RX idle. */
+    kUSART_RxBusy  /*!< RX busy. */
+};
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION s_usartDriverVersion = {ARM_USART_API_VERSION, ARM_USART_DRV_VERSION};
+
+static const ARM_USART_CAPABILITIES s_usartDriverCapabilities = {
+    1, /* supports usart (Asynchronous) mode */
+    0, /* supports Synchronous Master mode */
+    0, /* supports Synchronous Slave mode */
+    0, /* supports usart Single-wire mode */
+    0, /* supports usart IrDA mode */
+    0, /* supports usart Smart Card mode */
+    0, /* Smart Card Clock generator */
+    0, /* RTS Flow Control available */
+    0, /* CTS Flow Control available */
+    0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */
+    0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */
+    0, /* RTS Line: 0=not available, 1=available */
+    0, /* CTS Line: 0=not available, 1=available */
+    0, /* DTR Line: 0=not available, 1=available */
+    0, /* DSR Line: 0=not available, 1=available */
+    0, /* DCD Line: 0=not available, 1=available */
+    0, /* RI Line: 0=not available, 1=available */
+    0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */
+    0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */
+    0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */
+    0, /* Signal RI change event: \ref ARM_USART_EVENT_RI */
+};
+
+/*
+ * Common control function used by usart_NonBlockingControl/usart_DmaControl/usart_EdmaControl
+ */
+static int32_t USART_CommonControl(uint32_t control,
+                                   uint32_t arg,
+                                   cmsis_usart_resource_t *resource,
+                                   uint8_t *isConfigured)
+{
+    usart_config_t config;
+
+    USART_GetDefaultConfig(&config);
+    int32_t result  = ARM_DRIVER_OK;
+    bool isContinue = false;
+
+    switch (control & ARM_USART_CONTROL_Msk)
+    {
+        case ARM_USART_MODE_ASYNCHRONOUS:
+            /* USART Baudrate */
+            config.baudRate_Bps = arg;
+            isContinue          = true;
+            break;
+
+        /* TX/RX IO is controlled in application layer. */
+        case ARM_USART_CONTROL_TX:
+            if (arg != 0U)
+            {
+                config.enableTx = true;
+            }
+            else
+            {
+                config.enableTx = false;
+            }
+            result = ARM_DRIVER_OK;
+            break;
+
+        case ARM_USART_CONTROL_RX:
+            if (arg != 0U)
+            {
+                config.enableRx = true;
+            }
+            else
+            {
+                config.enableRx = false;
+            }
+
+            result = ARM_DRIVER_OK;
+            break;
+
+        default:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+    }
+    if (!isContinue)
+    {
+        return result;
+    }
+
+    switch (control & ARM_USART_PARITY_Msk)
+    {
+        case ARM_USART_PARITY_NONE:
+            config.parityMode = kUSART_ParityDisabled;
+            break;
+        case ARM_USART_PARITY_EVEN:
+            config.parityMode = kUSART_ParityEven;
+            break;
+        case ARM_USART_PARITY_ODD:
+            config.parityMode = kUSART_ParityOdd;
+            break;
+        default:
+            result = ARM_USART_ERROR_PARITY;
+            break;
+    }
+
+    if (result == ARM_USART_ERROR_PARITY)
+    {
+        return result;
+    }
+
+    switch (control & ARM_USART_STOP_BITS_Msk)
+    {
+        case ARM_USART_STOP_BITS_1:
+            /* The GetDefaultConfig has already set for this case. */
+            break;
+        case ARM_USART_STOP_BITS_2:
+            config.stopBitCount = kUSART_TwoStopBit;
+            break;
+        default:
+            result = ARM_USART_ERROR_STOP_BITS;
+            break;
+    }
+    if (result == ARM_USART_ERROR_STOP_BITS)
+    {
+        return result;
+    }
+
+    /* If usart is already configured, deinit it first. */
+    if (((*isConfigured) & (uint8_t)USART_FLAG_CONFIGURED) != 0U)
+    {
+        USART_Deinit(resource->base);
+        *isConfigured &= ~(uint8_t)USART_FLAG_CONFIGURED;
+    }
+
+    config.enableTx = true;
+    config.enableRx = true;
+
+    if (kStatus_USART_BaudrateNotSupport == USART_Init(resource->base, &config, resource->GetFreq()))
+    {
+        result = ARM_USART_ERROR_BAUDRATE;
+    }
+    else
+    {
+        *isConfigured |= (uint8_t)USART_FLAG_CONFIGURED;
+    }
+
+    return result;
+}
+
+static ARM_DRIVER_VERSION USARTx_GetVersion(void)
+{
+    return s_usartDriverVersion;
+}
+
+static ARM_USART_CAPABILITIES USARTx_GetCapabilities(void)
+{
+    return s_usartDriverCapabilities;
+}
+
+static int32_t USARTx_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+    return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS USARTx_GetModemStatus(void)
+{
+    ARM_USART_MODEM_STATUS modem_status = {0};
+
+    modem_status.cts      = 0U;
+    modem_status.dsr      = 0U;
+    modem_status.ri       = 0U;
+    modem_status.dcd      = 0U;
+    modem_status.reserved = 0U;
+
+    return modem_status;
+}
+
+#endif
+
+#if ((defined(RTE_USART0_DMA_EN) && RTE_USART0_DMA_EN) || (defined(RTE_USART1_DMA_EN) && RTE_USART1_DMA_EN) ||     \
+     (defined(RTE_USART2_DMA_EN) && RTE_USART2_DMA_EN) || (defined(RTE_USART3_DMA_EN) && RTE_USART3_DMA_EN) ||     \
+     (defined(RTE_USART4_DMA_EN) && RTE_USART4_DMA_EN) || (defined(RTE_USART5_DMA_EN) && RTE_USART5_DMA_EN) ||     \
+     (defined(RTE_USART6_DMA_EN) && RTE_USART6_DMA_EN) || (defined(RTE_USART7_DMA_EN) && RTE_USART7_DMA_EN) ||     \
+     (defined(RTE_USART8_DMA_EN) && RTE_USART8_DMA_EN) || (defined(RTE_USART9_DMA_EN) && RTE_USART9_DMA_EN) ||     \
+     (defined(RTE_USART10_DMA_EN) && RTE_USART10_DMA_EN) || (defined(RTE_USART11_DMA_EN) && RTE_USART11_DMA_EN) || \
+     (defined(RTE_USART12_DMA_EN) && RTE_USART12_DMA_EN) || (defined(RTE_USART13_DMA_EN) && RTE_USART13_DMA_EN))
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+static void KSDK_USART_DmaCallback(USART_Type *base, usart_dma_handle_t *handle, status_t status, void *userData)
+{
+    uint32_t event = 0U;
+
+    if (kStatus_USART_TxIdle == status)
+    {
+        event = ARM_USART_EVENT_SEND_COMPLETE;
+    }
+
+    if (kStatus_USART_RxIdle == status)
+    {
+        event = ARM_USART_EVENT_RECEIVE_COMPLETE;
+    }
+    else
+    {
+        /* Avoid MISRA 2012 15.7 violation */
+    }
+
+    /* User data is actually CMSIS driver callback. */
+    if (userData != NULL)
+    {
+        ((ARM_USART_SignalEvent_t)userData)(event);
+    }
+}
+
+static int32_t USART_DmaInitialize(ARM_USART_SignalEvent_t cb_event, cmsis_usart_dma_driver_state_t *usart)
+{
+    if (0U == (usart->flags & USART_FLAG_INIT))
+    {
+        usart->cb_event = cb_event;
+        usart->flags    = (uint8_t)USART_FLAG_INIT;
+    }
+
+    return ARM_DRIVER_OK;
+}
+
+static int32_t USART_DmaUninitialize(cmsis_usart_dma_driver_state_t *usart)
+{
+    usart->flags = (uint8_t)USART_FLAG_UNINIT;
+    return ARM_DRIVER_OK;
+}
+
+static int32_t USART_DmaPowerControl(ARM_POWER_STATE state, cmsis_usart_dma_driver_state_t *usart)
+{
+    usart_config_t config;
+    int32_t result = ARM_DRIVER_OK;
+
+    switch (state)
+    {
+        case ARM_POWER_OFF:
+            if ((usart->flags & (uint8_t)USART_FLAG_POWER) != 0U)
+            {
+                USART_Deinit(usart->resource->base);
+                DMA_DisableChannel(usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel);
+                DMA_DisableChannel(usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel);
+                usart->flags = (uint8_t)USART_FLAG_INIT;
+            }
+            break;
+        case ARM_POWER_LOW:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+        case ARM_POWER_FULL:
+            /* Must be initialized first. */
+            if (usart->flags == (uint8_t)USART_FLAG_UNINIT)
+            {
+                result = ARM_DRIVER_ERROR;
+                break;
+            }
+
+            if ((usart->flags & (uint8_t)USART_FLAG_POWER) != 0U)
+            {
+                /* Driver already powered */
+                break;
+            }
+
+            USART_GetDefaultConfig(&config);
+            config.enableTx = true;
+            config.enableRx = true;
+
+            /* Set up DMA setting. */
+            DMA_EnableChannel(usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel);
+            DMA_EnableChannel(usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel);
+
+            DMA_CreateHandle(usart->rxHandle, usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel);
+            DMA_CreateHandle(usart->txHandle, usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel);
+
+            /* Setup the usart. */
+            (void)USART_Init(usart->resource->base, &config, usart->resource->GetFreq());
+            (void)USART_TransferCreateHandleDMA(usart->resource->base, usart->handle, KSDK_USART_DmaCallback,
+                                                (void *)usart->cb_event, usart->txHandle, usart->rxHandle);
+
+            usart->flags |= ((uint8_t)USART_FLAG_POWER | (uint8_t)USART_FLAG_CONFIGURED);
+            break;
+        default:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+    }
+
+    return result;
+}
+
+static int32_t USART_DmaSend(const void *data, uint32_t num, cmsis_usart_dma_driver_state_t *usart)
+{
+    int32_t ret;
+    status_t status;
+    usart_transfer_t xfer;
+
+    xfer.txData   = (const uint8_t *)data;
+    xfer.dataSize = num;
+
+    status = USART_TransferSendDMA(usart->resource->base, usart->handle, &xfer);
+
+    switch (status)
+    {
+        case kStatus_Success:
+            ret = ARM_DRIVER_OK;
+            break;
+        case kStatus_InvalidArgument:
+            ret = ARM_DRIVER_ERROR_PARAMETER;
+            break;
+        case kStatus_USART_TxBusy:
+            ret = ARM_DRIVER_ERROR_BUSY;
+            break;
+        default:
+            ret = ARM_DRIVER_ERROR;
+            break;
+    }
+
+    return ret;
+}
+
+static int32_t USART_DmaReceive(void *data, uint32_t num, cmsis_usart_dma_driver_state_t *usart)
+{
+    int32_t ret;
+    status_t status;
+    usart_transfer_t xfer;
+
+    xfer.rxData   = (uint8_t *)data;
+    xfer.dataSize = num;
+
+    status = USART_TransferReceiveDMA(usart->resource->base, usart->handle, &xfer);
+
+    switch (status)
+    {
+        case kStatus_Success:
+            ret = ARM_DRIVER_OK;
+            break;
+        case kStatus_InvalidArgument:
+            ret = ARM_DRIVER_ERROR_PARAMETER;
+            break;
+        case kStatus_USART_RxBusy:
+            ret = ARM_DRIVER_ERROR_BUSY;
+            break;
+        default:
+            ret = ARM_DRIVER_ERROR;
+            break;
+    }
+
+    return ret;
+}
+
+static int32_t USART_DmaTransfer(const void *data_out,
+                                 void *data_in,
+                                 uint32_t num,
+                                 cmsis_usart_dma_driver_state_t *usart)
+{
+    /* Only in synchronous mode */
+    return ARM_DRIVER_ERROR;
+}
+
+static uint32_t USART_DmaGetTxCount(cmsis_usart_dma_driver_state_t *usart)
+{
+    uint32_t cnt;
+
+    /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */
+    if (kStatus_NoTransferInProgress == USART_TransferGetSendCountDMA(usart->resource->base, usart->handle, &cnt))
+    {
+        cnt = usart->handle->txDataSizeAll;
+    }
+
+    return cnt;
+}
+
+static uint32_t USART_DmaGetRxCount(cmsis_usart_dma_driver_state_t *usart)
+{
+    uint32_t cnt;
+
+    if (kStatus_NoTransferInProgress == USART_TransferGetReceiveCountDMA(usart->resource->base, usart->handle, &cnt))
+    {
+        cnt = usart->handle->rxDataSizeAll;
+    }
+
+    return cnt;
+}
+
+static int32_t USART_DmaControl(uint32_t control, uint32_t arg, cmsis_usart_dma_driver_state_t *usart)
+{
+    int32_t result  = ARM_DRIVER_OK;
+    bool isContinue = false;
+    /* Must be power on. */
+    if (0U == (usart->flags & (uint8_t)USART_FLAG_POWER))
+    {
+        return ARM_DRIVER_ERROR;
+    }
+
+    /* Does not support these features. */
+    if ((control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) != 0U)
+    {
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+
+    switch (control & ARM_USART_CONTROL_Msk)
+    {
+        /* Abort Send */
+        case ARM_USART_ABORT_SEND:
+            USART_EnableTxDMA(usart->resource->base, false);
+            DMA_AbortTransfer(usart->handle->txDmaHandle);
+            usart->handle->txState = (uint8_t)kUSART_TxIdle;
+            result                 = ARM_DRIVER_OK;
+            break;
+
+        /* Abort receive */
+        case ARM_USART_ABORT_RECEIVE:
+            USART_EnableRxDMA(usart->resource->base, false);
+            DMA_AbortTransfer(usart->handle->rxDmaHandle);
+            usart->handle->rxState = (uint8_t)kUSART_RxIdle;
+            result                 = ARM_DRIVER_OK;
+            break;
+
+        default:
+            isContinue = true;
+            break;
+    }
+    if (isContinue)
+    {
+        result = USART_CommonControl(control, arg, usart->resource, &usart->flags);
+    }
+    return result;
+}
+
+static ARM_USART_STATUS USART_DmaGetStatus(cmsis_usart_dma_driver_state_t *usart)
+{
+    ARM_USART_STATUS stat      = {0};
+    uint32_t ksdk_usart_status = usart->resource->base->STAT;
+
+    stat.tx_busy = (((uint8_t)kUSART_TxBusy == usart->handle->txState) ? (1U) : (0U));
+    stat.rx_busy = (((uint8_t)kUSART_RxBusy == usart->handle->rxState) ? (1U) : (0U));
+
+    stat.tx_underflow = 0U;
+    stat.rx_overflow  = 0U;
+
+    stat.rx_break = (uint32_t)(((ksdk_usart_status & USART_STAT_RXBRK_MASK)) != 0U);
+
+    stat.rx_framing_error = (uint32_t)(((ksdk_usart_status & USART_STAT_FRAMERRINT_MASK)) != 0U);
+    stat.rx_parity_error  = (uint32_t)(((ksdk_usart_status & USART_STAT_PARITYERRINT_MASK)) != 0U);
+    stat.reserved         = 0U;
+
+    return stat;
+}
+#endif
+
+#endif
+
+#if ((defined(RTE_USART0) && RTE_USART0 && !(defined(RTE_USART0_DMA_EN) && RTE_USART0_DMA_EN)) ||     \
+     (defined(RTE_USART1) && RTE_USART1 && !(defined(RTE_USART1_DMA_EN) && RTE_USART1_DMA_EN)) ||     \
+     (defined(RTE_USART2) && RTE_USART2 && !(defined(RTE_USART2_DMA_EN) && RTE_USART2_DMA_EN)) ||     \
+     (defined(RTE_USART3) && RTE_USART3 && !(defined(RTE_USART3_DMA_EN) && RTE_USART3_DMA_EN)) ||     \
+     (defined(RTE_USART4) && RTE_USART4 && !(defined(RTE_USART4_DMA_EN) && RTE_USART4_DMA_EN)) ||     \
+     (defined(RTE_USART5) && RTE_USART5 && !(defined(RTE_USART5_DMA_EN) && RTE_USART5_DMA_EN)) ||     \
+     (defined(RTE_USART6) && RTE_USART6 && !(defined(RTE_USART6_DMA_EN) && RTE_USART6_DMA_EN)) ||     \
+     (defined(RTE_USART7) && RTE_USART7 && !(defined(RTE_USART7_DMA_EN) && RTE_USART7_DMA_EN)) ||     \
+     (defined(RTE_USART8) && RTE_USART8 && !(defined(RTE_USART8_DMA_EN) && RTE_USART8_DMA_EN)) ||     \
+     (defined(RTE_USART9) && RTE_USART9 && !(defined(RTE_USART9_DMA_EN) && RTE_USART9_DMA_EN)) ||     \
+     (defined(RTE_USART10) && RTE_USART10 && !(defined(RTE_USART10_DMA_EN) && RTE_USART10_DMA_EN)) || \
+     (defined(RTE_USART11) && RTE_USART11 && !(defined(RTE_USART11_DMA_EN) && RTE_USART11_DMA_EN)) || \
+     (defined(RTE_USART12) && RTE_USART12 && !(defined(RTE_USART12_DMA_EN) && RTE_USART12_DMA_EN)) || \
+     (defined(RTE_USART13) && RTE_USART13 && !(defined(RTE_USART13_DMA_EN) && RTE_USART13_DMA_EN)))
+
+static void KSDK_USART_NonBlockingCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *userData)
+{
+    uint32_t event = 0U;
+
+    switch (status)
+    {
+        case kStatus_USART_TxIdle:
+            event = ARM_USART_EVENT_SEND_COMPLETE;
+            break;
+        case kStatus_USART_RxIdle:
+            event = ARM_USART_EVENT_RECEIVE_COMPLETE;
+            break;
+        case kStatus_USART_RxError:
+            event = ARM_USART_EVENT_RX_OVERFLOW;
+            break;
+        case kStatus_USART_TxError:
+            event = ARM_USART_EVENT_TX_UNDERFLOW;
+            break;
+        case kStatus_USART_FramingError:
+            event = ARM_USART_EVENT_RX_FRAMING_ERROR;
+            break;
+        case kStatus_USART_ParityError:
+            event = ARM_USART_EVENT_RX_PARITY_ERROR;
+            break;
+        default:
+            /* Avoid MISRA 16.4. */
+            break;
+    }
+
+    /* User data is actually CMSIS driver callback. */
+    if (userData != NULL)
+    {
+        ((ARM_USART_SignalEvent_t)userData)(event);
+    }
+}
+
+static int32_t USART_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event,
+                                           cmsis_usart_non_blocking_driver_state_t *usart)
+{
+    if (0U == (usart->flags & (uint8_t)USART_FLAG_INIT))
+    {
+        usart->cb_event = cb_event;
+        usart->flags    = (uint8_t)USART_FLAG_INIT;
+    }
+
+    return ARM_DRIVER_OK;
+}
+
+static int32_t USART_NonBlockingUninitialize(cmsis_usart_non_blocking_driver_state_t *usart)
+{
+    usart->flags = (uint8_t)USART_FLAG_UNINIT;
+    return ARM_DRIVER_OK;
+}
+
+static int32_t USART_NonBlockingPowerControl(ARM_POWER_STATE state, cmsis_usart_non_blocking_driver_state_t *usart)
+{
+    usart_config_t config;
+    int32_t result = ARM_DRIVER_OK;
+
+    switch (state)
+    {
+        case ARM_POWER_OFF:
+            if ((usart->flags & (uint8_t)USART_FLAG_POWER) != 0U)
+            {
+                USART_Deinit(usart->resource->base);
+                usart->flags = (uint8_t)USART_FLAG_INIT;
+            }
+            break;
+        case ARM_POWER_LOW:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+        case ARM_POWER_FULL:
+            /* Must be initialized first. */
+            if (usart->flags == (uint8_t)USART_FLAG_UNINIT)
+            {
+                result = ARM_DRIVER_ERROR;
+                break;
+            }
+
+            if ((usart->flags & (uint8_t)USART_FLAG_POWER) != 0U)
+            {
+                /* Driver already powered */
+                break;
+            }
+
+            USART_GetDefaultConfig(&config);
+            config.enableTx = true;
+            config.enableRx = true;
+
+            (void)USART_Init(usart->resource->base, &config, usart->resource->GetFreq());
+            (void)USART_TransferCreateHandle(usart->resource->base, usart->handle, KSDK_USART_NonBlockingCallback,
+                                             (void *)usart->cb_event);
+            usart->flags |= ((uint8_t)USART_FLAG_POWER | (uint8_t)USART_FLAG_CONFIGURED);
+
+            break;
+        default:
+            result = ARM_DRIVER_ERROR_UNSUPPORTED;
+            break;
+    }
+
+    return result;
+}
+
+static int32_t USART_NonBlockingSend(const void *data, uint32_t num, cmsis_usart_non_blocking_driver_state_t *usart)
+{
+    int32_t ret;
+    status_t status;
+    usart_transfer_t xfer;
+
+    xfer.txData   = (const uint8_t *)data;
+    xfer.dataSize = num;
+
+    status = USART_TransferSendNonBlocking(usart->resource->base, usart->handle, &xfer);
+
+    switch (status)
+    {
+        case kStatus_Success:
+            ret = ARM_DRIVER_OK;
+            break;
+        case kStatus_InvalidArgument:
+            ret = ARM_DRIVER_ERROR_PARAMETER;
+            break;
+        case kStatus_USART_TxBusy:
+            ret = ARM_DRIVER_ERROR_BUSY;
+            break;
+        default:
+            ret = ARM_DRIVER_ERROR;
+            break;
+    }
+
+    return ret;
+}
+
+static int32_t USART_NonBlockingReceive(void *data, uint32_t num, cmsis_usart_non_blocking_driver_state_t *usart)
+{
+    int32_t ret;
+    status_t status;
+    usart_transfer_t xfer;
+
+    xfer.rxData   = (uint8_t *)data;
+    xfer.dataSize = num;
+
+    status = USART_TransferReceiveNonBlocking(usart->resource->base, usart->handle, &xfer, NULL);
+
+    switch (status)
+    {
+        case kStatus_Success:
+            ret = ARM_DRIVER_OK;
+            break;
+        case kStatus_InvalidArgument:
+            ret = ARM_DRIVER_ERROR_PARAMETER;
+            break;
+        case kStatus_USART_RxBusy:
+            ret = ARM_DRIVER_ERROR_BUSY;
+            break;
+        default:
+            ret = ARM_DRIVER_ERROR;
+            break;
+    }
+
+    return ret;
+}
+
+static int32_t USART_NonBlockingTransfer(const void *data_out,
+                                         void *data_in,
+                                         uint32_t num,
+                                         cmsis_usart_non_blocking_driver_state_t *usart)
+{
+    /* Only in synchronous mode */
+    return ARM_DRIVER_ERROR;
+}
+
+static uint32_t USART_NonBlockingGetTxCount(cmsis_usart_non_blocking_driver_state_t *usart)
+{
+    uint32_t cnt;
+
+    /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */
+    if ((uint8_t)kUSART_TxIdle == usart->handle->txState)
+    {
+        cnt = usart->handle->txDataSizeAll;
+    }
+    else
+    {
+        cnt = usart->handle->txDataSizeAll - usart->handle->txDataSize;
+    }
+
+    return cnt;
+}
+
+static uint32_t USART_NonBlockingGetRxCount(cmsis_usart_non_blocking_driver_state_t *usart)
+{
+    uint32_t cnt;
+
+    if ((uint8_t)kUSART_RxIdle == usart->handle->rxState)
+    {
+        cnt = usart->handle->rxDataSizeAll;
+    }
+    else
+    {
+        cnt = usart->handle->rxDataSizeAll - usart->handle->rxDataSize;
+    }
+
+    return cnt;
+}
+
+static int32_t USART_NonBlockingControl(uint32_t control, uint32_t arg, cmsis_usart_non_blocking_driver_state_t *usart)
+{
+    int32_t result  = ARM_DRIVER_OK;
+    bool isContinue = false;
+    /* Must be power on. */
+    if (0U == (usart->flags & (uint8_t)USART_FLAG_POWER))
+    {
+        return ARM_DRIVER_ERROR;
+    }
+
+    /* Does not support these features. */
+    if ((control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) != 0U)
+    {
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+
+    switch (control & ARM_USART_CONTROL_Msk)
+    {
+        /* Abort Send */
+        case ARM_USART_ABORT_SEND:
+            usart->resource->base->FIFOINTENSET &= ~USART_FIFOINTENSET_TXLVL_MASK;
+            usart->handle->txDataSize = 0;
+            usart->handle->txState    = (uint8_t)kUSART_TxIdle;
+            result                    = ARM_DRIVER_OK;
+            break;
+
+        /* Abort receive */
+        case ARM_USART_ABORT_RECEIVE:
+            usart->resource->base->FIFOINTENSET &= ~USART_FIFOINTENSET_RXLVL_MASK;
+            usart->handle->rxDataSize = 0U;
+            usart->handle->rxState    = (uint8_t)kUSART_RxIdle;
+            result                    = ARM_DRIVER_OK;
+            break;
+
+        default:
+            isContinue = true;
+            break;
+    }
+
+    if (isContinue)
+    {
+        result = USART_CommonControl(control, arg, usart->resource, &usart->flags);
+    }
+    return result;
+}
+
+static ARM_USART_STATUS USART_NonBlockingGetStatus(cmsis_usart_non_blocking_driver_state_t *usart)
+{
+    ARM_USART_STATUS stat      = {0};
+    uint32_t ksdk_usart_status = usart->resource->base->STAT;
+
+    stat.tx_busy = (((uint8_t)kUSART_TxBusy == usart->handle->txState) ? (1U) : (0U));
+    stat.rx_busy = (((uint8_t)kUSART_RxBusy == usart->handle->rxState) ? (1U) : (0U));
+
+    stat.tx_underflow = 0U;
+    stat.rx_overflow  = 0U;
+
+    stat.rx_break = (uint32_t)(((ksdk_usart_status & (uint32_t)USART_STAT_RXBRK_MASK)) != 0U);
+
+    stat.rx_framing_error = (uint32_t)(((ksdk_usart_status & USART_STAT_FRAMERRINT_MASK)) != 0U);
+    stat.rx_parity_error  = (uint32_t)(((ksdk_usart_status & USART_STAT_PARITYERRINT_MASK)) != 0U);
+    stat.reserved         = 0U;
+
+    return stat;
+}
+
+#endif
+
+#if defined(USART0) && defined(RTE_USART0) && RTE_USART0
+
+/* User needs to provide the implementation for USART0_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t USART0_GetFreq(void);
+
+static cmsis_usart_resource_t usart0_Resource = {USART0, USART0_GetFreq};
+
+/* usart0 Driver Control Block */
+
+#if defined(RTE_USART0_DMA_EN) && RTE_USART0_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+static cmsis_usart_dma_resource_t usart0_DmaResource = {
+    RTE_USART0_DMA_TX_DMA_BASE,
+    RTE_USART0_DMA_TX_CH,
+    RTE_USART0_DMA_RX_DMA_BASE,
+    RTE_USART0_DMA_RX_CH,
+};
+
+static usart_dma_handle_t USART0_DmaHandle;
+static dma_handle_t USART0_DmaRxHandle;
+static dma_handle_t USART0_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart0_dma_driver_state")
+static cmsis_usart_dma_driver_state_t usart0_DmaDriverState = {
+#else
+static cmsis_usart_dma_driver_state_t usart0_DmaDriverState  = {
+#endif
+    &usart0_Resource, &usart0_DmaResource, &USART0_DmaHandle, &USART0_DmaRxHandle, &USART0_DmaTxHandle,
+};
+
+static int32_t USART0_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART0_PIN_INIT
+    RTE_USART0_PIN_INIT();
+#endif
+    return USART_DmaInitialize(cb_event, &usart0_DmaDriverState);
+}
+
+static int32_t USART0_DmaUninitialize(void)
+{
+#ifdef RTE_USART0_PIN_DEINIT
+    RTE_USART0_PIN_DEINIT();
+#endif
+    return USART_DmaUninitialize(&usart0_DmaDriverState);
+}
+
+static int32_t USART0_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return USART_DmaPowerControl(state, &usart0_DmaDriverState);
+}
+
+static int32_t USART0_DmaSend(const void *data, uint32_t num)
+{
+    return USART_DmaSend(data, num, &usart0_DmaDriverState);
+}
+
+static int32_t USART0_DmaReceive(void *data, uint32_t num)
+{
+    return USART_DmaReceive(data, num, &usart0_DmaDriverState);
+}
+
+static int32_t USART0_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_DmaTransfer(data_out, data_in, num, &usart0_DmaDriverState);
+}
+
+static uint32_t USART0_DmaGetTxCount(void)
+{
+    return USART_DmaGetTxCount(&usart0_DmaDriverState);
+}
+
+static uint32_t USART0_DmaGetRxCount(void)
+{
+    return USART_DmaGetRxCount(&usart0_DmaDriverState);
+}
+
+static int32_t USART0_DmaControl(uint32_t control, uint32_t arg)
+{
+    return USART_DmaControl(control, arg, &usart0_DmaDriverState);
+}
+
+static ARM_USART_STATUS USART0_DmaGetStatus(void)
+{
+    return USART_DmaGetStatus(&usart0_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static usart_handle_t USART0_Handle;
+#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1)
+static uint8_t usart0_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart0_non_blocking_driver_state")
+static cmsis_usart_non_blocking_driver_state_t usart0_NonBlockingDriverState = {
+#else
+static cmsis_usart_non_blocking_driver_state_t usart0_NonBlockingDriverState  = {
+#endif
+    &usart0_Resource,
+    &USART0_Handle,
+};
+
+static int32_t USART0_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART0_PIN_INIT
+    RTE_USART0_PIN_INIT();
+#endif
+    return USART_NonBlockingInitialize(cb_event, &usart0_NonBlockingDriverState);
+}
+
+static int32_t USART0_NonBlockingUninitialize(void)
+{
+#ifdef RTE_USART0_PIN_DEINIT
+    RTE_USART0_PIN_DEINIT();
+#endif
+    return USART_NonBlockingUninitialize(&usart0_NonBlockingDriverState);
+}
+
+static int32_t USART0_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+    int32_t result;
+
+    result = USART_NonBlockingPowerControl(state, &usart0_NonBlockingDriverState);
+#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1)
+    if ((state == ARM_POWER_FULL) && (usart0_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+    {
+        USART_TransferStartRingBuffer(usart0_NonBlockingDriverState.resource->base,
+                                      usart0_NonBlockingDriverState.handle, usart0_rxRingBuffer, USART_RX_BUFFER_LEN);
+    }
+#endif
+    return result;
+}
+
+static int32_t USART0_NonBlockingSend(const void *data, uint32_t num)
+{
+    return USART_NonBlockingSend(data, num, &usart0_NonBlockingDriverState);
+}
+
+static int32_t USART0_NonBlockingReceive(void *data, uint32_t num)
+{
+    return USART_NonBlockingReceive(data, num, &usart0_NonBlockingDriverState);
+}
+
+static int32_t USART0_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_NonBlockingTransfer(data_out, data_in, num, &usart0_NonBlockingDriverState);
+}
+
+static uint32_t USART0_NonBlockingGetTxCount(void)
+{
+    return USART_NonBlockingGetTxCount(&usart0_NonBlockingDriverState);
+}
+
+static uint32_t USART0_NonBlockingGetRxCount(void)
+{
+    return USART_NonBlockingGetRxCount(&usart0_NonBlockingDriverState);
+}
+
+static int32_t USART0_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+    int32_t result;
+
+    result = USART_NonBlockingControl(control, arg, &usart0_NonBlockingDriverState);
+    if (ARM_DRIVER_OK != result)
+    {
+        return result;
+    }
+#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1)
+    /* Start receiving interrupts */
+    usart0_NonBlockingDriverState.resource->base->FIFOINTENSET |=
+        USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+#endif
+    return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS USART0_NonBlockingGetStatus(void)
+{
+    return USART_NonBlockingGetStatus(&usart0_NonBlockingDriverState);
+}
+
+#endif
+
+ARM_DRIVER_USART Driver_USART0 = {
+    USARTx_GetVersion,      USARTx_GetCapabilities,
+#if RTE_USART0_DMA_EN
+    USART0_DmaInitialize,   USART0_DmaUninitialize, USART0_DmaPowerControl, USART0_DmaSend,    USART0_DmaReceive,
+    USART0_DmaTransfer,     USART0_DmaGetTxCount,   USART0_DmaGetRxCount,   USART0_DmaControl, USART0_DmaGetStatus,
+#else
+    USART0_NonBlockingInitialize,
+    USART0_NonBlockingUninitialize,
+    USART0_NonBlockingPowerControl,
+    USART0_NonBlockingSend,
+    USART0_NonBlockingReceive,
+    USART0_NonBlockingTransfer,
+    USART0_NonBlockingGetTxCount,
+    USART0_NonBlockingGetRxCount,
+    USART0_NonBlockingControl,
+    USART0_NonBlockingGetStatus,
+#endif
+    USARTx_SetModemControl, USARTx_GetModemStatus};
+
+#endif /* usart0 */
+
+#if defined(USART1) && defined(RTE_USART1) && RTE_USART1
+
+/* User needs to provide the implementation for USART1_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t USART1_GetFreq(void);
+
+static cmsis_usart_resource_t usart1_Resource = {USART1, USART1_GetFreq};
+
+#if defined(RTE_USART1_DMA_EN) && RTE_USART1_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_usart_dma_resource_t usart1_DmaResource = {
+    RTE_USART1_DMA_TX_DMA_BASE,
+    RTE_USART1_DMA_TX_CH,
+    RTE_USART1_DMA_RX_DMA_BASE,
+    RTE_USART1_DMA_RX_CH,
+};
+
+static usart_dma_handle_t USART1_DmaHandle;
+static dma_handle_t USART1_DmaRxHandle;
+static dma_handle_t USART1_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart1_dma_driver_state")
+static cmsis_usart_dma_driver_state_t usart1_DmaDriverState = {
+#else
+static cmsis_usart_dma_driver_state_t usart1_DmaDriverState  = {
+#endif
+    &usart1_Resource, &usart1_DmaResource, &USART1_DmaHandle, &USART1_DmaRxHandle, &USART1_DmaTxHandle,
+};
+
+static int32_t USART1_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART1_PIN_INIT
+    RTE_USART1_PIN_INIT();
+#endif
+    return USART_DmaInitialize(cb_event, &usart1_DmaDriverState);
+}
+
+static int32_t USART1_DmaUninitialize(void)
+{
+#ifdef RTE_USART1_PIN_DEINIT
+    RTE_USART1_PIN_DEINIT();
+#endif
+    return USART_DmaUninitialize(&usart1_DmaDriverState);
+}
+
+static int32_t USART1_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return USART_DmaPowerControl(state, &usart1_DmaDriverState);
+}
+
+static int32_t USART1_DmaSend(const void *data, uint32_t num)
+{
+    return USART_DmaSend(data, num, &usart1_DmaDriverState);
+}
+
+static int32_t USART1_DmaReceive(void *data, uint32_t num)
+{
+    return USART_DmaReceive(data, num, &usart1_DmaDriverState);
+}
+
+static int32_t USART1_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_DmaTransfer(data_out, data_in, num, &usart1_DmaDriverState);
+}
+
+static uint32_t USART1_DmaGetTxCount(void)
+{
+    return USART_DmaGetTxCount(&usart1_DmaDriverState);
+}
+
+static uint32_t USART1_DmaGetRxCount(void)
+{
+    return USART_DmaGetRxCount(&usart1_DmaDriverState);
+}
+
+static int32_t USART1_DmaControl(uint32_t control, uint32_t arg)
+{
+    return USART_DmaControl(control, arg, &usart1_DmaDriverState);
+}
+
+static ARM_USART_STATUS USART1_DmaGetStatus(void)
+{
+    return USART_DmaGetStatus(&usart1_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static usart_handle_t USART1_Handle;
+#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1)
+static uint8_t usart1_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart1_non_blocking_driver_state")
+static cmsis_usart_non_blocking_driver_state_t usart1_NonBlockingDriverState = {
+#else
+static cmsis_usart_non_blocking_driver_state_t usart1_NonBlockingDriverState  = {
+#endif
+    &usart1_Resource,
+    &USART1_Handle,
+};
+
+static int32_t USART1_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART1_PIN_INIT
+    RTE_USART1_PIN_INIT();
+#endif
+    return USART_NonBlockingInitialize(cb_event, &usart1_NonBlockingDriverState);
+}
+
+static int32_t USART1_NonBlockingUninitialize(void)
+{
+#ifdef RTE_USART1_PIN_DEINIT
+    RTE_USART1_PIN_DEINIT();
+#endif
+    return USART_NonBlockingUninitialize(&usart1_NonBlockingDriverState);
+}
+
+static int32_t USART1_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+    int32_t result;
+
+    result = USART_NonBlockingPowerControl(state, &usart1_NonBlockingDriverState);
+#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1)
+    if ((state == ARM_POWER_FULL) && (usart1_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+    {
+        USART_TransferStartRingBuffer(usart1_NonBlockingDriverState.resource->base,
+                                      usart1_NonBlockingDriverState.handle, usart1_rxRingBuffer, USART_RX_BUFFER_LEN);
+    }
+#endif
+    return result;
+}
+
+static int32_t USART1_NonBlockingSend(const void *data, uint32_t num)
+{
+    return USART_NonBlockingSend(data, num, &usart1_NonBlockingDriverState);
+}
+
+static int32_t USART1_NonBlockingReceive(void *data, uint32_t num)
+{
+    return USART_NonBlockingReceive(data, num, &usart1_NonBlockingDriverState);
+}
+
+static int32_t USART1_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_NonBlockingTransfer(data_out, data_in, num, &usart1_NonBlockingDriverState);
+}
+
+static uint32_t USART1_NonBlockingGetTxCount(void)
+{
+    return USART_NonBlockingGetTxCount(&usart1_NonBlockingDriverState);
+}
+
+static uint32_t USART1_NonBlockingGetRxCount(void)
+{
+    return USART_NonBlockingGetRxCount(&usart1_NonBlockingDriverState);
+}
+
+static int32_t USART1_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+    int32_t result;
+
+    result = USART_NonBlockingControl(control, arg, &usart1_NonBlockingDriverState);
+    if (ARM_DRIVER_OK != result)
+    {
+        return result;
+    }
+#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1)
+    /* Start receiving interrupts */
+    usart1_NonBlockingDriverState.resource->base->FIFOINTENSET |=
+        USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+#endif
+    return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS USART1_NonBlockingGetStatus(void)
+{
+    return USART_NonBlockingGetStatus(&usart1_NonBlockingDriverState);
+}
+
+#endif
+
+ARM_DRIVER_USART Driver_USART1 = {
+    USARTx_GetVersion,      USARTx_GetCapabilities,
+#if RTE_USART1_DMA_EN
+    USART1_DmaInitialize,   USART1_DmaUninitialize, USART1_DmaPowerControl, USART1_DmaSend,    USART1_DmaReceive,
+    USART1_DmaTransfer,     USART1_DmaGetTxCount,   USART1_DmaGetRxCount,   USART1_DmaControl, USART1_DmaGetStatus,
+#else
+    USART1_NonBlockingInitialize,
+    USART1_NonBlockingUninitialize,
+    USART1_NonBlockingPowerControl,
+    USART1_NonBlockingSend,
+    USART1_NonBlockingReceive,
+    USART1_NonBlockingTransfer,
+    USART1_NonBlockingGetTxCount,
+    USART1_NonBlockingGetRxCount,
+    USART1_NonBlockingControl,
+    USART1_NonBlockingGetStatus,
+#endif
+    USARTx_SetModemControl, USARTx_GetModemStatus};
+
+#endif /* usart1 */
+
+#if defined(USART2) && defined(RTE_USART2) && RTE_USART2
+
+/* User needs to provide the implementation for USART2_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t USART2_GetFreq(void);
+
+static cmsis_usart_resource_t usart2_Resource = {USART2, USART2_GetFreq};
+
+/* usart2 Driver Control Block */
+
+#if defined(RTE_USART2_DMA_EN) && RTE_USART2_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_usart_dma_resource_t usart2_DmaResource = {
+    RTE_USART2_DMA_TX_DMA_BASE,
+    RTE_USART2_DMA_TX_CH,
+    RTE_USART2_DMA_RX_DMA_BASE,
+    RTE_USART2_DMA_RX_CH,
+};
+
+static usart_dma_handle_t USART2_DmaHandle;
+static dma_handle_t USART2_DmaRxHandle;
+static dma_handle_t USART2_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart2_dma_driver_state")
+static cmsis_usart_dma_driver_state_t usart2_DmaDriverState = {
+#else
+static cmsis_usart_dma_driver_state_t usart2_DmaDriverState  = {
+#endif
+    &usart2_Resource, &usart2_DmaResource, &USART2_DmaHandle, &USART2_DmaRxHandle, &USART2_DmaTxHandle,
+};
+
+static int32_t USART2_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART2_PIN_INIT
+    RTE_USART2_PIN_INIT();
+#endif
+    return USART_DmaInitialize(cb_event, &usart2_DmaDriverState);
+}
+
+static int32_t USART2_DmaUninitialize(void)
+{
+#ifdef RTE_USART2_PIN_DEINIT
+    RTE_USART2_PIN_DEINIT();
+#endif
+    return USART_DmaUninitialize(&usart2_DmaDriverState);
+}
+
+static int32_t USART2_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return USART_DmaPowerControl(state, &usart2_DmaDriverState);
+}
+
+static int32_t USART2_DmaSend(const void *data, uint32_t num)
+{
+    return USART_DmaSend(data, num, &usart2_DmaDriverState);
+}
+
+static int32_t USART2_DmaReceive(void *data, uint32_t num)
+{
+    return USART_DmaReceive(data, num, &usart2_DmaDriverState);
+}
+
+static int32_t USART2_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_DmaTransfer(data_out, data_in, num, &usart2_DmaDriverState);
+}
+
+static uint32_t USART2_DmaGetTxCount(void)
+{
+    return USART_DmaGetTxCount(&usart2_DmaDriverState);
+}
+
+static uint32_t USART2_DmaGetRxCount(void)
+{
+    return USART_DmaGetRxCount(&usart2_DmaDriverState);
+}
+
+static int32_t USART2_DmaControl(uint32_t control, uint32_t arg)
+{
+    return USART_DmaControl(control, arg, &usart2_DmaDriverState);
+}
+
+static ARM_USART_STATUS USART2_DmaGetStatus(void)
+{
+    return USART_DmaGetStatus(&usart2_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static usart_handle_t USART2_Handle;
+#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1)
+static uint8_t usart2_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart2_non_blocking_driver_state")
+static cmsis_usart_non_blocking_driver_state_t usart2_NonBlockingDriverState = {
+#else
+static cmsis_usart_non_blocking_driver_state_t usart2_NonBlockingDriverState  = {
+#endif
+    &usart2_Resource,
+    &USART2_Handle,
+};
+
+static int32_t USART2_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART2_PIN_INIT
+    RTE_USART2_PIN_INIT();
+#endif
+    return USART_NonBlockingInitialize(cb_event, &usart2_NonBlockingDriverState);
+}
+
+static int32_t USART2_NonBlockingUninitialize(void)
+{
+#ifdef RTE_USART2_PIN_DEINIT
+    RTE_USART2_PIN_DEINIT();
+#endif
+    return USART_NonBlockingUninitialize(&usart2_NonBlockingDriverState);
+}
+
+static int32_t USART2_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+    int32_t result;
+
+    result = USART_NonBlockingPowerControl(state, &usart2_NonBlockingDriverState);
+#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1)
+    if ((state == ARM_POWER_FULL) && (usart2_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+    {
+        USART_TransferStartRingBuffer(usart2_NonBlockingDriverState.resource->base,
+                                      usart2_NonBlockingDriverState.handle, usart2_rxRingBuffer, USART_RX_BUFFER_LEN);
+    }
+#endif
+    return result;
+}
+
+static int32_t USART2_NonBlockingSend(const void *data, uint32_t num)
+{
+    return USART_NonBlockingSend(data, num, &usart2_NonBlockingDriverState);
+}
+
+static int32_t USART2_NonBlockingReceive(void *data, uint32_t num)
+{
+    return USART_NonBlockingReceive(data, num, &usart2_NonBlockingDriverState);
+}
+
+static int32_t USART2_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_NonBlockingTransfer(data_out, data_in, num, &usart2_NonBlockingDriverState);
+}
+
+static uint32_t USART2_NonBlockingGetTxCount(void)
+{
+    return USART_NonBlockingGetTxCount(&usart2_NonBlockingDriverState);
+}
+
+static uint32_t USART2_NonBlockingGetRxCount(void)
+{
+    return USART_NonBlockingGetRxCount(&usart2_NonBlockingDriverState);
+}
+
+static int32_t USART2_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+    int32_t result;
+
+    result = USART_NonBlockingControl(control, arg, &usart2_NonBlockingDriverState);
+    if (ARM_DRIVER_OK != result)
+    {
+        return result;
+    }
+#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1)
+    /* Start receiving interrupts */
+    usart2_NonBlockingDriverState.resource->base->FIFOINTENSET |=
+        USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+#endif
+    return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS USART2_NonBlockingGetStatus(void)
+{
+    return USART_NonBlockingGetStatus(&usart2_NonBlockingDriverState);
+}
+
+#endif
+
+ARM_DRIVER_USART Driver_USART2 = {
+    USARTx_GetVersion,      USARTx_GetCapabilities,
+#if RTE_USART2_DMA_EN
+    USART2_DmaInitialize,   USART2_DmaUninitialize, USART2_DmaPowerControl, USART2_DmaSend,    USART2_DmaReceive,
+    USART2_DmaTransfer,     USART2_DmaGetTxCount,   USART2_DmaGetRxCount,   USART2_DmaControl, USART2_DmaGetStatus,
+#else
+    USART2_NonBlockingInitialize,
+    USART2_NonBlockingUninitialize,
+    USART2_NonBlockingPowerControl,
+    USART2_NonBlockingSend,
+    USART2_NonBlockingReceive,
+    USART2_NonBlockingTransfer,
+    USART2_NonBlockingGetTxCount,
+    USART2_NonBlockingGetRxCount,
+    USART2_NonBlockingControl,
+    USART2_NonBlockingGetStatus,
+#endif
+    USARTx_SetModemControl, USARTx_GetModemStatus};
+
+#endif /* usart2 */
+
+#if defined(USART3) && defined(RTE_USART3) && RTE_USART3
+
+/* User needs to provide the implementation for USART3_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t USART3_GetFreq(void);
+
+static cmsis_usart_resource_t usart3_Resource = {USART3, USART3_GetFreq};
+
+/* usart3 Driver Control Block */
+#if defined(RTE_USART3_DMA_EN) && RTE_USART3_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_usart_dma_resource_t usart3_DmaResource = {
+    RTE_USART3_DMA_TX_DMA_BASE,
+    RTE_USART3_DMA_TX_CH,
+    RTE_USART3_DMA_RX_DMA_BASE,
+    RTE_USART3_DMA_RX_CH,
+};
+
+static usart_dma_handle_t USART3_DmaHandle;
+static dma_handle_t USART3_DmaRxHandle;
+static dma_handle_t USART3_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart3_dma_driver_state")
+static cmsis_usart_dma_driver_state_t usart3_DmaDriverState = {
+#else
+static cmsis_usart_dma_driver_state_t usart3_DmaDriverState  = {
+#endif
+    &usart3_Resource, &usart3_DmaResource, &USART3_DmaHandle, &USART3_DmaRxHandle, &USART3_DmaTxHandle,
+};
+
+static int32_t USART3_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART3_PIN_INIT
+    RTE_USART3_PIN_INIT();
+#endif
+    return USART_DmaInitialize(cb_event, &usart3_DmaDriverState);
+}
+
+static int32_t USART3_DmaUninitialize(void)
+{
+#ifdef RTE_USART3_PIN_DEINIT
+    RTE_USART3_PIN_DEINIT();
+#endif
+    return USART_DmaUninitialize(&usart3_DmaDriverState);
+}
+
+static int32_t USART3_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return USART_DmaPowerControl(state, &usart3_DmaDriverState);
+}
+
+static int32_t USART3_DmaSend(const void *data, uint32_t num)
+{
+    return USART_DmaSend(data, num, &usart3_DmaDriverState);
+}
+
+static int32_t USART3_DmaReceive(void *data, uint32_t num)
+{
+    return USART_DmaReceive(data, num, &usart3_DmaDriverState);
+}
+
+static int32_t USART3_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_DmaTransfer(data_out, data_in, num, &usart3_DmaDriverState);
+}
+
+static uint32_t USART3_DmaGetTxCount(void)
+{
+    return USART_DmaGetTxCount(&usart3_DmaDriverState);
+}
+
+static uint32_t USART3_DmaGetRxCount(void)
+{
+    return USART_DmaGetRxCount(&usart3_DmaDriverState);
+}
+
+static int32_t USART3_DmaControl(uint32_t control, uint32_t arg)
+{
+    return USART_DmaControl(control, arg, &usart3_DmaDriverState);
+}
+
+static ARM_USART_STATUS USART3_DmaGetStatus(void)
+{
+    return USART_DmaGetStatus(&usart3_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static usart_handle_t USART3_Handle;
+#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1)
+static uint8_t usart3_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart3_non_blocking_driver_state")
+static cmsis_usart_non_blocking_driver_state_t usart3_NonBlockingDriverState = {
+#else
+static cmsis_usart_non_blocking_driver_state_t usart3_NonBlockingDriverState  = {
+#endif
+    &usart3_Resource,
+    &USART3_Handle,
+};
+
+static int32_t USART3_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART3_PIN_INIT
+    RTE_USART3_PIN_INIT();
+#endif
+    return USART_NonBlockingInitialize(cb_event, &usart3_NonBlockingDriverState);
+}
+
+static int32_t USART3_NonBlockingUninitialize(void)
+{
+#ifdef RTE_USART3_PIN_DEINIT
+    RTE_USART3_PIN_DEINIT();
+#endif
+    return USART_NonBlockingUninitialize(&usart3_NonBlockingDriverState);
+}
+
+static int32_t USART3_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+    int32_t result;
+
+    result = USART_NonBlockingPowerControl(state, &usart3_NonBlockingDriverState);
+#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1)
+    if ((state == ARM_POWER_FULL) && (usart3_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+    {
+        USART_TransferStartRingBuffer(usart3_NonBlockingDriverState.resource->base,
+                                      usart3_NonBlockingDriverState.handle, usart3_rxRingBuffer, USART_RX_BUFFER_LEN);
+    }
+#endif
+    return result;
+}
+
+static int32_t USART3_NonBlockingSend(const void *data, uint32_t num)
+{
+    return USART_NonBlockingSend(data, num, &usart3_NonBlockingDriverState);
+}
+
+static int32_t USART3_NonBlockingReceive(void *data, uint32_t num)
+{
+    return USART_NonBlockingReceive(data, num, &usart3_NonBlockingDriverState);
+}
+
+static int32_t USART3_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_NonBlockingTransfer(data_out, data_in, num, &usart3_NonBlockingDriverState);
+}
+
+static uint32_t USART3_NonBlockingGetTxCount(void)
+{
+    return USART_NonBlockingGetTxCount(&usart3_NonBlockingDriverState);
+}
+
+static uint32_t USART3_NonBlockingGetRxCount(void)
+{
+    return USART_NonBlockingGetRxCount(&usart3_NonBlockingDriverState);
+}
+
+static int32_t USART3_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+    int32_t result;
+
+    result = USART_NonBlockingControl(control, arg, &usart3_NonBlockingDriverState);
+    if (ARM_DRIVER_OK != result)
+    {
+        return result;
+    }
+#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1)
+    /* Start receiving interrupts */
+    usart3_NonBlockingDriverState.resource->base->FIFOINTENSET |=
+        USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+#endif
+    return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS USART3_NonBlockingGetStatus(void)
+{
+    return USART_NonBlockingGetStatus(&usart3_NonBlockingDriverState);
+}
+
+#endif
+
+ARM_DRIVER_USART Driver_USART3 = {
+    USARTx_GetVersion,      USARTx_GetCapabilities,
+#if RTE_USART3_DMA_EN
+    USART3_DmaInitialize,   USART3_DmaUninitialize, USART3_DmaPowerControl, USART3_DmaSend,    USART3_DmaReceive,
+    USART3_DmaTransfer,     USART3_DmaGetTxCount,   USART3_DmaGetRxCount,   USART3_DmaControl, USART3_DmaGetStatus,
+#else
+    USART3_NonBlockingInitialize,
+    USART3_NonBlockingUninitialize,
+    USART3_NonBlockingPowerControl,
+    USART3_NonBlockingSend,
+    USART3_NonBlockingReceive,
+    USART3_NonBlockingTransfer,
+    USART3_NonBlockingGetTxCount,
+    USART3_NonBlockingGetRxCount,
+    USART3_NonBlockingControl,
+    USART3_NonBlockingGetStatus,
+#endif
+    USARTx_SetModemControl, USARTx_GetModemStatus};
+
+#endif /* usart3 */
+
+#if defined(USART4) && defined(RTE_USART4) && RTE_USART4
+
+/* User needs to provide the implementation for USART4_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t USART4_GetFreq(void);
+
+static cmsis_usart_resource_t usart4_Resource = {USART4, USART4_GetFreq};
+
+#if defined(RTE_USART4_DMA_EN) && RTE_USART4_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_usart_dma_resource_t usart4_DmaResource = {
+    RTE_USART4_DMA_TX_DMA_BASE,
+    RTE_USART4_DMA_TX_CH,
+    RTE_USART4_DMA_RX_DMA_BASE,
+    RTE_USART4_DMA_RX_CH,
+};
+
+static usart_dma_handle_t USART4_DmaHandle;
+static dma_handle_t USART4_DmaRxHandle;
+static dma_handle_t USART4_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart4_dma_driver_state")
+static cmsis_usart_dma_driver_state_t usart4_DmaDriverState = {
+#else
+static cmsis_usart_dma_driver_state_t usart4_DmaDriverState  = {
+#endif
+    &usart4_Resource, &usart4_DmaResource, &USART4_DmaHandle, &USART4_DmaRxHandle, &USART4_DmaTxHandle,
+};
+
+static int32_t USART4_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART4_PIN_INIT
+    RTE_USART4_PIN_INIT();
+#endif
+    return USART_DmaInitialize(cb_event, &usart4_DmaDriverState);
+}
+
+static int32_t USART4_DmaUninitialize(void)
+{
+#ifdef RTE_USART4_PIN_DEINIT
+    RTE_USART4_PIN_DEINIT();
+#endif
+    return USART_DmaUninitialize(&usart4_DmaDriverState);
+}
+
+static int32_t USART4_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return USART_DmaPowerControl(state, &usart4_DmaDriverState);
+}
+
+static int32_t USART4_DmaSend(const void *data, uint32_t num)
+{
+    return USART_DmaSend(data, num, &usart4_DmaDriverState);
+}
+
+static int32_t USART4_DmaReceive(void *data, uint32_t num)
+{
+    return USART_DmaReceive(data, num, &usart4_DmaDriverState);
+}
+
+static int32_t USART4_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_DmaTransfer(data_out, data_in, num, &usart4_DmaDriverState);
+}
+
+static uint32_t USART4_DmaGetTxCount(void)
+{
+    return USART_DmaGetTxCount(&usart4_DmaDriverState);
+}
+
+static uint32_t USART4_DmaGetRxCount(void)
+{
+    return USART_DmaGetRxCount(&usart4_DmaDriverState);
+}
+
+static int32_t USART4_DmaControl(uint32_t control, uint32_t arg)
+{
+    return USART_DmaControl(control, arg, &usart4_DmaDriverState);
+}
+
+static ARM_USART_STATUS USART4_DmaGetStatus(void)
+{
+    return USART_DmaGetStatus(&usart4_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static usart_handle_t USART4_Handle;
+#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1)
+static uint8_t usart4_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart4_non_blocking_driver_state")
+static cmsis_usart_non_blocking_driver_state_t usart4_NonBlockingDriverState = {
+#else
+static cmsis_usart_non_blocking_driver_state_t usart4_NonBlockingDriverState  = {
+#endif
+    &usart4_Resource,
+    &USART4_Handle,
+};
+
+static int32_t USART4_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART4_PIN_INIT
+    RTE_USART4_PIN_INIT();
+#endif
+    return USART_NonBlockingInitialize(cb_event, &usart4_NonBlockingDriverState);
+}
+
+static int32_t USART4_NonBlockingUninitialize(void)
+{
+#ifdef RTE_USART4_PIN_DEINIT
+    RTE_USART4_PIN_DEINIT();
+#endif
+    return USART_NonBlockingUninitialize(&usart4_NonBlockingDriverState);
+}
+
+static int32_t USART4_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+    uint32_t result;
+
+    result = USART_NonBlockingPowerControl(state, &usart4_NonBlockingDriverState);
+#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1)
+    if ((state == ARM_POWER_FULL) && (usart4_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+    {
+        USART_TransferStartRingBuffer(usart4_NonBlockingDriverState.resource->base,
+                                      usart4_NonBlockingDriverState.handle, usart4_rxRingBuffer, USART_RX_BUFFER_LEN);
+    }
+#endif
+    return result;
+}
+
+static int32_t USART4_NonBlockingSend(const void *data, uint32_t num)
+{
+    return USART_NonBlockingSend(data, num, &usart4_NonBlockingDriverState);
+}
+
+static int32_t USART4_NonBlockingReceive(void *data, uint32_t num)
+{
+    return USART_NonBlockingReceive(data, num, &usart4_NonBlockingDriverState);
+}
+
+static int32_t USART4_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_NonBlockingTransfer(data_out, data_in, num, &usart4_NonBlockingDriverState);
+}
+
+static uint32_t USART4_NonBlockingGetTxCount(void)
+{
+    return USART_NonBlockingGetTxCount(&usart4_NonBlockingDriverState);
+}
+
+static uint32_t USART4_NonBlockingGetRxCount(void)
+{
+    return USART_NonBlockingGetRxCount(&usart4_NonBlockingDriverState);
+}
+
+static int32_t USART4_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+    int32_t result;
+
+    result = USART_NonBlockingControl(control, arg, &usart4_NonBlockingDriverState);
+    if (ARM_DRIVER_OK != result)
+    {
+        return result;
+    }
+#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1)
+    /* Start receiving interrupts */
+    usart4_NonBlockingDriverState.resource->base->FIFOINTENSET |=
+        USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+#endif
+    return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS USART4_NonBlockingGetStatus(void)
+{
+    return USART_NonBlockingGetStatus(&usart4_NonBlockingDriverState);
+}
+
+#endif
+
+ARM_DRIVER_USART Driver_USART4 = {
+    USARTx_GetVersion,      USARTx_GetCapabilities,
+#if RTE_USART4_DMA_EN
+    USART4_DmaInitialize,   USART4_DmaUninitialize, USART4_DmaPowerControl, USART4_DmaSend,    USART4_DmaReceive,
+    USART4_DmaTransfer,     USART4_DmaGetTxCount,   USART4_DmaGetRxCount,   USART4_DmaControl, USART4_DmaGetStatus,
+#else
+    USART4_NonBlockingInitialize,
+    USART4_NonBlockingUninitialize,
+    USART4_NonBlockingPowerControl,
+    USART4_NonBlockingSend,
+    USART4_NonBlockingReceive,
+    USART4_NonBlockingTransfer,
+    USART4_NonBlockingGetTxCount,
+    USART4_NonBlockingGetRxCount,
+    USART4_NonBlockingControl,
+    USART4_NonBlockingGetStatus,
+#endif
+    USARTx_SetModemControl, USARTx_GetModemStatus};
+
+#endif /* usart4 */
+
+#if defined(USART5) && defined(RTE_USART5) && RTE_USART5
+
+/* User needs to provide the implementation for USART5_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t USART5_GetFreq(void);
+
+static cmsis_usart_resource_t usart5_Resource = {USART5, USART5_GetFreq};
+
+#if defined(RTE_USART5_DMA_EN) && RTE_USART5_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_usart_dma_resource_t usart5_DmaResource = {
+    RTE_USART5_DMA_TX_DMA_BASE,
+    RTE_USART5_DMA_TX_CH,
+    RTE_USART5_DMA_RX_DMA_BASE,
+    RTE_USART5_DMA_RX_CH,
+};
+
+static usart_dma_handle_t USART5_DmaHandle;
+static dma_handle_t USART5_DmaRxHandle;
+static dma_handle_t USART5_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart5_dma_driver_state")
+static cmsis_usart_dma_driver_state_t usart5_DmaDriverState = {
+#else
+static cmsis_usart_dma_driver_state_t usart5_DmaDriverState  = {
+#endif
+    &usart5_Resource, &usart5_DmaResource, &USART5_DmaHandle, &USART5_DmaRxHandle, &USART5_DmaTxHandle,
+};
+
+static int32_t USART5_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART5_PIN_INIT
+    RTE_USART5_PIN_INIT();
+#endif
+    return USART_DmaInitialize(cb_event, &usart5_DmaDriverState);
+}
+
+static int32_t USART5_DmaUninitialize(void)
+{
+#ifdef RTE_USART5_PIN_DEINIT
+    RTE_USART5_PIN_DEINIT();
+#endif
+    return USART_DmaUninitialize(&usart5_DmaDriverState);
+}
+
+static int32_t USART5_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return USART_DmaPowerControl(state, &usart5_DmaDriverState);
+}
+
+static int32_t USART5_DmaSend(const void *data, uint32_t num)
+{
+    return USART_DmaSend(data, num, &usart5_DmaDriverState);
+}
+
+static int32_t USART5_DmaReceive(void *data, uint32_t num)
+{
+    return USART_DmaReceive(data, num, &usart5_DmaDriverState);
+}
+
+static int32_t USART5_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_DmaTransfer(data_out, data_in, num, &usart5_DmaDriverState);
+}
+
+static uint32_t USART5_DmaGetTxCount(void)
+{
+    return USART_DmaGetTxCount(&usart5_DmaDriverState);
+}
+
+static uint32_t USART5_DmaGetRxCount(void)
+{
+    return USART_DmaGetRxCount(&usart5_DmaDriverState);
+}
+
+static int32_t USART5_DmaControl(uint32_t control, uint32_t arg)
+{
+    return USART_DmaControl(control, arg, &usart5_DmaDriverState);
+}
+
+static ARM_USART_STATUS USART5_DmaGetStatus(void)
+{
+    return USART_DmaGetStatus(&usart5_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static usart_handle_t USART5_Handle;
+#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1)
+static uint8_t usart5_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart5_non_blocking_driver_state")
+static cmsis_usart_non_blocking_driver_state_t usart5_NonBlockingDriverState = {
+#else
+static cmsis_usart_non_blocking_driver_state_t usart5_NonBlockingDriverState  = {
+#endif
+    &usart5_Resource,
+    &USART5_Handle,
+};
+
+static int32_t USART5_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART5_PIN_INIT
+    RTE_USART5_PIN_INIT();
+#endif
+    return USART_NonBlockingInitialize(cb_event, &usart5_NonBlockingDriverState);
+}
+
+static int32_t USART5_NonBlockingUninitialize(void)
+{
+#ifdef RTE_USART5_PIN_DEINIT
+    RTE_USART5_PIN_DEINIT();
+#endif
+    return USART_NonBlockingUninitialize(&usart5_NonBlockingDriverState);
+}
+
+static int32_t USART5_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+    int32_t result;
+
+    result = USART_NonBlockingPowerControl(state, &usart5_NonBlockingDriverState);
+#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1)
+    if ((state == ARM_POWER_FULL) && (usart5_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+    {
+        USART_TransferStartRingBuffer(usart5_NonBlockingDriverState.resource->base,
+                                      usart5_NonBlockingDriverState.handle, usart5_rxRingBuffer, USART_RX_BUFFER_LEN);
+    }
+#endif
+    return result;
+}
+
+static int32_t USART5_NonBlockingSend(const void *data, uint32_t num)
+{
+    return USART_NonBlockingSend(data, num, &usart5_NonBlockingDriverState);
+}
+
+static int32_t USART5_NonBlockingReceive(void *data, uint32_t num)
+{
+    return USART_NonBlockingReceive(data, num, &usart5_NonBlockingDriverState);
+}
+
+static int32_t USART5_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_NonBlockingTransfer(data_out, data_in, num, &usart5_NonBlockingDriverState);
+}
+
+static uint32_t USART5_NonBlockingGetTxCount(void)
+{
+    return USART_NonBlockingGetTxCount(&usart5_NonBlockingDriverState);
+}
+
+static uint32_t USART5_NonBlockingGetRxCount(void)
+{
+    return USART_NonBlockingGetRxCount(&usart5_NonBlockingDriverState);
+}
+
+static int32_t USART5_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+    int32_t result;
+
+    result = USART_NonBlockingControl(control, arg, &usart5_NonBlockingDriverState);
+    if (ARM_DRIVER_OK != result)
+    {
+        return result;
+    }
+#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1)
+    /* Start receiving interrupts */
+    usart5_NonBlockingDriverState.resource->base->FIFOINTENSET |=
+        USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+#endif
+    return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS USART5_NonBlockingGetStatus(void)
+{
+    return USART_NonBlockingGetStatus(&usart5_NonBlockingDriverState);
+}
+
+#endif
+
+ARM_DRIVER_USART Driver_USART5 = {
+    USARTx_GetVersion,      USARTx_GetCapabilities,
+#if RTE_USART5_DMA_EN
+    USART5_DmaInitialize,   USART5_DmaUninitialize, USART5_DmaPowerControl, USART5_DmaSend,    USART5_DmaReceive,
+    USART5_DmaTransfer,     USART5_DmaGetTxCount,   USART5_DmaGetRxCount,   USART5_DmaControl, USART5_DmaGetStatus,
+#else
+    USART5_NonBlockingInitialize,
+    USART5_NonBlockingUninitialize,
+    USART5_NonBlockingPowerControl,
+    USART5_NonBlockingSend,
+    USART5_NonBlockingReceive,
+    USART5_NonBlockingTransfer,
+    USART5_NonBlockingGetTxCount,
+    USART5_NonBlockingGetRxCount,
+    USART5_NonBlockingControl,
+    USART5_NonBlockingGetStatus,
+#endif
+    USARTx_SetModemControl, USARTx_GetModemStatus};
+
+#endif /* usart5 */
+
+#if defined(USART6) && defined(RTE_USART6) && RTE_USART6
+
+/* User needs to provide the implementation for USART6_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t USART6_GetFreq(void);
+
+static cmsis_usart_resource_t usart6_Resource = {USART6, USART6_GetFreq};
+
+#if defined(RTE_USART6_DMA_EN) && RTE_USART6_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_usart_dma_resource_t usart6_DmaResource = {
+    RTE_USART6_DMA_TX_DMA_BASE,
+    RTE_USART6_DMA_TX_CH,
+    RTE_USART6_DMA_RX_DMA_BASE,
+    RTE_USART6_DMA_RX_CH,
+};
+
+static usart_dma_handle_t USART6_DmaHandle;
+static dma_handle_t USART6_DmaRxHandle;
+static dma_handle_t USART6_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart6_dma_driver_state")
+static cmsis_usart_dma_driver_state_t usart6_DmaDriverState = {
+#else
+static cmsis_usart_dma_driver_state_t usart6_DmaDriverState  = {
+#endif
+    &usart6_Resource, &usart6_DmaResource, &USART6_DmaHandle, &USART6_DmaRxHandle, &USART6_DmaTxHandle,
+};
+
+static int32_t USART6_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART6_PIN_INIT
+    RTE_USART6_PIN_INIT();
+#endif
+    return USART_DmaInitialize(cb_event, &usart6_DmaDriverState);
+}
+
+static int32_t USART6_DmaUninitialize(void)
+{
+#ifdef RTE_USART6_PIN_DEINIT
+    RTE_USART6_PIN_DEINIT();
+#endif
+    return USART_DmaUninitialize(&usart6_DmaDriverState);
+}
+
+static int32_t USART6_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return USART_DmaPowerControl(state, &usart6_DmaDriverState);
+}
+
+static int32_t USART6_DmaSend(const void *data, uint32_t num)
+{
+    return USART_DmaSend(data, num, &usart6_DmaDriverState);
+}
+
+static int32_t USART6_DmaReceive(void *data, uint32_t num)
+{
+    return USART_DmaReceive(data, num, &usart6_DmaDriverState);
+}
+
+static int32_t USART6_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_DmaTransfer(data_out, data_in, num, &usart6_DmaDriverState);
+}
+
+static uint32_t USART6_DmaGetTxCount(void)
+{
+    return USART_DmaGetTxCount(&usart6_DmaDriverState);
+}
+
+static uint32_t USART6_DmaGetRxCount(void)
+{
+    return USART_DmaGetRxCount(&usart6_DmaDriverState);
+}
+
+static int32_t USART6_DmaControl(uint32_t control, uint32_t arg)
+{
+    return USART_DmaControl(control, arg, &usart6_DmaDriverState);
+}
+
+static ARM_USART_STATUS USART6_DmaGetStatus(void)
+{
+    return USART_DmaGetStatus(&usart6_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static usart_handle_t USART6_Handle;
+#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1)
+static uint8_t usart6_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart6_non_blocking_driver_state")
+static cmsis_usart_non_blocking_driver_state_t usart6_NonBlockingDriverState = {
+#else
+static cmsis_usart_non_blocking_driver_state_t usart6_NonBlockingDriverState  = {
+#endif
+    &usart6_Resource,
+    &USART6_Handle,
+};
+
+static int32_t USART6_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART6_PIN_INIT
+    RTE_USART6_PIN_INIT();
+#endif
+    return USART_NonBlockingInitialize(cb_event, &usart6_NonBlockingDriverState);
+}
+
+static int32_t USART6_NonBlockingUninitialize(void)
+{
+#ifdef RTE_USART6_PIN_DEINIT
+    RTE_USART6_PIN_DEINIT();
+#endif
+    return USART_NonBlockingUninitialize(&usart6_NonBlockingDriverState);
+}
+
+static int32_t USART6_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+    uint32_t result;
+
+    result = USART_NonBlockingPowerControl(state, &usart6_NonBlockingDriverState);
+#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1)
+    if ((state == ARM_POWER_FULL) && (usart6_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+    {
+        USART_TransferStartRingBuffer(usart6_NonBlockingDriverState.resource->base,
+                                      usart6_NonBlockingDriverState.handle, usart6_rxRingBuffer, USART_RX_BUFFER_LEN);
+    }
+#endif
+    return result;
+}
+
+static int32_t USART6_NonBlockingSend(const void *data, uint32_t num)
+{
+    return USART_NonBlockingSend(data, num, &usart6_NonBlockingDriverState);
+}
+
+static int32_t USART6_NonBlockingReceive(void *data, uint32_t num)
+{
+    return USART_NonBlockingReceive(data, num, &usart6_NonBlockingDriverState);
+}
+
+static int32_t USART6_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_NonBlockingTransfer(data_out, data_in, num, &usart6_NonBlockingDriverState);
+}
+
+static uint32_t USART6_NonBlockingGetTxCount(void)
+{
+    return USART_NonBlockingGetTxCount(&usart6_NonBlockingDriverState);
+}
+
+static uint32_t USART6_NonBlockingGetRxCount(void)
+{
+    return USART_NonBlockingGetRxCount(&usart6_NonBlockingDriverState);
+}
+
+static int32_t USART6_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+    int32_t result;
+
+    result = USART_NonBlockingControl(control, arg, &usart6_NonBlockingDriverState);
+    if (ARM_DRIVER_OK != result)
+    {
+        return result;
+    }
+#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1)
+    /* Start receiving interrupts */
+    usart6_NonBlockingDriverState.resource->base->FIFOINTENSET |=
+        USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+#endif
+    return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS USART6_NonBlockingGetStatus(void)
+{
+    return USART_NonBlockingGetStatus(&usart6_NonBlockingDriverState);
+}
+
+#endif
+
+ARM_DRIVER_USART Driver_USART6 = {
+    USARTx_GetVersion,      USARTx_GetCapabilities,
+#if RTE_USART6_DMA_EN
+    USART6_DmaInitialize,   USART6_DmaUninitialize, USART6_DmaPowerControl, USART6_DmaSend,    USART6_DmaReceive,
+    USART6_DmaTransfer,     USART6_DmaGetTxCount,   USART6_DmaGetRxCount,   USART6_DmaControl, USART6_DmaGetStatus,
+#else
+    USART6_NonBlockingInitialize,
+    USART6_NonBlockingUninitialize,
+    USART6_NonBlockingPowerControl,
+    USART6_NonBlockingSend,
+    USART6_NonBlockingReceive,
+    USART6_NonBlockingTransfer,
+    USART6_NonBlockingGetTxCount,
+    USART6_NonBlockingGetRxCount,
+    USART6_NonBlockingControl,
+    USART6_NonBlockingGetStatus,
+#endif
+    USARTx_SetModemControl, USARTx_GetModemStatus};
+
+#endif /* usart6 */
+
+#if defined(USART7) && defined(RTE_USART7) && RTE_USART7
+
+/* User needs to provide the implementation for USART7_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t USART7_GetFreq(void);
+
+static cmsis_usart_resource_t usart7_Resource = {USART7, USART7_GetFreq};
+
+#if defined(RTE_USART7_DMA_EN) && RTE_USART7_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_usart_dma_resource_t usart7_DmaResource = {
+    RTE_USART7_DMA_TX_DMA_BASE,
+    RTE_USART7_DMA_TX_CH,
+    RTE_USART7_DMA_RX_DMA_BASE,
+    RTE_USART7_DMA_RX_CH,
+};
+
+static usart_dma_handle_t USART7_DmaHandle;
+static dma_handle_t USART7_DmaRxHandle;
+static dma_handle_t USART7_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart7_dma_driver_state")
+static cmsis_usart_dma_driver_state_t usart7_DmaDriverState = {
+#else
+static cmsis_usart_dma_driver_state_t usart7_DmaDriverState  = {
+#endif
+    &usart7_Resource, &usart7_DmaResource, &USART7_DmaHandle, &USART7_DmaRxHandle, &USART7_DmaTxHandle,
+};
+
+static int32_t USART7_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART7_PIN_INIT
+    RTE_USART7_PIN_INIT();
+#endif
+    return USART_DmaInitialize(cb_event, &usart7_DmaDriverState);
+}
+
+static int32_t USART7_DmaUninitialize(void)
+{
+#ifdef RTE_USART7_PIN_DEINIT
+    RTE_USART7_PIN_DEINIT();
+#endif
+    return USART_DmaUninitialize(&usart7_DmaDriverState);
+}
+
+static int32_t USART7_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return USART_DmaPowerControl(state, &usart7_DmaDriverState);
+}
+
+static int32_t USART7_DmaSend(const void *data, uint32_t num)
+{
+    return USART_DmaSend(data, num, &usart7_DmaDriverState);
+}
+
+static int32_t USART7_DmaReceive(void *data, uint32_t num)
+{
+    return USART_DmaReceive(data, num, &usart7_DmaDriverState);
+}
+
+static int32_t USART7_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_DmaTransfer(data_out, data_in, num, &usart7_DmaDriverState);
+}
+
+static uint32_t USART7_DmaGetTxCount(void)
+{
+    return USART_DmaGetTxCount(&usart7_DmaDriverState);
+}
+
+static uint32_t USART7_DmaGetRxCount(void)
+{
+    return USART_DmaGetRxCount(&usart7_DmaDriverState);
+}
+
+static int32_t USART7_DmaControl(uint32_t control, uint32_t arg)
+{
+    return USART_DmaControl(control, arg, &usart7_DmaDriverState);
+}
+
+static ARM_USART_STATUS USART7_DmaGetStatus(void)
+{
+    return USART_DmaGetStatus(&usart7_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static usart_handle_t USART7_Handle;
+#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1)
+static uint8_t usart7_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart7_non_blocking_driver_state")
+static cmsis_usart_non_blocking_driver_state_t usart7_NonBlockingDriverState = {
+#else
+static cmsis_usart_non_blocking_driver_state_t usart7_NonBlockingDriverState  = {
+#endif
+    &usart7_Resource,
+    &USART7_Handle,
+};
+
+static int32_t USART7_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART7_PIN_INIT
+    RTE_USART7_PIN_INIT();
+#endif
+    return USART_NonBlockingInitialize(cb_event, &usart7_NonBlockingDriverState);
+}
+
+static int32_t USART7_NonBlockingUninitialize(void)
+{
+#ifdef RTE_USART7_PIN_DEINIT
+    RTE_USART7_PIN_DEINIT();
+#endif
+    return USART_NonBlockingUninitialize(&usart7_NonBlockingDriverState);
+}
+
+static int32_t USART7_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+    uint32_t result;
+
+    result = USART_NonBlockingPowerControl(state, &usart7_NonBlockingDriverState);
+#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1)
+    if ((state == ARM_POWER_FULL) && (usart7_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+    {
+        USART_TransferStartRingBuffer(usart7_NonBlockingDriverState.resource->base,
+                                      usart7_NonBlockingDriverState.handle, usart7_rxRingBuffer, USART_RX_BUFFER_LEN);
+    }
+#endif
+    return result;
+}
+
+static int32_t USART7_NonBlockingSend(const void *data, uint32_t num)
+{
+    return USART_NonBlockingSend(data, num, &usart7_NonBlockingDriverState);
+}
+
+static int32_t USART7_NonBlockingReceive(void *data, uint32_t num)
+{
+    return USART_NonBlockingReceive(data, num, &usart7_NonBlockingDriverState);
+}
+
+static int32_t USART7_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_NonBlockingTransfer(data_out, data_in, num, &usart7_NonBlockingDriverState);
+}
+
+static uint32_t USART7_NonBlockingGetTxCount(void)
+{
+    return USART_NonBlockingGetTxCount(&usart7_NonBlockingDriverState);
+}
+
+static uint32_t USART7_NonBlockingGetRxCount(void)
+{
+    return USART_NonBlockingGetRxCount(&usart7_NonBlockingDriverState);
+}
+
+static int32_t USART7_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+    int32_t result;
+
+    result = USART_NonBlockingControl(control, arg, &usart7_NonBlockingDriverState);
+    if (ARM_DRIVER_OK != result)
+    {
+        return result;
+    }
+#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1)
+    /* Start receiving interrupts */
+    usart7_NonBlockingDriverState.resource->base->FIFOINTENSET |=
+        USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+#endif
+    return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS USART7_NonBlockingGetStatus(void)
+{
+    return USART_NonBlockingGetStatus(&usart7_NonBlockingDriverState);
+}
+
+#endif
+
+ARM_DRIVER_USART Driver_USART7 = {
+    USARTx_GetVersion,      USARTx_GetCapabilities,
+#if RTE_USART7_DMA_EN
+    USART7_DmaInitialize,   USART7_DmaUninitialize, USART7_DmaPowerControl, USART7_DmaSend,    USART7_DmaReceive,
+    USART7_DmaTransfer,     USART7_DmaGetTxCount,   USART7_DmaGetRxCount,   USART7_DmaControl, USART7_DmaGetStatus,
+#else
+    USART7_NonBlockingInitialize,
+    USART7_NonBlockingUninitialize,
+    USART7_NonBlockingPowerControl,
+    USART7_NonBlockingSend,
+    USART7_NonBlockingReceive,
+    USART7_NonBlockingTransfer,
+    USART7_NonBlockingGetTxCount,
+    USART7_NonBlockingGetRxCount,
+    USART7_NonBlockingControl,
+    USART7_NonBlockingGetStatus,
+#endif
+    USARTx_SetModemControl, USARTx_GetModemStatus};
+
+#endif /* usart7 */
+
+#if defined(USART8) && defined(RTE_USART8) && RTE_USART8
+
+/* User needs to provide the implementation for USART8_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t USART8_GetFreq(void);
+
+static cmsis_usart_resource_t usart8_Resource = {USART8, USART8_GetFreq};
+
+#if defined(RTE_USART8_DMA_EN) RTE_USART8_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_usart_dma_resource_t usart8_DmaResource = {
+    RTE_USART8_DMA_TX_DMA_BASE,
+    RTE_USART8_DMA_TX_CH,
+    RTE_USART8_DMA_RX_DMA_BASE,
+    RTE_USART8_DMA_RX_CH,
+};
+
+static usart_dma_handle_t USART8_DmaHandle;
+static dma_handle_t USART8_DmaRxHandle;
+static dma_handle_t USART8_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart8_dma_driver_state")
+static cmsis_usart_dma_driver_state_t usart8_DmaDriverState = {
+#else
+static cmsis_usart_dma_driver_state_t usart8_DmaDriverState  = {
+#endif
+    &usart8_Resource, &usart8_DmaResource, &USART8_DmaHandle, &USART8_DmaRxHandle, &USART8_DmaTxHandle,
+};
+
+static int32_t USART8_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART8_PIN_INIT
+    RTE_USART8_PIN_INIT();
+#endif
+    return USART_DmaInitialize(cb_event, &usart8_DmaDriverState);
+}
+
+static int32_t USART8_DmaUninitialize(void)
+{
+#ifdef RTE_USART8_PIN_DEINIT
+    RTE_USART8_PIN_DEINIT();
+#endif
+    return USART_DmaUninitialize(&usart8_DmaDriverState);
+}
+
+static int32_t USART8_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return USART_DmaPowerControl(state, &usart8_DmaDriverState);
+}
+
+static int32_t USART8_DmaSend(const void *data, uint32_t num)
+{
+    return USART_DmaSend(data, num, &usart8_DmaDriverState);
+}
+
+static int32_t USART8_DmaReceive(void *data, uint32_t num)
+{
+    return USART_DmaReceive(data, num, &usart8_DmaDriverState);
+}
+
+static int32_t USART8_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_DmaTransfer(data_out, data_in, num, &usart8_DmaDriverState);
+}
+
+static uint32_t USART8_DmaGetTxCount(void)
+{
+    return USART_DmaGetTxCount(&usart8_DmaDriverState);
+}
+
+static uint32_t USART8_DmaGetRxCount(void)
+{
+    return USART_DmaGetRxCount(&usart8_DmaDriverState);
+}
+
+static int32_t USART8_DmaControl(uint32_t control, uint32_t arg)
+{
+    return USART_DmaControl(control, arg, &usart8_DmaDriverState);
+}
+
+static ARM_USART_STATUS USART8_DmaGetStatus(void)
+{
+    return USART_DmaGetStatus(&usart8_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static usart_handle_t USART8_Handle;
+#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1)
+static uint8_t usart8_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart8_non_blocking_driver_state")
+static cmsis_usart_non_blocking_driver_state_t usart8_NonBlockingDriverState = {
+#else
+static cmsis_usart_non_blocking_driver_state_t usart8_NonBlockingDriverState  = {
+#endif
+    &usart8_Resource,
+    &USART8_Handle,
+};
+
+static int32_t USART8_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART8_PIN_INIT
+    RTE_USART8_PIN_INIT();
+#endif
+    return USART_NonBlockingInitialize(cb_event, &usart8_NonBlockingDriverState);
+}
+
+static int32_t USART8_NonBlockingUninitialize(void)
+{
+#ifdef RTE_USART8_PIN_DEINIT
+    RTE_USART8_PIN_DEINIT();
+#endif
+    return USART_NonBlockingUninitialize(&usart8_NonBlockingDriverState);
+}
+
+static int32_t USART8_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+    uint32_t result;
+
+    result = USART_NonBlockingPowerControl(state, &usart8_NonBlockingDriverState);
+#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1)
+    if ((state == ARM_POWER_FULL) && (usart8_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+    {
+        USART_TransferStartRingBuffer(usart8_NonBlockingDriverState.resource->base,
+                                      usart8_NonBlockingDriverState.handle, usart8_rxRingBuffer, USART_RX_BUFFER_LEN);
+    }
+#endif
+
+    return result;
+}
+
+static int32_t USART8_NonBlockingSend(const void *data, uint32_t num)
+{
+    return USART_NonBlockingSend(data, num, &usart8_NonBlockingDriverState);
+}
+
+static int32_t USART8_NonBlockingReceive(void *data, uint32_t num)
+{
+    return USART_NonBlockingReceive(data, num, &usart8_NonBlockingDriverState);
+}
+
+static int32_t USART8_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_NonBlockingTransfer(data_out, data_in, num, &usart8_NonBlockingDriverState);
+}
+
+static uint32_t USART8_NonBlockingGetTxCount(void)
+{
+    return USART_NonBlockingGetTxCount(&usart8_NonBlockingDriverState);
+}
+
+static uint32_t USART8_NonBlockingGetRxCount(void)
+{
+    return USART_NonBlockingGetRxCount(&usart8_NonBlockingDriverState);
+}
+
+static int32_t USART8_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+    int32_t result;
+
+    result = USART_NonBlockingControl(control, arg, &usart8_NonBlockingDriverState);
+    if (ARM_DRIVER_OK != result)
+    {
+        return result;
+    }
+#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1)
+    /* Start receiving interrupts */
+    usart8_NonBlockingDriverState.resource->base->FIFOINTENSET |=
+        USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+#endif
+    return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS USART8_NonBlockingGetStatus(void)
+{
+    return USART_NonBlockingGetStatus(&usart8_NonBlockingDriverState);
+}
+
+#endif
+
+/* usart8 Driver Control Block */
+ARM_DRIVER_USART Driver_USART8 = {
+    USARTx_GetVersion,      USARTx_GetCapabilities,
+#if RTE_USART8_DMA_EN
+    USART8_DmaInitialize,   USART8_DmaUninitialize, USART8_DmaPowerControl, USART8_DmaSend,    USART8_DmaReceive,
+    USART8_DmaTransfer,     USART8_DmaGetTxCount,   USART8_DmaGetRxCount,   USART8_DmaControl, USART8_DmaGetStatus,
+#else
+    USART8_NonBlockingInitialize,
+    USART8_NonBlockingUninitialize,
+    USART8_NonBlockingPowerControl,
+    USART8_NonBlockingSend,
+    USART8_NonBlockingReceive,
+    USART8_NonBlockingTransfer,
+    USART8_NonBlockingGetTxCount,
+    USART8_NonBlockingGetRxCount,
+    USART8_NonBlockingControl,
+    USART8_NonBlockingGetStatus,
+#endif
+    USARTx_SetModemControl, USARTx_GetModemStatus};
+
+#endif /* usart8 */
+
+#if defined(USART9) && defined(RTE_USART9) && RTE_USART9
+
+/* User needs to provide the implementation for USART9_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t USART9_GetFreq(void);
+
+static cmsis_usart_resource_t usart9_Resource = {USART9, USART9_GetFreq};
+
+#if defined(RTE_USART9_DMA_EN) && RTE_USART9_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_usart_dma_resource_t usart9_DmaResource = {
+    RTE_USART9_DMA_TX_DMA_BASE,
+    RTE_USART9_DMA_TX_CH,
+    RTE_USART9_DMA_RX_DMA_BASE,
+    RTE_USART9_DMA_RX_CH,
+};
+
+static usart_dma_handle_t USART9_DmaHandle;
+static dma_handle_t USART9_DmaRxHandle;
+static dma_handle_t USART9_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart9_dma_driver_state")
+static cmsis_usart_dma_driver_state_t usart9_DmaDriverState = {
+#else
+static cmsis_usart_dma_driver_state_t usart9_DmaDriverState  = {
+#endif
+    &usart9_Resource, &usart9_DmaResource, &USART9_DmaHandle, &USART9_DmaRxHandle, &USART9_DmaTxHandle,
+};
+
+static int32_t USART9_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART9_PIN_INIT
+    RTE_USART9_PIN_INIT();
+#endif
+    return USART_DmaInitialize(cb_event, &usart9_DmaDriverState);
+}
+
+static int32_t USART9_DmaUninitialize(void)
+{
+#ifdef RTE_USART9_PIN_DEINIT
+    RTE_USART9_PIN_DEINIT();
+#endif
+    return USART_DmaUninitialize(&usart9_DmaDriverState);
+}
+
+static int32_t USART9_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return USART_DmaPowerControl(state, &usart9_DmaDriverState);
+}
+
+static int32_t USART9_DmaSend(const void *data, uint32_t num)
+{
+    return USART_DmaSend(data, num, &usart9_DmaDriverState);
+}
+
+static int32_t USART9_DmaReceive(void *data, uint32_t num)
+{
+    return USART_DmaReceive(data, num, &usart9_DmaDriverState);
+}
+
+static int32_t USART9_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_DmaTransfer(data_out, data_in, num, &usart9_DmaDriverState);
+}
+
+static uint32_t USART9_DmaGetTxCount(void)
+{
+    return USART_DmaGetTxCount(&usart9_DmaDriverState);
+}
+
+static uint32_t USART9_DmaGetRxCount(void)
+{
+    return USART_DmaGetRxCount(&usart9_DmaDriverState);
+}
+
+static int32_t USART9_DmaControl(uint32_t control, uint32_t arg)
+{
+    return USART_DmaControl(control, arg, &usart9_DmaDriverState);
+}
+
+static ARM_USART_STATUS USART9_DmaGetStatus(void)
+{
+    return USART_DmaGetStatus(&usart9_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static usart_handle_t USART9_Handle;
+#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1)
+static uint8_t usart9_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart9_non_blocking_driver_state")
+static cmsis_usart_non_blocking_driver_state_t usart9_NonBlockingDriverState = {
+#else
+static cmsis_usart_non_blocking_driver_state_t usart9_NonBlockingDriverState  = {
+#endif
+    &usart9_Resource,
+    &USART9_Handle,
+};
+
+static int32_t USART9_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART9_PIN_INIT
+    RTE_USART9_PIN_INIT();
+#endif
+    return USART_NonBlockingInitialize(cb_event, &usart9_NonBlockingDriverState);
+}
+
+static int32_t USART9_NonBlockingUninitialize(void)
+{
+#ifdef RTE_USART9_PIN_DEINIT
+    RTE_USART9_PIN_DEINIT();
+#endif
+    return USART_NonBlockingUninitialize(&usart9_NonBlockingDriverState);
+}
+
+static int32_t USART9_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+    uint32_t result;
+
+    result = USART_NonBlockingPowerControl(state, &usart9_NonBlockingDriverState);
+#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1)
+    if ((state == ARM_POWER_FULL) && (usart9_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+    {
+        USART_TransferStartRingBuffer(usart9_NonBlockingDriverState.resource->base,
+                                      usart9_NonBlockingDriverState.handle, usart9_rxRingBuffer, USART_RX_BUFFER_LEN);
+    }
+#endif
+
+    return result;
+}
+
+static int32_t USART9_NonBlockingSend(const void *data, uint32_t num)
+{
+    return USART_NonBlockingSend(data, num, &usart9_NonBlockingDriverState);
+}
+
+static int32_t USART9_NonBlockingReceive(void *data, uint32_t num)
+{
+    return USART_NonBlockingReceive(data, num, &usart9_NonBlockingDriverState);
+}
+
+static int32_t USART9_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_NonBlockingTransfer(data_out, data_in, num, &usart9_NonBlockingDriverState);
+}
+
+static uint32_t USART9_NonBlockingGetTxCount(void)
+{
+    return USART_NonBlockingGetTxCount(&usart9_NonBlockingDriverState);
+}
+
+static uint32_t USART9_NonBlockingGetRxCount(void)
+{
+    return USART_NonBlockingGetRxCount(&usart9_NonBlockingDriverState);
+}
+
+static int32_t USART9_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+    int32_t result;
+
+    result = USART_NonBlockingControl(control, arg, &usart9_NonBlockingDriverState);
+    if (ARM_DRIVER_OK != result)
+    {
+        return result;
+    }
+#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1)
+    /* Start receiving interrupts */
+    usart9_NonBlockingDriverState.resource->base->FIFOINTENSET |=
+        USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+#endif
+    return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS USART9_NonBlockingGetStatus(void)
+{
+    return USART_NonBlockingGetStatus(&usart9_NonBlockingDriverState);
+}
+
+#endif
+
+/* usart9 Driver Control Block */
+ARM_DRIVER_USART Driver_USART9 = {
+    USARTx_GetVersion,      USARTx_GetCapabilities,
+#if RTE_USART9_DMA_EN
+    USART9_DmaInitialize,   USART9_DmaUninitialize, USART9_DmaPowerControl, USART9_DmaSend,    USART9_DmaReceive,
+    USART9_DmaTransfer,     USART9_DmaGetTxCount,   USART9_DmaGetRxCount,   USART9_DmaControl, USART9_DmaGetStatus,
+#else
+    USART9_NonBlockingInitialize,
+    USART9_NonBlockingUninitialize,
+    USART9_NonBlockingPowerControl,
+    USART9_NonBlockingSend,
+    USART9_NonBlockingReceive,
+    USART9_NonBlockingTransfer,
+    USART9_NonBlockingGetTxCount,
+    USART9_NonBlockingGetRxCount,
+    USART9_NonBlockingControl,
+    USART9_NonBlockingGetStatus,
+#endif
+    USARTx_SetModemControl, USARTx_GetModemStatus};
+
+#endif /* usart9 */
+
+#if defined(USART10) && defined(RTE_USART10) && RTE_USART10
+
+/* User needs to provide the implementation for USART10_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t USART10_GetFreq(void);
+
+static cmsis_usart_resource_t usart10_Resource = {USART10, USART10_GetFreq};
+
+#if defined(RTE_USART10_DMA_EN) && RTE_USART10_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_usart_dma_resource_t usart10_DmaResource = {
+    RTE_USART10_DMA_TX_DMA_BASE,
+    RTE_USART10_DMA_TX_CH,
+    RTE_USART10_DMA_RX_DMA_BASE,
+    RTE_USART10_DMA_RX_CH,
+};
+
+static usart_dma_handle_t USART10_DmaHandle;
+static dma_handle_t USART10_DmaRxHandle;
+static dma_handle_t USART10_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart10_dma_driver_state")
+static cmsis_usart_dma_driver_state_t usart10_DmaDriverState = {
+#else
+static cmsis_usart_dma_driver_state_t usart10_DmaDriverState = {
+#endif
+    &usart10_Resource, &usart10_DmaResource, &USART10_DmaHandle, &USART10_DmaRxHandle, &USART10_DmaTxHandle,
+};
+
+static int32_t USART10_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART10_PIN_INIT
+    RTE_USART10_PIN_INIT();
+#endif
+    return USART_DmaInitialize(cb_event, &usart10_DmaDriverState);
+}
+
+static int32_t USART10_DmaUninitialize(void)
+{
+#ifdef RTE_USART10_PIN_DEINIT
+    RTE_USART10_PIN_DEINIT();
+#endif
+    return USART_DmaUninitialize(&usart10_DmaDriverState);
+}
+
+static int32_t USART10_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return USART_DmaPowerControl(state, &usart10_DmaDriverState);
+}
+
+static int32_t USART10_DmaSend(const void *data, uint32_t num)
+{
+    return USART_DmaSend(data, num, &usart10_DmaDriverState);
+}
+
+static int32_t USART10_DmaReceive(void *data, uint32_t num)
+{
+    return USART_DmaReceive(data, num, &usart10_DmaDriverState);
+}
+
+static int32_t USART10_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_DmaTransfer(data_out, data_in, num, &usart10_DmaDriverState);
+}
+
+static uint32_t USART10_DmaGetTxCount(void)
+{
+    return USART_DmaGetTxCount(&usart10_DmaDriverState);
+}
+
+static uint32_t USART10_DmaGetRxCount(void)
+{
+    return USART_DmaGetRxCount(&usart10_DmaDriverState);
+}
+
+static int32_t USART10_DmaControl(uint32_t control, uint32_t arg)
+{
+    return USART_DmaControl(control, arg, &usart10_DmaDriverState);
+}
+
+static ARM_USART_STATUS USART10_DmaGetStatus(void)
+{
+    return USART_DmaGetStatus(&usart10_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static usart_handle_t USART10_Handle;
+#if defined(USART10_RX_BUFFER_ENABLE) && (USART10_RX_BUFFER_ENABLE == 1)
+static uint8_t usart10_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart10_non_blocking_driver_state")
+static cmsis_usart_non_blocking_driver_state_t usart10_NonBlockingDriverState = {
+#else
+static cmsis_usart_non_blocking_driver_state_t usart10_NonBlockingDriverState = {
+#endif
+    &usart10_Resource,
+    &USART10_Handle,
+};
+
+static int32_t USART10_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART10_PIN_INIT
+    RTE_USART10_PIN_INIT();
+#endif
+    return USART_NonBlockingInitialize(cb_event, &usart10_NonBlockingDriverState);
+}
+
+static int32_t USART10_NonBlockingUninitialize(void)
+{
+#ifdef RTE_USART10_PIN_DEINIT
+    RTE_USART10_PIN_DEINIT();
+#endif
+    return USART_NonBlockingUninitialize(&usart10_NonBlockingDriverState);
+}
+
+static int32_t USART10_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+    uint32_t result;
+
+    result = USART_NonBlockingPowerControl(state, &usart10_NonBlockingDriverState);
+#if defined(USART10_RX_BUFFER_ENABLE) && (USART10_RX_BUFFER_ENABLE == 1)
+    if ((state == ARM_POWER_FULL) && (usart10_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+    {
+        USART_TransferStartRingBuffer(usart10_NonBlockingDriverState.resource->base,
+                                      usart10_NonBlockingDriverState.handle, usart10_rxRingBuffer, USART_RX_BUFFER_LEN);
+    }
+#endif
+    return result;
+}
+
+static int32_t USART10_NonBlockingSend(const void *data, uint32_t num)
+{
+    return USART_NonBlockingSend(data, num, &usart10_NonBlockingDriverState);
+}
+
+static int32_t USART10_NonBlockingReceive(void *data, uint32_t num)
+{
+    return USART_NonBlockingReceive(data, num, &usart10_NonBlockingDriverState);
+}
+
+static int32_t USART10_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_NonBlockingTransfer(data_out, data_in, num, &usart10_NonBlockingDriverState);
+}
+
+static uint32_t USART10_NonBlockingGetTxCount(void)
+{
+    return USART_NonBlockingGetTxCount(&usart10_NonBlockingDriverState);
+}
+
+static uint32_t USART10_NonBlockingGetRxCount(void)
+{
+    return USART_NonBlockingGetRxCount(&usart10_NonBlockingDriverState);
+}
+
+static int32_t USART10_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+    int32_t result;
+
+    result = USART_NonBlockingControl(control, arg, &usart10_NonBlockingDriverState);
+    if (ARM_DRIVER_OK != result)
+    {
+        return result;
+    }
+#if defined(USART10_RX_BUFFER_ENABLE) && (USART10_RX_BUFFER_ENABLE == 1)
+    /* Start receiving interrupts */
+    usart10_NonBlockingDriverState.resource->base->FIFOINTENSET |=
+        USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+#endif
+    return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS USART10_NonBlockingGetStatus(void)
+{
+    return USART_NonBlockingGetStatus(&usart10_NonBlockingDriverState);
+}
+
+#endif
+
+ARM_DRIVER_USART Driver_USART10 = {
+    USARTx_GetVersion,      USARTx_GetCapabilities,
+#if RTE_USART10_DMA_EN
+    USART10_DmaInitialize,  USART10_DmaUninitialize, USART10_DmaPowerControl, USART10_DmaSend,    USART10_DmaReceive,
+    USART10_DmaTransfer,    USART10_DmaGetTxCount,   USART10_DmaGetRxCount,   USART10_DmaControl, USART10_DmaGetStatus,
+#else
+    USART10_NonBlockingInitialize,
+    USART10_NonBlockingUninitialize,
+    USART10_NonBlockingPowerControl,
+    USART10_NonBlockingSend,
+    USART10_NonBlockingReceive,
+    USART10_NonBlockingTransfer,
+    USART10_NonBlockingGetTxCount,
+    USART10_NonBlockingGetRxCount,
+    USART10_NonBlockingControl,
+    USART10_NonBlockingGetStatus,
+#endif
+    USARTx_SetModemControl, USARTx_GetModemStatus};
+
+#endif /* usart10 */
+
+#if defined(USART11) && defined(RTE_USART11) && RTE_USART11
+
+/* User needs to provide the implementation for USART11_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t USART11_GetFreq(void);
+
+static cmsis_usart_resource_t usart11_Resource = {USART11, USART11_GetFreq};
+
+#if defined(RTE_USART11_DMA_EN) && RTE_USART11_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_usart_dma_resource_t usart11_DmaResource = {
+    RTE_USART11_DMA_TX_DMA_BASE,
+    RTE_USART11_DMA_TX_CH,
+    RTE_USART11_DMA_RX_DMA_BASE,
+    RTE_USART11_DMA_RX_CH,
+};
+
+static usart_dma_handle_t USART11_DmaHandle;
+static dma_handle_t USART11_DmaRxHandle;
+static dma_handle_t USART11_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart11_dma_driver_state")
+static cmsis_usart_dma_driver_state_t usart11_DmaDriverState = {
+#else
+static cmsis_usart_dma_driver_state_t usart11_DmaDriverState = {
+#endif
+    &usart11_Resource, &usart11_DmaResource, &USART11_DmaHandle, &USART11_DmaRxHandle, &USART11_DmaTxHandle,
+};
+
+static int32_t USART11_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART11_PIN_INIT
+    RTE_USART11_PIN_INIT();
+#endif
+    return USART_DmaInitialize(cb_event, &usart11_DmaDriverState);
+}
+
+static int32_t USART11_DmaUninitialize(void)
+{
+#ifdef RTE_USART11_PIN_DEINIT
+    RTE_USART11_PIN_DEINIT();
+#endif
+    return USART_DmaUninitialize(&usart11_DmaDriverState);
+}
+
+static int32_t USART11_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return USART_DmaPowerControl(state, &usart11_DmaDriverState);
+}
+
+static int32_t USART11_DmaSend(const void *data, uint32_t num)
+{
+    return USART_DmaSend(data, num, &usart11_DmaDriverState);
+}
+
+static int32_t USART11_DmaReceive(void *data, uint32_t num)
+{
+    return USART_DmaReceive(data, num, &usart11_DmaDriverState);
+}
+
+static int32_t USART11_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_DmaTransfer(data_out, data_in, num, &usart11_DmaDriverState);
+}
+
+static uint32_t USART11_DmaGetTxCount(void)
+{
+    return USART_DmaGetTxCount(&usart11_DmaDriverState);
+}
+
+static uint32_t USART11_DmaGetRxCount(void)
+{
+    return USART_DmaGetRxCount(&usart11_DmaDriverState);
+}
+
+static int32_t USART11_DmaControl(uint32_t control, uint32_t arg)
+{
+    return USART_DmaControl(control, arg, &usart11_DmaDriverState);
+}
+
+static ARM_USART_STATUS USART11_DmaGetStatus(void)
+{
+    return USART_DmaGetStatus(&usart11_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static usart_handle_t USART11_Handle;
+#if defined(USART11_RX_BUFFER_ENABLE) && (USART11_RX_BUFFER_ENABLE == 1)
+static uint8_t usart11_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart11_non_blocking_driver_state")
+static cmsis_usart_non_blocking_driver_state_t usart11_NonBlockingDriverState = {
+#else
+static cmsis_usart_non_blocking_driver_state_t usart11_NonBlockingDriverState = {
+#endif
+    &usart11_Resource,
+    &USART11_Handle,
+};
+
+static int32_t USART11_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART11_PIN_INIT
+    RTE_USART11_PIN_INIT();
+#endif
+    return USART_NonBlockingInitialize(cb_event, &usart11_NonBlockingDriverState);
+}
+
+static int32_t USART11_NonBlockingUninitialize(void)
+{
+#ifdef RTE_USART11_PIN_DEINIT
+    RTE_USART11_PIN_DEINIT();
+#endif
+    return USART_NonBlockingUninitialize(&usart11_NonBlockingDriverState);
+}
+
+static int32_t USART11_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+    uint32_t result;
+
+    result = USART_NonBlockingPowerControl(state, &usart11_NonBlockingDriverState);
+#if defined(USART11_RX_BUFFER_ENABLE) && (USART11_RX_BUFFER_ENABLE == 1)
+    if ((state == ARM_POWER_FULL) && (usart11_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+    {
+        USART_TransferStartRingBuffer(usart11_NonBlockingDriverState.resource->base,
+                                      usart11_NonBlockingDriverState.handle, usart11_rxRingBuffer, USART_RX_BUFFER_LEN);
+    }
+#endif
+    return result;
+}
+
+static int32_t USART11_NonBlockingSend(const void *data, uint32_t num)
+{
+    return USART_NonBlockingSend(data, num, &usart11_NonBlockingDriverState);
+}
+
+static int32_t USART11_NonBlockingReceive(void *data, uint32_t num)
+{
+    return USART_NonBlockingReceive(data, num, &usart11_NonBlockingDriverState);
+}
+
+static int32_t USART11_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_NonBlockingTransfer(data_out, data_in, num, &usart11_NonBlockingDriverState);
+}
+
+static uint32_t USART11_NonBlockingGetTxCount(void)
+{
+    return USART_NonBlockingGetTxCount(&usart11_NonBlockingDriverState);
+}
+
+static uint32_t USART11_NonBlockingGetRxCount(void)
+{
+    return USART_NonBlockingGetRxCount(&usart11_NonBlockingDriverState);
+}
+
+static int32_t USART11_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+    int32_t result;
+
+    result = USART_NonBlockingControl(control, arg, &usart11_NonBlockingDriverState);
+    if (ARM_DRIVER_OK != result)
+    {
+        return result;
+    }
+#if defined(USART11_RX_BUFFER_ENABLE) && (USART11_RX_BUFFER_ENABLE == 1)
+    /* Start receiving interrupts */
+    usart11_NonBlockingDriverState.resource->base->FIFOINTENSET |=
+        USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+#endif
+    return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS USART11_NonBlockingGetStatus(void)
+{
+    return USART_NonBlockingGetStatus(&usart11_NonBlockingDriverState);
+}
+
+#endif
+
+ARM_DRIVER_USART Driver_USART11 = {
+    USARTx_GetVersion,      USARTx_GetCapabilities,
+#if RTE_USART11_DMA_EN
+    USART11_DmaInitialize,  USART11_DmaUninitialize, USART11_DmaPowerControl, USART11_DmaSend,    USART11_DmaReceive,
+    USART11_DmaTransfer,    USART11_DmaGetTxCount,   USART11_DmaGetRxCount,   USART11_DmaControl, USART11_DmaGetStatus,
+#else
+    USART11_NonBlockingInitialize,
+    USART11_NonBlockingUninitialize,
+    USART11_NonBlockingPowerControl,
+    USART11_NonBlockingSend,
+    USART11_NonBlockingReceive,
+    USART11_NonBlockingTransfer,
+    USART11_NonBlockingGetTxCount,
+    USART11_NonBlockingGetRxCount,
+    USART11_NonBlockingControl,
+    USART11_NonBlockingGetStatus,
+#endif
+    USARTx_SetModemControl, USARTx_GetModemStatus};
+
+#endif /* usart11 */
+
+#if defined(USART12) && defined(RTE_USART12) && RTE_USART12
+
+/* User needs to provide the implementation for USART12_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t USART12_GetFreq(void);
+
+static cmsis_usart_resource_t usart12_Resource = {USART12, USART12_GetFreq};
+
+#if defined(RTE_USART12_DMA_EN) && RTE_USART12_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_usart_dma_resource_t usart12_DmaResource = {
+    RTE_USART12_DMA_TX_DMA_BASE,
+    RTE_USART12_DMA_TX_CH,
+    RTE_USART12_DMA_RX_DMA_BASE,
+    RTE_USART12_DMA_RX_CH,
+};
+
+static usart_dma_handle_t USART12_DmaHandle;
+static dma_handle_t USART12_DmaRxHandle;
+static dma_handle_t USART12_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart12_dma_driver_state")
+static cmsis_usart_dma_driver_state_t usart12_DmaDriverState = {
+#else
+static cmsis_usart_dma_driver_state_t usart12_DmaDriverState = {
+#endif
+    &usart12_Resource, &usart12_DmaResource, &USART12_DmaHandle, &USART12_DmaRxHandle, &USART12_DmaTxHandle,
+};
+
+static int32_t USART12_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART12_PIN_INIT
+    RTE_USART12_PIN_INIT();
+#endif
+    return USART_DmaInitialize(cb_event, &usart12_DmaDriverState);
+}
+
+static int32_t USART12_DmaUninitialize(void)
+{
+#ifdef RTE_USART12_PIN_DEINIT
+    RTE_USART12_PIN_DEINIT();
+#endif
+    return USART_DmaUninitialize(&usart12_DmaDriverState);
+}
+
+static int32_t USART12_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return USART_DmaPowerControl(state, &usart12_DmaDriverState);
+}
+
+static int32_t USART12_DmaSend(const void *data, uint32_t num)
+{
+    return USART_DmaSend(data, num, &usart12_DmaDriverState);
+}
+
+static int32_t USART12_DmaReceive(void *data, uint32_t num)
+{
+    return USART_DmaReceive(data, num, &usart12_DmaDriverState);
+}
+
+static int32_t USART12_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_DmaTransfer(data_out, data_in, num, &usart12_DmaDriverState);
+}
+
+static uint32_t USART12_DmaGetTxCount(void)
+{
+    return USART_DmaGetTxCount(&usart12_DmaDriverState);
+}
+
+static uint32_t USART12_DmaGetRxCount(void)
+{
+    return USART_DmaGetRxCount(&usart12_DmaDriverState);
+}
+
+static int32_t USART12_DmaControl(uint32_t control, uint32_t arg)
+{
+    return USART_DmaControl(control, arg, &usart12_DmaDriverState);
+}
+
+static ARM_USART_STATUS USART12_DmaGetStatus(void)
+{
+    return USART_DmaGetStatus(&usart12_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static usart_handle_t USART12_Handle;
+#if defined(USART12_RX_BUFFER_ENABLE) && (USART12_RX_BUFFER_ENABLE == 1)
+static uint8_t usart12_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart12_non_blocking_driver_state")
+static cmsis_usart_non_blocking_driver_state_t usart12_NonBlockingDriverState = {
+#else
+static cmsis_usart_non_blocking_driver_state_t usart12_NonBlockingDriverState = {
+#endif
+    &usart12_Resource,
+    &USART12_Handle,
+};
+
+static int32_t USART12_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART12_PIN_INIT
+    RTE_USART12_PIN_INIT();
+#endif
+    return USART_NonBlockingInitialize(cb_event, &usart12_NonBlockingDriverState);
+}
+
+static int32_t USART12_NonBlockingUninitialize(void)
+{
+#ifdef RTE_USART12_PIN_DEINIT
+    RTE_USART12_PIN_DEINIT();
+#endif
+    return USART_NonBlockingUninitialize(&usart12_NonBlockingDriverState);
+}
+
+static int32_t USART12_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+    uint32_t result;
+
+    result = USART_NonBlockingPowerControl(state, &usart12_NonBlockingDriverState);
+#if defined(USART12_RX_BUFFER_ENABLE) && (USART12_RX_BUFFER_ENABLE == 1)
+    if ((state == ARM_POWER_FULL) && (usart12_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+    {
+        USART_TransferStartRingBuffer(usart12_NonBlockingDriverState.resource->base,
+                                      usart12_NonBlockingDriverState.handle, usart12_rxRingBuffer, USART_RX_BUFFER_LEN);
+    }
+#endif
+    return result;
+}
+
+static int32_t USART12_NonBlockingSend(const void *data, uint32_t num)
+{
+    return USART_NonBlockingSend(data, num, &usart12_NonBlockingDriverState);
+}
+
+static int32_t USART12_NonBlockingReceive(void *data, uint32_t num)
+{
+    return USART_NonBlockingReceive(data, num, &usart12_NonBlockingDriverState);
+}
+
+static int32_t USART12_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_NonBlockingTransfer(data_out, data_in, num, &usart12_NonBlockingDriverState);
+}
+
+static uint32_t USART12_NonBlockingGetTxCount(void)
+{
+    return USART_NonBlockingGetTxCount(&usart12_NonBlockingDriverState);
+}
+
+static uint32_t USART12_NonBlockingGetRxCount(void)
+{
+    return USART_NonBlockingGetRxCount(&usart12_NonBlockingDriverState);
+}
+
+static int32_t USART12_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+    int32_t result;
+
+    result = USART_NonBlockingControl(control, arg, &usart12_NonBlockingDriverState);
+    if (ARM_DRIVER_OK != result)
+    {
+        return result;
+    }
+#if defined(USART12_RX_BUFFER_ENABLE) && (USART12_RX_BUFFER_ENABLE == 1)
+    /* Start receiving interrupts */
+    usart12_NonBlockingDriverState.resource->base->FIFOINTENSET |=
+        USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+#endif
+    return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS USART12_NonBlockingGetStatus(void)
+{
+    return USART_NonBlockingGetStatus(&usart12_NonBlockingDriverState);
+}
+
+#endif
+
+ARM_DRIVER_USART Driver_USART12 = {
+    USARTx_GetVersion,      USARTx_GetCapabilities,
+#if RTE_USART12_DMA_EN
+    USART12_DmaInitialize,  USART12_DmaUninitialize, USART12_DmaPowerControl, USART12_DmaSend,    USART12_DmaReceive,
+    USART12_DmaTransfer,    USART12_DmaGetTxCount,   USART12_DmaGetRxCount,   USART12_DmaControl, USART12_DmaGetStatus,
+#else
+    USART12_NonBlockingInitialize,
+    USART12_NonBlockingUninitialize,
+    USART12_NonBlockingPowerControl,
+    USART12_NonBlockingSend,
+    USART12_NonBlockingReceive,
+    USART12_NonBlockingTransfer,
+    USART12_NonBlockingGetTxCount,
+    USART12_NonBlockingGetRxCount,
+    USART12_NonBlockingControl,
+    USART12_NonBlockingGetStatus,
+#endif
+    USARTx_SetModemControl, USARTx_GetModemStatus};
+
+#endif /* usart12 */
+
+#if defined(USART13) && defined(RTE_USART13) && RTE_USART13
+
+/* User needs to provide the implementation for USART13_GetFreq/InitPins/DeinitPins
+in the application for enabling according instance. */
+extern uint32_t USART13_GetFreq(void);
+
+static cmsis_usart_resource_t usart13_Resource = {USART13, USART13_GetFreq};
+
+#if defined(RTE_USART13_DMA_EN) && RTE_USART13_DMA_EN
+
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+
+cmsis_usart_dma_resource_t usart13_DmaResource = {
+    RTE_USART13_DMA_TX_DMA_BASE,
+    RTE_USART13_DMA_TX_CH,
+    RTE_USART13_DMA_RX_DMA_BASE,
+    RTE_USART13_DMA_RX_CH,
+};
+
+static usart_dma_handle_t USART13_DmaHandle;
+static dma_handle_t USART13_DmaRxHandle;
+static dma_handle_t USART13_DmaTxHandle;
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart13_dma_driver_state")
+static cmsis_usart_dma_driver_state_t usart13_DmaDriverState = {
+#else
+static cmsis_usart_dma_driver_state_t usart13_DmaDriverState = {
+#endif
+    &usart13_Resource, &usart13_DmaResource, &USART13_DmaHandle, &USART13_DmaRxHandle, &USART13_DmaTxHandle,
+};
+
+static int32_t USART13_DmaInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART13_PIN_INIT
+    RTE_USART13_PIN_INIT();
+#endif
+    return USART_DmaInitialize(cb_event, &usart13_DmaDriverState);
+}
+
+static int32_t USART13_DmaUninitialize(void)
+{
+#ifdef RTE_USART13_PIN_DEINIT
+    RTE_USART13_PIN_DEINIT();
+#endif
+    return USART_DmaUninitialize(&usart13_DmaDriverState);
+}
+
+static int32_t USART13_DmaPowerControl(ARM_POWER_STATE state)
+{
+    return USART_DmaPowerControl(state, &usart13_DmaDriverState);
+}
+
+static int32_t USART13_DmaSend(const void *data, uint32_t num)
+{
+    return USART_DmaSend(data, num, &usart13_DmaDriverState);
+}
+
+static int32_t USART13_DmaReceive(void *data, uint32_t num)
+{
+    return USART_DmaReceive(data, num, &usart13_DmaDriverState);
+}
+
+static int32_t USART13_DmaTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_DmaTransfer(data_out, data_in, num, &usart13_DmaDriverState);
+}
+
+static uint32_t USART13_DmaGetTxCount(void)
+{
+    return USART_DmaGetTxCount(&usart13_DmaDriverState);
+}
+
+static uint32_t USART13_DmaGetRxCount(void)
+{
+    return USART_DmaGetRxCount(&usart13_DmaDriverState);
+}
+
+static int32_t USART13_DmaControl(uint32_t control, uint32_t arg)
+{
+    return USART_DmaControl(control, arg, &usart13_DmaDriverState);
+}
+
+static ARM_USART_STATUS USART13_DmaGetStatus(void)
+{
+    return USART_DmaGetStatus(&usart13_DmaDriverState);
+}
+
+#endif
+
+#else
+
+static usart_handle_t USART13_Handle;
+#if defined(USART13_RX_BUFFER_ENABLE) && (USART13_RX_BUFFER_ENABLE == 1)
+static uint8_t usart13_rxRingBuffer[USART_RX_BUFFER_LEN];
+#endif
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ARMCC_SECTION("usart13_non_blocking_driver_state")
+static cmsis_usart_non_blocking_driver_state_t usart13_NonBlockingDriverState = {
+#else
+static cmsis_usart_non_blocking_driver_state_t usart13_NonBlockingDriverState = {
+#endif
+    &usart13_Resource,
+    &USART13_Handle,
+};
+
+static int32_t USART13_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event)
+{
+#ifdef RTE_USART13_PIN_INIT
+    RTE_USART13_PIN_INIT();
+#endif
+    return USART_NonBlockingInitialize(cb_event, &usart13_NonBlockingDriverState);
+}
+
+static int32_t USART13_NonBlockingUninitialize(void)
+{
+#ifdef RTE_USART13_PIN_DEINIT
+    RTE_USART13_PIN_DEINIT();
+#endif
+    return USART_NonBlockingUninitialize(&usart13_NonBlockingDriverState);
+}
+
+static int32_t USART13_NonBlockingPowerControl(ARM_POWER_STATE state)
+{
+    uint32_t result;
+
+    result = USART_NonBlockingPowerControl(state, &usart13_NonBlockingDriverState);
+#if defined(USART13_RX_BUFFER_ENABLE) && (USART13_RX_BUFFER_ENABLE == 1)
+    if ((state == ARM_POWER_FULL) && (usart13_NonBlockingDriverState.handle->rxRingBuffer == NULL))
+    {
+        USART_TransferStartRingBuffer(usart13_NonBlockingDriverState.resource->base,
+                                      usart13_NonBlockingDriverState.handle, usart13_rxRingBuffer, USART_RX_BUFFER_LEN);
+    }
+#endif
+    return result;
+}
+
+static int32_t USART13_NonBlockingSend(const void *data, uint32_t num)
+{
+    return USART_NonBlockingSend(data, num, &usart13_NonBlockingDriverState);
+}
+
+static int32_t USART13_NonBlockingReceive(void *data, uint32_t num)
+{
+    return USART_NonBlockingReceive(data, num, &usart13_NonBlockingDriverState);
+}
+
+static int32_t USART13_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num)
+{
+    return USART_NonBlockingTransfer(data_out, data_in, num, &usart13_NonBlockingDriverState);
+}
+
+static uint32_t USART13_NonBlockingGetTxCount(void)
+{
+    return USART_NonBlockingGetTxCount(&usart13_NonBlockingDriverState);
+}
+
+static uint32_t USART13_NonBlockingGetRxCount(void)
+{
+    return USART_NonBlockingGetRxCount(&usart13_NonBlockingDriverState);
+}
+
+static int32_t USART13_NonBlockingControl(uint32_t control, uint32_t arg)
+{
+    int32_t result;
+
+    result = USART_NonBlockingControl(control, arg, &usart13_NonBlockingDriverState);
+    if (ARM_DRIVER_OK != result)
+    {
+        return result;
+    }
+#if defined(USART13_RX_BUFFER_ENABLE) && (USART13_RX_BUFFER_ENABLE == 1)
+    /* Start receiving interrupts */
+    usart13_NonBlockingDriverState.resource->base->FIFOINTENSET |=
+        USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+#endif
+    return ARM_DRIVER_OK;
+}
+
+static ARM_USART_STATUS USART13_NonBlockingGetStatus(void)
+{
+    return USART_NonBlockingGetStatus(&usart13_NonBlockingDriverState);
+}
+
+#endif
+
+ARM_DRIVER_USART Driver_USART13 = {
+    USARTx_GetVersion,      USARTx_GetCapabilities,
+#if RTE_USART13_DMA_EN
+    USART13_DmaInitialize,  USART13_DmaUninitialize, USART13_DmaPowerControl, USART13_DmaSend,    USART13_DmaReceive,
+    USART13_DmaTransfer,    USART13_DmaGetTxCount,   USART13_DmaGetRxCount,   USART13_DmaControl, USART13_DmaGetStatus,
+#else
+    USART13_NonBlockingInitialize,
+    USART13_NonBlockingUninitialize,
+    USART13_NonBlockingPowerControl,
+    USART13_NonBlockingSend,
+    USART13_NonBlockingReceive,
+    USART13_NonBlockingTransfer,
+    USART13_NonBlockingGetTxCount,
+    USART13_NonBlockingGetRxCount,
+    USART13_NonBlockingControl,
+    USART13_NonBlockingGetStatus,
+#endif
+    USARTx_SetModemControl, USARTx_GetModemStatus};
+
+#endif /* usart13 */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_usart_cmsis.h

@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
+ * Copyright 2016-2017 NXP. Not a Contribution.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _FSL_USART_CMSIS_H_
+#define _FSL_USART_CMSIS_H_
+
+#include "fsl_common.h"
+#include "Driver_USART.h"
+#include "RTE_Device.h"
+#include "fsl_usart.h"
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+#include "fsl_usart_dma.h"
+#endif
+
+#if defined(USART0) && defined(RTE_USART0) && RTE_USART0
+extern ARM_DRIVER_USART Driver_USART0;
+#endif /* USART0 */
+
+#if defined(USART1) && defined(RTE_USART1) && RTE_USART1
+extern ARM_DRIVER_USART Driver_USART1;
+#endif /* USART1 */
+
+#if defined(USART2) && defined(RTE_USART2) && RTE_USART2
+extern ARM_DRIVER_USART Driver_USART2;
+#endif /* USART2 */
+
+#if defined(USART3) && defined(RTE_USART3) && RTE_USART3
+extern ARM_DRIVER_USART Driver_USART3;
+#endif /* USART3 */
+
+#if defined(USART4) && defined(RTE_USART4) && RTE_USART4
+extern ARM_DRIVER_USART Driver_USART4;
+#endif /* USART4 */
+
+#if defined(USART5) && defined(RTE_USART5) && RTE_USART5
+extern ARM_DRIVER_USART Driver_USART5;
+#endif /* USART5 */
+
+#if defined(USART6) && defined(RTE_USART6) && RTE_USART6
+extern ARM_DRIVER_USART Driver_USART6;
+#endif /* USART6 */
+
+#if defined(USART7) && defined(RTE_USART7) && RTE_USART7
+extern ARM_DRIVER_USART Driver_USART7;
+#endif /* USART7 */
+
+#if defined(USART8) && defined(RTE_USART8) && RTE_USART8
+extern ARM_DRIVER_USART Driver_USART8;
+#endif /* USART8 */
+
+#if defined(USART9) && defined(RTE_USART9) && RTE_USART9
+extern ARM_DRIVER_USART Driver_USART9;
+#endif /* USART9 */
+
+#if defined(USART10) && defined(RTE_USART10) && RTE_USART10
+extern ARM_DRIVER_USART Driver_USART10;
+#endif /* USART10 */
+
+#if defined(USART11) && defined(RTE_USART11) && RTE_USART11
+extern ARM_DRIVER_USART Driver_USART11;
+#endif /* USART11 */
+
+#if defined(USART12) && defined(RTE_USART12) && RTE_USART12
+extern ARM_DRIVER_USART Driver_USART12;
+#endif /* USART12 */
+
+#if defined(USART13) && defined(RTE_USART13) && RTE_USART13
+extern ARM_DRIVER_USART Driver_USART13;
+#endif /* USART13 */
+
+/* USART Driver state flags */
+#define USART_FLAG_UNINIT     (0UL)
+#define USART_FLAG_INIT       (1UL << 0)
+#define USART_FLAG_POWER      (1UL << 1)
+#define USART_FLAG_CONFIGURED (1UL << 2)
+
+#endif /* _FSL_USART_CMSIS_H_ */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2018, NXP
+ * Copyright 2018-2021, NXP
  * All rights reserved.
  *
  *
@@ -60,9 +60,9 @@ static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base)
 }
 
 /*!
- * @brief Enable the access to ANACTRL registers and initialize ANACTRL module.
+ * brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function.
  *
- * @param base ANACTRL peripheral base address.
+ * param base ANACTRL peripheral base address.
  */
 void ANACTRL_Init(ANACTRL_Type *base)
 {
@@ -75,9 +75,9 @@ void ANACTRL_Init(ANACTRL_Type *base)
 }
 
 /*!
- * @brief De-initialize ANACTRL module.
+ * brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function.
  *
- * @param base ANACTRL peripheral base address.
+ * param base ANACTRL peripheral base address.
  */
 void ANACTRL_Deinit(ANACTRL_Type *base)
 {
@@ -90,214 +90,144 @@ void ANACTRL_Deinit(ANACTRL_Type *base)
 }
 
 /*!
- * @brief Set the on-chip high-speed Free Running Oscillator.
+ * brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock output
+ * and enable/disable 96MHZ clock output.
  *
- * @param base ANACTRL peripheral base address.
- * @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure.
+ * param base ANACTRL peripheral base address.
+ * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure.
  */
-void ANACTRL_SetFro192M(ANACTRL_Type *base, anactrl_fro192M_config_t *config)
+void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config)
 {
     assert(NULL != config);
 
-    uint32_t tmp32 = 0;
+    uint32_t tmp32 = base->FRO192M_CTRL;
 
-    /* Set FRO trim values. */
-    base->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_WRTRIM_MASK;
-    tmp32 |= ANACTRL_FRO192M_CTRL_BIAS_TRIM(config->biasTrim) | ANACTRL_FRO192M_CTRL_TEMP_TRIM(config->tempTrim) |
-             ANACTRL_FRO192M_CTRL_DAC_TRIM(config->dacTrim);
+    tmp32 &= ~(ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK);
 
     if (config->enable12MHzClk)
     {
         tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK;
     }
-    if (config->enable48MhzClk)
-    {
-        tmp32 |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK;
-    }
     if (config->enable96MHzClk)
     {
         tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK;
     }
 
-    if (config->enableAnalogTestBus)
-    {
-        tmp32 |= ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK;
-    }
-
     base->FRO192M_CTRL |= tmp32;
 }
 
 /*!
- * @brief Get the default configuration of FRO192M.
+ * brief Gets the default configuration of FRO192M.
  * The default values are:
  * code
- *   config->biasTrim = 0x1AU;
- *   config->tempTrim = 0x20U;
- *   config->enable12MHzClk = true;
- *   config->enable48MhzClk = true;
- *   config->dacTrim = 0x80U;
- *   config->enableAnalogTestBus = false;
- *   config->enable96MHzClk = false;
- * encode
- * @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure.
+    config->enable12MHzClk = true;
+    config->enable96MHzClk = false;
+    endcode
+ * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure.
  */
 void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config)
 {
     assert(NULL != config);
 
     /* Initializes the configure structure to zero. */
-    memset(config, 0, sizeof(*config));
-
-    config->biasTrim            = 0x1AU;
-    config->tempTrim            = 0x20U;
-    config->enable12MHzClk      = true;
-    config->enable48MhzClk      = true;
-    config->dacTrim             = 0x80U;
-    config->enableAnalogTestBus = false;
-    config->enable96MHzClk      = false;
+    (void)memset(config, 0, sizeof(*config));
+
+    config->enable12MHzClk = true;
+    config->enable96MHzClk = false;
 }
 
 /*!
- * @brief Set the 32 MHz Crystal oscillator.
+ * brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU
+ * system, and so on.
  *
- * @param base ANACTRL peripheral base address.
- * @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure.
+ * param base ANACTRL peripheral base address.
+ * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure.
  */
-void ANACTRL_SetXo32M(ANACTRL_Type *base, anactrl_xo32M_config_t *config)
+void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config)
 {
     assert(NULL != config);
 
-    uint32_t tmp32 = 0U;
+    uint32_t tmp32 = base->XO32M_CTRL;
+
+    tmp32 &= ~(ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK | ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK);
 
     /* Set XO32M CTRL. */
-    if (config->enableACBufferBypass)
-    {
-        tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK;
-    }
+#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \
+      FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD)
+    tmp32 &= ~ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;
     if (config->enablePllUsbOutput)
     {
         tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;
     }
+#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */
+
+    if (config->enableACBufferBypass)
+    {
+        tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK;
+    }
+
     if (config->enableSysCLkOutput)
     {
         tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;
     }
     base->XO32M_CTRL = tmp32;
 
-    /* Set LDO XO32M. */
-    tmp32 = ANACTRL_LDO_XO32M_HIGHZ(config->LDOOutputMode) | ANACTRL_LDO_XO32M_VOUT(config->LDOOutputLevel) |
-            ANACTRL_LDO_XO32M_IBIAS(config->bias) | ANACTRL_LDO_XO32M_STABMODE(config->stability);
-    if (config->enableLDOBypass)
+#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \
+     FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD)
+    if (config->enableADCOutput)
     {
-        tmp32 |= ANACTRL_LDO_XO32M_BYPASS_MASK;
+        base->DUMMY_CTRL |= ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK;
     }
-
-    base->LDO_XO32M = tmp32;
+    else
+    {
+        base->DUMMY_CTRL &= ~ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK;
+    }
+#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */
 }
 
 /*!
- * @brief Get the default configuration of XO32M.
+ * brief Gets the default configuration of XO32M.
  * The default values are:
  * code
- *   config->enableACBufferBypass = false;
- *   config->enablePllUsbOutput = false;
- *   config->enableSysCLkOutput = false;
- *   config->enableLDOBypass = false;
- *   config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode;
- *   config->LDOOutputLevel = kANACTRL_LDOOutputLevel4;
- *   config->bias = 2U;
- *   config->stability = 3U;
- * encode
- * @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure.
+    config->enableSysCLkOutput = false;
+    config->enableACBufferBypass = false;
+    endcode
+ * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure.
  */
 void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config)
 {
     assert(NULL != config);
 
     /* Initializes the configure structure to zero. */
-    memset(config, 0, sizeof(*config));
+    (void)memset(config, 0, sizeof(*config));
 
-    config->enableACBufferBypass = false;
-    config->enablePllUsbOutput   = false;
+#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \
+      FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD)
+    config->enablePllUsbOutput = false;
+#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */
     config->enableSysCLkOutput   = false;
-    config->enableLDOBypass      = false;
-    config->LDOOutputMode        = kANACTRL_LDOOutputHighNormalMode;
-    config->LDOOutputLevel       = kANACTRL_LDOOutputLevel4;
-    config->bias                 = 2U;
-    config->stability            = 3U;
-}
-
-/*!
- * @brief Set the ring oscillators.
- *
- * @param base ANACTRL peripheral base address.
- * @param config Pointer to ring osc configuration structure. Refer to "anactrl_ring_osc_config_t" structure.
- */
-void ANACTRL_SetRingOsc(ANACTRL_Type *base, anactrl_ring_osc_config_t *config)
-{
-    assert(NULL != config);
-
-    uint32_t tmp32 = 0U;
-
-    /* Configure the first ring oscillator. */
-    tmp32 = ANACTRL_RINGO0_CTRL_SL(config->ringOscSel) | ANACTRL_RINGO0_CTRL_FS(config->ringOscFreqOutputDiv) |
-            ANACTRL_RINGO0_CTRL_SWN_SWP(config->pnRingOscMode) | ANACTRL_RINGO0_CTRL_E_ND0_MASK |
-            ANACTRL_RINGO0_CTRL_E_ND1_MASK | ANACTRL_RINGO0_CTRL_E_NR0_MASK | ANACTRL_RINGO0_CTRL_E_NR1_MASK |
-            ANACTRL_RINGO0_CTRL_E_IV0_MASK | ANACTRL_RINGO0_CTRL_E_IV1_MASK | ANACTRL_RINGO0_CTRL_E_PN0_MASK |
-            ANACTRL_RINGO0_CTRL_E_PN1_MASK | ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK |
-            ANACTRL_RINGO0_CTRL_DIVISOR(config->ringOscOutClkDiv);
-    base->RINGO0_CTRL = tmp32;
-
-    /* Configure the second and third ring oscillator. */
-    tmp32 = ANACTRL_RINGO1_CTRL_S(config->ringOscSel) | ANACTRL_RINGO1_CTRL_FS(config->ringOscFreqOutputDiv) |
-            ANACTRL_RINGO1_CTRL_E_R24_MASK | ANACTRL_RINGO1_CTRL_E_R35_MASK | ANACTRL_RINGO1_CTRL_E_M2_MASK |
-            ANACTRL_RINGO1_CTRL_E_M3_MASK | ANACTRL_RINGO1_CTRL_E_M4_MASK | ANACTRL_RINGO1_CTRL_E_M5_MASK |
-            ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK | ANACTRL_RINGO1_CTRL_DIVISOR(config->ringOscOutClkDiv);
-    base->RINGO1_CTRL = tmp32;
-    base->RINGO2_CTRL = tmp32;
-
-    /* Ensure the Riongo module is enabled. */
-    base->RINGO0_CTRL &= ~ANACTRL_RINGO0_CTRL_PD_MASK;
-    base->RINGO1_CTRL &= ~ANACTRL_RINGO1_CTRL_PD_MASK;
-    base->RINGO2_CTRL &= ~ANACTRL_RINGO2_CTRL_PD_MASK;
-}
-
-/*!
- * @brief Get the default configuration of ring oscillators.
- * The default values are:
- * code
- *   config->ringOscSel = kANACTRL_ShortRingOsc;
- *   config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput;
- *   config->pnRingOscMode = kANACTRL_NormalMode;
- *   config->ringOscOutClkDiv = 0U;
- * encode
- * @param config Pointer to ring oscillator configuration structure. Refer to "anactrl_ring_osc_config_t" structure.
- */
-void ANACTRL_GetDefaultRingOscConfig(anactrl_ring_osc_config_t *config)
-{
-    assert(NULL != config);
-
-    /* Initializes the configure structure to zero. */
-    memset(config, 0, sizeof(*config));
-
-    config->ringOscSel           = kANACTRL_ShortRingOsc;
-    config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput;
-    config->pnRingOscMode        = kANACTRL_NormalMode;
-    config->ringOscOutClkDiv     = 0U;
+    config->enableACBufferBypass = false;
+#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \
+     FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD)
+    config->enableADCOutput = true;
+#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */
 }
 
+#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL)
 /*!
- * @brief Measure Frequency
+ * brief Measures the frequency of the target clock source.
  *
  * This function measures target frequency according to a accurate reference frequency.The formula is:
  * Ftarget = (CAPVAL * Freference) / ((1<<SCALE)-1)
  *
- * @param base ANACTRL peripheral base address.
- * @scale Define the power of 2 count that ref counter counts to during measurement.
- * @refClkFreq frequency of the reference clock.
- * @return frequency of the target clock.
+ * note Both tartget and reference clocks are selectable by programming the target clock select FREQMEAS_TARGET register
+ * in INPUTMUX and reference clock select FREQMEAS_REF register in INPUTMUX.
+ *
+ * param base ANACTRL peripheral base address.
+ * param scale Define the power of 2 count that ref counter counts to during measurement, ranges from 2 to 31.
+ * param refClkFreq frequency of the reference clock.
  *
- * @Note the minimum count (scale) is 2.
+ * return frequency of the target clock.
  */
 uint32_t ANACTRL_MeasureFrequency(ANACTRL_Type *base, uint8_t scale, uint32_t refClkFreq)
 {
@@ -314,7 +244,8 @@ uint32_t ANACTRL_MeasureFrequency(ANACTRL_Type *base, uint8_t scale, uint32_t re
 
     /* Calculate the target clock frequency. */
     capval        = (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK);
-    targetClkFreq = (capval * refClkFreq) / ((1 << scale) - 1);
+    targetClkFreq = (capval * refClkFreq) / ((1UL << scale) - 1UL);
 
     return targetClkFreq;
 }
+#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2018, NXP
+ * Copyright 2018-2021, NXP
  * All rights reserved.
  *
  *
@@ -20,31 +20,41 @@
  * Definitions
  ******************************************************************************/
 /*! @brief ANACTRL driver version. */
-#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */`
+#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */`
 
 /*!
  * @brief ANACTRL interrupt flags
  */
 enum _anactrl_interrupt_flags
 {
-    kANACTRL_BodVbatFlag =
-        ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before Interrupt Enable. */
-    kANACTRL_BodVbatInterruptFlag =
-        ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status after Interrupt Enable. */
-    kANACTRL_BodVbatPowerFlag =
-        ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power status output. */
-    kANACTRL_BodCoreFlag =
-        ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before Interrupt Enable. */
-    kANACTRL_BodCoreInterruptFlag =
-        ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status after Interrupt Enable. */
-    kANACTRL_BodCorePowerFlag =
-        ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK, /*!< Current value of BOD CORE power status output. */
-    kANACTRL_DcdcFlag =
-        ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK, /*!< DCDC Interrupt status before Interrupt Enable. */
-    kANACTRL_DcdcInterruptFlag =
-        ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after Interrupt Enable. */
-    kANACTRL_DcdcPowerFlag =
-        ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK, /*!< Current value of DCDC power status output. */
+#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN)
+    kANACTRL_BodVDDMainFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status
+                                                                               before Interrupt Enable. */
+    kANACTRL_BodVDDMainInterruptFlag =
+        ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK,                     /*!< BOD VDDMAIN Interrupt status
+                                                                                 after Interrupt Enable. */
+    kANACTRL_BodVDDMainPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK, /*!< Current value of BOD VDDMAIN
+                                                                                   power status output. */
+#else
+    kANACTRL_BodVbatFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before
+                                                                                Interrupt Enable. */
+    kANACTRL_BodVbatInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status
+                                                                                            after Interrupt Enable. */
+    kANACTRL_BodVbatPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power
+                                                                                    status output. */
+#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */
+    kANACTRL_BodCoreFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before
+                                                                                Interrupt Enable. */
+    kANACTRL_BodCoreInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status
+                                                                                            after Interrupt Enable. */
+    kANACTRL_BodCorePowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK,      /*!< Current value of BOD CORE power
+                                                                                         status output. */
+    kANACTRL_DcdcFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK,              /*!< DCDC Interrupt status before
+                                                                                         Interrupt Enable. */
+    kANACTRL_DcdcInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after
+                                                                                        Interrupt Enable. */
+    kANACTRL_DcdcPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK,            /*!< Current value of DCDC power
+                                                                                       status output. */
 };
 
 /*!
@@ -52,19 +62,16 @@ enum _anactrl_interrupt_flags
  */
 enum _anactrl_interrupt
 {
-    kANACTRL_BodVbatInterruptEnable =
-        ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt control. */
-    kANACTRL_BodCoreInterruptEnable =
-        ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK,                         /*!< BOD CORE interrupt control. */
-    kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK, /*!< DCDC interrupt control. */
-    kANACTRL_BodVbatInterruptClear =
-        ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK, /*!< BOD VBAT interrupt clear.1: Clear the interrupt.
-                                                             Self-cleared bit. */
-    kANACTRL_BodCoreInterruptClear =
-        ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK, /*!< BOD CORE interrupt clear.1: Clear the interrupt.
-                                                             Self-cleared bit. */
-    kANACTRL_DcdcInterruptClear = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK, /*!< DCDC interrupt clear.1: Clear the
-                                                                                    interrupt. Self-cleared bit. */
+#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN)
+    kANACTRL_BodVDDMainInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK, /*!< BOD VDDMAIN
+                                                                                            interrupt control. */
+#else
+    kANACTRL_BodVbatInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt
+                                                                                            control. */
+#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */
+    kANACTRL_BodCoreInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt
+                                                                                            control. */
+    kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK,       /*!< DCDC interrupt control. */
 };
 
 /*!
@@ -72,15 +79,9 @@ enum _anactrl_interrupt
  */
 enum _anactrl_flags
 {
-    kANACTRL_PMUId = ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK, /*!< Power Management Unit (PMU) analog macro-bloc
-                                                                identification number. */
-    kANACTRL_OSCId =
-        ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK, /*!< Oscillators analog macro-bloc identification number. */
-    kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK, /*!< Flash power-down status. */
-    kANACTRL_FlashInitErrorFlag =
-        ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization error status. */
-    kANACTRL_FinalTestFlag =
-        ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK, /*!< Indicates current status of final test. */
+    kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK,     /*!< Flash power-down status. */
+    kANACTRL_FlashInitErrorFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization
+                                                                                          error status. */
 };
 
 /*!
@@ -88,68 +89,15 @@ enum _anactrl_flags
  */
 enum _anactrl_osc_flags
 {
-    kANACTRL_OutputClkValidFlag = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK, /*!< Output clock valid signal. */
-    kANACTRL_CCOThresholdVoltageFlag =
-        ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK, /*!< CCO threshold voltage detector output (signal vcco_ok). */
-    kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK
-                                    << 16U, /*!< Indicates XO out frequency statibilty. */
+    kANACTRL_OutputClkValidFlag      = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK,  /*!< Output clock valid signal. */
+    kANACTRL_CCOThresholdVoltageFlag = ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK,  /*!< CCO threshold voltage detector
+                                                                                     output (signal vcco_ok). */
+    kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK << 16U, /*!< Indicates XO out
+                                                                                    frequency statibilty. */
 };
 
 /*!
- * @brief LDO output mode
- */
-typedef enum _anactrl_ldo_output_mode
-{
-    kANACTRL_LDOOutputHighNormalMode    = 0U, /*!< Output in High normal state. */
-    kANACTRL_LDOOutputHighImpedanceMode = 1U, /*!< Output in High Impedance state. */
-} anactrl_ldo_output_mode_t;
-
-/*!
- * @brief LDO output level
- */
-typedef enum _anactrl_ldo_output_level
-{
-    kANACTRL_LDOOutputLevel0 = 0U, /*!< Output level 0.750 V. */
-    kANACTRL_LDOOutputLevel1,      /*!< Output level 0.775 V. */
-    kANACTRL_LDOOutputLevel2,      /*!< Output level 0.800 V. */
-    kANACTRL_LDOOutputLevel3,      /*!< Output level 0.825 V. */
-    kANACTRL_LDOOutputLevel4,      /*!< Output level 0.850 V. */
-    kANACTRL_LDOOutputLevel5,      /*!< Output level 0.875 V. */
-    kANACTRL_LDOOutputLevel6,      /*!< Output level 0.900 V. */
-    kANACTRL_LDOOutputLevel7,      /*!< Output level 0.925 V. */
-} anactrl_ldo_output_level_t;
-
-/*!
- * @brief Select short or long ring osc
- */
-typedef enum _anactrl_ring_osc_selector
-{
-    kANACTRL_ShortRingOsc = 0U, /*!< Select short ring osc (few elements). */
-    kANACTRL_LongRingOsc  = 1U, /*!< Select long ring osc (many elements). */
-} anactrl_ring_osc_selector_t;
-
-/*!
- * @brief Ring osc frequency output divider
- */
-typedef enum _anactrl_ring_osc_freq_output_divider
-{
-    kANACTRL_HighFreqOutput = 0U, /*!< High frequency output (frequency lower than 100 MHz). */
-    kANACTRL_LowFreqOutput  = 1U, /*!< Low frequency output (frequency lower than 10 MHz). */
-} anactrl_ring_osc_freq_output_divider_t;
-
-/*!
- * @brief PN-Ring osc (P-Transistor and N-Transistor processing) control.
- */
-typedef enum _anactrl_pn_ring_osc_mode
-{
-    kANACTRL_NormalMode              = 0U, /*!< Normal mode. */
-    kANACTRL_PMonitorPTransistorMode = 1U, /*!< P-Monitor mode. Measure with weak P transistor. */
-    kANACTRL_PMonitorNTransistorMode = 2U, /*!< P-Monitor mode. Measure with weak N transistor. */
-    kANACTRL_NotUse                  = 3U, /*!< Do not use. */
-} anactrl_pn_ring_osc_mode_t;
-
-/*!
- * @breif Configuration for FRO192M
+ * @brief Configuration for FRO192M
  *
  * This structure holds the configuration settings for the on-chip high-speed Free Running Oscillator. To initialize
  * this structure to reasonable defaults, call the ANACTRL_GetDefaultFro192MConfig() function and pass a
@@ -157,18 +105,12 @@ typedef enum _anactrl_pn_ring_osc_mode
  */
 typedef struct _anactrl_fro192M_config
 {
-    uint8_t biasTrim;         /*!< Set bias trimming value (course frequency trimming). */
-    uint8_t tempTrim;         /*!< Set temperature coefficient trimming value. */
-    uint8_t dacTrim;          /*!< Set curdac trimming value (fine frequency trimming) This trim is used to
-        adjust the frequency, given that the bias and temperature trim are set. */
-    bool enable12MHzClk;      /*!< Enable 12MHz clock. */
-    bool enable48MhzClk;      /*!< Enable 48MHz clock. */
-    bool enable96MHzClk;      /*!< Enable 96MHz clock. */
-    bool enableAnalogTestBus; /*!< Enable analog test bus. */
+    bool enable12MHzClk; /*!< Enable 12MHz clock. */
+    bool enable96MHzClk; /*!< Enable 96MHz clock. */
 } anactrl_fro192M_config_t;
 
 /*!
- * @breif Configuration for XO32M
+ * @brief Configuration for XO32M
  *
  * This structure holds the configuration settings for the 32 MHz crystal oscillator. To initialize this
  * structure to reasonable defaults, call the ANACTRL_GetDefaultXo32MConfig() function and pass a
@@ -176,30 +118,18 @@ typedef struct _anactrl_fro192M_config
  */
 typedef struct _anactrl_xo32M_config
 {
-    bool enableACBufferBypass;                 /*!< Enable XO AC buffer bypass in pll and top level. */
-    bool enablePllUsbOutput;                   /*!< Enable XO 32 MHz output to USB HS PLL. */
-    bool enableSysCLkOutput;                   /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */
-    bool enableLDOBypass;                      /*!< Activate LDO bypass. */
-    anactrl_ldo_output_mode_t LDOOutputMode;   /*!< Set LDO output mode. */
-    anactrl_ldo_output_level_t LDOOutputLevel; /*!< Set LDO output level. */
-    uint8_t bias;                              /*!< Adjust the biasing current. */
-    uint8_t stability;                         /*!< Stability configuration. */
+    bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */
+#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \
+      FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD)
+    bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */
+#endif                       /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */
+    bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */
+#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \
+     FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD)
+    bool enableADCOutput; /*!< Enable High speed crystal oscillator output to ADC. */
+#endif                    /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */
 } anactrl_xo32M_config_t;
 
-/*!
- * @breif Configuration for ring oscillator
- *
- * This structure holds the configuration settings for the three ring oscillators. To initialize this
- * structure to reasonable defaults, call the ANACTRL_GetDefaultRingOscConfig() function and pass a
- * pointer to your config structure instance.
- */
-typedef struct _anactrl_ring_osc_config
-{
-    anactrl_ring_osc_selector_t ringOscSel;
-    anactrl_ring_osc_freq_output_divider_t ringOscFreqOutputDiv;
-    anactrl_pn_ring_osc_mode_t pnRingOscMode;
-    uint8_t ringOscOutClkDiv;
-} anactrl_ring_osc_config_t;
 /*******************************************************************************
  * API
  ******************************************************************************/
@@ -214,14 +144,14 @@ extern "C" {
  */
 
 /*!
- * @brief Enable the access to ANACTRL registers and initialize ANACTRL module.
+ * @brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function.
  *
  * @param base ANACTRL peripheral base address.
  */
 void ANACTRL_Init(ANACTRL_Type *base);
 
 /*!
- * @brief De-initialize ANACTRL module.
+ * @brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function.
  *
  * @param base ANACTRL peripheral base address.
  */
@@ -234,120 +164,71 @@ void ANACTRL_Deinit(ANACTRL_Type *base);
  */
 
 /*!
- * @brief Set the on-chip high-speed Free Running Oscillator.
+ * @brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock
+ * output and enable/disable 96MHZ clock output.
  *
  * @param base ANACTRL peripheral base address.
- * @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure.
+ * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure.
  */
-void ANACTRL_SetFro192M(ANACTRL_Type *base, anactrl_fro192M_config_t *config);
+void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config);
 
 /*!
- * @brief Get the default configuration of FRO192M.
+ * @brief Gets the default configuration of FRO192M.
  * The default values are:
- * code
- *   config->biasTrim = 0x1AU;
- *   config->tempTrim = 0x20U;
- *   config->enable12MHzClk = true;
- *   config->enable48MhzClk = true;
- *   config->dacTrim = 0x80U;
- *   config->enableAnalogTestBus = false;
- *   config->enable96MHzClk = false;
- * encode
- * @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure.
+ * @code
+    config->enable12MHzClk = true;
+    config->enable96MHzClk = false;
+    @endcode
+ * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure.
  */
 void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config);
 
 /*!
- * @brief Set the 32 MHz Crystal oscillator.
+ * @brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU
+ * system, and so on.
  *
  * @param base ANACTRL peripheral base address.
- * @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure.
+ * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure.
  */
-void ANACTRL_SetXo32M(ANACTRL_Type *base, anactrl_xo32M_config_t *config);
+void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config);
 
 /*!
- * @brief Get the default configuration of XO32M.
+ * @brief Gets the default configuration of XO32M.
  * The default values are:
- * code
- *   config->enableACBufferBypass = false;
- *   config->enablePllUsbOutput = false;
- *   config->enableSysCLkOutput = false;
- *   config->enableLDOBypass = false;
- *   config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode;
- *   config->LDOOutputLevel = kANACTRL_LDOOutputLevel4;
- *   config->bias = 2U;
- *   config->stability = 3U;
- * encode
- * @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure.
+ * @code
+    config->enableSysCLkOutput = false;
+    config->enableACBufferBypass = false;
+    @endcode
+ * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure.
  */
 void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config);
 
-/*!
- * @brief Set the ring oscillators.
- *
- * @param base ANACTRL peripheral base address.
- * @param config Pointer to ring osc configuration structure. Refer to "anactrl_ring_osc_config_t" structure.
- */
-void ANACTRL_SetRingOsc(ANACTRL_Type *base, anactrl_ring_osc_config_t *config);
-
-/*!
- * @brief Get the default configuration of ring oscillators.
- * The default values are:
- * code
- *   config->ringOscSel = kANACTRL_ShortRingOsc;
- *   config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput;
- *   config->pnRingOscMode = kANACTRL_NormalMode;
- *   config->ringOscOutClkDiv = 0U;
- * encode
- * @param config Pointer to ring oscillator configuration structure. Refer to "anactrl_ring_osc_config_t" structure.
- */
-void ANACTRL_GetDefaultRingOscConfig(anactrl_ring_osc_config_t *config);
-/* @} */
-
-/*!
- * @name ADC control
- * @{
- */
-
-/*!
- * @brief Enable VBAT divider branch.
- *
- * @param base ANACTRL peripheral base address.
- * @param enable switcher to the function.
- */
-static inline void ANACTRL_EnableAdcVBATDivider(ANACTRL_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->ADC_CTRL |= ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK;
-    }
-    else
-    {
-        base->ADC_CTRL &= ~ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK;
-    }
-}
 /* @} */
 
+#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL)
 /*!
  * @name Measure Frequency
  * @{
  */
 
 /*!
- * @brief Measure Frequency
+ * @brief Measures the frequency of the target clock source.
  *
  * This function measures target frequency according to a accurate reference frequency.The formula is:
  * Ftarget = (CAPVAL * Freference) / ((1<<SCALE)-1)
  *
+ * @note Both tartget and reference clocks are selectable by programming the target clock select FREQMEAS_TARGET
+ * register in INPUTMUX and reference clock select FREQMEAS_REF register in INPUTMUX.
+ *
  * @param base ANACTRL peripheral base address.
- * @scale Define the power of 2 count that ref counter counts to during measurement.
- * @refClkFreq frequency of the reference clock.
- * @return frequency of the target clock.
+ * @param scale Define the power of 2 count that ref counter counts to during measurement, ranges from 2 to 31.
+ * @param refClkFreq frequency of the reference clock.
  *
- * @Note the minimum count (scale) is 2.
+ * @return frequency of the target clock.
  */
 uint32_t ANACTRL_MeasureFrequency(ANACTRL_Type *base, uint8_t scale, uint32_t refClkFreq);
 /* @} */
+#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */
 
 /*!
  * @name Interrupt Interface
@@ -355,25 +236,36 @@ uint32_t ANACTRL_MeasureFrequency(ANACTRL_Type *base, uint8_t scale, uint32_t re
  */
 
 /*!
- * @brief Enable the ANACTRL interrupts.
+ * @brief Enables the ANACTRL interrupts.
  *
- * @param bas ANACTRL peripheral base address.
+ * @param base ANACTRL peripheral base address.
  * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration.
  */
-static inline void ANACTRL_EnableInterrupt(ANACTRL_Type *base, uint32_t mask)
+static inline void ANACTRL_EnableInterrupts(ANACTRL_Type *base, uint32_t mask)
 {
     base->BOD_DCDC_INT_CTRL |= (0x15U & mask);
 }
 
 /*!
- * @brief Disable the ANACTRL interrupts.
+ * @brief Disables the ANACTRL interrupts.
+ *
+ * @param base ANACTRL peripheral base address.
+ * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration.
+ */
+static inline void ANACTRL_DisableInterrupts(ANACTRL_Type *base, uint32_t mask)
+{
+    base->BOD_DCDC_INT_CTRL &= ~(0x15U & mask);
+}
+
+/*!
+ * @brief Clears the ANACTRL interrupts.
  *
- * @param bas ANACTRL peripheral base address.
+ * @param base ANACTRL peripheral base address.
  * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration.
  */
-static inline void ANACTRL_DisableInterrupt(ANACTRL_Type *base, uint32_t mask)
+static inline void ANACTRL_ClearInterrupts(ANACTRL_Type *base, uint32_t mask)
 {
-    base->BOD_DCDC_INT_CTRL = (base->BOD_DCDC_INT_CTRL & ~0x2AU) | (mask & 0x2AU);
+    base->BOD_DCDC_INT_CTRL |= (uint32_t)(mask << 1UL);
 }
 /* @} */
 
@@ -383,7 +275,7 @@ static inline void ANACTRL_DisableInterrupt(ANACTRL_Type *base, uint32_t mask)
  */
 
 /*!
- * @brief Get ANACTRL status flags.
+ * @brief Gets ANACTRL status flags.
  *
  * This function gets Analog control status flags. The flags are returned as the logical
  * OR value of the enumerators @ref _anactrl_flags. To check for a specific status,
@@ -405,7 +297,7 @@ static inline uint32_t ANACTRL_GetStatusFlags(ANACTRL_Type *base)
 }
 
 /*!
- * @brief Get ANACTRL oscillators status flags.
+ * @brief Gets ANACTRL oscillators status flags.
  *
  * This function gets Anactrl oscillators status flags. The flags are returned as the logical
  * OR value of the enumerators @ref _anactrl_osc_flags. To check for a specific status,
@@ -427,7 +319,7 @@ static inline uint32_t ANACTRL_GetOscStatusFlags(ANACTRL_Type *base)
 }
 
 /*!
- * @brief Get ANACTRL interrupt status flags.
+ * @brief Gets ANACTRL interrupt status flags.
  *
  * This function gets Anactrl interrupt status flags. The flags are returned as the logical
  * OR value of the enumerators @ref _anactrl_interrupt_flags. To check for a specific status,
@@ -449,6 +341,33 @@ static inline uint32_t ANACTRL_GetInterruptStatusFlags(ANACTRL_Type *base)
 }
 /* @} */
 
+#if (defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) && (FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG == 1U))
+/*!
+ * @brief Aux_Bias Control Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Enables/disabless 1V reference voltage buffer.
+ *
+ * @param base ANACTRL peripheral base address.
+ * @param enable Used to enable or disable 1V reference voltage buffer.
+ */
+static inline void ANACTRL_EnableVref1V(ANACTRL_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->AUX_BIAS |= ANACTRL_AUX_BIAS_VREF1VENABLE_MASK;
+    }
+    else
+    {
+        base->AUX_BIAS &= ~ANACTRL_AUX_BIAS_VREF1VENABLE_MASK;
+    }
+}
+
+/* @} */
+#endif /* defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) */
+
 #if defined(__cplusplus)
 }
 #endif

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 NXP
+ * Copyright 2018-2021 NXP
  * All rights reserved.
  *
  *
@@ -23,9 +23,9 @@
  */
 /*! @name Driver version */
 /*@{*/
-/*! @brief CASPER driver version. Version 2.0.2.
+/*! @brief CASPER driver version. Version 2.2.3.
  *
- * Current version: 2.0.2
+ * Current version: 2.2.3
  *
  * Change log:
  * - Version 2.0.0
@@ -33,9 +33,38 @@
  * - Version 2.0.1
  *   - Bug fix KPSDK-24531 double_scalar_multiplication() result may be all zeroes for some specific input
  * - Version 2.0.2
- *   - Bug fix KPSDK-25015 CASPER_MEMCPY hard-fault on LPC55xx when both source and destination buffers are outside of CASPER_RAM
+ *   - Bug fix KPSDK-25015 CASPER_MEMCPY hard-fault on LPC55xx when both source and destination buffers are outside of
+ * CASPER_RAM
+ * - Version 2.0.3
+ *   - Bug fix KPSDK-28107 RSUB, FILL and ZERO operations not implemented in enum _casper_operation.
+ * - Version 2.0.4
+ *   - For GCC compiler, enforce O1 optimize level, specifically to remove strict-aliasing option.
+ *     This driver is very specific and requires -fno-strict-aliasing.
+ * - Version 2.0.5
+ *   - Fix sign-compare warning.
+ * - Version 2.0.6
+ *   - Fix IAR Pa082 warning.
+ * - Version 2.0.7
+ *   - Fix MISRA-C 2012 issue.
+ * - Version 2.0.8
+ *   - Add feature macro for CASPER_RAM_OFFSET.
+ * - Version 2.0.9
+ *   - Remove unused function Jac_oncurve().
+ *   - Fix ECC384 build.
+ * - Version 2.0.10
+ *   - Fix MISRA-C 2012 issue.
+ * - Version 2.1.0
+ *   - Add ECC NIST P-521 elliptic curve.
+ * - Version 2.2.0
+ *   - Rework driver to support multiple curves at once.
+ * - Version 2.2.1
+ *   - Fix MISRA-C 2012 issue.
+ * - Version 2.2.2
+ *   - Enable hardware interleaving to RAMX0 and RAMX1 for CASPER by feature macro FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE
+ * - Version 2.2.3
+ *   - Added macro into CASPER_Init and CASPER_Deinit to support devices without clock and reset control.
  */
-#define FSL_CASPER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+#define FSL_CASPER_DRIVER_VERSION (MAKE_VERSION(2, 2, 3))
 /*@}*/
 
 /*! @brief CASPER operation
@@ -51,40 +80,51 @@ typedef enum _casper_operation
     kCASPER_OpMul6464Reduce =
         0x04,               /*! Walking 1 or more of J loop, doing c,r[-1]=r+a*b using 64x64=128, but skip 1st write*/
     kCASPER_OpAdd64 = 0x08, /*! Walking add with off_AB, and in/out off_RES doing c,r=r+a+c using 64+64=65*/
-    kCASPER_OpSub64 = 0x09, /*! Walking subtract with off_AB, and in/out off_RES doing r=r-a uding 64-64=64, with last
+    kCASPER_OpSub64 = 0x09, /*! Walking subtract with off_AB, and in/out off_RES doing r=r-a using 64-64=64, with last
                                borrow implicit if any*/
     kCASPER_OpDouble64 = 0x0A, /*! Walking add to self with off_RES doing c,r=r+r+c using 64+64=65*/
-    kCASPER_OpXor64 = 0x0B,    /*! Walking XOR with off_AB, and in/out off_RES doing r=r^a using 64^64=64*/
+    kCASPER_OpXor64    = 0x0B, /*! Walking XOR with off_AB, and in/out off_RES doing r=r^a using 64^64=64*/
+    kCASPER_OpRSub64   = 0x0C, /*! Walking subtract with off_AB, and in/out off_RES using r=a-r */
     kCASPER_OpShiftLeft32 =
         0x10, /*! Walking shift left doing r1,r=(b*D)|r1, where D is 2^amt and is loaded by app (off_CD not used)*/
     kCASPER_OpShiftRight32 = 0x11, /*! Walking shift right doing r,r1=(b*D)|r1, where D is 2^(32-amt) and is loaded by
                                       app (off_CD not used) and off_RES starts at MSW*/
-    kCASPER_OpCopy = 0x14,         /*! Copy from ABoff to resoff, 64b at a time*/
-    kCASPER_OpRemask = 0x15,       /*! Copy and mask from ABoff to resoff, 64b at a time*/
-    kCASPER_OpCompare = 0x16,      /*! Compare two arrays, running all the way to the end*/
-    kCASPER_OpCompareFast = 0x17,  /*! Compare two arrays, stopping on 1st !=*/
+    kCASPER_OpCopy        = 0x14,  /*! Copy from ABoff to resoff, 64b at a time*/
+    kCASPER_OpRemask      = 0x15,  /*! Copy and mask from ABoff to resoff, 64b at a time*/
+    kCASPER_OpFill        = 0x16,  /*! Fill RESOFF using 64 bits at a time with value in A and B */
+    kCASPER_OpZero        = 0x17,  /*! Fill RESOFF using 64 bits at a time of 0s */
+    kCASPER_OpCompare     = 0x18,  /*! Compare two arrays, running all the way to the end*/
+    kCASPER_OpCompareFast = 0x19,  /*! Compare two arrays, stopping on 1st !=*/
 } casper_operation_t;
 
-#define CASPER_CP 1
-#define CASPER_CP_CTRL0 (0x0 >> 2)
-#define CASPER_CP_CTRL1 (0x4 >> 2)
-#define CASPER_CP_LOADER (0x8 >> 2)
-#define CASPER_CP_STATUS (0xC >> 2)
+/*! @brief Algorithm used for CASPER operation */
+typedef enum _casper_algo_t
+{
+    kCASPER_ECC_P256 = 0x01, /*!< ECC_P256*/
+    kCASPER_ECC_P384 = 0x02, /*!< ECC_P384 */
+    kCASPER_ECC_P521 = 0x03, /*!< ECC_P521 */
+} casper_algo_t;
+
+#define CASPER_CP          1
+#define CASPER_CP_CTRL0    (0x0 >> 2)
+#define CASPER_CP_CTRL1    (0x4 >> 2)
+#define CASPER_CP_LOADER   (0x8 >> 2)
+#define CASPER_CP_STATUS   (0xC >> 2)
 #define CASPER_CP_INTENSET (0x10 >> 2)
 #define CASPER_CP_INTENCLR (0x14 >> 2)
-#define CASPER_CP_INTSTAT (0x18 >> 2)
-#define CASPER_CP_AREG (0x20 >> 2)
-#define CASPER_CP_BREG (0x24 >> 2)
-#define CASPER_CP_CREG (0x28 >> 2)
-#define CASPER_CP_DREG (0x2C >> 2)
-#define CASPER_CP_RES0 (0x30 >> 2)
-#define CASPER_CP_RES1 (0x34 >> 2)
-#define CASPER_CP_RES2 (0x38 >> 2)
-#define CASPER_CP_RES3 (0x3C >> 2)
-#define CASPER_CP_MASK (0x60 >> 2)
-#define CASPER_CP_REMASK (0x64 >> 2)
-#define CASPER_CP_LOCK (0x80 >> 2)
-#define CASPER_CP_ID (0xFFC >> 2)
+#define CASPER_CP_INTSTAT  (0x18 >> 2)
+#define CASPER_CP_AREG     (0x20 >> 2)
+#define CASPER_CP_BREG     (0x24 >> 2)
+#define CASPER_CP_CREG     (0x28 >> 2)
+#define CASPER_CP_DREG     (0x2C >> 2)
+#define CASPER_CP_RES0     (0x30 >> 2)
+#define CASPER_CP_RES1     (0x34 >> 2)
+#define CASPER_CP_RES2     (0x38 >> 2)
+#define CASPER_CP_RES3     (0x3C >> 2)
+#define CASPER_CP_MASK     (0x60 >> 2)
+#define CASPER_CP_REMASK   (0x64 >> 2)
+#define CASPER_CP_LOCK     (0x80 >> 2)
+#define CASPER_CP_ID       (0xFFC >> 2)
 /* mcr (cp,  opc1, value, CRn, CRm, opc2) */
 #define CASPER_Wr32b(value, off) __arm_mcr(CASPER_CP, 0, value, ((off >> 4)), (off), 0)
 /* mcrr(coproc, opc1, value, CRm) */
@@ -97,28 +137,15 @@ typedef enum _casper_operation
 /*  it will be slower by a bit. */
 /*  The file is compiled with N_bitlen passed in as number of bits of the RSA key */
 /*  #define N_bitlen 2048 */
-#define N_wordlen_max (4096 / 32)
-
-#define CASPER_ECC_P256 1
-#define CASPER_ECC_P384 0
-
-#if CASPER_ECC_P256
-#define N_bitlen 256
-#endif /* CASPER_ECC_P256 */
-
-#if CASPER_ECC_P384
-#define N_bitlen 384
-#endif /* CASPER_ECC_P256 */
-
-#define NUM_LIMBS (N_bitlen / 32)
+#define N_wordlen_max (4096U / 32U)
 
 enum
 {
-    kCASPER_RamOffset_Result = 0x0u,
-    kCASPER_RamOffset_Base = (N_wordlen_max + 8u),
+    kCASPER_RamOffset_Result   = 0x0u,
+    kCASPER_RamOffset_Base     = (N_wordlen_max + 8u),
     kCASPER_RamOffset_TempBase = (2u * N_wordlen_max + 16u),
-    kCASPER_RamOffset_Modulus = (kCASPER_RamOffset_TempBase + N_wordlen_max + 4u),
-    kCASPER_RamOffset_M64 = 1022,
+    kCASPER_RamOffset_Modulus  = (kCASPER_RamOffset_TempBase + N_wordlen_max + 4u),
+    kCASPER_RamOffset_M64      = 1022U,
 };
 
 /*! @} */
@@ -185,7 +212,15 @@ void CASPER_ModExp(CASPER_Type *base,
                    uint32_t pubE,
                    uint8_t *plaintext);
 
-void CASPER_ecc_init(void);
+/*!
+ * @brief Initialize prime modulus mod in Casper memory .
+ *
+ * Set the prime modulus mod in Casper memory and set N_wordlen
+ * according to selected algorithm.
+ *
+ * @param curve elliptic curve algoritm
+ */
+void CASPER_ecc_init(casper_algo_t curve);
 
 /*!
  * @brief Performs ECC secp256r1 point single scalar multiplication
@@ -287,6 +322,56 @@ void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base,
                                  uint32_t Y2[12],
                                  uint32_t scalar2[12]);
 
+/*!
+ * @brief Performs ECC secp521r1 point single scalar multiplication
+ *
+ * This function performs ECC secp521r1 point single scalar multiplication
+ * [resX; resY] = scalar * [X; Y]
+ * Coordinates are affine in normal form, little endian.
+ * Scalars are little endian.
+ * All arrays are little endian byte arrays, uint32_t type is used
+ * only to enforce the 32-bit alignment (0-mod-4 address).
+ *
+ * @param base CASPER base address
+ * @param[out] resX Output X affine coordinate in normal form, little endian.
+ * @param[out] resY Output Y affine coordinate in normal form, little endian.
+ * @param X Input X affine coordinate in normal form, little endian.
+ * @param Y Input Y affine coordinate in normal form, little endian.
+ * @param scalar Input scalar integer, in normal form, little endian.
+ */
+void CASPER_ECC_SECP521R1_Mul(
+    CASPER_Type *base, uint32_t resX[18], uint32_t resY[18], uint32_t X[18], uint32_t Y[18], uint32_t scalar[18]);
+
+/*!
+ * @brief Performs ECC secp521r1 point double scalar multiplication
+ *
+ * This function performs ECC secp521r1 point double scalar multiplication
+ * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2]
+ * Coordinates are affine in normal form, little endian.
+ * Scalars are little endian.
+ * All arrays are little endian byte arrays, uint32_t type is used
+ * only to enforce the 32-bit alignment (0-mod-4 address).
+ *
+ * @param base CASPER base address
+ * @param[out] resX Output X affine coordinate.
+ * @param[out] resY Output Y affine coordinate.
+ * @param X1 Input X1 affine coordinate.
+ * @param Y1 Input Y1 affine coordinate.
+ * @param scalar1 Input scalar1 integer.
+ * @param X2 Input X2 affine coordinate.
+ * @param Y2 Input Y2 affine coordinate.
+ * @param scalar2 Input scalar2 integer.
+ */
+void CASPER_ECC_SECP521R1_MulAdd(CASPER_Type *base,
+                                 uint32_t resX[18],
+                                 uint32_t resY[18],
+                                 uint32_t X1[18],
+                                 uint32_t Y1[18],
+                                 uint32_t scalar1[18],
+                                 uint32_t X2[18],
+                                 uint32_t Y2[18],
+                                 uint32_t scalar2[18]);
+
 void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2);
 void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1);
 

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_cmp.c

@@ -1,9 +1,9 @@
 /*
- * Copyright 2018 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
 
 #include "fsl_cmp.h"
 
@@ -23,33 +23,106 @@
 /*******************************************************************************
  * Code
  ******************************************************************************/
-void CMP_Init(cmp_config_t *config)
+
+/*!
+ * @brief CMP initialization.
+ *
+ * This function enables the CMP module and do necessary settings.
+ *
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_Init(const cmp_config_t *config)
 {
     assert(NULL != config);
 
-/*enable the clock to the register interface*/
+    uint32_t tmpReg = 0U;
+
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the clock. */
     CLOCK_EnableClock(kCLOCK_Comp);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
-/*Clear reset to peripheral cmp*/
 #if !(defined(FSL_FEATURE_CMP_HAS_NO_RESET) && FSL_TEATURE_CMP_HAS_NO_RESET)
-    RESET_ClearPeripheralReset(kCMP_RST_SHIFT_RSTn);
-#endif
+    /* Reset the CMP module. */
+    RESET_PeripheralReset(kCMP_RST_SHIFT_RSTn);
+#endif /* FSL_FEATURE_CMP_HAS_NO_RESET */
+
+    tmpReg = (PMC->COMP & ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_FILTERCGF_CLKDIV_MASK |
+                            PMC_COMP_FILTERCGF_SAMPLEMODE_MASK));
+
+    if (true == config->enableLowPower)
+    {
+        tmpReg |= PMC_COMP_LOWPOWER_MASK;
+    }
+    else
+    {
+        tmpReg &= ~PMC_COMP_LOWPOWER_MASK;
+    }
 
-    /*clear COMP bits*/
-    PMC->COMP &= ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK);
+    if (true == config->enableHysteresis)
+    {
+        tmpReg |= PMC_COMP_HYST_MASK;
+    }
+    else
+    {
+        tmpReg &= ~PMC_COMP_HYST_MASK;
+    }
 
-    PMC->COMP |= (config->enLowPower << PMC_COMP_LOWPOWER_SHIFT) /*Select if enter low power mode*/
-                 | (config->enHysteris << PMC_COMP_HYST_SHIFT)   /*select if enable hysteresis*/
-                 | config->pmuxInput                             /*pmux input source select*/
-                 | config->nmuxInput;                            /*nmux input source select */
+    tmpReg |= (PMC_COMP_FILTERCGF_CLKDIV(config->filterClockDivider) |
+               PMC_COMP_FILTERCGF_SAMPLEMODE(config->filterSampleMode));
+
+    PMC->COMP = tmpReg;
 }
 
+/*!
+ * @brief CMP deinitialization.
+ *
+ * This function gates the clock for CMP module.
+ */
 void CMP_Deinit(void)
 {
-/*disable the clock to the register interface*/
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the clock. */
     CLOCK_DisableClock(kCLOCK_Comp);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
+
+/*!
+ * @brief Initializes the CMP user configuration structure.
+ *
+ * This function initializes the user configuration structure to these default values.
+ * @code
+ *   config->enableHysteresis    = true;
+ *   config->enableLowPower      = true;
+ *   config->filterClockDivider  = kCMP_FilterClockDivide1;
+ *   config->filterSampleMode    = kCMP_FilterSampleMode0;
+ * @endcode
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_GetDefaultConfig(cmp_config_t *config)
+{
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->enableHysteresis   = true;
+    config->enableLowPower     = true;
+    config->filterClockDivider = kCMP_FilterClockDivide1;
+    config->filterSampleMode   = kCMP_FilterSampleMode0;
+}
+
+/*!
+ * @brief Configures the VREFINPUT.
+ *
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_SetVREF(const cmp_vref_config_t *config)
+{
+    assert(NULL != config);
+    assert(config->vrefValue < 32U);
+
+    uint32_t tmpReg = PMC->COMP & ~(PMC_COMP_VREF_MASK | PMC_COMP_VREFINPUT_MASK);
+
+    tmpReg |= PMC_COMP_VREFINPUT(config->vrefSource) | PMC_COMP_VREF(config->vrefValue);
+
+    PMC->COMP = tmpReg;
+}

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_cmp.h

@@ -1,9 +1,9 @@
 /*
- * Copyright 2018 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
 
 #ifndef __FSL_CMP_H_
 #define __FSL_CMP_H_
@@ -20,61 +20,79 @@
  *****************************************************************************/
 /*! @name Driver version */
 /*@{*/
-/*! @brief Driver version 2.0.0. */
-#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
+/*! @brief Driver version 2.2.1. */
+#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 1U))
 /*@}*/
 
-/*! @brief VREF select */
-enum _cmp_vref_select
+/*! @brief CMP input mux for positive and negative sides. */
+enum _cmp_input_mux
 {
-    KCMP_VREFSelectVDDA = 1U,         /*!< Select VDDA as VREF*/
-    KCMP_VREFSelectInternalVREF = 0U, /*!< select internal VREF as VREF*/
+    kCMP_InputVREF = 0U, /*!< Cmp input from VREF. */
+    kCMP_Input1    = 1U, /*!< Cmp input source 1. */
+    kCMP_Input2    = 2U, /*!< Cmp input source 2. */
+    kCMP_Input3    = 3U, /*!< Cmp input source 3. */
+    kCMP_Input4    = 4U, /*!< Cmp input source 4. */
+    kCMP_Input5    = 5U, /*!< Cmp input source 5. */
 };
 
-/*! @brief cmp interrupt type */
-typedef enum _cmp_interrupt_type
+/*! @brief CMP interrupt type. */
+enum _cmp_interrupt_type
 {
-    kCMP_EdgeDisable = 0U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT,       /*!< disable edge sensitive */
-    kCMP_EdgeRising = 2U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT,        /*!< Edge sensitive, falling edge */
-    kCMP_EdgeFalling = 4U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT,       /*!< Edge sensitive, rising edge */
-    kCMP_EdgeRisingFalling = 6U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Edge sensitive, rising and falling edge */
-
-    kCMP_LevelDisable = 1U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT,  /*!< disable level sensitive */
-    kCMP_LevelHigh = 3U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT,     /*!< Level sensitive, high level */
-    kCMP_LevelLow = 5U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT,      /*!< Level sensitive, low level */
-    kCMP_LevelDisable1 = 7U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< disable level sensitive */
-} cmp_interrupt_type_t;
-
-/*! @brief cmp Pmux input source */
-typedef enum _cmp_pmux_input
+    kCMP_EdgeDisable       = 0U, /*!< Disable edge interupt. */
+    kCMP_EdgeRising        = 2U, /*!< Interrupt on falling edge. */
+    kCMP_EdgeFalling       = 4U, /*!< Interrupt on rising edge. */
+    kCMP_EdgeRisingFalling = 6U, /*!< Interrupt on both rising and falling edges. */
+
+    kCMP_LevelDisable = 1U, /*!< Disable level interupt. */
+    kCMP_LevelHigh    = 3U, /*!< Interrupt on high level. */
+    kCMP_LevelLow     = 5U, /*!< Interrupt on low level. */
+};
+
+/*! @brief CMP Voltage Reference source. */
+typedef enum _cmp_vref_source
 {
-    kCMP_PInputVREF = 0U << PMC_COMP_PMUX_SHIFT,  /*!< Cmp Pmux input from VREF */
-    kCMP_PInputP0_0 = 1U << PMC_COMP_PMUX_SHIFT,  /*!< Cmp Pmux input from P0_0 */
-    kCMP_PInputP0_9 = 2U << PMC_COMP_PMUX_SHIFT,  /*!< Cmp Pmux input from P0_9 */
-    kCMP_PInputP0_18 = 3U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P0_18 */
-    kCMP_PInputP1_14 = 4U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P1_14 */
-    kCMP_PInputP2_23 = 5U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P2_23 */
-} cmp_pmux_input_t;
-
-/*! @brief cmp Nmux input source */
-typedef enum _cmp_nmux_input
+    KCMP_VREFSourceVDDA         = 1U, /*!< Select VDDA as VREF. */
+    KCMP_VREFSourceInternalVREF = 0U, /*!< Select internal VREF as VREF. */
+} cmp_vref_source_t;
+
+typedef struct _cmp_vref_config
 {
-    kCMP_NInputVREF = 0U << PMC_COMP_NMUX_SHIFT,  /*!< Cmp Nmux input from VREF */
-    kCMP_NInputP0_0 = 1U << PMC_COMP_NMUX_SHIFT,  /*!< Cmp Nmux input from P0_0 */
-    kCMP_NInputP0_9 = 2U << PMC_COMP_NMUX_SHIFT,  /*!< Cmp Nmux input from P0_9 */
-    kCMP_NInputP0_18 = 3U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P0_18 */
-    kCMP_NInputP1_14 = 4U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P1_14 */
-    kCMP_NInputP2_23 = 5U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P2_23 */
-} cmp_nmux_input_t;
-
-/*! @brief cmp configurataions */
+    cmp_vref_source_t vrefSource; /*!< Reference voltage source. */
+    uint8_t vrefValue; /*!< Reference voltage step. Available range is 0-31. Per step equals to VREFINPUT/31. */
+} cmp_vref_config_t;
+
+/*! @brief CMP Filter sample mode. */
+typedef enum _cmp_filtercgf_samplemode
+{
+    kCMP_FilterSampleMode0 = 0U, /*!< Bypass mode. Filtering is disabled. */
+    kCMP_FilterSampleMode1 = 1U, /*!< Filter 1 clock period. */
+    kCMP_FilterSampleMode2 = 2U, /*!< Filter 2 clock period. */
+    kCMP_FilterSampleMode3 = 3U  /*!< Filter 3 clock period. */
+} cmp_filtercgf_samplemode_t;
+
+/*! @brief CMP Filter clock divider. */
+typedef enum _cmp_filtercgf_clkdiv
+{
+    kCMP_FilterClockDivide1  = 0U, /*!< Filter clock period duration equals 1 analog comparator clock period. */
+    kCMP_FilterClockDivide2  = 1U, /*!< Filter clock period duration equals 2 analog comparator clock period. */
+    kCMP_FilterClockDivide4  = 2U, /*!< Filter clock period duration equals 4 analog comparator clock period. */
+    kCMP_FilterClockDivide8  = 3U, /*!< Filter clock period duration equals 8 analog comparator clock period. */
+    kCMP_FilterClockDivide16 = 4U, /*!< Filter clock period duration equals 16 analog comparator clock period. */
+    kCMP_FilterClockDivide32 = 5U, /*!< Filter clock period duration equals 32 analog comparator clock period. */
+    kCMP_FilterClockDivide64 = 6U  /*!< Filter clock period duration equals 64 analog comparator clock period. */
+} cmp_filtercgf_clkdiv_t;
+
+/*! @brief CMP configuration structure. */
 typedef struct _cmp_config
 {
-    bool enHysteris;            /*!< low hysteresis */
-    bool enLowPower;            /*!<low power mode*/
-    cmp_nmux_input_t nmuxInput; /*!<Nmux input select*/
-    cmp_pmux_input_t pmuxInput; /*!<Pmux input select*/
+    bool enableHysteresis;                     /*!< Enable hysteresis. */
+    bool enableLowPower;                       /*!< Enable low power mode. */
+    cmp_filtercgf_clkdiv_t filterClockDivider; /* Filter clock divider. Filter clock equals the Analog Comparator clock
+                                                  divided by 2^FILTERCGF_CLKDIV. */
+    cmp_filtercgf_samplemode_t
+        filterSampleMode; /* Filter sample mode. Control the filtering of the Analog Comparator output. */
 } cmp_config_t;
+
 /*************************************************************************************************
  * API
  ************************************************************************************************/
@@ -83,142 +101,96 @@ extern "C" {
 #endif
 
 /*!
- * @name Cmp Initialization and deinitialization
+ * @name Initialization and deinitialization
  * @{
  */
 
 /*!
- * @brief CMP intialization.
- * Note: The cmp initial function not responsible for cmp power, application shall handle it.
+ * @brief CMP initialization.
  *
- * @param config init configurations.
+ * This function enables the CMP module and do necessary settings.
+ *
+ * @param config Pointer to the configuration structure.
  */
-void CMP_Init(cmp_config_t *config);
+void CMP_Init(const cmp_config_t *config);
 
 /*!
- * @brief CMP deintialization.
- * Note: The cmp deinit function not responsible for cmp power, application shall handle it.
+ * @brief CMP deinitialization.
  *
+ * This function gates the clock for CMP module.
  */
 void CMP_Deinit(void);
 
-/* @} */
-
-/*!
- * @name cmp functionality
- * @{
- */
-
 /*!
- * @brief select input source for pmux.
+ * @brief Initializes the CMP user configuration structure.
  *
- * @param pmux_select_source reference cmp_pmux_input_t above.
+ * This function initializes the user configuration structure to these default values.
+ * @code
+ *   config->enableHysteresis    = true;
+ *   config->enableLowPower      = true;
+ *   config->filterClockDivider  = kCMP_FilterClockDivide1;
+ *   config->filterSampleMode    = kCMP_FilterSampleMode0;
+ * @endcode
+ * @param config Pointer to the configuration structure.
  */
-static inline void CMP_PmuxSelect(cmp_pmux_input_t pmux_select_source)
-{
-    PMC->COMP &= ~PMC_COMP_PMUX_MASK;
-    PMC->COMP |= pmux_select_source;
-}
+void CMP_GetDefaultConfig(cmp_config_t *config);
 
-/*!
- * @brief select input source for nmux.
- *
- * @param nmux_select_source reference cmp_nmux_input_t above.
- */
-static inline void CMP_NmuxSelect(cmp_nmux_input_t nmux_select_source)
-{
-    PMC->COMP &= ~PMC_COMP_NMUX_MASK;
-    PMC->COMP |= nmux_select_source;
-}
+/* @} */
 
 /*!
- * @brief switch cmp work mode.
- *
- * @param enable true is enter low power mode, false is enter fast mode
+ * @name Compare Interface
+ * @{
  */
-static inline void CMP_EnableLowePowerMode(bool enable)
-{
-    if (enable)
-    {
-        PMC->COMP |= PMC_COMP_LOWPOWER_MASK;
-    }
-    else
-    {
-        PMC->COMP &= ~PMC_COMP_LOWPOWER_MASK;
-    }
-}
 
-/*!
- * @brief Control reference voltage step, per steps of (VREFINPUT/31).
+/*
+ * @brief Set the input channels for the comparator.
  *
- * @param step reference voltage step, per steps of (VREFINPUT/31).
+ * @param positiveChannel Positive side input channel number. See "_cmp_input_mux".
+ * @param negativeChannel Negative side input channel number. See "_cmp_input_mux".
  */
-static inline void CMP_SetRefStep(uint32_t step)
+static inline void CMP_SetInputChannels(uint8_t positiveChannel, uint8_t negativeChannel)
 {
-    PMC->COMP |= step << PMC_COMP_VREF_SHIFT;
+    PMC->COMP &= ~(PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK);
+    PMC->COMP |= (PMC_COMP_PMUX(positiveChannel) | PMC_COMP_NMUX(negativeChannel));
 }
 
 /*!
- * @brief cmp enable hysteresis.
+ * @brief Configures the VREFINPUT.
  *
+ * @param config Pointer to the configuration structure.
  */
-static inline void CMP_EnableHysteresis(bool enable)
-{
-    if (enable)
-    {
-        PMC->COMP |= PMC_COMP_HYST_MASK;
-    }
-    else
-    {
-        PMC->COMP &= ~PMC_COMP_HYST_MASK;
-    }
-}
+void CMP_SetVREF(const cmp_vref_config_t *config);
 
 /*!
- * @brief VREF select between internal VREF and VDDA (for the resistive ladder).
+ * @brief Get CMP compare output.
  *
- * @param select 1 is Select VDDA, 0 is Select internal VREF.
+ * @return The output result. true: voltage on positive side is greater than negative side.
+ *                            false: voltage on positive side is lower than negative side.
  */
-static inline void CMP_VREFSelect(uint32_t select)
+static inline bool CMP_GetOutput(void)
 {
-    if (select)
-    {
-        PMC->COMP |= PMC_COMP_VREFINPUT_MASK;
-    }
-    else
-    {
-        PMC->COMP &= ~PMC_COMP_VREFINPUT_MASK;
-    }
-}
-
-/*!
- * @brief comparator analog output.
- *
- * @return 1 indicates p is greater than n, 0 indicates n is greater than p.
- */
-static inline uint32_t CMP_GetOutput(void)
-{
-    return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK) ? 1 : 0;
+    return SYSCON_COMP_INT_STATUS_VAL_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK);
 }
 
 /* @} */
 
 /*!
- * @name cmp interrupt
+ * @name Interrupt Interface
  * @{
  */
 
 /*!
- * @brief cmp enable interrupt.
+ * @brief CMP enable interrupt.
  *
+ * @param type CMP interrupt type. See "_cmp_interrupt_type".
  */
-static inline void CMP_EnableInterrupt(void)
+static inline void CMP_EnableInterrupt(uint32_t type)
 {
-    SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK;
+    SYSCON->COMP_INT_CTRL |= (SYSCON_COMP_INT_CTRL_INT_CTRL(type) | SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK);
 }
 
 /*!
- * @brief cmp disable interrupt.
+ * @brief CMP disable interrupt.
  *
  */
 static inline void CMP_DisableInterrupt(void)
@@ -226,62 +198,88 @@ static inline void CMP_DisableInterrupt(void)
     SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK;
 }
 
+/*!
+ * @brief CMP clear interrupt.
+ *
+ */
+static inline void CMP_ClearInterrupt(void)
+{
+    SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK;
+}
+
 /*!
  * @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection.
  *
- * @param enable true is Select Analog Comparator raw output (unfiltered) as input for interrupt detection.
- *               false is Select Analog Comparator filtered output as input for interrupt detection.
+ * @param enable false: Select Analog Comparator raw output (unfiltered) as input for interrupt detection.
+ *               true: Select Analog Comparator filtered output as input for interrupt detection.
+ *
+ * @note: When CMP is configured as the wakeup source in power down mode, this function must use the raw output as the
+ *        interupt source, that is, call this function and set parameter enable to false.
  */
-static inline void CMP_InterruptSourceSelect(bool enable)
+static inline void CMP_EnableFilteredInterruptSource(bool enable)
 {
     if (enable)
     {
-        SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK;
+        SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK;
     }
     else
     {
-        SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK;
+        SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK;
     }
 }
+/* @} */
 
 /*!
- * @brief cmp get status.
- *
- * @return true is interrupt pending, false is no interrupt pending.
+ * @name Status Interface
+ * @{
  */
-static inline bool CMP_GetStatus(void)
-{
-    return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK) ? true : false;
-}
 
 /*!
- * @brief cmp clear interrupt status.
+ * @brief Get CMP interrupt status before interupt enable.
  *
+ * @return Interrupt status. true: interrupt pending,
+ *                           false: no interrupt pending.
  */
-static inline void CMP_ClearStatus(void)
+static inline bool CMP_GetPreviousInterruptStatus(void)
 {
-    SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK;
+    return SYSCON_COMP_INT_STATUS_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK);
 }
 
 /*!
- * @brief Comparator interrupt type select.
+ * @brief Get CMP interrupt status after interupt enable.
  *
- * @param type reference cmp_interrupt_type_t.
+ * @return Interrupt status. true: interrupt pending,
+ *                           false: no interrupt pending.
  */
-static inline void CMP_InterruptTypeSelect(cmp_interrupt_type_t cmp_interrupt_type)
+static inline bool CMP_GetInterruptStatus(void)
 {
-    SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_CTRL_MASK;
-    SYSCON->COMP_INT_CTRL |= cmp_interrupt_type;
+    return SYSCON_COMP_INT_STATUS_INT_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK);
 }
+/* @} */
+
+/*!
+ * @name Filter Interface
+ * @{
+ */
 
 /*!
- * @brief cmp get interrupt status.
+ * @brief CMP Filter Sample Config.
+ *
+ * This function allows the users to configure the sampling mode and clock divider of the CMP Filter.
  *
- * @return true is interrupt pending, false is no interrupt pending.
+ * @param filterSampleMode   CMP Select filter sample mode
+ * @param filterClockDivider CMP Set fileter clock divider
  */
-static inline bool CMP_GetInterruptStatus(void)
+static inline void CMP_FilterSampleConfig(cmp_filtercgf_samplemode_t filterSampleMode,
+                                          cmp_filtercgf_clkdiv_t filterClockDivider)
 {
-    return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) ? true : false;
+    uint32_t comp = PMC->COMP;
+
+    comp &= ~(PMC_COMP_FILTERCGF_CLKDIV_MASK | PMC_COMP_FILTERCGF_SAMPLEMODE_MASK);
+    comp |= (((uint32_t)filterClockDivider << PMC_COMP_FILTERCGF_CLKDIV_SHIFT) |
+             ((uint32_t)filterSampleMode << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT));
+
+    PMC->COMP = comp;
 }
 /* @} */
 

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.c

@@ -1,13 +1,13 @@
 /*
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2021 NXP
  * All rights reserved.
  *
- *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_common.h"
+
 #define SDK_MEM_MAGIC_NUMBER 12345U
 
 typedef struct _mem_align_control_block
@@ -21,127 +21,65 @@ typedef struct _mem_align_control_block
 #define FSL_COMPONENT_ID "platform.drivers.common"
 #endif
 
-#ifndef __GIC_PRIO_BITS
-#if defined(ENABLE_RAM_VECTOR_TABLE)
-uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+#if !((defined(__DSC__) && defined(__CW__)))
+void *SDK_Malloc(size_t size, size_t alignbytes)
 {
-/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
-    extern uint32_t Image$$VECTOR_ROM$$Base[];
-    extern uint32_t Image$$VECTOR_RAM$$Base[];
-    extern uint32_t Image$$RW_m_data$$Base[];
-
-#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
-#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
-#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
-#elif defined(__ICCARM__)
-    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
-    extern uint32_t __VECTOR_TABLE[];
-    extern uint32_t __VECTOR_RAM[];
-#elif defined(__GNUC__)
-    extern uint32_t __VECTOR_TABLE[];
-    extern uint32_t __VECTOR_RAM[];
-    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
-    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
-#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
-    uint32_t n;
-    uint32_t ret;
-    uint32_t irqMaskValue;
-
-    irqMaskValue = DisableGlobalIRQ();
-    if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+    mem_align_cb_t *p_cb = NULL;
+    uint32_t alignedsize;
+
+    /* Check overflow. */
+    alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes);
+    if (alignedsize < size)
     {
-        /* Copy the vector table from ROM to RAM */
-        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
-        {
-            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
-        }
-        /* Point the VTOR to the position of vector table */
-        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+        return NULL;
     }
 
-    ret = __VECTOR_RAM[irq + 16];
-    /* make sure the __VECTOR_RAM is noncachable */
-    __VECTOR_RAM[irq + 16] = irqHandler;
-
-    EnableGlobalIRQ(irqMaskValue);
-
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
-
-    return ret;
-}
-#endif /* ENABLE_RAM_VECTOR_TABLE. */
-#endif /* __GIC_PRIO_BITS. */
-
-#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
-#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
-
-void EnableDeepSleepIRQ(IRQn_Type interrupt)
-{
-    uint32_t intNumber = (uint32_t)interrupt;
-
-    uint32_t index = 0;
-
-    while (intNumber >= 32u)
+    if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t))
     {
-        index++;
-        intNumber -= 32u;
+        return NULL;
     }
 
-    SYSCON->STARTERSET[index] = 1u << intNumber;
-    EnableIRQ(interrupt); /* also enable interrupt at NVIC */
-}
-
-void DisableDeepSleepIRQ(IRQn_Type interrupt)
-{
-    uint32_t intNumber = (uint32_t)interrupt;
-
-    DisableIRQ(interrupt); /* also disable interrupt at NVIC */
-    uint32_t index = 0;
+    alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t);
 
-    while (intNumber >= 32u)
+    union
     {
-        index++;
-        intNumber -= 32u;
-    }
+        void *pointer_value;
+        uintptr_t unsigned_value;
+    } p_align_addr, p_addr;
 
-    SYSCON->STARTERCLR[index] = 1u << intNumber;
-}
-#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
-#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+    p_addr.pointer_value = malloc((size_t)alignedsize);
 
-void *SDK_Malloc(size_t size, size_t alignbytes)
-{
-    mem_align_cb_t *p_cb = NULL;
-    uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);
-    void *p_align_addr, *p_addr = malloc(alignedsize);
-
-    if (!p_addr)
+    if (p_addr.pointer_value == NULL)
     {
         return NULL;
     }
 
-    p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes);
+    p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);
 
-    p_cb             = (mem_align_cb_t *)((uint32_t)p_align_addr - 4U);
+    p_cb             = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
     p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
-    p_cb->offset     = (uint32_t)p_align_addr - (uint32_t)p_addr;
+    p_cb->offset     = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);
 
-    return (void *)p_align_addr;
+    return p_align_addr.pointer_value;
 }
 
 void SDK_Free(void *ptr)
 {
-    mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4U);
+    union
+    {
+        void *pointer_value;
+        uintptr_t unsigned_value;
+    } p_free;
+    p_free.pointer_value = ptr;
+    mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
 
     if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
     {
         return;
     }
 
-    free((void *)((uint32_t)ptr - p_cb->offset));
+    p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
+
+    free(p_free.pointer_value);
 }
+#endif

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2021 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -15,7 +15,7 @@
 #include <string.h>
 #include <stdlib.h>
 
-#if defined(__ICCARM__)
+#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__)
 #include <stddef.h>
 #endif
 
@@ -26,159 +26,202 @@
  * @{
  */
 
+/*******************************************************************************
+ * Configurations
+ ******************************************************************************/
+
+/*! @brief Macro to use the default weak IRQ handler in drivers. */
+#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
+#endif
+
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @brief Construct a status code value from a group and code number. */
-#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+#define MAKE_STATUS(group, code) ((((group)*100L) + (code)))
+
+/*! @brief Construct the version number for drivers.
+ *
+ * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M)
+ * and 16-bit platforms(such as DSC).
+ *
+ * @verbatim
+
+   | Unused    || Major Version || Minor Version ||  Bug Fix    |
+   31        25  24           17  16            9  8            0
 
-/*! @brief Construct the version number for drivers. */
-#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+   @endverbatim
+ */
+#define MAKE_VERSION(major, minor, bugfix) (((major) * 65536L) + ((minor) * 256L) + (bugfix))
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief common driver version 2.0.1. */
-#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief common driver version. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
 /*@}*/
 
 /* Debug console type definition. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_NONE          0U      /*!< No debug console.             */
-#define DEBUG_CONSOLE_DEVICE_TYPE_UART          1U      /*!< Debug console based on UART.   */
-#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART        2U      /*!< Debug console based on LPUART. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI         3U      /*!< Debug console based on LPSCI.  */
-#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC        4U      /*!< Debug console based on USBCDC. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM      5U      /*!< Debug console based on FLEXCOMM. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_IUART         6U      /*!< Debug console based on i.MX UART. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART        7U      /*!< Debug console based on LPC_VUSART. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART    8U      /*!< Debug console based on LPC_USART. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_SWO           9U      /*!< Debug console based on SWO. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE       0U  /*!< No debug console.             */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART       1U  /*!< Debug console based on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART     2U  /*!< Debug console based on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI      3U  /*!< Debug console based on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC     4U  /*!< Debug console based on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM   5U  /*!< Debug console based on FLEXCOMM. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART      6U  /*!< Debug console based on i.MX UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART     7U  /*!< Debug console based on LPC_VUSART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U  /*!< Debug console based on LPC_USART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_SWO        9U  /*!< Debug console based on SWO. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI       10U /*!< Debug console based on QSCI. */
 
 /*! @brief Status group numbers. */
 enum _status_groups
 {
-    kStatusGroup_Generic = 0,                 /*!< Group number for generic status codes. */
-    kStatusGroup_FLASH = 1,                   /*!< Group number for FLASH status codes. */
-    kStatusGroup_LPSPI = 4,                   /*!< Group number for LPSPI status codes. */
-    kStatusGroup_FLEXIO_SPI = 5,              /*!< Group number for FLEXIO SPI status codes. */
-    kStatusGroup_DSPI = 6,                    /*!< Group number for DSPI status codes. */
-    kStatusGroup_FLEXIO_UART = 7,             /*!< Group number for FLEXIO UART status codes. */
-    kStatusGroup_FLEXIO_I2C = 8,              /*!< Group number for FLEXIO I2C status codes. */
-    kStatusGroup_LPI2C = 9,                   /*!< Group number for LPI2C status codes. */
-    kStatusGroup_UART = 10,                   /*!< Group number for UART status codes. */
-    kStatusGroup_I2C = 11,                    /*!< Group number for UART status codes. */
-    kStatusGroup_LPSCI = 12,                  /*!< Group number for LPSCI status codes. */
-    kStatusGroup_LPUART = 13,                 /*!< Group number for LPUART status codes. */
-    kStatusGroup_SPI = 14,                    /*!< Group number for SPI status code.*/
-    kStatusGroup_XRDC = 15,                   /*!< Group number for XRDC status code.*/
-    kStatusGroup_SEMA42 = 16,                 /*!< Group number for SEMA42 status code.*/
-    kStatusGroup_SDHC = 17,                   /*!< Group number for SDHC status code */
-    kStatusGroup_SDMMC = 18,                  /*!< Group number for SDMMC status code */
-    kStatusGroup_SAI = 19,                    /*!< Group number for SAI status code */
-    kStatusGroup_MCG = 20,                    /*!< Group number for MCG status codes. */
-    kStatusGroup_SCG = 21,                    /*!< Group number for SCG status codes. */
-    kStatusGroup_SDSPI = 22,                  /*!< Group number for SDSPI status codes. */
-    kStatusGroup_FLEXIO_I2S = 23,             /*!< Group number for FLEXIO I2S status codes */
-    kStatusGroup_FLEXIO_MCULCD = 24,          /*!< Group number for FLEXIO LCD status codes */
-    kStatusGroup_FLASHIAP = 25,               /*!< Group number for FLASHIAP status codes */
-    kStatusGroup_FLEXCOMM_I2C = 26,           /*!< Group number for FLEXCOMM I2C status codes */
-    kStatusGroup_I2S = 27,                    /*!< Group number for I2S status codes */
-    kStatusGroup_IUART = 28,                  /*!< Group number for IUART status codes */
-    kStatusGroup_CSI = 29,                    /*!< Group number for CSI status codes */
-    kStatusGroup_MIPI_DSI = 30,               /*!< Group number for MIPI DSI status codes */
-    kStatusGroup_SDRAMC = 35,                 /*!< Group number for SDRAMC status codes. */
-    kStatusGroup_POWER = 39,                  /*!< Group number for POWER status codes. */
-    kStatusGroup_ENET = 40,                   /*!< Group number for ENET status codes. */
-    kStatusGroup_PHY = 41,                    /*!< Group number for PHY status codes. */
-    kStatusGroup_TRGMUX = 42,                 /*!< Group number for TRGMUX status codes. */
-    kStatusGroup_SMARTCARD = 43,              /*!< Group number for SMARTCARD status codes. */
-    kStatusGroup_LMEM = 44,                   /*!< Group number for LMEM status codes. */
-    kStatusGroup_QSPI = 45,                   /*!< Group number for QSPI status codes. */
-    kStatusGroup_DMA = 50,                    /*!< Group number for DMA status codes. */
-    kStatusGroup_EDMA = 51,                   /*!< Group number for EDMA status codes. */
-    kStatusGroup_DMAMGR = 52,                 /*!< Group number for DMAMGR status codes. */
-    kStatusGroup_FLEXCAN = 53,                /*!< Group number for FlexCAN status codes. */
-    kStatusGroup_LTC = 54,                    /*!< Group number for LTC status codes. */
-    kStatusGroup_FLEXIO_CAMERA = 55,          /*!< Group number for FLEXIO CAMERA status codes. */
-    kStatusGroup_LPC_SPI = 56,                /*!< Group number for LPC_SPI status codes. */
-    kStatusGroup_LPC_USART = 57,              /*!< Group number for LPC_USART status codes. */
-    kStatusGroup_DMIC = 58,                   /*!< Group number for DMIC status codes. */
-    kStatusGroup_SDIF = 59,                   /*!< Group number for SDIF status codes.*/
-    kStatusGroup_SPIFI = 60,                  /*!< Group number for SPIFI status codes. */
-    kStatusGroup_OTP = 61,                    /*!< Group number for OTP status codes. */
-    kStatusGroup_MCAN = 62,                   /*!< Group number for MCAN status codes. */
-    kStatusGroup_CAAM = 63,                   /*!< Group number for CAAM status codes. */
-    kStatusGroup_ECSPI = 64,                  /*!< Group number for ECSPI status codes. */
-    kStatusGroup_USDHC = 65,                  /*!< Group number for USDHC status codes.*/
-    kStatusGroup_LPC_I2C = 66,                /*!< Group number for LPC_I2C status codes.*/
-    kStatusGroup_DCP = 67,                    /*!< Group number for DCP status codes.*/
-    kStatusGroup_MSCAN = 68,                  /*!< Group number for MSCAN status codes.*/
-    kStatusGroup_ESAI = 69,                   /*!< Group number for ESAI status codes. */
-    kStatusGroup_FLEXSPI = 70,                /*!< Group number for FLEXSPI status codes. */
-    kStatusGroup_MMDC = 71,                   /*!< Group number for MMDC status codes. */
-    kStatusGroup_PDM = 72,                    /*!< Group number for MIC status codes. */
-    kStatusGroup_SDMA = 73,                   /*!< Group number for SDMA status codes. */
-    kStatusGroup_ICS = 74,                    /*!< Group number for ICS status codes. */
-    kStatusGroup_SPDIF = 75,                  /*!< Group number for SPDIF status codes. */
-    kStatusGroup_LPC_MINISPI = 76,            /*!< Group number for LPC_MINISPI status codes. */
-    kStatusGroup_HASHCRYPT = 77,              /*!< Group number for Hashcrypt status codes */
-    kStatusGroup_LPC_SPI_SSP = 78,            /*!< Group number for LPC_SPI_SSP status codes. */
-    kStatusGroup_I3C = 79,                    /*!< Group number for I3C status codes */
-    kStatusGroup_LPC_I2C_1 = 97,              /*!< Group number for LPC_I2C_1 status codes. */
-    kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */
-    kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */
-    kStatusGroup_SEMC = 100,                  /*!< Group number for SEMC status codes. */
+    kStatusGroup_Generic               = 0,   /*!< Group number for generic status codes. */
+    kStatusGroup_FLASH                 = 1,   /*!< Group number for FLASH status codes. */
+    kStatusGroup_LPSPI                 = 4,   /*!< Group number for LPSPI status codes. */
+    kStatusGroup_FLEXIO_SPI            = 5,   /*!< Group number for FLEXIO SPI status codes. */
+    kStatusGroup_DSPI                  = 6,   /*!< Group number for DSPI status codes. */
+    kStatusGroup_FLEXIO_UART           = 7,   /*!< Group number for FLEXIO UART status codes. */
+    kStatusGroup_FLEXIO_I2C            = 8,   /*!< Group number for FLEXIO I2C status codes. */
+    kStatusGroup_LPI2C                 = 9,   /*!< Group number for LPI2C status codes. */
+    kStatusGroup_UART                  = 10,  /*!< Group number for UART status codes. */
+    kStatusGroup_I2C                   = 11,  /*!< Group number for UART status codes. */
+    kStatusGroup_LPSCI                 = 12,  /*!< Group number for LPSCI status codes. */
+    kStatusGroup_LPUART                = 13,  /*!< Group number for LPUART status codes. */
+    kStatusGroup_SPI                   = 14,  /*!< Group number for SPI status code.*/
+    kStatusGroup_XRDC                  = 15,  /*!< Group number for XRDC status code.*/
+    kStatusGroup_SEMA42                = 16,  /*!< Group number for SEMA42 status code.*/
+    kStatusGroup_SDHC                  = 17,  /*!< Group number for SDHC status code */
+    kStatusGroup_SDMMC                 = 18,  /*!< Group number for SDMMC status code */
+    kStatusGroup_SAI                   = 19,  /*!< Group number for SAI status code */
+    kStatusGroup_MCG                   = 20,  /*!< Group number for MCG status codes. */
+    kStatusGroup_SCG                   = 21,  /*!< Group number for SCG status codes. */
+    kStatusGroup_SDSPI                 = 22,  /*!< Group number for SDSPI status codes. */
+    kStatusGroup_FLEXIO_I2S            = 23,  /*!< Group number for FLEXIO I2S status codes */
+    kStatusGroup_FLEXIO_MCULCD         = 24,  /*!< Group number for FLEXIO LCD status codes */
+    kStatusGroup_FLASHIAP              = 25,  /*!< Group number for FLASHIAP status codes */
+    kStatusGroup_FLEXCOMM_I2C          = 26,  /*!< Group number for FLEXCOMM I2C status codes */
+    kStatusGroup_I2S                   = 27,  /*!< Group number for I2S status codes */
+    kStatusGroup_IUART                 = 28,  /*!< Group number for IUART status codes */
+    kStatusGroup_CSI                   = 29,  /*!< Group number for CSI status codes */
+    kStatusGroup_MIPI_DSI              = 30,  /*!< Group number for MIPI DSI status codes */
+    kStatusGroup_SDRAMC                = 35,  /*!< Group number for SDRAMC status codes. */
+    kStatusGroup_POWER                 = 39,  /*!< Group number for POWER status codes. */
+    kStatusGroup_ENET                  = 40,  /*!< Group number for ENET status codes. */
+    kStatusGroup_PHY                   = 41,  /*!< Group number for PHY status codes. */
+    kStatusGroup_TRGMUX                = 42,  /*!< Group number for TRGMUX status codes. */
+    kStatusGroup_SMARTCARD             = 43,  /*!< Group number for SMARTCARD status codes. */
+    kStatusGroup_LMEM                  = 44,  /*!< Group number for LMEM status codes. */
+    kStatusGroup_QSPI                  = 45,  /*!< Group number for QSPI status codes. */
+    kStatusGroup_DMA                   = 50,  /*!< Group number for DMA status codes. */
+    kStatusGroup_EDMA                  = 51,  /*!< Group number for EDMA status codes. */
+    kStatusGroup_DMAMGR                = 52,  /*!< Group number for DMAMGR status codes. */
+    kStatusGroup_FLEXCAN               = 53,  /*!< Group number for FlexCAN status codes. */
+    kStatusGroup_LTC                   = 54,  /*!< Group number for LTC status codes. */
+    kStatusGroup_FLEXIO_CAMERA         = 55,  /*!< Group number for FLEXIO CAMERA status codes. */
+    kStatusGroup_LPC_SPI               = 56,  /*!< Group number for LPC_SPI status codes. */
+    kStatusGroup_LPC_USART             = 57,  /*!< Group number for LPC_USART status codes. */
+    kStatusGroup_DMIC                  = 58,  /*!< Group number for DMIC status codes. */
+    kStatusGroup_SDIF                  = 59,  /*!< Group number for SDIF status codes.*/
+    kStatusGroup_SPIFI                 = 60,  /*!< Group number for SPIFI status codes. */
+    kStatusGroup_OTP                   = 61,  /*!< Group number for OTP status codes. */
+    kStatusGroup_MCAN                  = 62,  /*!< Group number for MCAN status codes. */
+    kStatusGroup_CAAM                  = 63,  /*!< Group number for CAAM status codes. */
+    kStatusGroup_ECSPI                 = 64,  /*!< Group number for ECSPI status codes. */
+    kStatusGroup_USDHC                 = 65,  /*!< Group number for USDHC status codes.*/
+    kStatusGroup_LPC_I2C               = 66,  /*!< Group number for LPC_I2C status codes.*/
+    kStatusGroup_DCP                   = 67,  /*!< Group number for DCP status codes.*/
+    kStatusGroup_MSCAN                 = 68,  /*!< Group number for MSCAN status codes.*/
+    kStatusGroup_ESAI                  = 69,  /*!< Group number for ESAI status codes. */
+    kStatusGroup_FLEXSPI               = 70,  /*!< Group number for FLEXSPI status codes. */
+    kStatusGroup_MMDC                  = 71,  /*!< Group number for MMDC status codes. */
+    kStatusGroup_PDM                   = 72,  /*!< Group number for MIC status codes. */
+    kStatusGroup_SDMA                  = 73,  /*!< Group number for SDMA status codes. */
+    kStatusGroup_ICS                   = 74,  /*!< Group number for ICS status codes. */
+    kStatusGroup_SPDIF                 = 75,  /*!< Group number for SPDIF status codes. */
+    kStatusGroup_LPC_MINISPI           = 76,  /*!< Group number for LPC_MINISPI status codes. */
+    kStatusGroup_HASHCRYPT             = 77,  /*!< Group number for Hashcrypt status codes */
+    kStatusGroup_LPC_SPI_SSP           = 78,  /*!< Group number for LPC_SPI_SSP status codes. */
+    kStatusGroup_I3C                   = 79,  /*!< Group number for I3C status codes */
+    kStatusGroup_LPC_I2C_1             = 97,  /*!< Group number for LPC_I2C_1 status codes. */
+    kStatusGroup_NOTIFIER              = 98,  /*!< Group number for NOTIFIER status codes. */
+    kStatusGroup_DebugConsole          = 99,  /*!< Group number for debug console status codes. */
+    kStatusGroup_SEMC                  = 100, /*!< Group number for SEMC status codes. */
     kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
-    kStatusGroup_IAP = 102,                   /*!< Group number for IAP status codes */
-
-    kStatusGroup_HAL_GPIO = 121,              /*!< Group number for HAL GPIO status codes. */
-    kStatusGroup_HAL_UART = 122,              /*!< Group number for HAL UART status codes. */
-    kStatusGroup_HAL_TIMER = 123,             /*!< Group number for HAL TIMER status codes. */
-    kStatusGroup_HAL_SPI = 124,               /*!< Group number for HAL SPI status codes. */
-    kStatusGroup_HAL_I2C = 125,               /*!< Group number for HAL I2C status codes. */
-    kStatusGroup_HAL_FLASH = 126,             /*!< Group number for HAL FLASH status codes. */
-    kStatusGroup_HAL_PWM = 127,               /*!< Group number for HAL PWM status codes. */
-    kStatusGroup_HAL_RNG = 128,               /*!< Group number for HAL RNG status codes. */
-    kStatusGroup_TIMERMANAGER = 135,          /*!< Group number for TiMER MANAGER status codes. */
-    kStatusGroup_SERIALMANAGER = 136,         /*!< Group number for SERIAL MANAGER status codes. */
-    kStatusGroup_LED = 137,                   /*!< Group number for LED status codes. */
-    kStatusGroup_BUTTON = 138,                /*!< Group number for BUTTON status codes. */
-    kStatusGroup_EXTERN_EEPROM = 139,         /*!< Group number for EXTERN EEPROM status codes. */
-    kStatusGroup_SHELL = 140,                 /*!< Group number for SHELL status codes. */
-    kStatusGroup_MEM_MANAGER = 141,           /*!< Group number for MEM MANAGER status codes. */
-    kStatusGroup_LIST = 142,                  /*!< Group number for List status codes. */
-    kStatusGroup_OSA = 143,                   /*!< Group number for OSA status codes. */
-    kStatusGroup_COMMON_TASK = 144,           /*!< Group number for Common task status codes. */
-    kStatusGroup_MSG = 145,                   /*!< Group number for messaging status codes. */
-    kStatusGroup_SDK_OCOTP = 146,             /*!< Group number for OCOTP status codes. */
-    kStatusGroup_SDK_FLEXSPINOR = 147,        /*!< Group number for FLEXSPINOR status codes.*/
-    kStatusGroup_CODEC = 148,                 /*!< Group number for codec status codes. */
+    kStatusGroup_IAP                   = 102, /*!< Group number for IAP status codes */
+    kStatusGroup_SFA                   = 103, /*!< Group number for SFA status codes*/
+    kStatusGroup_SPC                   = 104, /*!< Group number for SPC status codes. */
+    kStatusGroup_PUF                   = 105, /*!< Group number for PUF status codes. */
+    kStatusGroup_TOUCH_PANEL           = 106, /*!< Group number for touch panel status codes */
+
+    kStatusGroup_HAL_GPIO       = 121, /*!< Group number for HAL GPIO status codes. */
+    kStatusGroup_HAL_UART       = 122, /*!< Group number for HAL UART status codes. */
+    kStatusGroup_HAL_TIMER      = 123, /*!< Group number for HAL TIMER status codes. */
+    kStatusGroup_HAL_SPI        = 124, /*!< Group number for HAL SPI status codes. */
+    kStatusGroup_HAL_I2C        = 125, /*!< Group number for HAL I2C status codes. */
+    kStatusGroup_HAL_FLASH      = 126, /*!< Group number for HAL FLASH status codes. */
+    kStatusGroup_HAL_PWM        = 127, /*!< Group number for HAL PWM status codes. */
+    kStatusGroup_HAL_RNG        = 128, /*!< Group number for HAL RNG status codes. */
+    kStatusGroup_HAL_I2S        = 129, /*!< Group number for HAL I2S status codes. */
+    kStatusGroup_TIMERMANAGER   = 135, /*!< Group number for TiMER MANAGER status codes. */
+    kStatusGroup_SERIALMANAGER  = 136, /*!< Group number for SERIAL MANAGER status codes. */
+    kStatusGroup_LED            = 137, /*!< Group number for LED status codes. */
+    kStatusGroup_BUTTON         = 138, /*!< Group number for BUTTON status codes. */
+    kStatusGroup_EXTERN_EEPROM  = 139, /*!< Group number for EXTERN EEPROM status codes. */
+    kStatusGroup_SHELL          = 140, /*!< Group number for SHELL status codes. */
+    kStatusGroup_MEM_MANAGER    = 141, /*!< Group number for MEM MANAGER status codes. */
+    kStatusGroup_LIST           = 142, /*!< Group number for List status codes. */
+    kStatusGroup_OSA            = 143, /*!< Group number for OSA status codes. */
+    kStatusGroup_COMMON_TASK    = 144, /*!< Group number for Common task status codes. */
+    kStatusGroup_MSG            = 145, /*!< Group number for messaging status codes. */
+    kStatusGroup_SDK_OCOTP      = 146, /*!< Group number for OCOTP status codes. */
+    kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/
+    kStatusGroup_CODEC          = 148, /*!< Group number for codec status codes. */
+    kStatusGroup_ASRC           = 149, /*!< Group number for codec status ASRC. */
+    kStatusGroup_OTFAD          = 150, /*!< Group number for codec status codes. */
+    kStatusGroup_SDIOSLV        = 151, /*!< Group number for SDIOSLV status codes. */
+    kStatusGroup_MECC           = 152, /*!< Group number for MECC status codes. */
+    kStatusGroup_ENET_QOS       = 153, /*!< Group number for ENET_QOS status codes. */
+    kStatusGroup_LOG            = 154, /*!< Group number for LOG status codes. */
+    kStatusGroup_I3CBUS         = 155, /*!< Group number for I3CBUS status codes. */
+    kStatusGroup_QSCI           = 156, /*!< Group number for QSCI status codes. */
+    kStatusGroup_SNT            = 157, /*!< Group number for SNT status codes. */
+    kStatusGroup_QUEUEDSPI      = 158, /*!< Group number for QSPI status codes. */
+    kStatusGroup_POWER_MANAGER  = 159, /*!< Group number for POWER_MANAGER status codes. */
+    kStatusGroup_IPED = 160,                  /*!< Group number for IPED status codes. */
+    kStatusGroup_CSS_PKC = 161,               /*!< Group number for CSS PKC status codes. */
+    kStatusGroup_HOSTIF      = 162, /*!< Group number for HOSTIF status codes. */
+    kStatusGroup_CLIF           = 163, /*!< Group number for CLIF status codes. */
+    kStatusGroup_BMA            = 164, /*!< Group number for BMA status codes. */
 };
 
-/*! @brief Generic status return codes. */
-enum _generic_status
+/*! \public
+ * @brief Generic status return codes.
+ */
+enum
 {
-    kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
-    kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
-    kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
-    kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
-    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
-    kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
-    kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
+    kStatus_Success         = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */
+    kStatus_Fail            = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */
+    kStatus_ReadOnly        = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */
+    kStatus_OutOfRange      = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */
+    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */
+    kStatus_Timeout         = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */
+    kStatus_NoTransferInProgress =
+        MAKE_STATUS(kStatusGroup_Generic, 6),            /*!< Generic status for no transfer in progress. */
+    kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */
+    kStatus_NoData =
+        MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */
 };
 
 /*! @brief Type used for all status and error return values. */
 typedef int32_t status_t;
 
-/*
- * Macro guard for whether to use default weak IRQ implementation in drivers
+/*!
+ * @name Min/max macros
+ * @{
  */
-#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
-#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
-#endif
-
-/*! @name Min/max macros */
-/* @{ */
 #if !defined(MIN)
 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
 #endif
@@ -204,389 +247,57 @@ typedef int32_t status_t;
 #endif
 /* @} */
 
-/*! @name Timer utilities */
-/* @{ */
-/*! Macro to convert a microsecond period to raw count value */
-#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
-/*! Macro to convert a raw count value to microsecond */
-#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
-
-/*! Macro to convert a millisecond period to raw count value */
-#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
-/*! Macro to convert a raw count value to millisecond */
-#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
-/* @} */
-
-/*! @name Alignment variable definition macros */
-/* @{ */
-#if (defined(__ICCARM__))
-/**
- * Workaround to disable MISRA C message suppress warnings for IAR compiler.
- * http://supp.iar.com/Support/?note=24725
- */
-_Pragma("diag_suppress=Pm120")
-#define SDK_PRAGMA(x) _Pragma(#x)
-    _Pragma("diag_error=Pm120")
-/*! Macro to define a variable with alignbytes alignment */
-#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
-/*! Macro to define a variable with L1 d-cache line size alignment */
-#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
-#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
-#endif
-/*! Macro to define a variable with L2 cache line size alignment */
-#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
-#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
-#endif
-#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
-/*! Macro to define a variable with alignbytes alignment */
-#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
-/*! Macro to define a variable with L1 d-cache line size alignment */
-#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
-#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
-#endif
-/*! Macro to define a variable with L2 cache line size alignment */
-#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
-#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
-#endif
-#elif defined(__GNUC__)
-/*! Macro to define a variable with alignbytes alignment */
-#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
-/*! Macro to define a variable with L1 d-cache line size alignment */
-#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
-#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
-#endif
-/*! Macro to define a variable with L2 cache line size alignment */
-#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
-#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
-#endif
-#else
-#error Toolchain not supported
-#define SDK_ALIGN(var, alignbytes) var
-#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
-#define SDK_L1DCACHE_ALIGN(var) var
-#endif
-#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
-#define SDK_L2CACHE_ALIGN(var) var
-#endif
-#endif
-
-/*! Macro to change a value to a given size aligned value */
-#define SDK_SIZEALIGN(var, alignbytes) \
-    ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
-/* @} */
-
-/*! @name Non-cacheable region definition macros */
-/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
- * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
- * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
- * will be initialized to zero in system startup.
+/*! @name Suppress fallthrough warning macro */
+/* For switch case code block, if case section ends without "break;" statement, there wil be
+ fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
+ To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
+ case section which misses "break;"statement.
  */
 /* @{ */
-#if (defined(__ICCARM__))
-#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
-#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
-#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough))
 #else
-#define AT_NONCACHEABLE_SECTION(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
-#define AT_NONCACHEABLE_SECTION_INIT(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
-#endif
-#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
-#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
-#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
-    __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
-#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
-    __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
-#else
-#define AT_NONCACHEABLE_SECTION(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
-#define AT_NONCACHEABLE_SECTION_INIT(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
-#endif
-#elif(defined(__GNUC__))
-/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
- * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
- */
-#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
-#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
-    __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
-#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
-    __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
-#else
-#define AT_NONCACHEABLE_SECTION(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
-#define AT_NONCACHEABLE_SECTION_INIT(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
-#endif
-#else
-#error Toolchain not supported.
-#define AT_NONCACHEABLE_SECTION(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
-#define AT_NONCACHEABLE_SECTION_INIT(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
+#define SUPPRESS_FALL_THROUGH_WARNING()
 #endif
 /* @} */
 
-/*! @name Time sensitive region */
-/* @{ */
-#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
-#if (defined(__ICCARM__))
-#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
-#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
-#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
-#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
-#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
-#elif(defined(__GNUC__))
-#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
-#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
-#else
-#error Toolchain not supported.
-#endif /* defined(__ICCARM__) */
-#else
-#if (defined(__ICCARM__))
-#define AT_QUICKACCESS_SECTION_CODE(func) func
-#define AT_QUICKACCESS_SECTION_DATA(func) func
-#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
-#define AT_QUICKACCESS_SECTION_CODE(func) func
-#define AT_QUICKACCESS_SECTION_DATA(func) func
-#elif(defined(__GNUC__))
-#define AT_QUICKACCESS_SECTION_CODE(func) func
-#define AT_QUICKACCESS_SECTION_DATA(func) func
-#else
-#error Toolchain not supported.
-#endif
-#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
-/* @} */
-
-/*! @name Ram Function */
-#if (defined(__ICCARM__))
-#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
-#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
-#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
-#elif(defined(__GNUC__))
-#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
-#else
-#error Toolchain not supported.
-#endif /* defined(__ICCARM__) */
-/* @} */
-
-/*
- * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
- * defined in previous of this file.
- */
-#include "fsl_clock.h"
-
-/*
- * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
- */
-#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
-     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
-#include "fsl_reset.h"
-#endif
-
 /*******************************************************************************
  * API
  ******************************************************************************/
 
 #if defined(__cplusplus)
-        extern "C"
-{
+extern "C" {
 #endif
 
-    /*!
-     * @brief Enable specific interrupt.
-     *
-     * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
-     * levels. For example, there are NVIC and intmux. Here the interrupts connected
-     * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
-     * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
-     * to NVIC first then routed to core.
-     *
-     * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
-     * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
-     *
-     * @param interrupt The IRQ number.
-     * @retval kStatus_Success Interrupt enabled successfully
-     * @retval kStatus_Fail Failed to enable the interrupt
-     */
-    static inline status_t EnableIRQ(IRQn_Type interrupt)
-    {
-        if (NotAvail_IRQn == interrupt)
-        {
-            return kStatus_Fail;
-        }
-
-#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
-        if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
-        {
-            return kStatus_Fail;
-        }
-#endif
-
-#if defined(__GIC_PRIO_BITS)
-        GIC_EnableIRQ(interrupt);
-#else
-        NVIC_EnableIRQ(interrupt);
-#endif
-        return kStatus_Success;
-    }
-
-    /*!
-     * @brief Disable specific interrupt.
-     *
-     * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
-     * levels. For example, there are NVIC and intmux. Here the interrupts connected
-     * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
-     * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
-     * to NVIC first then routed to core.
-     *
-     * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
-     * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
-     *
-     * @param interrupt The IRQ number.
-     * @retval kStatus_Success Interrupt disabled successfully
-     * @retval kStatus_Fail Failed to disable the interrupt
-     */
-    static inline status_t DisableIRQ(IRQn_Type interrupt)
-    {
-        if (NotAvail_IRQn == interrupt)
-        {
-            return kStatus_Fail;
-        }
-
-#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
-        if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
-        {
-            return kStatus_Fail;
-        }
-#endif
+#if !((defined(__DSC__) && defined(__CW__)))
+/*!
+ * @brief Allocate memory with given alignment and aligned size.
+ *
+ * This is provided to support the dynamically allocated memory
+ * used in cache-able region.
+ * @param size The length required to malloc.
+ * @param alignbytes The alignment size.
+ * @retval The allocated memory.
+ */
+void *SDK_Malloc(size_t size, size_t alignbytes);
 
-#if defined(__GIC_PRIO_BITS)
-        GIC_DisableIRQ(interrupt);
-#else
-    NVIC_DisableIRQ(interrupt);
+/*!
+ * @brief Free memory.
+ *
+ * @param ptr The memory to be release.
+ */
+void SDK_Free(void *ptr);
 #endif
-        return kStatus_Success;
-    }
-
-    /*!
-     * @brief Disable the global IRQ
-     *
-     * Disable the global interrupt and return the current primask register. User is required to provided the primask
-     * register for the EnableGlobalIRQ().
-     *
-     * @return Current primask value.
-     */
-    static inline uint32_t DisableGlobalIRQ(void)
-    {
-#if defined (__XCC__)
-        return 0;
-#else
-#if defined(CPSR_I_Msk)
-        uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
-
-        __disable_irq();
-
-        return cpsr;
-#else
-    uint32_t regPrimask = __get_PRIMASK();
-
-    __disable_irq();
 
-    return regPrimask;
-#endif
-#endif
-    }
-
-    /*!
-     * @brief Enable the global IRQ
-     *
-     * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
-     * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
-     * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
-     *
-     * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
-     * DisableGlobalIRQ().
-     */
-    static inline void EnableGlobalIRQ(uint32_t primask)
-    {
-#if defined (__XCC__)
-#else
-#if defined(CPSR_I_Msk)
-        __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
-#else
-    __set_PRIMASK(primask);
-#endif
-#endif
-    }
-
-#if defined(ENABLE_RAM_VECTOR_TABLE)
-    /*!
-     * @brief install IRQ handler
-     *
-     * @param irq IRQ number
-     * @param irqHandler IRQ handler address
-     * @return The old IRQ handler address
-     */
-    uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
-#endif /* ENABLE_RAM_VECTOR_TABLE. */
-
-#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
-    /*!
-     * @brief Enable specific interrupt for wake-up from deep-sleep mode.
-     *
-     * Enable the interrupt for wake-up from deep sleep mode.
-     * Some interrupts are typically used in sleep mode only and will not occur during
-     * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
-     * those clocks (significantly increasing power consumption in the reduced power mode),
-     * making these wake-ups possible.
-     *
-     * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
-     *
-     * @param interrupt The IRQ number.
-     */
-    void EnableDeepSleepIRQ(IRQn_Type interrupt);
-
-    /*!
-     * @brief Disable specific interrupt for wake-up from deep-sleep mode.
-     *
-     * Disable the interrupt for wake-up from deep sleep mode.
-     * Some interrupts are typically used in sleep mode only and will not occur during
-     * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
-     * those clocks (significantly increasing power consumption in the reduced power mode),
-     * making these wake-ups possible.
-     *
-     * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
-     *
-     * @param interrupt The IRQ number.
-     */
-    void DisableDeepSleepIRQ(IRQn_Type interrupt);
-#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
-
-    /*!
-     * @brief Allocate memory with given alignment and aligned size.
-     *
-     * This is provided to support the dynamically allocated memory
-     * used in cache-able region.
-     * @param size The length required to malloc.
-     * @param alignbytes The alignment size.
-     * @retval The allocated memory.
-     */
-    void *SDK_Malloc(size_t size, size_t alignbytes);
-
-    /*!
-     * @brief Free memory.
-     *
-     * @param ptr The memory to be release.
-     */
-    void SDK_Free(void *ptr);
+/*!
+ * @brief Delay at least for some time.
+ *  Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
+ *  if precise delay count was needed, please implement a new delay function with hardware timer.
+ *
+ * @param delayTime_us  Delay time in unit of microsecond.
+ * @param coreClock_Hz  Core clock frequency with Hz.
+ */
+void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
 
 #if defined(__cplusplus)
 }
@@ -594,4 +305,12 @@ _Pragma("diag_suppress=Pm120")
 
 /*! @} */
 
+#if (defined(__DSC__) && defined(__CW__))
+#include "fsl_common_dsc.h"
+#elif defined(__XCC__)
+#include "fsl_common_dsp.h"
+#else
+#include "fsl_common_arm.h"
+#endif
+
 #endif /* _FSL_COMMON_H_ */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common_arm.c

@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common_arm"
+#endif
+
+#ifndef __GIC_PRIO_BITS
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+#ifdef __VECTOR_TABLE
+#undef __VECTOR_TABLE
+#endif
+
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+#define __VECTOR_TABLE          Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM            Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
+    uint32_t n;
+    uint32_t ret;
+    uint32_t irqMaskValue;
+
+    irqMaskValue = DisableGlobalIRQ();
+    if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+    {
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+
+    ret = __VECTOR_RAM[(int32_t)irq + 16];
+    /* make sure the __VECTOR_RAM is noncachable */
+    __VECTOR_RAM[(int32_t)irq + 16] = irqHandler;
+
+    EnableGlobalIRQ(irqMaskValue);
+
+    return ret;
+}
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+#endif /* __GIC_PRIO_BITS. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+/*
+ * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
+ * powerlib should be used instead of these functions.
+ */
+#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
+
+/*
+ * When the SYSCON STARTER registers are discontinuous, these functions are
+ * implemented in fsl_power.c.
+ */
+#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
+
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t intNumber = (uint32_t)interrupt;
+
+    uint32_t index = 0;
+
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERSET[index] = 1UL << intNumber;
+    (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t intNumber = (uint32_t)interrupt;
+
+    (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+    uint32_t index = 0;
+
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERCLR[index] = 1UL << intNumber;
+}
+#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
+#endif /* FSL_FEATURE_POWERLIB_EXTEND */
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#if defined(SDK_DELAY_USE_DWT) && defined(DWT)
+/* Use WDT. */
+static void enableCpuCycleCounter(void)
+{
+    /* Make sure the DWT trace fucntion is enabled. */
+    if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
+    {
+        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+    }
+
+    /* CYCCNT not supported on this device. */
+    assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk));
+
+    /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */
+    if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL))
+    {
+        DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
+    }
+}
+
+static uint32_t getCpuCycleCount(void)
+{
+    return DWT->CYCCNT;
+}
+#else                 /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+/* Use software loop. */
+#if defined(__CC_ARM) /* This macro is arm v5 specific */
+/* clang-format off */
+__ASM static void DelayLoop(uint32_t count)
+{
+loop
+    SUBS R0, R0, #1
+    CMP  R0, #0
+    BNE  loop
+    BX   LR
+}
+/* clang-format on */
+#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)
+/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,
+ * use SUB and CMP here for compatibility */
+static void DelayLoop(uint32_t count)
+{
+    __ASM volatile("    MOV    R0, %0" : : "r"(count));
+    __ASM volatile(
+        "loop:                          \n"
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+        "    SUB    R0, R0, #1          \n"
+#else
+        "    SUBS   R0, R0, #1          \n"
+#endif
+        "    CMP    R0, #0              \n"
+
+        "    BNE    loop                \n"
+        :
+        :
+        : "r0");
+}
+#endif /* defined(__CC_ARM) */
+#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+
+/*!
+ * @brief Delay at least for some time.
+ *  Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have
+ *  effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and
+ *  coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports
+ *  up to 4294967 in current code. If long time delay is needed, please implement a new delay function.
+ *
+ * @param delayTime_us  Delay time in unit of microsecond.
+ * @param coreClock_Hz  Core clock frequency with Hz.
+ */
+void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
+{
+    uint64_t count;
+
+    if (delayTime_us > 0U)
+    {
+        count = USEC_TO_COUNT(delayTime_us, coreClock_Hz);
+
+        assert(count <= UINT32_MAX);
+
+#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */
+
+        enableCpuCycleCounter();
+        /* Calculate the count ticks. */
+        count += getCpuCycleCount();
+
+        if (count > UINT32_MAX)
+        {
+            count -= UINT32_MAX;
+            /* Wait for cyccnt overflow. */
+            while (count < getCpuCycleCount())
+            {
+            }
+        }
+
+        /* Wait for cyccnt reach count value. */
+        while (count > getCpuCycleCount())
+        {
+        }
+#else
+        /* Divide value may be different in various environment to ensure delay is precise.
+         * Every loop count includes three instructions, due to Cortex-M7 sometimes executes
+         * two instructions in one period, through test here set divide 1.5. Other M cores use
+         * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does
+         * not matter because other instructions outside while loop is enough to fill the time.
+         */
+#if (__CORTEX_M == 7)
+        count = count / 3U * 2U;
+#else
+        count = count / 4U;
+#endif
+        DelayLoop((uint32_t)count);
+#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+    }
+}

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common_arm.h

@@ -0,0 +1,671 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_COMMON_ARM_H_
+#define _FSL_COMMON_ARM_H_
+
+/*
+ * For CMSIS pack RTE.
+ * CMSIS pack RTE generates "RTC_Components.h" which contains the statements
+ * of the related <RTE_Components_h> element for all selected software components.
+ */
+#ifdef _RTE_
+#include "RTE_Components.h"
+#endif
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*! @name Atomic modification
+ *
+ * These macros are used for atomic access, such as read-modify-write
+ * to the peripheral registers.
+ *
+ * - SDK_ATOMIC_LOCAL_ADD
+ * - SDK_ATOMIC_LOCAL_SET
+ * - SDK_ATOMIC_LOCAL_CLEAR
+ * - SDK_ATOMIC_LOCAL_TOGGLE
+ * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET
+ *
+ * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr
+ * means the address of the peripheral register or variable you want to modify
+ * atomically, the parameter @c clearBits is the bits to clear, the parameter
+ * @c setBits it the bits to set.
+ * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this:
+ *
+ * @code
+   volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR;
+
+   SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02);
+   @endcode
+ *
+ * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result,
+ * register bit1:bit0 = 0b10.
+ *
+ * @note For the platforms don't support exclusive load and store, these macros
+ * disable the global interrupt to pretect the modification.
+ *
+ * @note These macros only guarantee the local processor atomic operations. For
+ * the multi-processor devices, use hardware semaphore such as SEMA42 to
+ * guarantee exclusive access if necessary.
+ *
+ * @{
+ */
+
+/* clang-format off */
+#if ((defined(__ARM_ARCH_7M__     ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined(__ARM_ARCH_7EM__    ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1)))
+/* clang-format on */
+
+/* If the LDREX and STREX are supported, use them. */
+#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \
+    do                                              \
+    {                                               \
+        (val) = __LDREXB(addr);                     \
+        (ops);                                      \
+    } while (0UL != __STREXB((val), (addr)))
+
+#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \
+    do                                              \
+    {                                               \
+        (val) = __LDREXH(addr);                     \
+        (ops);                                      \
+    } while (0UL != __STREXH((val), (addr)))
+
+#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \
+    do                                              \
+    {                                               \
+        (val) = __LDREXW(addr);                     \
+        (ops);                                      \
+    } while (0UL != __STREXW((val), (addr)))
+
+static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val);
+}
+
+static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val);
+}
+
+static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val);
+}
+
+static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val);
+}
+
+static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val);
+}
+
+static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val);
+}
+
+static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits);
+}
+
+static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits);
+}
+
+static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits);
+}
+
+static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits);
+}
+
+static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits);
+}
+
+static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits);
+}
+
+static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits);
+}
+
+static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits);
+}
+
+static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits);
+}
+
+static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits)
+{
+    uint8_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
+}
+
+static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits)
+{
+    uint16_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
+}
+
+static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits)
+{
+    uint32_t s_val;
+
+    _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
+}
+
+#define SDK_ATOMIC_LOCAL_ADD(addr, val)                                                                                        \
+    ((1UL == sizeof(*(addr))) ?                                                                                                \
+         _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) :                               \
+         ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \
+                                     _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val))))
+
+#define SDK_ATOMIC_LOCAL_SET(addr, bits)                                                                                        \
+    ((1UL == sizeof(*(addr))) ?                                                                                                 \
+         _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) :                               \
+         ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
+                                     _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
+
+#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits)                                                                 \
+    ((1UL == sizeof(*(addr))) ?                                                                            \
+         _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) :        \
+         ((2UL == sizeof(*(addr))) ?                                                                       \
+              _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
+              _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
+
+#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)                                                                 \
+    ((1UL == sizeof(*(addr))) ?                                                                             \
+         _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) :        \
+         ((2UL == sizeof(*(addr))) ?                                                                        \
+              _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \
+              _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits))))
+
+#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits)                                                                           \
+    ((1UL == sizeof(*(addr))) ?                                                                                                            \
+         _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) :         \
+         ((2UL == sizeof(*(addr))) ?                                                                                                       \
+              _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \
+              _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits))))
+#else
+
+#define SDK_ATOMIC_LOCAL_ADD(addr, val)      \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) += (val);                    \
+        EnableGlobalIRQ(s_atomicOldInt);     \
+    } while (0)
+
+#define SDK_ATOMIC_LOCAL_SET(addr, bits)     \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) |= (bits);                   \
+        EnableGlobalIRQ(s_atomicOldInt);     \
+    } while (0)
+
+#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits)   \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) &= ~(bits);                  \
+        EnableGlobalIRQ(s_atomicOldInt);     \
+    } while (0)
+
+#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)  \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) ^= (bits);                   \
+        EnableGlobalIRQ(s_atomicOldInt);     \
+    } while (0)
+
+#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
+    do                                                           \
+    {                                                            \
+        uint32_t s_atomicOldInt;                                 \
+        s_atomicOldInt = DisableGlobalIRQ();                     \
+        *(addr)        = (*(addr) & ~(clearBits)) | (setBits);   \
+        EnableGlobalIRQ(s_atomicOldInt);                         \
+    } while (0)
+
+#endif
+/* @} */
+
+/*! @name Timer utilities */
+/* @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz))
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz))
+/* @} */
+
+/*! @name ISR exit barrier
+ * @{
+ *
+ * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ * exception return operation might vector to incorrect interrupt.
+ * For Cortex-M7, if core speed much faster than peripheral register write speed,
+ * the peripheral interrupt flags may be still set after exiting ISR, this results to
+ * the same error similar with errata 83869.
+ */
+#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U))
+#define SDK_ISR_EXIT_BARRIER __DSB()
+#else
+#define SDK_ISR_EXIT_BARRIER
+#endif
+
+/* @} */
+
+/*! @name Alignment variable definition macros */
+/* @{ */
+#if (defined(__ICCARM__))
+/*
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.
+ * http:/ /supp.iar.com/Support/?note=24725
+ */
+_Pragma("diag_suppress=Pm120")
+#define SDK_PRAGMA(x) _Pragma(#x)
+    _Pragma("diag_error=Pm120")
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
+#elif defined(__GNUC__)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#else
+#error Toolchain not supported
+#endif
+
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#endif
+
+/*! Macro to change a value to a given size aligned value */
+#define SDK_SIZEALIGN(var, alignbytes) \
+    ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
+/* @} */
+
+/*! @name Non-cacheable region definition macros */
+/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
+ * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable
+ * variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them,
+ * these zero-inited variables will be initialized to zero in system startup.
+ */
+/* @{ */
+
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \
+     defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
+
+#if (defined(__ICCARM__))
+#define AT_NONCACHEABLE_SECTION(var)                   var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_INIT(var)              var @"NonCacheable.init"
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+    SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
+
+#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+    __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
+#if (defined(__CC_ARM))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
+#else
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var
+#endif
+
+#elif (defined(__GNUC__))
+/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
+ */
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+    __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
+#else
+#error Toolchain not supported.
+#endif
+
+#else
+
+#define AT_NONCACHEABLE_SECTION(var)                        var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes)      SDK_ALIGN(var, alignbytes)
+#define AT_NONCACHEABLE_SECTION_INIT(var)                   var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes)
+
+#endif
+
+/* @} */
+
+/*!
+ * @name Time sensitive region
+ * @{
+ */
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
+#define AT_QUICKACCESS_SECTION_DATA(var)  var @"DataQuickAccess"
+#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
+    SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess"
+#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
+#define AT_QUICKACCESS_SECTION_DATA(var)  __attribute__((section("DataQuickAccess"))) var
+#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
+    __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var
+#elif (defined(__GNUC__))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
+#define AT_QUICKACCESS_SECTION_DATA(var)  __attribute__((section("DataQuickAccess"))) var
+#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
+    __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes)))
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+
+/*! @name Ram Function */
+#if (defined(__ICCARM__))
+#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
+#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#elif (defined(__GNUC__))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+/* @} */
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+        void DefaultISR(void);
+#endif
+
+/*
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
+ * defined in previous of this file.
+ */
+#include "fsl_clock.h"
+
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Enable specific interrupt.
+ *
+ * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt enabled successfully
+ * @retval kStatus_Fail Failed to enable the interrupt
+ */
+static inline status_t EnableIRQ(IRQn_Type interrupt)
+{
+    status_t status = kStatus_Success;
+
+    if (NotAvail_IRQn == interrupt)
+    {
+        status = kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        status = kStatus_Fail;
+    }
+#endif
+
+    else
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_EnableIRQ(interrupt);
+#else
+        NVIC_EnableIRQ(interrupt);
+#endif
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Disable specific interrupt.
+ *
+ * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt disabled successfully
+ * @retval kStatus_Fail Failed to disable the interrupt
+ */
+static inline status_t DisableIRQ(IRQn_Type interrupt)
+{
+    status_t status = kStatus_Success;
+
+    if (NotAvail_IRQn == interrupt)
+    {
+        status = kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        status = kStatus_Fail;
+    }
+#endif
+
+    else
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_DisableIRQ(interrupt);
+#else
+        NVIC_DisableIRQ(interrupt);
+#endif
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Disable the global IRQ
+ *
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask
+ * register for the EnableGlobalIRQ().
+ *
+ * @return Current primask value.
+ */
+static inline uint32_t DisableGlobalIRQ(void)
+{
+#if defined(CPSR_I_Msk)
+    uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
+
+    __disable_irq();
+
+    return cpsr;
+#else
+    uint32_t regPrimask = __get_PRIMASK();
+
+    __disable_irq();
+
+    return regPrimask;
+#endif
+}
+
+/*!
+ * @brief Enable the global IRQ
+ *
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+ * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+ *
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+ * DisableGlobalIRQ().
+ */
+static inline void EnableGlobalIRQ(uint32_t primask)
+{
+#if defined(CPSR_I_Msk)
+    __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+#else
+    __set_PRIMASK(primask);
+#endif
+}
+
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+/*!
+ * @brief install IRQ handler
+ *
+ * @param irq IRQ number
+ * @param irqHandler IRQ handler address
+ * @return The old IRQ handler address
+ */
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+/*
+ * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
+ * powerlib should be used instead of these functions.
+ */
+#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
+/*!
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Enable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
+ *
+ * @param interrupt The IRQ number.
+ */
+void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+/*!
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Disable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
+ *
+ * @param interrupt The IRQ number.
+ */
+void DisableDeepSleepIRQ(IRQn_Type interrupt);
+#endif /* FSL_FEATURE_POWERLIB_EXTEND */
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @} */
+
+#endif /* _FSL_COMMON_ARM_H_ */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2019-2020 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -57,7 +57,7 @@ void CRC_Init(CRC_Type *base, const crc_config_t *config)
 #endif
 
     /* configure CRC module and write the seed */
-    base->MODE = 0 | CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) |
+    base->MODE = CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) |
                  CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) |
                  CRC_MODE_CMPL_SUM(config->complementOut);
     base->SEED = config->seed;
@@ -81,7 +81,7 @@ void CRC_Init(CRC_Type *base, const crc_config_t *config)
 void CRC_GetDefaultConfig(crc_config_t *config)
 {
     /* Initializes the configure structure to zero. */
-    memset(config, 0, sizeof(*config));
+    (void)memset(config, 0, sizeof(*config));
 
     static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL,     CRC_DRIVER_DEFAULT_REVERSE_IN,
                                                 CRC_DRIVER_DEFAULT_COMPLEMENT_IN,  CRC_DRIVER_DEFAULT_REVERSE_OUT,
@@ -102,6 +102,18 @@ void CRC_Reset(CRC_Type *base)
     CRC_Init(base, &config);
 }
 
+/*!
+ * brief Write seed (initial checksum) to CRC peripheral module.
+ *
+ * param base   CRC peripheral address.
+ * param seed   CRC Seed value.
+ */
+void CRC_WriteSeed(CRC_Type *base, uint32_t seed)
+{
+    /*  write the seed (initial checksum) */
+    base->SEED = seed;
+}
+
 /*!
  * brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure.
  *
@@ -113,8 +125,9 @@ void CRC_Reset(CRC_Type *base)
 void CRC_GetConfig(CRC_Type *base, crc_config_t *config)
 {
     /* extract CRC mode settings */
-    uint32_t mode         = base->MODE;
-    config->polynomial    = (crc_polynomial_t)((mode & CRC_MODE_CRC_POLY_MASK) >> CRC_MODE_CRC_POLY_SHIFT);
+    uint32_t mode = base->MODE;
+    config->polynomial =
+        (crc_polynomial_t)(uint32_t)(((uint32_t)(mode & CRC_MODE_CRC_POLY_MASK)) >> CRC_MODE_CRC_POLY_SHIFT);
     config->reverseIn     = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK);
     config->complementIn  = (bool)(mode & CRC_MODE_CMPL_WR_MASK);
     config->reverseOut    = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK);
@@ -144,7 +157,7 @@ void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
     const uint32_t *data32;
 
     /* 8-bit reads and writes till source address is aligned 4 bytes */
-    while ((dataSize) && ((uint32_t)data & 3U))
+    while ((0U != dataSize) && (0U != ((uint32_t)data & 3U)))
     {
         *((__O uint8_t *)&(base->WR_DATA)) = *data;
         data++;
@@ -152,7 +165,7 @@ void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
     }
 
     /* use 32-bit reads and writes as long as possible */
-    data32 = (const uint32_t *)data;
+    data32 = (const uint32_t *)(uint32_t)data;
     while (dataSize >= sizeof(uint32_t))
     {
         *((__O uint32_t *)&(base->WR_DATA)) = *data32;
@@ -163,7 +176,7 @@ void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
     data = (const uint8_t *)data32;
 
     /* 8-bit reads and writes till end of data buffer */
-    while (dataSize)
+    while (0U != dataSize)
     {
         *((__O uint8_t *)&(base->WR_DATA)) = *data;
         data++;

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2019-2020 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -24,17 +24,23 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief CRC driver version. Version 2.0.1.
+/*! @brief CRC driver version. Version 2.1.1.
  *
- * Current version: 2.0.1
+ * Current version: 2.1.1
  *
  * Change log:
  * - Version 2.0.0
  *   - initial version
  * - Version 2.0.1
  *   - add explicit type cast when writing to WR_DATA
+ * - Version 2.0.2
+ *   - Fix MISRA issue
+ * - Version 2.1.0
+ *   - Add CRC_WriteSeed function
+ * - Version 2.1.1
+ *   - Fix MISRA issue
  */
-#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
 /*@}*/
 
 #ifndef CRC_DRIVER_CUSTOM_DEFAULTS
@@ -106,6 +112,14 @@ static inline void CRC_Deinit(CRC_Type *base)
  */
 void CRC_Reset(CRC_Type *base);
 
+/*!
+ * @brief Write seed to CRC peripheral module.
+ *
+ * @param base   CRC peripheral address.
+ * @param seed   CRC Seed value.
+ */
+void CRC_WriteSeed(CRC_Type *base, uint32_t seed);
+
 /*!
  * @brief Loads default values to CRC protocol configuration structure.
  *

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -25,6 +25,13 @@
  */
 static uint32_t CTIMER_GetInstance(CTIMER_Type *base);
 
+/*!
+ * @brief CTIMER generic IRQ handle function.
+ *
+ * @param index FlexCAN peripheral instance index.
+ */
+static void CTIMER_GenericIRQHandler(uint32_t index);
+
 /*******************************************************************************
  * Variables
  ******************************************************************************/
@@ -49,10 +56,11 @@ static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS;
 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
 
 /*! @brief Pointers real ISRs installed by drivers for each instance. */
-static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0};
+static ctimer_callback_t *s_ctimerCallback[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = {0};
 
 /*! @brief Callback type installed by drivers for each instance. */
-static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback};
+static ctimer_callback_type_t ctimerCallbackType[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = {
+    kCTIMER_SingleCallback};
 
 /*! @brief Array to map timer instance to IRQ number. */
 static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS;
@@ -89,7 +97,7 @@ static uint32_t CTIMER_GetInstance(CTIMER_Type *base)
  */
 void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config)
 {
-    assert(config);
+    assert(config != NULL);
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the timer clock*/
@@ -128,7 +136,7 @@ void CTIMER_Deinit(CTIMER_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Disable IRQ at NVIC Level */
-    DisableIRQ(s_ctimerIRQ[index]);
+    (void)DisableIRQ(s_ctimerIRQ[index]);
 }
 
 /*!
@@ -144,10 +152,10 @@ void CTIMER_Deinit(CTIMER_Type *base)
  */
 void CTIMER_GetDefaultConfig(ctimer_config_t *config)
 {
-    assert(config);
+    assert(config != NULL);
 
     /* Initializes the configure structure to zero. */
-    memset(config, 0, sizeof(*config));
+    (void)memset(config, 0, sizeof(*config));
 
     /* Run as a timer */
     config->mode = kCTIMER_TimerMode;
@@ -162,83 +170,87 @@ void CTIMER_GetDefaultConfig(ctimer_config_t *config)
  *
  * Enables PWM mode on the match channel passed in and will then setup the match value
  * and other match parameters to generate a PWM signal.
- * This function will assign match channel 3 to set the PWM cycle.
+ * This function can manually assign the specified channel to set the PWM cycle.
  *
  * note When setting PWM output from multiple output pins, all should use the same PWM
  * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution.
  *
  * param base             Ctimer peripheral base address
+ * param pwmPeriodChannel Specify the channel to control the PWM period
  * param matchChannel     Match pin to be used to output the PWM signal
  * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100
  * param pwmFreq_Hz       PWM signal frequency in Hz
  * param srcClock_Hz      Timer counter clock in Hz
  * param enableInt        Enable interrupt when the timer value reaches the match value of the PWM pulse,
- *                         if it is 0 then no interrupt is generated
+ *                         if it is 0 then no interrupt will be generated.
  *
  * return kStatus_Success on success
- *         kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle
+ *         kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle
  */
 status_t CTIMER_SetupPwm(CTIMER_Type *base,
+                         const ctimer_match_t pwmPeriodChannel,
                          ctimer_match_t matchChannel,
                          uint8_t dutyCyclePercent,
                          uint32_t pwmFreq_Hz,
                          uint32_t srcClock_Hz,
                          bool enableInt)
 {
-    assert(pwmFreq_Hz > 0);
+    assert(pwmFreq_Hz > 0U);
 
     uint32_t reg;
     uint32_t period, pulsePeriod = 0;
-    uint32_t timerClock = srcClock_Hz / (base->PR + 1);
+    uint32_t timerClock = srcClock_Hz / (base->PR + 1U);
     uint32_t index      = CTIMER_GetInstance(base);
 
-    if (matchChannel == kCTIMER_Match_3)
+    if (matchChannel == pwmPeriodChannel)
     {
         return kStatus_Fail;
     }
 
-    /* Enable PWM mode on the channel */
-    base->PWMC |= (1U << matchChannel);
+    /* Enable PWM mode on the match channel */
+    base->PWMC |= (1UL << (uint32_t)matchChannel);
 
     /* Clear the stop, reset and interrupt bits for this channel */
     reg = base->MCR;
-    reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
+    reg &=
+        ~(((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK))
+          << ((uint32_t)matchChannel * 3U));
 
     /* If call back function is valid then enable match interrupt for the channel */
     if (enableInt)
     {
-        reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
+        reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U)));
     }
 
-    /* Reset the counter when match on channel 3 */
-    reg |= CTIMER_MCR_MR3R_MASK;
+    /* Reset the counter when match on PWM period channel (pwmPeriodChannel)  */
+    reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U));
 
     base->MCR = reg;
 
     /* Calculate PWM period match value */
-    period = (timerClock / pwmFreq_Hz) - 1;
+    period = (timerClock / pwmFreq_Hz) - 1U;
 
     /* Calculate pulse width match value */
-    if (dutyCyclePercent == 0)
+    if (dutyCyclePercent == 0U)
     {
-        pulsePeriod = period + 1;
+        pulsePeriod = period + 1U;
     }
     else
     {
-        pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
+        pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U;
     }
 
-    /* Match on channel 3 will define the PWM period */
-    base->MR[kCTIMER_Match_3] = period;
+    /* Specified channel pwmPeriodChannel will define the PWM period */
+    base->MR[pwmPeriodChannel] = period;
 
     /* This will define the PWM pulse period */
     base->MR[matchChannel] = pulsePeriod;
     /* Clear status flags */
-    CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
+    CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel);
     /* If call back function is valid then enable interrupt and update the call back function */
     if (enableInt)
     {
-        EnableIRQ(s_ctimerIRQ[index]);
+        (void)EnableIRQ(s_ctimerIRQ[index]);
     }
 
     return kStatus_Success;
@@ -249,23 +261,28 @@ status_t CTIMER_SetupPwm(CTIMER_Type *base,
  *
  * Enables PWM mode on the match channel passed in and will then setup the match value
  * and other match parameters to generate a PWM signal.
- * This function will assign match channel 3 to set the PWM cycle.
+ * This function can manually assign the specified channel to set the PWM cycle.
  *
  * note When setting PWM output from multiple output pins, all should use the same PWM
  * period
  *
  * param base             Ctimer peripheral base address
+ * param pwmPeriodChannel Specify the channel to control the PWM period
  * param matchChannel     Match pin to be used to output the PWM signal
  * param pwmPeriod        PWM period match value
  * param pulsePeriod      Pulse width match value
  * param enableInt        Enable interrupt when the timer value reaches the match value of the PWM pulse,
- *                         if it is 0 then no interrupt is generated
+ *                         if it is 0 then no interrupt will be generated.
  *
  * return kStatus_Success on success
- *         kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period
+ *         kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM period
  */
-status_t CTIMER_SetupPwmPeriod(
-    CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt)
+status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base,
+                               const ctimer_match_t pwmPeriodChannel,
+                               ctimer_match_t matchChannel,
+                               uint32_t pwmPeriod,
+                               uint32_t pulsePeriod,
+                               bool enableInt)
 {
 /* Some CTimers only have 16bits , so the value is limited*/
 #if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B
@@ -275,40 +292,42 @@ status_t CTIMER_SetupPwmPeriod(
     uint32_t reg;
     uint32_t index = CTIMER_GetInstance(base);
 
-    if (matchChannel == kCTIMER_Match_3)
+    if (matchChannel == pwmPeriodChannel)
     {
         return kStatus_Fail;
     }
 
-    /* Enable PWM mode on the channel */
-    base->PWMC |= (1U << matchChannel);
+    /* Enable PWM mode on PWM pulse channel */
+    base->PWMC |= (1UL << (uint32_t)matchChannel);
 
-    /* Clear the stop, reset and interrupt bits for this channel */
+    /* Clear the stop, reset and interrupt bits for PWM pulse channel */
     reg = base->MCR;
-    reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
+    reg &=
+        ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)
+          << ((uint32_t)matchChannel * 3U));
 
-    /* If call back function is valid then enable match interrupt for the channel */
+    /* If call back function is valid then enable match interrupt for PWM pulse channel */
     if (enableInt)
     {
-        reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
+        reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U)));
     }
 
-    /* Reset the counter when match on channel 3 */
-    reg |= CTIMER_MCR_MR3R_MASK;
+    /* Reset the counter when match on PWM period channel (pwmPeriodChannel)  */
+    reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U));
 
     base->MCR = reg;
 
-    /* Match on channel 3 will define the PWM period */
-    base->MR[kCTIMER_Match_3] = pwmPeriod;
+    /* Specified channel pwmPeriodChannel will define the PWM period */
+    base->MR[pwmPeriodChannel] = pwmPeriod;
 
     /* This will define the PWM pulse period */
     base->MR[matchChannel] = pulsePeriod;
     /* Clear status flags */
-    CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
+    CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel);
     /* If call back function is valid then enable interrupt and update the call back function */
     if (enableInt)
     {
-        EnableIRQ(s_ctimerIRQ[index]);
+        (void)EnableIRQ(s_ctimerIRQ[index]);
     }
 
     return kStatus_Success;
@@ -317,30 +336,32 @@ status_t CTIMER_SetupPwmPeriod(
 /*!
  * brief Updates the duty cycle of an active PWM signal.
  *
- * note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution.
+ * note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution.
+ * This function can manually assign the specified channel to set the PWM cycle.
  *
  * param base             Ctimer peripheral base address
+ * param pwmPeriodChannel Specify the channel to control the PWM period
  * param matchChannel     Match pin to be used to output the PWM signal
  * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100
  */
-void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent)
+void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base,
+                               const ctimer_match_t pwmPeriodChannel,
+                               ctimer_match_t matchChannel,
+                               uint8_t dutyCyclePercent)
 {
     uint32_t pulsePeriod = 0, period;
 
-    /* Match channel 3 defines the PWM period */
-    period = base->MR[kCTIMER_Match_3];
-
-    /* Calculate pulse width match value */
-    pulsePeriod = (period * dutyCyclePercent) / 100;
+    /* Specified channel pwmPeriodChannel  defines the PWM period */
+    period = base->MR[pwmPeriodChannel];
 
     /* For 0% dutycyle, make pulse period greater than period so the event will never occur */
-    if (dutyCyclePercent == 0)
+    if (dutyCyclePercent == 0U)
     {
-        pulsePeriod = period + 1;
+        pulsePeriod = period + 1U;
     }
     else
     {
-        pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
+        pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U;
     }
 
     /* Update dutycycle */
@@ -367,33 +388,53 @@ void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const cti
 
     /* Set the counter operation when a match on this channel occurs */
     reg = base->MCR;
-    reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
-    reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3)));
-    reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3)));
-    reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
+    reg &=
+        ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)
+          << ((uint32_t)matchChannel * 3U));
+    reg |= ((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)matchChannel * 3U)));
+    reg |= ((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)matchChannel * 3U)));
+    reg |= ((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U)));
     base->MCR = reg;
 
     reg = base->EMR;
     /* Set the match output operation when a match on this channel occurs */
-    reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2));
-    reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2));
+    reg &= ~(((uint32_t)CTIMER_EMR_EMC0_MASK) << ((uint32_t)matchChannel * 2U));
+    reg |= ((uint32_t)config->outControl) << (CTIMER_EMR_EMC0_SHIFT + ((uint32_t)matchChannel * 2U));
 
     /* Set the initial state of the EM bit/output */
-    reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel);
-    reg |= (uint32_t)config->outPinInitState << matchChannel;
+    reg &= ~(((uint32_t)CTIMER_EMR_EM0_MASK) << (uint32_t)matchChannel);
+    reg |= ((uint32_t)config->outPinInitState) << (uint32_t)matchChannel;
     base->EMR = reg;
 
     /* Set the match value */
     base->MR[matchChannel] = config->matchValue;
     /* Clear status flags */
-    CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
+    CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel);
     /* If interrupt is enabled then enable interrupt and update the call back function */
     if (config->enableInterrupt)
     {
-        EnableIRQ(s_ctimerIRQ[index]);
+        (void)EnableIRQ(s_ctimerIRQ[index]);
     }
 }
 
+/*!
+ * brief Get the status of output match.
+ *
+ * This function gets the status of output MAT, whether or not this output is connected to a pin.
+ * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ *
+ * param base         Ctimer peripheral base address
+ * param matchChannel External match channel, user can obtain the status of multiple match channels
+ *                    at the same time by using the logic of "|"
+ *                    enumeration ::ctimer_external_match_t
+ * return The mask of external match channel status flags. Users need to use the
+ *        _ctimer_external_match type to decode the return variables.
+ */
+uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel)
+{
+    return (base->EMR & matchChannel);
+}
+
 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
 /*!
  * brief Setup the capture.
@@ -413,15 +454,17 @@ void CTIMER_SetupCapture(CTIMER_Type *base,
     uint32_t index = CTIMER_GetInstance(base);
 
     /* Set the capture edge */
-    reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3));
-    reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3));
+    reg &= ~((uint32_t)((uint32_t)CTIMER_CCR_CAP0RE_MASK | (uint32_t)CTIMER_CCR_CAP0FE_MASK |
+                        (uint32_t)CTIMER_CCR_CAP0I_MASK)
+             << ((uint32_t)capture * 3U));
+    reg |= ((uint32_t)edge) << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U));
     /* Clear status flags */
-    CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture));
+    CTIMER_ClearStatusFlags(base, (((uint32_t)kCTIMER_Capture0Flag) << (uint32_t)capture));
     /* If call back function is valid then enable capture interrupt for the channel and update the call back function */
     if (enableInt)
     {
-        reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3);
-        EnableIRQ(s_ctimerIRQ[index]);
+        reg |= ((uint32_t)CTIMER_CCR_CAP0I_MASK) << ((uint32_t)capture * 3U);
+        (void)EnableIRQ(s_ctimerIRQ[index]);
     }
     base->CCR = reg;
 }
@@ -441,7 +484,12 @@ void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctim
     ctimerCallbackType[index] = cb_type;
 }
 
-void CTIMER_GenericIRQHandler(uint32_t index)
+/*!
+ * brief CTIMER generic IRQ handle function.
+ *
+ * param index FlexCAN peripheral instance index.
+ */
+static void CTIMER_GenericIRQHandler(uint32_t index)
 {
     uint32_t int_stat, i, mask;
     /* Get Interrupt status flags */
@@ -450,7 +498,7 @@ void CTIMER_GenericIRQHandler(uint32_t index)
     CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat);
     if (ctimerCallbackType[index] == kCTIMER_SingleCallback)
     {
-        if (s_ctimerCallback[index][0])
+        if (s_ctimerCallback[index][0] != NULL)
         {
             s_ctimerCallback[index][0](int_stat);
         }
@@ -463,82 +511,67 @@ void CTIMER_GenericIRQHandler(uint32_t index)
 #if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT
         for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++)
 #else
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT)
         for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++)
+#else
+        for (i = 0; i <= CTIMER_IR_CR1INT_SHIFT; i++)
+#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */
 #endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
 #endif
         {
-            mask = 0x01 << i;
+            mask = 0x01UL << i;
             /* For each status flag bit that was set call the callback function if it is valid */
-            if ((int_stat & mask) && (s_ctimerCallback[index][i]))
+            if (((int_stat & mask) != 0U) && (s_ctimerCallback[index][i] != NULL))
             {
                 s_ctimerCallback[index][i](int_stat);
             }
         }
     }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 
 /* IRQ handler functions overloading weak symbols in the startup */
 #if defined(CTIMER0)
+void CTIMER0_DriverIRQHandler(void);
 void CTIMER0_DriverIRQHandler(void)
 {
     CTIMER_GenericIRQHandler(0);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(CTIMER1)
+void CTIMER1_DriverIRQHandler(void);
 void CTIMER1_DriverIRQHandler(void)
 {
     CTIMER_GenericIRQHandler(1);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(CTIMER2)
+void CTIMER2_DriverIRQHandler(void);
 void CTIMER2_DriverIRQHandler(void)
 {
     CTIMER_GenericIRQHandler(2);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(CTIMER3)
+void CTIMER3_DriverIRQHandler(void);
 void CTIMER3_DriverIRQHandler(void)
 {
     CTIMER_GenericIRQHandler(3);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(CTIMER4)
+void CTIMER4_DriverIRQHandler(void);
 void CTIMER4_DriverIRQHandler(void)
 {
     CTIMER_GenericIRQHandler(4);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -23,7 +23,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */
+#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*!< Version 2.2.2 */
 /*@}*/
 
 /*! @brief List of Timer capture channels */
@@ -31,10 +31,12 @@ typedef enum _ctimer_capture_channel
 {
     kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */
     kCTIMER_Capture_1,      /*!< Timer capture channel 1 */
-    kCTIMER_Capture_2,      /*!< Timer capture channel 2 */
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2)
+    kCTIMER_Capture_2, /*!< Timer capture channel 2 */
+#endif                 /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */
 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
     kCTIMER_Capture_3 /*!< Timer capture channel 3 */
-#endif                /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
+#endif                /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
 } ctimer_capture_channel_t;
 
 /*! @brief List of capture edge options */
@@ -54,6 +56,15 @@ typedef enum _ctimer_match
     kCTIMER_Match_3       /*!< Timer match register 3 */
 } ctimer_match_t;
 
+/*! @brief List of external match */
+typedef enum _ctimer_external_match
+{
+    kCTIMER_External_Match_0 = (1U << 0), /*!< External match 0 */
+    kCTIMER_External_Match_1 = (1U << 1), /*!< External match 1 */
+    kCTIMER_External_Match_2 = (1U << 2), /*!< External match 2 */
+    kCTIMER_External_Match_3 = (1U << 3)  /*!< External match 3 */
+} ctimer_external_match_t;
+
 /*! @brief List of output control options */
 typedef enum _ctimer_match_output_control
 {
@@ -82,7 +93,9 @@ typedef enum _ctimer_interrupt_enable
 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
     kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */
     kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2)
     kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */
+#endif                                                       /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */
 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
     kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */
 #endif                                                       /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
@@ -99,7 +112,9 @@ typedef enum _ctimer_status_flags
 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
     kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */
     kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT)
     kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */
+#endif                                            /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */
 #if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT
     kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */
 #endif                                            /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
@@ -211,46 +226,47 @@ void CTIMER_GetDefaultConfig(ctimer_config_t *config);
  *
  * Enables PWM mode on the match channel passed in and will then setup the match value
  * and other match parameters to generate a PWM signal.
- * This function will assign match channel 3 to set the PWM cycle.
+ * This function can manually assign the specified channel to set the PWM cycle.
  *
  * @note When setting PWM output from multiple output pins, all should use the same PWM
  * period
  *
  * @param base             Ctimer peripheral base address
+ * @param pwmPeriodChannel Specify the channel to control the PWM period
  * @param matchChannel     Match pin to be used to output the PWM signal
  * @param pwmPeriod        PWM period match value
  * @param pulsePeriod      Pulse width match value
  * @param enableInt        Enable interrupt when the timer value reaches the match value of the PWM pulse,
- *                         if it is 0 then no interrupt is generated
- *
- * @return kStatus_Success on success
- *         kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period
+ *                         if it is 0 then no interrupt will be generated.
  */
-status_t CTIMER_SetupPwmPeriod(
-    CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt);
+status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base,
+                               const ctimer_match_t pwmPeriodChannel,
+                               ctimer_match_t matchChannel,
+                               uint32_t pwmPeriod,
+                               uint32_t pulsePeriod,
+                               bool enableInt);
 
 /*!
  * @brief Configures the PWM signal parameters.
  *
  * Enables PWM mode on the match channel passed in and will then setup the match value
  * and other match parameters to generate a PWM signal.
- * This function will assign match channel 3 to set the PWM cycle.
+ * This function can manually assign the specified channel to set the PWM cycle.
  *
  * @note When setting PWM output from multiple output pins, all should use the same PWM
  * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution.
  *
  * @param base             Ctimer peripheral base address
+ * @param pwmPeriodChannel Specify the channel to control the PWM period
  * @param matchChannel     Match pin to be used to output the PWM signal
  * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100
  * @param pwmFreq_Hz       PWM signal frequency in Hz
  * @param srcClock_Hz      Timer counter clock in Hz
  * @param enableInt        Enable interrupt when the timer value reaches the match value of the PWM pulse,
- *                         if it is 0 then no interrupt is generated
- *
- * @return kStatus_Success on success
- *         kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle
+ *                         if it is 0 then no interrupt will be generated.
  */
 status_t CTIMER_SetupPwm(CTIMER_Type *base,
+                         const ctimer_match_t pwmPeriodChannel,
                          ctimer_match_t matchChannel,
                          uint8_t dutyCyclePercent,
                          uint32_t pwmFreq_Hz,
@@ -273,13 +289,18 @@ static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t
 /*!
  * @brief Updates the duty cycle of an active PWM signal.
  *
- * @note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution.
+ * @note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution.
+ * This function can manually assign the specified channel to set the PWM cycle.
  *
  * @param base             Ctimer peripheral base address
+ * @param pwmPeriodChannel Specify the channel to control the PWM period
  * @param matchChannel     Match pin to be used to output the PWM signal
  * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100
  */
-void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent);
+void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base,
+                               const ctimer_match_t pwmPeriodChannel,
+                               ctimer_match_t matchChannel,
+                               uint8_t dutyCyclePercent);
 
 /*! @}*/
 
@@ -294,6 +315,21 @@ void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, u
  */
 void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config);
 
+/*!
+ * @brief Get the status of output match.
+ *
+ * This function gets the status of output MAT, whether or not this output is connected to a pin.
+ * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ *
+ * @param base         Ctimer peripheral base address
+ * @param matchChannel External match channel, user can obtain the status of multiple match channels
+ *                     at the same time by using the logic of "|"
+ *                     enumeration ::ctimer_external_match_t
+ * @return The mask of external match channel status flags. Users need to use the
+ *         _ctimer_external_match type to decode the return variables.
+ */
+uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel);
+
 /*!
  * @brief Setup the capture.
  *
@@ -347,7 +383,10 @@ static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask)
 
 /* Enable capture interrupts */
 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
-    base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
+    base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2)
+                         | CTIMER_CCR_CAP2I_MASK
+#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */
 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
                          | CTIMER_CCR_CAP3I_MASK
 #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
@@ -369,7 +408,10 @@ static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask)
 
 /* Disable capture interrupts */
 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
-    base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
+    base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2)
+                           | CTIMER_CCR_CAP2I_MASK
+#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */
 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
                            | CTIMER_CCR_CAP3I_MASK
 #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
@@ -395,7 +437,10 @@ static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base)
 
 /* Get all the capture interrupts enabled */
 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
-    enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
+    enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2)
+                                 | CTIMER_CCR_CAP2I_MASK
+#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */
 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
                                  | CTIMER_CCR_CAP3I_MASK
 #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.c

@@ -1,12 +1,15 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_dma.h"
+#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET)
+#include "fsl_memory.h"
+#endif
 
 /*******************************************************************************
  * Definitions
@@ -55,10 +58,34 @@ static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS;
 
 /*! @brief Pointers to transfer handle for each DMA channel. */
 static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS];
+
 /*! @brief DMA driver internal descriptor table */
-DMA_ALLOCATE_HEAD_DESCRIPTORS(s_dma_descriptor_table0, FSL_FEATURE_DMA_MAX_CHANNELS);
+#ifdef FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE
+SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS],
+          FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE);
+#else
+#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp))
+AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS],
+                              FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE);
+#else
+SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS],
+          FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE);
+#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */
+#endif /* FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE */
+
 #if defined(DMA1)
-DMA_ALLOCATE_HEAD_DESCRIPTORS(s_dma_descriptor_table1, FSL_FEATURE_DMA_MAX_CHANNELS);
+#ifdef FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE
+SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS],
+          FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE);
+#else
+#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp))
+AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS],
+                              FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE);
+#else
+SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS],
+          FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE);
+#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */
+#endif /* FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE */
 static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0, s_dma_descriptor_table1};
 #else
 static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0};
@@ -70,7 +97,7 @@ static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0};
 
 static uint32_t DMA_GetInstance(DMA_Type *base)
 {
-    int32_t instance;
+    uint32_t instance;
     /* Find the instance index from base address mappings. */
     for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++)
     {
@@ -94,7 +121,7 @@ static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base)
     /* Compute start channel */
     for (i = 0; i < instance; i++)
     {
-        startChannel += FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]);
+        startChannel += (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]);
     }
 
     return startChannel;
@@ -121,7 +148,11 @@ void DMA_Init(DMA_Type *base)
     RESET_PeripheralReset(s_dmaResets[DMA_GetInstance(base)]);
 #endif
     /* set descriptor table */
+#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET)
+    base->SRAMBASE = MEMORY_ConvertMemoryMapAddress((uint32_t)s_dma_descriptor_table[instance], kMEMORY_Local2DMA);
+#else
     base->SRAMBASE = (uint32_t)s_dma_descriptor_table[instance];
+#endif
     /* enable dma peripheral */
     base->CTRL |= DMA_CTRL_ENABLE_MASK;
 }
@@ -152,14 +183,15 @@ void DMA_Deinit(DMA_Type *base)
  */
 void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger)
 {
-    assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger));
-
-    uint32_t tmp = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK |
-                    DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK |
-                    DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK);
-    tmp          = base->CHANNEL[channel].CFG & (~tmp);
-    tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap);
-    base->CHANNEL[channel].CFG = tmp;
+    assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1);
+    assert((channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger));
+
+    uint32_t tmpReg = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK |
+                       DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK |
+                       DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK);
+    tmpReg          = base->CHANNEL[channel].CFG & (~tmpReg);
+    tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap);
+    base->CHANNEL[channel].CFG = tmpReg;
 }
 
 /*!
@@ -171,7 +203,8 @@ void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_t
  */
 uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
+    assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1);
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
 
     /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes
      * impossible to distinguish between:
@@ -182,15 +215,15 @@ uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)
 
     /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */
     if ((!DMA_ChannelIsActive(base, channel)) &&
-        (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >>
-                   DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)))
+        (0x3FFUL == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >>
+                     DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)))
     {
-        return 0;
+        return 0UL;
     }
 
     return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >>
             DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) +
-           1;
+           1UL;
 }
 
 /* Verify and convert dma_xfercfg_t to XFERCFG register */
@@ -198,9 +231,10 @@ static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr)
 {
     assert(xfercfg != NULL);
     /* check source increment */
-    assert((xfercfg->srcInc <= kDMA_AddressInterleave4xWidth) && (xfercfg->dstInc <= kDMA_AddressInterleave4xWidth));
+    assert((xfercfg->srcInc <= (uint8_t)kDMA_AddressInterleave4xWidth) &&
+           (xfercfg->dstInc <= (uint8_t)kDMA_AddressInterleave4xWidth));
     /* check data width */
-    assert(xfercfg->byteWidth <= kDMA_Transfer32BitWidth);
+    assert(xfercfg->byteWidth <= (uint8_t)kDMA_Transfer32BitWidth);
     /* check transfer count */
     assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT);
 
@@ -219,15 +253,15 @@ static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr)
     /* set INTB */
     xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB);
     /* set data width */
-    xfer |= DMA_CHANNEL_XFERCFG_WIDTH(xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1);
+    xfer |= DMA_CHANNEL_XFERCFG_WIDTH(xfercfg->byteWidth == 4U ? 2U : xfercfg->byteWidth - 1UL);
     /* set source increment value */
-    xfer |= DMA_CHANNEL_XFERCFG_SRCINC((xfercfg->srcInc == kDMA_AddressInterleave4xWidth) ? (xfercfg->srcInc - 1) :
-                                                                                            xfercfg->srcInc);
+    xfer |= DMA_CHANNEL_XFERCFG_SRCINC(
+        (xfercfg->srcInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->srcInc - 1UL) : xfercfg->srcInc);
     /* set destination increment value */
-    xfer |= DMA_CHANNEL_XFERCFG_DSTINC((xfercfg->dstInc == kDMA_AddressInterleave4xWidth) ? (xfercfg->dstInc - 1) :
-                                                                                            xfercfg->dstInc);
+    xfer |= DMA_CHANNEL_XFERCFG_DSTINC(
+        (xfercfg->dstInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->dstInc - 1UL) : xfercfg->dstInc);
     /* set transfer count */
-    xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1);
+    xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1UL);
 
     /* store xferCFG */
     *xfercfg_addr = xfer;
@@ -245,7 +279,13 @@ static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr)
 void DMA_SetupDescriptor(
     dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc)
 {
-    assert(((uint32_t)nextDesc & (FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1)) == 0U);
+    assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL);
+
+#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET)
+    srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA);
+    dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA);
+    nextDesc     = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA);
+#endif
 
     uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0;
 
@@ -264,20 +304,36 @@ void DMA_SetupDescriptor(
         width += 1U;
     }
 
-    if (srcInc == 3U)
+    /*
+     * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes.
+     * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes.
+     * Transfers of 8 bit width can be at any address
+     */
+    if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) &&
+        ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width)))
     {
-        srcInc = kDMA_AddressInterleave4xWidth;
-    }
+        if (srcInc == 3U)
+        {
+            srcInc = kDMA_AddressInterleave4xWidth;
+        }
+
+        if (dstInc == 3U)
+        {
+            dstInc = kDMA_AddressInterleave4xWidth;
+        }
 
-    if (dstInc == 3U)
+        desc->xfercfg    = xfercfg;
+        desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width);
+        desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width);
+        desc->linkToNextDesc = nextDesc;
+    }
+    else
     {
-        dstInc = kDMA_AddressInterleave4xWidth;
+        /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */
+        desc->xfercfg    = 0U;
+        desc->srcEndAddr = NULL;
+        desc->dstEndAddr = NULL;
     }
-
-    desc->xfercfg        = xfercfg;
-    desc->srcEndAddr     = DMA_DESCRIPTOR_END_ADDRESS(srcStartAddr, srcInc, transferCount * width, width);
-    desc->dstEndAddr     = DMA_DESCRIPTOR_END_ADDRESS(dstStartAddr, dstInc, transferCount * width, width);
-    desc->linkToNextDesc = nextDesc;
 }
 
 /*!
@@ -299,7 +355,13 @@ void DMA_SetupChannelDescriptor(dma_descriptor_t *desc,
                                 dma_burst_wrap_t wrapType,
                                 uint32_t burstSize)
 {
-    assert(((uint32_t)nextDesc & (FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1)) == 0U);
+    assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL);
+
+#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET)
+    srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA);
+    dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA);
+    nextDesc     = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA);
+#endif
 
     uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0;
 
@@ -318,41 +380,65 @@ void DMA_SetupChannelDescriptor(dma_descriptor_t *desc,
         width += 1U;
     }
 
-    if (srcInc == 3U)
+    /*
+     * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes.
+     * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes.
+     * Transfers of 8 bit width can be at any address
+     */
+    if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) &&
+        ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width)))
     {
-        srcInc = kDMA_AddressInterleave4xWidth;
-    }
+        if (srcInc == 3U)
+        {
+            srcInc = kDMA_AddressInterleave4xWidth;
+        }
 
-    if (dstInc == 3U)
-    {
-        dstInc = kDMA_AddressInterleave4xWidth;
-    }
+        if (dstInc == 3U)
+        {
+            dstInc = kDMA_AddressInterleave4xWidth;
+        }
 
-    desc->xfercfg = xfercfg;
+        desc->xfercfg = xfercfg;
 
-    if (wrapType == kDMA_NoWrap)
-    {
-        desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS(srcStartAddr, srcInc, transferCount * width, width);
-        desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS(dstStartAddr, dstInc, transferCount * width, width);
-    }
-    /* for the wrap transfer, the destination address should be determined by the burstSize/width/interleave size */
-    if (wrapType == kDMA_SrcWrap)
-    {
-        desc->srcEndAddr = (void *)((uint32_t)srcStartAddr + ((1U << burstSize) - 1U) * width * srcInc);
-        desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS(dstStartAddr, dstInc, transferCount * width, width);
-    }
-    if (wrapType == kDMA_DstWrap)
-    {
-        desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS(srcStartAddr, srcInc, transferCount * width, width);
-        desc->dstEndAddr = (void *)((uint32_t)dstStartAddr + ((1U << burstSize) - 1U) * width * dstInc);
+        if (wrapType == kDMA_NoWrap)
+        {
+            desc->srcEndAddr =
+                DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width);
+            desc->dstEndAddr =
+                DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width);
+        }
+        /* for the wrap transfer, the destination address should be determined by the burstSize/width/interleave size */
+        if (wrapType == kDMA_SrcWrap)
+        {
+            desc->srcEndAddr =
+                (uint32_t *)((uint32_t)(uint32_t *)srcStartAddr + ((1UL << burstSize) - 1UL) * width * srcInc);
+            desc->dstEndAddr =
+                DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width);
+        }
+        if (wrapType == kDMA_DstWrap)
+        {
+            desc->srcEndAddr =
+                DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width);
+            desc->dstEndAddr =
+                (uint32_t *)((uint32_t)(uint32_t *)dstStartAddr + ((1UL << burstSize) - 1UL) * width * dstInc);
+        }
+        if (wrapType == kDMA_SrcAndDstWrap)
+        {
+            desc->srcEndAddr =
+                (uint32_t *)(((uint32_t)(uint32_t *)srcStartAddr) + ((1UL << burstSize) - 1UL) * width * srcInc);
+            desc->dstEndAddr =
+                (uint32_t *)(((uint32_t)(uint32_t *)dstStartAddr) + ((1UL << burstSize) - 1UL) * width * dstInc);
+        }
+
+        desc->linkToNextDesc = nextDesc;
     }
-    if (wrapType == kDMA_SrcAndDstWrap)
+    else
     {
-        desc->srcEndAddr = (void *)((uint32_t)srcStartAddr + ((1U << burstSize) - 1U) * width * srcInc);
-        desc->dstEndAddr = (void *)((uint32_t)dstStartAddr + ((1U << burstSize) - 1U) * width * dstInc);
+        /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */
+        desc->xfercfg    = 0U;
+        desc->srcEndAddr = NULL;
+        desc->dstEndAddr = NULL;
     }
-
-    desc->linkToNextDesc = nextDesc;
 }
 
 /*!
@@ -367,9 +453,9 @@ void DMA_SetupChannelDescriptor(dma_descriptor_t *desc,
  */
 void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc)
 {
-    assert(((uint32_t)nextDesc & (FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1)) == 0U);
-    assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth));
-    assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth));
+    assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL);
+    assert((NULL != srcAddr) && (0UL == ((uint32_t)(uint32_t *)srcAddr) % xfercfg->byteWidth));
+    assert((NULL != dstAddr) && (0UL == ((uint32_t)(uint32_t *)dstAddr) % xfercfg->byteWidth));
 
     uint32_t xfercfg_reg = 0;
 
@@ -391,10 +477,11 @@ void DMA_AbortTransfer(dma_handle_t *handle)
     assert(NULL != handle);
 
     DMA_DisableChannel(handle->base, handle->channel);
-    while (DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & (1U << DMA_CHANNEL_INDEX(handle->channel)))
+    while ((DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) &
+            (1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel))) != 0UL)
     {
     }
-    DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1U << DMA_CHANNEL_INDEX(handle->channel);
+    DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel);
     DMA_EnableChannel(handle->base, handle->channel);
 }
 
@@ -411,20 +498,21 @@ void DMA_AbortTransfer(dma_handle_t *handle)
  */
 void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel)
 {
-    assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)));
+    assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1);
+    assert((NULL != handle) && (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)));
 
-    int32_t dmaInstance;
+    uint32_t dmaInstance;
     uint32_t startChannel = 0;
     /* base address is invalid DMA instance */
     dmaInstance  = DMA_GetInstance(base);
     startChannel = DMA_GetVirtualStartChannel(base);
 
-    memset(handle, 0, sizeof(*handle));
+    (void)memset(handle, 0, sizeof(*handle));
     handle->base                        = base;
-    handle->channel                     = channel;
+    handle->channel                     = (uint8_t)channel;
     s_DMAHandle[startChannel + channel] = handle;
     /* Enable NVIC interrupt */
-    EnableIRQ(s_dmaIRQNumber[dmaInstance]);
+    (void)EnableIRQ(s_dmaIRQNumber[dmaInstance]);
     /* Enable channel interrupt */
     DMA_EnableChannelInterrupts(handle->base, channel);
 }
@@ -474,47 +562,49 @@ void DMA_PrepareTransfer(dma_transfer_config_t *config,
 {
     uint32_t xfer_count;
     assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr));
-    assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4));
-    assert(((uint32_t)nextDesc & (FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1)) == 0U);
+    assert((byteWidth == 1UL) || (byteWidth == 2UL) || (byteWidth == 4UL));
+    assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL);
 
     /* check max */
     xfer_count = transferBytes / byteWidth;
-    assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0 == transferBytes % byteWidth));
+    assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0UL == transferBytes % byteWidth));
+
+    (void)memset(config, 0, sizeof(*config));
 
-    memset(config, 0, sizeof(*config));
-    switch (type)
+    if (type == kDMA_MemoryToMemory)
     {
-        case kDMA_MemoryToMemory:
-            config->xfercfg.srcInc = 1;
-            config->xfercfg.dstInc = 1;
-            config->isPeriph       = false;
-            break;
-        case kDMA_PeripheralToMemory:
-            /* Peripheral register - source doesn't increment */
-            config->xfercfg.srcInc = 0;
-            config->xfercfg.dstInc = 1;
-            config->isPeriph       = true;
-            break;
-        case kDMA_MemoryToPeripheral:
-            /* Peripheral register - destination doesn't increment */
-            config->xfercfg.srcInc = 1;
-            config->xfercfg.dstInc = 0;
-            config->isPeriph       = true;
-            break;
-        case kDMA_StaticToStatic:
-            config->xfercfg.srcInc = 0;
-            config->xfercfg.dstInc = 0;
-            config->isPeriph       = true;
-            break;
-        default:
-            return;
+        config->xfercfg.srcInc = 1;
+        config->xfercfg.dstInc = 1;
+        config->isPeriph       = false;
+    }
+
+    else if (type == kDMA_PeripheralToMemory)
+    {
+        /* Peripheral register - source doesn't increment */
+        config->xfercfg.srcInc = 0;
+        config->xfercfg.dstInc = 1;
+        config->isPeriph       = true;
+    }
+    else if (type == kDMA_MemoryToPeripheral)
+    {
+        /* Peripheral register - destination doesn't increment */
+        config->xfercfg.srcInc = 1;
+        config->xfercfg.dstInc = 0;
+        config->isPeriph       = true;
+    }
+    /* kDMA_StaticToStatic */
+    else
+    {
+        config->xfercfg.srcInc = 0;
+        config->xfercfg.dstInc = 0;
+        config->isPeriph       = true;
     }
 
     config->dstAddr               = (uint8_t *)dstAddr;
     config->srcAddr               = (uint8_t *)srcAddr;
     config->nextDesc              = (uint8_t *)nextDesc;
-    config->xfercfg.transferCount = xfer_count;
-    config->xfercfg.byteWidth     = byteWidth;
+    config->xfercfg.transferCount = (uint16_t)xfer_count;
+    config->xfercfg.byteWidth     = (uint8_t)byteWidth;
     config->xfercfg.intA          = true;
     config->xfercfg.reload        = nextDesc != NULL;
     config->xfercfg.valid         = true;
@@ -531,27 +621,27 @@ void DMA_PrepareTransfer(dma_transfer_config_t *config,
  */
 void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph)
 {
-    assert(channel <= FSL_FEATURE_DMA_MAX_CHANNELS);
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_MAX_CHANNELS);
 
-    uint32_t tmp = DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
+    uint32_t tmpReg = DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
 
     if (trigger != NULL)
     {
-        tmp |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK |
-               DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK |
-               DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK;
+        tmpReg |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK |
+                  DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK |
+                  DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK;
     }
 
-    tmp = base->CHANNEL[channel].CFG & (~tmp);
+    tmpReg = base->CHANNEL[channel].CFG & (~tmpReg);
 
     if (trigger != NULL)
     {
-        tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap);
+        tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap);
     }
 
-    tmp |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph);
+    tmpReg |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph);
 
-    base->CHANNEL[channel].CFG = tmp;
+    base->CHANNEL[channel].CFG = tmpReg;
 }
 
 /*!
@@ -576,27 +666,27 @@ void DMA_PrepareChannelTransfer(dma_channel_config_t *config,
                                 void *nextDesc)
 {
     assert((NULL != config) && (NULL != srcStartAddr) && (NULL != dstStartAddr));
-    assert(((uint32_t)nextDesc & (FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1)) == 0U);
+    assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL);
 
     /* check max */
-    memset(config, 0, sizeof(*config));
+    (void)memset(config, 0, sizeof(*config));
 
-    switch (type)
+    if (type == kDMA_MemoryToMemory)
     {
-        case kDMA_MemoryToMemory:
-            config->isPeriph = false;
-            break;
-        case kDMA_PeripheralToMemory:
-            config->isPeriph = true;
-            break;
-        case kDMA_MemoryToPeripheral:
-            config->isPeriph = true;
-            break;
-        case kDMA_StaticToStatic:
-            config->isPeriph = true;
-            break;
-        default:
-            return;
+        config->isPeriph = false;
+    }
+    else if (type == kDMA_PeripheralToMemory)
+    {
+        config->isPeriph = true;
+    }
+    else if (type == kDMA_MemoryToPeripheral)
+    {
+        config->isPeriph = true;
+    }
+    /* kDMA_StaticToStatic */
+    else
+    {
+        config->isPeriph = true;
     }
 
     config->dstStartAddr = (uint8_t *)dstStartAddr;
@@ -606,6 +696,43 @@ void DMA_PrepareChannelTransfer(dma_channel_config_t *config,
     config->xferCfg      = xferCfg;
 }
 
+/*!
+ * brief load channel transfer decriptor.
+ *
+ * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA
+ * transfer, the head descriptor table is defined in DMA driver, it is useful for the case:
+ * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly
+ * and then call this api to load the configured descriptor to driver descriptor table. code DMA_Init(DMA0);
+ *   DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL);
+ *   DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL);
+ *   DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc);
+ *   DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL);
+ *   while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL))
+ *   {}
+ * endcode
+ *
+ * param base DMA base address.
+ * param channel DMA channel.
+ * param descriptor configured DMA descriptor.
+ */
+void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor)
+{
+    assert(NULL != descriptor);
+    assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1);
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
+
+    uint32_t instance                   = DMA_GetInstance(base);
+    dma_descriptor_t *channelDescriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][channel]);
+
+    channelDescriptor->xfercfg        = descriptor->xfercfg;
+    channelDescriptor->srcEndAddr     = descriptor->srcEndAddr;
+    channelDescriptor->dstEndAddr     = descriptor->dstEndAddr;
+    channelDescriptor->linkToNextDesc = descriptor->linkToNextDesc;
+
+    /* Set channel XFERCFG register according first channel descriptor. */
+    base->CHANNEL[channel].XFERCFG = descriptor->xfercfg;
+}
+
 /*!
  * brief Install DMA descriptor memory.
  *
@@ -621,10 +748,14 @@ void DMA_PrepareChannelTransfer(dma_channel_config_t *config,
 void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr)
 {
     assert(addr != NULL);
-    assert(((uint32_t)addr & (FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE - 1U)) == 0U);
 
+#if defined FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn
+    assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn(base) - 1UL)) == 0U);
+#else
+    assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0U);
+#endif
     /* reconfigure the DMA descriptor base address */
-    base->SRAMBASE = (uint32_t)addr;
+    base->SRAMBASE = (uint32_t)(uint32_t *)addr;
 }
 
 /*!
@@ -646,7 +777,7 @@ void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr)
  required, then application should prepare
  *  three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor.
  * code
-    //define link descriptor table in application with macro
+    define link descriptor table in application with macro
     DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]);
 
     DMA_SetupDescriptor(nextDesc0,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
@@ -669,18 +800,19 @@ void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr)
  * param nextDesc address of next descriptor.
  */
 void DMA_SubmitChannelTransferParameter(
-    dma_handle_t *handle, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc)
+    dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc)
 {
     assert((NULL != srcStartAddr) && (NULL != dstStartAddr));
-    assert(handle->channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base));
+    assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1);
+    assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base));
 
     uint32_t instance            = DMA_GetInstance(handle->base);
     dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]);
 
-    DMA_SetupDescriptor(descriptor, xfercfg, srcStartAddr, dstStartAddr, nextDesc);
+    DMA_SetupDescriptor(descriptor, xferCfg, srcStartAddr, dstStartAddr, nextDesc);
 
     /* Set channel XFERCFG register according first channel descriptor. */
-    handle->base->CHANNEL[handle->channel].XFERCFG = xfercfg;
+    handle->base->CHANNEL[handle->channel].XFERCFG = xferCfg;
 }
 
 /*!
@@ -693,7 +825,7 @@ void DMA_SubmitChannelTransferParameter(
  * 1. for the ping pong case, application should responsible for the descriptor, for example, application should
  * prepare two descriptor table with macro.
  * code
-    //define link descriptor table in application with macro
+    define link descriptor table in application with macro
     DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]);
 
     DMA_SetupDescriptor(nextDesc0,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
@@ -713,16 +845,7 @@ void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descrip
 {
     assert((NULL != handle) && (NULL != descriptor));
 
-    uint32_t instance                   = DMA_GetInstance(handle->base);
-    dma_descriptor_t *channelDescriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]);
-
-    channelDescriptor->xfercfg        = descriptor->xfercfg;
-    channelDescriptor->srcEndAddr     = descriptor->srcEndAddr;
-    channelDescriptor->dstEndAddr     = descriptor->dstEndAddr;
-    channelDescriptor->linkToNextDesc = descriptor->linkToNextDesc;
-
-    /* Set channel XFERCFG register according first channel descriptor. */
-    handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg;
+    DMA_LoadChannelDescriptor(handle->base, handle->channel, descriptor);
 }
 
 /*!
@@ -745,7 +868,7 @@ void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descrip
  required, then application should prepare
  *  three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor.
  * code
-    //define link descriptor table in application with macro
+    define link descriptor table in application with macro
     DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc);
 
     DMA_SetupDescriptor(nextDesc0,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
@@ -764,7 +887,7 @@ void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descrip
  prepare
  *  two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor.
  * code
-    //define link descriptor table in application with macro
+    define link descriptor table in application with macro
     DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc);
 
     DMA_SetupDescriptor(nextDesc0,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
@@ -785,7 +908,8 @@ void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descrip
 status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config)
 {
     assert((NULL != handle) && (NULL != config));
-    assert(handle->channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base));
+    assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1);
+    assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base));
     uint32_t instance            = DMA_GetInstance(handle->base);
     dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]);
 
@@ -801,9 +925,9 @@ status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *c
     DMA_SetupChannelDescriptor(
         descriptor, config->xferCfg, config->srcStartAddr, config->dstStartAddr, config->nextDesc,
         config->trigger == NULL ? kDMA_NoWrap : config->trigger->wrap,
-        (config->trigger == NULL ?
-             kDMA_BurstSize1 :
-             (config->trigger->burst & (DMA_CHANNEL_CFG_BURSTPOWER_MASK)) >> DMA_CHANNEL_CFG_BURSTPOWER_SHIFT));
+        (config->trigger == NULL ? (uint32_t)kDMA_BurstSize1 :
+                                   ((uint32_t)config->trigger->burst & (DMA_CHANNEL_CFG_BURSTPOWER_MASK)) >>
+                                       DMA_CHANNEL_CFG_BURSTPOWER_SHIFT));
 
     /* Set channel XFERCFG register according first channel descriptor. */
     handle->base->CHANNEL[handle->channel].XFERCFG = config->xferCfg;
@@ -828,7 +952,8 @@ status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *c
 status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config)
 {
     assert((NULL != handle) && (NULL != config));
-    assert(handle->channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base));
+    assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1);
+    assert(handle->channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base));
 
     uint32_t instance            = DMA_GetInstance(handle->base);
     dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]);
@@ -867,9 +992,10 @@ status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config)
 void DMA_StartTransfer(dma_handle_t *handle)
 {
     assert(NULL != handle);
+    assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1);
 
     uint32_t channel = handle->channel;
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base));
+    assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base));
 
     /* enable channel */
     DMA_EnableChannel(handle->base, channel);
@@ -884,12 +1010,13 @@ void DMA_StartTransfer(dma_handle_t *handle)
 void DMA_IRQHandle(DMA_Type *base)
 {
     dma_handle_t *handle;
-    int32_t channel_index;
+    uint8_t channel_index;
     uint32_t startChannel = DMA_GetVirtualStartChannel(base);
     uint32_t i            = 0;
+    bool intEnabled = false, intA = false, intB = false;
 
     /* Find channels that have completed transfer */
-    for (i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++)
+    for (i = 0; i < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++)
     {
         handle = s_DMAHandle[i + startChannel];
         /* Handle is not present */
@@ -897,33 +1024,37 @@ void DMA_IRQHandle(DMA_Type *base)
         {
             continue;
         }
-        channel_index = DMA_CHANNEL_INDEX(handle->channel);
+        channel_index = DMA_CHANNEL_INDEX(base, handle->channel);
         /* Channel uses INTA flag */
-        if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1U << channel_index))
+        intEnabled = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTENSET) & (1UL << channel_index)) != 0UL);
+        intA       = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1UL << channel_index)) != 0UL);
+        if (intEnabled && intA)
         {
             /* Clear INTA flag */
-            DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1U << channel_index));
-            if (handle->callback)
+            DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1UL << channel_index));
+            if (handle->callback != NULL)
             {
                 (handle->callback)(handle, handle->userData, true, kDMA_IntA);
             }
         }
+
+        intB = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1UL << channel_index)) != 0UL);
         /* Channel uses INTB flag */
-        if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1U << channel_index))
+        if (intEnabled && intB)
         {
             /* Clear INTB flag */
-            DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1U << channel_index));
-            if (handle->callback)
+            DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1UL << channel_index));
+            if (handle->callback != NULL)
             {
                 (handle->callback)(handle, handle->userData, true, kDMA_IntB);
             }
         }
         /* Error flag */
-        if (DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1U << channel_index))
+        if ((DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1UL << channel_index)) != 0UL)
         {
             /* Clear error flag */
-            DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1U << channel_index));
-            if (handle->callback)
+            DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1UL << channel_index));
+            if (handle->callback != NULL)
             {
                 (handle->callback)(handle, handle->userData, false, kDMA_IntError);
             }
@@ -931,24 +1062,18 @@ void DMA_IRQHandle(DMA_Type *base)
     }
 }
 
+void DMA0_DriverIRQHandler(void);
 void DMA0_DriverIRQHandler(void)
 {
     DMA_IRQHandle(DMA0);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 
 #if defined(DMA1)
+void DMA1_DriverIRQHandler(void);
 void DMA1_DriverIRQHandler(void)
 {
     DMA_IRQHandle(DMA1);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -24,16 +24,16 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief DMA driver version */
-#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */
+#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) /*!< Version 2.4.4. */
 /*@}*/
 
 /*! @brief DMA max transfer size */
-#define DMA_MAX_TRANSFER_COUNT 0x400
+#define DMA_MAX_TRANSFER_COUNT 0x400U
 /*! @brief DMA channel numbers */
 #if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS
 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS
-#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS
-#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT)
+#define FSL_FEATURE_DMA_MAX_CHANNELS           FSL_FEATURE_DMA_NUMBER_OF_CHANNELS
+#define FSL_FEATURE_DMA_ALL_CHANNELS           (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT)
 #endif
 /*! @brief DMA head link descriptor table align size */
 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
@@ -41,25 +41,44 @@
  * To simplify user interface, this macro will help allocate descriptor memory,
  * user just need to provide the name and the number for the allocate descriptor.
  *
- * @param name, allocate decriptor name.
- * @param number, number of descriptor to be allocated.
+ * @param name Allocate decriptor name.
+ * @param number Number of descriptor to be allocated.
  */
 #define DMA_ALLOCATE_HEAD_DESCRIPTORS(name, number) \
     SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE)
+/*! @brief DMA head descriptor table allocate macro at noncacheable section
+ * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section,
+ * user just need to provide the name and the number for the allocate descriptor.
+ *
+ * @param name Allocate decriptor name.
+ * @param number Number of descriptor to be allocated.
+ */
+#define DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE(name, number) \
+    AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE)
 /*! @brief DMA link descriptor table allocate macro
  * To simplify user interface, this macro will help allocate descriptor memory,
  * user just need to provide the name and the number for the allocate descriptor.
  *
- * @param name, allocate decriptor name.
- * @param number, number of descriptor to be allocated.
+ * @param name Allocate decriptor name.
+ * @param number Number of descriptor to be allocated.
  */
 #define DMA_ALLOCATE_LINK_DESCRIPTORS(name, number) \
     SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE)
-
-/* Channel group consists of 32 channels. channel_group = (channel / 32) */
+/*! @brief DMA link descriptor table allocate macro at noncacheable section
+ * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section,
+ * user just need to provide the name and the number for the allocate descriptor.
+ *
+ * @param name Allocate decriptor name.
+ * @param number Number of descriptor to be allocated.
+ */
+#define DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE(name, number) \
+    AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE)
+/*! @brief DMA transfer buffer address need to align with the transfer width */
+#define DMA_ALLOCATE_DATA_TRANSFER_BUFFER(name, width) SDK_ALIGN(name, width)
+/* Channel group consists of 32 channels. channel_group = 0 */
 #define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U)
-/* Channel index in channel group. channel_index = (channel % 32) */
-#define DMA_CHANNEL_INDEX(channel) (((uint8_t)(channel)) & 0x1F)
+/* Channel index in channel group. channel_index = (channel % (channel number per instance)) */
+#define DMA_CHANNEL_INDEX(base, channel) (((uint8_t)(channel)) & 0x1FU)
 /*! @brief DMA linked descriptor address algin size */
 #define DMA_COMMON_REG_GET(base, channel, reg) \
     (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)])
@@ -69,40 +88,41 @@
     (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value))
 
 /*! @brief DMA descriptor end address calculate
- * @param start, start address
- * @param inc, address interleave size
- * @param bytes, transfer bytes
- * @param width, transfer width
+ * @param start start address
+ * @param inc address interleave size
+ * @param bytes transfer bytes
+ * @param width transfer width
  */
-#define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) ((void *)((uint32_t)(start) + inc * bytes - inc * width))
+#define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) \
+    ((uint32_t *)((uint32_t)(start) + (inc) * (bytes) - (inc) * (width)))
 
 /*! @brief DMA channel transfer configurations macro
- * @param reload, true is reload link descriptor after current exhaust, false is not
- * @param clrTrig, true is clear trigger status, wait software trigger, false is not
- * @param intA, enable interruptA
- * @param intB, enable interruptB
- * @param width,transfer width
- * @param srcInc, source address interleave size
- * @param dstInc, destination address interleave size
- * @param bytes, transfer bytes
+ * @param reload true is reload link descriptor after current exhaust, false is not
+ * @param clrTrig true is clear trigger status, wait software trigger, false is not
+ * @param intA enable interruptA
+ * @param intB enable interruptB
+ * @param width transfer width
+ * @param srcInc source address interleave size
+ * @param dstInc destination address interleave size
+ * @param bytes transfer bytes
  */
 #define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes)                                 \
     DMA_CHANNEL_XFERCFG_CFGVALID_MASK | DMA_CHANNEL_XFERCFG_RELOAD(reload) | DMA_CHANNEL_XFERCFG_CLRTRIG(clrTrig) | \
         DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) |                                     \
-        DMA_CHANNEL_XFERCFG_WIDTH(width == 4 ? 2 : (width - 1)) |                                                   \
-        DMA_CHANNEL_XFERCFG_SRCINC(srcInc == 4 ? (srcInc - 1) : srcInc) |                                           \
-        DMA_CHANNEL_XFERCFG_DSTINC(dstInc == 4 ? (dstInc - 1) : dstInc) |                                           \
-        DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1)
+        DMA_CHANNEL_XFERCFG_WIDTH(width == 4UL ? 2UL : (width - 1UL)) |                                             \
+        DMA_CHANNEL_XFERCFG_SRCINC(srcInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (srcInc - 1UL) : srcInc) |   \
+        DMA_CHANNEL_XFERCFG_DSTINC(dstInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (dstInc - 1UL) : dstInc) |   \
+        DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1UL)
 
-/*! @brief DMA transfer status */
-enum _dma_transfer_status
+/*! @brief _dma_transfer_status DMA transfer status */
+enum
 {
     kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the
                                                                 transfer request. */
 };
 
-/*! @brief dma address interleave size */
-enum _dma_addr_interleave_size
+/*! @brief _dma_addr_interleave_size dma address interleave size */
+enum
 {
     kDMA_AddressInterleave0xWidth = 0U, /*!< dma source/destination address no interleave */
     kDMA_AddressInterleave1xWidth = 1U, /*!< dma source/destination address interleave 1xwidth */
@@ -110,8 +130,8 @@ enum _dma_addr_interleave_size
     kDMA_AddressInterleave4xWidth = 4U, /*!< dma source/destination address interleave 3xwidth */
 };
 
-/*! @brief dma transfer width */
-enum _dma_transfer_width
+/*! @brief _dma_transfer_width dma transfer width */
+enum
 {
     kDMA_Transfer8BitWidth  = 1U, /*!< dma channel transfer bit width is 8 bit */
     kDMA_Transfer16BitWidth = 2U, /*!< dma channel transfer bit width is 16 bit */
@@ -177,8 +197,8 @@ typedef enum _dma_trigger_type
         DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */
 } dma_trigger_type_t;
 
-/*! @brief DMA burst size*/
-enum _dma_burst_size
+/*! @brief _dma_burst_size DMA burst size*/
+enum
 {
     kDMA_BurstSize1    = 0U,  /*!< burst size 1 transfer */
     kDMA_BurstSize2    = 1U,  /*!< burst size 2 transfer */
@@ -329,6 +349,7 @@ void DMA_Deinit(DMA_Type *base);
 void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr);
 
 /* @} */
+
 /*!
  * @name DMA Channel Operation
  * @{
@@ -343,8 +364,25 @@ void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr);
  */
 static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
-    return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false;
+    assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) &&
+           (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)));
+
+    return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL;
+}
+
+/*!
+ * @brief Return whether DMA channel is busy
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return True for busy state, false otherwise.
+ */
+static inline bool DMA_ChannelIsBusy(DMA_Type *base, uint32_t channel)
+{
+    assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) &&
+           (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)));
+
+    return (DMA_COMMON_CONST_REG_GET(base, channel, BUSY) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL;
 }
 
 /*!
@@ -355,8 +393,9 @@ static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel)
  */
 static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
-    DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1U << DMA_CHANNEL_INDEX(channel);
+    assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) &&
+           (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)));
+    DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1UL << DMA_CHANNEL_INDEX(base, channel);
 }
 
 /*!
@@ -367,8 +406,9 @@ static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel)
  */
 static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
-    DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1U << DMA_CHANNEL_INDEX(channel);
+    assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) &&
+           (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)));
+    DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel);
 }
 
 /*!
@@ -379,8 +419,9 @@ static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel
  */
 static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
-    DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1U << DMA_CHANNEL_INDEX(channel);
+    assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) &&
+           (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)));
+    DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1UL << DMA_CHANNEL_INDEX(base, channel);
 }
 
 /*!
@@ -391,8 +432,9 @@ static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel)
  */
 static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
-    DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1U << DMA_CHANNEL_INDEX(channel);
+    assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) &&
+           (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)));
+    DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel);
 }
 
 /*!
@@ -403,7 +445,8 @@ static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel)
  */
 static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
+    assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) &&
+           (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)));
     base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
 }
 
@@ -416,7 +459,8 @@ static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel)
  */
 static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
+    assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) &&
+           (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)));
     base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
 }
 
@@ -460,7 +504,8 @@ uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel);
  */
 static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority)
 {
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
+    assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) &&
+           (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)));
     base->CHANNEL[channel].CFG =
         (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority);
 }
@@ -474,13 +519,14 @@ static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_
  */
 static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
-    return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >>
-                            DMA_CHANNEL_CFG_CHPRIORITY_SHIFT);
+    assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) &&
+           (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)));
+    return (dma_priority_t)(uint8_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >>
+                                     DMA_CHANNEL_CFG_CHPRIORITY_SHIFT);
 }
 
 /*!
- * @brief Set channel configuration valid..
+ * @brief Set channel configuration valid.
  *
  * @param base DMA peripheral base address.
  * @param channel DMA channel number.
@@ -560,6 +606,29 @@ void DMA_SetupChannelDescriptor(dma_descriptor_t *desc,
                                 dma_burst_wrap_t wrapType,
                                 uint32_t burstSize);
 
+/*!
+ * @brief load channel transfer decriptor.
+ *
+ * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA
+ * transfer, the head descriptor table is defined in DMA driver, it is useful for the case:
+ * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly
+ * and then call this api to load the configured descriptor to driver descriptor table.
+ * @code
+ *   DMA_Init(DMA0);
+ *   DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL);
+ *   DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL);
+ *   DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc);
+ *   DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL);
+ *   while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL))
+ *   {}
+ * @endcode
+ *
+ * @param base DMA base address.
+ * @param channel DMA channel.
+ * @param descriptor configured DMA descriptor.
+ */
+void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor);
+
 /* @} */
 
 /*!
@@ -681,7 +750,7 @@ status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config)
  required, then application should prepare
  *  three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor.
  * @code
-    //define link descriptor table in application with macro
+    define link descriptor table in application with macro
     DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]);
 
     DMA_SetupDescriptor(nextDesc0,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
@@ -704,7 +773,7 @@ status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config)
  * @param nextDesc address of next descriptor.
  */
 void DMA_SubmitChannelTransferParameter(
-    dma_handle_t *handle, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc);
+    dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc);
 
 /*!
  * @brief Submit channel descriptor.
@@ -716,7 +785,7 @@ void DMA_SubmitChannelTransferParameter(
  * 1. for the ping pong case, application should responsible for the descriptor, for example, application should
  * prepare two descriptor table with macro.
  * @code
-    //define link descriptor table in application with macro
+    define link descriptor table in application with macro
     DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]);
 
     DMA_SetupDescriptor(nextDesc0,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
@@ -754,7 +823,7 @@ void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descrip
  required, then application should prepare
  *  three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor.
  * @code
-    //define link descriptor table in application with macro
+    define link descriptor table in application with macro
     DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc);
     DMA_SetupDescriptor(nextDesc0,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
  srcStartAddr, dstStartAddr, nextDesc1);
@@ -772,7 +841,7 @@ void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descrip
  prepare
  *  two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor.
  * @code
-    //define link descriptor table in application with macro
+    define link descriptor table in application with macro
     DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc);
 
     DMA_SetupDescriptor(nextDesc0,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -18,6 +18,15 @@
 #define FSL_COMPONENT_ID "platform.drivers.flexcomm"
 #endif
 
+/*!
+ * @brief Used for conversion between `void*` and `uint32_t`.
+ */
+typedef union pvoid_to_u32
+{
+    void *pvoid;
+    uint32_t u32;
+} pvoid_to_u32_t;
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -31,18 +40,18 @@ static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T
  * Variables
  ******************************************************************************/
 
+/*! @brief Array to map FLEXCOMM instance number to base address. */
+static const uint32_t s_flexcommBaseAddrs[] = FLEXCOMM_BASE_ADDRS;
+
 /*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
-static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+static flexcomm_irq_handler_t s_flexcommIrqHandler[ARRAY_SIZE(s_flexcommBaseAddrs)];
 
 /*! @brief Pointers to handles for each instance to provide context to interrupt routines */
-static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+static void *s_flexcommHandle[ARRAY_SIZE(s_flexcommBaseAddrs)];
 
 /*! @brief Array to map FLEXCOMM instance number to IRQ number. */
 IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS;
 
-/*! @brief Array to map FLEXCOMM instance number to base address. */
-static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS;
-
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief IDs of clock for each FLEXCOMM module */
 static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;
@@ -66,11 +75,11 @@ static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T
     }
     else if (periph <= FLEXCOMM_PERIPH_I2S_TX)
     {
-        return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > (uint32_t)0 ? true : false;
+        return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false;
     }
     else if (periph == FLEXCOMM_PERIPH_I2S_RX)
     {
-        return (base->PSELID & (1 << 7)) > (uint32_t)0 ? true : false;
+        return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false;
     }
     else
     {
@@ -82,18 +91,20 @@ static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T
 /*! brief Returns instance number for FLEXCOMM module with given base address. */
 uint32_t FLEXCOMM_GetInstance(void *base)
 {
-    int i;
+    uint32_t i;
+    pvoid_to_u32_t BaseAddr;
+    BaseAddr.pvoid = base;
 
-    for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++)
+    for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++)
     {
-        if ((uint32_t)base == s_flexcommBaseAddrs[i])
+        if (BaseAddr.u32 == s_flexcommBaseAddrs[i])
         {
-            return i;
+            break;
         }
     }
 
-    assert(false);
-    return 0;
+    assert(i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT);
+    return i;
 }
 
 /* Changes FLEXCOMM mode */
@@ -106,13 +117,14 @@ static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph
     }
 
     /* Flexcomm is locked to different peripheral type than expected  */
-    if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph))
+    if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) &&
+        ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph))
     {
         return kStatus_Fail;
     }
 
     /* Check if we are asked to lock */
-    if (lock)
+    if (lock != 0)
     {
         base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK;
     }
@@ -127,12 +139,7 @@ static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph
 /*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
 status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph)
 {
-    int idx = FLEXCOMM_GetInstance(base);
-
-    if (idx < 0)
-    {
-        return kStatus_InvalidArgument;
-    }
+    uint32_t idx = FLEXCOMM_GetInstance(base);
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the peripheral clock */
@@ -150,7 +157,7 @@ status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph)
 
 /*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
  * mode */
-void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle)
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle)
 {
     uint32_t instance;
 
@@ -159,242 +166,247 @@ void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *ha
 
     /* Clear handler first to avoid execution of the handler with wrong handle */
     s_flexcommIrqHandler[instance] = NULL;
-    s_flexcommHandle[instance]     = handle;
+    s_flexcommHandle[instance]     = flexcommHandle;
     s_flexcommIrqHandler[instance] = handler;
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 
 /* IRQ handler functions overloading weak symbols in the startup */
 #if defined(FLEXCOMM0)
+void FLEXCOMM0_DriverIRQHandler(void);
 void FLEXCOMM0_DriverIRQHandler(void)
 {
-    assert(s_flexcommIrqHandler[0]);
-    s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM0);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(FLEXCOMM1)
+void FLEXCOMM1_DriverIRQHandler(void);
 void FLEXCOMM1_DriverIRQHandler(void)
 {
-    assert(s_flexcommIrqHandler[1]);
-    s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM1);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(FLEXCOMM2)
+void FLEXCOMM2_DriverIRQHandler(void);
 void FLEXCOMM2_DriverIRQHandler(void)
 {
-    assert(s_flexcommIrqHandler[2]);
-    s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM2);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(FLEXCOMM3)
+void FLEXCOMM3_DriverIRQHandler(void);
 void FLEXCOMM3_DriverIRQHandler(void)
 {
-    assert(s_flexcommIrqHandler[3]);
-    s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM3);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(FLEXCOMM4)
+void FLEXCOMM4_DriverIRQHandler(void);
 void FLEXCOMM4_DriverIRQHandler(void)
 {
-    assert(s_flexcommIrqHandler[4]);
-    s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM4);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 
 #endif
 
 #if defined(FLEXCOMM5)
+void FLEXCOMM5_DriverIRQHandler(void);
 void FLEXCOMM5_DriverIRQHandler(void)
 {
-    assert(s_flexcommIrqHandler[5]);
-    s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM5);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(FLEXCOMM6)
+void FLEXCOMM6_DriverIRQHandler(void);
 void FLEXCOMM6_DriverIRQHandler(void)
 {
-    assert(s_flexcommIrqHandler[6]);
-    s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM6);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(FLEXCOMM7)
+void FLEXCOMM7_DriverIRQHandler(void);
 void FLEXCOMM7_DriverIRQHandler(void)
 {
-    assert(s_flexcommIrqHandler[7]);
-    s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM7);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(FLEXCOMM8)
+void FLEXCOMM8_DriverIRQHandler(void);
 void FLEXCOMM8_DriverIRQHandler(void)
 {
-    assert(s_flexcommIrqHandler[8]);
-    s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM8);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(FLEXCOMM9)
+void FLEXCOMM9_DriverIRQHandler(void);
 void FLEXCOMM9_DriverIRQHandler(void)
 {
-    assert(s_flexcommIrqHandler[9]);
-    s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM9);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(FLEXCOMM10)
+void FLEXCOMM10_DriverIRQHandler(void);
 void FLEXCOMM10_DriverIRQHandler(void)
 {
-    assert(s_flexcommIrqHandler[10]);
-    s_flexcommIrqHandler[10]((void *)s_flexcommBaseAddrs[10], s_flexcommHandle[10]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM10);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(FLEXCOMM11)
+void FLEXCOMM11_DriverIRQHandler(void);
 void FLEXCOMM11_DriverIRQHandler(void)
 {
-    assert(s_flexcommIrqHandler[11]);
-    s_flexcommIrqHandler[11]((void *)s_flexcommBaseAddrs[11], s_flexcommHandle[11]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM11);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(FLEXCOMM12)
+void FLEXCOMM12_DriverIRQHandler(void);
 void FLEXCOMM12_DriverIRQHandler(void)
 {
-    assert(s_flexcommIrqHandler[12]);
-    s_flexcommIrqHandler[12]((void *)s_flexcommBaseAddrs[12], s_flexcommHandle[12]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM12);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(FLEXCOMM13)
+void FLEXCOMM13_DriverIRQHandler(void);
 void FLEXCOMM13_DriverIRQHandler(void)
 {
-    assert(s_flexcommIrqHandler[13]);
-    s_flexcommIrqHandler[13]((void *)s_flexcommBaseAddrs[13], s_flexcommHandle[13]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM13);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(FLEXCOMM14)
+void FLEXCOMM14_DriverIRQHandler(void);
 void FLEXCOMM14_DriverIRQHandler(void)
 {
     uint32_t instance;
 
     /* Look up instance number */
     instance = FLEXCOMM_GetInstance(FLEXCOMM14);
-    assert(s_flexcommIrqHandler[instance]);
-    s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(FLEXCOMM15)
+void FLEXCOMM15_DriverIRQHandler(void);
 void FLEXCOMM15_DriverIRQHandler(void)
 {
     uint32_t instance;
 
     /* Look up instance number */
-    instance = FLEXCOMM_GetInstance(FLEXCOMM14);
-    assert(s_flexcommIrqHandler[instance]);
-    s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    instance = FLEXCOMM_GetInstance(FLEXCOMM15);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(FLEXCOMM16)
+void FLEXCOMM16_DriverIRQHandler(void);
 void FLEXCOMM16_DriverIRQHandler(void)
 {
-    assert(s_flexcommIrqHandler[16]);
-    s_flexcommIrqHandler[16]((void *)s_flexcommBaseAddrs[16], s_flexcommHandle[16]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM16);
+    assert(s_flexcommIrqHandler[instance] != NULL);
+    s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -17,8 +17,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief FlexCOMM driver version 2.0.1. */
-#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*! @brief FlexCOMM driver version 2.0.2. */
+#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
 /*@}*/
 
 /*! @brief FLEXCOMM peripheral modes. */
@@ -53,7 +53,7 @@ status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);
 
 /*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
  * mode */
-void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle);
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle);
 
 #if defined(__cplusplus)
 }

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_fro_calib.h

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2017, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_FRO_CALIB_H_
+#define _FSL_FRO_CALIB_H_
+
+#include "fsl_common.h"
+#include "fsl_device_registers.h"
+#include <stdint.h>
+
+/*!
+ * @addtogroup power
+ * @{
+ */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FRO_CALIB driver version 1.0.0. */
+#define FSL_FRO_CALIB_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
+/*@}*/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.fro_calib"
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Returns the version of the FRO Calibration library */
+unsigned int fro_calib_Get_Lib_Ver(void);
+
+/* ctimer instance */
+/* ctimer clock frquency in KHz */
+void Chip_TIMER_Instance_Freq(CTIMER_Type *base, unsigned int ctimerFreq);
+
+/* USB_SOF_Event */
+/* Application software should be written to make sure the USB_SOF_EVENT() is */
+/* being called with lower interrupt latency for calibration to work properly */
+void USB_SOF_Event(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* _FSL_FRO_CALIB_H_ */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2020 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -124,11 +124,15 @@ void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t
 void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback)
 {
     uint32_t instance;
+    uint32_t combValue;
+    uint32_t trigValue;
 
     instance = GINT_GetInstance(base);
 
-    *comb     = (gint_comb_t)((base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT);
-    *trig     = (gint_trig_t)((base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT);
+    combValue = (base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT;
+    *comb     = (gint_comb_t)combValue;
+    trigValue = (base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT;
+    *trig     = (gint_trig_t)trigValue;
     *callback = s_gintCallback[instance];
 }
 
@@ -193,7 +197,7 @@ void GINT_EnableCallback(GINT_Type *base)
        Clear status and pending interrupt before enabling the irq in NVIC. */
     GINT_ClrStatus(base);
     NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
-    EnableIRQ(s_gintIRQ[instance]);
+    (void)EnableIRQ(s_gintIRQ[instance]);
 }
 
 /*!
@@ -211,7 +215,7 @@ void GINT_DisableCallback(GINT_Type *base)
     uint32_t instance;
 
     instance = GINT_GetInstance(base);
-    DisableIRQ(s_gintIRQ[instance]);
+    (void)DisableIRQ(s_gintIRQ[instance]);
     GINT_ClrStatus(base);
     NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
 }
@@ -248,6 +252,7 @@ void GINT_Deinit(GINT_Type *base)
 
 /* IRQ handler functions overloading weak symbols in the startup */
 #if defined(GINT0)
+void GINT0_DriverIRQHandler(void);
 void GINT0_DriverIRQHandler(void)
 {
     /* Clear interrupt before callback */
@@ -257,15 +262,12 @@ void GINT0_DriverIRQHandler(void)
     {
         s_gintCallback[0]();
     }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(GINT1)
+void GINT1_DriverIRQHandler(void);
 void GINT1_DriverIRQHandler(void)
 {
     /* Clear interrupt before callback */
@@ -275,15 +277,12 @@ void GINT1_DriverIRQHandler(void)
     {
         s_gintCallback[1]();
     }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(GINT2)
+void GINT2_DriverIRQHandler(void);
 void GINT2_DriverIRQHandler(void)
 {
     /* Clear interrupt before callback */
@@ -293,15 +292,12 @@ void GINT2_DriverIRQHandler(void)
     {
         s_gintCallback[2]();
     }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(GINT3)
+void GINT3_DriverIRQHandler(void);
 void GINT3_DriverIRQHandler(void)
 {
     /* Clear interrupt before callback */
@@ -311,15 +307,12 @@ void GINT3_DriverIRQHandler(void)
     {
         s_gintCallback[3]();
     }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(GINT4)
+void GINT4_DriverIRQHandler(void);
 void GINT4_DriverIRQHandler(void)
 {
     /* Clear interrupt before callback */
@@ -329,15 +322,12 @@ void GINT4_DriverIRQHandler(void)
     {
         s_gintCallback[4]();
     }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(GINT5)
+void GINT5_DriverIRQHandler(void);
 void GINT5_DriverIRQHandler(void)
 {
     /* Clear interrupt before callback */
@@ -347,15 +337,12 @@ void GINT5_DriverIRQHandler(void)
     {
         s_gintCallback[5]();
     }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(GINT6)
+void GINT6_DriverIRQHandler(void);
 void GINT6_DriverIRQHandler(void)
 {
     /* Clear interrupt before callback */
@@ -365,15 +352,12 @@ void GINT6_DriverIRQHandler(void)
     {
         s_gintCallback[6]();
     }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
 
 #if defined(GINT7)
+void GINT7_DriverIRQHandler(void);
 void GINT7_DriverIRQHandler(void)
 {
     /* Clear interrupt before callback */
@@ -383,10 +367,6 @@ void GINT7_DriverIRQHandler(void)
     {
         s_gintCallback[7]();
     }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2020 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -24,7 +24,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
+#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */
 /*@}*/
 
 /*! @brief GINT combine inputs type */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2020 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -28,10 +28,27 @@ static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N;
 /*******************************************************************************
  * Prototypes
  ************ ******************************************************************/
+/*!
+ * @brief Enable GPIO port clock.
+ *
+ * @param base   GPIO peripheral base pointer.
+ * @param port   GPIO port number.
+ */
+static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port);
 
 /*******************************************************************************
  * Code
  ******************************************************************************/
+static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    assert(port < ARRAY_SIZE(s_gpioClockName));
+
+    /* Upgate the GPIO clock */
+    CLOCK_EnableClock(s_gpioClockName[port]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
 /*!
  * brief Initializes the GPIO peripheral.
  *
@@ -42,12 +59,8 @@ static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N;
  */
 void GPIO_PortInit(GPIO_Type *base, uint32_t port)
 {
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    assert(port < ARRAY_SIZE(s_gpioClockName));
+    GPIO_EnablePortClock(base, port);
 
-    /* Upgate the GPIO clock */
-    CLOCK_EnableClock(s_gpioClockName[port]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 #if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
     /* Reset the GPIO module */
     RESET_PeripheralReset(s_gpioResets[port]);
@@ -62,13 +75,13 @@ void GPIO_PortInit(GPIO_Type *base, uint32_t port)
  *
  * This is an example to define an input pin or output pin configuration:
  * code
- * // Define a digital input pin configuration,
+ * Define a digital input pin configuration,
  * gpio_pin_config_t config =
  * {
  *   kGPIO_DigitalInput,
  *   0,
  * }
- * //Define a digital output pin configuration,
+ * Define a digital output pin configuration,
  * gpio_pin_config_t config =
  * {
  *   kGPIO_DigitalOutput,
@@ -83,12 +96,14 @@ void GPIO_PortInit(GPIO_Type *base, uint32_t port)
  */
 void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
 {
+    GPIO_EnablePortClock(base, port);
+
     if (config->pinDirection == kGPIO_DigitalInput)
     {
 #if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
-        base->DIRCLR[port] = 1U << pin;
+        base->DIRCLR[port] = 1UL << pin;
 #else
-        base->DIR[port] &= ~(1U << pin);
+        base->DIR[port] &= ~(1UL << pin);
 #endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
     }
     else
@@ -96,24 +111,24 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_c
         /* Set default output value */
         if (config->outputLogic == 0U)
         {
-            base->CLR[port] = (1U << pin);
+            base->CLR[port] = (1UL << pin);
         }
         else
         {
-            base->SET[port] = (1U << pin);
+            base->SET[port] = (1UL << pin);
         }
 /* Set pin direction */
 #if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
-        base->DIRSET[port] = 1U << pin;
+        base->DIRSET[port] = 1UL << pin;
 #else
-        base->DIR[port] |= 1U << pin;
+        base->DIR[port] |= 1UL << pin;
 #endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
     }
 }
 
 #if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
 /*!
- * @brief Configures the gpio pin interrupt.
+ * @brief Set the configuration of pin interrupt.
  *
  * @param base GPIO base pointer.
  * @param port GPIO port number
@@ -122,9 +137,9 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_c
  */
 void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config)
 {
-    base->INTEDG[port] = base->INTEDG[port] | (config->mode << pin);
+    base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin);
 
-    base->INTPOL[port] = base->INTPOL[port] | (config->polarity << pin);
+    base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin);
 }
 
 /*!
@@ -137,11 +152,11 @@ void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gp
  */
 void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
 {
-    if (kGPIO_InterruptA == index)
+    if ((uint32_t)kGPIO_InterruptA == index)
     {
         base->INTENA[port] = base->INTENA[port] | mask;
     }
-    else if (kGPIO_InterruptB == index)
+    else if ((uint32_t)kGPIO_InterruptB == index)
     {
         base->INTENB[port] = base->INTENB[port] | mask;
     }
@@ -161,11 +176,11 @@ void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, u
  */
 void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
 {
-    if (kGPIO_InterruptA == index)
+    if ((uint32_t)kGPIO_InterruptA == index)
     {
         base->INTENA[port] = base->INTENA[port] & ~mask;
     }
-    else if (kGPIO_InterruptB == index)
+    else if ((uint32_t)kGPIO_InterruptB == index)
     {
         base->INTENB[port] = base->INTENB[port] & ~mask;
     }
@@ -186,11 +201,11 @@ void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index,
  */
 void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
 {
-    if (kGPIO_InterruptA == index)
+    if ((uint32_t)kGPIO_InterruptA == index)
     {
         base->INTSTATA[port] = mask;
     }
-    else if (kGPIO_InterruptB == index)
+    else if ((uint32_t)kGPIO_InterruptB == index)
     {
         base->INTSTATB[port] = mask;
     }
@@ -212,11 +227,11 @@ uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t in
 {
     uint32_t status = 0U;
 
-    if (kGPIO_InterruptA == index)
+    if ((uint32_t)kGPIO_InterruptA == index)
     {
         status = base->INTSTATA[port];
     }
-    else if (kGPIO_InterruptB == index)
+    else if ((uint32_t)kGPIO_InterruptB == index)
     {
         status = base->INTSTATB[port];
     }
@@ -225,7 +240,6 @@ uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t in
         /*Should not enter here*/
     }
     return status;
-
 }
 
 /*!
@@ -238,13 +252,13 @@ uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t in
  */
 void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
 {
-    if (kGPIO_InterruptA == index)
+    if ((uint32_t)kGPIO_InterruptA == index)
     {
-        base->INTENA[port] = base->INTENA[port] | (1U << pin);
+        base->INTENA[port] = base->INTENA[port] | (1UL << pin);
     }
-    else if (kGPIO_InterruptB == index)
+    else if ((uint32_t)kGPIO_InterruptB == index)
     {
-        base->INTENB[port] = base->INTENB[port] | (1U << pin);
+        base->INTENB[port] = base->INTENB[port] | (1UL << pin);
     }
     else
     {
@@ -262,13 +276,13 @@ void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint3
  */
 void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
 {
-    if (kGPIO_InterruptA == index)
+    if ((uint32_t)kGPIO_InterruptA == index)
     {
-        base->INTENA[port] = base->INTENA[port] & ~(1U << pin);
+        base->INTENA[port] = base->INTENA[port] & ~(1UL << pin);
     }
-    else if (kGPIO_InterruptB == index)
+    else if ((uint32_t)kGPIO_InterruptB == index)
     {
-        base->INTENB[port] = base->INTENB[port] & ~(1U << pin);
+        base->INTENB[port] = base->INTENB[port] & ~(1UL << pin);
     }
     else
     {
@@ -287,13 +301,13 @@ void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint
  */
 void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
 {
-    if (kGPIO_InterruptA == index)
+    if ((uint32_t)kGPIO_InterruptA == index)
     {
-        base->INTSTATA[port] = 1U << pin;
+        base->INTSTATA[port] = 1UL << pin;
     }
-    else if (kGPIO_InterruptB == index)
+    else if ((uint32_t)kGPIO_InterruptB == index)
     {
-        base->INTSTATB[port] = 1U << pin;
+        base->INTSTATB[port] = 1UL << pin;
     }
     else
     {

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2020 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -24,14 +24,14 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief LPC GPIO driver version 2.1.3. */
-#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
+/*! @brief LPC GPIO driver version. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 7))
 /*@}*/
 
 /*! @brief LPC GPIO direction definition */
 typedef enum _gpio_pin_direction
 {
-    kGPIO_DigitalInput = 0U,  /*!< Set current pin as digital input*/
+    kGPIO_DigitalInput  = 0U, /*!< Set current pin as digital input*/
     kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
 } gpio_pin_direction_t;
 
@@ -50,16 +50,16 @@ typedef struct _gpio_pin_config
 
 #if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT)
 #define GPIO_PIN_INT_LEVEL 0x00U
-#define GPIO_PIN_INT_EDGE 0x01U
+#define GPIO_PIN_INT_EDGE  0x01U
 
 #define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U
-#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U
+#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER  0x01U
 
 /*! @brief GPIO Pin Interrupt enable mode */
 typedef enum _gpio_pin_enable_mode
 {
     kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */
-    kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE    /*!< Generate Pin Interrupt on edge mode */
+    kGPIO_PinIntEnableEdge  = GPIO_PIN_INT_EDGE   /*!< Generate Pin Interrupt on edge mode */
 } gpio_pin_enable_mode_t;
 
 /*! @brief GPIO Pin Interrupt enable polarity */
@@ -81,8 +81,8 @@ typedef enum _gpio_interrupt_index
 /*! @brief Configures the interrupt generation condition. */
 typedef struct _gpio_interrupt_config
 {
-    uint8_t mode;         /* The trigger mode of GPIO interrupts */
-    uint8_t polarity;     /* The polarity of GPIO interrupts */
+    uint8_t mode;     /* The trigger mode of GPIO interrupts */
+    uint8_t polarity; /* The polarity of GPIO interrupts */
 } gpio_interrupt_config_t;
 #endif
 
@@ -90,8 +90,7 @@ typedef struct _gpio_interrupt_config
  * API
  ******************************************************************************/
 #if defined(__cplusplus)
-extern "C"
-{
+extern "C" {
 #endif
 
 /*! @name GPIO Configuration */
@@ -115,13 +114,13 @@ void GPIO_PortInit(GPIO_Type *base, uint32_t port);
  *
  * This is an example to define an input pin or output pin configuration:
  * @code
- * // Define a digital input pin configuration,
+ * Define a digital input pin configuration,
  * gpio_pin_config_t config =
  * {
  *   kGPIO_DigitalInput,
  *   0,
  * }
- * //Define a digital output pin configuration,
+ * Define a digital output pin configuration,
  * gpio_pin_config_t config =
  * {
  *   kGPIO_DigitalOutput,
@@ -269,7 +268,7 @@ static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port)
 
 #if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
 /*!
- * @brief Configures the gpio pin interrupt.
+ * @brief Set the configuration of pin interrupt.
  *
  * @param base GPIO base pointer.
  * @param port GPIO port number

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -26,9 +26,9 @@ enum _hashcrypt_status
  */
 /*! @name Driver version */
 /*@{*/
-/*! @brief HASHCRYPT driver version. Version 2.0.2.
+/*! @brief HASHCRYPT driver version. Version 2.2.5.
  *
- * Current version: 2.0.2
+ * Current version: 2.2.5
  *
  * Change log:
  * - Version 2.0.0
@@ -37,18 +37,55 @@ enum _hashcrypt_status
  *   - Support loading AES key from unaligned address
  * - Version 2.0.2
  *   - Support loading AES key from unaligned address for different compiler and core variants
+ * - Version 2.0.3
+ *   - Remove SHA512 and AES ICB algorithm definitions
+ * - Version 2.0.4
+ *   - Add SHA context switch support
+ * - Version 2.1.0
+ *   - Update the register name and macro to align with new header.
+ * - Version 2.1.1
+ *   - Fix MISRA C-2012.
+ * - Version 2.1.2
+ *   - Support loading AES input data from unaligned address.
+ * - Version 2.1.3
+ *   - Fix MISRA C-2012.
+ * - Version 2.1.4
+ *   - Fix context switch cannot work when switching from AES.
+ * - Version 2.1.5
+ *   - Add data synchronization barriere inside hashcrypt_sha_ldm_stm_16_words()
+ *     to prevent possible optimization issue.
+ * - Version 2.2.0
+ *   - Add AES-OFB and AES-CFB mixed IP/SW modes.
+ * - Version 2.2.1
+ *   - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words()
+ *     prevent compiler from reordering memory write when -O2 or higher is used.
+ * - Version 2.2.2
+ *   - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words()
+ *     to fix optimization issue
+ * - Version 2.2.3
+ *   - Added check for size in hashcrypt_aes_one_block to prevent overflowing COUNT field in MEMCTRL register, if its
+ * bigger than COUNT field do a multiple runs.
+ * - Version 2.2.4
+ *   - In all HASHCRYPT_AES_xx functions have been added setting CTRL_MODE bitfield to 0 after processing data, which
+ * decreases power consumption.
+ * - Version 2.2.5
+ *   - Add data synchronization barrier and instruction  synchronization barrier inside
+ * hashcrypt_sha_process_message_data() to fix optimization issue
  */
-#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 2, 5))
 /*@}*/
 
+/*! @brief Algorithm definitions correspond with the values for Mode field in Control register !*/
+#define HASHCRYPT_MODE_SHA1   0x1
+#define HASHCRYPT_MODE_SHA256 0x2
+#define HASHCRYPT_MODE_AES    0x4
+
 /*! @brief Algorithm used for Hashcrypt operation */
 typedef enum _hashcrypt_algo_t
 {
-    kHASHCRYPT_Sha1   = 1, /*!< SHA_1 */
-    kHASHCRYPT_Sha256 = 2, /*!< SHA_256 */
-    kHASHCRYPT_Sha512 = 3, /*!< SHA_512 */
-    kHASHCRYPT_Aes    = 4, /*!< AES */
-    kHASHCRYPT_AesIcb = 5, /*!< AES_ICB */
+    kHASHCRYPT_Sha1   = HASHCRYPT_MODE_SHA1,   /*!< SHA_1 */
+    kHASHCRYPT_Sha256 = HASHCRYPT_MODE_SHA256, /*!< SHA_256 */
+    kHASHCRYPT_Aes    = HASHCRYPT_MODE_AES,    /*!< AES */
 } hashcrypt_algo_t;
 
 /*! @} */
@@ -63,9 +100,9 @@ typedef enum _hashcrypt_algo_t
  */
 
 /*! AES block size in bytes */
-#define HASHCRYPT_AES_BLOCK_SIZE 16
-#define AES_ENCRYPT 0
-#define AES_DECRYPT 1
+#define HASHCRYPT_AES_BLOCK_SIZE 16U
+#define AES_ENCRYPT              0
+#define AES_DECRYPT              1
 
 /*! @brief AES mode */
 typedef enum _hashcrypt_aes_mode_t
@@ -116,7 +153,11 @@ typedef struct _hashcrypt_handle hashcrypt_handle_t;
  */
 
 /*! @brief HASHCRYPT HASH Context size. */
+#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0)
+#define HASHCRYPT_HASH_CTX_SIZE 30
+#else
 #define HASHCRYPT_HASH_CTX_SIZE 22
+#endif
 
 /*! @brief Storage type used to save hash context. */
 typedef struct _hashcrypt_hash_ctx_t
@@ -287,6 +328,68 @@ status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base,
                                 uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE],
                                 size_t *szLeft);
 
+/*!
+ * @brief Encrypts or decrypts AES using OFB block mode.
+ *
+ * Encrypts or decrypts AES using OFB block mode.
+ * AES OFB mode uses only forward AES cipher and same algorithm for encryption and decryption.
+ * The only difference between encryption and decryption is that, for encryption, the input argument
+ * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text
+ * and the output argument is plain text.
+ *
+ * @param base HASHCRYPT peripheral base address
+ * @param handle Handle used for this request.
+ * @param input Input data for OFB block mode
+ * @param[out] output Output data for OFB block mode
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector to combine with the first input block.
+ * @return Status from encrypt operation
+ */
+
+status_t HASHCRYPT_AES_CryptOfb(HASHCRYPT_Type *base,
+                                hashcrypt_handle_t *handle,
+                                const uint8_t *input,
+                                uint8_t *output,
+                                size_t size,
+                                const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]);
+
+/*!
+ * @brief Encrypts AES using CFB block mode.
+ *
+ * @param base HASHCRYPT peripheral base address
+ * @param handle Handle used for this request.
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @return Status from encrypt operation
+ */
+
+status_t HASHCRYPT_AES_EncryptCfb(HASHCRYPT_Type *base,
+                                  hashcrypt_handle_t *handle,
+                                  const uint8_t *plaintext,
+                                  uint8_t *ciphertext,
+                                  size_t size,
+                                  const uint8_t iv[16]);
+
+/*!
+ * @brief Decrypts AES using CFB block mode.
+ *
+ * @param base HASHCRYPT peripheral base address
+ * @param handle Handle used for this request.
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plaintext text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @return Status from encrypt operation
+ */
+
+status_t HASHCRYPT_AES_DecryptCfb(HASHCRYPT_Type *base,
+                                  hashcrypt_handle_t *handle,
+                                  const uint8_t *ciphertext,
+                                  uint8_t *plaintext,
+                                  size_t size,
+                                  const uint8_t iv[16]);
 /*!
  *@}
  */ /* end of hashcrypt_driver_aes */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2021 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -27,8 +27,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief I2C driver version 2.0.5. */
-#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
+/*! @brief I2C driver version. */
+#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
 /*@}*/
 
 /*! @brief Retry times for waiting flag. */
@@ -36,20 +36,26 @@
 #define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
 #endif
 
+/*! @brief Whether to ignore the nack signal of the last byte during master transmit. */
+#ifndef I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK
+#define I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK \
+    1U /* Define to one means master ignores the last byte's nack and considers the transfer successful. */
+#endif
+
 /* definitions for MSTCODE bits in I2C Status register STAT */
-#define I2C_STAT_MSTCODE_IDLE (0)    /*!< Master Idle State Code */
-#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */
-#define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */
-#define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */
-#define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */
+#define I2C_STAT_MSTCODE_IDLE    (0U) /*!< Master Idle State Code */
+#define I2C_STAT_MSTCODE_RXREADY (1U) /*!< Master Receive Ready State Code */
+#define I2C_STAT_MSTCODE_TXREADY (2U) /*!< Master Transmit Ready State Code */
+#define I2C_STAT_MSTCODE_NACKADR (3U) /*!< Master NACK by slave on address State Code */
+#define I2C_STAT_MSTCODE_NACKDAT (4U) /*!< Master NACK by slave on data State Code */
 
 /* definitions for SLVSTATE bits in I2C Status register STAT */
 #define I2C_STAT_SLVST_ADDR (0)
-#define I2C_STAT_SLVST_RX (1)
-#define I2C_STAT_SLVST_TX (2)
+#define I2C_STAT_SLVST_RX   (1)
+#define I2C_STAT_SLVST_TX   (2)
 
 /*! @brief I2C status return codes. */
-enum _i2c_status
+enum
 {
     kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */
     kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */
@@ -62,33 +68,112 @@ enum _i2c_status
     kStatus_I2C_NoTransferInProgress =
         MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */
     kStatus_I2C_DmaRequestFail  = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */
-    kStatus_I2C_StartStopError  = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8),
-    kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9),
-    kStatus_I2C_Timeout         = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 10), /*!< Timeout poling status flags. */
-    kStatus_I2C_Addr_Nak        = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 11), /*!< NAK received for Address */
+    kStatus_I2C_StartStopError  = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), /*!< Start and stop error. */
+    kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), /*!< Unexpected state. */
+    kStatus_I2C_Timeout =
+        MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C,
+                    10), /*!< Timeout when waiting for I2C master/slave pending status to set to continue transfer. */
+    kStatus_I2C_Addr_Nak      = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 11), /*!< NAK received for Address */
+    kStatus_I2C_EventTimeout  = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 12), /*!< Timeout waiting for bus event. */
+    kStatus_I2C_SclLowTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 13), /*!< Timeout SCL signal remains low. */
 };
 
 /*! @} */
 
 /*!
- * @addtogroup i2c_master_driver
+ * @addtogroup i2c_driver
  * @{
  */
 
 /*!
- * @brief I2C master peripheral flags.
+ * @brief I2C status flags.
  *
  * @note These enums are meant to be OR'd together to form a bit mask.
  */
-enum _i2c_master_flags
+enum _i2c_status_flags
 {
-    kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. */
+    kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 0 */
     kI2C_MasterArbitrationLostFlag =
-        I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */
+        I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus. bit 4*/
     kI2C_MasterStartStopErrorFlag =
-        I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */
+        I2C_STAT_MSTSTSTPERR_MASK,       /*!< There was an error during start or stop phase of the transaction. bit 6 */
+    kI2C_MasterIdleFlag     = 1UL << 5U, /*!< The I2C master idle status. bit 5 */
+    kI2C_MasterRxReadyFlag  = 1UL << I2C_STAT_MSTSTATE_SHIFT,        /*!< The I2C master rx ready status. bit 1 */
+    kI2C_MasterTxReadyFlag  = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 1U), /*!< The I2C master tx ready status. bit 2 */
+    kI2C_MasterAddrNackFlag = 1UL << 7U,                             /*!< The I2C master address nack status. bit 7 */
+    kI2C_MasterDataNackFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 2U), /*!< The I2C master data nack status. bit 3 */
+    kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK,  /*!< The I2C module is waiting for software interaction. bit 8 */
+    kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0
+                                                          = yes, 1 = no). bit 11 */
+    kI2C_SlaveSelected =
+        I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. bit 14 */
+    kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK, /*!< Indicates that slave was previously deselected (deselect event
+                                                     took place, w1c). bit 15 */
+    kI2C_SlaveAddressedFlag     = 1UL << 22U,     /*!< One of the I2C slave's 4 addresses is matched. bit 22 */
+    kI2C_SlaveReceiveFlag       = 1UL << I2C_STAT_SLVSTATE_SHIFT,        /*!< Slave receive data available. bit 9 */
+    kI2C_SlaveTransmitFlag      = 1UL << (I2C_STAT_SLVSTATE_SHIFT + 1U), /*!< Slave data can be transmitted. bit 10 */
+    kI2C_SlaveAddress0MatchFlag = 1UL << 20U,                            /*!< Slave address0 match. bit 20 */
+    kI2C_SlaveAddress1MatchFlag = 1UL << I2C_STAT_SLVIDX_SHIFT,          /*!< Slave address1 match. bit 12 */
+    kI2C_SlaveAddress2MatchFlag = 1UL << (I2C_STAT_SLVIDX_SHIFT + 1U),   /*!< Slave address2 match. bit 13 */
+    kI2C_SlaveAddress3MatchFlag = 1UL << 21U,                            /*!< Slave address3 match. bit 21 */
+    kI2C_MonitorReadyFlag       = I2C_STAT_MONRDY_MASK,                  /*!< The I2C monitor ready interrupt. bit 16 */
+    kI2C_MonitorOverflowFlag    = I2C_STAT_MONOV_MASK,        /*!< The monitor data overrun interrupt. bit 17 */
+    kI2C_MonitorActiveFlag      = I2C_STAT_MONACTIVE_MASK,    /*!< The monitor is active. bit 18 */
+    kI2C_MonitorIdleFlag        = I2C_STAT_MONIDLE_MASK,      /*!< The monitor idle interrupt. bit 19 */
+    kI2C_EventTimeoutFlag       = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. bit 24 */
+    kI2C_SclTimeoutFlag         = I2C_STAT_SCLTIMEOUT_MASK,   /*!< The SCL timeout interrupt. bit 25 */
+
+    /* All master flags that can be cleared by software */
+    kI2C_MasterAllClearFlags = kI2C_MasterArbitrationLostFlag | kI2C_MasterStartStopErrorFlag,
+    /* All slave flags that can be cleared by software */
+    kI2C_SlaveAllClearFlags = kI2C_SaveDeselected,
+    /* All common flags that can be cleared by software */
+    kI2C_CommonAllClearFlags =
+        kI2C_MonitorOverflowFlag | kI2C_MonitorIdleFlag | kI2C_EventTimeoutFlag | kI2C_SclTimeoutFlag,
 };
 
+/*!
+ * @brief I2C interrupt enable.
+ *
+ * @note These enums are meant to be OR'd together to form a bit mask.
+ */
+enum _i2c_interrupt_enable
+{
+    kI2C_MasterPendingInterruptEnable =
+        I2C_STAT_MSTPENDING_MASK, /*!< The I2C master communication pending interrupt. */
+    kI2C_MasterArbitrationLostInterruptEnable =
+        I2C_STAT_MSTARBLOSS_MASK, /*!< The I2C master arbitration lost interrupt. */
+    kI2C_MasterStartStopErrorInterruptEnable =
+        I2C_STAT_MSTSTSTPERR_MASK, /*!< The I2C master start/stop timing error interrupt. */
+    kI2C_SlavePendingInterruptEnable = I2C_STAT_SLVPENDING_MASK, /*!< The I2C slave communication pending interrupt. */
+    kI2C_SlaveNotStretchingInterruptEnable =
+        I2C_STAT_SLVNOTSTR_MASK, /*!< The I2C slave not streching interrupt, deep-sleep mode can be entered only when
+                                    this interrupt occurs. */
+    kI2C_SlaveDeselectedInterruptEnable = I2C_STAT_SLVDESEL_MASK,     /*!< The I2C slave deselection interrupt. */
+    kI2C_MonitorReadyInterruptEnable    = I2C_STAT_MONRDY_MASK,       /*!< The I2C monitor ready interrupt. */
+    kI2C_MonitorOverflowInterruptEnable = I2C_STAT_MONOV_MASK,        /*!< The monitor data overrun interrupt. */
+    kI2C_MonitorIdleInterruptEnable     = I2C_STAT_MONIDLE_MASK,      /*!< The monitor idle interrupt. */
+    kI2C_EventTimeoutInterruptEnable    = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. */
+    kI2C_SclTimeoutInterruptEnable      = I2C_STAT_SCLTIMEOUT_MASK,   /*!< The SCL timeout interrupt. */
+
+    /* All master interrupt sources */
+    kI2C_MasterAllInterruptEnable = kI2C_MasterPendingInterruptEnable | kI2C_MasterArbitrationLostInterruptEnable |
+                                    kI2C_MasterStartStopErrorInterruptEnable,
+    /* All slave interrupt sources */
+    kI2C_SlaveAllInterruptEnable =
+        kI2C_SlavePendingInterruptEnable | kI2C_SlaveNotStretchingInterruptEnable | kI2C_SlaveDeselectedInterruptEnable,
+    /* All common interrupt sources */
+    kI2C_CommonAllInterruptEnable = kI2C_MonitorReadyInterruptEnable | kI2C_MonitorOverflowInterruptEnable |
+                                    kI2C_MonitorIdleInterruptEnable | kI2C_EventTimeoutInterruptEnable |
+                                    kI2C_SclTimeoutInterruptEnable,
+};
+/*! @} */
+
+/*!
+ * @addtogroup i2c_master_driver
+ * @{
+ */
+
 /*! @brief Direction of master and slave transfers. */
 typedef enum _i2c_direction
 {
@@ -110,6 +195,7 @@ typedef struct _i2c_master_config
     bool enableMaster;     /*!< Whether to enable master mode. */
     uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */
     bool enableTimeout;    /*!< Enable internal timeout function. */
+    uint8_t timeout_Ms;    /*!< Event timeout and SCL low timeout value. */
 } i2c_master_config_t;
 
 /* Forward declaration of the transfer descriptor and handle typedefs. */
@@ -154,6 +240,7 @@ enum _i2c_transfer_states
     kIdleState = 0,
     kTransmitSubaddrState,
     kTransmitDataState,
+    kReceiveDataBeginState,
     kReceiveDataState,
     kReceiveLastDataState,
     kStartState,
@@ -170,7 +257,7 @@ struct _i2c_master_transfer
 {
     uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available
                        options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */
-    uint16_t slaveAddress;     /*!< The 7-bit slave address. */
+    uint8_t slaveAddress;      /*!< The 7-bit slave address. */
     i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */
     uint32_t subaddress;       /*!< Sub address. Transferred MSB first. */
     size_t subaddressSize;     /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */
@@ -190,7 +277,8 @@ struct _i2c_master_handle
     uint8_t *buf;            /*!< Buffer pointer for current state. */
     uint32_t remainingSubaddr;
     uint8_t subaddrBuf[4];
-    i2c_master_transfer_t transfer;                    /*!< Copy of the current transfer info. */
+    bool checkAddrNack;             /*!< Whether to check the nack signal is detected during addressing. */
+    i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */
     i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */
     void *userData;                                    /*!< Application data passed to callback. */
 };
@@ -201,22 +289,6 @@ struct _i2c_master_handle
  * @addtogroup i2c_slave_driver
  * @{
  */
-
-/*!
- * @brief I2C slave peripheral flags.
- *
- * @note These enums are meant to be OR'd together to form a bit mask.
- */
-enum _i2c_slave_flags
-{
-    kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. */
-    kI2C_SlaveNotStretching =
-        I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */
-    kI2C_SlaveSelected = I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. */
-    kI2C_SaveDeselected =
-        I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */
-};
-
 /*! @brief I2C slave address register. */
 typedef enum _i2c_slave_address_register
 {
@@ -359,6 +431,11 @@ struct _i2c_slave_handle
     void *userData;                         /*!< Callback parameter passed to callback. */
 };
 
+/*! @brief Typedef for master interrupt handler. */
+typedef void (*flexcomm_i2c_master_irq_handler_t)(I2C_Type *base, i2c_master_handle_t *handle);
+
+/*! @brief Typedef for slave interrupt handler. */
+typedef void (*flexcomm_i2c_slave_irq_handler_t)(I2C_Type *base, i2c_slave_handle_t *handle);
 /*! @} */
 
 /*******************************************************************************
@@ -451,11 +528,11 @@ static inline void I2C_MasterEnable(I2C_Type *base, bool enable)
 {
     if (enable)
     {
-        base->CFG = (base->CFG & I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK;
+        base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK;
     }
     else
     {
-        base->CFG = (base->CFG & I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK;
+        base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK;
     }
 }
 
@@ -463,7 +540,6 @@ static inline void I2C_MasterEnable(I2C_Type *base, bool enable)
 
 /*! @name Status */
 /*@{*/
-
 /*!
  * @brief Gets the I2C status flags.
  *
@@ -474,16 +550,33 @@ static inline void I2C_MasterEnable(I2C_Type *base, bool enable)
  * @return State of the status flags:
  *         - 1: related status flag is set.
  *         - 0: related status flag is not set.
- * @see _i2c_master_flags
+ * @see @ref _i2c_status_flags.
  */
-static inline uint32_t I2C_GetStatusFlags(I2C_Type *base)
+uint32_t I2C_GetStatusFlags(I2C_Type *base);
+
+/*!
+ * @brief Clears the I2C status flag state.
+ *
+ * Refer to kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags to see
+ * the clearable flags. Attempts to clear other flags has no effect.
+ *
+ * @param base The I2C peripheral base address.
+ * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of the members in
+ *  kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags. You may pass
+ *  the result of a previous call to I2C_GetStatusFlags().
+ * @see #_i2c_status_flags, _i2c_master_status_flags and _i2c_slave_status_flags.
+ */
+static inline void I2C_ClearStatusFlags(I2C_Type *base, uint32_t statusMask)
 {
-    return base->STAT;
+    /* Only deal with the clearable flags */
+    statusMask &=
+        ((uint32_t)kI2C_CommonAllClearFlags | (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_SlaveAllClearFlags);
+    base->STAT = statusMask;
 }
 
 /*!
  * @brief Clears the I2C master status flag state.
- *
+ * @deprecated Do not use this function. It has been superceded by @ref I2C_ClearStatusFlags
  * The following status register flags can be cleared:
  * - #kI2C_MasterArbitrationLostFlag
  * - #kI2C_MasterStartStopErrorFlag
@@ -492,9 +585,9 @@ static inline uint32_t I2C_GetStatusFlags(I2C_Type *base)
  *
  * @param base The I2C peripheral base address.
  * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of
- *  #_i2c_master_flags enumerators OR'd together. You may pass the result of a previous call to
+ *  #_i2c_status_flags enumerators OR'd together. You may pass the result of a previous call to
  *  I2C_GetStatusFlags().
- * @see _i2c_master_flags.
+ * @see _i2c_status_flags.
  */
 static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask)
 {
@@ -508,10 +601,10 @@ static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMas
 /*@{*/
 
 /*!
- * @brief Enables the I2C master interrupt requests.
+ * @brief Enables the I2C interrupt requests.
  *
  * @param base The I2C peripheral base address.
- * @param interruptMask Bit mask of interrupts to enable. See #_i2c_master_flags for the set
+ * @param interruptMask Bit mask of interrupts to enable. See #_i2c_interrupt_enable for the set
  *      of constants that should be OR'd together to form the bit mask.
  */
 static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask)
@@ -520,10 +613,10 @@ static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask)
 }
 
 /*!
- * @brief Disables the I2C master interrupt requests.
+ * @brief Disables the I2C interrupt requests.
  *
  * @param base The I2C peripheral base address.
- * @param interruptMask Bit mask of interrupts to disable. See #_i2c_master_flags for the set
+ * @param interruptMask Bit mask of interrupts to disable. See #_i2c_interrupt_enable for the set
  *      of constants that should be OR'd together to form the bit mask.
  */
 static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask)
@@ -532,10 +625,10 @@ static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask)
 }
 
 /*!
- * @brief Returns the set of currently enabled I2C master interrupt requests.
+ * @brief Returns the set of currently enabled I2C interrupt requests.
  *
  * @param base The I2C peripheral base address.
- * @return A bitmask composed of #_i2c_master_flags enumerators OR'd together to indicate the
+ * @return A bitmask composed of #_i2c_interrupt_enable enumerators OR'd together to indicate the
  *      set of enabled interrupts.
  */
 static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base)
@@ -560,6 +653,18 @@ static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base)
  */
 void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
 
+/*!
+ * @brief Sets the I2C bus timeout value.
+ *
+ * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or
+ * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module.
+ *
+ * @param base The I2C peripheral base address.
+ * @param timeout_Ms Timeout value in millisecond.
+ * @param srcClock_Hz I2C functional clock frequency in Hertz.
+ */
+void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz);
+
 /*!
  * @brief Returns whether the bus is idle.
  *
@@ -658,6 +763,7 @@ status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uin
  * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
  * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
  * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
+ * @retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing.
  */
 status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer);
 
@@ -835,7 +941,7 @@ static inline void I2C_SlaveEnable(I2C_Type *base, bool enable)
  *
  * @param base The I2C peripheral base address.
  * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of
- *  #_i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to
+ *  _i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to
  *  I2C_SlaveGetStatusFlags().
  * @see _i2c_slave_flags.
  */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2020 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -25,6 +25,15 @@ typedef struct _i2c_master_dma_private_handle
     i2c_master_dma_handle_t *handle;
 } i2c_master_dma_private_handle_t;
 
+/*!
+ * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_i2c_dma_master_irq_handler_t`
+ */
+typedef union i2c_dma_to_flexcomm
+{
+    flexcomm_i2c_dma_master_irq_handler_t i2c_dma_master_handler;
+    flexcomm_irq_handler_t flexcomm_handler;
+} i2c_dma_to_flexcomm_t;
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -35,7 +44,7 @@ typedef struct _i2c_master_dma_private_handle
  * @param handle DMA handler for I2C master DMA driver
  * @param userData user param passed to the callback function
  */
-static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData);
+static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode);
 
 /*!
  * @brief Set up master transfer, send slave address and sub address(if any), wait until the
@@ -49,24 +58,30 @@ static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
                                                 i2c_master_dma_handle_t *handle,
                                                 i2c_master_transfer_t *xfer);
 
+static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle);
+
+/*!
+ * @brief Execute states until the transfer is done.
+ * @param handle Master nonblocking driver handle.
+ * @param[out] isDone Set to true if the transfer has completed.
+ * @retval #kStatus_Success
+ * @retval #kStatus_I2C_ArbitrationLost
+ * @retval #kStatus_I2C_Nak
+ */
+static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone);
 /*******************************************************************************
  * Variables
  ******************************************************************************/
 
-/*<! Private handle only used for internally. */
-static i2c_master_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_I2C_COUNT];
-
 /*! @brief IRQ name array */
 static const IRQn_Type s_i2cIRQ[] = I2C_IRQS;
 
+/*<! Private handle only used for internally. */
+static i2c_master_dma_private_handle_t s_dmaPrivateHandle[ARRAY_SIZE(s_i2cIRQ)];
+
 /*******************************************************************************
  * Codes
  ******************************************************************************/
-
-/*!
- * @brief Prepares the transfer state machine and fills in the command buffer.
- * @param handle Master nonblocking driver handle.
- */
 static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
                                                 i2c_master_dma_handle_t *handle,
                                                 i2c_master_transfer_t *xfer)
@@ -76,25 +91,26 @@ static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
     handle->transfer = *xfer;
     transfer         = &(handle->transfer);
 
-    handle->transferCount     = 0;
-    handle->remainingBytesDMA = 0;
+    handle->transferCount     = 0U;
+    handle->remainingBytesDMA = 0U;
     handle->buf               = (uint8_t *)transfer->data;
-    handle->remainingSubaddr  = 0;
+    handle->remainingSubaddr  = 0U;
 
-    if (transfer->flags & kI2C_TransferNoStartFlag)
+    if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U)
     {
-        /* Start condition shall be ommited, switch directly to next phase */
-        if (transfer->dataSize == 0)
+        handle->checkAddrNack = false;
+        /* Start condition shall not be ommited, switch directly to next phase */
+        if (transfer->dataSize == 0U)
         {
-            handle->state = kStopState;
+            handle->state = (uint8_t)kStopState;
         }
         else if (handle->transfer.direction == kI2C_Write)
         {
-            handle->state = xfer->dataSize = kTransmitDataState;
+            handle->state = (uint8_t)kTransmitDataState;
         }
         else if (handle->transfer.direction == kI2C_Read)
         {
-            handle->state = (xfer->dataSize == 1) ? kReceiveLastDataState : kReceiveDataState;
+            handle->state = (xfer->dataSize == 1U) ? (uint8_t)kReceiveLastDataState : (uint8_t)kReceiveDataState;
         }
         else
         {
@@ -103,7 +119,7 @@ static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
     }
     else
     {
-        if (transfer->subaddressSize != 0)
+        if (transfer->subaddressSize != 0U)
         {
             int i;
             uint32_t subaddress;
@@ -115,15 +131,16 @@ static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
 
             /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */
             subaddress = xfer->subaddress;
-            for (i = xfer->subaddressSize - 1; i >= 0; i--)
+            for (i = (int)xfer->subaddressSize - 1; i >= 0; i--)
             {
-                handle->subaddrBuf[i] = subaddress & 0xff;
+                handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU;
                 subaddress >>= 8;
             }
             handle->remainingSubaddr = transfer->subaddressSize;
         }
 
-        handle->state = kStartState;
+        handle->state         = (uint8_t)kStartState;
+        handle->checkAddrNack = true;
     }
 
     return kStatus_Success;
@@ -131,14 +148,18 @@ static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
 
 static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle)
 {
-    int transfer_size;
+    uint32_t transfer_size;
     dma_transfer_config_t xferConfig;
+    uint32_t address;
+    address = (uint32_t)&base->MSTDAT;
 
     /* Update transfer count */
-    handle->transferCount = handle->buf - (uint8_t *)handle->transfer.data;
+    int32_t count = handle->buf - (uint8_t *)handle->transfer.data;
+    assert(count >= 0);
+    handle->transferCount = (uint32_t)count;
 
     /* Check if there is anything to be transferred at all */
-    if (handle->remainingBytesDMA == 0)
+    if (handle->remainingBytesDMA == 0U)
     {
         /* No data to be transferrred, disable DMA */
         base->MSTCTL = 0;
@@ -147,20 +168,20 @@ static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle)
 
     /* Calculate transfer size */
     transfer_size = handle->remainingBytesDMA;
-    if (transfer_size > I2C_MAX_DMA_TRANSFER_COUNT)
+    if (transfer_size > (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT)
     {
-        transfer_size = I2C_MAX_DMA_TRANSFER_COUNT;
+        transfer_size = (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT;
     }
 
     switch (handle->transfer.direction)
     {
         case kI2C_Write:
-            DMA_PrepareTransfer(&xferConfig, handle->buf, (void *)&base->MSTDAT, sizeof(uint8_t), transfer_size,
+            DMA_PrepareTransfer(&xferConfig, handle->buf, (uint32_t *)address, sizeof(uint8_t), transfer_size,
                                 kDMA_MemoryToPeripheral, NULL);
             break;
 
         case kI2C_Read:
-            DMA_PrepareTransfer(&xferConfig, (void *)&base->MSTDAT, handle->buf, sizeof(uint8_t), transfer_size,
+            DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, handle->buf, sizeof(uint8_t), transfer_size,
                                 kDMA_PeripheralToMemory, NULL);
             break;
 
@@ -170,21 +191,14 @@ static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle)
             break;
     }
 
-    DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+    (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
     DMA_StartTransfer(handle->dmaHandle);
 
     handle->remainingBytesDMA -= transfer_size;
     handle->buf += transfer_size;
+    handle->checkAddrNack = false;
 }
 
-/*!
- * @brief Execute states until the transfer is done.
- * @param handle Master nonblocking driver handle.
- * @param[out] isDone Set to true if the transfer has completed.
- * @retval #kStatus_Success
- * @retval #kStatus_I2C_ArbitrationLost
- * @retval #kStatus_I2C_Nak
- */
 static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone)
 {
     uint32_t status;
@@ -192,7 +206,9 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha
     struct _i2c_master_transfer *transfer;
     dma_transfer_config_t xferConfig;
     status_t err;
-    uint32_t start_flag = 0;
+    uint32_t start_flag = 0U;
+    uint32_t address;
+    address = (uint32_t)&base->MSTDAT;
 
     transfer = &(handle->transfer);
 
@@ -200,7 +216,7 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha
 
     status = I2C_GetStatusFlags(base);
 
-    if (status & I2C_STAT_MSTARBLOSS_MASK)
+    if ((status & (uint32_t)I2C_STAT_MSTARBLOSS_MASK) != 0U)
     {
         I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK);
         DMA_AbortTransfer(handle->dmaHandle);
@@ -208,7 +224,7 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha
         return kStatus_I2C_ArbitrationLost;
     }
 
-    if (status & I2C_STAT_MSTSTSTPERR_MASK)
+    if ((status & (uint32_t)I2C_STAT_MSTSTSTPERR_MASK) != 0U)
     {
         I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK);
         DMA_AbortTransfer(handle->dmaHandle);
@@ -216,62 +232,90 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha
         return kStatus_I2C_StartStopError;
     }
 
-    if ((status & I2C_STAT_MSTPENDING_MASK) == 0)
+    /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT
+       register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens
+       before, the timeout status can be used to avoid the transfer hangs indefinitely. */
+    if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U)
+    {
+        I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag);
+        DMA_AbortTransfer(handle->dmaHandle);
+        base->MSTCTL = 0;
+        return kStatus_I2C_EventTimeout;
+    }
+
+    /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time
+       specified by TIMEOUT register. */
+    if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U)
+    {
+        I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag);
+        DMA_AbortTransfer(handle->dmaHandle);
+        base->MSTCTL = 0;
+        return kStatus_I2C_SclLowTimeout;
+    }
+
+    if ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U)
     {
         return kStatus_I2C_Busy;
     }
 
     /* Get the state of the I2C module */
-    master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+    master_state = (base->STAT & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
 
-    if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT))
+    if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT))
     {
         /* Slave NACKed last byte, issue stop and return error */
         DMA_AbortTransfer(handle->dmaHandle);
         base->MSTCTL  = I2C_MSTCTL_MSTSTOP_MASK;
-        handle->state = kWaitForCompletionState;
-        return kStatus_I2C_Nak;
+        handle->state = (uint8_t)kWaitForCompletionState;
+        if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack == true))
+        {
+            return kStatus_I2C_Addr_Nak;
+        }
+        else
+        {
+            return kStatus_I2C_Nak;
+        }
     }
 
     err = kStatus_Success;
 
-    if (handle->state == kStartState)
+    if (handle->state == (uint8_t)kStartState)
     {
         /* set start flag for later use */
         start_flag = I2C_MSTCTL_MSTSTART_MASK;
 
-        if (handle->remainingSubaddr)
+        if (handle->remainingSubaddr != 0U)
         {
             base->MSTDAT  = (uint32_t)transfer->slaveAddress << 1;
-            handle->state = kTransmitSubaddrState;
+            handle->state = (uint8_t)kTransmitSubaddrState;
         }
         else if (transfer->direction == kI2C_Write)
         {
             base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
-            if (transfer->dataSize == 0)
+            if (transfer->dataSize == 0U)
             {
                 /* No data to be transferred, initiate start and schedule stop */
                 base->MSTCTL  = I2C_MSTCTL_MSTSTART_MASK;
-                handle->state = kStopState;
+                handle->state = (uint8_t)kStopState;
                 return err;
             }
-            handle->state = kTransmitDataState;
+            handle->state = (uint8_t)kTransmitDataState;
         }
-        else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0))
+        else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0U))
         {
             base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u;
-            if (transfer->dataSize == 1)
+            if (transfer->dataSize == 1U)
             {
                 /* The very last byte is always received by means of SW */
                 base->MSTCTL  = I2C_MSTCTL_MSTSTART_MASK;
-                handle->state = kReceiveLastDataState;
+                handle->state = (uint8_t)kReceiveLastDataState;
                 return err;
             }
-            handle->state = kReceiveDataState;
+            handle->state = (uint8_t)kReceiveDataState;
         }
         else
         {
-            handle->state = kIdleState;
+            handle->state = (uint8_t)kIdleState;
             err           = kStatus_I2C_UnexpectedState;
             return err;
         }
@@ -279,8 +323,8 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha
 
     switch (handle->state)
     {
-        case kTransmitSubaddrState:
-            if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag))
+        case (uint8_t)kTransmitSubaddrState:
+            if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag))
             {
                 return kStatus_I2C_UnexpectedState;
             }
@@ -288,26 +332,26 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha
             base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
 
             /* Prepare and submit DMA transfer. */
-            DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (void *)&base->MSTDAT, sizeof(uint8_t),
+            DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (uint32_t *)address, sizeof(uint8_t),
                                 handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL);
-            DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+            (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
             DMA_StartTransfer(handle->dmaHandle);
             handle->remainingSubaddr = 0;
-            if (transfer->dataSize)
+            if (transfer->dataSize != 0U)
             {
                 /* There is data to be transferred, if there is write to read turnaround it is necessary to perform
                  * repeated start */
-                handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState;
+                handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState;
             }
             else
             {
                 /* No more data, schedule stop condition */
-                handle->state = kStopState;
+                handle->state = (uint8_t)kStopState;
             }
             break;
 
-        case kTransmitDataState:
-            if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag))
+        case (uint8_t)kTransmitDataState:
+            if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag))
             {
                 return kStatus_I2C_UnexpectedState;
             }
@@ -318,58 +362,71 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha
             I2C_RunDMATransfer(base, handle);
 
             /* Schedule stop condition */
-            handle->state = kStopState;
+            handle->state         = (uint8_t)kStopState;
+            handle->checkAddrNack = false;
             break;
 
-        case kReceiveDataState:
-            if ((master_state != I2C_STAT_MSTCODE_RXREADY) && (!start_flag))
+        case (uint8_t)kReceiveDataState:
+            if ((master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) && (0U == start_flag))
             {
-                return kStatus_I2C_UnexpectedState;
+                if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStartFlag))
+                {
+                    return kStatus_I2C_UnexpectedState;
+                }
             }
 
             base->MSTCTL              = start_flag | I2C_MSTCTL_MSTDMA_MASK;
-            handle->remainingBytesDMA = handle->transfer.dataSize - 1;
+            handle->remainingBytesDMA = handle->transfer.dataSize - 1U;
 
+            if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U)
+            {
+                /* Read the master data register to avoid the data be read again */
+                (void)base->MSTDAT;
+            }
             I2C_RunDMATransfer(base, handle);
 
             /* Schedule reception of last data byte */
-            handle->state = kReceiveLastDataState;
+            handle->state         = (uint8_t)kReceiveLastDataState;
+            handle->checkAddrNack = false;
             break;
 
-        case kReceiveLastDataState:
-            if (master_state != I2C_STAT_MSTCODE_RXREADY)
+        case (uint8_t)kReceiveLastDataState:
+            if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY)
             {
                 return kStatus_I2C_UnexpectedState;
             }
 
-            ((uint8_t *)transfer->data)[transfer->dataSize - 1] = base->MSTDAT;
+            ((uint8_t *)transfer->data)[transfer->dataSize - 1U] = (uint8_t)base->MSTDAT;
             handle->transferCount++;
 
             /* No more data expected, issue NACK and STOP right away */
-            base->MSTCTL  = I2C_MSTCTL_MSTSTOP_MASK;
-            handle->state = kWaitForCompletionState;
+            if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag))
+            {
+                base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+            }
+            handle->state = (uint8_t)kWaitForCompletionState;
             break;
 
-        case kStopState:
-            if (transfer->flags & kI2C_TransferNoStopFlag)
+        case (uint8_t)kStopState:
+            if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U)
             {
                 /* Stop condition is omitted, we are done */
                 *isDone       = true;
-                handle->state = kIdleState;
+                handle->state = (uint8_t)kIdleState;
                 break;
             }
             /* Send stop condition */
             base->MSTCTL  = I2C_MSTCTL_MSTSTOP_MASK;
-            handle->state = kWaitForCompletionState;
+            handle->state = (uint8_t)kWaitForCompletionState;
             break;
 
-        case kWaitForCompletionState:
+        case (uint8_t)kWaitForCompletionState:
             *isDone       = true;
-            handle->state = kIdleState;
+            handle->state = (uint8_t)kIdleState;
             break;
 
-        case kStartState:
-        case kIdleState:
+        case (uint8_t)kStartState:
+        case (uint8_t)kIdleState:
         default:
             /* State machine shall not be invoked again once it enters the idle state */
             err = kStatus_I2C_UnexpectedState;
@@ -379,39 +436,42 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha
     return err;
 }
 
-void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle)
+static void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle)
 {
     bool isDone;
     status_t result;
 
     /* Don't do anything if we don't have a valid handle. */
-    if (!handle)
+    if (NULL == handle)
     {
         return;
     }
 
     result = I2C_RunTransferStateMachineDMA(base, handle, &isDone);
 
-    if (isDone || (result != kStatus_Success))
+    if ((result != kStatus_Success) || isDone)
     {
+        /* Restore handle to idle state. */
+        handle->state = (uint8_t)kIdleState;
+
         /* Disable internal IRQ enables. */
-        I2C_DisableInterrupts(base,
-                              I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
+        I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK |
+                                        I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK);
 
         /* Invoke callback. */
-        if (handle->completionCallback)
+        if (handle->completionCallback != NULL)
         {
             handle->completionCallback(base, handle, result, handle->userData);
         }
     }
 }
 
-static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData)
+static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode)
 {
     i2c_master_dma_private_handle_t *dmaPrivateHandle;
 
     /* Don't do anything if we don't have a valid handle. */
-    if (!handle)
+    if (NULL == handle)
     {
         return;
     }
@@ -435,13 +495,15 @@ void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
                                        void *userData,
                                        dma_handle_t *dmaHandle)
 {
-    uint32_t instance;
+    assert(handle != NULL);
+    assert(dmaHandle != NULL);
 
-    assert(handle);
-    assert(dmaHandle);
+    uint32_t instance;
+    i2c_dma_to_flexcomm_t handler;
+    handler.i2c_dma_master_handler = I2C_MasterTransferDMAHandleIRQ;
 
     /* Zero handle. */
-    memset(handle, 0, sizeof(*handle));
+    (void)memset(handle, 0, sizeof(*handle));
 
     /* Look up instance number */
     instance = I2C_GetInstance(base);
@@ -450,12 +512,12 @@ void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
     handle->completionCallback = callback;
     handle->userData           = userData;
 
-    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_MasterTransferDMAHandleIRQ, handle);
+    FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle);
 
     /* Clear internal IRQ enables and enable NVIC IRQ. */
-    I2C_DisableInterrupts(base,
-                          I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
-    EnableIRQ(s_i2cIRQ[instance]);
+    I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK |
+                                    I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK);
+    (void)EnableIRQ(s_i2cIRQ[instance]);
 
     /* Set the handle for DMA. */
     handle->dmaHandle = dmaHandle;
@@ -463,7 +525,7 @@ void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
     s_dmaPrivateHandle[instance].base   = base;
     s_dmaPrivateHandle[instance].handle = handle;
 
-    DMA_SetCallback(dmaHandle, (dma_callback)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]);
+    DMA_SetCallback(dmaHandle, I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]);
 }
 
 /*!
@@ -482,12 +544,12 @@ status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle,
 {
     status_t result;
 
-    assert(handle);
-    assert(xfer);
+    assert(handle != NULL);
+    assert(xfer != NULL);
     assert(xfer->subaddressSize <= sizeof(xfer->subaddress));
 
     /* Return busy if another transaction is in progress. */
-    if (handle->state != kIdleState)
+    if (handle->state != (uint8_t)kIdleState)
     {
         return kStatus_I2C_Busy;
     }
@@ -499,8 +561,10 @@ status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle,
     I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
 
     /* Enable I2C internal IRQ sources */
-    I2C_EnableInterrupts(base,
-                         I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_MSTPENDING_MASK);
+    /* Enable arbitration lost interrupt, start/stop error interrupt and master pending interrupt.
+       The master pending flag is not set during dma transfer. */
+    I2C_EnableInterrupts(base, I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK |
+                                   I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK);
 
     return result;
 }
@@ -514,15 +578,15 @@ status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle,
  */
 status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count)
 {
-    assert(handle);
+    assert(handle != NULL);
 
-    if (!count)
+    if (NULL == count)
     {
         return kStatus_InvalidArgument;
     }
 
     /* Catch when there is not an active transfer. */
-    if (handle->state == kIdleState)
+    if (handle->state == (uint8_t)kIdleState)
     {
         *count = 0;
         return kStatus_NoTransferInProgress;
@@ -544,7 +608,7 @@ void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle)
     uint32_t status;
     uint32_t master_state;
 
-    if (handle->state != kIdleState)
+    if (handle->state != (uint8_t)kIdleState)
     {
         DMA_AbortTransfer(handle->dmaHandle);
 
@@ -552,22 +616,22 @@ void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle)
         base->MSTCTL = 0;
 
         /* Disable internal IRQ enables. */
-        I2C_DisableInterrupts(base,
-                              I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
+        I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK |
+                                        I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK);
 
         /* Wait until module is ready */
         do
         {
             status = I2C_GetStatusFlags(base);
-        } while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
+        } while ((status & (uint8_t)I2C_STAT_MSTPENDING_MASK) == 0U);
 
         /* Clear controller state. */
         I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
 
         /* Get the state of the I2C module */
-        master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+        master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
 
-        if (master_state != I2C_STAT_MSTCODE_IDLE)
+        if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE)
         {
             /* Send a stop command to finalize the transfer. */
             base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
@@ -576,13 +640,13 @@ void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle)
             do
             {
                 status = I2C_GetStatusFlags(base);
-            } while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
+            } while ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U);
 
             /* Clear controller state. */
             I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
         }
 
         /* Reset the state to idle. */
-        handle->state = kIdleState;
+        handle->state = (uint8_t)kIdleState;
     }
 }

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2021 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -22,8 +22,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief I2C DMA driver version 2.0.3. */
-#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
+/*! @brief I2C DMA driver version. */
+#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
 /*@}*/
 
 /*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */
@@ -38,6 +38,9 @@ typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base,
                                                    status_t status,
                                                    void *userData);
 
+/*! @brief Typedef for master dma handler. */
+typedef void (*flexcomm_i2c_dma_master_irq_handler_t)(I2C_Type *base, i2c_master_dma_handle_t *handle);
+
 /*! @brief I2C master dma transfer structure. */
 struct _i2c_master_dma_handle
 {
@@ -47,8 +50,9 @@ struct _i2c_master_dma_handle
     uint8_t *buf;               /*!< Buffer pointer for current state. */
     uint32_t remainingSubaddr;
     uint8_t subaddrBuf[4];
-    dma_handle_t *dmaHandle;                               /*!< The DMA handler used. */
-    i2c_master_transfer_t transfer;                        /*!< Copy of the current transfer info. */
+    bool checkAddrNack;             /*!< Whether to check the nack signal is detected during addressing. */
+    dma_handle_t *dmaHandle;        /*!< The DMA handler used. */
+    i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */
     i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */
     void *userData;                                        /*!< Callback parameter passed to callback function. */
 };

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_freertos.c

@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_i2c_freertos.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_freertos"
+#endif
+
+static void I2C_RTOS_Callback(I2C_Type *base, i2c_master_handle_t *drv_handle, status_t status, void *userData)
+{
+    i2c_rtos_handle_t *handle = (i2c_rtos_handle_t *)userData;
+    BaseType_t reschedule;
+    handle->async_status = status;
+    (void)xSemaphoreGiveFromISR(handle->semaphore, &reschedule);
+    portYIELD_FROM_ISR(reschedule);
+}
+
+/*!
+ * brief Initializes I2C.
+ *
+ * This function initializes the I2C module and the related RTOS context.
+ *
+ * param handle The RTOS I2C handle, the pointer to an allocated space for RTOS context.
+ * param base The pointer base address of the I2C instance to initialize.
+ * param masterConfig Configuration structure to set-up I2C in master mode.
+ * param srcClock_Hz Frequency of input clock of the I2C module.
+ * return status of the operation.
+ */
+status_t I2C_RTOS_Init(i2c_rtos_handle_t *handle,
+                       I2C_Type *base,
+                       const i2c_master_config_t *masterConfig,
+                       uint32_t srcClock_Hz)
+{
+    if (handle == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (base == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    (void)memset(handle, 0, sizeof(i2c_rtos_handle_t));
+
+    handle->mutex = xSemaphoreCreateMutex();
+    if (handle->mutex == NULL)
+    {
+        return kStatus_Fail;
+    }
+
+    handle->semaphore = xSemaphoreCreateBinary();
+    if (handle->semaphore == NULL)
+    {
+        vSemaphoreDelete(handle->mutex);
+        return kStatus_Fail;
+    }
+
+    handle->base = base;
+
+    I2C_MasterInit(handle->base, masterConfig, srcClock_Hz);
+    I2C_MasterTransferCreateHandle(base, &handle->drv_handle, I2C_RTOS_Callback, (void *)handle);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Deinitializes the I2C.
+ *
+ * This function deinitializes the I2C module and the related RTOS context.
+ *
+ * param handle The RTOS I2C handle.
+ */
+status_t I2C_RTOS_Deinit(i2c_rtos_handle_t *handle)
+{
+    I2C_MasterDeinit(handle->base);
+
+    vSemaphoreDelete(handle->semaphore);
+    vSemaphoreDelete(handle->mutex);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Performs I2C transfer.
+ *
+ * This function performs an I2C transfer according to data given in the transfer structure.
+ *
+ * param handle The RTOS I2C handle.
+ * param transfer Structure specifying the transfer parameters.
+ * return status of the operation.
+ */
+status_t I2C_RTOS_Transfer(i2c_rtos_handle_t *handle, i2c_master_transfer_t *transfer)
+{
+    status_t status;
+
+    /* Lock resource mutex */
+    if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE)
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    status = I2C_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer);
+    if (status != kStatus_Success)
+    {
+        (void)xSemaphoreGive(handle->mutex);
+        return status;
+    }
+
+    /* Wait for transfer to finish */
+    (void)xSemaphoreTake(handle->semaphore, portMAX_DELAY);
+
+    /* Unlock resource mutex */
+    (void)xSemaphoreGive(handle->mutex);
+
+    /* Return status captured by callback function */
+    return handle->async_status;
+}

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_freertos.h

@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __FSL_I2C_FREERTOS_H__
+#define __FSL_I2C_FREERTOS_H__
+
+#include "FreeRTOS.h"
+#include "portable.h"
+#include "semphr.h"
+
+#include "fsl_i2c.h"
+
+/*!
+ * @addtogroup i2c_freertos_driver I2C FreeRTOS Driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief I2C FreeRTOS driver version 2.0.8. */
+#define FSL_I2C_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 8))
+/*@}*/
+
+/*! @brief I2C FreeRTOS handle */
+typedef struct _i2c_rtos_handle
+{
+    I2C_Type *base;                 /*!< I2C base address */
+    i2c_master_handle_t drv_handle; /*!< A handle of the underlying driver, treated as opaque by the RTOS layer */
+    status_t async_status;          /*!< Transactional state of the underlying driver */
+    SemaphoreHandle_t mutex;        /*!< A mutex to lock the handle during a transfer */
+    SemaphoreHandle_t semaphore;    /*!< A semaphore to notify and unblock task when the transfer ends */
+#if (configSUPPORT_STATIC_ALLOCATION == 1)
+    StaticSemaphore_t mutexBuffer;     /*!< Statically allocated memory for mutex */
+    StaticSemaphore_t semaphoreBuffer; /*!< Statically allocated memory for semaphore */
+#endif
+} i2c_rtos_handle_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name I2C RTOS Operation
+ * @{
+ */
+
+/*!
+ * @brief Initializes I2C.
+ *
+ * This function initializes the I2C module and the related RTOS context.
+ *
+ * @param handle The RTOS I2C handle, the pointer to an allocated space for RTOS context.
+ * @param base The pointer base address of the I2C instance to initialize.
+ * @param masterConfig Configuration structure to set-up I2C in master mode.
+ * @param srcClock_Hz Frequency of input clock of the I2C module.
+ * @return status of the operation.
+ */
+status_t I2C_RTOS_Init(i2c_rtos_handle_t *handle,
+                       I2C_Type *base,
+                       const i2c_master_config_t *masterConfig,
+                       uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes the I2C.
+ *
+ * This function deinitializes the I2C module and the related RTOS context.
+ *
+ * @param handle The RTOS I2C handle.
+ */
+status_t I2C_RTOS_Deinit(i2c_rtos_handle_t *handle);
+
+/*!
+ * @brief Performs I2C transfer.
+ *
+ * This function performs an I2C transfer according to data given in the transfer structure.
+ *
+ * @param handle The RTOS I2C handle.
+ * @param transfer Structure specifying the transfer parameters.
+ * @return status of the operation.
+ */
+status_t I2C_RTOS_Transfer(i2c_rtos_handle_t *handle, i2c_master_transfer_t *transfer);
+
+/*!
+ * @}
+ */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* __FSL_I2C_FREERTOS_H__ */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2020 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -26,19 +26,19 @@
 /*! @name Driver version */
 /*@{*/
 
-/*! @brief I2S driver version 2.1.0. */
-#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief I2S driver version 2.3.1. */
+#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
 /*@}*/
 
 #ifndef I2S_NUM_BUFFERS
 
 /*! @brief Number of buffers . */
-#define I2S_NUM_BUFFERS (4)
+#define I2S_NUM_BUFFERS (4U)
 
 #endif
 
-/*! @brief I2S status codes. */
-enum _i2s_status
+/*! @brief _i2s_status I2S status codes. */
+enum
 {
     kStatus_I2S_BufferComplete =
         MAKE_STATUS(kStatusGroup_I2S, 0),                /*!< Transfer from/into a single buffer has completed */
@@ -78,8 +78,8 @@ typedef enum _i2s_mode
     kI2S_ModeDspWsLong  = 0x3  /*!< DSP mode, WS having one data slot long pulse */
 } i2s_mode_t;
 
-/*! @brief I2S secondary channel. */
-enum _i2s_secondary_channel
+/*! @brief _i2s_secondary_channel I2S secondary channel. */
+enum
 {
     kI2S_SecondaryChannel1 = 0U, /*!< secondary channel 1 */
     kI2S_SecondaryChannel2 = 1U, /*!< secondary channel 2 */
@@ -112,8 +112,8 @@ typedef struct _i2s_config
 /*! @brief Buffer to transfer from or receive audio data into. */
 typedef struct _i2s_transfer
 {
-    volatile uint8_t *data;   /*!< Pointer to data buffer. */
-    volatile size_t dataSize; /*!< Buffer size in bytes. */
+    uint8_t *data;   /*!< Pointer to data buffer. */
+    size_t dataSize; /*!< Buffer size in bytes. */
 } i2s_transfer_t;
 
 /*! @brief Transactional state of the intialized transfer or receive I2S operation. */
@@ -136,20 +136,21 @@ typedef void (*i2s_transfer_callback_t)(I2S_Type *base,
 /*! @brief Members not to be accessed / modified outside of the driver. */
 struct _i2s_handle
 {
-    uint32_t state;                             /*!< State of transfer */
+    volatile uint32_t state;                    /*!< State of transfer */
     i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */
     void *userData;                             /*!< Application data passed to callback */
     bool oneChannel;                            /*!< true mono, false stereo */
     uint8_t dataLength;                         /*!< Data length (4 - 32) */
-    bool pack48;     /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit
-                        values) */
-    bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */
+    bool pack48;       /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit
+                          values) */
+    uint8_t watermark; /*!< FIFO trigger level */
+    bool useFifo48H;   /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */
+
     volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */
     volatile uint8_t queueUser;                        /*!< Queue index where user's next transfer will be stored */
     volatile uint8_t queueDriver;                      /*!< Queue index of buffer actually used by the driver */
     volatile uint32_t errorCount;                      /*!< Number of buffer underruns/overruns */
     volatile uint32_t transferCount;                   /*!< Number of bytes transferred */
-    volatile uint8_t watermark;                        /*!< FIFO trigger level */
 };
 
 /*******************************************************************************
@@ -277,6 +278,18 @@ void I2S_RxGetDefaultConfig(i2s_config_t *config);
  */
 void I2S_Deinit(I2S_Type *base);
 
+/*!
+ * @brief Transmitter/Receiver bit clock rate configurations.
+ *
+ * @param base SAI base pointer.
+ * @param sourceClockHz bit clock source frequency.
+ * @param sampleRate audio data sample rate.
+ * @param bitWidth audio data bitWidth.
+ * @param channelNumbers audio channel numbers.
+ */
+void I2S_SetBitClockRate(
+    I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers);
+
 /*! @} */
 
 /*!
@@ -404,6 +417,10 @@ void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChanne
  */
 static inline void I2S_DisableSecondaryChannel(I2S_Type *base, uint32_t channel)
 {
+#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn
+    assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1);
+#endif
+
     base->SECCHANNEL[channel].PCFG1 &= ~I2S_CFG1_MAINENABLE_MASK;
 }
 #endif
@@ -461,6 +478,14 @@ static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base)
     return base->FIFOINTENSET;
 }
 
+/*!
+ * @brief Flush the valid data in TX fifo.
+ *
+ * @param base I2S base pointer.
+ * @return kStatus_Fail empty TX fifo failed, kStatus_Success empty tx fifo success.
+ */
+status_t I2S_EmptyTxFifo(I2S_Type *base);
+
 /*!
  * @brief Invoked from interrupt handler when transmit FIFO level decreases.
  *

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2020 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -21,7 +21,7 @@
 #endif
 
 #define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t))
-#define DMA_DESCRIPTORS (2U)
+#define DMA_DESCRIPTORS        (2U)
 
 /*<! @brief Structure for statically allocated private data. */
 typedef struct _i2s_dma_private_handle
@@ -50,9 +50,10 @@ typedef struct _i2s_dma_private_handle
 /*! @brief I2S DMA transfer private state. */
 enum _i2s_dma_state
 {
-    kI2S_DmaStateIdle = 0x0U, /*!< I2S is in idle state */
-    kI2S_DmaStateTx,          /*!< I2S is busy transmitting data */
-    kI2S_DmaStateRx,          /*!< I2S is busy receiving data */
+    kI2S_DmaStateIdle = 0x0U,      /*!< I2S is in idle state */
+    kI2S_DmaStateTx,               /*!< I2S is busy transmitting data */
+    kI2S_DmaStateRx,               /*!< I2S is busy receiving data */
+    kI2S_DmaStateBusyLoopTransfer, /*!< I2S is busy loop transfer */
 };
 
 /*******************************************************************************
@@ -73,7 +74,13 @@ static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle);
  * Variables
  ******************************************************************************/
 /*<! @brief Allocate DMA transfer descriptors. */
-DMA_ALLOCATE_LINK_DESCRIPTORS(s_DmaDescriptors, DMA_DESCRIPTORS *FSL_FEATURE_SOC_I2S_COUNT);
+#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp))
+AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT],
+                              FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE);
+#else
+SDK_ALIGN(static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT],
+          FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE);
+#endif
 
 /*<! @brief Buffer with dummy TX data. */
 SDK_ALIGN(static uint32_t s_DummyBufferTx, 4U);
@@ -98,8 +105,8 @@ static status_t I2S_EnqueueUserBuffer(I2S_Type *base, i2s_dma_handle_t *handle,
 
     /* Validate input data and transfer buffer */
 
-    assert(handle);
-    if (!handle)
+    assert(handle != NULL);
+    if (handle == NULL)
     {
         return kStatus_InvalidArgument;
     }
@@ -125,7 +132,7 @@ static status_t I2S_EnqueueUserBuffer(I2S_Type *base, i2s_dma_handle_t *handle,
         return kStatus_InvalidArgument;
     }
 
-    if (handle->i2sQueue[handle->queueUser].dataSize)
+    if (handle->i2sQueue[handle->queueUser].dataSize != 0UL)
     {
         /* Previously prepared buffers not processed yet, reject request */
         return kStatus_I2S_Busy;
@@ -164,7 +171,7 @@ static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle)
 
 static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle)
 {
-    if (handle->state != kI2S_DmaStateIdle)
+    if (handle->state != (uint32_t)kI2S_DmaStateIdle)
     {
         DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel);
     }
@@ -185,19 +192,19 @@ void I2S_TxTransferCreateHandleDMA(I2S_Type *base,
                                    i2s_dma_transfer_callback_t callback,
                                    void *userData)
 {
-    assert(handle);
-    assert(dmaHandle);
+    assert(handle != NULL);
+    assert(dmaHandle != NULL);
 
     uint32_t instance                       = I2S_GetInstance(base);
     i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
 
-    memset(handle, 0U, sizeof(*handle));
-    handle->state              = kI2S_DmaStateIdle;
+    (void)memset(handle, 0, sizeof(*handle));
+    handle->state              = (uint32_t)kI2S_DmaStateIdle;
     handle->dmaHandle          = dmaHandle;
     handle->completionCallback = callback;
     handle->userData           = userData;
 
-    handle->bytesPerFrame = (((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U) / 8U;
+    handle->bytesPerFrame = (uint8_t)((((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U) / 8U);
     /* if one channel is disabled, bytesPerFrame should be 4U, user should pay attention that when data length is
      * shorter than 16, the data format: left data put in 0-15 bit and right data should put in 16-31
      */
@@ -211,7 +218,7 @@ void I2S_TxTransferCreateHandleDMA(I2S_Type *base,
         handle->bytesPerFrame = 4U;
     }
 
-    memset(privateHandle, 0U, sizeof(*privateHandle));
+    (void)memset(privateHandle, 0, sizeof(*privateHandle));
     privateHandle->base   = base;
     privateHandle->handle = handle;
 
@@ -243,9 +250,9 @@ status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_tra
     }
 
     /* Initialize DMA transfer */
-    if (handle->state == kI2S_DmaStateIdle)
+    if (handle->state == (uint32_t)kI2S_DmaStateIdle)
     {
-        handle->state = kI2S_DmaStateTx;
+        handle->state = (uint32_t)kI2S_DmaStateTx;
         status        = I2S_StartTransferDMA(base, handle);
         if (status != kStatus_Success)
         {
@@ -268,8 +275,8 @@ status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_tra
  */
 void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle)
 {
-    assert(handle);
-    assert(handle->dmaHandle);
+    assert(handle != NULL);
+    assert(handle->dmaHandle != NULL);
 
     uint32_t instance                       = I2S_GetInstance(base);
     i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
@@ -279,41 +286,30 @@ void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle)
     /* Abort operation */
     DMA_AbortTransfer(handle->dmaHandle);
 
-    if (handle->state == kI2S_DmaStateTx)
+    if (handle->state == (uint32_t)kI2S_DmaStateTx)
     {
-        /* Wait until all transmitted data get out of FIFO */
-        while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U)
-        {
-        }
-        /* The last piece of valid data can be still being transmitted from I2S at this moment */
-
-        /* Write additional data to FIFO */
-        base->FIFOWR = 0U;
-        while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U)
-        {
-        }
-        /* At this moment the additional data are out of FIFO, starting being transmitted.
-         * This means the preceding valid data has been just transmitted and we can stop I2S. */
+        /* Disable TX */
         I2S_TxEnableDMA(base, false);
     }
     else
     {
+        /* Disable RX */
         I2S_RxEnableDMA(base, false);
     }
 
     I2S_Disable(base);
 
     /* Reset state */
-    handle->state = kI2S_DmaStateIdle;
+    handle->state = (uint32_t)kI2S_DmaStateIdle;
 
     /* Clear transfer queue */
-    memset((void *)&(handle->i2sQueue), 0U, sizeof(handle->i2sQueue));
+    (void)memset((void *)&(handle->i2sQueue), 0, sizeof(handle->i2sQueue));
     handle->queueDriver = 0U;
     handle->queueUser   = 0U;
 
     /* Clear internal state */
-    memset((void *)&(privateHandle->descriptorQueue), 0U, sizeof(privateHandle->descriptorQueue));
-    memset((void *)&(privateHandle->enqueuedBytes), 0U, sizeof(privateHandle->enqueuedBytes));
+    (void)memset((void *)&(privateHandle->descriptorQueue), 0, sizeof(privateHandle->descriptorQueue));
+    (void)memset((void *)&(privateHandle->enqueuedBytes), 0, sizeof(privateHandle->enqueuedBytes));
     privateHandle->enqueuedBytesStart = 0U;
     privateHandle->enqueuedBytesEnd   = 0U;
     privateHandle->dmaDescriptorsUsed = 0U;
@@ -366,9 +362,9 @@ status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_
     }
 
     /* Initialize DMA transfer */
-    if (handle->state == kI2S_DmaStateIdle)
+    if (handle->state == (uint32_t)kI2S_DmaStateIdle)
     {
-        handle->state = kI2S_DmaStateRx;
+        handle->state = (uint32_t)kI2S_DmaStateRx;
         status        = I2S_StartTransferDMA(base, handle);
         if (status != kStatus_Success)
         {
@@ -411,17 +407,17 @@ static void I2S_RxEnableDMA(I2S_Type *base, bool enable)
 
 static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer)
 {
-    assert(transfer);
+    assert(transfer != NULL);
 
     uint16_t transferBytes;
 
-    if (transfer->dataSize >= (2 * DMA_MAX_TRANSFER_BYTES))
+    if (transfer->dataSize >= (2UL * DMA_MAX_TRANSFER_BYTES))
     {
         transferBytes = DMA_MAX_TRANSFER_BYTES;
     }
     else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES)
     {
-        transferBytes = transfer->dataSize / 2U;
+        transferBytes = (uint16_t)(transfer->dataSize / 2U);
         if ((transferBytes % 4U) != 0U)
         {
             transferBytes -= (transferBytes % 4U);
@@ -429,40 +425,254 @@ static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer)
     }
     else
     {
-        transferBytes = transfer->dataSize;
+        transferBytes = (uint16_t)transfer->dataSize;
     }
 
     return transferBytes;
 }
 
+/*!
+ * brief Install DMA descriptor memory for loop transfer only.
+ *
+ * This function used to register DMA descriptor memory for the i2s loop dma transfer.
+ *
+ * It must be callbed before I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA and after
+ * I2S_RxTransferCreateHandleDMA/I2S_TxTransferCreateHandleDMA.
+ *
+ * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least.
+ *
+ * param handle Pointer to i2s DMA transfer handle.
+ * param dmaDescriptorAddr DMA descriptor start address.
+ * param dmaDescriptorNum DMA descriptor number.
+ */
+void I2S_TransferInstallLoopDMADescriptorMemory(i2s_dma_handle_t *handle,
+                                                void *dmaDescriptorAddr,
+                                                size_t dmaDescriptorNum)
+{
+    assert(handle != NULL);
+    assert((((uint32_t)(uint32_t *)dmaDescriptorAddr) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) ==
+           0UL);
+
+    handle->i2sLoopDMADescriptor    = (dma_descriptor_t *)dmaDescriptorAddr;
+    handle->i2sLoopDMADescriptorNum = dmaDescriptorNum;
+}
+
+static status_t I2S_TransferLoopDMA(I2S_Type *base,
+                                    i2s_dma_handle_t *handle,
+                                    i2s_transfer_t *xfer,
+                                    uint32_t loopTransferCount)
+{
+    assert(handle != NULL);
+    assert(handle->dmaHandle != NULL);
+    assert(xfer != NULL);
+
+    uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL;
+    i2s_transfer_t *currentTransfer = xfer;
+    bool intA                       = true;
+
+    if (handle->i2sLoopDMADescriptor == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->state == (uint32_t)kI2S_DmaStateBusyLoopTransfer)
+    {
+        return kStatus_I2S_Busy;
+    }
+
+    for (uint32_t i = 0U; i < loopTransferCount; i++)
+    {
+        currentTransfer = &xfer[i];
+
+        if ((currentTransfer->data == NULL) || (currentTransfer->dataSize == 0U) ||
+            (i >= handle->i2sLoopDMADescriptorNum) ||
+            (currentTransfer->dataSize / handle->bytesPerFrame > DMA_MAX_TRANSFER_COUNT))
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        if (handle->state == (uint32_t)kI2S_DmaStateTx)
+        {
+            srcAddr  = (uint32_t *)(uint32_t)currentTransfer->data;
+            destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR));
+            srcInc   = 1U;
+            destInc  = 0UL;
+        }
+        else
+        {
+            srcAddr  = (uint32_t *)(uint32_t)(&(base->FIFORD));
+            destAddr = (uint32_t *)(uint32_t)currentTransfer->data;
+            srcInc   = 0U;
+            destInc  = 1UL;
+        }
+
+        intA = intA == true ? false : true;
+
+        if (i == (loopTransferCount - 1U))
+        {
+            /* set up linked descriptor */
+            DMA_SetupDescriptor(&handle->i2sLoopDMADescriptor[i],
+                                DMA_CHANNEL_XFER(1UL, 0UL, intA, !intA, handle->bytesPerFrame, srcInc, destInc,
+                                                 currentTransfer->dataSize),
+                                srcAddr, destAddr, &handle->i2sLoopDMADescriptor[0U]);
+        }
+        else
+        {
+            /* set up linked descriptor */
+            DMA_SetupDescriptor(&handle->i2sLoopDMADescriptor[i],
+                                DMA_CHANNEL_XFER(1UL, 0UL, intA, !intA, handle->bytesPerFrame, srcInc, destInc,
+                                                 currentTransfer->dataSize),
+                                srcAddr, destAddr, &handle->i2sLoopDMADescriptor[i + 1U]);
+        }
+    }
+
+    /* transferSize make sense to non link transfer only */
+    if (handle->state == (uint32_t)kI2S_DmaStateTx)
+    {
+        srcAddr  = (uint32_t *)(uint32_t)xfer->data;
+        destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR));
+        srcInc   = 1U;
+        destInc  = 0UL;
+    }
+    else
+    {
+        srcAddr  = (uint32_t *)(uint32_t)(&(base->FIFORD));
+        destAddr = (uint32_t *)(uint32_t)xfer->data;
+        srcInc   = 0U;
+        destInc  = 1UL;
+    }
+
+    DMA_SubmitChannelTransferParameter(
+        handle->dmaHandle,
+        DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 1UL, handle->bytesPerFrame, srcInc, destInc, (uint32_t)xfer->dataSize), srcAddr,
+        destAddr, (void *)&handle->i2sLoopDMADescriptor[1U]);
+
+    /* Submit and start initial DMA transfer */
+    if (handle->state == (uint32_t)kI2S_DmaStateTx)
+    {
+        I2S_TxEnableDMA(base, true);
+    }
+    else
+    {
+        I2S_RxEnableDMA(base, true);
+    }
+    DMA_EnableChannelPeriphRq(handle->dmaHandle->base, handle->dmaHandle->channel);
+    /* start transfer */
+    DMA_StartTransfer(handle->dmaHandle);
+    I2S_Enable(base);
+
+    handle->state = (uint32_t)kI2S_DmaStateBusyLoopTransfer;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Send loop transfer data using DMA.
+ *
+ * This function receives data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * This function support loop transfer, such as A->B->...->A, the loop transfer chain
+ * will be converted into a chain of descriptor and submit to dma.
+ * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required,
+ * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory.
+ *
+ * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support
+ * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop
+ * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer.
+ *
+ * param base I2S peripheral base address.
+ * param handle Pointer to usart_dma_handle_t structure.
+ * param xfer I2S DMA transfer structure. See #i2s_transfer_t.
+ * param i2s_channel I2S start channel number
+ * retval kStatus_Success
+ */
+status_t I2S_TransferSendLoopDMA(I2S_Type *base,
+                                 i2s_dma_handle_t *handle,
+                                 i2s_transfer_t *xfer,
+                                 uint32_t loopTransferCount)
+{
+    assert(handle != NULL);
+    assert(handle->i2sLoopDMADescriptor != NULL);
+
+    handle->state = (uint32_t)kI2S_DmaStateTx;
+
+    return I2S_TransferLoopDMA(base, handle, xfer, loopTransferCount);
+}
+
+/*!
+ * brief Receive loop transfer data using DMA.
+ *
+ * This function receives data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * This function support loop transfer, such as A->B->...->A, the loop transfer chain
+ * will be converted into a chain of descriptor and submit to dma.
+ * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required,
+ * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory.
+ *
+ * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support
+ * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop
+ * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer.
+ *
+ * param base I2S peripheral base address.
+ * param handle Pointer to usart_dma_handle_t structure.
+ * param xfer I2S DMA transfer structure. See #i2s_transfer_t.
+ * param i2s_channel I2S start channel number
+ * retval kStatus_Success
+ */
+status_t I2S_TransferReceiveLoopDMA(I2S_Type *base,
+                                    i2s_dma_handle_t *handle,
+                                    i2s_transfer_t *xfer,
+                                    uint32_t loopTransferCount)
+{
+    assert(handle != NULL);
+    assert(handle->i2sLoopDMADescriptor != NULL);
+
+    handle->state = (uint32_t)kI2S_DmaStateRx;
+
+    return I2S_TransferLoopDMA(base, handle, xfer, loopTransferCount);
+}
+
 static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle)
 {
     uint32_t instance                       = I2S_GetInstance(base);
     i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
     volatile i2s_transfer_t *transfer       = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]);
     uint16_t transferBytes                  = I2S_GetTransferBytes(transfer);
-    int i                                   = 0U;
+    uint32_t i                              = 0U;
     uint32_t xferConfig                     = 0U;
+    uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL;
 
+    if (handle->state == (uint32_t)kI2S_DmaStateTx)
+    {
+        srcAddr  = (uint32_t *)(uint32_t)transfer->data;
+        destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR));
+        srcInc   = 1U;
+        destInc  = 0UL;
+    }
+    else
+    {
+        srcAddr  = (uint32_t *)(uint32_t)(&(base->FIFORD));
+        destAddr = (uint32_t *)(uint32_t)transfer->data;
+        srcInc   = 0U;
+        destInc  = 1UL;
+    }
     /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */
     privateHandle->dmaDescriptorsUsed = 1U;
     privateHandle->intA               = false;
 
     /* submit transfer parameter directly */
-    xferConfig = DMA_CHANNEL_XFER(true, false, privateHandle->intA, !privateHandle->intA, handle->bytesPerFrame,
-                                  (handle->state == kI2S_DmaStateTx) ? 1U : 0U,
-                                  (handle->state == kI2S_DmaStateTx) ? 0U : 1U, transferBytes);
-    DMA_SubmitChannelTransferParameter(
-        handle->dmaHandle, xferConfig,
-        (void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)transfer->data : (uint32_t)(&(base->FIFORD))),
-        (void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)(&(base->FIFOWR)) : (uint32_t)transfer->data),
-        (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U]));
+    xferConfig = DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 1UL, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes);
+
+    DMA_SubmitChannelTransferParameter(handle->dmaHandle, xferConfig, srcAddr, destAddr,
+                                       (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U]));
 
     privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes;
     privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS;
 
     transfer->dataSize -= transferBytes;
-    transfer->data += transferBytes;
+    transfer->data = (uint8_t *)((uint32_t)transfer->data + transferBytes);
 
     if (transfer->dataSize == 0U)
     {
@@ -478,17 +688,16 @@ static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle)
      */
     for (i = 0; i < DMA_DESCRIPTORS; i++)
     {
-        DMA_SetupDescriptor(&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]),
-                            DMA_CHANNEL_XFER(true, false, false, false, sizeof(uint32_t), 0U, 0U, 8U),
-                            ((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t)&s_DummyBufferTx :
-                                                                  (void *)(uint32_t)(&(base->FIFORD))),
-                            ((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t)(&(base->FIFOWR)) :
-                                                                  (void *)(uint32_t)&s_DummyBufferRx),
-                            &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1) % DMA_DESCRIPTORS)]));
+        /* DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 0UL, sizeof(uint32_t), 0U, 0U, 8U) = 0x10203UL  */
+        DMA_SetupDescriptor(
+            &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]), 0x10203UL,
+            ((handle->state == (uint32_t)kI2S_DmaStateTx) ? &s_DummyBufferTx : (uint32_t *)(uint32_t)(&(base->FIFORD))),
+            ((handle->state == (uint32_t)kI2S_DmaStateTx) ? (uint32_t *)(uint32_t)(&(base->FIFOWR)) : &s_DummyBufferRx),
+            &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1U) % DMA_DESCRIPTORS)]));
     }
 
     /* Submit and start initial DMA transfer */
-    if (handle->state == kI2S_DmaStateTx)
+    if (handle->state == (uint32_t)kI2S_DmaStateTx)
     {
         I2S_TxEnableDMA(base, true);
     }
@@ -514,6 +723,8 @@ static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle)
     dma_descriptor_t *descriptor;
     dma_descriptor_t *nextDescriptor;
     uint32_t xferConfig = 0U;
+    bool intA           = false;
+    uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL;
 
     instance      = I2S_GetInstance(base);
     privateHandle = &(s_DmaPrivateHandle[instance]);
@@ -521,13 +732,28 @@ static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle)
     while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS)
     {
         transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]);
-
+        intA     = privateHandle->intA;
         if (transfer->dataSize == 0U)
         {
             /* Nothing to be added */
             return;
         }
 
+        if (handle->state == (uint32_t)kI2S_DmaStateTx)
+        {
+            srcAddr  = (uint32_t *)(uint32_t)transfer->data;
+            destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR));
+            srcInc   = 1U;
+            destInc  = 0UL;
+        }
+        else
+        {
+            srcAddr  = (uint32_t *)(uint32_t)(&(base->FIFORD));
+            destAddr = (uint32_t *)(uint32_t)transfer->data;
+            srcInc   = 0U;
+            destInc  = 1UL;
+        }
+
         /* Determine currently configured descriptor and the other which it will link to */
         descriptor                = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]);
         privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS;
@@ -537,16 +763,10 @@ static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle)
         privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes;
         privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS;
 
-        xferConfig = DMA_CHANNEL_XFER(true, false, !privateHandle->intA, privateHandle->intA, handle->bytesPerFrame,
-                                      (handle->state == kI2S_DmaStateTx) ? 1U : 0U,
-                                      (handle->state == kI2S_DmaStateTx) ? 0U : 1U, transferBytes);
+        xferConfig =
+            DMA_CHANNEL_XFER(1UL, 0UL, !intA, intA, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes);
 
-        DMA_SetupDescriptor(descriptor, xferConfig,
-                            ((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t)transfer->data :
-                                                                  (void *)(uint32_t) & (base->FIFORD)),
-                            ((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t) & (base->FIFOWR) :
-                                                                  (void *)(uint32_t)transfer->data),
-                            nextDescriptor);
+        DMA_SetupDescriptor(descriptor, xferConfig, srcAddr, destAddr, nextDescriptor);
 
         /* Advance internal state */
         privateHandle->dmaDescriptorsUsed++;
@@ -575,8 +795,11 @@ void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, ui
     i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData;
     i2s_dma_handle_t *i2sHandle             = privateHandle->handle;
     I2S_Type *base                          = privateHandle->base;
+    uint8_t queueDriverIndex                = i2sHandle->queueDriver;
+    uint32_t enqueueBytes                   = privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
+    uint32_t queueDataAddr                  = (uint32_t)i2sHandle->i2sQueue[queueDriverIndex].data;
 
-    if ((!transferDone) || (i2sHandle->state == kI2S_DmaStateIdle))
+    if ((!transferDone) || (i2sHandle->state == (uint32_t)kI2S_DmaStateIdle))
     {
         return;
     }
@@ -585,35 +808,41 @@ void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, ui
     {
         /* Finished descriptor, decrease amount of data to be processed */
 
-        i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize -=
-            privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
-        i2sHandle->i2sQueue[i2sHandle->queueDriver].data +=
-            privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
+        i2sHandle->i2sQueue[queueDriverIndex].dataSize -= enqueueBytes;
+        i2sHandle->i2sQueue[queueDriverIndex].data                      = (uint8_t *)(queueDataAddr + enqueueBytes);
         privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U;
         privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS;
         privateHandle->dmaDescriptorsUsed--;
     }
 
-    if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U)
+    if (i2sHandle->i2sQueue[queueDriverIndex].dataSize == 0U)
     {
         /* Entire user buffer sent or received - advance to next one */
-        i2sHandle->i2sQueue[i2sHandle->queueDriver].data = NULL;
-        i2sHandle->queueDriver                           = (i2sHandle->queueDriver + 1U) % I2S_NUM_BUFFERS;
+        i2sHandle->i2sQueue[queueDriverIndex].data = NULL;
+        i2sHandle->queueDriver                     = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS;
         /* Notify user about buffer completion */
-        if (i2sHandle->completionCallback)
+        if (i2sHandle->completionCallback != NULL)
         {
             (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData);
         }
     }
-    /* check next buffer queue is avaliable or not */
-    if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U)
-    {
-        /* All user buffers processed */
-        I2S_TransferAbortDMA(base, i2sHandle);
-    }
-    else
+
+    if (i2sHandle->state != (uint32_t)kI2S_DmaStateBusyLoopTransfer)
     {
-        /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */
-        I2S_AddTransferDMA(base, i2sHandle);
+        /* check next buffer queue is avaliable or not */
+        if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U)
+        {
+            if (i2sHandle->state == (uint32_t)kI2S_DmaStateTx)
+            {
+                (void)I2S_EmptyTxFifo(base);
+            }
+            /* All user buffers processed */
+            I2S_TransferAbortDMA(base, i2sHandle);
+        }
+        else
+        {
+            /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */
+            I2S_AddTransferDMA(base, i2sHandle);
+        }
     }
 }

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2020 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -26,8 +26,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief I2S DMA driver version 2.1.0. */
-#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief I2S DMA driver version 2.3.1. */
+#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
 /*@}*/
 
 /*! @brief Members not to be accessed / modified outside of the driver. */
@@ -56,6 +56,9 @@ struct _i2s_dma_handle
     volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */
     volatile uint8_t queueUser;                        /*!< Queue index where user's next transfer will be stored */
     volatile uint8_t queueDriver;                      /*!< Queue index of buffer actually used by the driver */
+
+    dma_descriptor_t *i2sLoopDMADescriptor; /*!< descriptor pool pointer */
+    size_t i2sLoopDMADescriptorNum;         /*!< number of descriptor in descriptors pool */
 };
 
 /*******************************************************************************
@@ -151,6 +154,76 @@ status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_
  */
 void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds);
 
+/*!
+ * @brief Install DMA descriptor memory for loop transfer only.
+ *
+ * This function used to register DMA descriptor memory for the i2s loop dma transfer.
+ *
+ * It must be callbed before I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA and after
+ * I2S_RxTransferCreateHandleDMA/I2S_TxTransferCreateHandleDMA.
+ *
+ * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least.
+ *
+ * @param handle Pointer to i2s DMA transfer handle.
+ * @param dmaDescriptorAddr DMA descriptor start address.
+ * @param dmaDescriptorNum DMA descriptor number.
+ */
+void I2S_TransferInstallLoopDMADescriptorMemory(i2s_dma_handle_t *handle,
+                                                void *dmaDescriptorAddr,
+                                                size_t dmaDescriptorNum);
+
+/*!
+ * @brief Send link transfer data using DMA.
+ *
+ * This function receives data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * This function support loop transfer, such as A->B->...->A, the loop transfer chain
+ * will be converted into a chain of descriptor and submit to dma.
+ * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required,
+ * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory.
+ *
+ * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support
+ * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop
+ * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer.
+ *
+ * @param base I2S peripheral base address.
+ * @param handle Pointer to usart_dma_handle_t structure.
+ * @param xfer I2S DMA transfer structure. See #i2s_transfer_t.
+ * @param loopTransferCount loop count
+ * @retval kStatus_Success
+ */
+status_t I2S_TransferSendLoopDMA(I2S_Type *base,
+                                 i2s_dma_handle_t *handle,
+                                 i2s_transfer_t *xfer,
+                                 uint32_t loopTransferCount);
+
+/*!
+ * @brief Receive link transfer data using DMA.
+ *
+ * This function receives data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * This function support loop transfer, such as A->B->...->A, the loop transfer chain
+ * will be converted into a chain of descriptor and submit to dma.
+ * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required,
+ * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory.
+ *
+ * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support
+ * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop
+ * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer.
+ *
+ * @param base I2S peripheral base address.
+ * @param handle Pointer to usart_dma_handle_t structure.
+ * @param xfer I2S DMA transfer structure. See #i2s_transfer_t.
+ * @param loopTransferCount loop count
+ * @retval kStatus_Success
+ */
+status_t I2S_TransferReceiveLoopDMA(I2S_Type *base,
+                                    i2s_dma_handle_t *handle,
+                                    i2s_transfer_t *xfer,
+                                    uint32_t loopTransferCount);
+
 /*! @} */
 
 /*! @} */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 NXP
+ * Copyright 2018-2021 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -8,30 +8,58 @@
 
 #include "fsl_iap.h"
 #include "fsl_iap_ffr.h"
+#include "fsl_iap_kbp.h"
+#include "fsl_iap_skboot_authenticate.h"
 #include "fsl_device_registers.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
 /* Component ID definition, used by tools. */
 #ifndef FSL_COMPONENT_ID
 #define FSL_COMPONENT_ID "platform.drivers.iap1"
 #endif
 
+#if (defined(LPC5512_SERIES) || defined(LPC5514_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \
+     defined(LPC55S16_SERIES) || defined(LPC5524_SERIES) || defined(LPC5502_SERIES) || defined(LPC5504_SERIES) || \
+     defined(LPC5506_SERIES) || defined(LPC55S04_SERIES) || defined(LPC55S06_SERIES))
+
+#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1301fe00U)
+
+#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || defined(LPC5526_SERIES) || \
+       defined(LPC55S26_SERIES) || defined(LPC5528_SERIES) || defined(LPC55S28_SERIES) ||                       \
+       defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES))
+
+#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x130010f0U)
+
+#else
+#error "No valid CPU defined!"
+
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static status_t get_cfpa_higher_version(flash_config_t *config);
+
 /*!
- * @addtogroup flash_driver_api
+ * @name flash and ffr Structure
  * @{
  */
 
-#define ROM_API_TREE ((uint32_t *)0x130010f0)
-#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)ROM_API_TREE)
-
-static uint32_t S_VersionMajor = 0;
+typedef union functionCommandOption
+{
+    uint32_t commandAddr;
+    status_t (*eraseCommand)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
+    status_t (*programCommand)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
+    status_t (*verifyProgramCommand)(flash_config_t *config,
+                                     uint32_t start,
+                                     uint32_t lengthInBytes,
+                                     const uint8_t *expectedData,
+                                     uint32_t *failedAddress,
+                                     uint32_t *failedData);
+    status_t (*flashReadCommand)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes);
+} function_command_option_t;
 
-typedef status_t (*EraseCommend_t)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
-typedef status_t (*ProgramCommend_t)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
-typedef status_t (*VerifyProgramCommend_t)(flash_config_t *config,
-                                           uint32_t start,
-                                           uint32_t lengthInBytes,
-                                           const uint8_t *expectedData,
-                                           uint32_t *failedAddress,
-                                           uint32_t *failedData);
 /*
  *!@brief Structure of version property.
  *
@@ -58,7 +86,38 @@ typedef union StandardVersion
 } standard_version_t;
 
 /*! @brief Interface for the flash driver.*/
-typedef struct FlashDriverInterface
+typedef struct version1FlashDriverInterface
+{
+    standard_version_t version; /*!< flash driver API version number.*/
+
+    /*!< Flash driver.*/
+    status_t (*flash_init)(flash_config_t *config);
+    status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
+    status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
+    status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes);
+    status_t (*flash_verify_program)(flash_config_t *config,
+                                     uint32_t start,
+                                     uint32_t lengthInBytes,
+                                     const uint8_t *expectedData,
+                                     uint32_t *failedAddress,
+                                     uint32_t *failedData);
+    status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value);
+    uint32_t reserved[3]; /*! Reserved for future use */
+    /*!< Flash FFR driver*/
+    status_t (*ffr_init)(flash_config_t *config);
+    status_t (*ffr_lock_all)(flash_config_t *config);
+    status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part);
+    status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid);
+    status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
+    status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore);
+    status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode);
+    status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex);
+    status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len);
+    status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
+} version1_flash_driver_interface_t;
+
+/*! @brief Interface for the flash driver.*/
+typedef struct version0FlashDriverInterface
 {
     standard_version_t version; /*!< flash driver API version number.*/
 
@@ -74,20 +133,10 @@ typedef struct FlashDriverInterface
                                      uint32_t *failedAddress,
                                      uint32_t *failedData);
     status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value);
-    status_t (*flash_erase_with_checker)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
-    status_t (*flash_program_with_checker)(flash_config_t *config,
-                                           uint32_t start,
-                                           uint8_t *src,
-                                           uint32_t lengthInBytes);
-    status_t (*flash_verify_program_with_checker)(flash_config_t *config,
-                                                  uint32_t start,
-                                                  uint32_t lengthInBytes,
-                                                  const uint8_t *expectedData,
-                                                  uint32_t *failedAddress,
-                                                  uint32_t *failedData);
+
     /*!< Flash FFR driver*/
     status_t (*ffr_init)(flash_config_t *config);
-    status_t (*ffr_deinit)(flash_config_t *config);
+    status_t (*ffr_lock_all)(flash_config_t *config);
     status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part);
     status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid);
     status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
@@ -96,8 +145,38 @@ typedef struct FlashDriverInterface
     status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex);
     status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len);
     status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
+} version0_flash_driver_interface_t;
+
+typedef union flashDriverInterface
+{
+    const version1_flash_driver_interface_t *version1FlashDriver;
+    const version0_flash_driver_interface_t *version0FlashDriver;
 } flash_driver_interface_t;
 
+/*! @}*/
+
+/*!
+ * @name Bootloader API and image authentication Structure
+ * @{
+ */
+
+/*! @brief Interface for Bootloader API functions. */
+typedef struct _kb_interface
+{
+    /*!< Initialize the API. */
+    status_t (*kb_init_function)(kb_session_ref_t **session, const kb_options_t *options);
+    status_t (*kb_deinit_function)(kb_session_ref_t *session);
+    status_t (*kb_execute_function)(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength);
+} kb_interface_t;
+
+//! @brief Interface for image authentication API
+typedef struct _skboot_authenticate_interface
+{
+    skboot_status_t (*skboot_authenticate_function)(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified);
+    void (*skboot_hashcrypt_irq_handler)(void);
+} skboot_authenticate_interface_t;
+/*! @}*/
+
 /*!
  * @brief Root of the bootloader API tree.
  *
@@ -108,74 +187,151 @@ typedef struct FlashDriverInterface
  */
 typedef struct BootloaderTree
 {
-    void (*runBootloader)(void *arg);            /*!< Function to start the bootloader executing. */
-    standard_version_t bootloader_version;       /*!< Bootloader version number. */
-    const char *copyright;                       /*!< Copyright string. */
-    const uint32_t *reserved;                    /*!< Do NOT use. */
-    const flash_driver_interface_t *flashDriver; /*!< Flash driver API. */
+    void (*runBootloader)(void *arg);      /*!< Function to start the bootloader executing. */
+    standard_version_t bootloader_version; /*!< Bootloader version number. */
+    const char *copyright;                 /*!< Copyright string. */
+    const uint32_t reserved0;              /*!< Do NOT use. */
+    flash_driver_interface_t flashDriver;
+    const kb_interface_t *kbApi;                               /*!< Bootloader API. */
+    const uint32_t reserved1[4];                               /*!< Do NOT use. */
+    const skboot_authenticate_interface_t *skbootAuthenticate; /*!< Image authentication API. */
 } bootloader_tree_t;
 
+/*******************************************************************************
+ * Prototype
+ ******************************************************************************/
+static uint32_t get_rom_api_version(void);
+
 /*******************************************************************************
  * Variables
  ******************************************************************************/
 
-/*! @brief Global pointer to the flash driver API table in ROM. */
-flash_driver_interface_t *FLASH_API_TREE;
 /*! Get pointer to flash driver API table in ROM. */
-#define FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver
+#define VERSION1_FLASH_API_TREE       BOOTLOADER_API_TREE_POINTER->flashDriver.version1FlashDriver
+#define VERSION0_FLASH_API_TREE       BOOTLOADER_API_TREE_POINTER->flashDriver.version0FlashDriver
+#define LPC55S69_REV0_FLASH_READ_ADDR (0x130043a3U)
+#define LPC55S69_REV1_FLASH_READ_ADDR (0x13007539U)
+#define LPC55S16_REV0_FLASH_READ_ADDR (0x1300ade5U)
+
 /*******************************************************************************
  * Code
  ******************************************************************************/
 
-/*! See fsl_flash.h for documentation of this function. */
+static uint32_t get_rom_api_version(void)
+{
+    if (BOOTLOADER_API_TREE_POINTER->bootloader_version.major == 3u)
+    {
+        return 1u;
+    }
+    else
+    {
+        return 0u;
+    }
+}
+
+/*!
+ * @brief Initializes the global flash properties structure members.
+ *
+ * This function checks and initializes the Flash module for the other Flash APIs.
+ */
 status_t FLASH_Init(flash_config_t *config)
 {
-    assert(FLASH_API_TREE);
-    config->modeConfig.sysFreqInMHz = kSysToFlashFreq_defaultInMHz;
-    S_VersionMajor                  = BOOTLOADER_API_TREE_POINTER->bootloader_version.major;
-    return FLASH_API_TREE->flash_init(config);
+    status_t status;
+    /* Initialize the clock to 96MHz */
+    config->modeConfig.sysFreqInMHz = (uint32_t)kSysToFlashFreq_defaultInMHz;
+    if (get_rom_api_version() == 1u)
+    {
+        status = VERSION1_FLASH_API_TREE->flash_init(config);
+    }
+    else
+    {
+        status = VERSION0_FLASH_API_TREE->flash_init(config);
+    }
+
+    if (config->PFlashTotalSize == 0xA0000U)
+    {
+        config->PFlashTotalSize -= 17U * config->PFlashPageSize;
+    }
+
+    return status;
 }
 
-/*! See fsl_flash.h for documentation of this function. */
+/*!
+ * @brief Erases the flash sectors encompassed by parameters passed into function.
+ *
+ * This function erases the appropriate number of flash sectors based on the
+ * desired start address and length.
+ */
 status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key)
 {
-    if (S_VersionMajor == 2)
+    if (get_rom_api_version() == 0u)
     {
-        EraseCommend_t EraseCommand =
-            (EraseCommend_t)(0x1300413b); /*!< get the flash erase api location adress int rom */
-        return EraseCommand(config, start, lengthInBytes, key);
+        function_command_option_t runCmdFuncOption;
+        runCmdFuncOption.commandAddr = 0x1300413bU; /*!< get the flash erase api location adress in rom */
+        return runCmdFuncOption.eraseCommand(config, start, lengthInBytes, key);
     }
     else
     {
-        assert(FLASH_API_TREE);
-        return FLASH_API_TREE->flash_erase(config, start, lengthInBytes, key);
+        return VERSION1_FLASH_API_TREE->flash_erase(config, start, lengthInBytes, key);
     }
 }
 
-/*! See fsl_flash.h for documentation of this function. */
+/*! See fsl_iap.h for documentation of this function. */
 status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)
 {
-    if (S_VersionMajor == 2)
+    if (get_rom_api_version() == 0u)
+    {
+        function_command_option_t runCmdFuncOption;
+        runCmdFuncOption.commandAddr = 0x1300419dU; /*!< get the flash program api location adress in rom*/
+        return runCmdFuncOption.programCommand(config, start, src, lengthInBytes);
+    }
+    else
+    {
+        assert(VERSION1_FLASH_API_TREE);
+        return VERSION1_FLASH_API_TREE->flash_program(config, start, src, lengthInBytes);
+    }
+}
+
+/*! See fsl_iap.h for documentation of this function. */
+status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes)
+{
+    if (get_rom_api_version() == 0u)
     {
-        ProgramCommend_t ProgramCommend =
-            (ProgramCommend_t)(0x1300419d); /*!< get the flash program api location adress in rom*/
-        return ProgramCommend(config, start, src, lengthInBytes);
+        /*!< get the flash read api location adress in rom*/
+        function_command_option_t runCmdFuncOption;
+        runCmdFuncOption.commandAddr = LPC55S69_REV0_FLASH_READ_ADDR;
+        return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes);
     }
     else
     {
-        assert(FLASH_API_TREE);
-        return FLASH_API_TREE->flash_program(config, start, src, lengthInBytes);
+        /*!< get the flash read api location adress in rom*/
+        function_command_option_t runCmdFuncOption;
+        if ((SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK) != 0u)
+        {
+            runCmdFuncOption.commandAddr = LPC55S69_REV1_FLASH_READ_ADDR;
+        }
+        else
+        {
+            runCmdFuncOption.commandAddr = LPC55S16_REV0_FLASH_READ_ADDR;
+        }
+        return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes);
     }
 }
 
-/*! See fsl_flash.h for documentation of this function. */
+/*! See fsl_iap.h for documentation of this function. */
 status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes)
 {
-    assert(FLASH_API_TREE);
-    return FLASH_API_TREE->flash_verify_erase(config, start, lengthInBytes);
+    assert(VERSION1_FLASH_API_TREE);
+    return VERSION1_FLASH_API_TREE->flash_verify_erase(config, start, lengthInBytes);
 }
 
-/*! See fsl_flash.h for documentation of this function. */
+/*!
+ * @brief Verifies programming of the desired flash area at a specified margin level.
+ *
+ * This function verifies the data programed in the flash memory using the
+ * Flash Program Check Command and compares it to the expected data for a given
+ * flash area as determined by the start address and length.
+ */
 status_t FLASH_VerifyProgram(flash_config_t *config,
                              uint32_t start,
                              uint32_t lengthInBytes,
@@ -183,103 +339,328 @@ status_t FLASH_VerifyProgram(flash_config_t *config,
                              uint32_t *failedAddress,
                              uint32_t *failedData)
 {
-    if (S_VersionMajor == 2)
+    if (get_rom_api_version() == 0u)
     {
-        VerifyProgramCommend_t VerifyProgramCommend =
-            (VerifyProgramCommend_t)(0x1300427d); /*!< get the flash verify program api location adress in
-                                                     rom*/
-        return VerifyProgramCommend(config, start, lengthInBytes, expectedData, failedAddress, failedData);
+        function_command_option_t runCmdFuncOption;
+        runCmdFuncOption.commandAddr = 0x1300427dU; /*!< get the flash verify program api location adress in rom*/
+        return runCmdFuncOption.verifyProgramCommand(config, start, lengthInBytes, expectedData, failedAddress,
+                                                     failedData);
     }
     else
     {
-        assert(FLASH_API_TREE);
-        return FLASH_API_TREE->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress,
-                                                    failedData);
+        assert(VERSION1_FLASH_API_TREE);
+        return VERSION1_FLASH_API_TREE->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress,
+                                                             failedData);
     }
 }
 
-/*! See fsl_flash.h for documentation of this function.*/
+/*!
+ * @brief Returns the desired flash property.
+ */
 status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value)
 {
-    assert(FLASH_API_TREE);
-    return FLASH_API_TREE->flash_get_property(config, whichProperty, value);
+    assert(VERSION1_FLASH_API_TREE);
+    return VERSION1_FLASH_API_TREE->flash_get_property(config, whichProperty, value);
 }
 /********************************************************************************
  * fsl iap ffr CODE
  *******************************************************************************/
 
-/*! See fsl_iap_ffr.h for documentation of this function. */
+static status_t get_cfpa_higher_version(flash_config_t *config)
+{
+    uint32_t pageData[FLASH_FFR_MAX_PAGE_SIZE / sizeof(uint32_t)];
+    uint32_t versionPing = 0U;
+    uint32_t versionPong = 0U;
+
+    /* Get the CFPA ping page data and the corresponding version */
+    config->ffrConfig.cfpaPageOffset = 1U;
+    status_t status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE);
+    if (status != (int32_t)kStatus_FLASH_Success)
+    {
+        return status;
+    }
+    versionPing = pageData[1];
+
+    /* Get the CFPA pong page data and the corresponding version */
+    config->ffrConfig.cfpaPageOffset = 2U;
+    status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE);
+    if (status != (int32_t)kStatus_FLASH_Success)
+    {
+        return status;
+    }
+    versionPong = pageData[1];
+
+    /* Compare the CFPA ping version and pong version and set it correctly in flash_config structure */
+    if (versionPing > versionPong)
+    {
+        config->ffrConfig.cfpaPageVersion = versionPing;
+        config->ffrConfig.cfpaPageOffset  = 1U;
+    }
+    else
+    {
+        config->ffrConfig.cfpaPageVersion = versionPong;
+        config->ffrConfig.cfpaPageOffset  = 2U;
+    }
+    return (int32_t)kStatus_FLASH_Success;
+}
+
+/*!
+ * Initializes the global FFR properties structure members.
+ */
 status_t FFR_Init(flash_config_t *config)
 {
-    assert(FLASH_API_TREE);
-    return FLASH_API_TREE->ffr_init(config);
+    status_t status;
+    if (get_rom_api_version() == 0u)
+    {
+        assert(VERSION0_FLASH_API_TREE);
+        status = VERSION0_FLASH_API_TREE->ffr_init(config);
+        if (status != (status_t)kStatus_FLASH_Success)
+        {
+            return status;
+        }
+        return get_cfpa_higher_version(config);
+    }
+    else
+    {
+        assert(VERSION1_FLASH_API_TREE);
+        status = VERSION1_FLASH_API_TREE->ffr_init(config);
+        if (status != (status_t)kStatus_FLASH_Success)
+        {
+            return status;
+        }
+        return get_cfpa_higher_version(config);
+    }
 }
 
-/*! See fsl_iap_ffr.h for documentation of this function. */
-status_t FFR_Deinit(flash_config_t *config)
+/*!
+ * Enable firewall for all flash banks.
+ */
+status_t FFR_Lock_All(flash_config_t *config)
 {
-    assert(FLASH_API_TREE);
-    return FLASH_API_TREE->ffr_deinit(config);
+    if (get_rom_api_version() == 0u)
+    {
+        assert(VERSION0_FLASH_API_TREE);
+        return VERSION0_FLASH_API_TREE->ffr_lock_all(config);
+    }
+    else
+    {
+        assert(VERSION1_FLASH_API_TREE);
+        return VERSION1_FLASH_API_TREE->ffr_lock_all(config);
+    }
 }
 
-/*! See fsl_iap_ffr.h for documentation of this function. */
+/*!
+ * APIs to access CMPA pages;
+ * This routine will erase "customer factory page" and program the page with passed data.
+ */
 status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part)
 {
-    assert(FLASH_API_TREE);
-    return FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part);
+    if (get_rom_api_version() == 0u)
+    {
+        assert(VERSION0_FLASH_API_TREE);
+        return VERSION0_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part);
+    }
+    else
+    {
+        assert(VERSION1_FLASH_API_TREE);
+        return VERSION1_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part);
+    }
 }
 
-/*! See fsl_iap_ffr.h for documentation of this function. */
+/*!
+ * See fsl_iap_ffr.h for documentation of this function.
+ */
 status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid)
 {
-    assert(FLASH_API_TREE);
-    return FLASH_API_TREE->ffr_get_uuid(config, uuid);
+    if (get_rom_api_version() == 0u)
+    {
+        assert(VERSION0_FLASH_API_TREE);
+        return VERSION0_FLASH_API_TREE->ffr_get_uuid(config, uuid);
+    }
+    else
+    {
+        assert(VERSION1_FLASH_API_TREE);
+        return VERSION1_FLASH_API_TREE->ffr_get_uuid(config, uuid);
+    }
 }
 
-/*! See fsl_iap_ffr.h for documentation of this function. */
+/*!
+ * APIs to access CMPA pages
+ * Read data stored in 'Customer Factory CFG Page'.
+ */
 status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len)
 {
-    assert(FLASH_API_TREE);
-    return FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len);
+    if (get_rom_api_version() == 0u)
+    {
+        assert(VERSION0_FLASH_API_TREE);
+        return VERSION0_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len);
+    }
+    else
+    {
+        assert(VERSION1_FLASH_API_TREE);
+        return VERSION1_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len);
+    }
 }
 
-/*! See fsl_iap_ffr.h for documentation of this function. */
+/*!
+ * This routine writes the 3 pages allocated for Key store data,
+ * Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state.
+ */
 status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore)
 {
-    assert(FLASH_API_TREE);
-    return FLASH_API_TREE->ffr_keystore_write(config, pKeyStore);
+    if (get_rom_api_version() == 0u)
+    {
+        assert(VERSION0_FLASH_API_TREE);
+        return VERSION0_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore);
+    }
+    else
+    {
+        assert(VERSION1_FLASH_API_TREE);
+        return VERSION1_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore);
+    }
 }
 
 /*! See fsl_iap_ffr.h for documentation of this function. */
 status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode)
 {
-    assert(FLASH_API_TREE);
-    return FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode);
+    if (get_rom_api_version() == 0u)
+    {
+        assert(VERSION0_FLASH_API_TREE);
+        return VERSION0_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode);
+    }
+    else
+    {
+        assert(VERSION1_FLASH_API_TREE);
+        return VERSION1_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode);
+    }
 }
 
 /*! See fsl_iap_ffr.h for documentation of this function. */
 status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex)
 {
-    assert(FLASH_API_TREE);
-    return FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex);
+    if (get_rom_api_version() == 0u)
+    {
+        assert(VERSION0_FLASH_API_TREE);
+        return VERSION0_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex);
+    }
+    else
+    {
+        assert(VERSION1_FLASH_API_TREE);
+        return VERSION1_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex);
+    }
 }
 
-/*! See fsl_iap_ffr.h for documentation of this function. */
+/*!
+ * APIs to access CFPA pages
+ * This routine will erase CFPA and program the CFPA page with passed data.
+ */
 status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len)
 {
-    assert(FLASH_API_TREE);
-    return FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len);
+    if (get_rom_api_version() == 0u)
+    {
+        assert(VERSION0_FLASH_API_TREE);
+        return VERSION0_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len);
+    }
+    else
+    {
+        assert(VERSION1_FLASH_API_TREE);
+        return VERSION1_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len);
+    }
 }
 
-/*! See fsl_iap_ffr.h for documentation of this function. */
+/*!
+ * APIs to access CFPA pages
+ * Generic read function, used by customer to read data stored in 'Customer In-field Page'.
+ */
 status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len)
 {
-    assert(FLASH_API_TREE);
-    return FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len);
+    if (get_rom_api_version() == 0u)
+    {
+        assert(VERSION0_FLASH_API_TREE);
+        return VERSION0_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len);
+    }
+    else
+    {
+        assert(VERSION1_FLASH_API_TREE);
+        return VERSION1_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len);
+    }
 }
 
-/*! @}*/
+/********************************************************************************
+ * Bootloader API
+ *******************************************************************************/
+/*!
+ * @brief Initialize ROM API for a given operation.
+ *
+ * Inits the ROM API based on the options provided by the application in the second
+ * argument. Every call to rom_init() should be paired with a call to rom_deinit().
+ */
+status_t kb_init(kb_session_ref_t **session, const kb_options_t *options)
+{
+    assert(BOOTLOADER_API_TREE_POINTER);
+    return BOOTLOADER_API_TREE_POINTER->kbApi->kb_init_function(session, options);
+}
+
+/*!
+ * @brief Cleans up the ROM API context.
+ *
+ * After this call, the @a context parameter can be reused for another operation
+ * by calling rom_init() again.
+ */
+status_t kb_deinit(kb_session_ref_t *session)
+{
+    assert(BOOTLOADER_API_TREE_POINTER);
+    return BOOTLOADER_API_TREE_POINTER->kbApi->kb_deinit_function(session);
+}
+
+/*!
+ * Perform the operation configured during init.
+ *
+ * This application must call this API repeatedly, passing in sequential chunks of
+ * data from the boot image (SB file) that is to be processed. The ROM will perform
+ * the selected operation on this data and return. The application may call this
+ * function with as much or as little data as it wishes, which can be used to select
+ * the granularity of time given to the application in between executing the operation.
+ *
+ * @param context Current ROM context pointer.
+ * @param data Buffer of boot image data provided to the ROM by the application.
+ * @param dataLength Length in bytes of the data in the buffer provided to the ROM.
+ *
+ * @retval #kStatus_Success The operation has completed successfully.
+ * @retval #kStatus_Fail An error occurred while executing the operation.
+ * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to
+ *     continue processing the boot image.
+ */
+status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength)
+{
+    assert(BOOTLOADER_API_TREE_POINTER);
+    return BOOTLOADER_API_TREE_POINTER->kbApi->kb_execute_function(session, data, dataLength);
+}
+
+/********************************************************************************
+ * Image authentication API
+ *******************************************************************************/
+
+/*!
+ * @brief Authenticate entry function with ARENA allocator init
+ *
+ * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface
+ */
+skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified)
+{
+    assert(BOOTLOADER_API_TREE_POINTER);
+    return BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_authenticate_function(imageStartAddr,
+                                                                                         isSignVerified);
+}
 
+/*!
+ * @brief Interface for image authentication API
+ */
+void HASH_IRQHandler(void)
+{
+    assert(BOOTLOADER_API_TREE_POINTER);
+    BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_hashcrypt_irq_handler();
+}
 /********************************************************************************
  * EOF
  *******************************************************************************/

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 NXP
+ * Copyright 2018-2021 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -30,15 +30,15 @@
 #endif
 
 /*! @brief Flash driver version for SDK*/
-#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4. */
 
 /*! @brief Flash driver version for ROM*/
 enum _flash_driver_version_constants
 {
     kFLASH_DriverVersionName   = 'F', /*!< Flash driver version name.*/
     kFLASH_DriverVersionMajor  = 2,   /*!< Major flash driver version.*/
-    kFLASH_DriverVersionMinor  = 0,   /*!< Minor flash driver version.*/
-    kFLASH_DriverVersionBugfix = 0    /*!< Bugfix for flash driver version.*/
+    kFLASH_DriverVersionMinor  = 1,   /*!< Minor flash driver version.*/
+    kFLASH_DriverVersionBugfix = 3    /*!< Bugfix for flash driver version.*/
 };
 
 /*@}*/
@@ -61,13 +61,13 @@ enum _flash_driver_version_constants
  */
 /*! @brief Flash driver status group. */
 #if defined(kStatusGroup_FlashDriver)
-#define kStatusGroupGeneric kStatusGroup_Generic
+#define kStatusGroupGeneric     kStatusGroup_Generic
 #define kStatusGroupFlashDriver kStatusGroup_FlashDriver
 #elif defined(kStatusGroup_FLASHIAP)
-#define kStatusGroupGeneric kStatusGroup_Generic
+#define kStatusGroupGeneric     kStatusGroup_Generic
 #define kStatusGroupFlashDriver kStatusGroup_FLASH
 #else
-#define kStatusGroupGeneric 0
+#define kStatusGroupGeneric     0
 #define kStatusGroupFlashDriver 1
 #endif
 
@@ -350,12 +350,14 @@ status_t FLASH_Init(flash_config_t *config);
  *
  * @param config The pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be erased.
- *              The start address does not need to be sector-aligned.
+ *              The start address need to be 512bytes-aligned.
  * @param lengthInBytes The length, given in bytes (not words or long-words)
- *                      to be erased. Must be word-aligned.
+ *                      to be erased. Must be 512bytes-aligned.
  * @param key The value used to validate all flash erase APIs.
  *
- * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_Success API was executed successfully;
+ *         the appropriate number of flash sectors based on the desired
+ *         start address and length were erased successfully.
  * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline.
  * @retval #kStatus_FLASH_AddressError The address is out of range.
@@ -381,13 +383,14 @@ status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBy
  *
  * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be programmed. Must be
- *              word-aligned.
+ *              512bytes-aligned.
  * @param src A pointer to the source buffer of data that is to be programmed
  *            into the flash.
  * @param lengthInBytes The length, given in bytes (not words or long-words),
- *                      to be programmed. Must be word-aligned.
+ *                      to be programmed. Must be 512bytes-aligned.
  *
- * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_Success API was executed successfully; the desired data were programed successfully
+ *         into flash based on desired start address and length.
  * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline.
  * @retval #kStatus_FLASH_AddressError Address is out of range.
@@ -401,6 +404,31 @@ status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uin
 
 /*@}*/
 
+/*!
+ * @brief Reads flash at locations passed in through parameters.
+ *
+ * This function read the flash memory from a given flash area as determined
+ * by the start address and the length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be read.
+ * @param dest A pointer to the dest buffer of data that is to be read
+ *            from the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *                      to be read.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
+ * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution.
+ */
+status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes);
+
 /*!
  * @name Verification
  * @{
@@ -415,12 +443,11 @@ status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uin
  *
  * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be verified.
- *        The start address does not need to be sector-aligned but must be word-aligned.
+ *        The start address need to be 512bytes-aligned.
  * @param lengthInBytes The length, given in bytes (not words or long-words),
- *        to be verified. Must be word-aligned.
- * @param margin Read margin choice.
+ *        to be verified. Must be 512bytes-aligned.
  *
- * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_Success API was executed successfully; the specified FLASH region has been erased.
  * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
  * @retval #kStatus_FLASH_AddressError Address is out of range.
@@ -440,18 +467,19 @@ status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t leng
  * flash area as determined by the start address and length.
  *
  * @param config A pointer to the storage for the driver runtime state.
- * @param start The start address of the desired flash memory to be verified. Must be word-aligned.
+ * @param start The start address of the desired flash memory to be verified. need be 512bytes-aligned.
  * @param lengthInBytes The length, given in bytes (not words or long-words),
- *        to be verified. Must be word-aligned.
+ *        to be verified. need be 512bytes-aligned.
  * @param expectedData A pointer to the expected data that is to be
  *        verified against.
- * @param margin Read margin choice.
  * @param failedAddress A pointer to the returned failing address.
  * @param failedData A pointer to the returned failing data.  Some derivatives do
  *        not include failed data as part of the FCCOBx registers.  In this
  *        case, zeros are returned upon failure.
  *
- * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_Success API was executed successfully;
+ *         the desired data have been successfully programed into specified FLASH region.
+ *
  * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
  * @retval #kStatus_FLASH_AddressError Address is out of range.
@@ -483,7 +511,7 @@ status_t FLASH_VerifyProgram(flash_config_t *config,
  *        enum flash_property_tag_t
  * @param value A pointer to the value returned for the desired flash property.
  *
- * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_Success API was executed successfully; the flash property was stored to value.
  * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_UnknownProperty An unknown property tag.
  */
@@ -495,4 +523,6 @@ status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichPro
 }
 #endif
 
+/*@}*/
+
 #endif /* __FLASH_FLASH_H_ */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_ffr.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -26,7 +26,7 @@
  * @{
  */
 /*! @brief Flash IFR driver version for SDK*/
-#define FSL_FLASH_IFR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_FLASH_IFR_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */
 /*@}*/
 
 /*! @brief Alignment(down) utility. */
@@ -39,10 +39,11 @@
 #define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a))))))
 #endif
 
-#define FLASH_FFR_MAX_PAGE_SIZE (512u)
+#define FLASH_FFR_MAX_PAGE_SIZE    (512u)
 #define FLASH_FFR_HASH_DIGEST_SIZE (32u)
-#define FLASH_FFR_IV_CODE_SIZE (52u)
+#define FLASH_FFR_IV_CODE_SIZE     (52u)
 
+/*! @brief flash ffr page offset. */
 enum _flash_ffr_page_offset
 {
     kFfrPageOffset_CFPA         = 0, /*!< Customer In-Field programmed area*/
@@ -61,6 +62,7 @@ enum _flash_ffr_page_offset
     kFfrPageOffset_NMPA_End    = 16, /*!< Reserved (Part of NMPA)*/
 };
 
+/*! @brief flash ffr page number. */
 enum _flash_ffr_page_num
 {
     kFfrPageNum_CFPA = 3,  /*!< Customer In-Field programmed area*/
@@ -112,14 +114,14 @@ typedef struct _cfpa_cfg_info
     uint8_t sha256[32];                       /*!< [0x1e0-0x1ff] */
 } cfpa_cfg_info_t;
 
-#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U)
+#define FFR_BOOTCFG_BOOTSPEED_MASK  (0x18U)
 #define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U)
 #define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x0U)
 #define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x1U)
 
-#define FFR_USBID_VENDORID_MASK (0xFFFFU)
-#define FFR_USBID_VENDORID_SHIFT (0U)
-#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U)
+#define FFR_USBID_VENDORID_MASK   (0xFFFFU)
+#define FFR_USBID_VENDORID_SHIFT  (0U)
+#define FFR_USBID_PRODUCTID_MASK  (0xFFFF0000U)
 #define FFR_USBID_PRODUCTID_SHIFT (16U)
 
 typedef struct _cmpa_cfg_info
@@ -150,16 +152,16 @@ typedef struct _cmpa_key_store_header
     uint8_t reserved[4];
 } cmpa_key_store_header_t;
 
-#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U)
-#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U)
-#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U)
+#define FFR_SYSTEM_SPEED_CODE_MASK             (0x3U)
+#define FFR_SYSTEM_SPEED_CODE_SHIFT            (0U)
+#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ   (0x0U)
 #define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U)
 #define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U)
 #define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U)
 
-#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU)
-#define FFR_PERIPHERALCFG_PERI_SHIFT (0U)
-#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U)
+#define FFR_PERIPHERALCFG_PERI_MASK    (0x7FFFFFFFU)
+#define FFR_PERIPHERALCFG_PERI_SHIFT   (0U)
+#define FFR_PERIPHERALCFG_COREEN_MASK  (0x10000000U)
 #define FFR_PERIPHERALCFG_COREEN_SHIFT (31U)
 
 typedef struct _nmpa_cfg_info
@@ -226,36 +228,161 @@ typedef enum _ffr_bank_type
 extern "C" {
 #endif
 
-/*! Generic APIs for FFR */
+/*!
+ * @name FFR APIs
+ * @{
+ */
+
+/*!
+ * @brief Initializes the global FFR properties structure members.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ */
 status_t FFR_Init(flash_config_t *config);
-status_t FFR_Deinit(flash_config_t *config);
 
-/*! APIs to access CFPA pages */
-status_t FFR_CustomerPagesInit(flash_config_t *config);
+/*!
+ * @brief Enable firewall for all flash banks.
+ *
+ * CFPA, CMPA, and NMPA flash areas region will be locked, After this function executed;
+ * Unless the board is reset again.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ *
+ * @retval #kStatus_FLASH_Success An invalid argument is provided.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ */
+status_t FFR_Lock_All(flash_config_t *config);
+
+/*!
+ * @brief APIs to access CFPA pages
+ *
+ * This routine will erase CFPA and program the CFPA page with passed data.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param page_data A pointer to the source buffer of data that is to be programmed
+ *        into the CFPA.
+ * @param valid_len The length, given in bytes, to be programmed.
+ *
+ * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked.
+ * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page.
+ */
 status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len);
-/*! Read data stored in 'Customer In-field Page'. */
+
+/*!
+ * @brief APIs to access CFPA pages
+ *
+ * Generic read function, used by customer to read data stored in 'Customer In-field Page'.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param pData A pointer to the dest buffer of data that is to be read from 'Customer In-field Page'.
+ * @param offset An offset from the 'Customer In-field Page' start address.
+ * @param len The length, given in bytes, to be read.
+ *
+ * @retval #kStatus_FLASH_Success Get data from 'Customer In-field Page'.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_CommandFailure access error.
+ */
 status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
 
-/*! APIs to access CMPA pages */
-bool FFR_IsCmpaCfgPageUpdateInProgress(flash_config_t *config);
-status_t FFR_RecoverCmpaCfgPage(flash_config_t *config);
-status_t FFR_ProcessCmpaCfgPageUpdate(flash_config_t *config, cmpa_prog_process_t option);
+/*!
+ * @brief APIs to access CMPA pages
+ *
+ * This routine will erase "customer factory page" and program the page with passed data.
+ * If 'seal_part' parameter is TRUE then the routine will compute SHA256 hash of
+ * the page contents and then programs the pages.
+ * 1.During development customer code uses this API with 'seal_part' set to FALSE.
+ * 2.During manufacturing this parameter should be set to TRUE to seal the part
+ * from further modifications
+ * 3.This routine checks if the page is sealed or not. A page is said to be sealed if
+ * the SHA256 value in the page has non-zero value. On boot ROM locks the firewall for
+ * the region if hash is programmed anyways. So, write/erase commands will fail eventually.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param page_data A pointer to the source buffer of data that is to be programmed
+ *        into the "customer factory page".
+ * @param seal_part Set fasle for During development customer code.
+ *
+ * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CMPA.
+ * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline.
+ * @retval kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_CommandFailure access error.
+ */
 status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part);
-/*! Read data stored in 'Customer Factory CFG Page'. */
+
+/*!
+ * @brief APIs to access CMPA page
+ *
+ * Read data stored in 'Customer Factory CFG Page'.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param pData A pointer to the dest buffer of data that is to be read
+ *            from the Customer Factory CFG Page.
+ * @param offset Address offset relative to the CMPA area.
+ * @param len The length, given in bytes to be read.
+ *
+ * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'.
+ * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline.
+ * @retval kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_CommandFailure access error.
+ */
 status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
+
+/*!
+ * @brief APIs to access CMPA page
+ *
+ * 1.SW should use this API routine to get the UUID of the chip.
+ * 2.Calling routine should pass a pointer to buffer which can hold 128-bit value.
+ */
+status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid);
+
+/*!
+ * @brief This routine writes the 3 pages allocated for Key store data,
+ *
+ * 1.Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state.
+ * 2.Optional routines to set individual data members (activation code, key codes etc) to construct
+ * the key store structure in RAM before committing it to IFR/FFR.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param pKeyStore A Pointer to the 3 pages allocated for Key store data.
+ *        that will be written to 'customer factory page'.
+ *
+ * @retval #kStatus_FLASH_Success The key were programed successfully into FFR.
+ * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline.
+ * @retval kStatus_FTFx_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_CommandFailure access error.
+ */
 status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore);
+
+/*!
+ * @brief Get/Read Key store code routines
+ *
+ * 1. Calling code should pass buffer pointer which can hold activation code 1192 bytes.
+ * 2. Check if flash aperture is small or regular and read the data appropriately.
+ */
 status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode);
+
+/*!
+ * @brief Get/Read Key store code routines
+ *
+ * 1. Calling code should pass buffer pointer which can hold key code 52 bytes.
+ * 2. Check if flash aperture is small or regular and read the data appropriately.
+ * 3. keyIndex specifies which key code is read.
+ */
 status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex);
 
-/*! APIs to access NMPA pages */
-status_t FFR_NxpAreaCheckIntegrity(flash_config_t *config);
-status_t FFR_GetRompatchData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
-/*! Read data stored in 'NXP Manufacuring Programmed CFG Page'. */
-status_t FFR_GetManufactureData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
-status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid);
+/*@}*/
 
 #ifdef __cplusplus
 }
 #endif
 
+/*@}*/
+
 #endif /*! __FSL_FLASH_FFR_H_ */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_kbp.h

@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2020-2021, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IAP_KBP_H_
+#define _FSL_IAP_KBP_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup kb_driver
+ * @{
+ */
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief ROM API status group number */
+#define kStatusGroup_RomApi (108U)
+
+/*! @brief ROM API status codes. */
+enum
+{
+    kStatus_RomApiExecuteCompleted = kStatus_Success, /*!< ROM successfully process the whole sb file/boot image.*/
+    kStatus_RomApiNeedMoreData =
+        MAKE_STATUS(kStatusGroup_RomApi, 1), /*!< ROM needs more data to continue processing the boot image.*/
+    kStatus_RomApiBufferSizeNotEnough =
+        MAKE_STATUS(kStatusGroup_RomApi,
+                    2), /*!< The user buffer is not enough for use by Kboot during execution of the operation.*/
+    kStatus_RomApiInvalidBuffer =
+        MAKE_STATUS(kStatusGroup_RomApi, 3), /*!< The user buffer is not ok for sbloader or authentication.*/
+};
+
+/*!
+ *  @brief Details of the operation to be performed by the ROM.
+ *
+ * The #kRomAuthenticateImage operation requires the entire signed image to be
+ * available to the application.
+ */
+typedef enum _kb_operation
+{
+    kRomAuthenticateImage = 1, /*!< Authenticate a signed image.*/
+    kRomLoadImage         = 2, /*!< Load SB file.*/
+    kRomOperationCount    = 3,
+} kb_operation_t;
+
+/*!
+ * @brief Security constraint flags, Security profile flags.
+ */
+enum _kb_security_profile
+{
+    kKbootMinRSA4096 = (1 << 16),
+};
+
+/*!
+ * @brief Memory region definition.
+ */
+typedef struct _kb_region
+{
+    uint32_t address;
+    uint32_t length;
+} kb_region_t;
+
+/*!
+ * @brief User-provided options passed into kb_init().
+ *
+ * The buffer field is a pointer to memory provided by the caller for use by
+ * Kboot during execution of the operation. Minimum size is the size of each
+ * certificate in the chain plus 432 bytes additional per certificate.
+ *
+ * The profile field is a mask that specifies which features are required in
+ * the SB file or image being processed. This includes the minimum AES and RSA
+ * key sizes. See the _kb_security_profile enum for profile mask constants.
+ * The image being loaded or authenticated must match the profile or an error will
+ * be returned.
+ *
+ * minBuildNumber is an optional field that can be used to prevent version
+ * rollback. The API will check the build number of the image, and if it is less
+ * than minBuildNumber will fail with an error.
+ *
+ * maxImageLength is used to verify the offsetToCertificateBlockHeaderInBytes
+ * value at the beginning of a signed image. It should be set to the length of
+ * the SB file. If verifying an image in flash, it can be set to the internal
+ * flash size or a large number like 0x10000000.
+ *
+ * userRHK can optionally be used by the user to override the RHK in IFR. If
+ * userRHK is not NULL, it points to a 32-byte array containing the SHA-256 of
+ * the root certificate's RSA public key.
+ *
+ * The regions field points to an array of memory regions that the SB file being
+ * loaded is allowed to access. If regions is NULL, then all memory is
+ * accessible by the SB file. This feature is required to prevent a malicious
+ * image from erasing good code or RAM contents while it is being loaded, only
+ * for us to find that the image is inauthentic when we hit the end of the
+ * section.
+ *
+ * overrideSBBootSectionID lets the caller override the default section of the
+ * SB file that is processed during a kKbootLoadSB operation. By default,
+ * the section specified in the firstBootableSectionID field of the SB header
+ * is loaded. If overrideSBBootSectionID is non-zero, then the section with
+ * the given ID will be loaded instead.
+ *
+ * The userSBKEK field lets a user provide their own AES-256 key for unwrapping
+ * keys in an SB file during the kKbootLoadSB operation. userSBKEK should point
+ * to a 32-byte AES-256 key. If userSBKEK is NULL then the IFR SBKEK will be used.
+ * After kb_init() returns, the caller should zero out the data pointed to by
+ * userSBKEK, as the API will have installed the key in the CAU3.
+ */
+
+typedef struct _kb_load_sb
+{
+    uint32_t profile;
+    uint32_t minBuildNumber;
+    uint32_t overrideSBBootSectionID;
+    uint32_t *userSBKEK;
+    uint32_t regionCount;
+    const kb_region_t *regions;
+} kb_load_sb_t;
+
+typedef struct _kb_authenticate
+{
+    uint32_t profile;
+    uint32_t minBuildNumber;
+    uint32_t maxImageLength;
+    uint32_t *userRHK;
+} kb_authenticate_t;
+
+typedef struct _kb_options
+{
+    uint32_t version; /*!< Should be set to kKbootApiVersion.*/
+    uint8_t *buffer;  /*!< Caller-provided buffer used by Kboot.*/
+    uint32_t bufferLength;
+    kb_operation_t op;
+    union
+    {
+        kb_authenticate_t authenticate; /*! Settings for kKbootAuthenticate operation.*/
+        kb_load_sb_t loadSB;            /*! Settings for kKbootLoadSB operation.*/
+    };
+} kb_options_t;
+
+/*!
+ * @brief Interface to memory operations for one region of memory.
+ */
+typedef struct _memory_region_interface
+{
+    status_t (*init)(void);
+    status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer);
+    status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer);
+    status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern);
+    status_t (*flush)(void);
+    status_t (*erase)(uint32_t address, uint32_t length);
+    status_t (*config)(uint32_t *buffer);
+    status_t (*erase_all)(void);
+} memory_region_interface_t;
+
+/*!
+ * @brief Structure of a memory map entry.
+ */
+typedef struct _memory_map_entry
+{
+    uint32_t startAddress;
+    uint32_t endAddress;
+    uint32_t memoryProperty;
+    uint32_t memoryId;
+    const memory_region_interface_t *memoryInterface;
+} memory_map_entry_t;
+
+typedef struct _kb_opaque_session_ref
+{
+    kb_options_t context;
+    bool cau3Initialized;
+    memory_map_entry_t *memoryMap;
+} kb_session_ref_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initialize ROM API for a given operation.
+ *
+ * Inits the ROM API based on the options provided by the application in the second
+ * argument. Every call to rom_init() should be paired with a call to rom_deinit().
+ *
+ * @retval #kStatus_Success API was executed successfully.
+ * @retval #kStatus_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_RomApiBufferSizeNotEnough The user buffer is not enough for use by Kboot during execution of the
+ * operation.
+ * @retval #kStatus_RomApiInvalidBuffer The user buffer is not ok for sbloader or authentication.
+ * @retval #kStatus_SKBOOT_Fail Return the failed status of secure boot.
+ * @retval #kStatus_SKBOOT_KeyStoreMarkerInvalid The key code for the particular PRINCE region is not present in the
+ * keystore
+ * @retval #kStatus_SKBOOT_Success Return the successful status of secure boot.
+ */
+status_t kb_init(kb_session_ref_t **session, const kb_options_t *options);
+
+/*!
+ * @brief Cleans up the ROM API context.
+ *
+ * After this call, the context parameter can be reused for another operation
+ * by calling rom_init() again.
+ *
+ * @retval #kStatus_Success API was executed successfully
+ */
+status_t kb_deinit(kb_session_ref_t *session);
+
+/*!
+ * Perform the operation configured during init.
+ *
+ * This application must call this API repeatedly, passing in sequential chunks of
+ * data from the boot image (SB file) that is to be processed. The ROM will perform
+ * the selected operation on this data and return. The application may call this
+ * function with as much or as little data as it wishes, which can be used to select
+ * the granularity of time given to the application in between executing the operation.
+ *
+ * @param session Current ROM context pointer.
+ * @param data Buffer of boot image data provided to the ROM by the application.
+ * @param dataLength Length in bytes of the data in the buffer provided to the ROM.
+ *
+ * @retval #kStatus_Success ROM successfully process the part of sb file/boot image.
+ * @retval #kStatus_RomApiExecuteCompleted ROM successfully process the whole sb file/boot image.
+ * @retval #kStatus_Fail An error occurred while executing the operation.
+ * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to
+ * continue processing the boot image.
+ * @retval #kStatus_RomApiBufferSizeNotEnough user buffer is not enough for
+ * use by Kboot during execution of the operation.
+ */
+status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif /* _FSL_IAP_KBP_H_ */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_skboot_authenticate.h

@@ -0,0 +1,77 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_IAP_SKBOOT_AUTHENTICATE_H_
+#define _FSL_IAP_SKBOOT_AUTHENTICATE_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup skboot_authenticate
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief SKBOOT return status*/
+typedef enum _skboot_status
+{
+    kStatus_SKBOOT_Success               = 0x5ac3c35au, /*!< SKBOOT return success status.*/
+    kStatus_SKBOOT_Fail                  = 0xc35ac35au, /*!< SKBOOT return fail status.*/
+    kStatus_SKBOOT_InvalidArgument       = 0xc35a5ac3u, /*!< SKBOOT return invalid argument status.*/
+    kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< SKBOOT return Keystore invalid Marker status.*/
+    kStatus_SKBOOT_HashcryptFinishedWithStatusSuccess =
+        0xc15a5ac3, /*!< SKBOOT return Hashcrypt finished with the success status.*/
+    kStatus_SKBOOT_HashcryptFinishedWithStatusFail =
+        0xc15a5acb, /*!< SKBOOT return Hashcrypt finished with the fail status.*/
+} skboot_status_t;
+
+/*! @brief Secure bool flag*/
+typedef enum _secure_bool
+{
+    kSECURE_TRUE                       = 0xc33cc33cU, /*!< Secure true flag.*/
+    kSECURE_FALSE                      = 0x5aa55aa5U, /*!< Secure false flag.*/
+    kSECURE_CALLPROTECT_SECURITY_FLAGS = 0xc33c5aa5U, /*!< Secure call protect the security flag.*/
+    kSECURE_CALLPROTECT_IS_APP_READY   = 0x5aa5c33cU, /*!< Secure call protect the app is ready flag.*/
+    kSECURE_TRACKER_VERIFIED           = 0x55aacc33U, /*!< Secure tracker verified flag.*/
+} secure_bool_t;
+
+/*******************************************************************************
+ * Externs
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Authenticate entry function with ARENA allocator init
+ *
+ * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface
+ */
+skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified);
+
+/*!
+ * @brief Interface for image authentication API
+ */
+void HASH_IRQHandler(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif /* _FSL_IAP_SKBOOT_AUTHENTICATE_H_ */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2021 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -61,9 +61,9 @@ void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connect
     /* extract pmux to be used */
     pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT;
     /*  extract function number */
-    output_id = ((uint32_t)(connection)) & 0xffffU;
+    output_id = ((uint32_t)(connection)) & ((1UL << PMUX_SHIFT) - 1U);
     /* programm signal */
-    *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4)) = output_id;
+    *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4U)) = output_id;
 }
 
 #if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA)
@@ -81,20 +81,34 @@ void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connect
 void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable)
 {
     uint32_t ena_id;
+    uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U;
     uint32_t bit_offset;
 
+#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX
+    uint32_t chmux_offset;
+    uint32_t chmux_value;
+
+    /* Only enable need to update channel mux */
+    if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U))
+    {
+        chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1UL << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1UL);
+        chmux_value  = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1UL << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1UL);
+        *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value;
+    }
+    ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U;
+#endif
     /* extract enable register to be used */
-    ena_id = ((uint32_t)(signal)) >> ENA_SHIFT;
+    ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask;
     /* extract enable bit offset */
-    bit_offset = ((uint32_t)(signal)) & 0xfU;
+    bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U);
     /* set signal */
     if (enable)
     {
-        *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1U << bit_offset);
+        *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset);
     }
     else
     {
-        *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1U << bit_offset);
+        *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset);
     }
 }
 #endif

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2021 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -27,8 +27,8 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief Group interrupt driver version for SDK */
-#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
-                                                            /*@}*/
+#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
+/*@}*/
 
 /*******************************************************************************
  * API

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux_connections.h

@@ -28,143 +28,149 @@
  */
 
 /*! @brief Periphinmux IDs */
-#define SCT0_INMUX0 0x00U
-#define TIMER0CAPTSEL0 0x20U
-#define TIMER1CAPTSEL0 0x40U
-#define TIMER2CAPTSEL0 0x60U
-#define PINTSEL0 0xC0U
-#define DMA0_ITRIG_INMUX0 0xE0U
-#define DMA0_OTRIG_INMUX0 0x160U
-#define FREQMEAS_REF_REG 0x180U
+#define SCT0_INMUX0         0x00U
+#define TIMER0CAPTSEL0      0x20U
+#define TIMER1CAPTSEL0      0x40U
+#define TIMER2CAPTSEL0      0x60U
+#define PINTSEL_PMUX_ID     0xC0U
+#define PINTSEL0            0xC0U
+#define DMA0_ITRIG_INMUX0   0xE0U
+#define DMA0_OTRIG_INMUX0   0x160U
+#define FREQMEAS_REF_REG    0x180U
 #define FREQMEAS_TARGET_REG 0x184U
-#define TIMER3CAPTSEL0 0x1A0U
-#define TIMER4CAPTSEL0 0x1C0U
-#define PINTSECSEL0 0x1E0U
-#define DMA1_ITRIG_INMUX0 0x200U
-#define DMA1_OTRIG_INMUX0 0x240U
-#define PMUX_SHIFT 20U
+#define TIMER3CAPTSEL0      0x1A0U
+#define TIMER4CAPTSEL0      0x1C0U
+#define PINTSECSEL0         0x1E0U
+#define DMA1_ITRIG_INMUX0   0x200U
+#define DMA1_OTRIG_INMUX0   0x240U
+#define DMA0_REQ_ENA_ID     0x740U
+#define DMA1_REQ_ENA_ID     0x760U
+#define DMA0_ITRIG_ENA_ID   0x780U
+#define DMA1_ITRIG_ENA_ID   0x7A0U
+#define ENA_SHIFT           8U
+#define PMUX_SHIFT          20U
 
 /*! @brief INPUTMUX connections type */
 typedef enum _inputmux_connection_t
 {
     /*!< SCT0 INMUX. */
-    kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_SctGpi0ToSct0         = 0U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_SctGpi1ToSct0         = 1U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_SctGpi2ToSct0         = 2U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_SctGpi3ToSct0         = 3U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_SctGpi4ToSct0         = 4U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_SctGpi5ToSct0         = 5U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_SctGpi6ToSct0         = 6U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_SctGpi7ToSct0         = 7U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToSct0       = 8U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToSct0       = 9U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToSct0       = 10U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M0ToSct0       = 11U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToSct0       = 12U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_AdcIrqToSct0          = 13U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_GpiointBmatchToSct0   = 14U + (SCT0_INMUX0 << PMUX_SHIFT),
     kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_INMUX0 << PMUX_SHIFT),
     kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_CompOutToSct0         = 17U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_I2sSharedSck0ToSct0   = 18U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_I2sSharedSck1ToSct0   = 19U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_I2sSharedWs0ToSct0    = 20U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_I2sSharedWs1ToSct0    = 21U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_ArmTxevToSct0         = 22U + (SCT0_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_DebugHaltedToSct0     = 23U + (SCT0_INMUX0 << PMUX_SHIFT),
 
     /*!< TIMER0 CAPTSEL. */
-    kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp17ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp18ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp0ToTimer0Captsel      = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp1ToTimer0Captsel      = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp2ToTimer0Captsel      = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp3ToTimer0Captsel      = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp4ToTimer0Captsel      = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp5ToTimer0Captsel      = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp6ToTimer0Captsel      = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp7ToTimer0Captsel      = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp8ToTimer0Captsel      = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp9ToTimer0Captsel      = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp10ToTimer0Captsel     = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp11ToTimer0Captsel     = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp12ToTimer0Captsel     = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp13ToTimer0Captsel     = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp14ToTimer0Captsel     = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp15ToTimer0Captsel     = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp16ToTimer0Captsel     = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp17ToTimer0Captsel     = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp18ToTimer0Captsel     = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp19ToTimer0Captsel     = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
     kINPUTMUX_Usb0FrameToggleToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
     kINPUTMUX_Usb1FrameToggleToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CompOutToTimer0Captsel         = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_I2sSharedWs0ToTimer0Captsel    = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_I2sSharedWs1ToTimer0Captsel    = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
 
     /*!< TIMER1 CAPTSEL. */
-    kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp17ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp18ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp0ToTimer1Captsel      = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp1ToTimer1Captsel      = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp2ToTimer1Captsel      = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp3ToTimer1Captsel      = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp4ToTimer1Captsel      = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp5ToTimer1Captsel      = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp6ToTimer1Captsel      = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp7ToTimer1Captsel      = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp8ToTimer1Captsel      = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp9ToTimer1Captsel      = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp10ToTimer1Captsel     = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp11ToTimer1Captsel     = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp12ToTimer1Captsel     = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp13ToTimer1Captsel     = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp14ToTimer1Captsel     = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp15ToTimer1Captsel     = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp16ToTimer1Captsel     = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp17ToTimer1Captsel     = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp18ToTimer1Captsel     = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp19ToTimer1Captsel     = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
     kINPUTMUX_Usb0FrameToggleToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
     kINPUTMUX_Usb1FrameToggleToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CompOutToTimer1Captsel         = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_I2sSharedWs0ToTimer1Captsel    = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_I2sSharedWs1ToTimer1Captsel    = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
 
     /*!< TIMER2 CAPTSEL. */
-    kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp17ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp18ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp0ToTimer2Captsel      = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp1ToTimer2Captsel      = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp2ToTimer2Captsel      = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp3ToTimer2Captsel      = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp4ToTimer2Captsel      = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp5ToTimer2Captsel      = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp6ToTimer2Captsel      = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp7ToTimer2Captsel      = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp8ToTimer2Captsel      = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp9ToTimer2Captsel      = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp10ToTimer2Captsel     = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp11ToTimer2Captsel     = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp12ToTimer2Captsel     = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp13ToTimer2Captsel     = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp14ToTimer2Captsel     = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp15ToTimer2Captsel     = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp16ToTimer2Captsel     = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp17ToTimer2Captsel     = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp18ToTimer2Captsel     = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp19ToTimer2Captsel     = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
     kINPUTMUX_Usb0FrameToggleToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
     kINPUTMUX_Usb1FrameToggleToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CompOutToTimer2Captsel         = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_I2sSharedWs0ToTimer2Captsel    = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_I2sSharedWs1ToTimer2Captsel    = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
 
     /*!< Pin interrupt select. */
-    kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin0ToPintsel  = 0U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin1ToPintsel  = 1U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin2ToPintsel  = 2U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin3ToPintsel  = 3U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin4ToPintsel  = 4U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin5ToPintsel  = 5U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin6ToPintsel  = 6U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin7ToPintsel  = 7U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin8ToPintsel  = 8U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin9ToPintsel  = 9U + (PINTSEL0 << PMUX_SHIFT),
     kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL0 << PMUX_SHIFT),
     kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL0 << PMUX_SHIFT),
     kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT),
@@ -187,16 +193,16 @@ typedef enum _inputmux_connection_t
     kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT),
     kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL0 << PMUX_SHIFT),
     kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin0ToPintsel  = 32U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin1ToPintsel  = 33U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin2ToPintsel  = 34U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin3ToPintsel  = 35U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin4ToPintsel  = 36U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin5ToPintsel  = 37U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin6ToPintsel  = 38U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin7ToPintsel  = 39U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin8ToPintsel  = 40U + (PINTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin9ToPintsel  = 41U + (PINTSEL0 << PMUX_SHIFT),
     kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT),
     kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT),
     kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT),
@@ -221,33 +227,33 @@ typedef enum _inputmux_connection_t
     kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT),
 
     /*!< DMA0 Input trigger. */
-    kINPUTMUX_PinInt0ToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_PinInt1ToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_PinInt2ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_PinInt3ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_CompOutToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Otrig0ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Otrig1ToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Otrig2ToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Otrig3ToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_PinInt0ToDma0     = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_PinInt1ToDma0     = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_PinInt2ToDma0     = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_PinInt3ToDma0     = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToDma0   = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToDma0   = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToDma0   = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M1ToDma0   = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToDma0   = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToDma0   = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M0ToDma0   = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M1ToDma0   = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToDma0   = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToDma0   = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_CompOutToDma0     = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Otrig0ToDma0      = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Otrig1ToDma0      = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Otrig2ToDma0      = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Otrig3ToDma0      = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
     kINPUTMUX_Sct0DmaReq0ToDma0 = 19U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
     kINPUTMUX_Sct0DmaReq1ToDma0 = 20U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_HashDmaRxToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_HashDmaRxToDma0   = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
 
     /*!< DMA0 output trigger. */
-    kINPUTMUX_Dma0Hash0TxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Dma0HsLspiRxTrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Dma0HsLspiTxTrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Dma0Hash0TxTrigoutToTriginChannels     = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Dma0HsLspiRxTrigoutToTriginChannels    = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Dma0HsLspiTxTrigoutToTriginChannels    = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
     kINPUTMUX_Dma0Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
     kINPUTMUX_Dma0Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
     kINPUTMUX_Dma0Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
@@ -264,94 +270,94 @@ typedef enum _inputmux_connection_t
     kINPUTMUX_Dma0Flexcomm6TxTrigoutToTriginChannels = 17U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
     kINPUTMUX_Dma0Flexcomm7RxTrigoutToTriginChannels = 18U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
     kINPUTMUX_Dma0Flexcomm7TxTrigoutToTriginChannels = 19U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Dma0Adc0Ch0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Dma0Adc0Ch1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Dma0Adc0Ch0TrigoutToTriginChannels     = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Dma0Adc0Ch1TrigoutToTriginChannels     = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
 
     /*!< Selection for frequency measurement reference clock. */
     kINPUTMUX_ExternOscToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT),
-    kINPUTMUX_Fro12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT),
-    kINPUTMUX_Fro96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT),
-    kINPUTMUX_WdtOscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT),
-    kINPUTMUX_32KhzOscToFreqmeasRef= 4u + (FREQMEAS_REF_REG << PMUX_SHIFT),
-    kINPUTMUX_MainClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT),
-    kINPUTMUX_FreqmeGpioClk_aRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT),
-    kINPUTMUX_FreqmeGpioClk_bRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Fro12MhzToFreqmeasRef  = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_Fro96MhzToFreqmeasRef  = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_WdtOscToFreqmeasRef    = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_32KhzOscToFreqmeasRef  = 4u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_MainClkToFreqmeasRef   = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_FreqmeGpioClk_aRef     = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT),
+    kINPUTMUX_FreqmeGpioClk_bRef     = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT),
 
-   /*!< Selection for frequency measurement target clock. */
+    /*!< Selection for frequency measurement target clock. */
     kINPUTMUX_ExternOscToFreqmeasTarget = 0U + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
-    kINPUTMUX_Fro12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
-    kINPUTMUX_Fro96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
-    kINPUTMUX_WdtOscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
-    kINPUTMUX_32KhzOscToFreqmeasTarget= 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
-    kINPUTMUX_MainClkToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
-    kINPUTMUX_FreqmeGpioClk_aTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
-    kINPUTMUX_FreqmeGpioClk_bTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
+    kINPUTMUX_Fro12MhzToFreqmeasTarget  = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
+    kINPUTMUX_Fro96MhzToFreqmeasTarget  = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
+    kINPUTMUX_WdtOscToFreqmeasTarget    = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
+    kINPUTMUX_32KhzOscToFreqmeasTarget  = 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
+    kINPUTMUX_MainClkToFreqmeasTarget   = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
+    kINPUTMUX_FreqmeGpioClk_aTarget     = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
+    kINPUTMUX_FreqmeGpioClk_bTarget     = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
 
     /*!< TIMER3 CAPTSEL. */
-    kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp17ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp18ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp0ToTimer3Captsel      = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp1ToTimer3Captsel      = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp2ToTimer3Captsel      = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp3ToTimer3Captsel      = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp4ToTimer3Captsel      = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp5ToTimer3Captsel      = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp6ToTimer3Captsel      = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp7ToTimer3Captsel      = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp8ToTimer3Captsel      = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp9ToTimer3Captsel      = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp10ToTimer3Captsel     = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp11ToTimer3Captsel     = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp12ToTimer3Captsel     = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp13ToTimer3Captsel     = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp14ToTimer3Captsel     = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp15ToTimer3Captsel     = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp16ToTimer3Captsel     = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp17ToTimer3Captsel     = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp18ToTimer3Captsel     = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp19ToTimer3Captsel     = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
     kINPUTMUX_Usb0FrameToggleToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
     kINPUTMUX_Usb1FrameToggleToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CompOutToTimer3Captsel         = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_I2sSharedWs0ToTimer3Captsel    = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_I2sSharedWs1ToTimer3Captsel    = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
 
     /*!< Timer4 CAPTSEL. */
-    kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp17ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp18ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp0ToTimer4Captsel      = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp1ToTimer4Captsel      = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp2ToTimer4Captsel      = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp3ToTimer4Captsel      = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp4ToTimer4Captsel      = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp5ToTimer4Captsel      = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp6ToTimer4Captsel      = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp7ToTimer4Captsel      = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp8ToTimer4Captsel      = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp9ToTimer4Captsel      = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp10ToTimer4Captsel     = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp11ToTimer4Captsel     = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp12ToTimer4Captsel     = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp13ToTimer4Captsel     = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp14ToTimer4Captsel     = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp15ToTimer4Captsel     = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp16ToTimer4Captsel     = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp17ToTimer4Captsel     = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp18ToTimer4Captsel     = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CtimerInp19ToTimer4Captsel     = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
     kINPUTMUX_Usb0FrameToggleToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
     kINPUTMUX_Usb1FrameToggleToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
-    kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_CompOutToTimer4Captsel         = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_I2sSharedWs0ToTimer4Captsel    = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
+    kINPUTMUX_I2sSharedWs1ToTimer4Captsel    = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
 
     /*Pin interrupt secure select */
-    kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin0ToPintSecsel  = 0U + (PINTSECSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin1ToPintSecsel  = 1U + (PINTSECSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin2ToPintSecsel  = 2U + (PINTSECSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin3ToPintSecsel  = 3U + (PINTSECSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin4ToPintSecsel  = 4U + (PINTSECSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin5ToPintSecsel  = 5U + (PINTSECSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin6ToPintSecsel  = 6U + (PINTSECSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin7ToPintSecsel  = 7U + (PINTSECSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin8ToPintSecsel  = 8U + (PINTSECSEL0 << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin9ToPintSecsel  = 9U + (PINTSECSEL0 << PMUX_SHIFT),
     kINPUTMUX_GpioPort0Pin10ToPintSecsel = 10U + (PINTSECSEL0 << PMUX_SHIFT),
     kINPUTMUX_GpioPort0Pin11ToPintSecsel = 11U + (PINTSECSEL0 << PMUX_SHIFT),
     kINPUTMUX_GpioPort0Pin12ToPintSecsel = 12U + (PINTSECSEL0 << PMUX_SHIFT),
@@ -376,34 +382,115 @@ typedef enum _inputmux_connection_t
     kINPUTMUX_GpioPort0Pin31ToPintSecsel = 31U + (PINTSECSEL0 << PMUX_SHIFT),
 
     /*!< DMA1 Input trigger. */
-    kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Ctimer4M1ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Otrig0ToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Otrig1ToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Otrig2ToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Otrig3ToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_PinInt0ToDma1     = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_PinInt1ToDma1     = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_PinInt2ToDma1     = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_PinInt3ToDma1     = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToDma1   = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToDma1   = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToDma1   = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToDma1   = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Otrig0ToDma1      = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Otrig1ToDma1      = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Otrig2ToDma1      = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Otrig3ToDma1      = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
     kINPUTMUX_Sct0DmaReq0ToDma1 = 12U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
     kINPUTMUX_Sct0DmaReq1ToDma1 = 13U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_HashDmaRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_HashDmaRxToDma1   = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
 
     /*!< DMA1 output trigger. */
-    kINPUTMUX_Dma1Hash0TxTrigoutToTriginChannels = 0U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Dma1Hash0TxTrigoutToTriginChannels     = 0U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels    = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels    = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
     kINPUTMUX_Dma1Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
     kINPUTMUX_Dma1Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
     kINPUTMUX_Dma1Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
     kINPUTMUX_Dma1Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Dma1Flexcomm2RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
-    kINPUTMUX_Dma1Flexcomm2TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Dma1Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
+    kINPUTMUX_Dma1Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
 } inputmux_connection_t;
 
+/*! @brief INPUTMUX signal enable/disable type */
+typedef enum _inputmux_signal_t
+{
+    /*!< DMA0 REQ signal. */
+    kINPUTMUX_HashCryptToDmac0Ch0RequestEna    = 0U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm8RxToDmac0Ch2RequestEna  = 2U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm8TxToDmac0Ch3RequestEna  = 3U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm0RxToDmac0Ch4RequestEna  = 4U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm0TxToDmac0Ch5RequestEna  = 5U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm1RxToDmac0Ch6RequestEna  = 6U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm1TxToDmac0Ch7RequestEna  = 7U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm3RxToDmac0Ch8RequestEna  = 8U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm3TxToDmac0Ch9RequestEna  = 9U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm2RxToDmac0Ch10RequestEna = 10U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm2TxToDmac0Ch11RequestEna = 11U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm4RxToDmac0Ch12RequestEna = 12U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm4TxToDmac0Ch13RequestEna = 13U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm5RxToDmac0Ch14RequestEna = 14U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm5TxToDmac0Ch15RequestEna = 15U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm6RxToDmac0Ch16RequestEna = 16U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm6TxToDmac0Ch17RequestEna = 17U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm7RxToDmac0Ch18RequestEna = 18U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm7TxToDmac0Ch19RequestEna = 19U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Adc0FIFO0ToDmac0Ch21RequestEna   = 21U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Adc0FIFO1ToDmac0Ch22RequestEna   = 22U + (DMA0_REQ_ENA_ID << ENA_SHIFT),
+
+    /*!< DMA1 REQ signal. */
+    kINPUTMUX_HashCryptToDmac1Ch0RequestEna   = 0U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm8RxToDmac1Ch2RequestEna = 2U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm8TxToDmac1Ch3RequestEna = 3U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm0RxToDmac1Ch4RequestEna = 4U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm0TxToDmac1Ch5RequestEna = 5U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm1RxToDmac1Ch6RequestEna = 6U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm1TxToDmac1Ch7RequestEna = 7U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm3RxToDmac1Ch8RequestEna = 8U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Flexcomm3TxToDmac1Ch9RequestEna = 9U + (DMA1_REQ_ENA_ID << ENA_SHIFT),
+
+    /*!< DMA0 input trigger source enable. */
+    kINPUTMUX_Dmac0InputTriggerPint0Ena     = 0U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerPint1Ena     = 1U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerPint2Ena     = 2U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerPint3Ena     = 3U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerCtimer0M0Ena = 4U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerCtimer0M1Ena = 5U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerCtimer1M0Ena = 6U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerCtimer1M1Ena = 7U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerCtimer2M0Ena = 8U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerCtimer2M1Ena = 9U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerCtimer3M0Ena = 10U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerCtimer3M1Ena = 11U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerCtimer4M0Ena = 12U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerCtimer4M1Ena = 13U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerCompOutEna   = 14U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerDma0Out0Ena  = 15U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerDma0Out1Ena  = 16U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerDma0Out2Ena  = 17U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerDma0Out3Ena  = 18U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerSctDmac0Ena  = 19U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerSctDmac1Ena  = 20U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac0InputTriggerHashOutEna   = 21U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT),
+
+    /*!< DMA1 input trigger source enable. */
+    kINPUTMUX_Dmac1InputTriggerPint0Ena     = 0U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac1InputTriggerPint1Ena     = 1U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac1InputTriggerPint2Ena     = 2U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac1InputTriggerPint3Ena     = 3U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac1InputTriggerCtimer0M0Ena = 4U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac1InputTriggerCtimer0M1Ena = 5U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac1InputTriggerCtimer2M0Ena = 6U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac1InputTriggerCtimer4M0Ena = 7U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac1InputTriggerDma1Out0Ena  = 8U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac1InputTriggerDma1Out1Ena  = 9U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac1InputTriggerDma1Out2Ena  = 10U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac1InputTriggerDma1Out3Ena  = 11U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac1InputTriggerSctDmac0Ena  = 12U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac1InputTriggerSctDmac1Ena  = 13U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
+    kINPUTMUX_Dmac1InputTriggerHashOutEna   = 14U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT),
+} inputmux_signal_t;
+
+/*@}*/
+
 /*@}*/
 
 #endif /* _FSL_INPUTMUX_CONNECTIONS_ */

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iocon.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2021 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -29,8 +29,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief IOCON driver version 2.1.1. */
-#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*! @brief IOCON driver version. */
+#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
 /*@}*/
 
 /**
@@ -38,53 +38,57 @@
  */
 typedef struct _iocon_group
 {
-    uint32_t port : 8;      /* Pin port */
-    uint32_t pin : 8;       /* Pin number */
-    uint32_t ionumber : 8;  /* IO number */
-    uint32_t modefunc : 16; /* Function and mode */
+    uint8_t port;      /* Pin port */
+    uint8_t pin;       /* Pin number */
+    uint8_t ionumber;  /* IO number */
+    uint16_t modefunc; /* Function and mode */
 } iocon_group_t;
 
 /**
  * @brief IOCON function and mode selection definitions
  * @note See the User Manual for specific modes and functions supported by the various pins.
  */
+#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
+#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
+#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
+#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
+#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
+#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
+#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
+#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
 #if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4)
-#define IOCON_FUNC0 0x0  /*!< Selects pin function 0 */
-#define IOCON_FUNC1 0x1  /*!< Selects pin function 1 */
-#define IOCON_FUNC2 0x2  /*!< Selects pin function 2 */
-#define IOCON_FUNC3 0x3  /*!< Selects pin function 3 */
-#define IOCON_FUNC4 0x4  /*!< Selects pin function 4 */
-#define IOCON_FUNC5 0x5  /*!< Selects pin function 5 */
-#define IOCON_FUNC6 0x6  /*!< Selects pin function 6 */
-#define IOCON_FUNC7 0x7  /*!< Selects pin function 7 */
-#define IOCON_FUNC8 0x8  /*!< Selects pin function 8 */
-#define IOCON_FUNC9 0x9  /*!< Selects pin function 9 */
+#define IOCON_FUNC8  0x8 /*!< Selects pin function 8 */
+#define IOCON_FUNC9  0x9 /*!< Selects pin function 9 */
 #define IOCON_FUNC10 0xA /*!< Selects pin function 10 */
 #define IOCON_FUNC11 0xB /*!< Selects pin function 11 */
 #define IOCON_FUNC12 0xC /*!< Selects pin function 12 */
 #define IOCON_FUNC13 0xD /*!< Selects pin function 13 */
 #define IOCON_FUNC14 0xE /*!< Selects pin function 14 */
 #define IOCON_FUNC15 0xF /*!< Selects pin function 15 */
+#endif                   /* FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH */
+
 #if defined(IOCON_PIO_MODE_SHIFT)
-#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT)    /*!< No addition pin function */
+#define IOCON_MODE_INACT    (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */
 #define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */
-#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT)   /*!< Selects pull-up function */
+#define IOCON_MODE_PULLUP   (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */
 #define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */
 #endif
 
 #if defined(IOCON_PIO_I2CSLEW_SHIFT)
 #define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */
-#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT)  /*!< I2C Slew Rate Control */
+#define IOCON_I2C_MODE  (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */
+#define IOCON_I2C_SLEW  IOCON_I2C_MODE                   /*!< Deprecated name for #IOCON_I2C_MODE */
 #endif
 
 #if defined(IOCON_PIO_EGP_SHIFT)
 #define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */
-#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT)  /*!< I2C Slew Rate Control */
+#define IOCON_I2C_MODE  (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */
+#define IOCON_I2C_SLEW  IOCON_I2C_MODE               /*!< Deprecated name for #IOCON_I2C_MODE */
 #endif
 
 #if defined(IOCON_PIO_SLEW_SHIFT)
 #define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */
-#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT)     /*!< Driver Slew Rate Control */
+#define IOCON_SLEW_FAST     (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */
 #endif
 
 #if defined(IOCON_PIO_INVERT_SHIFT)
@@ -99,11 +103,11 @@ typedef struct _iocon_group
 
 #if defined(IOCON_PIO_FILTEROFF_SHIFT)
 #define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */
-#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT)  /*!< Input filter On for GPIO pins */
+#define IOCON_INPFILT_ON  (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */
 #endif
 
 #if defined(IOCON_PIO_I2CDRIVE_SHIFT)
-#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT)  /*!< Low drive, Output drive sink is 4 mA */
+#define IOCON_I2C_LOWDRIVER  (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */
 #define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */
 #endif
 
@@ -113,7 +117,7 @@ typedef struct _iocon_group
 
 #if defined(IOCON_PIO_I2CFILTER_SHIFT)
 #define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!<  I2C 50 ns glitch filter enabled */
-#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT)  /*!<  I2C 50 ns glitch filter not enabled,  */
+#define IOCON_I2CFILTER_ON  (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!<  I2C 50 ns glitch filter not enabled,  */
 #endif
 
 #if defined(IOCON_PIO_ASW_SHIFT)
@@ -127,96 +131,20 @@ typedef struct _iocon_group
 
 #if defined(IOCON_PIO_ECS_SHIFT)
 #define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */
-#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT)  /*!< Pull-up resistor is connected */
-#endif
-
-#if defined(IOCON_PIO_S_MODE_SHIFT)
-#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */
-#define IOCON_S_MODE_1CLK                                                                              \
-    (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \
-                                           */
-#define IOCON_S_MODE_2CLK                                                                               \
-    (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \
-                                           */
-#define IOCON_S_MODE_3CLK                                                                               \
-    (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \
-                                           */
-#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */
-#endif
-
-#if defined(IOCON_PIO_CLK_DIV_SHIFT)
-#define IOCON_CLKDIV(div) \
-    ((div)                \
-     << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
-#endif
-
-#else
-#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
-#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
-#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
-#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
-#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
-#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
-#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
-#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
-
-#if defined(IOCON_PIO_MODE_SHIFT)
-#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT)    /*!< No addition pin function */
-#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */
-#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT)   /*!< Selects pull-up function */
-#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */
-#endif
-
-#if defined(IOCON_PIO_I2CSLEW_SHIFT)
-#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */
-#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT)  /*!< I2C Slew Rate Control */
-#endif
-
-#if defined(IOCON_PIO_EGP_SHIFT)
-#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */
-#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT)  /*!< I2C Slew Rate Control */
-#endif
-
-#if defined(IOCON_PIO_INVERT_SHIFT)
-#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */
-#endif
-
-#if defined(IOCON_PIO_DIGIMODE_SHIFT)
-#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */
-#define IOCON_DIGITAL_EN \
-    (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */
-#endif
-
-#if defined(IOCON_PIO_FILTEROFF_SHIFT)
-#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */
-#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT)  /*!< Input filter On for GPIO pins */
-#endif
-
-#if defined(IOCON_PIO_I2CDRIVE_SHIFT)
-#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT)  /*!< Low drive, Output drive sink is 4 mA */
-#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */
-#endif
-
-#if defined(IOCON_PIO_OD_SHIFT)
-#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */
-#endif
-
-#if defined(IOCON_PIO_I2CFILTER_SHIFT)
-#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!<  I2C 50 ns glitch filter enabled */
-#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT)  /*!<  I2C 50 ns glitch filter not enabled */
+#define IOCON_ECS_ON  (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */
 #endif
 
 #if defined(IOCON_PIO_S_MODE_SHIFT)
 #define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */
 #define IOCON_S_MODE_1CLK                                                                              \
     (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \
-                                           */
+                                     */
 #define IOCON_S_MODE_2CLK                                                                               \
     (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \
-                                           */
+                                     */
 #define IOCON_S_MODE_3CLK                                                                               \
     (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \
-                                           */
+                                     */
 #define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */
 #endif
 
@@ -226,7 +154,6 @@ typedef struct _iocon_group
      << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
 #endif
 
-#endif
 #if defined(__cplusplus)
 extern "C" {
 #endif

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2020 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -69,7 +69,7 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the clock for LPADC instance. */
-    CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]);
+    (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Reset the module. */
@@ -119,7 +119,7 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)
     tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay)                /* Power up delay. */
              | ADC_CFG_REFSEL(config->referenceVoltageSource)   /* Reference voltage. */
              | ADC_CFG_PWRSEL(config->powerLevelMode)           /* Power configuration. */
-             | ADC_CFG_TPRICTRL(config->triggerPrioirtyPolicy); /* Trigger priority policy. */
+             | ADC_CFG_TPRICTRL(config->triggerPriorityPolicy); /* Trigger priority policy. */
     base->CFG = tmp32;
 
     /* ADCx_PAUSE. */
@@ -157,7 +157,7 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)
  *   config->powerUpDelay            = 0x80;
  *   config->referenceVoltageSource  = kLPADC_ReferenceVoltageAlt1;
  *   config->powerLevelMode          = kLPADC_PowerLevelAlt1;
- *   config->triggerPrioirtyPolicy   = kLPADC_TriggerPriorityPreemptImmediately;
+ *   config->triggerPriorityPolicy   = kLPADC_TriggerPriorityPreemptImmediately;
  *   config->enableConvPause         = false;
  *   config->convPauseDelay          = 0U;
  *   config->FIFO0Watermark          = 0U;
@@ -169,7 +169,7 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)
 void LPADC_GetDefaultConfig(lpadc_config_t *config)
 {
     /* Initializes the configure structure to zero. */
-    memset(config, 0, sizeof(*config));
+    (void)memset(config, 0, sizeof(*config));
 
 #if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN
     config->enableInternalClock = false;
@@ -186,7 +186,7 @@ void LPADC_GetDefaultConfig(lpadc_config_t *config)
     config->powerUpDelay            = 0x80;
     config->referenceVoltageSource  = kLPADC_ReferenceVoltageAlt1;
     config->powerLevelMode          = kLPADC_PowerLevelAlt1;
-    config->triggerPrioirtyPolicy   = kLPADC_TriggerPriorityPreemptImmediately;
+    config->triggerPriorityPolicy   = kLPADC_TriggerPriorityPreemptImmediately;
     config->enableConvPause         = false;
     config->convPauseDelay          = 0U;
 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
@@ -209,7 +209,7 @@ void LPADC_Deinit(ADC_Type *base)
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate the clock. */
-    CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]);
+    (void)CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
@@ -294,7 +294,10 @@ void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_
             | ADC_TCTRL_TDLY(config->delayPower)    /* Trigger delay select. */
             | ADC_TCTRL_TPRI(config->priority)      /* Trigger priority setting. */
 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
-            | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect)
+            | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect)
+#if !(defined(FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) && FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B)
+            | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect)
+#endif /* FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B  */
 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
         ;
     if (config->enableHardwareTrigger)
@@ -324,12 +327,12 @@ void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config)
     assert(config != NULL); /* Check if the input pointer is available. */
 
     /* Initializes the configure structure to zero. */
-    memset(config, 0, sizeof(*config));
+    (void)memset(config, 0, sizeof(*config));
 
     config->targetCommandId = 0U;
     config->delayPower      = 0U;
     config->priority        = 0U;
-#if defined(FSL_FEATURE_LPADC_FIFO_COUNT) && FSL_FEATURE_LPADC_FIFO_COUNT
+#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
     config->channelAFIFOSelect = 0U;
     config->channelBFIFOSelect = 0U;
 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
@@ -378,7 +381,7 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_
     }
 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */
 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
-    tmp32 |= ADC_CMDL_MODE(config->conversionResoultuionMode);
+    tmp32 |= ADC_CMDL_MODE(config->conversionResolutionMode);
 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
     base->CMD[commandId].CMDL = tmp32;
 
@@ -433,7 +436,7 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_
  *   config->hardwareCompareMode        = kLPADC_HardwareCompareDisabled;
  *   config->hardwareCompareValueHigh   = 0U;
  *   config->hardwareCompareValueLow    = 0U;
- *   config->conversionResoultuionMode  = kLPADC_ConversionResolutionStandard;
+ *   config->conversionResolutionMode  = kLPADC_ConversionResolutionStandard;
  *   config->enableWaitTrigger          = false;
  * endcode
  * param config Pointer to configuration structure.
@@ -443,7 +446,7 @@ void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config)
     assert(config != NULL); /* Check if the input pointer is available. */
 
     /* Initializes the configure structure to zero. */
-    memset(config, 0, sizeof(*config));
+    (void)memset(config, 0, sizeof(*config));
 
 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE
     config->sampleScaleMode = kLPADC_SampleFullScale;
@@ -459,7 +462,7 @@ void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config)
     config->hardwareCompareValueHigh   = 0U; /* No used. */
     config->hardwareCompareValueLow    = 0U; /* No used. */
 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
-    config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard;
+    config->conversionResolutionMode = kLPADC_ConversionResolutionStandard;
 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
 #if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG
     config->enableWaitTrigger = false;
@@ -477,7 +480,7 @@ void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config)
  * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction.
  *
  * param base LPADC peripheral base address.
- * bool enable switcher to the calibration function.
+ * param enable switcher to the calibration function.
  */
 void LPADC_EnableCalibration(ADC_Type *base, bool enable)
 {
@@ -539,7 +542,7 @@ void LPADC_DoAutoCalibration(ADC_Type *base)
     {
     }
     /* The valid bits of data are bits 14:3 in the RESFIFO register. */
-    LPADC_SetOffsetValue(base, (mLpadcResultConfigStruct.convValue) >> 3U);
+    LPADC_SetOffsetValue(base, (uint32_t)(mLpadcResultConfigStruct.convValue) >> 3UL);
     /* Disable the calibration function. */
     LPADC_EnableCalibration(base, false);
 

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2021 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -23,8 +23,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief LPADC driver version 2.1.1. */
-#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*! @brief LPADC driver version 2.5.1. */
+#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
 /*@}*/
 
 /*!
@@ -70,6 +70,42 @@ enum _lpadc_interrupt_enable
                                                                          requests when FOF1 flag is asserted. */
     kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK,      /*!< Configures ADC to generate watermark interrupt
                                                                          requests when RDY1 flag is asserted. */
+#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT)
+    kLPADC_TriggerExceptionInterruptEnable = ADC_IE_TEXC_IE_MASK, /*!< Configures ADC to generate trigger exception
+                                                                      interrupt. */
+    kLPADC_Trigger0CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 0UL),   /*!< Configures ADC to generate interrupt
+                                                                                when trigger 0 completion. */
+    kLPADC_Trigger1CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 1UL),   /*!< Configures ADC to generate interrupt
+                                                                                when trigger 1 completion. */
+    kLPADC_Trigger2CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 2UL),   /*!< Configures ADC to generate interrupt
+                                                                                when trigger 2 completion. */
+    kLPADC_Trigger3CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 3UL),   /*!< Configures ADC to generate interrupt
+                                                                                when trigger 3 completion. */
+    kLPADC_Trigger4CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 4UL),   /*!< Configures ADC to generate interrupt
+                                                                                when trigger 4 completion. */
+    kLPADC_Trigger5CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 5UL),   /*!< Configures ADC to generate interrupt
+                                                                                when trigger 5 completion. */
+    kLPADC_Trigger6CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 6UL),   /*!< Configures ADC to generate interrupt
+                                                                                when trigger 6 completion. */
+    kLPADC_Trigger7CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 7UL),   /*!< Configures ADC to generate interrupt
+                                                                                when trigger 7 completion. */
+    kLPADC_Trigger8CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 8UL),   /*!< Configures ADC to generate interrupt
+                                                                                when trigger 8 completion. */
+    kLPADC_Trigger9CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 9UL),   /*!< Configures ADC to generate interrupt
+                                                                                when trigger 9 completion. */
+    kLPADC_Trigger10CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 10UL), /*!< Configures ADC to generate interrupt
+                                                                              when trigger 10 completion. */
+    kLPADC_Trigger11CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 11UL), /*!< Configures ADC to generate interrupt
+                                                                              when trigger 11 completion. */
+    kLPADC_Trigger12CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 12UL), /*!< Configures ADC to generate interrupt
+                                                                              when trigger 12 completion. */
+    kLPADC_Trigger13CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 13UL), /*!< Configures ADC to generate interrupt
+                                                                              when trigger 13 completion. */
+    kLPADC_Trigger14CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 14UL), /*!< Configures ADC to generate interrupt
+                                                                              when trigger 14 completion. */
+    kLPADC_Trigger15CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 15UL), /*!< Configures ADC to generate interrupt
+                                                                              when trigger 15 completion. */
+#endif                                                                        /* FSL_FEATURE_LPADC_HAS_TSTAT */
 };
 #else
 /*!
@@ -95,6 +131,64 @@ enum _lpadc_interrupt_enable
 };
 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
 
+#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT)
+/*!
+ * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags.
+ */
+enum _lpadc_trigger_status_flags
+{
+    kLPADC_Trigger0InterruptedFlag  = 1UL << 0UL,  /*!< Trigger 0 is interrupted by a high priority exception. */
+    kLPADC_Trigger1InterruptedFlag  = 1UL << 1UL,  /*!< Trigger 1 is interrupted by a high priority exception. */
+    kLPADC_Trigger2InterruptedFlag  = 1UL << 2UL,  /*!< Trigger 2 is interrupted by a high priority exception. */
+    kLPADC_Trigger3InterruptedFlag  = 1UL << 3UL,  /*!< Trigger 3 is interrupted by a high priority exception. */
+    kLPADC_Trigger4InterruptedFlag  = 1UL << 4UL,  /*!< Trigger 4 is interrupted by a high priority exception. */
+    kLPADC_Trigger5InterruptedFlag  = 1UL << 5UL,  /*!< Trigger 5 is interrupted by a high priority exception. */
+    kLPADC_Trigger6InterruptedFlag  = 1UL << 6UL,  /*!< Trigger 6 is interrupted by a high priority exception. */
+    kLPADC_Trigger7InterruptedFlag  = 1UL << 7UL,  /*!< Trigger 7 is interrupted by a high priority exception. */
+    kLPADC_Trigger8InterruptedFlag  = 1UL << 8UL,  /*!< Trigger 8 is interrupted by a high priority exception. */
+    kLPADC_Trigger9InterruptedFlag  = 1UL << 9UL,  /*!< Trigger 9 is interrupted by a high priority exception. */
+    kLPADC_Trigger10InterruptedFlag = 1UL << 10UL, /*!< Trigger 10 is interrupted by a high priority exception. */
+    kLPADC_Trigger11InterruptedFlag = 1UL << 11UL, /*!< Trigger 11 is interrupted by a high priority exception. */
+    kLPADC_Trigger12InterruptedFlag = 1UL << 12UL, /*!< Trigger 12 is interrupted by a high priority exception. */
+    kLPADC_Trigger13InterruptedFlag = 1UL << 13UL, /*!< Trigger 13 is interrupted by a high priority exception. */
+    kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */
+    kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */
+
+    kLPADC_Trigger0CompletedFlag = 1UL << 16UL,  /*!< Trigger 0 is completed and
+                                                     trigger 0 has enabled completion interrupts. */
+    kLPADC_Trigger1CompletedFlag = 1UL << 17UL,  /*!< Trigger 1 is completed and
+                                                     trigger 1 has enabled completion interrupts. */
+    kLPADC_Trigger2CompletedFlag = 1UL << 18UL,  /*!< Trigger 2 is completed and
+                                                     trigger 2 has enabled completion interrupts. */
+    kLPADC_Trigger3CompletedFlag = 1UL << 19UL,  /*!< Trigger 3 is completed and
+                                                     trigger 3 has enabled completion interrupts. */
+    kLPADC_Trigger4CompletedFlag = 1UL << 20UL,  /*!< Trigger 4 is completed and
+                                                     trigger 4 has enabled completion interrupts. */
+    kLPADC_Trigger5CompletedFlag = 1UL << 21UL,  /*!< Trigger 5 is completed and
+                                                     trigger 5 has enabled completion interrupts. */
+    kLPADC_Trigger6CompletedFlag = 1UL << 22UL,  /*!< Trigger 6 is completed and
+                                                     trigger 6 has enabled completion interrupts. */
+    kLPADC_Trigger7CompletedFlag = 1UL << 23UL,  /*!< Trigger 7 is completed and
+                                                     trigger 7 has enabled completion interrupts. */
+    kLPADC_Trigger8CompletedFlag = 1UL << 24UL,  /*!< Trigger 8 is completed and
+                                                     trigger 8 has enabled completion interrupts. */
+    kLPADC_Trigger9CompletedFlag = 1UL << 25UL,  /*!< Trigger 9 is completed and
+                                                     trigger 9 has enabled completion interrupts. */
+    kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and
+                                                    trigger 10 has enabled completion interrupts. */
+    kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and
+                                                    trigger 11 has enabled completion interrupts. */
+    kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and
+                                                    trigger 12 has enabled completion interrupts. */
+    kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and
+                                                    trigger 13 has enabled completion interrupts. */
+    kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and
+                                                    trigger 14 has enabled completion interrupts. */
+    kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and
+                                                    trigger 15 has enabled completion interrupts. */
+};
+#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */
+
 /*!
  * @brief Define enumeration of sample scale mode.
  *
@@ -119,8 +213,8 @@ typedef enum _lpadc_sample_channel_mode
     kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */
     kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */
 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF
-    kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minue side. */
-    kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minue side. */
+    kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minus side. */
+    kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minus side. */
 #elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE
     kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */
     kLPADC_SampleChannelDualSingleEndBothSide =
@@ -179,11 +273,12 @@ typedef enum _lpadc_hardware_compare_mode
     kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */
 } lpadc_hardware_compare_mode_t;
 
+#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
 /*!
  * @brief Define enumeration of conversion resolution mode.
  *
  * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to
- * #_lpadc_sample_channel_mode
+ * #lpadc_sample_channel_mode_t
  */
 typedef enum _lpadc_conversion_resolution_mode
 {
@@ -192,6 +287,7 @@ typedef enum _lpadc_conversion_resolution_mode
     kLPADC_ConversionResolutionHigh = 1U,     /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit
                                                    conversion with 2’s complement output. */
 } lpadc_conversion_resolution_mode_t;
+#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
 
 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
 /*!
@@ -260,7 +356,7 @@ typedef enum _lpadc_trigger_priority_policy
 } lpadc_trigger_priority_policy_t;
 
 /*!
- * @beief LPADC global configuration.
+ * @brief LPADC global configuration.
  *
  * This structure would used to keep the settings for initialization.
  */
@@ -291,8 +387,8 @@ typedef struct
     lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for
                                                                   conversions.*/
     lpadc_power_level_mode_t powerLevelMode;                 /*!< Power Configuration Selection. */
-    lpadc_trigger_priority_policy_t triggerPrioirtyPolicy; /*!< Control how higher priority triggers are handled, see to
-                                                                #lpadc_trigger_priority_policy_mode_t. */
+    lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to
+                                                                lpadc_trigger_priority_policy_t. */
     bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during
                                command execution sequencing between LOOP iterations, between commands in a sequence, and
                                between conversions when command is executing in "Compare Until True" configuration. */
@@ -341,8 +437,8 @@ typedef struct
     uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */
     uint32_t hardwareCompareValueLow;  /*!< Compare Value Low. The available value range is in 16-bit. */
 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
-    lpadc_conversion_resolution_mode_t conversionResoultuionMode; /*!< Conversion resolution mode. */
-#endif                                                            /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
+    lpadc_conversion_resolution_mode_t conversionResolutionMode; /*!< Conversion resolution mode. */
+#endif                                                           /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
 #if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG
     bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be
                                  automatically executed; when enabled, the active trigger must be asserted again before
@@ -413,7 +509,7 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config);
  *   config->powerUpDelay            = 0x80;
  *   config->referenceVoltageSource  = kLPADC_ReferenceVoltageAlt1;
  *   config->powerLevelMode          = kLPADC_PowerLevelAlt1;
- *   config->triggerPrioirtyPolicy   = kLPADC_TriggerPriorityPreemptImmediately;
+ *   config->triggerPriorityPolicy   = kLPADC_TriggerPriorityPreemptImmediately;
  *   config->enableConvPause         = false;
  *   config->convPauseDelay          = 0U;
  *   config->FIFOWatermark           = 0U;
@@ -523,6 +619,32 @@ static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
     base->STAT = mask;
 }
 
+#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT)
+/*!
+ * @brief Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high
+ * priority trigger exception.
+ *
+ * @param base LPADC peripheral base address.
+ * @return The OR'ed value of @ref _lpadc_trigger_status_flags.
+ */
+static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base)
+{
+    return base->TSTAT;
+}
+
+/*!
+ * @brief Clear trigger status flags.
+ *
+ * @param base LPADC peripheral base address.
+ * @param mask The mask of trigger status flags to be cleared, should be the
+ *              OR'ed value of @ref _lpadc_trigger_status_flags.
+ */
+static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask)
+{
+    base->TSTAT = mask;
+}
+#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */
+
 /* @} */
 
 /*!
@@ -534,7 +656,7 @@ static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
  * @brief Enable interrupts.
  *
  * @param base LPADC peripheral base address.
- * @mask Mask value for interrupt events. See to #_lpadc_interrupt_enable.
+ * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable.
  */
 static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask)
 {
@@ -728,7 +850,7 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_
  *   config->hardwareCompareMode        = kLPADC_HardwareCompareDisabled;
  *   config->hardwareCompareValueHigh   = 0U;
  *   config->hardwareCompareValueLow    = 0U;
- *   config->conversionResoultuionMode  = kLPADC_ConversionResolutionStandard;
+ *   config->conversionResolutionMode  = kLPADC_ConversionResolutionStandard;
  *   config->enableWaitTrigger          = false;
  * @endcode
  * @param config Pointer to configuration structure.
@@ -746,7 +868,7 @@ void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config);
  * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction.
  *
  * @param base LPADC peripheral base address.
- * @bool enable switcher to the calibration function.
+ * @param enable switcher to the calibration function.
  */
 void LPADC_EnableCalibration(ADC_Type *base, bool enable);
 #if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM
@@ -800,7 +922,7 @@ static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_
  * @brief Enable the offset calibration function.
  *
  * @param base LPADC peripheral base address.
- * @bool enable switcher to the calibration function.
+ * @param enable switcher to the calibration function.
  */
 static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable)
 {
@@ -830,6 +952,7 @@ void LPADC_DoOffsetCalibration(ADC_Type *base);
 void LPADC_DoAutoCalibration(ADC_Type *base);
 #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */
 #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */
+
 /* @} */
 
 #if defined(__cplusplus)

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mailbox.h

@@ -1,7 +1,6 @@
 /*
- * Copyright 2014, NXP
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -30,8 +29,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief MAILBOX driver version 2.1.0. */
-#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief MAILBOX driver version 2.2.0. */
+#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
 /*@}*/
 
 /*!
@@ -43,13 +42,25 @@ typedef enum _mailbox_cpu_id
     kMAILBOX_CM33_Core1 = 0,
     kMAILBOX_CM33_Core0
 } mailbox_cpu_id_t;
-#else
+#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
 typedef enum _mailbox_cpu_id
 {
     kMAILBOX_CM0Plus = 0,
     kMAILBOX_CM4
 } mailbox_cpu_id_t;
 #endif
+
+#if (defined(CPU_NXH2004J640UK48))
+typedef enum _mailbox_id
+{
+    kMAILBOX_CM0Plus_Core0 = 0,
+    kMAILBOX_CM0Plus_Core1,
+    kMAILBOX_CM0Plus_Sw_Irq0,
+    kMAILBOX_CM0Plus_Sw_Irq1,
+    kMAILBOX_CM0Plus_Sw_Irq2,
+    kMAILBOX_CM0Plus_Sw_Irq3
+} mailbox_id_t;
+#endif
 /*******************************************************************************
  * API
  ******************************************************************************/
@@ -97,6 +108,8 @@ static inline void MAILBOX_Deinit(MAILBOX_Type *base)
 
 /* @} */
 
+#if ((defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) || \
+     (defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
 /*!
  * @brief Set data value in the mailbox based on the CPU ID.
  *
@@ -111,7 +124,7 @@ static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id,
 {
 #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES))
     assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
-#else
+#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
     assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
 #endif
     base->MBOXIRQ[cpu_id].IRQ = mboxData;
@@ -130,7 +143,7 @@ static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu
 {
 #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES))
     assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
-#else
+#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
     assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
 #endif
     return base->MBOXIRQ[cpu_id].IRQ;
@@ -151,7 +164,7 @@ static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu
 {
 #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES))
     assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
-#else
+#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
     assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
 #endif
     base->MBOXIRQ[cpu_id].IRQSET = mboxSetBits;
@@ -172,12 +185,76 @@ static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_cpu_id_t c
 {
 #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES))
     assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
-#else
+#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
     assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
 #endif
     base->MBOXIRQ[cpu_id].IRQCLR = mboxClrBits;
 }
 
+#elif (defined(CPU_NXH2004J640UK48))
+
+/*!
+ * @brief Set data value in the mailbox based on the Mailbox ID.
+ *
+ * @param base MAILBOX peripheral base address.
+ * @param id Mailbox Index for NXH2004 devices
+ * @param mboxData Data to send in the mailbox.
+ *
+ */
+static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxData)
+{
+    assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3));
+    base->MBOXIRQ[id].IRQ = mboxData;
+}
+
+/*!
+ * @brief Get data in the mailbox based on the Mailbox ID.
+ *
+ * @param base MAILBOX peripheral base address.
+ * @param id, Mailbox index for NXH2004 devies.
+ *
+ * @return Current mailbox data.
+ */
+static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_id_t id)
+{
+    assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3));
+    return base->MBOXIRQ[id].IRQ;
+}
+
+/*!
+ * @brief Set data bits in the mailbox based on the Mailbox Index.
+ *
+ * @param base MAILBOX peripheral base address.
+ * @param id Mailbox Index for NXH2004 devices
+ * @param mboxSetBits Data bits to set in the mailbox.
+ *
+ * @note Sets data bits to send via the MAILBOX. A value of 0 will
+ * do nothing. Only sets bits selected with a 1 in it's bit position.
+ */
+static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxSetBits)
+{
+    assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3));
+    base->MBOXIRQ[id].IRQSET = mboxSetBits;
+}
+
+/*!
+ * @brief Clear data bits in the mailbox based on the Mailbox ID.
+ *
+ * @param base MAILBOX peripheral base address.
+ * @param id, Index to Mailbox for NXH2004 devices.
+ * @param mboxClrBits Data bits to clear in the mailbox.
+ *
+ * @note Clear data bits to send via the MAILBOX. A value of 0 will do
+ * nothing. Only clears bits selected with a 1 in it's bit position.
+ */
+static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxClrBits)
+{
+    assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3));
+    base->MBOXIRQ[id].IRQCLR = mboxClrBits;
+}
+
+#endif /*CPU_NXH2004J640UK48*/
+
 /*!
  * @brief Get MUTEX state and lock mutex
  *

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2020 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -37,10 +37,10 @@ static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
-#if defined(FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET
+#if defined(MRT_RSTS_N)
 /*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */
 static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N;
-#else
+#elif defined(MRT_RSTS)
 /*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */
 static const reset_ip_name_t s_mrtResets[] = MRT_RSTS;
 #endif
@@ -79,7 +79,7 @@ static uint32_t MRT_GetInstance(MRT_Type *base)
  */
 void MRT_Init(MRT_Type *base, const mrt_config_t *config)
 {
-    assert(config);
+    assert(config != NULL);
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate the MRT clock */
@@ -87,8 +87,10 @@ void MRT_Init(MRT_Type *base, const mrt_config_t *config)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
+#if defined(MRT_RSTS_N) || defined(MRT_RSTS)
     /* Reset the module. */
     RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]);
+#endif
 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
 
 #if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK)
@@ -136,10 +138,10 @@ void MRT_Deinit(MRT_Type *base)
  */
 void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
 
     uint32_t newValue = count;
-    if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == kMRT_OneShotMode) || (immediateLoad))
+    if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == (uint8_t)kMRT_OneShotMode) || (immediateLoad))
     {
         /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */
         newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK;

bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2020 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -23,7 +23,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */
+#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3 */
 /*@}*/
 
 /*! @brief List of MRT channels */
@@ -112,7 +112,7 @@ void MRT_Deinit(MRT_Type *base);
  */
 static inline void MRT_GetDefaultConfig(mrt_config_t *config)
 {
-    assert(config);
+    assert(config != NULL);
 #if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK)
     /* Use hardware status operating mode */
     config->enableMultiTask = false;
@@ -128,14 +128,14 @@ static inline void MRT_GetDefaultConfig(mrt_config_t *config)
  */
 static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
 
     uint32_t reg = base->CHANNEL[channel].CTRL;
 
     /* Clear old value */
     reg &= ~MRT_CHANNEL_CTRL_MODE_MASK;
     /* Add the new mode */
-    reg |= mode;
+    reg |= (uint32_t)mode;
 
     base->CHANNEL[channel].CTRL = reg;
 }
@@ -157,7 +157,7 @@ static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, cons
  */
 static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
     base->CHANNEL[channel].CTRL |= mask;
 }
 
@@ -171,7 +171,7 @@ static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint
  */
 static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
     base->CHANNEL[channel].CTRL &= ~mask;
 }
 
@@ -186,7 +186,7 @@ static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uin
  */
 static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
     return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK);
 }
 
@@ -208,7 +208,7 @@ static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t chann
  */
 static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
     return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK));
 }
 
@@ -222,7 +222,7 @@ static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel)
  */
 static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
     base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK);
 }
 
@@ -264,7 +264,7 @@ void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, b
  */
 static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
     return base->CHANNEL[channel].TIMER;
 }
 
@@ -285,12 +285,12 @@ static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t chann
  *
  * @param base    Multi-Rate timer peripheral base address
  * @param channel Timer channel number.
- * @param count   Timer period in units of ticks
+ * @param count   Timer period in units of ticks. Count can contain the LOAD bit, which control the force load feature.
  */
 static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
-    assert(count < MRT_CHANNEL_INTVAL_IVALUE_MASK);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint32_t)(count & ~MRT_CHANNEL_INTVAL_LOAD_MASK) <= (uint32_t)MRT_CHANNEL_INTVAL_IVALUE_MASK);
     /* Write the timer interval value */
     base->CHANNEL[channel].INTVAL = count;
 }
@@ -305,7 +305,7 @@ static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t c
  */
 static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
     /* Stop the timer immediately */
     base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK;
 }
@@ -343,7 +343,7 @@ static inline uint32_t MRT_GetIdleChannel(MRT_Type *base)
  */
 static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
 
     uint32_t reg = base->CHANNEL[channel].STAT;