将swm320和swm341整合进synwit (#6290)

* 将swm320和swm341整合进synwit

.github/workflows/action.yml

@@ -172,8 +172,8 @@ jobs:
         #  - {RTT_BSP: "stm32/stm32wle5-yizhilian-lm402", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "wch/arm/ch32f103c8-core", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "wch/arm/ch32f203r-evt", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "swm320", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "swm341", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "synwit/swm320", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "synwit/swm341", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "beaglebone", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "zynqmp-r5-axu4ev", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "frdm-k64f", RTT_TOOL_CHAIN: "sourcery-arm"}

bsp/swm320/drivers/drv_adc.c

@@ -1,217 +0,0 @@
-/*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-5-26      lik          first version
- */
-
-#include "drv_adc.h"
-
-#ifdef RT_USING_ADC
-#ifdef BSP_USING_ADC
-
-//#define DRV_DEBUG
-#define LOG_TAG "drv.adc"
-#include <drv_log.h>
-
-static struct swm_adc_cfg adc_cfg[] =
-    {
-#ifdef BSP_USING_ADC0
-        ADC0_CFG,
-#endif
-#ifdef BSP_USING_ADC1
-        ADC1_CFG,
-#endif
-
-};
-
-static struct swm_adc adc_drv[sizeof(adc_cfg) / sizeof(adc_cfg[0])];
-
-static rt_err_t swm_adc_enabled(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_bool_t enabled)
-{
-    struct swm_adc_cfg *cfg = RT_NULL;
-    RT_ASSERT(adc_device != RT_NULL);
-    cfg = adc_device->parent.user_data;
-
-    if (enabled)
-    {
-        ADC_Open(cfg->ADCx);
-    }
-    else
-    {
-        ADC_Close(cfg->ADCx);
-    }
-
-    return RT_EOK;
-}
-
-static rt_uint32_t swm_adc_get_channel(rt_uint32_t channel)
-{
-    rt_uint32_t swm_channel = 0;
-
-    switch (channel)
-    {
-    case 0:
-        swm_channel = ADC_CH0;
-        break;
-    case 1:
-        swm_channel = ADC_CH1;
-        break;
-    case 2:
-        swm_channel = ADC_CH2;
-        break;
-    case 3:
-        swm_channel = ADC_CH3;
-        break;
-    case 4:
-        swm_channel = ADC_CH4;
-        break;
-    case 5:
-        swm_channel = ADC_CH5;
-        break;
-    case 6:
-        swm_channel = ADC_CH6;
-        break;
-    case 7:
-        swm_channel = ADC_CH7;
-        break;
-    }
-
-    return swm_channel;
-}
-
-static rt_err_t swm_get_adc_value(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_uint32_t *value)
-{
-    uint32_t adc_chn;
-    struct swm_adc_cfg *cfg = RT_NULL;
-    RT_ASSERT(adc_device != RT_NULL);
-    RT_ASSERT(value != RT_NULL);
-    cfg = adc_device->parent.user_data;
-
-    if (channel < 8)
-    {
-        /* set stm32 ADC channel */
-        adc_chn = swm_adc_get_channel(channel);
-    }
-    else
-    {
-        LOG_E("ADC channel must be between 0 and 7.");
-        return -RT_ERROR;
-    }
-
-    /* start ADC */
-    ADC_Start(cfg->ADCx);
-    /* Wait for the ADC to convert */
-    while ((cfg->ADCx->CH[channel].STAT & 0x01) == 0)
-        ;
-
-    /* get ADC value */
-    *value = (rt_uint32_t)ADC_Read(cfg->ADCx, adc_chn);
-
-    return RT_EOK;
-}
-
-static const struct rt_adc_ops swm_adc_ops =
-    {
-        .enabled = swm_adc_enabled,
-        .convert = swm_get_adc_value,
-};
-
-static int rt_hw_adc_init(void)
-{
-    int i = 0;
-    int result = RT_EOK;
-
-    for (i = 0; i < sizeof(adc_cfg) / sizeof(adc_cfg[0]); i++)
-    {
-        /* ADC init */
-        adc_drv[i].cfg = &adc_cfg[i];
-
-        if (adc_drv[i].cfg->ADCx == ADC0)
-        {
-#ifdef BSP_USING_ADC0_CHN0
-            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH0;
-#endif
-#ifdef BSP_USING_ADC0_CHN1
-            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH1;
-#endif
-#ifdef BSP_USING_ADC0_CHN2
-            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH2;
-#endif
-#ifdef BSP_USING_ADC0_CHN3
-            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH3;
-#endif
-#ifdef BSP_USING_ADC0_CHN4
-            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH4;
-            PORT_Init(PORTA, PIN12, PORTA_PIN12_ADC0_IN4, 0); //PA.12 => ADC0.CH4
-#endif
-#ifdef BSP_USING_ADC0_CHN5
-            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH5;
-            PORT_Init(PORTA, PIN11, PORTA_PIN11_ADC0_IN5, 0); //PA.11 => ADC0.CH5
-#endif
-#ifdef BSP_USING_ADC0_CHN6
-            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH6;
-            PORT_Init(PORTA, PIN10, PORTA_PIN10_ADC0_IN6, 0); //PA.10 => ADC0.CH6
-#endif
-#ifdef BSP_USING_ADC0_CHN7
-            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH7;
-            PORT_Init(PORTA, PIN9, PORTA_PIN9_ADC0_IN7, 0); //PA.9  => ADC0.CH7
-#endif
-        }
-        else if (adc_drv[i].cfg->ADCx == ADC1)
-        {
-#ifdef BSP_USING_ADC1_CHN0
-            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH0;
-            PORT_Init(PORTC, PIN7, PORTC_PIN7_ADC1_IN0, 0); //PC.7 => ADC1.CH0
-#endif
-#ifdef BSP_USING_ADC1_CHN1
-            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH1;
-            PORT_Init(PORTC, PIN6, PORTC_PIN6_ADC1_IN1, 0); //PC.6 => ADC1.CH1
-#endif
-#ifdef BSP_USING_ADC1_CHN2
-            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH2;
-            PORT_Init(PORTC, PIN5, PORTC_PIN5_ADC1_IN2, 0); //PC.5 => ADC1.CH2
-#endif
-#ifdef BSP_USING_ADC1_CHN3
-            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH3;
-            PORT_Init(PORTC, PIN4, PORTC_PIN4_ADC1_IN3, 0); //PC.4 => ADC1.CH3
-#endif
-#ifdef BSP_USING_ADC1_CHN4
-            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH4;
-            PORT_Init(PORTN, PIN0, PORTN_PIN0_ADC1_IN4, 0); //PN.0 => ADC1.CH4
-#endif
-#ifdef BSP_USING_ADC1_CHN5
-            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH5;
-            PORT_Init(PORTN, PIN1, PORTN_PIN1_ADC1_IN5, 0); //PN.1 => ADC1.CH5
-#endif
-#ifdef BSP_USING_ADC1_CHN6
-            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH6;
-            PORT_Init(PORTN, PIN2, PORTN_PIN2_ADC1_IN6, 0); //PN.2 => ADC1.CH6
-#endif
-#ifdef BSP_USING_ADC1_CHN7
-            adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH7;
-#endif
-        }
-
-        ADC_Init(adc_drv[i].cfg->ADCx, &(adc_drv[i].cfg->adc_initstruct));
-        ADC_Open(adc_drv[i].cfg->ADCx);
-        /* register ADC device */
-        if (rt_hw_adc_register(&adc_drv[i].adc_device, adc_drv[i].cfg->name, &swm_adc_ops, adc_drv[i].cfg) == RT_EOK)
-        {
-            LOG_D("%s init success", adc_drv[i].cfg->name);
-        }
-        else
-        {
-            LOG_E("%s register failed", adc_drv[i].cfg->name);
-            result = -RT_ERROR;
-        }
-    }
-
-    return result;
-}
-INIT_BOARD_EXPORT(rt_hw_adc_init);
-#endif /* BSP_USING_ADC */
-#endif /* RT_USING_ADC */

bsp/swm320/drivers/drv_adc.h

@@ -1,71 +0,0 @@
-/*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-5-26      lik          first version
- */
-
-#ifndef __DRV_ADC_H__
-#define __DRV_ADC_H__
-
-#include "board.h"
-
-struct swm_adc_cfg
-{
-    const char *name;
-    ADC_TypeDef *ADCx;
-    ADC_InitStructure adc_initstruct;
-};
-
-struct swm_adc
-{
-    struct swm_adc_cfg *cfg;
-    struct rt_adc_device adc_device;
-};
-
-#ifdef BSP_USING_ADC0
-#ifndef ADC0_CFG
-#define ADC0_CFG                                        \
-    {                                                   \
-        .name = "adc0",                                 \
-        .ADCx = ADC0,                                   \
-        .adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \
-        .adc_initstruct.clk_div = 25,                   \
-        .adc_initstruct.pga_ref = PGA_REF_INTERNAL,     \
-        .adc_initstruct.channels = 0,                   \
-        .adc_initstruct.samplAvg = ADC_AVG_SAMPLE1,     \
-        .adc_initstruct.trig_src = ADC_TRIGSRC_SW,      \
-        .adc_initstruct.Continue = 0,                   \
-        .adc_initstruct.EOC_IEn = 0,                    \
-        .adc_initstruct.OVF_IEn = 0,                    \
-        .adc_initstruct.HFULL_IEn = 0,                  \
-        .adc_initstruct.FULL_IEn = 0,                   \
-    }
-#endif /* ADC0_CFG */
-#endif /* BSP_USING_ADC0 */
-
-#ifdef BSP_USING_ADC1
-#ifndef ADC1_CFG
-#define ADC1_CFG                                        \
-    {                                                   \
-        .name = "adc1",                                 \
-        .ADCx = ADC1,                                   \
-        .adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \
-        .adc_initstruct.clk_div = 25,                   \
-        .adc_initstruct.pga_ref = PGA_REF_INTERNAL,     \
-        .adc_initstruct.channels = 0,                   \
-        .adc_initstruct.samplAvg = ADC_AVG_SAMPLE1,     \
-        .adc_initstruct.trig_src = ADC_TRIGSRC_SW,      \
-        .adc_initstruct.Continue = 0,                   \
-        .adc_initstruct.EOC_IEn = 0,                    \
-        .adc_initstruct.OVF_IEn = 0,                    \
-        .adc_initstruct.HFULL_IEn = 0,                  \
-        .adc_initstruct.FULL_IEn = 0,                   \
-    }
-#endif /* ADC1_CFG */
-#endif /* BSP_USING_ADC1 */
-
-#endif /* __DRV_ADC_H__ */

bsp/swm320/drivers/drv_crypto.c

@@ -1,226 +0,0 @@
-/*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-07-10     lik          first version
- */
-
-#include "drv_crypto.h"
-#include <string.h>
-
-#ifdef RT_USING_HWCRYPTO
-
-struct swm_hwcrypto_device
-{
-    struct rt_hwcrypto_device dev;
-    struct rt_mutex mutex;
-};
-
-#ifdef BSP_USING_CRC
-
-static struct hwcrypto_crc_cfg crc_backup_cfg;
-
-static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)
-{
-    rt_uint32_t result = 0;
-    struct swm_hwcrypto_device *swm_hw_dev = (struct swm_hwcrypto_device *)ctx->parent.device->user_data;
-
-    struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->parent.contex);
-
-    rt_mutex_take(&swm_hw_dev->mutex, RT_WAITING_FOREVER);
-
-    if (memcmp(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)) != 0)
-    {
-        hw_crc_cfg->CRCx = CRC;
-
-        hw_crc_cfg->inival = ctx->crc_cfg.last_val;
-
-        switch (ctx->crc_cfg.width)
-        {
-        case 8:
-            hw_crc_cfg->crc_inbits = 2;
-            break;
-        case 16:
-            hw_crc_cfg->crc_inbits = 1;
-            break;
-        case 32:
-            hw_crc_cfg->crc_inbits = 0;
-            break;
-        default:
-            goto _exit;
-        }
-        switch (ctx->crc_cfg.poly)
-        {
-        case 0x1021:
-            hw_crc_cfg->crc_1632 = 1;
-            break;
-        case 0x04C11DB7:
-            hw_crc_cfg->crc_1632 = 0;
-            break;
-        default:
-            goto _exit;
-        }
-
-        hw_crc_cfg->crc_out_not = 0;
-
-        switch (ctx->crc_cfg.flags)
-        {
-        case 0:
-        case CRC_FLAG_REFIN:
-            hw_crc_cfg->crc_out_rev = 0;
-            break;
-        case CRC_FLAG_REFOUT:
-        case CRC_FLAG_REFIN | CRC_FLAG_REFOUT:
-            hw_crc_cfg->crc_out_rev = 1;
-            break;
-        default:
-            goto _exit;
-        }
-
-        CRC_Init(hw_crc_cfg->CRCx, (hw_crc_cfg->crc_inbits << 1) | hw_crc_cfg->crc_1632, hw_crc_cfg->crc_out_not, hw_crc_cfg->crc_out_rev, hw_crc_cfg->inival);
-        memcpy(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg));
-    }
-
-    for (uint32_t i = 0; i < length; i++)
-        CRC_Write((uint32_t)in[i]);
-    result = CRC_Result();
-
-    ctx->crc_cfg.last_val = result;
-
-    crc_backup_cfg.last_val = ctx->crc_cfg.last_val;
-    result = (result ? result ^ (ctx->crc_cfg.xorout) : result);
-
-_exit:
-    rt_mutex_release(&swm_hw_dev->mutex);
-
-    return result;
-}
-
-static const struct hwcrypto_crc_ops crc_ops =
-    {
-        .update = _crc_update,
-};
-#endif /* BSP_USING_CRC */
-
-static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
-{
-    rt_err_t res = RT_EOK;
-
-    switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
-    {
-#if defined(BSP_USING_CRC)
-    case HWCRYPTO_TYPE_CRC:
-    {
-        struct swm_crc_cfg *contex = rt_calloc(1, sizeof(struct swm_crc_cfg));
-        if (RT_NULL == contex)
-        {
-            res = -RT_ERROR;
-            break;
-        }
-        contex->CRCx = DEFAULT_CRC;
-        contex->inival = DEFAULT_INIVAL;
-        contex->crc_inbits = DEFAULT_INBITS;
-        contex->crc_1632 = DEFAULT_CRC1632;
-        contex->crc_out_not = DEFAULT_OUT_NOT;
-        contex->crc_out_rev = DEFAULT_OUT_REV;
-
-        ctx->contex = contex;
-        ((struct hwcrypto_crc *)ctx)->ops = &crc_ops;
-        break;
-    }
-#endif /* BSP_USING_CRC */
-    default:
-        res = -RT_ERROR;
-        break;
-    }
-    return res;
-}
-
-static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx)
-{
-    struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->contex);
-    switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
-    {
-#if defined(BSP_USING_CRC)
-    case HWCRYPTO_TYPE_CRC:
-        hw_crc_cfg->CRCx->CR &= ~CRC_CR_EN_Msk;
-        break;
-#endif /* BSP_USING_CRC */
-    default:
-        break;
-    }
-
-    rt_free(ctx->contex);
-}
-
-static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src)
-{
-    rt_err_t res = RT_EOK;
-
-    switch (src->type & HWCRYPTO_MAIN_TYPE_MASK)
-    {
-#if defined(BSP_USING_CRC)
-    case HWCRYPTO_TYPE_CRC:
-        if (des->contex && src->contex)
-        {
-            rt_memcpy(des->contex, src->contex, sizeof(struct swm_crc_cfg));
-        }
-        break;
-#endif /* BSP_USING_CRC */
-    default:
-        res = -RT_ERROR;
-        break;
-    }
-    return res;
-}
-
-static void _crypto_reset(struct rt_hwcrypto_ctx *ctx)
-{
-    struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->contex);
-    switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
-    {
-#if defined(BSP_USING_CRC)
-    case HWCRYPTO_TYPE_CRC:
-        hw_crc_cfg->CRCx->CR &= ~CRC_CR_EN_Msk;
-        break;
-#endif /* BSP_USING_CRC */
-    default:
-        break;
-    }
-}
-
-static const struct rt_hwcrypto_ops _ops =
-    {
-        .create = _crypto_create,
-        .destroy = _crypto_destroy,
-        .copy = _crypto_clone,
-        .reset = _crypto_reset,
-};
-
-int rt_hw_crypto_init(void)
-{
-    static struct swm_hwcrypto_device _crypto_dev;
-    rt_uint32_t cpuid[2] = {0};
-
-    _crypto_dev.dev.ops = &_ops;
-
-    cpuid[0] = SCB->CPUID;
-    _crypto_dev.dev.id = 0;
-    rt_memcpy(&_crypto_dev.dev.id, cpuid, 8);
-
-    _crypto_dev.dev.user_data = &_crypto_dev;
-
-    if (rt_hwcrypto_register(&_crypto_dev.dev, RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK)
-    {
-        return -1;
-    }
-    rt_mutex_init(&_crypto_dev.mutex, RT_HWCRYPTO_DEFAULT_NAME, RT_IPC_FLAG_PRIO);
-    return 0;
-}
-INIT_BOARD_EXPORT(rt_hw_crypto_init);
-
-
-#endif /* RT_USING_HWCRYPTO */

bsp/swm320/drivers/drv_crypto.h

@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-07-10     lik          first version
- */
-
-#ifndef __DRV_CRYPTO_H__
-#define __DRV_CRYPTO_H__
-
-#include "board.h"
-
-/* swm config class */
-struct swm_crc_cfg
-{
-    CRC_TypeDef *CRCx;
-    uint32_t inival;
-    uint8_t crc_inbits;
-    uint8_t crc_1632;
-    uint8_t crc_out_not;
-    uint8_t crc_out_rev;
-};
-
-#ifdef BSP_USING_CRC
-
-#define DEFAULT_CRC (CRC)
-#define DEFAULT_INIVAL (0x00000000)
-#define DEFAULT_INBITS (2)
-#define DEFAULT_CRC1632 (0)
-#define DEFAULT_OUT_NOT (0)
-#define DEFAULT_OUT_REV (0)
-
-#endif /* BSP_USING_CRC */
-
-int rt_hw_crypto_init(void);
-
-#endif /* __DRV_CRYPTO_H__ */

bsp/swm320/drivers/drv_gpio.h

@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-12-10     Zohar_Lee    first version
- * 2020-07-10     lik          rewrite
- */
-
-#ifndef __DRV_GPIO_H__
-#define __DRV_GPIO_H__
-
-#include "board.h"
-
-#define __SWM_PIN(index, gpio, pin_index)                    \
-    {                                                        \
-        index, GPIO##gpio, PIN##pin_index, GPIO##gpio##_IRQn \
-    }
-#define GPIO0 ((GPIO_TypeDef *)(0))
-#define GPIO0_IRQn (GPIOA0_IRQn)
-
-struct swm_pin_index
-{
-    uint32_t index;
-    GPIO_TypeDef *gpio;
-    uint32_t pin;
-    IRQn_Type irq;
-};
-typedef struct swm_pin_index pin_t;
-
-int rt_hw_pin_init(void);
-
-#endif /* __DRV_GPIO_H__ */

bsp/swm320/drivers/drv_hwtimer.c

@@ -1,256 +0,0 @@
-/*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-12-10    Zohar_Lee    first version
- * 2020-07-10    lik          format file
- */
-
-#include "drv_hwtimer.h"
-
-#ifdef RT_USING_HWTIMER
-#ifdef BSP_USING_TIM
-
-enum
-{
-#ifdef BSP_USING_TIM0
-    TIM0_INDEX,
-#endif
-#ifdef BSP_USING_TIM1
-    TIM1_INDEX,
-#endif
-#ifdef BSP_USING_TIM2
-    TIM2_INDEX,
-#endif
-#ifdef BSP_USING_TIM3
-    TIM3_INDEX,
-#endif
-#ifdef BSP_USING_TIM4
-    TIM4_INDEX,
-#endif
-#ifdef BSP_USING_TIM5
-    TIM5_INDEX,
-#endif
-};
-
-static struct swm_hwtimer_cfg hwtimer_cfg[] =
-    {
-#ifdef BSP_USING_TIM0
-        TIM0_CFG,
-#endif
-#ifdef BSP_USING_TIM1
-        TIM1_CFG,
-#endif
-#ifdef BSP_USING_TIM2
-        TIM2_CFG,
-#endif
-#ifdef BSP_USING_TIM3
-        TIM3_CFG,
-#endif
-#ifdef BSP_USING_TIM4
-        TIM4_CFG,
-#endif
-#ifdef BSP_USING_TIM5
-        TIM5_CFG,
-#endif
-};
-
-static struct swm_hwtimer hwtimer_drv[sizeof(hwtimer_cfg) / sizeof(hwtimer_cfg[0])] = {0};
-
-static void swm_timer_init(struct rt_hwtimer_device *timer_device, rt_uint32_t state)
-{
-    struct swm_hwtimer_cfg *cfg = RT_NULL;
-    RT_ASSERT(timer_device != RT_NULL);
-
-    if (state)
-    {
-        cfg = timer_device->parent.user_data;
-        TIMR_Init(cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock, 1);
-        timer_device->freq = SystemCoreClock;
-    }
-}
-
-static rt_err_t swm_timer_start(rt_hwtimer_t *timer_device, rt_uint32_t cnt, rt_hwtimer_mode_t opmode)
-{
-    rt_err_t result = RT_EOK;
-    struct swm_hwtimer_cfg *cfg = RT_NULL;
-    RT_ASSERT(timer_device != RT_NULL);
-    cfg = timer_device->parent.user_data;
-
-    if (opmode == HWTIMER_MODE_ONESHOT)
-    {
-        /* set timer to single mode */
-        timer_device->mode = HWTIMER_MODE_ONESHOT;
-    }
-    else
-    {
-        timer_device->mode = HWTIMER_MODE_PERIOD;
-    }
-    TIMR_SetPeriod(cfg->TIMRx, cnt);
-    TIMR_Stop(cfg->TIMRx);
-    TIMR_Start(cfg->TIMRx);
-
-    return result;
-}
-
-static void swm_timer_stop(rt_hwtimer_t *timer_device)
-{
-    struct swm_hwtimer_cfg *cfg = RT_NULL;
-    RT_ASSERT(timer_device != RT_NULL);
-    cfg = timer_device->parent.user_data;
-
-    /* stop timer */
-    TIMR_Stop(cfg->TIMRx);
-}
-
-static rt_uint32_t swm_timer_count_get(rt_hwtimer_t *timer_device)
-{
-    struct swm_hwtimer_cfg *cfg = RT_NULL;
-    RT_ASSERT(timer_device != RT_NULL);
-    cfg = timer_device->parent.user_data;
-
-    return TIMR_GetCurValue(cfg->TIMRx);
-}
-
-static rt_err_t swm_timer_ctrl(rt_hwtimer_t *timer_device, rt_uint32_t cmd, void *args)
-{
-    struct swm_hwtimer_cfg *cfg = RT_NULL;
-    rt_err_t result = RT_EOK;
-    RT_ASSERT(timer_device != RT_NULL);
-    RT_ASSERT(args != RT_NULL);
-    cfg = timer_device->parent.user_data;
-
-    switch (cmd)
-    {
-    case HWTIMER_CTRL_FREQ_SET:
-    {
-        rt_uint32_t freq;
-        freq = *(rt_uint32_t *)args;
-
-        TIMR_Init(cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock / freq, 1);
-    }
-    break;
-    default:
-    {
-        result = -RT_ENOSYS;
-    }
-    break;
-    }
-
-    return result;
-}
-
-static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
-
-static struct rt_hwtimer_ops swm_hwtimer_ops =
-    {
-        .init = swm_timer_init,
-        .start = swm_timer_start,
-        .stop = swm_timer_stop,
-        .count_get = swm_timer_count_get,
-        .control = swm_timer_ctrl};
-
-void rt_hw_hwtimer_isr(rt_hwtimer_t *timer_device)
-{
-    struct swm_hwtimer_cfg *cfg = RT_NULL;
-    RT_ASSERT(timer_device != RT_NULL);
-    cfg = timer_device->parent.user_data;
-
-    TIMR_INTClr(cfg->TIMRx);
-    rt_device_hwtimer_isr(timer_device);
-}
-#ifdef BSP_USING_TIM0
-void TIMR0_Handler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-    rt_hw_hwtimer_isr(&(hwtimer_drv[TIM0_INDEX].time_device));
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif //BSP_USING_TIM0
-
-#ifdef BSP_USING_TIM1
-void TIMR1_Handler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-    rt_hw_hwtimer_isr(&(hwtimer_drv[TIM1_INDEX].time_device));
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif //BSP_USING_TIM1
-
-#ifdef BSP_USING_TIM2
-void TIMR2_Handler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-    rt_hw_hwtimer_isr(&(hwtimer_drv[TIM2_INDEX].time_device));
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif //BSP_USING_TIM2
-
-#ifdef BSP_USING_TIM3
-void TIMR3_Handler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-    rt_hw_hwtimer_isr(&(hwtimer_drv[TIM3_INDEX].time_device));
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif //BSP_USING_TIM3
-
-#ifdef BSP_USING_TIM4
-void TIMR4_Handler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-    rt_hw_hwtimer_isr(&(hwtimer_drv[TIM4_INDEX].time_device));
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif //BSP_USING_TIM4
-
-#ifdef BSP_USING_TIM5
-void TIMR5_Handler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-    rt_hw_hwtimer_isr(&(hwtimer_drv[TIM5_INDEX].time_device));
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif //BSP_USING_TIM5
-
-static int rt_hw_hwtimer_init(void)
-{
-    int i = 0;
-    int result = RT_EOK;
-
-    for (i = 0; i < sizeof(hwtimer_cfg) / sizeof(hwtimer_cfg[0]); i++)
-    {
-        hwtimer_drv[i].cfg = &hwtimer_cfg[i];
-        hwtimer_drv[i].time_device.info = &_info;
-        hwtimer_drv[i].time_device.ops = &swm_hwtimer_ops;
-        if (rt_device_hwtimer_register(&hwtimer_drv[i].time_device, hwtimer_drv[i].cfg->name, hwtimer_drv[i].cfg) == RT_EOK)
-        {
-            ;
-        }
-        else
-        {
-            result = -RT_ERROR;
-        }
-    }
-
-    return result;
-}
-INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
-
-#endif /* BSP_USING_TIM */
-#endif /* RT_USING_HWTIMER */

bsp/swm320/drivers/drv_hwtimer.h

@@ -1,101 +0,0 @@
-/*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-12-10     Zohar_Lee    first version
- * 2020-07-10     lik          rewrite
- */
-
-#ifndef __DRV_HWTIMER_H__
-#define __DRV_HWTIMER_H__
-
-#include "board.h"
-
-struct swm_hwtimer_cfg
-{
-    char *name;
-    TIMR_TypeDef *TIMRx;
-};
-
-struct swm_hwtimer
-{
-    struct swm_hwtimer_cfg *cfg;
-    rt_hwtimer_t time_device;
-};
-
-#ifndef TIM_DEV_INFO_CONFIG
-#define TIM_DEV_INFO_CONFIG            \
-    {                                  \
-        .maxfreq = 120000000,          \
-        .minfreq = 120000000,          \
-        .maxcnt = 0xFFFFFFFF,          \
-        .cntmode = HWTIMER_CNTMODE_DW, \
-    }
-#endif /* TIM_DEV_INFO_CONFIG */
-
-#ifdef BSP_USING_TIM0
-#ifndef TIM0_CFG
-#define TIM0_CFG          \
-    {                     \
-        .name = "timer0", \
-        .TIMRx = TIMR0,   \
-    }
-#endif /* TIM0_CFG */
-#endif /* BSP_USING_TIM0 */
-
-#ifdef BSP_USING_TIM1
-#ifndef TIM1_CFG
-#define TIM1_CFG          \
-    {                     \
-        .name = "timer1", \
-        .TIMRx = TIMR1,   \
-    }
-#endif /* TIM1_CFG */
-#endif /* BSP_USING_TIM1 */
-
-#ifdef BSP_USING_TIM2
-#ifndef TIM2_CFG
-#define TIM2_CFG          \
-    {                     \
-        .name = "timer2", \
-        .TIMRx = TIMR2,   \
-    }
-#endif /* TIM2_CFG */
-#endif /* BSP_USING_TIM2 */
-
-#ifdef BSP_USING_TIM3
-#ifndef TIM3_CFG
-#define TIM3_CFG          \
-    {                     \
-        .name = "timer3", \
-        .TIMRx = TIMR3,   \
-    }
-#endif /* TIM3_CFG */
-#endif /* BSP_USING_TIM3 */
-
-#ifdef BSP_USING_TIM4
-#ifndef TIM4_CFG
-#define TIM4_CFG          \
-    {                     \
-        .name = "timer4", \
-        .TIMRx = TIMR4,   \
-    }
-#endif /* TIM4_CFG */
-#endif /* BSP_USING_TIM4 */
-
-#ifdef BSP_USING_TIM5
-#ifndef TIM5_CFG
-#define TIM5_CFG          \
-    {                     \
-        .name = "timer5", \
-        .TIMRx = TIMR5,   \
-    }
-#endif /* TIM5_CFG */
-#endif /* BSP_USING_TIM5 */
-
-int rt_hw_hwtimer_init(void);
-
-#endif /* __DRV_HWTIMER_H__ */

bsp/swm320/drivers/drv_pwm.c

@@ -1,233 +0,0 @@
-/*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-12-10     Zohar_Lee    first version
- * 2020-07-10     lik          format file
- */
-
-#include "drv_pwm.h"
-
-#ifdef RT_USING_PWM
-#ifdef BSP_USING_PWM
-
-//#define DRV_DEBUG
-#define LOG_TAG "drv.pwm"
-#include <drv_log.h>
-
-#define MIN_PERIOD 2
-#define MIN_PULSE 1
-
-static struct swm_pwm_cfg pwm_cfg[] =
-    {
-#ifdef BSP_USING_PWM0
-        PWM0_CFG,
-#endif
-#ifdef BSP_USING_PWM1
-        PWM1_CFG,
-#endif
-#ifdef BSP_USING_PWM2
-        PWM2_CFG,
-#endif
-#ifdef BSP_USING_PWM3
-        PWM3_CFG,
-#endif
-#ifdef BSP_USING_PWM4
-        PWM4_CFG,
-#endif
-#ifdef BSP_USING_PWM5
-        PWM5_CFG,
-#endif
-};
-
-static struct swm_pwm pwm_drv[sizeof(pwm_cfg) / sizeof(pwm_cfg[0])] = {0};
-
-static rt_err_t swm_pwm_control(struct rt_device_pwm *pwm_device, int cmd, void *arg);
-static struct rt_pwm_ops pwm_ops =
-    {
-        swm_pwm_control};
-
-static rt_err_t swm_pwm_enable(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration, rt_bool_t enable)
-{
-    struct swm_pwm_cfg *cfg = RT_NULL;
-    RT_ASSERT(pwm_device != RT_NULL);
-    cfg = pwm_device->parent.user_data;
-
-    if (!enable)
-    {
-        if (PWM_CH_A == configuration->channel)
-        {
-            PWM_Stop(cfg->PWMx, 1, 0);
-        }
-        if (PWM_CH_B == configuration->channel)
-        {
-            PWM_Stop(cfg->PWMx, 0, 1);
-        }
-    }
-    else
-    {
-        if (PWM_CH_A == configuration->channel)
-        {
-            PWM_Start(cfg->PWMx, 1, 0);
-        }
-        if (PWM_CH_B == configuration->channel)
-        {
-            PWM_Start(cfg->PWMx, 0, 1);
-        }
-    }
-
-    return RT_EOK;
-}
-
-static rt_err_t swm_pwm_get(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration)
-{
-    rt_uint64_t tim_clock;
-    tim_clock = SystemCoreClock / 8;
-
-    struct swm_pwm_cfg *cfg = RT_NULL;
-    RT_ASSERT(pwm_device != RT_NULL);
-    cfg = pwm_device->parent.user_data;
-
-    /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
-    tim_clock /= 1000000UL;
-    configuration->period = PWM_GetCycle(cfg->PWMx, configuration->channel) * 1000UL / tim_clock;
-    configuration->pulse = PWM_GetHDuty(cfg->PWMx, configuration->channel) * 1000UL / tim_clock;
-
-    return RT_EOK;
-}
-
-static rt_err_t swm_pwm_set(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration)
-{
-    rt_uint32_t period, pulse;
-    rt_uint64_t tim_clock;
-    tim_clock = SystemCoreClock / 8;
-
-    struct swm_pwm_cfg *cfg = RT_NULL;
-    RT_ASSERT(pwm_device != RT_NULL);
-    cfg = pwm_device->parent.user_data;
-
-    /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
-    /* when SystemCoreClock = 120MHz, configuration->period max 4.369ms */
-    /* when SystemCoreClock = 20MHz, configuration->period max 26.214ms */
-    tim_clock /= 1000000UL;
-    period = (unsigned long long)configuration->period * tim_clock / 1000ULL;
-    pulse = (unsigned long long)configuration->pulse * tim_clock / 1000ULL;
-    if (period < MIN_PERIOD)
-    {
-        period = MIN_PERIOD;
-    }
-    if (pulse < MIN_PULSE)
-    {
-        pulse = MIN_PULSE;
-    }
-    PWM_SetCycle(cfg->PWMx, configuration->channel, period);
-    PWM_SetHDuty(cfg->PWMx, configuration->channel, pulse);
-
-    return RT_EOK;
-}
-
-static rt_err_t swm_pwm_control(struct rt_device_pwm *pwm_device, int cmd, void *arg)
-{
-    RT_ASSERT(pwm_device != RT_NULL);
-
-    struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
-
-    switch (cmd)
-    {
-    case PWM_CMD_ENABLE:
-        return swm_pwm_enable(pwm_device, configuration, RT_TRUE);
-    case PWM_CMD_DISABLE:
-        return swm_pwm_enable(pwm_device, configuration, RT_FALSE);
-    case PWM_CMD_SET:
-        return swm_pwm_set(pwm_device, configuration);
-    case PWM_CMD_GET:
-        return swm_pwm_get(pwm_device, configuration);
-    default:
-        return RT_EINVAL;
-    }
-}
-
-int rt_hw_pwm_init(void)
-{
-    int i = 0;
-    int result = RT_EOK;
-
-    for (i = 0; i < sizeof(pwm_cfg) / sizeof(pwm_cfg[0]); i++)
-    {
-        pwm_drv[i].cfg = &pwm_cfg[i];
-
-        if (pwm_drv[i].cfg->PWMx == PWM0)
-        {
-#ifdef BSP_USING_PWM0A
-            PORT_Init(PORTC, PIN2, FUNMUX0_PWM0A_OUT, 0);
-#endif
-#ifdef BSP_USING_PWM0B
-            PORT_Init(PORTC, PIN4, FUNMUX0_PWM0B_OUT, 0);
-#endif
-        }
-        else if (pwm_drv[i].cfg->PWMx == PWM1)
-        {
-#ifdef BSP_USING_PWM1A
-            PORT_Init(PORTC, PIN3, FUNMUX1_PWM1A_OUT, 0);
-#endif
-#ifdef BSP_USING_PWM1B
-            PORT_Init(PORTC, PIN5, FUNMUX1_PWM1B_OUT, 0);
-#endif
-        }
-        else if (pwm_drv[i].cfg->PWMx == PWM2)
-        {
-#ifdef BSP_USING_PWM2A
-            PORT_Init(PORTN, PIN4, FUNMUX0_PWM2A_OUT, 0);
-#endif
-#ifdef BSP_USING_PWM2B
-            PORT_Init(PORTN, PIN6, FUNMUX0_PWM2B_OUT, 0);
-#endif
-        }
-        else if (pwm_drv[i].cfg->PWMx == PWM3)
-        {
-#ifdef BSP_USING_PWM3A
-            PORT_Init(PORTN, PIN3, FUNMUX1_PWM3A_OUT, 0);
-#endif
-#ifdef BSP_USING_PWM3B
-            PORT_Init(PORTN, PIN5, FUNMUX1_PWM3B_OUT, 0);
-#endif
-        }
-        else if (pwm_drv[i].cfg->PWMx == PWM4)
-        {
-#ifdef BSP_USING_PWM4A
-            PORT_Init(PORTN, PIN8, FUNMUX0_PWM4A_OUT, 0);
-#endif
-#ifdef BSP_USING_PWM4B
-            PORT_Init(PORTN, PIN10, FUNMUX0_PWM4B_OUT, 0);
-#endif
-        }
-        else if (pwm_drv[i].cfg->PWMx == PWM5)
-        {
-#ifdef BSP_USING_PWM5A
-            PORT_Init(PORTN, PIN7, FUNMUX1_PWM5A_OUT, 0);
-#endif
-#ifdef BSP_USING_PWM5B
-            PORT_Init(PORTN, PIN9, FUNMUX1_PWM5B_OUT, 0);
-#endif
-        }
-
-        PWM_Init(pwm_drv[i].cfg->PWMx, &(pwm_drv[i].cfg->pwm_initstruct));
-        if (rt_device_pwm_register(&pwm_drv[i].pwm_device, pwm_drv[i].cfg->name, &pwm_ops, pwm_drv[i].cfg) == RT_EOK)
-        {
-            LOG_D("%s register success", pwm_drv[i].cfg->name);
-        }
-        else
-        {
-            LOG_E("%s register failed", pwm_drv[i].cfg->name);
-            result = -RT_ERROR;
-        }
-    }
-    return result;
-}
-INIT_DEVICE_EXPORT(rt_hw_pwm_init);
-
-#endif /* BSP_USING_PWM */
-#endif /* RT_USING_PWM */

bsp/swm320/drivers/drv_pwm.h

@@ -1,164 +0,0 @@
-/*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-12-10     Zohar_Lee    first version
- * 2020-07-10     lik          rewrite
- */
-
-#ifndef __DRV_PWM_H__
-#define __DRV_PWM_H__
-
-#include "board.h"
-
-struct swm_pwm_cfg
-{
-    const char *name;
-    PWM_TypeDef *PWMx;
-    PWM_InitStructure pwm_initstruct;
-};
-
-struct swm_pwm
-{
-    struct swm_pwm_cfg *cfg;
-    struct rt_device_pwm pwm_device;
-};
-
-#ifdef BSP_USING_PWM0
-#ifndef PWM0_CFG
-#define PWM0_CFG                                \
-    {                                           \
-        .name = "pwm0",                         \
-        .PWMx = PWM0,                           \
-        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
-        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
-        .pwm_initstruct.cycleA = 10000,         \
-        .pwm_initstruct.hdutyA = 5000,          \
-        .pwm_initstruct.initLevelA = 1,         \
-        .pwm_initstruct.cycleB = 10000,         \
-        .pwm_initstruct.hdutyB = 5000,          \
-        .pwm_initstruct.initLevelB = 1,         \
-        .pwm_initstruct.HEndAIEn = 0,           \
-        .pwm_initstruct.NCycleAIEn = 0,         \
-        .pwm_initstruct.HEndBIEn = 0,           \
-        .pwm_initstruct.NCycleBIEn = 0,         \
-    }
-#endif /* PWM0_CFG */
-#endif /* BSP_USING_PWM0 */
-
-#ifdef BSP_USING_PWM1
-#ifndef PWM1_CFG
-#define PWM1_CFG                                \
-    {                                           \
-        .name = "pwm1",                         \
-        .PWMx = PWM1,                           \
-        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
-        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
-        .pwm_initstruct.cycleA = 10000,         \
-        .pwm_initstruct.hdutyA = 5000,          \
-        .pwm_initstruct.initLevelA = 1,         \
-        .pwm_initstruct.cycleB = 10000,         \
-        .pwm_initstruct.hdutyB = 5000,          \
-        .pwm_initstruct.initLevelB = 1,         \
-        .pwm_initstruct.HEndAIEn = 0,           \
-        .pwm_initstruct.NCycleAIEn = 0,         \
-        .pwm_initstruct.HEndBIEn = 0,           \
-        .pwm_initstruct.NCycleBIEn = 0,         \
-    }
-#endif /* PWM1_CFG */
-#endif /* BSP_USING_PWM1 */
-
-#ifdef BSP_USING_PWM2
-#ifndef PWM2_CFG
-#define PWM2_CFG                                \
-    {                                           \
-        .name = "pwm2",                         \
-        .PWMx = PWM2,                           \
-        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
-        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
-        .pwm_initstruct.cycleA = 10000,         \
-        .pwm_initstruct.hdutyA = 5000,          \
-        .pwm_initstruct.initLevelA = 1,         \
-        .pwm_initstruct.cycleB = 10000,         \
-        .pwm_initstruct.hdutyB = 5000,          \
-        .pwm_initstruct.initLevelB = 1,         \
-        .pwm_initstruct.HEndAIEn = 0,           \
-        .pwm_initstruct.NCycleAIEn = 0,         \
-        .pwm_initstruct.HEndBIEn = 0,           \
-        .pwm_initstruct.NCycleBIEn = 0,         \
-    }
-#endif /* PWM2_CFG */
-#endif /* BSP_USING_PWM2 */
-
-#ifdef BSP_USING_PWM3
-#ifndef PWM3_CFG
-#define PWM3_CFG                                \
-    {                                           \
-        .name = "pwm3",                         \
-        .PWMx = PWM3,                           \
-        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
-        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
-        .pwm_initstruct.cycleA = 10000,         \
-        .pwm_initstruct.hdutyA = 5000,          \
-        .pwm_initstruct.initLevelA = 1,         \
-        .pwm_initstruct.cycleB = 10000,         \
-        .pwm_initstruct.hdutyB = 5000,          \
-        .pwm_initstruct.initLevelB = 1,         \
-        .pwm_initstruct.HEndAIEn = 0,           \
-        .pwm_initstruct.NCycleAIEn = 0,         \
-        .pwm_initstruct.HEndBIEn = 0,           \
-        .pwm_initstruct.NCycleBIEn = 0,         \
-    }
-#endif /* PWM3_CFG */
-#endif /* BSP_USING_PWM3 */
-
-#ifdef BSP_USING_PWM4
-#ifndef PWM4_CFG
-#define PWM4_CFG                                \
-    {                                           \
-        .name = "pwm4",                         \
-        .PWMx = PWM4,                           \
-        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
-        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
-        .pwm_initstruct.cycleA = 10000,         \
-        .pwm_initstruct.hdutyA = 5000,          \
-        .pwm_initstruct.initLevelA = 1,         \
-        .pwm_initstruct.cycleB = 10000,         \
-        .pwm_initstruct.hdutyB = 5000,          \
-        .pwm_initstruct.initLevelB = 1,         \
-        .pwm_initstruct.HEndAIEn = 0,           \
-        .pwm_initstruct.NCycleAIEn = 0,         \
-        .pwm_initstruct.HEndBIEn = 0,           \
-        .pwm_initstruct.NCycleBIEn = 0,         \
-    }
-#endif /* PWM4_CFG */
-#endif /* BSP_USING_PWM4 */
-
-#ifdef BSP_USING_PWM5
-#ifndef PWM5_CFG
-#define PWM5_CFG                                \
-    {                                           \
-        .name = "pwm5",                         \
-        .PWMx = PWM5,                           \
-        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
-        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
-        .pwm_initstruct.cycleA = 10000,         \
-        .pwm_initstruct.hdutyA = 5000,          \
-        .pwm_initstruct.initLevelA = 1,         \
-        .pwm_initstruct.cycleB = 10000,         \
-        .pwm_initstruct.hdutyB = 5000,          \
-        .pwm_initstruct.initLevelB = 1,         \
-        .pwm_initstruct.HEndAIEn = 0,           \
-        .pwm_initstruct.NCycleAIEn = 0,         \
-        .pwm_initstruct.HEndBIEn = 0,           \
-        .pwm_initstruct.NCycleBIEn = 0,         \
-    }
-#endif /* PWM5_CFG */
-#endif /* BSP_USING_PWM5 */
-
-int rt_hw_pwm_init(void);
-
-#endif /* __DRV_PWM_H__ */

bsp/swm320/drivers/drv_sdio.h

@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-07-10     lik          first version
- */
-
-#ifndef __DRV_SDIO_H__
-#define __DRV_SDIO_H__
-
-#include "board.h"
-
-#define SDIO_BUFF_SIZE 4096
-#define SDIO_ALIGN_LEN 4
-
-#ifndef SDIO_MAX_FREQ
-#define SDIO_MAX_FREQ (30000000)
-#endif
-
-struct sdio_pkg
-{
-    struct rt_mmcsd_cmd *cmd;
-    void *buff;
-    rt_uint32_t flag;
-};
-
-typedef rt_err_t (*sdio_txconfig)(struct sdio_pkg *pkg, rt_uint32_t *buff, int size);
-typedef rt_err_t (*sdio_rxconfig)(struct sdio_pkg *pkg, rt_uint32_t *buff, int size);
-typedef rt_uint32_t (*sdio_clk_get)(SDIO_TypeDef *hw_sdio);
-
-struct swm_sdio_des
-{
-    SDIO_TypeDef *hw_sdio;
-    sdio_txconfig txconfig;
-    sdio_rxconfig rxconfig;
-    sdio_clk_get clk_get;
-};
-
-#endif /* __DRV_SDIO_H__ */

bsp/swm320/drivers/drv_soft_i2c.c

@@ -1,197 +0,0 @@
-/*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-05-31     ZYH          first version
- * 2018-12-10     Zohar_Lee    format file
- * 2020-07-10     lik          rewrite
- */
-
-#include "drv_soft_i2c.h"
-
-#ifdef RT_USING_I2C
-#ifdef BSP_USING_I2C
-
-/***************************************************************
-*!!!!!!!!!!!!!!!!!!!!!!!!!!!!NOTICE!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-*In order to use swm drv_soft_i2c,you need to commented out
-line 114 (SDA_H(ops);) and line 167 (SDA_H(ops);) in i2c-bit-ops.c
-At the same time, add one line (SDA_L(ops);)after line 154 (SCL_L(ops);)
-in i2c-bit-ops.c
-***************************************************************/
-
-//#define DRV_DEBUG
-#define LOG_TAG "drv.i2c"
-#include <drv_log.h>
-
-#if !defined(BSP_USING_I2C0) && !defined(BSP_USING_I2C1)
-#error "Please define at least one BSP_USING_I2Cx"
-/* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */
-#endif
-
-static const struct swm_soft_i2c_cfg soft_i2c_cfg[] =
-    {
-#ifdef BSP_USING_I2C0
-        I2C0_BUS_CFG,
-#endif
-#ifdef BSP_USING_I2C1
-        I2C1_BUS_CFG,
-#endif
-};
-
-static struct swm_i2c i2c_drv[sizeof(soft_i2c_cfg) / sizeof(soft_i2c_cfg[0])];
-
-/**
- * This function initializes the i2c pin.
- *
- * @param swm i2c dirver class.
- */
-static void swm_i2c_gpio_init(struct swm_i2c *i2c)
-{
-    struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)i2c->ops.data;
-
-    rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
-    rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
-
-    rt_pin_write(cfg->scl, PIN_HIGH);
-    rt_pin_write(cfg->sda, PIN_HIGH);
-}
-
-/**
- * This function sets the sda pin.
- *
- * @param swm config class.
- * @param The sda pin state.
- */
-static void swm_set_sda(void *data, rt_int32_t state)
-{
-    struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data;
-    rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
-    if (state)
-    {
-        rt_pin_write(cfg->sda, PIN_HIGH);
-    }
-    else
-    {
-        rt_pin_write(cfg->sda, PIN_LOW);
-    }
-}
-
-/**
- * This function sets the scl pin.
- *
- * @param swm config class.
- * @param The scl pin state.
- */
-static void swm_set_scl(void *data, rt_int32_t state)
-{
-    struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data;
-    rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
-    if (state)
-    {
-        rt_pin_write(cfg->scl, PIN_HIGH);
-    }
-    else
-    {
-        rt_pin_write(cfg->scl, PIN_LOW);
-    }
-}
-
-/**
- * This function gets the sda pin state.
- *
- * @param The sda pin state.
- */
-static rt_int32_t swm_get_sda(void *data)
-{
-    struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data;
-    rt_pin_mode(cfg->sda, PIN_MODE_INPUT_PULLUP);
-    return rt_pin_read(cfg->sda);
-}
-
-/**
- * This function gets the scl pin state.
- *
- * @param The scl pin state.
- */
-static rt_int32_t swm_get_scl(void *data)
-{
-    struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data;
-    rt_pin_mode(cfg->scl, PIN_MODE_INPUT_PULLUP);
-    return rt_pin_read(cfg->scl);
-}
-
-/**
- * The time delay function.
- *
- * @param microseconds.
- */
-static void swm_udelay(rt_uint32_t us)
-{
-    rt_uint32_t ticks;
-    rt_uint32_t told, tnow, tcnt = 0;
-    rt_uint32_t reload = SysTick->LOAD;
-
-    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
-    told = SysTick->VAL;
-    while (1)
-    {
-        tnow = SysTick->VAL;
-        if (tnow != told)
-        {
-            if (tnow < told)
-            {
-                tcnt += told - tnow;
-            }
-            else
-            {
-                tcnt += reload - tnow + told;
-            }
-            told = tnow;
-            if (tcnt >= ticks)
-            {
-                break;
-            }
-        }
-    }
-}
-
-static const struct rt_i2c_bit_ops swm_bit_ops =
-    {
-        .data = RT_NULL,
-        .set_sda = swm_set_sda,
-        .set_scl = swm_set_scl,
-        .get_sda = swm_get_sda,
-        .get_scl = swm_get_scl,
-        .udelay = swm_udelay,
-        .delay_us = 1,
-        .timeout = 100};
-
-/* I2C initialization function */
-int rt_hw_i2c_init(void)
-{
-    rt_err_t result;
-
-    for (int i = 0; i < sizeof(i2c_drv) / sizeof(struct swm_i2c); i++)
-    {
-        i2c_drv[i].ops = swm_bit_ops;
-        i2c_drv[i].ops.data = (void *)&soft_i2c_cfg[i];
-        i2c_drv[i].i2c2_bus.priv = &i2c_drv[i].ops;
-        swm_i2c_gpio_init(&i2c_drv[i]);
-        result = rt_i2c_bit_add_bus(&i2c_drv[i].i2c2_bus, soft_i2c_cfg[i].name);
-        RT_ASSERT(result == RT_EOK);
-
-        LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
-              soft_i2c_cfg[i].name,
-              soft_i2c_cfg[i].scl,
-              soft_i2c_cfg[i].sda);
-    }
-
-    return RT_EOK;
-}
-INIT_DEVICE_EXPORT(rt_hw_i2c_init);
-#endif /* BSP_USING_I2C */
-#endif /* RT_USING_I2C */

bsp/swm320/drivers/drv_soft_i2c.h

@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-12-10     Zohar_Lee    first version
- * 2020-07-10     lik          rewrite
- */
-
-#ifndef __DRV_SOFT_I2C_H__
-#define __DRV_SOFT_I2C_H__
-
-#include "board.h"
-
-/* swm config class */
-struct swm_soft_i2c_cfg
-{
-    rt_uint8_t scl;
-    rt_uint8_t sda;
-    const char *name;
-};
-/* swm i2c dirver class */
-struct swm_i2c
-{
-    struct rt_i2c_bit_ops ops;
-    struct rt_i2c_bus_device i2c2_bus;
-};
-
-#ifdef BSP_USING_I2C0
-#define I2C0_BUS_CFG             \
-    {                            \
-        .scl = BSP_I2C0_SCL_PIN, \
-        .sda = BSP_I2C0_SDA_PIN, \
-        .name = "i2c0",          \
-    }
-#endif
-
-#ifdef BSP_USING_I2C1
-#define I2C1_BUS_CFG             \
-    {                            \
-        .scl = BSP_I2C1_SCL_PIN, \
-        .sda = BSP_I2C1_SDA_PIN, \
-        .name = "i2c1",          \
-    }
-#endif
-
-int rt_hw_i2c_init(void);
-
-#endif /* __DRV_SOFT_I2C_H__ */

bsp/swm320/drivers/drv_spi.h

@@ -1,80 +0,0 @@
-/*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-12-10     Zohar_Lee    first version
- * 2020-07-10     lik          rewrite
- */
-
-#ifndef __DRV_SPI_H__
-#define __DRV_SPI_H__
-
-#include "board.h"
-
-struct swm_spi_cs
-{
-    GPIO_TypeDef *GPIOx;
-    uint32_t gpio_pin;
-};
-
-struct swm_spi_cfg
-{
-    const char *name;
-    SPI_TypeDef *SPIx;
-    SPI_InitStructure spi_initstruct;
-};
-
-/* swm spi dirver class */
-struct swm_spi
-{
-    struct swm_spi_cfg *cfg;
-    struct rt_spi_configuration *configure;
-    struct rt_spi_bus spi_bus;
-};
-
-#ifdef BSP_USING_SPI0
-#ifndef SPI0_BUS_CONFIG
-#define SPI0_BUS_CONFIG                               \
-    {                                                 \
-        .name = "spi0",                               \
-        .SPIx = SPI0,                                 \
-        .spi_initstruct.clkDiv = SPI_CLKDIV_32,       \
-        .spi_initstruct.FrameFormat = SPI_FORMAT_SPI, \
-        .spi_initstruct.SampleEdge = SPI_SECOND_EDGE, \
-        .spi_initstruct.IdleLevel = SPI_HIGH_LEVEL,   \
-        .spi_initstruct.WordSize = 8,                 \
-        .spi_initstruct.Master = 1,                   \
-        .spi_initstruct.RXHFullIEn = 0,               \
-        .spi_initstruct.TXEmptyIEn = 0,               \
-        .spi_initstruct.TXCompleteIEn = 0,            \
-    }
-#endif /* SPI1_BUS_CONFIG */
-#endif /* BSP_USING_SPI1 */
-
-#ifdef BSP_USING_SPI1
-#ifndef SPI1_BUS_CONFIG
-#define SPI1_BUS_CONFIG                               \
-    {                                                 \
-        .name = "spi1",                               \
-        .SPIx = SPI1,                                 \
-        .spi_initstruct.clkDiv = SPI_CLKDIV_32,       \
-        .spi_initstruct.FrameFormat = SPI_FORMAT_SPI, \
-        .spi_initstruct.SampleEdge = SPI_SECOND_EDGE, \
-        .spi_initstruct.IdleLevel = SPI_HIGH_LEVEL,   \
-        .spi_initstruct.WordSize = 8,                 \
-        .spi_initstruct.Master = 1,                   \
-        .spi_initstruct.RXHFullIEn = 0,               \
-        .spi_initstruct.TXEmptyIEn = 0,               \
-        .spi_initstruct.TXCompleteIEn = 0,            \
-    }
-#endif /* SPI1_BUS_CONFIG */
-#endif /* BSP_USING_SPI1 */
-
-//cannot be used before completion init
-rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *GPIOx, uint32_t n);
-int rt_hw_spi_init(void);
-
-#endif /* __DRV_SPI_H__ */

bsp/swm320/drivers/drv_uart.c

@@ -1,284 +0,0 @@
-/*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-05-31     ZYH          first version
- * 2018-12-10     Zohar_Lee    format file
- * 2020-07-10     lik          format file
- */
-
-#include "drv_uart.h"
-
-#ifdef RT_USING_SERIAL
-#ifdef BSP_USING_UART
-
-//#define DRV_DEBUG
-#define LOG_TAG "drv.uart"
-#include <drv_log.h>
-
-#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \
-    !defined(BSP_USING_UART3)
-#error "Please define at least one BSP_USING_UARTx"
-/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
-#endif
-
-enum
-{
-#ifdef BSP_USING_UART0
-    UART0_INDEX,
-#endif
-#ifdef BSP_USING_UART1
-    UART1_INDEX,
-#endif
-#ifdef BSP_USING_UART2
-    UART2_INDEX,
-#endif
-#ifdef BSP_USING_UART3
-    UART3_INDEX,
-#endif
-};
-
-static struct swm_uart_cfg uart_cfg[] =
-    {
-#ifdef BSP_USING_UART0
-        UART0_CFG,
-#endif
-#ifdef BSP_USING_UART1
-        UART1_CFG,
-#endif
-#ifdef BSP_USING_UART2
-        UART2_CFG,
-#endif
-#ifdef BSP_USING_UART3
-        UART3_CFG,
-#endif
-};
-
-static struct swm_uart uart_drv[sizeof(uart_cfg) / sizeof(uart_cfg[0])] = {0};
-
-static rt_err_t swm_uart_init(struct rt_serial_device *serial_device, struct serial_configure *configure)
-{
-    struct swm_uart_cfg *cfg;
-    RT_ASSERT(serial_device != RT_NULL);
-    RT_ASSERT(configure != RT_NULL);
-    cfg = serial_device->parent.user_data;
-
-    cfg->uart_initstruct.Baudrate = configure->baud_rate;
-    switch (configure->data_bits)
-    {
-    case DATA_BITS_8:
-        cfg->uart_initstruct.DataBits = UART_DATA_8BIT;
-        break;
-    case DATA_BITS_9:
-        cfg->uart_initstruct.DataBits = UART_DATA_9BIT;
-        break;
-    default:
-        cfg->uart_initstruct.DataBits = UART_DATA_8BIT;
-        break;
-    }
-    switch (configure->stop_bits)
-    {
-    case STOP_BITS_1:
-        cfg->uart_initstruct.StopBits = UART_STOP_1BIT;
-        break;
-    case STOP_BITS_2:
-        cfg->uart_initstruct.StopBits = UART_STOP_2BIT;
-        break;
-    default:
-        cfg->uart_initstruct.StopBits = UART_STOP_1BIT;
-        break;
-    }
-    switch (configure->parity)
-    {
-    case PARITY_NONE:
-        cfg->uart_initstruct.Parity = UART_PARITY_NONE;
-        break;
-    case PARITY_ODD:
-        cfg->uart_initstruct.Parity = UART_PARITY_ODD;
-        break;
-    case PARITY_EVEN:
-        cfg->uart_initstruct.Parity = UART_PARITY_EVEN;
-        break;
-    default:
-        cfg->uart_initstruct.Parity = UART_PARITY_NONE;
-        break;
-    }
-    switch ((uint32_t)cfg->UARTx)
-    {
-    case ((uint32_t)UART0):
-        PORT_Init(PORTA, PIN2, FUNMUX0_UART0_RXD, 1);
-        PORT_Init(PORTA, PIN3, FUNMUX1_UART0_TXD, 0);
-        break;
-    case ((uint32_t)UART1):
-        PORT_Init(PORTC, PIN2, FUNMUX0_UART1_RXD, 1);
-        PORT_Init(PORTC, PIN3, FUNMUX1_UART1_TXD, 0);
-        break;
-    case ((uint32_t)UART2):
-        PORT_Init(PORTC, PIN4, FUNMUX0_UART2_RXD, 1);
-        PORT_Init(PORTC, PIN5, FUNMUX1_UART2_TXD, 0);
-        break;
-    case ((uint32_t)UART3):
-        PORT_Init(PORTC, PIN6, FUNMUX0_UART3_RXD, 1);
-        PORT_Init(PORTC, PIN7, FUNMUX1_UART3_TXD, 0);
-        break;
-    default:
-        break;
-    }
-    UART_Init(cfg->UARTx, &(cfg->uart_initstruct));
-    UART_Open(cfg->UARTx);
-    return RT_EOK;
-}
-
-static rt_err_t swm_uart_control(struct rt_serial_device *serial_device, int cmd, void *arg)
-{
-    struct swm_uart_cfg *cfg;
-    RT_ASSERT(serial_device != RT_NULL);
-    cfg = serial_device->parent.user_data;
-
-    switch (cmd)
-    {
-    case RT_DEVICE_CTRL_CLR_INT:
-        /* disable rx irq */
-        NVIC_DisableIRQ(cfg->irq);
-        break;
-    case RT_DEVICE_CTRL_SET_INT:
-        /* enable rx irq */
-        NVIC_EnableIRQ(cfg->irq);
-        break;
-    }
-    return RT_EOK;
-}
-
-static int swm_uart_putc(struct rt_serial_device *serial_device, char c)
-{
-    struct swm_uart_cfg *cfg;
-    RT_ASSERT(serial_device != RT_NULL);
-    cfg = serial_device->parent.user_data;
-
-    while (UART_IsTXFIFOFull(cfg->UARTx))
-        ;
-    UART_WriteByte(cfg->UARTx, c);
-    while (UART_IsTXBusy(cfg->UARTx))
-        ;
-    return 1;
-}
-
-static int swm_uart_getc(struct rt_serial_device *serial_device)
-{
-    int ch;
-    struct swm_uart_cfg *cfg;
-    RT_ASSERT(serial_device != RT_NULL);
-    cfg = serial_device->parent.user_data;
-
-    ch = -1;
-    if (UART_IsRXFIFOEmpty(cfg->UARTx) == 0)
-    {
-        UART_ReadByte(cfg->UARTx, (uint32_t *)&ch);
-    }
-    return ch;
-}
-
-static const struct rt_uart_ops swm_uart_ops =
-    {
-        .configure = swm_uart_init,
-        .control = swm_uart_control,
-        .putc = swm_uart_putc,
-        .getc = swm_uart_getc,
-        .dma_transmit = RT_NULL};
-
-/**
- * Uart common interrupt process. This need add to uart ISR.
- *
- * @param serial serial device
- */
-static void rt_hw_uart_isr(struct rt_serial_device *serial_device)
-{
-    struct swm_uart_cfg *cfg;
-    RT_ASSERT(serial_device != RT_NULL);
-    cfg = serial_device->parent.user_data;
-
-    /* UART in mode Receiver -------------------------------------------------*/
-    if (UART_INTRXThresholdStat(cfg->UARTx) || UART_INTTimeoutStat(cfg->UARTx))
-    {
-        rt_hw_serial_isr(serial_device, RT_SERIAL_EVENT_RX_IND);
-    }
-}
-
-#if defined(BSP_USING_UART0)
-void UART0_Handler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    rt_hw_uart_isr(&(uart_drv[UART0_INDEX].serial_device));
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif /* BSP_USING_UART0 */
-
-#if defined(BSP_USING_UART1)
-void UART1_Handler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    rt_hw_uart_isr(&(uart_drv[UART1_INDEX].serial_device));
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif /* BSP_USING_UART1 */
-
-#if defined(BSP_USING_UART2)
-void UART2_Handler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    rt_hw_uart_isr(&(uart_drv[UART2_INDEX].serial_device));
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif /* BSP_USING_UART2 */
-
-#if defined(BSP_USING_UART3)
-void UART3_Handler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    rt_hw_uart_isr(&(uart_drv[UART3_INDEX].serial_device));
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif /* BSP_USING_UART3 */
-
-int rt_hw_uart_init(void)
-{
-    struct serial_configure cfg = RT_SERIAL_CONFIG_DEFAULT;
-    int i = 0;
-    rt_err_t result = RT_EOK;
-
-    for (i = 0; i < sizeof(uart_cfg) / sizeof(uart_cfg[0]); i++)
-    {
-        uart_drv[i].cfg = &uart_cfg[i];
-        uart_drv[i].serial_device.ops = &swm_uart_ops;
-        uart_drv[i].serial_device.config = cfg;
-        /* register UART device */
-        result = rt_hw_serial_register(&uart_drv[i].serial_device, uart_drv[i].cfg->name,
-                                       RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart_drv[i].cfg);
-        RT_ASSERT(result == RT_EOK);
-    }
-
-    return result;
-}
-INIT_BOARD_EXPORT(rt_hw_uart_init);
-
-#endif /* BSP_USING_UART */
-#endif /* RT_USING_SERIAL */

bsp/swm320/drivers/drv_uart.h

@@ -1,115 +0,0 @@
-/*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-12-10     Zohar_Lee    first version
- * 2020-07-10     lik          rewrite
- */
-
-#ifndef __DRV_UART_H__
-#define __DRV_UART_H__
-
-#include "board.h"
-
-/* swm config class */
-struct swm_uart_cfg
-{
-    const char *name;
-    UART_TypeDef *UARTx;
-    IRQn_Type irq;
-    UART_InitStructure uart_initstruct;
-};
-
-/* swm uart dirver class */
-struct swm_uart
-{
-    struct swm_uart_cfg *cfg;
-    struct rt_serial_device serial_device;
-};
-
-#ifdef BSP_USING_UART0
-#ifndef UART0_CFG
-#define UART0_CFG                                   \
-    {                                               \
-        .name = "uart0",                            \
-        .UARTx = UART0,                             \
-        .irq = UART0_IRQn,                          \
-        .uart_initstruct.Baudrate = 115200,         \
-        .uart_initstruct.DataBits = UART_DATA_8BIT, \
-        .uart_initstruct.Parity = UART_PARITY_NONE, \
-        .uart_initstruct.StopBits = UART_STOP_1BIT, \
-        .uart_initstruct.RXThreshold = 0,           \
-        .uart_initstruct.RXThresholdIEn = 1,        \
-        .uart_initstruct.TXThresholdIEn = 0,        \
-        .uart_initstruct.TimeoutTime = 10,          \
-        .uart_initstruct.TimeoutIEn = 1,            \
-    }
-#endif /* UART0_CFG */
-#endif /* BSP_USING_UART0 */
-
-#ifdef BSP_USING_UART1
-#ifndef UART1_CFG
-#define UART1_CFG                                   \
-    {                                               \
-        .name = "uart1",                            \
-        .UARTx = UART1,                             \
-        .irq = UART1_IRQn,                          \
-        .uart_initstruct.Baudrate = 115200,         \
-        .uart_initstruct.DataBits = UART_DATA_8BIT, \
-        .uart_initstruct.Parity = UART_PARITY_NONE, \
-        .uart_initstruct.StopBits = UART_STOP_1BIT, \
-        .uart_initstruct.RXThreshold = 0,           \
-        .uart_initstruct.RXThresholdIEn = 1,        \
-        .uart_initstruct.TXThresholdIEn = 0,        \
-        .uart_initstruct.TimeoutTime = 10,          \
-        .uart_initstruct.TimeoutIEn = 1,            \
-    }
-#endif /* UART1_CFG */
-#endif /* BSP_USING_UART1 */
-
-#ifdef BSP_USING_UART2
-#ifndef UART2_CFG
-#define UART2_CFG                                   \
-    {                                               \
-        .name = "uart2",                            \
-        .UARTx = UART2,                             \
-        .irq = UART2_IRQn,                          \
-        .uart_initstruct.Baudrate = 115200,         \
-        .uart_initstruct.DataBits = UART_DATA_8BIT, \
-        .uart_initstruct.Parity = UART_PARITY_NONE, \
-        .uart_initstruct.StopBits = UART_STOP_1BIT, \
-        .uart_initstruct.RXThreshold = 0,           \
-        .uart_initstruct.RXThresholdIEn = 1,        \
-        .uart_initstruct.TXThresholdIEn = 0,        \
-        .uart_initstruct.TimeoutTime = 10,          \
-        .uart_initstruct.TimeoutIEn = 1,            \
-    }
-#endif /* UART2_CFG */
-#endif /* BSP_USING_UART2 */
-
-#ifdef BSP_USING_UART3
-#ifndef UART3_CFG
-#define UART3_CFG                                   \
-    {                                               \
-        .name = "uart3",                            \
-        .UARTx = UART3,                             \
-        .irq = UART3_IRQn,                          \
-        .uart_initstruct.Baudrate = 115200,         \
-        .uart_initstruct.DataBits = UART_DATA_8BIT, \
-        .uart_initstruct.Parity = UART_PARITY_NONE, \
-        .uart_initstruct.StopBits = UART_STOP_1BIT, \
-        .uart_initstruct.RXThreshold = 0,           \
-        .uart_initstruct.RXThresholdIEn = 1,        \
-        .uart_initstruct.TXThresholdIEn = 0,        \
-        .uart_initstruct.TimeoutTime = 10,          \
-        .uart_initstruct.TimeoutIEn = 1,            \
-    }
-#endif /* UART3_CFG */
-#endif /* BSP_USING_UART3 */
-
-int rt_hw_serial_init(void);
-
-#endif /* __DRV_UART_H__ */

bsp/swm320/drivers/drv_wdt.c

@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-12-10     Zohar_Lee    first version
- * 2020-07-10     lik          format file
- */
-
-#include "drv_wdt.h"
-
-#ifdef RT_USING_WDT
-#ifdef BSP_USING_WDT
-//#define DRV_DEBUG
-#define LOG_TAG "drv.wdt"
-#include <drv_log.h>
-
-static struct swm_wdt_cfg wdt_cfg =
-    {
-        .name = "wdt",
-        .WDTx = WDT,
-};
-
-static struct swm_wdt wdt_drv;
-
-static rt_err_t swm_wdt_init(rt_watchdog_t *wdt_device)
-{
-    return RT_EOK;
-}
-
-static rt_err_t swm_wdt_control(rt_watchdog_t *wdt_device, int cmd, void *arg)
-{
-    struct swm_wdt_cfg *cfg;
-    RT_ASSERT(wdt_device != RT_NULL);
-    cfg = wdt_device->parent.user_data;
-
-    switch (cmd)
-    {
-    case RT_DEVICE_CTRL_WDT_KEEPALIVE:
-        WDT_Feed(cfg->WDTx);
-        break;
-    case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
-        WDT_Init(cfg->WDTx, (SystemCoreClock * (*(rt_uint32_t *)arg)), WDT_MODE_RESET);
-        break;
-    case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
-        *(rt_uint32_t *)arg = (cfg->WDTx->LOAD) / SystemCoreClock;
-        break;
-    case RT_DEVICE_CTRL_WDT_GET_TIMELEFT:
-        *(rt_uint32_t *)arg = WDT_GetValue(cfg->WDTx) / SystemCoreClock;
-        break;
-    case RT_DEVICE_CTRL_WDT_START:
-        WDT_Start(cfg->WDTx);
-        break;
-    case RT_DEVICE_CTRL_WDT_STOP:
-        WDT_Stop(cfg->WDTx);
-        break;
-    default:
-        LOG_W("This command is not supported.");
-        return -RT_ERROR;
-    }
-
-    return RT_EOK;
-}
-
-const static struct rt_watchdog_ops swm_wdt_ops =
-    {
-        swm_wdt_init,
-        swm_wdt_control};
-
-int rt_hw_wdt_init(void)
-{
-    wdt_drv.cfg = &wdt_cfg;
-    wdt_drv.wdt_device.ops = &swm_wdt_ops;
-
-    if (rt_hw_watchdog_register(&wdt_drv.wdt_device, wdt_drv.cfg->name, RT_DEVICE_FLAG_RDWR, wdt_drv.cfg) != RT_EOK)
-    {
-        LOG_E("wdt device register failed.");
-        return -RT_ERROR;
-    }
-    LOG_D("wdt device register success.");
-    return RT_EOK;
-}
-INIT_BOARD_EXPORT(rt_hw_wdt_init);
-
-#endif /* BSP_USING_WDT */
-#endif /* RT_USING_WDT */

bsp/swm320/libraries/CMSIS/CoreSupport/core_cm0.h

@@ -1,692 +0,0 @@
-/**************************************************************************/ /**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V4.00
- * @date     22. August 2014
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-#if defined(__ICCARM__)
-#pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M0
-  @{
- */
-
-/*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version   */
-#define __CM0_CMSIS_VERSION_SUB (0x00)  /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
-                             __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M (0x00) /*!< Cortex-M Core                    */
-
-#if defined(__CC_ARM)
-#define __ASM __asm       /*!< asm keyword for ARM Compiler          */
-#define __INLINE __inline /*!< inline keyword for ARM Compiler       */
-#define __STATIC_INLINE static __inline
-
-#elif defined(__GNUC__)
-#define __ASM __asm     /*!< asm keyword for GNU Compiler          */
-#define __INLINE inline /*!< inline keyword for GNU Compiler       */
-#define __STATIC_INLINE static inline
-
-#elif defined(__ICCARM__)
-#define __ASM __asm     /*!< asm keyword for IAR Compiler          */
-#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-#define __STATIC_INLINE static inline
-
-#elif defined(__TMS470__)
-#define __ASM __asm /*!< asm keyword for TI CCS Compiler       */
-#define __STATIC_INLINE static inline
-
-#elif defined(__TASKING__)
-#define __ASM __asm     /*!< asm keyword for TASKING Compiler      */
-#define __INLINE inline /*!< inline keyword for TASKING Compiler   */
-#define __STATIC_INLINE static inline
-
-#elif defined(__CSMC__)
-#define __packed
-#define __ASM _asm      /*!< asm keyword for COSMIC Compiler      */
-#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-#define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED 0
-
-#if defined(__CC_ARM)
-#if defined __TARGET_FPU_VFP
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined(__GNUC__)
-#if defined(__VFP_FP__) && !defined(__SOFTFP__)
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined(__ICCARM__)
-#if defined __ARMVFP__
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined(__TMS470__)
-#if defined __TI__VFP_SUPPORT____
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined(__TASKING__)
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined(__CSMC__) /* Cosmic */
-#if (__CSMC__ & 0x400)  // FPU present for parser
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-#endif
-
-#include <stdint.h>       /* standard types definitions                      */
-#include <core_cmInstr.h> /* Core Instruction Access                         */
-#include <core_cmFunc.h>  /* Core Function Access                            */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM0_REV
-#define __CM0_REV 0x0000
-#warning "__CM0_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS 2
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig 0
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define __I volatile /*!< Defines 'read only' permissions                 */
-#else
-#define __I volatile const /*!< Defines 'read only' permissions                 */
-#endif
-#define __O volatile  /*!< Defines 'write only' permissions                */
-#define __IO volatile /*!< Defines 'read / write' permissions              */
-
-    /*@} end of group Cortex_M0 */
-
-    /*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
- ******************************************************************************/
-    /** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-    /** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-    /** \brief  Union type to access the Application Program Status Register (APSR).
- */
-    typedef union
-    {
-        struct
-        {
-#if (__CORTEX_M != 0x04)
-            uint32_t _reserved0 : 27; /*!< bit:  0..26  Reserved                           */
-#else
-        uint32_t _reserved0 : 16; /*!< bit:  0..15  Reserved                           */
-        uint32_t GE : 4;          /*!< bit: 16..19  Greater than or Equal flags        */
-        uint32_t _reserved1 : 7;  /*!< bit: 20..26  Reserved                           */
-#endif
-            uint32_t Q : 1; /*!< bit:     27  Saturation condition flag          */
-            uint32_t V : 1; /*!< bit:     28  Overflow condition code flag       */
-            uint32_t C : 1; /*!< bit:     29  Carry condition code flag          */
-            uint32_t Z : 1; /*!< bit:     30  Zero condition code flag           */
-            uint32_t N : 1; /*!< bit:     31  Negative condition code flag       */
-        } b;                /*!< Structure used for bit  access                  */
-        uint32_t w;         /*!< Type      used for word access                  */
-    } APSR_Type;
-
-    /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-    typedef union
-    {
-        struct
-        {
-            uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number                   */
-            uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved                           */
-        } b;                          /*!< Structure used for bit  access                  */
-        uint32_t w;                   /*!< Type      used for word access                  */
-    } IPSR_Type;
-
-    /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-    typedef union
-    {
-        struct
-        {
-            uint32_t ISR : 9; /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-            uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved                           */
-#else
-        uint32_t _reserved0 : 7;  /*!< bit:  9..15  Reserved                           */
-        uint32_t GE : 4;          /*!< bit: 16..19  Greater than or Equal flags        */
-        uint32_t _reserved1 : 4;  /*!< bit: 20..23  Reserved                           */
-#endif
-            uint32_t T : 1;  /*!< bit:     24  Thumb bit        (read 0)          */
-            uint32_t IT : 2; /*!< bit: 25..26  saved IT state   (read 0)          */
-            uint32_t Q : 1;  /*!< bit:     27  Saturation condition flag          */
-            uint32_t V : 1;  /*!< bit:     28  Overflow condition code flag       */
-            uint32_t C : 1;  /*!< bit:     29  Carry condition code flag          */
-            uint32_t Z : 1;  /*!< bit:     30  Zero condition code flag           */
-            uint32_t N : 1;  /*!< bit:     31  Negative condition code flag       */
-        } b;                 /*!< Structure used for bit  access                  */
-        uint32_t w;          /*!< Type      used for word access                  */
-    } xPSR_Type;
-
-    /** \brief  Union type to access the Control Registers (CONTROL).
- */
-    typedef union
-    {
-        struct
-        {
-            uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
-            uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used                   */
-            uint32_t FPCA : 1;        /*!< bit:      2  FP extension active flag           */
-            uint32_t _reserved0 : 29; /*!< bit:  3..31  Reserved                           */
-        } b;                          /*!< Structure used for bit  access                  */
-        uint32_t w;                   /*!< Type      used for word access                  */
-    } CONTROL_Type;
-
-    /*@} end of group CMSIS_CORE */
-
-    /** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-    /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-    typedef struct
-    {
-        __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-        uint32_t RESERVED0[31];
-        __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-        uint32_t RSERVED1[31];
-        __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-        uint32_t RESERVED2[31];
-        __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-        uint32_t RESERVED3[31];
-        uint32_t RESERVED4[64];
-        __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-    } NVIC_Type;
-
-    /*@} end of group CMSIS_NVIC */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-    /** \brief  Structure type to access the System Control Block (SCB).
- */
-    typedef struct
-    {
-        __I uint32_t CPUID; /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-        __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-        uint32_t RESERVED0;
-        __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-        __IO uint32_t SCR;   /*!< Offset: 0x010 (R/W)  System Control Register                               */
-        __IO uint32_t CCR;   /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-        uint32_t RESERVED1;
-        __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-        __IO uint32_t SHCSR;  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-    } SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24                                    /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20                               /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16                                    /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4                                 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0                                 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31                               /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28                              /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27                              /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26                              /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25                              /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23                               /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22                               /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12                                    /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0                                    /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16                                  /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16                                      /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15                               /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2                                  /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1                                    /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4                              /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2                              /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1                                /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3                                /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15                                  /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-    /*@} end of group CMSIS_SCB */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-    /** \brief  Structure type to access the System Timer (SysTick).
- */
-    typedef struct
-    {
-        __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-        __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-        __IO uint32_t VAL;  /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-        __I uint32_t CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-    } SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16                                  /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2                                   /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1                                 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0                                /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0                                       /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0                                       /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31                               /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30                              /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0                                       /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE (0xE000E000UL)            /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address              */
-#define NVIC_BASE (SCS_BASE + 0x0100UL)    /*!< NVIC Base Address                 */
-#define SCB_BASE (SCS_BASE + 0x0D00UL)     /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *)SCB_BASE)             /*!< SCB configuration struct           */
-#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct       */
-#define NVIC ((NVIC_Type *)NVIC_BASE)          /*!< NVIC configuration struct          */
-
-/*@} */
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ((((uint32_t)(IRQn)) & 0x03) * 8)
-#define _SHP_IDX(IRQn) (((((uint32_t)(IRQn)&0x0F) - 8) >> 2))
-#define _IP_IDX(IRQn) (((uint32_t)(IRQn) >> 2))
-
-    /** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ISER[0] = (1 << ((uint32_t)(IRQn)&0x1F));
-    }
-
-    /** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ICER[0] = (1 << ((uint32_t)(IRQn)&0x1F));
-    }
-
-    /** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-    __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-    {
-        return ((uint32_t)((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0));
-    }
-
-    /** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn)&0x1F));
-    }
-
-    /** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */
-    }
-
-    /** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-    __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-    {
-        if (IRQn < 0)
-        {
-            SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-                                       (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
-        }
-        else
-        {
-            NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-                                      (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
-        }
-    }
-
-    /** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-    __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-    {
-
-        if (IRQn < 0)
-        {
-            return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
-        } /* get priority for Cortex-M0 system interrupts */
-        else
-        {
-            return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
-        } /* get priority for device specific interrupts  */
-    }
-
-    /** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-    __STATIC_INLINE void NVIC_SystemReset(void)
-    {
-        __DSB(); /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-        SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                      SCB_AIRCR_SYSRESETREQ_Msk);
-        __DSB(); /* Ensure completion of memory access */
-        while (1)
-            ; /* wait until reset */
-    }
-
-    /*@} end of CMSIS_Core_NVICFunctions */
-
-    /* ##################################    SysTick function  ############################################ */
-    /** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-    /** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-    __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-    {
-        if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)
-            return (1); /* Reload value impossible */
-
-        SysTick->LOAD = ticks - 1;                                   /* set reload register */
-        NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
-        SysTick->VAL = 0;                                            /* Load the SysTick Counter Value */
-        SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                        SysTick_CTRL_TICKINT_Msk |
-                        SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
-        return (0);                              /* Function successful */
-    }
-
-#endif
-
-    /*@} end of CMSIS_Core_SysTickFunctions */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

bsp/swm320/libraries/CMSIS/CoreSupport/core_cm0plus.h

@@ -1,804 +0,0 @@
-/**************************************************************************/ /**
- * @file     core_cm0plus.h
- * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version  V4.00
- * @date     22. August 2014
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-#if defined(__ICCARM__)
-#pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex-M0+
-  @{
- */
-
-/*  CMSIS CM0P definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version   */
-#define __CM0PLUS_CMSIS_VERSION_SUB (0x00)  /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
-                                 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M (0x00) /*!< Cortex-M Core                    */
-
-#if defined(__CC_ARM)
-#define __ASM __asm       /*!< asm keyword for ARM Compiler          */
-#define __INLINE __inline /*!< inline keyword for ARM Compiler       */
-#define __STATIC_INLINE static __inline
-
-#elif defined(__GNUC__)
-#define __ASM __asm     /*!< asm keyword for GNU Compiler          */
-#define __INLINE inline /*!< inline keyword for GNU Compiler       */
-#define __STATIC_INLINE static inline
-
-#elif defined(__ICCARM__)
-#define __ASM __asm     /*!< asm keyword for IAR Compiler          */
-#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-#define __STATIC_INLINE static inline
-
-#elif defined(__TMS470__)
-#define __ASM __asm /*!< asm keyword for TI CCS Compiler       */
-#define __STATIC_INLINE static inline
-
-#elif defined(__TASKING__)
-#define __ASM __asm     /*!< asm keyword for TASKING Compiler      */
-#define __INLINE inline /*!< inline keyword for TASKING Compiler   */
-#define __STATIC_INLINE static inline
-
-#elif defined(__CSMC__)
-#define __packed
-#define __ASM _asm      /*!< asm keyword for COSMIC Compiler      */
-#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-#define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED 0
-
-#if defined(__CC_ARM)
-#if defined __TARGET_FPU_VFP
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined(__GNUC__)
-#if defined(__VFP_FP__) && !defined(__SOFTFP__)
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined(__ICCARM__)
-#if defined __ARMVFP__
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined(__TMS470__)
-#if defined __TI__VFP_SUPPORT____
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined(__TASKING__)
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined(__CSMC__) /* Cosmic */
-#if (__CSMC__ & 0x400)  // FPU present for parser
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-#endif
-
-#include <stdint.h>       /* standard types definitions                      */
-#include <core_cmInstr.h> /* Core Instruction Access                         */
-#include <core_cmFunc.h>  /* Core Function Access                            */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM0PLUS_REV
-#define __CM0PLUS_REV 0x0000
-#warning "__CM0PLUS_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT 0
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __VTOR_PRESENT
-#define __VTOR_PRESENT 0
-#warning "__VTOR_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS 2
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig 0
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define __I volatile /*!< Defines 'read only' permissions                 */
-#else
-#define __I volatile const /*!< Defines 'read only' permissions                 */
-#endif
-#define __O volatile  /*!< Defines 'write only' permissions                */
-#define __IO volatile /*!< Defines 'read / write' permissions              */
-
-    /*@} end of group Cortex-M0+ */
-
-    /*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-    /** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-    /** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-    /** \brief  Union type to access the Application Program Status Register (APSR).
- */
-    typedef union
-    {
-        struct
-        {
-#if (__CORTEX_M != 0x04)
-            uint32_t _reserved0 : 27; /*!< bit:  0..26  Reserved                           */
-#else
-        uint32_t _reserved0 : 16; /*!< bit:  0..15  Reserved                           */
-        uint32_t GE : 4;          /*!< bit: 16..19  Greater than or Equal flags        */
-        uint32_t _reserved1 : 7;  /*!< bit: 20..26  Reserved                           */
-#endif
-            uint32_t Q : 1; /*!< bit:     27  Saturation condition flag          */
-            uint32_t V : 1; /*!< bit:     28  Overflow condition code flag       */
-            uint32_t C : 1; /*!< bit:     29  Carry condition code flag          */
-            uint32_t Z : 1; /*!< bit:     30  Zero condition code flag           */
-            uint32_t N : 1; /*!< bit:     31  Negative condition code flag       */
-        } b;                /*!< Structure used for bit  access                  */
-        uint32_t w;         /*!< Type      used for word access                  */
-    } APSR_Type;
-
-    /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-    typedef union
-    {
-        struct
-        {
-            uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number                   */
-            uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved                           */
-        } b;                          /*!< Structure used for bit  access                  */
-        uint32_t w;                   /*!< Type      used for word access                  */
-    } IPSR_Type;
-
-    /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-    typedef union
-    {
-        struct
-        {
-            uint32_t ISR : 9; /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-            uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved                           */
-#else
-        uint32_t _reserved0 : 7;  /*!< bit:  9..15  Reserved                           */
-        uint32_t GE : 4;          /*!< bit: 16..19  Greater than or Equal flags        */
-        uint32_t _reserved1 : 4;  /*!< bit: 20..23  Reserved                           */
-#endif
-            uint32_t T : 1;  /*!< bit:     24  Thumb bit        (read 0)          */
-            uint32_t IT : 2; /*!< bit: 25..26  saved IT state   (read 0)          */
-            uint32_t Q : 1;  /*!< bit:     27  Saturation condition flag          */
-            uint32_t V : 1;  /*!< bit:     28  Overflow condition code flag       */
-            uint32_t C : 1;  /*!< bit:     29  Carry condition code flag          */
-            uint32_t Z : 1;  /*!< bit:     30  Zero condition code flag           */
-            uint32_t N : 1;  /*!< bit:     31  Negative condition code flag       */
-        } b;                 /*!< Structure used for bit  access                  */
-        uint32_t w;          /*!< Type      used for word access                  */
-    } xPSR_Type;
-
-    /** \brief  Union type to access the Control Registers (CONTROL).
- */
-    typedef union
-    {
-        struct
-        {
-            uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
-            uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used                   */
-            uint32_t FPCA : 1;        /*!< bit:      2  FP extension active flag           */
-            uint32_t _reserved0 : 29; /*!< bit:  3..31  Reserved                           */
-        } b;                          /*!< Structure used for bit  access                  */
-        uint32_t w;                   /*!< Type      used for word access                  */
-    } CONTROL_Type;
-
-    /*@} end of group CMSIS_CORE */
-
-    /** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-    /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-    typedef struct
-    {
-        __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-        uint32_t RESERVED0[31];
-        __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-        uint32_t RSERVED1[31];
-        __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-        uint32_t RESERVED2[31];
-        __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-        uint32_t RESERVED3[31];
-        uint32_t RESERVED4[64];
-        __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-    } NVIC_Type;
-
-    /*@} end of group CMSIS_NVIC */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-    /** \brief  Structure type to access the System Control Block (SCB).
- */
-    typedef struct
-    {
-        __I uint32_t CPUID; /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-        __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-#if (__VTOR_PRESENT == 1)
-        __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-#else
-    uint32_t RESERVED0;
-#endif
-        __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-        __IO uint32_t SCR;   /*!< Offset: 0x010 (R/W)  System Control Register                               */
-        __IO uint32_t CCR;   /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-        uint32_t RESERVED1;
-        __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-        __IO uint32_t SHCSR;  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-    } SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24                                    /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20                               /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16                                    /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4                                 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0                                 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31                               /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28                              /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27                              /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26                              /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25                              /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23                               /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22                               /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12                                    /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0                                    /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if (__VTOR_PRESENT == 1)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 8                                   /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16                                  /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16                                      /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15                               /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2                                  /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1                                    /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4                              /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2                              /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1                                /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3                                /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15                                  /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-    /*@} end of group CMSIS_SCB */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-    /** \brief  Structure type to access the System Timer (SysTick).
- */
-    typedef struct
-    {
-        __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-        __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-        __IO uint32_t VAL;  /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-        __I uint32_t CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-    } SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16                                  /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2                                   /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1                                 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0                                /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0                                       /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0                                       /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31                               /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30                              /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0                                       /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-    /*@} end of group CMSIS_SysTick */
-
-#if (__MPU_PRESENT == 1)
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-    /** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-    typedef struct
-    {
-        __I uint32_t TYPE;  /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-        __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-        __IO uint32_t RNR;  /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-        __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-        __IO uint32_t RASR; /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-    } MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16                               /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8                                /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0                              /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2                                /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1                              /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0                              /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 8                                 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4                           /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0                              /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16                               /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28                       /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24                         /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19                          /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18                      /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17                      /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16                      /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M0+ Hardware */
-#define SCS_BASE (0xE000E000UL)            /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address              */
-#define NVIC_BASE (SCS_BASE + 0x0100UL)    /*!< NVIC Base Address                 */
-#define SCB_BASE (SCS_BASE + 0x0D00UL)     /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *)SCB_BASE)             /*!< SCB configuration struct           */
-#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct       */
-#define NVIC ((NVIC_Type *)NVIC_BASE)          /*!< NVIC configuration struct          */
-
-#if (__MPU_PRESENT == 1)
-#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit             */
-#define MPU ((MPU_Type *)MPU_BASE)     /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ((((uint32_t)(IRQn)) & 0x03) * 8)
-#define _SHP_IDX(IRQn) (((((uint32_t)(IRQn)&0x0F) - 8) >> 2))
-#define _IP_IDX(IRQn) (((uint32_t)(IRQn) >> 2))
-
-    /** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ISER[0] = (1 << ((uint32_t)(IRQn)&0x1F));
-    }
-
-    /** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ICER[0] = (1 << ((uint32_t)(IRQn)&0x1F));
-    }
-
-    /** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-    __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-    {
-        return ((uint32_t)((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0));
-    }
-
-    /** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn)&0x1F));
-    }
-
-    /** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */
-    }
-
-    /** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-    __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-    {
-        if (IRQn < 0)
-        {
-            SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-                                       (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
-        }
-        else
-        {
-            NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-                                      (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
-        }
-    }
-
-    /** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-    __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-    {
-
-        if (IRQn < 0)
-        {
-            return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
-        } /* get priority for Cortex-M0 system interrupts */
-        else
-        {
-            return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
-        } /* get priority for device specific interrupts  */
-    }
-
-    /** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-    __STATIC_INLINE void NVIC_SystemReset(void)
-    {
-        __DSB(); /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-        SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                      SCB_AIRCR_SYSRESETREQ_Msk);
-        __DSB(); /* Ensure completion of memory access */
-        while (1)
-            ; /* wait until reset */
-    }
-
-    /*@} end of CMSIS_Core_NVICFunctions */
-
-    /* ##################################    SysTick function  ############################################ */
-    /** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-    /** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-    __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-    {
-        if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)
-            return (1); /* Reload value impossible */
-
-        SysTick->LOAD = ticks - 1;                                   /* set reload register */
-        NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
-        SysTick->VAL = 0;                                            /* Load the SysTick Counter Value */
-        SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                        SysTick_CTRL_TICKINT_Msk |
-                        SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
-        return (0);                              /* Function successful */
-    }
-
-#endif
-
-    /*@} end of CMSIS_Core_SysTickFunctions */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

bsp/swm320/libraries/CMSIS/CoreSupport/core_cm3.h

@@ -1,1624 +0,0 @@
-/**************************************************************************/ /**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V4.00
- * @date     22. August 2014
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-#if defined(__ICCARM__)
-#pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M3
-  @{
- */
-
-/*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version   */
-#define __CM3_CMSIS_VERSION_SUB (0x00)  /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
-                             __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M (0x03) /*!< Cortex-M Core                    */
-
-#if defined(__CC_ARM)
-#define __ASM __asm       /*!< asm keyword for ARM Compiler          */
-#define __INLINE __inline /*!< inline keyword for ARM Compiler       */
-#define __STATIC_INLINE static __inline
-
-#elif defined(__GNUC__)
-#define __ASM __asm     /*!< asm keyword for GNU Compiler          */
-#define __INLINE inline /*!< inline keyword for GNU Compiler       */
-#define __STATIC_INLINE static inline
-
-#elif defined(__ICCARM__)
-#define __ASM __asm     /*!< asm keyword for IAR Compiler          */
-#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-#define __STATIC_INLINE static inline
-
-#elif defined(__TMS470__)
-#define __ASM __asm /*!< asm keyword for TI CCS Compiler       */
-#define __STATIC_INLINE static inline
-
-#elif defined(__TASKING__)
-#define __ASM __asm     /*!< asm keyword for TASKING Compiler      */
-#define __INLINE inline /*!< inline keyword for TASKING Compiler   */
-#define __STATIC_INLINE static inline
-
-#elif defined(__CSMC__)
-#define __packed
-#define __ASM _asm      /*!< asm keyword for COSMIC Compiler      */
-#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-#define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED 0
-
-#if defined(__CC_ARM)
-#if defined __TARGET_FPU_VFP
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined(__GNUC__)
-#if defined(__VFP_FP__) && !defined(__SOFTFP__)
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined(__ICCARM__)
-#if defined __ARMVFP__
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined(__TMS470__)
-#if defined __TI__VFP_SUPPORT____
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined(__TASKING__)
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined(__CSMC__) /* Cosmic */
-#if (__CSMC__ & 0x400)  // FPU present for parser
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-#endif
-
-#include <stdint.h>       /* standard types definitions                      */
-#include <core_cmInstr.h> /* Core Instruction Access                         */
-#include <core_cmFunc.h>  /* Core Function Access                            */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM3_REV
-#define __CM3_REV 0x0200
-#warning "__CM3_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT 0
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS 4
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig 0
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define __I volatile /*!< Defines 'read only' permissions                 */
-#else
-#define __I volatile const /*!< Defines 'read only' permissions                 */
-#endif
-#define __O volatile  /*!< Defines 'write only' permissions                */
-#define __IO volatile /*!< Defines 'read / write' permissions              */
-
-    /*@} end of group Cortex_M3 */
-
-    /*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-    /** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-    /** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-    /** \brief  Union type to access the Application Program Status Register (APSR).
- */
-    typedef union
-    {
-        struct
-        {
-#if (__CORTEX_M != 0x04)
-            uint32_t _reserved0 : 27; /*!< bit:  0..26  Reserved                           */
-#else
-        uint32_t _reserved0 : 16; /*!< bit:  0..15  Reserved                           */
-        uint32_t GE : 4;          /*!< bit: 16..19  Greater than or Equal flags        */
-        uint32_t _reserved1 : 7;  /*!< bit: 20..26  Reserved                           */
-#endif
-            uint32_t Q : 1; /*!< bit:     27  Saturation condition flag          */
-            uint32_t V : 1; /*!< bit:     28  Overflow condition code flag       */
-            uint32_t C : 1; /*!< bit:     29  Carry condition code flag          */
-            uint32_t Z : 1; /*!< bit:     30  Zero condition code flag           */
-            uint32_t N : 1; /*!< bit:     31  Negative condition code flag       */
-        } b;                /*!< Structure used for bit  access                  */
-        uint32_t w;         /*!< Type      used for word access                  */
-    } APSR_Type;
-
-    /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-    typedef union
-    {
-        struct
-        {
-            uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number                   */
-            uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved                           */
-        } b;                          /*!< Structure used for bit  access                  */
-        uint32_t w;                   /*!< Type      used for word access                  */
-    } IPSR_Type;
-
-    /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-    typedef union
-    {
-        struct
-        {
-            uint32_t ISR : 9; /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-            uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved                           */
-#else
-        uint32_t _reserved0 : 7;  /*!< bit:  9..15  Reserved                           */
-        uint32_t GE : 4;          /*!< bit: 16..19  Greater than or Equal flags        */
-        uint32_t _reserved1 : 4;  /*!< bit: 20..23  Reserved                           */
-#endif
-            uint32_t T : 1;  /*!< bit:     24  Thumb bit        (read 0)          */
-            uint32_t IT : 2; /*!< bit: 25..26  saved IT state   (read 0)          */
-            uint32_t Q : 1;  /*!< bit:     27  Saturation condition flag          */
-            uint32_t V : 1;  /*!< bit:     28  Overflow condition code flag       */
-            uint32_t C : 1;  /*!< bit:     29  Carry condition code flag          */
-            uint32_t Z : 1;  /*!< bit:     30  Zero condition code flag           */
-            uint32_t N : 1;  /*!< bit:     31  Negative condition code flag       */
-        } b;                 /*!< Structure used for bit  access                  */
-        uint32_t w;          /*!< Type      used for word access                  */
-    } xPSR_Type;
-
-    /** \brief  Union type to access the Control Registers (CONTROL).
- */
-    typedef union
-    {
-        struct
-        {
-            uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
-            uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used                   */
-            uint32_t FPCA : 1;        /*!< bit:      2  FP extension active flag           */
-            uint32_t _reserved0 : 29; /*!< bit:  3..31  Reserved                           */
-        } b;                          /*!< Structure used for bit  access                  */
-        uint32_t w;                   /*!< Type      used for word access                  */
-    } CONTROL_Type;
-
-    /*@} end of group CMSIS_CORE */
-
-    /** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-    /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-    typedef struct
-    {
-        __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-        uint32_t RESERVED0[24];
-        __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-        uint32_t RSERVED1[24];
-        __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-        uint32_t RESERVED2[24];
-        __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-        uint32_t RESERVED3[24];
-        __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-        uint32_t RESERVED4[56];
-        __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED5[644];
-        __O uint32_t STIR; /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-    } NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0                                /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
-
-    /*@} end of group CMSIS_NVIC */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-    /** \brief  Structure type to access the System Control Block (SCB).
- */
-    typedef struct
-    {
-        __I uint32_t CPUID;   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-        __IO uint32_t ICSR;   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-        __IO uint32_t VTOR;   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-        __IO uint32_t AIRCR;  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-        __IO uint32_t SCR;    /*!< Offset: 0x010 (R/W)  System Control Register                               */
-        __IO uint32_t CCR;    /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-        __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-        __IO uint32_t SHCSR;  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-        __IO uint32_t CFSR;   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-        __IO uint32_t HFSR;   /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-        __IO uint32_t DFSR;   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-        __IO uint32_t MMFAR;  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-        __IO uint32_t BFAR;   /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-        __IO uint32_t AFSR;   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-        __I uint32_t PFR[2];  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-        __I uint32_t DFR;     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-        __I uint32_t ADR;     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-        __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-        __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-        uint32_t RESERVED0[5];
-        __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-    } SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24                                    /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20                               /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16                                    /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4                                 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0                                 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31                               /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28                              /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27                              /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26                              /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25                              /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23                               /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22                               /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12                                    /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11                              /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0                                    /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if (__CM3_REV < 0x0201)                                   /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos 29                            /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos 7                                   /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos 7                                    /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16                                  /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16                                      /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15                               /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8                               /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2                                  /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1                                    /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0                                /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4                              /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2                              /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1                                /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8                              /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4                              /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3                                /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1                                 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0                                   /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18                                 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17                                 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16                                 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15                                  /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14                                    /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13                                    /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12                                    /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11                                /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10                               /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8                                 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7                                /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3                                  /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1                                  /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0                                  /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16                                    /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8                                   /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0                                   /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30                           /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4                              /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1                          /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-
-    /*@} end of group CMSIS_SCB */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-    /** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-    typedef struct
-    {
-        uint32_t RESERVED0[1];
-        __I uint32_t ICTR; /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-        __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
-#else
-    uint32_t RESERVED1[1];
-#endif
-    } SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0                                      /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
-
-    /* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2                                 /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1                                    /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0                                    /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
-
-    /*@} end of group CMSIS_SCnotSCB */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-    /** \brief  Structure type to access the System Timer (SysTick).
- */
-    typedef struct
-    {
-        __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-        __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-        __IO uint32_t VAL;  /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-        __I uint32_t CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-    } SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16                                  /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2                                   /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1                                 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0                                /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0                                       /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0                                       /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31                               /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30                              /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0                                       /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-    /*@} end of group CMSIS_SysTick */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-    /** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-    typedef struct
-    {
-        __O union
-        {
-            __O uint8_t u8;   /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-            __O uint16_t u16; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-            __O uint32_t u32; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-        } PORT[32];           /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-        uint32_t RESERVED0[864];
-        __IO uint32_t TER; /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-        uint32_t RESERVED1[15];
-        __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-        uint32_t RESERVED2[15];
-        __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-        uint32_t RESERVED3[29];
-        __O uint32_t IWR;   /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-        __I uint32_t IRR;   /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-        __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-        uint32_t RESERVED4[43];
-        __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-        __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-        uint32_t RESERVED5[6];
-        __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-        __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-        __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-        __I uint32_t PID7; /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-        __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-        __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-        __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-        __I uint32_t PID3; /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-        __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-        __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-        __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-        __I uint32_t CID3; /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-    } ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0                               /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23                        /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16                                 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10                           /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8                               /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4                           /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3                           /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1                          /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0                           /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0                                 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1                           /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-
-    /*@}*/ /* end of group CMSIS_ITM */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-    /** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-    typedef struct
-    {
-        __IO uint32_t CTRL;      /*!< Offset: 0x000 (R/W)  Control Register                          */
-        __IO uint32_t CYCCNT;    /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-        __IO uint32_t CPICNT;    /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-        __IO uint32_t EXCCNT;    /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-        __IO uint32_t SLEEPCNT;  /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-        __IO uint32_t LSUCNT;    /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-        __IO uint32_t FOLDCNT;   /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-        __I uint32_t PCSR;       /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-        __IO uint32_t COMP0;     /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-        __IO uint32_t MASK0;     /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-        __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-        uint32_t RESERVED0[1];
-        __IO uint32_t COMP1;     /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-        __IO uint32_t MASK1;     /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-        __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-        uint32_t RESERVED1[1];
-        __IO uint32_t COMP2;     /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-        __IO uint32_t MASK2;     /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-        __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-        uint32_t RESERVED2[1];
-        __IO uint32_t COMP3;     /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-        __IO uint32_t MASK3;     /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-        __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-    } DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28                              /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27                               /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26                                /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25                               /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24                               /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22                                /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21                                 /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20                                /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19                                  /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18                                /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17                                /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16                                /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12                                 /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10                              /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9                              /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5                                /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1                                  /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0                                 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0                                 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0                                 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0                                     /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0                                 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0                                   /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0                             /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24                                  /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16                                     /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12                                     /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10                                    /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9                                   /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8                                      /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7                                    /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5                                     /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0                                    /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
-
-    /*@}*/ /* end of group CMSIS_DWT */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-    /** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-    typedef struct
-    {
-        __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-        __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2];
-        __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55];
-        __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131];
-        __I uint32_t FFSR;  /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-        __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-        __I uint32_t FSCR;  /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759];
-        __I uint32_t TRIGGER;   /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-        __I uint32_t FIFO0;     /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-        __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1];
-        __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-        __I uint32_t FIFO1;     /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-        __IO uint32_t ITCTRL;   /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39];
-        __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-        __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8];
-        __I uint32_t DEVID;   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-        __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-    } TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0                                    /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0                              /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3                                 /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2                                 /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1                                 /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0                                /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8                              /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1                               /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0                                  /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29                                   /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27                                     /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26                                   /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24                                     /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16                             /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8                              /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0                              /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0                                    /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29                                   /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27                                     /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26                                   /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24                                     /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16                             /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8                              /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0                              /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0                                    /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0                              /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11                                /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10                                 /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9                                  /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6                                 /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5                                  /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0                                      /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 0                                  /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 4                                    /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-    /*@}*/ /* end of group CMSIS_TPI */
-
-#if (__MPU_PRESENT == 1)
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-    /** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-    typedef struct
-    {
-        __I uint32_t TYPE;     /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-        __IO uint32_t CTRL;    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-        __IO uint32_t RNR;     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-        __IO uint32_t RBAR;    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-        __IO uint32_t RASR;    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-        __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-        __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-        __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-        __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-        __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-        __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-    } MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16                               /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8                                /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0                              /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2                                /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1                              /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0                              /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5                                  /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4                           /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0                              /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16                               /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28                       /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24                         /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19                          /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18                      /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17                      /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16                      /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-    /** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-    typedef struct
-    {
-        __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-        __O uint32_t DCRSR;  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-        __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-        __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-    } CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16                                       /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25                                      /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24                                       /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19                                    /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18                                   /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17                                  /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16                                    /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5                                        /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3                                       /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2                                   /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1                                   /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0                                      /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16                                  /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0                                      /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24                                  /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19                                   /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18                                    /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17                                    /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16                                  /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10                                      /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9                                      /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8                                      /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7                                       /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6                                      /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5                                       /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4                                     /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0                                         /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000UL)            /*!< System Control Space Base Address  */
-#define ITM_BASE (0xE0000000UL)            /*!< ITM Base Address                   */
-#define DWT_BASE (0xE0001000UL)            /*!< DWT Base Address                   */
-#define TPI_BASE (0xE0040000UL)            /*!< TPI Base Address                   */
-#define CoreDebug_BASE (0xE000EDF0UL)      /*!< Core Debug Base Address            */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address               */
-#define NVIC_BASE (SCS_BASE + 0x0100UL)    /*!< NVIC Base Address                  */
-#define SCB_BASE (SCS_BASE + 0x0D00UL)     /*!< System Control Block Base Address  */
-
-#define SCnSCB ((SCnSCB_Type *)SCS_BASE)             /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *)SCB_BASE)                   /*!< SCB configuration struct           */
-#define SysTick ((SysTick_Type *)SysTick_BASE)       /*!< SysTick configuration struct       */
-#define NVIC ((NVIC_Type *)NVIC_BASE)                /*!< NVIC configuration struct          */
-#define ITM ((ITM_Type *)ITM_BASE)                   /*!< ITM configuration struct           */
-#define DWT ((DWT_Type *)DWT_BASE)                   /*!< DWT configuration struct           */
-#define TPI ((TPI_Type *)TPI_BASE)                   /*!< TPI configuration struct           */
-#define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit             */
-#define MPU ((MPU_Type *)MPU_BASE)     /*!< Memory Protection Unit             */
-#endif
-
-    /*@} */
-
-    /*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-    /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-    /* ##########################   NVIC functions  #################################### */
-    /** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-    /** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-    __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-    {
-        uint32_t reg_value;
-        uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used          */
-
-        reg_value = SCB->AIRCR;                                         /* read old register configuration    */
-        reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change               */
-        reg_value = (reg_value |
-                     ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                     (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
-        SCB->AIRCR = reg_value;
-    }
-
-    /** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-    __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-    {
-        return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
-    }
-
-    /** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* enable interrupt */
-    }
-
-    /** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* disable interrupt */
-    }
-
-    /** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-    __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-    {
-        return ((uint32_t)((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */
-    }
-
-    /** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* set interrupt pending */
-    }
-
-    /** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */
-    }
-
-    /** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-    __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-    {
-        return ((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */
-    }
-
-    /** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-    __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-    {
-        if (IRQn < 0)
-        {
-            SCB->SHP[((uint32_t)(IRQn)&0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
-        } /* set Priority for Cortex-M  System Interrupts */
-        else
-        {
-            NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
-        } /* set Priority for device specific Interrupts  */
-    }
-
-    /** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-    __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-    {
-
-        if (IRQn < 0)
-        {
-            return ((uint32_t)(SCB->SHP[((uint32_t)(IRQn)&0xF) - 4] >> (8 - __NVIC_PRIO_BITS)));
-        } /* get priority for Cortex-M  system interrupts */
-        else
-        {
-            return ((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS)));
-        } /* get priority for device specific interrupts  */
-    }
-
-    /** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-    __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-    {
-        uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used          */
-        uint32_t PreemptPriorityBits;
-        uint32_t SubPriorityBits;
-
-        PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-        SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-        return (
-            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-            ((SubPriority & ((1 << (SubPriorityBits)) - 1))));
-    }
-
-    /** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-    __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
-    {
-        uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used          */
-        uint32_t PreemptPriorityBits;
-        uint32_t SubPriorityBits;
-
-        PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-        SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-        *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-        *pSubPriority = (Priority) & ((1 << (SubPriorityBits)) - 1);
-    }
-
-    /** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-    __STATIC_INLINE void NVIC_SystemReset(void)
-    {
-        __DSB(); /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-        SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                      (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                      SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
-        __DSB();                                  /* Ensure completion of memory access */
-        while (1)
-            ; /* wait until reset */
-    }
-
-    /*@} end of CMSIS_Core_NVICFunctions */
-
-    /* ##################################    SysTick function  ############################################ */
-    /** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-    /** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-    __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-    {
-        if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)
-            return (1); /* Reload value impossible */
-
-        SysTick->LOAD = ticks - 1;                                   /* set reload register */
-        NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
-        SysTick->VAL = 0;                                            /* Load the SysTick Counter Value */
-        SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                        SysTick_CTRL_TICKINT_Msk |
-                        SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
-        return (0);                              /* Function successful */
-    }
-
-#endif
-
-    /*@} end of CMSIS_Core_SysTickFunctions */
-
-    /* ##################################### Debug In/Output function ########################################### */
-    /** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-    extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters.                         */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5     /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-    /** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-    __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
-    {
-        if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
-            (ITM->TER & (1UL << 0)))           /* ITM Port #0 enabled */
-        {
-            while (ITM->PORT[0].u32 == 0)
-                ;
-            ITM->PORT[0].u8 = (uint8_t)ch;
-        }
-        return (ch);
-    }
-
-    /** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-    __STATIC_INLINE int32_t ITM_ReceiveChar(void)
-    {
-        int32_t ch = -1; /* no character available */
-
-        if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-        {
-            ch = ITM_RxBuffer;
-            ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
-        }
-
-        return (ch);
-    }
-
-    /** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-    __STATIC_INLINE int32_t ITM_CheckChar(void)
-    {
-
-        if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-        {
-            return (0); /* no character available */
-        }
-        else
-        {
-            return (1); /*    character available */
-        }
-    }
-
-    /*@} end of CMSIS_core_DebugFunctions */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

bsp/swm320/libraries/CMSIS/CoreSupport/core_cm4.h

@@ -1,1775 +0,0 @@
-/**************************************************************************/ /**
- * @file     core_cm4.h
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V4.00
- * @date     22. August 2014
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-#if defined(__ICCARM__)
-#pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M4
-  @{
- */
-
-/*  CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version   */
-#define __CM4_CMSIS_VERSION_SUB (0x00)  /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
-                             __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M (0x04) /*!< Cortex-M Core                    */
-
-#if defined(__CC_ARM)
-#define __ASM __asm       /*!< asm keyword for ARM Compiler          */
-#define __INLINE __inline /*!< inline keyword for ARM Compiler       */
-#define __STATIC_INLINE static __inline
-
-#elif defined(__GNUC__)
-#define __ASM __asm     /*!< asm keyword for GNU Compiler          */
-#define __INLINE inline /*!< inline keyword for GNU Compiler       */
-#define __STATIC_INLINE static inline
-
-#elif defined(__ICCARM__)
-#define __ASM __asm     /*!< asm keyword for IAR Compiler          */
-#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-#define __STATIC_INLINE static inline
-
-#elif defined(__TMS470__)
-#define __ASM __asm /*!< asm keyword for TI CCS Compiler       */
-#define __STATIC_INLINE static inline
-
-#elif defined(__TASKING__)
-#define __ASM __asm     /*!< asm keyword for TASKING Compiler      */
-#define __INLINE inline /*!< inline keyword for TASKING Compiler   */
-#define __STATIC_INLINE static inline
-
-#elif defined(__CSMC__)
-#define __packed
-#define __ASM _asm      /*!< asm keyword for COSMIC Compiler      */
-#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-#define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined(__CC_ARM)
-#if defined __TARGET_FPU_VFP
-#if (__FPU_PRESENT == 1)
-#define __FPU_USED 1
-#else
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED 0
-#endif
-#else
-#define __FPU_USED 0
-#endif
-
-#elif defined(__GNUC__)
-#if defined(__VFP_FP__) && !defined(__SOFTFP__)
-#if (__FPU_PRESENT == 1)
-#define __FPU_USED 1
-#else
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED 0
-#endif
-#else
-#define __FPU_USED 0
-#endif
-
-#elif defined(__ICCARM__)
-#if defined __ARMVFP__
-#if (__FPU_PRESENT == 1)
-#define __FPU_USED 1
-#else
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED 0
-#endif
-#else
-#define __FPU_USED 0
-#endif
-
-#elif defined(__TMS470__)
-#if defined __TI_VFP_SUPPORT__
-#if (__FPU_PRESENT == 1)
-#define __FPU_USED 1
-#else
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED 0
-#endif
-#else
-#define __FPU_USED 0
-#endif
-
-#elif defined(__TASKING__)
-#if defined __FPU_VFP__
-#if (__FPU_PRESENT == 1)
-#define __FPU_USED 1
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED 0
-#endif
-#else
-#define __FPU_USED 0
-#endif
-
-#elif defined(__CSMC__) /* Cosmic */
-#if (__CSMC__ & 0x400)  // FPU present for parser
-#if (__FPU_PRESENT == 1)
-#define __FPU_USED 1
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED 0
-#endif
-#else
-#define __FPU_USED 0
-#endif
-#endif
-
-#include <stdint.h>       /* standard types definitions                      */
-#include <core_cmInstr.h> /* Core Instruction Access                         */
-#include <core_cmFunc.h>  /* Core Function Access                            */
-#include <core_cmSimd.h>  /* Compiler specific SIMD Intrinsics               */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM4_REV
-#define __CM4_REV 0x0000
-#warning "__CM4_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT 0
-#warning "__FPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT 0
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS 4
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig 0
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define __I volatile /*!< Defines 'read only' permissions                 */
-#else
-#define __I volatile const /*!< Defines 'read only' permissions                 */
-#endif
-#define __O volatile  /*!< Defines 'write only' permissions                */
-#define __IO volatile /*!< Defines 'read / write' permissions              */
-
-    /*@} end of group Cortex_M4 */
-
-    /*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-    /** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-    /** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-    /** \brief  Union type to access the Application Program Status Register (APSR).
- */
-    typedef union
-    {
-        struct
-        {
-#if (__CORTEX_M != 0x04)
-            uint32_t _reserved0 : 27; /*!< bit:  0..26  Reserved                           */
-#else
-        uint32_t _reserved0 : 16; /*!< bit:  0..15  Reserved                           */
-        uint32_t GE : 4;          /*!< bit: 16..19  Greater than or Equal flags        */
-        uint32_t _reserved1 : 7;  /*!< bit: 20..26  Reserved                           */
-#endif
-            uint32_t Q : 1; /*!< bit:     27  Saturation condition flag          */
-            uint32_t V : 1; /*!< bit:     28  Overflow condition code flag       */
-            uint32_t C : 1; /*!< bit:     29  Carry condition code flag          */
-            uint32_t Z : 1; /*!< bit:     30  Zero condition code flag           */
-            uint32_t N : 1; /*!< bit:     31  Negative condition code flag       */
-        } b;                /*!< Structure used for bit  access                  */
-        uint32_t w;         /*!< Type      used for word access                  */
-    } APSR_Type;
-
-    /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-    typedef union
-    {
-        struct
-        {
-            uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number                   */
-            uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved                           */
-        } b;                          /*!< Structure used for bit  access                  */
-        uint32_t w;                   /*!< Type      used for word access                  */
-    } IPSR_Type;
-
-    /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-    typedef union
-    {
-        struct
-        {
-            uint32_t ISR : 9; /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-            uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved                           */
-#else
-        uint32_t _reserved0 : 7;  /*!< bit:  9..15  Reserved                           */
-        uint32_t GE : 4;          /*!< bit: 16..19  Greater than or Equal flags        */
-        uint32_t _reserved1 : 4;  /*!< bit: 20..23  Reserved                           */
-#endif
-            uint32_t T : 1;  /*!< bit:     24  Thumb bit        (read 0)          */
-            uint32_t IT : 2; /*!< bit: 25..26  saved IT state   (read 0)          */
-            uint32_t Q : 1;  /*!< bit:     27  Saturation condition flag          */
-            uint32_t V : 1;  /*!< bit:     28  Overflow condition code flag       */
-            uint32_t C : 1;  /*!< bit:     29  Carry condition code flag          */
-            uint32_t Z : 1;  /*!< bit:     30  Zero condition code flag           */
-            uint32_t N : 1;  /*!< bit:     31  Negative condition code flag       */
-        } b;                 /*!< Structure used for bit  access                  */
-        uint32_t w;          /*!< Type      used for word access                  */
-    } xPSR_Type;
-
-    /** \brief  Union type to access the Control Registers (CONTROL).
- */
-    typedef union
-    {
-        struct
-        {
-            uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
-            uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used                   */
-            uint32_t FPCA : 1;        /*!< bit:      2  FP extension active flag           */
-            uint32_t _reserved0 : 29; /*!< bit:  3..31  Reserved                           */
-        } b;                          /*!< Structure used for bit  access                  */
-        uint32_t w;                   /*!< Type      used for word access                  */
-    } CONTROL_Type;
-
-    /*@} end of group CMSIS_CORE */
-
-    /** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-    /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-    typedef struct
-    {
-        __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-        uint32_t RESERVED0[24];
-        __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-        uint32_t RSERVED1[24];
-        __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-        uint32_t RESERVED2[24];
-        __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-        uint32_t RESERVED3[24];
-        __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-        uint32_t RESERVED4[56];
-        __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED5[644];
-        __O uint32_t STIR; /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-    } NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0                                /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
-
-    /*@} end of group CMSIS_NVIC */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-    /** \brief  Structure type to access the System Control Block (SCB).
- */
-    typedef struct
-    {
-        __I uint32_t CPUID;   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-        __IO uint32_t ICSR;   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-        __IO uint32_t VTOR;   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-        __IO uint32_t AIRCR;  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-        __IO uint32_t SCR;    /*!< Offset: 0x010 (R/W)  System Control Register                               */
-        __IO uint32_t CCR;    /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-        __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-        __IO uint32_t SHCSR;  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-        __IO uint32_t CFSR;   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-        __IO uint32_t HFSR;   /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-        __IO uint32_t DFSR;   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-        __IO uint32_t MMFAR;  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-        __IO uint32_t BFAR;   /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-        __IO uint32_t AFSR;   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-        __I uint32_t PFR[2];  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-        __I uint32_t DFR;     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-        __I uint32_t ADR;     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-        __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-        __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-        uint32_t RESERVED0[5];
-        __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-    } SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24                                    /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20                               /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16                                    /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4                                 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0                                 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31                               /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28                              /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27                              /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26                              /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25                              /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23                               /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22                               /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12                                    /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11                              /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0                                    /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7                                    /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16                                  /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16                                      /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15                               /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8                               /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2                                  /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1                                    /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0                                /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4                              /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2                              /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1                                /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8                              /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4                              /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3                                /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1                                 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0                                   /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18                                 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17                                 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16                                 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15                                  /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14                                    /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13                                    /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12                                    /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11                                /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10                               /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8                                 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7                                /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3                                  /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1                                  /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0                                  /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16                                    /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8                                   /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0                                   /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30                           /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4                              /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1                          /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-
-    /*@} end of group CMSIS_SCB */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-    /** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-    typedef struct
-    {
-        uint32_t RESERVED0[1];
-        __I uint32_t ICTR;   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-        __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
-    } SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0                                      /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos 9                                 /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos 8                                 /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2                                 /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1                                    /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0                                    /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
-
-    /*@} end of group CMSIS_SCnotSCB */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-    /** \brief  Structure type to access the System Timer (SysTick).
- */
-    typedef struct
-    {
-        __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-        __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-        __IO uint32_t VAL;  /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-        __I uint32_t CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-    } SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16                                  /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2                                   /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1                                 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0                                /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0                                       /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0                                       /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31                               /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30                              /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0                                       /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-    /*@} end of group CMSIS_SysTick */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-    /** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-    typedef struct
-    {
-        __O union
-        {
-            __O uint8_t u8;   /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-            __O uint16_t u16; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-            __O uint32_t u32; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-        } PORT[32];           /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-        uint32_t RESERVED0[864];
-        __IO uint32_t TER; /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-        uint32_t RESERVED1[15];
-        __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-        uint32_t RESERVED2[15];
-        __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-        uint32_t RESERVED3[29];
-        __O uint32_t IWR;   /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-        __I uint32_t IRR;   /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-        __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-        uint32_t RESERVED4[43];
-        __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-        __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-        uint32_t RESERVED5[6];
-        __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-        __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-        __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-        __I uint32_t PID7; /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-        __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-        __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-        __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-        __I uint32_t PID3; /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-        __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-        __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-        __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-        __I uint32_t CID3; /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-    } ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0                               /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23                        /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16                                 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10                           /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8                               /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4                           /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3                           /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1                          /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0                           /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0                                 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1                           /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-
-    /*@}*/ /* end of group CMSIS_ITM */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-    /** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-    typedef struct
-    {
-        __IO uint32_t CTRL;      /*!< Offset: 0x000 (R/W)  Control Register                          */
-        __IO uint32_t CYCCNT;    /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-        __IO uint32_t CPICNT;    /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-        __IO uint32_t EXCCNT;    /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-        __IO uint32_t SLEEPCNT;  /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-        __IO uint32_t LSUCNT;    /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-        __IO uint32_t FOLDCNT;   /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-        __I uint32_t PCSR;       /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-        __IO uint32_t COMP0;     /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-        __IO uint32_t MASK0;     /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-        __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-        uint32_t RESERVED0[1];
-        __IO uint32_t COMP1;     /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-        __IO uint32_t MASK1;     /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-        __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-        uint32_t RESERVED1[1];
-        __IO uint32_t COMP2;     /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-        __IO uint32_t MASK2;     /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-        __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-        uint32_t RESERVED2[1];
-        __IO uint32_t COMP3;     /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-        __IO uint32_t MASK3;     /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-        __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-    } DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28                              /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27                               /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26                                /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25                               /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24                               /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22                                /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21                                 /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20                                /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19                                  /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18                                /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17                                /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16                                /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12                                 /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10                              /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9                              /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5                                /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1                                  /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0                                 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0                                 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0                                 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0                                     /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0                                 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0                                   /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0                             /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24                                  /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16                                     /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12                                     /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10                                    /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9                                   /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8                                      /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7                                    /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5                                     /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0                                    /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
-
-    /*@}*/ /* end of group CMSIS_DWT */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-    /** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-    typedef struct
-    {
-        __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-        __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2];
-        __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55];
-        __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131];
-        __I uint32_t FFSR;  /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-        __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-        __I uint32_t FSCR;  /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759];
-        __I uint32_t TRIGGER;   /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-        __I uint32_t FIFO0;     /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-        __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1];
-        __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-        __I uint32_t FIFO1;     /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-        __IO uint32_t ITCTRL;   /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39];
-        __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-        __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8];
-        __I uint32_t DEVID;   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-        __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-    } TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0                                    /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0                              /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3                                 /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2                                 /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1                                 /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0                                /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8                              /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1                               /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0                                  /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29                                   /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27                                     /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26                                   /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24                                     /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16                             /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8                              /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0                              /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0                                    /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29                                   /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27                                     /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26                                   /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24                                     /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16                             /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8                              /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0                              /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0                                    /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0                              /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11                                /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10                                 /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9                                  /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6                                 /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5                                  /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0                                      /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 0                                  /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 4                                    /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-    /*@}*/ /* end of group CMSIS_TPI */
-
-#if (__MPU_PRESENT == 1)
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-    /** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-    typedef struct
-    {
-        __I uint32_t TYPE;     /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-        __IO uint32_t CTRL;    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-        __IO uint32_t RNR;     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-        __IO uint32_t RBAR;    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-        __IO uint32_t RASR;    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-        __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-        __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-        __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-        __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-        __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-        __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-    } MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16                               /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8                                /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0                              /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2                                /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1                              /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0                              /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5                                  /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4                           /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0                              /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16                               /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28                       /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24                         /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19                          /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18                      /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17                      /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16                      /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-#if (__FPU_PRESENT == 1)
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-    \brief      Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-    /** \brief  Structure type to access the Floating Point Unit (FPU).
- */
-    typedef struct
-    {
-        uint32_t RESERVED0[1];
-        __IO uint32_t FPCCR;  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
-        __IO uint32_t FPCAR;  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
-        __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
-        __I uint32_t MVFR0;   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
-        __I uint32_t MVFR1;   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
-    } FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos 31                           /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30                           /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8                             /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3                             /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1                           /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0                             /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos 3                                       /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos 26                          /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25                         /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24                         /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28                                         /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24                                     /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20                                   /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16                              /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12                                         /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8                                         /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4                                         /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0                                         /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28                                    /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24                               /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4                                   /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0                                 /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-    /** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-    typedef struct
-    {
-        __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-        __O uint32_t DCRSR;  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-        __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-        __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-    } CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16                                       /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25                                      /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24                                       /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19                                    /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18                                   /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17                                  /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16                                    /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5                                        /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3                                       /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2                                   /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1                                   /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0                                      /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16                                  /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0                                      /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24                                  /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19                                   /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18                                    /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17                                    /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16                                  /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10                                      /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9                                      /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8                                      /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7                                       /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6                                      /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5                                       /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4                                     /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0                                         /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE (0xE000E000UL)            /*!< System Control Space Base Address  */
-#define ITM_BASE (0xE0000000UL)            /*!< ITM Base Address                   */
-#define DWT_BASE (0xE0001000UL)            /*!< DWT Base Address                   */
-#define TPI_BASE (0xE0040000UL)            /*!< TPI Base Address                   */
-#define CoreDebug_BASE (0xE000EDF0UL)      /*!< Core Debug Base Address            */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address               */
-#define NVIC_BASE (SCS_BASE + 0x0100UL)    /*!< NVIC Base Address                  */
-#define SCB_BASE (SCS_BASE + 0x0D00UL)     /*!< System Control Block Base Address  */
-
-#define SCnSCB ((SCnSCB_Type *)SCS_BASE)             /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *)SCB_BASE)                   /*!< SCB configuration struct           */
-#define SysTick ((SysTick_Type *)SysTick_BASE)       /*!< SysTick configuration struct       */
-#define NVIC ((NVIC_Type *)NVIC_BASE)                /*!< NVIC configuration struct          */
-#define ITM ((ITM_Type *)ITM_BASE)                   /*!< ITM configuration struct           */
-#define DWT ((DWT_Type *)DWT_BASE)                   /*!< DWT configuration struct           */
-#define TPI ((TPI_Type *)TPI_BASE)                   /*!< TPI configuration struct           */
-#define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit             */
-#define MPU ((MPU_Type *)MPU_BASE)     /*!< Memory Protection Unit             */
-#endif
-
-#if (__FPU_PRESENT == 1)
-#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit                */
-#define FPU ((FPU_Type *)FPU_BASE)     /*!< Floating Point Unit                */
-#endif
-
-    /*@} */
-
-    /*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-    /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-    /* ##########################   NVIC functions  #################################### */
-    /** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-    /** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-    __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-    {
-        uint32_t reg_value;
-        uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used          */
-
-        reg_value = SCB->AIRCR;                                         /* read old register configuration    */
-        reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change               */
-        reg_value = (reg_value |
-                     ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                     (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
-        SCB->AIRCR = reg_value;
-    }
-
-    /** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-    __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-    {
-        return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
-    }
-
-    /** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-    {
-        /*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
-        NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
-    }
-
-    /** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* disable interrupt */
-    }
-
-    /** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-    __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-    {
-        return ((uint32_t)((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */
-    }
-
-    /** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* set interrupt pending */
-    }
-
-    /** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */
-    }
-
-    /** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-    __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-    {
-        return ((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */
-    }
-
-    /** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-    __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-    {
-        if (IRQn < 0)
-        {
-            SCB->SHP[((uint32_t)(IRQn)&0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
-        } /* set Priority for Cortex-M  System Interrupts */
-        else
-        {
-            NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
-        } /* set Priority for device specific Interrupts  */
-    }
-
-    /** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-    __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-    {
-
-        if (IRQn < 0)
-        {
-            return ((uint32_t)(SCB->SHP[((uint32_t)(IRQn)&0xF) - 4] >> (8 - __NVIC_PRIO_BITS)));
-        } /* get priority for Cortex-M  system interrupts */
-        else
-        {
-            return ((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS)));
-        } /* get priority for device specific interrupts  */
-    }
-
-    /** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-    __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-    {
-        uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used          */
-        uint32_t PreemptPriorityBits;
-        uint32_t SubPriorityBits;
-
-        PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-        SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-        return (
-            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-            ((SubPriority & ((1 << (SubPriorityBits)) - 1))));
-    }
-
-    /** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-    __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
-    {
-        uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used          */
-        uint32_t PreemptPriorityBits;
-        uint32_t SubPriorityBits;
-
-        PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-        SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-        *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-        *pSubPriority = (Priority) & ((1 << (SubPriorityBits)) - 1);
-    }
-
-    /** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-    __STATIC_INLINE void NVIC_SystemReset(void)
-    {
-        __DSB(); /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-        SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                      (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                      SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
-        __DSB();                                  /* Ensure completion of memory access */
-        while (1)
-            ; /* wait until reset */
-    }
-
-    /*@} end of CMSIS_Core_NVICFunctions */
-
-    /* ##################################    SysTick function  ############################################ */
-    /** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-    /** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-    __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-    {
-        if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)
-            return (1); /* Reload value impossible */
-
-        SysTick->LOAD = ticks - 1;                                   /* set reload register */
-        NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
-        SysTick->VAL = 0;                                            /* Load the SysTick Counter Value */
-        SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                        SysTick_CTRL_TICKINT_Msk |
-                        SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
-        return (0);                              /* Function successful */
-    }
-
-#endif
-
-    /*@} end of CMSIS_Core_SysTickFunctions */
-
-    /* ##################################### Debug In/Output function ########################################### */
-    /** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-    extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters.                         */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5     /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-    /** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-    __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
-    {
-        if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
-            (ITM->TER & (1UL << 0)))           /* ITM Port #0 enabled */
-        {
-            while (ITM->PORT[0].u32 == 0)
-                ;
-            ITM->PORT[0].u8 = (uint8_t)ch;
-        }
-        return (ch);
-    }
-
-    /** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-    __STATIC_INLINE int32_t ITM_ReceiveChar(void)
-    {
-        int32_t ch = -1; /* no character available */
-
-        if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-        {
-            ch = ITM_RxBuffer;
-            ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
-        }
-
-        return (ch);
-    }
-
-    /** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-    __STATIC_INLINE int32_t ITM_CheckChar(void)
-    {
-
-        if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-        {
-            return (0); /* no character available */
-        }
-        else
-        {
-            return (1); /*    character available */
-        }
-    }
-
-    /*@} end of CMSIS_core_DebugFunctions */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

bsp/swm320/libraries/CMSIS/CoreSupport/core_cm7.h

@@ -1,2193 +0,0 @@
-/**************************************************************************/ /**
- * @file     core_cm7.h
- * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
- * @version  V4.00
- * @date     01. September 2014
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-#if defined(__ICCARM__)
-#pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM7_H_GENERIC
-#define __CORE_CM7_H_GENERIC
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M7
-  @{
- */
-
-/*  CMSIS CM7 definitions */
-#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version   */
-#define __CM7_CMSIS_VERSION_SUB (0x00)  /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
-                             __CM7_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M (0x07) /*!< Cortex-M Core                    */
-
-#if defined(__CC_ARM)
-#define __ASM __asm       /*!< asm keyword for ARM Compiler          */
-#define __INLINE __inline /*!< inline keyword for ARM Compiler       */
-#define __STATIC_INLINE static __inline
-
-#elif defined(__GNUC__)
-#define __ASM __asm     /*!< asm keyword for GNU Compiler          */
-#define __INLINE inline /*!< inline keyword for GNU Compiler       */
-#define __STATIC_INLINE static inline
-
-#elif defined(__ICCARM__)
-#define __ASM __asm     /*!< asm keyword for IAR Compiler          */
-#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-#define __STATIC_INLINE static inline
-
-#elif defined(__TMS470__)
-#define __ASM __asm /*!< asm keyword for TI CCS Compiler       */
-#define __STATIC_INLINE static inline
-
-#elif defined(__TASKING__)
-#define __ASM __asm     /*!< asm keyword for TASKING Compiler      */
-#define __INLINE inline /*!< inline keyword for TASKING Compiler   */
-#define __STATIC_INLINE static inline
-
-#elif defined(__CSMC__)
-#define __packed
-#define __ASM _asm      /*!< asm keyword for COSMIC Compiler      */
-#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-#define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined(__CC_ARM)
-#if defined __TARGET_FPU_VFP
-#if (__FPU_PRESENT == 1)
-#define __FPU_USED 1
-#else
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED 0
-#endif
-#else
-#define __FPU_USED 0
-#endif
-
-#elif defined(__GNUC__)
-#if defined(__VFP_FP__) && !defined(__SOFTFP__)
-#if (__FPU_PRESENT == 1)
-#define __FPU_USED 1
-#else
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED 0
-#endif
-#else
-#define __FPU_USED 0
-#endif
-
-#elif defined(__ICCARM__)
-#if defined __ARMVFP__
-#if (__FPU_PRESENT == 1)
-#define __FPU_USED 1
-#else
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED 0
-#endif
-#else
-#define __FPU_USED 0
-#endif
-
-#elif defined(__TMS470__)
-#if defined __TI_VFP_SUPPORT__
-#if (__FPU_PRESENT == 1)
-#define __FPU_USED 1
-#else
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED 0
-#endif
-#else
-#define __FPU_USED 0
-#endif
-
-#elif defined(__TASKING__)
-#if defined __FPU_VFP__
-#if (__FPU_PRESENT == 1)
-#define __FPU_USED 1
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED 0
-#endif
-#else
-#define __FPU_USED 0
-#endif
-
-#elif defined(__CSMC__) /* Cosmic */
-#if (__CSMC__ & 0x400)  // FPU present for parser
-#if (__FPU_PRESENT == 1)
-#define __FPU_USED 1
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED 0
-#endif
-#else
-#define __FPU_USED 0
-#endif
-#endif
-
-#include <stdint.h>       /* standard types definitions                      */
-#include <core_cmInstr.h> /* Core Instruction Access                         */
-#include <core_cmFunc.h>  /* Core Function Access                            */
-#include <core_cmSimd.h>  /* Compiler specific SIMD Intrinsics               */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM7_H_DEPENDANT
-#define __CORE_CM7_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM7_REV
-#define __CM7_REV 0x0000
-#warning "__CM7_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT 0
-#warning "__FPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT 0
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __ICACHE_PRESENT
-#define __ICACHE_PRESENT 0
-#warning "__ICACHE_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __DCACHE_PRESENT
-#define __DCACHE_PRESENT 0
-#warning "__DCACHE_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __DTCM_PRESENT
-#define __DTCM_PRESENT 0
-#warning "__DTCM_PRESENT        not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS 3
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig 0
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define __I volatile /*!< Defines 'read only' permissions                 */
-#else
-#define __I volatile const /*!< Defines 'read only' permissions                 */
-#endif
-#define __O volatile  /*!< Defines 'write only' permissions                */
-#define __IO volatile /*!< Defines 'read / write' permissions              */
-
-    /*@} end of group Cortex_M7 */
-
-    /*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-    /** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-    /** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-    /** \brief  Union type to access the Application Program Status Register (APSR).
- */
-    typedef union
-    {
-        struct
-        {
-#if (__CORTEX_M != 0x07)
-            uint32_t _reserved0 : 27; /*!< bit:  0..26  Reserved                           */
-#else
-        uint32_t _reserved0 : 16; /*!< bit:  0..15  Reserved                           */
-        uint32_t GE : 4;          /*!< bit: 16..19  Greater than or Equal flags        */
-        uint32_t _reserved1 : 7;  /*!< bit: 20..26  Reserved                           */
-#endif
-            uint32_t Q : 1; /*!< bit:     27  Saturation condition flag          */
-            uint32_t V : 1; /*!< bit:     28  Overflow condition code flag       */
-            uint32_t C : 1; /*!< bit:     29  Carry condition code flag          */
-            uint32_t Z : 1; /*!< bit:     30  Zero condition code flag           */
-            uint32_t N : 1; /*!< bit:     31  Negative condition code flag       */
-        } b;                /*!< Structure used for bit  access                  */
-        uint32_t w;         /*!< Type      used for word access                  */
-    } APSR_Type;
-
-    /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-    typedef union
-    {
-        struct
-        {
-            uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number                   */
-            uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved                           */
-        } b;                          /*!< Structure used for bit  access                  */
-        uint32_t w;                   /*!< Type      used for word access                  */
-    } IPSR_Type;
-
-    /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-    typedef union
-    {
-        struct
-        {
-            uint32_t ISR : 9; /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x07)
-            uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved                           */
-#else
-        uint32_t _reserved0 : 7;  /*!< bit:  9..15  Reserved                           */
-        uint32_t GE : 4;          /*!< bit: 16..19  Greater than or Equal flags        */
-        uint32_t _reserved1 : 4;  /*!< bit: 20..23  Reserved                           */
-#endif
-            uint32_t T : 1;  /*!< bit:     24  Thumb bit        (read 0)          */
-            uint32_t IT : 2; /*!< bit: 25..26  saved IT state   (read 0)          */
-            uint32_t Q : 1;  /*!< bit:     27  Saturation condition flag          */
-            uint32_t V : 1;  /*!< bit:     28  Overflow condition code flag       */
-            uint32_t C : 1;  /*!< bit:     29  Carry condition code flag          */
-            uint32_t Z : 1;  /*!< bit:     30  Zero condition code flag           */
-            uint32_t N : 1;  /*!< bit:     31  Negative condition code flag       */
-        } b;                 /*!< Structure used for bit  access                  */
-        uint32_t w;          /*!< Type      used for word access                  */
-    } xPSR_Type;
-
-    /** \brief  Union type to access the Control Registers (CONTROL).
- */
-    typedef union
-    {
-        struct
-        {
-            uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
-            uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used                   */
-            uint32_t FPCA : 1;        /*!< bit:      2  FP extension active flag           */
-            uint32_t _reserved0 : 29; /*!< bit:  3..31  Reserved                           */
-        } b;                          /*!< Structure used for bit  access                  */
-        uint32_t w;                   /*!< Type      used for word access                  */
-    } CONTROL_Type;
-
-    /*@} end of group CMSIS_CORE */
-
-    /** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-    /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-    typedef struct
-    {
-        __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-        uint32_t RESERVED0[24];
-        __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-        uint32_t RSERVED1[24];
-        __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-        uint32_t RESERVED2[24];
-        __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-        uint32_t RESERVED3[24];
-        __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-        uint32_t RESERVED4[56];
-        __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED5[644];
-        __O uint32_t STIR; /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-    } NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0                                /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
-
-    /*@} end of group CMSIS_NVIC */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-    /** \brief  Structure type to access the System Control Block (SCB).
- */
-    typedef struct
-    {
-        __I uint32_t CPUID;      /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-        __IO uint32_t ICSR;      /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-        __IO uint32_t VTOR;      /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-        __IO uint32_t AIRCR;     /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-        __IO uint32_t SCR;       /*!< Offset: 0x010 (R/W)  System Control Register                               */
-        __IO uint32_t CCR;       /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-        __IO uint8_t SHPR[12];   /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-        __IO uint32_t SHCSR;     /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-        __IO uint32_t CFSR;      /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-        __IO uint32_t HFSR;      /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-        __IO uint32_t DFSR;      /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-        __IO uint32_t MMFAR;     /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-        __IO uint32_t BFAR;      /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-        __IO uint32_t AFSR;      /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-        __I uint32_t ID_PFR[2];  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-        __I uint32_t ID_DFR;     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-        __I uint32_t ID_AFR;     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-        __I uint32_t ID_MFR[4];  /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-        __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-        uint32_t RESERVED0[1];
-        __I uint32_t CLIDR;   /*!< Offset: 0x078 (R/ )  Cache Level ID register                               */
-        __I uint32_t CTR;     /*!< Offset: 0x07C (R/ )  Cache Type register                                   */
-        __I uint32_t CCSIDR;  /*!< Offset: 0x080 (R/ )  Cache Size ID Register                                */
-        __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W)  Cache Size Selection Register                         */
-        __IO uint32_t CPACR;  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-        uint32_t RESERVED3[93];
-        __O uint32_t STIR; /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register                 */
-        uint32_t RESERVED4[15];
-        __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0                      */
-        __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1                      */
-        __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1                      */
-        uint32_t RESERVED5[1];
-        __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU                         */
-        uint32_t RESERVED6[1];
-        __O uint32_t ICIMVAU;  /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU                      */
-        __O uint32_t DCIMVAU;  /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC                      */
-        __O uint32_t DCISW;    /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way                         */
-        __O uint32_t DCCMVAU;  /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU                           */
-        __O uint32_t DCCMVAC;  /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC                           */
-        __O uint32_t DCCSW;    /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way                              */
-        __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC            */
-        __O uint32_t DCCISW;   /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way               */
-        uint32_t RESERVED7[6];
-        __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register   */
-        __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers         */
-        __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W)  AHBP Control Register                                 */
-        __IO uint32_t CACR;   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register                             */
-        __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register                            */
-        uint32_t RESERVED8[1];
-        __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register                   */
-    } SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24                                    /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20                               /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16                                    /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4                                 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0                                 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31                               /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28                              /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27                              /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26                              /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25                              /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23                               /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22                               /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12                                    /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11                              /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0                                    /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7                                    /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16                                  /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16                                      /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15                               /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8                               /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2                                  /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1                                    /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0                                /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4                              /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2                              /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1                                /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos 18                      /*!< SCB CCR: Branch prediction enable bit Position */
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
-
-#define SCB_CCR_IC_Pos 17                      /*!< SCB CCR: Instruction cache enable bit Position */
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
-
-#define SCB_CCR_DC_Pos 16                      /*!< SCB CCR: Cache enable bit Position */
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
-
-#define SCB_CCR_STKALIGN_Pos 9                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8                              /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4                              /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3                                /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1                                 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0                                   /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18                                 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17                                 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16                                 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15                                  /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14                                    /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13                                    /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12                                    /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11                                /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10                               /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8                                 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7                                /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3                                  /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1                                  /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0                                  /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16                                    /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8                                   /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0                                   /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30                           /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4                              /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1                          /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-
-/* Cache Level ID register */
-#define SCB_CLIDR_LOUU_Pos 27                          /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos 24                            /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
-
-/* Cache Type register */
-#define SCB_CTR_FORMAT_Pos 29                          /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos 24                         /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos 20                         /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos 16                              /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos 0                               /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */
-
-/* Cache Size ID Register */
-#define SCB_CCSIDR_WT_Pos 31                         /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos 30                         /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos 29                         /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos 28                         /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos 13                                   /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3                                         /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos 0                                /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */
-
-/* Cache Size Selection Register */
-#define SCB_CSSELR_LEVEL_Pos 0                             /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos 0                           /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register */
-#define SCB_STIR_INTID_Pos 0                               /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register*/
-#define SCB_ITCMCR_SZ_Pos 3                            /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos 2                               /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos 1                             /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos 0                            /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Registers */
-#define SCB_DTCMCR_SZ_Pos 3                            /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos 2                             /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos 1                           /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos 0                          /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register */
-#define SCB_AHBPCR_SZ_Pos 1                          /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos 0                          /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register */
-#define SCB_CACR_FORCEWT_Pos 2                             /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos 1                           /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos 0                          /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */
-
-/* AHBS control register */
-#define SCB_AHBSCR_INITCOUNT_Pos 11                                   /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos 2                                /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos 0                           /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register */
-#define SCB_ABFSR_AXIMTYPE_Pos 8                               /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos 4                           /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos 3                           /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos 2                           /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos 1                           /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos 0                           /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */
-
-    /*@} end of group CMSIS_SCB */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-    /** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-    typedef struct
-    {
-        uint32_t RESERVED0[1];
-        __I uint32_t ICTR;   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-        __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
-    } SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0                                      /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12                                       /*!< ACTLR: DISITMATBFLUSH Position */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
-
-#define SCnSCB_ACTLR_DISRAMODE_Pos 11                                  /*!< ACTLR: DISRAMODE Position */
-#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
-
-#define SCnSCB_ACTLR_FPEXCODIS_Pos 10                                  /*!< ACTLR: FPEXCODIS Position */
-#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2                                 /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0                                    /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
-
-    /*@} end of group CMSIS_SCnotSCB */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-    /** \brief  Structure type to access the System Timer (SysTick).
- */
-    typedef struct
-    {
-        __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-        __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-        __IO uint32_t VAL;  /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-        __I uint32_t CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-    } SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16                                  /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2                                   /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1                                 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0                                /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0                                       /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0                                       /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31                               /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30                              /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0                                       /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-    /*@} end of group CMSIS_SysTick */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-    /** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-    typedef struct
-    {
-        __O union
-        {
-            __O uint8_t u8;   /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-            __O uint16_t u16; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-            __O uint32_t u32; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-        } PORT[32];           /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-        uint32_t RESERVED0[864];
-        __IO uint32_t TER; /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-        uint32_t RESERVED1[15];
-        __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-        uint32_t RESERVED2[15];
-        __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-        uint32_t RESERVED3[29];
-        __O uint32_t IWR;   /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-        __I uint32_t IRR;   /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-        __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-        uint32_t RESERVED4[43];
-        __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-        __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-        uint32_t RESERVED5[6];
-        __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-        __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-        __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-        __I uint32_t PID7; /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-        __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-        __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-        __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-        __I uint32_t PID3; /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-        __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-        __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-        __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-        __I uint32_t CID3; /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-    } ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0                               /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23                        /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16                                 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10                           /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8                               /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4                           /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3                           /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1                          /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0                           /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0                                 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1                           /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-
-    /*@}*/ /* end of group CMSIS_ITM */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-    /** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-    typedef struct
-    {
-        __IO uint32_t CTRL;      /*!< Offset: 0x000 (R/W)  Control Register                          */
-        __IO uint32_t CYCCNT;    /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-        __IO uint32_t CPICNT;    /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-        __IO uint32_t EXCCNT;    /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-        __IO uint32_t SLEEPCNT;  /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-        __IO uint32_t LSUCNT;    /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-        __IO uint32_t FOLDCNT;   /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-        __I uint32_t PCSR;       /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-        __IO uint32_t COMP0;     /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-        __IO uint32_t MASK0;     /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-        __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-        uint32_t RESERVED0[1];
-        __IO uint32_t COMP1;     /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-        __IO uint32_t MASK1;     /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-        __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-        uint32_t RESERVED1[1];
-        __IO uint32_t COMP2;     /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-        __IO uint32_t MASK2;     /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-        __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-        uint32_t RESERVED2[1];
-        __IO uint32_t COMP3;     /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-        __IO uint32_t MASK3;     /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-        __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-        uint32_t RESERVED3[981];
-        __O uint32_t LAR; /*!< Offset: 0xFB0 (  W)  Lock Access Register                      */
-        __I uint32_t LSR; /*!< Offset: 0xFB4 (R  )  Lock Status Register                      */
-    } DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28                              /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27                               /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26                                /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25                               /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24                               /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22                                /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21                                 /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20                                /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19                                  /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18                                /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17                                /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16                                /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12                                 /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10                              /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9                              /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5                                /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1                                  /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0                                 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0                                 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0                                 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0                                     /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0                                 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0                                   /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0                             /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24                                  /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16                                     /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12                                     /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10                                    /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9                                   /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8                                      /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7                                    /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5                                     /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0                                    /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
-
-    /*@}*/ /* end of group CMSIS_DWT */
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-    /** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-    typedef struct
-    {
-        __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-        __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2];
-        __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55];
-        __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131];
-        __I uint32_t FFSR;  /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-        __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-        __I uint32_t FSCR;  /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759];
-        __I uint32_t TRIGGER;   /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-        __I uint32_t FIFO0;     /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-        __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1];
-        __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-        __I uint32_t FIFO1;     /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-        __IO uint32_t ITCTRL;   /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39];
-        __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-        __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8];
-        __I uint32_t DEVID;   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-        __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-    } TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0                                    /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0                              /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3                                 /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2                                 /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1                                 /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0                                /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8                              /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1                               /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0                                  /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29                                   /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27                                     /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26                                   /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24                                     /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16                             /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8                              /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0                              /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0                                    /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29                                   /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27                                     /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26                                   /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24                                     /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16                             /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8                              /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0                              /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0                                    /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0                              /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11                                /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10                                 /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9                                  /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6                                 /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5                                  /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0                                      /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 0                                  /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 4                                    /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-    /*@}*/ /* end of group CMSIS_TPI */
-
-#if (__MPU_PRESENT == 1)
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-    /** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-    typedef struct
-    {
-        __I uint32_t TYPE;     /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-        __IO uint32_t CTRL;    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-        __IO uint32_t RNR;     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-        __IO uint32_t RBAR;    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-        __IO uint32_t RASR;    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-        __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-        __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-        __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-        __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-        __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-        __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-    } MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16                               /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8                                /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0                              /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2                                /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1                              /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0                              /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5                                  /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4                           /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0                              /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16                               /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28                       /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24                         /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19                          /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18                      /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17                      /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16                      /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-#if (__FPU_PRESENT == 1)
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-    \brief      Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-    /** \brief  Structure type to access the Floating Point Unit (FPU).
- */
-    typedef struct
-    {
-        uint32_t RESERVED0[1];
-        __IO uint32_t FPCCR;  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
-        __IO uint32_t FPCAR;  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
-        __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
-        __I uint32_t MVFR0;   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
-        __I uint32_t MVFR1;   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
-        __I uint32_t MVFR2;   /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2                       */
-    } FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos 31                           /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30                           /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8                             /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3                             /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1                           /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0                             /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos 3                                       /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos 26                          /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25                         /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24                         /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28                                         /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24                                     /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20                                   /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16                              /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12                                         /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8                                         /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4                                         /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0                                         /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28                                    /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24                               /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4                                   /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0                                 /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
-
-/* Media and FP Feature Register 2 */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-    /** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-    /** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-    typedef struct
-    {
-        __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-        __O uint32_t DCRSR;  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-        __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-        __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-    } CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16                                       /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25                                      /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24                                       /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19                                    /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18                                   /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17                                  /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16                                    /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5                                        /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3                                       /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2                                   /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1                                   /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0                                      /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16                                  /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0                                      /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24                                  /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19                                   /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18                                    /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17                                    /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16                                  /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10                                      /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9                                      /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8                                      /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7                                       /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6                                      /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5                                       /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4                                     /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0                                         /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE (0xE000E000UL)            /*!< System Control Space Base Address  */
-#define ITM_BASE (0xE0000000UL)            /*!< ITM Base Address                   */
-#define DWT_BASE (0xE0001000UL)            /*!< DWT Base Address                   */
-#define TPI_BASE (0xE0040000UL)            /*!< TPI Base Address                   */
-#define CoreDebug_BASE (0xE000EDF0UL)      /*!< Core Debug Base Address            */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address               */
-#define NVIC_BASE (SCS_BASE + 0x0100UL)    /*!< NVIC Base Address                  */
-#define SCB_BASE (SCS_BASE + 0x0D00UL)     /*!< System Control Block Base Address  */
-
-#define SCnSCB ((SCnSCB_Type *)SCS_BASE)             /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *)SCB_BASE)                   /*!< SCB configuration struct           */
-#define SysTick ((SysTick_Type *)SysTick_BASE)       /*!< SysTick configuration struct       */
-#define NVIC ((NVIC_Type *)NVIC_BASE)                /*!< NVIC configuration struct          */
-#define ITM ((ITM_Type *)ITM_BASE)                   /*!< ITM configuration struct           */
-#define DWT ((DWT_Type *)DWT_BASE)                   /*!< DWT configuration struct           */
-#define TPI ((TPI_Type *)TPI_BASE)                   /*!< TPI configuration struct           */
-#define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit             */
-#define MPU ((MPU_Type *)MPU_BASE)     /*!< Memory Protection Unit             */
-#endif
-
-#if (__FPU_PRESENT == 1)
-#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit                */
-#define FPU ((FPU_Type *)FPU_BASE)     /*!< Floating Point Unit                */
-#endif
-
-    /*@} */
-
-    /*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-    /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-    /* ##########################   NVIC functions  #################################### */
-    /** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-    /** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-    __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-    {
-        uint32_t reg_value;
-        uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used          */
-
-        reg_value = SCB->AIRCR;                                         /* read old register configuration    */
-        reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change               */
-        reg_value = (reg_value |
-                     ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                     (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
-        SCB->AIRCR = reg_value;
-    }
-
-    /** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-    __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-    {
-        return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
-    }
-
-    /** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-    {
-        /*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
-        NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
-    }
-
-    /** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* disable interrupt */
-    }
-
-    /** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-    __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-    {
-        return ((uint32_t)((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */
-    }
-
-    /** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* set interrupt pending */
-    }
-
-    /** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-    __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-    {
-        NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */
-    }
-
-    /** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-    __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-    {
-        return ((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */
-    }
-
-    /** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-    __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-    {
-        if (IRQn < 0)
-        {
-            SCB->SHPR[((uint32_t)(IRQn)&0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
-        } /* set Priority for Cortex-M  System Interrupts */
-        else
-        {
-            NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
-        } /* set Priority for device specific Interrupts  */
-    }
-
-    /** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-    __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-    {
-
-        if (IRQn < 0)
-        {
-            return ((uint32_t)(SCB->SHPR[((uint32_t)(IRQn)&0xF) - 4] >> (8 - __NVIC_PRIO_BITS)));
-        } /* get priority for Cortex-M  system interrupts */
-        else
-        {
-            return ((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS)));
-        } /* get priority for device specific interrupts  */
-    }
-
-    /** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-    __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-    {
-        uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used          */
-        uint32_t PreemptPriorityBits;
-        uint32_t SubPriorityBits;
-
-        PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-        SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-        return (
-            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-            ((SubPriority & ((1 << (SubPriorityBits)) - 1))));
-    }
-
-    /** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-    __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
-    {
-        uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used          */
-        uint32_t PreemptPriorityBits;
-        uint32_t SubPriorityBits;
-
-        PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-        SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-        *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-        *pSubPriority = (Priority) & ((1 << (SubPriorityBits)) - 1);
-    }
-
-    /** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-    __STATIC_INLINE void NVIC_SystemReset(void)
-    {
-        __DSB(); /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-        SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                      (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                      SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
-        __DSB();                                  /* Ensure completion of memory access */
-        while (1)
-            ; /* wait until reset */
-    }
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ##########################  Cache functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_CacheFunctions Cache Functions
-    \brief      Functions that configure Instruction and Data cache.
-    @{
- */
-
-/* Cache Size ID Register Macros */
-#define CCSIDR_WAYS(x) (((x)&SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
-#define CCSIDR_SETS(x) (((x)&SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos)
-#define CCSIDR_LSSHIFT(x) (((x)&SCB_CCSIDR_LINESIZE_Msk) >> SCB_CCSIDR_LINESIZE_Pos)
-
-    /** \brief Enable I-Cache
-
-    The function turns on I-Cache
-  */
-    __STATIC_INLINE void SCB_EnableICache(void)
-    {
-#if (__ICACHE_PRESENT == 1)
-        __DSB();
-        __ISB();
-        SCB->ICIALLU = 0;           // invalidate I-Cache
-        SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache
-        __DSB();
-        __ISB();
-#endif
-    }
-
-    /** \brief Disable I-Cache
-
-    The function turns off I-Cache
-  */
-    __STATIC_INLINE void SCB_DisableICache(void)
-    {
-#if (__ICACHE_PRESENT == 1)
-        __DSB();
-        __ISB();
-        SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache
-        SCB->ICIALLU = 0;            // invalidate I-Cache
-        __DSB();
-        __ISB();
-#endif
-    }
-
-    /** \brief Invalidate I-Cache
-
-    The function invalidates I-Cache
-  */
-    __STATIC_INLINE void SCB_InvalidateICache(void)
-    {
-#if (__ICACHE_PRESENT == 1)
-        __DSB();
-        __ISB();
-        SCB->ICIALLU = 0;
-        __DSB();
-        __ISB();
-#endif
-    }
-
-    /** \brief Enable D-Cache
-
-    The function turns on D-Cache
-  */
-    __STATIC_INLINE void SCB_EnableDCache(void)
-    {
-#if (__DCACHE_PRESENT == 1)
-        uint32_t ccsidr, sshift, wshift, sw;
-        uint32_t sets, ways;
-
-        ccsidr = SCB->CCSIDR;
-        sets = CCSIDR_SETS(ccsidr);
-        sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
-        ways = CCSIDR_WAYS(ccsidr);
-        wshift = __CLZ(ways) & 0x1f;
-
-        __DSB();
-
-        do
-        { // invalidate D-Cache
-            int32_t tmpways = ways;
-            do
-            {
-                sw = ((tmpways << wshift) | (sets << sshift));
-                SCB->DCISW = sw;
-            } while (tmpways--);
-        } while (sets--);
-        __DSB();
-
-        SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache
-
-        __DSB();
-        __ISB();
-#endif
-    }
-
-    /** \brief Disable D-Cache
-
-    The function turns off D-Cache
-  */
-    __STATIC_INLINE void SCB_DisableDCache(void)
-    {
-#if (__DCACHE_PRESENT == 1)
-        uint32_t ccsidr, sshift, wshift, sw;
-        uint32_t sets, ways;
-
-        ccsidr = SCB->CCSIDR;
-        sets = CCSIDR_SETS(ccsidr);
-        sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
-        ways = CCSIDR_WAYS(ccsidr);
-        wshift = __CLZ(ways) & 0x1f;
-
-        __DSB();
-
-        SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache
-
-        do
-        { // clean & invalidate D-Cache
-            int32_t tmpways = ways;
-            do
-            {
-                sw = ((tmpways << wshift) | (sets << sshift));
-                SCB->DCCISW = sw;
-            } while (tmpways--);
-        } while (sets--);
-
-        __DSB();
-        __ISB();
-#endif
-    }
-
-    /** \brief Invalidate D-Cache
-
-    The function invalidates D-Cache
-  */
-    __STATIC_INLINE void SCB_InvalidateDCache(void)
-    {
-#if (__DCACHE_PRESENT == 1)
-        uint32_t ccsidr, sshift, wshift, sw;
-        uint32_t sets, ways;
-
-        ccsidr = SCB->CCSIDR;
-        sets = CCSIDR_SETS(ccsidr);
-        sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
-        ways = CCSIDR_WAYS(ccsidr);
-        wshift = __CLZ(ways) & 0x1f;
-
-        __DSB();
-
-        do
-        { // invalidate D-Cache
-            int32_t tmpways = ways;
-            do
-            {
-                sw = ((tmpways << wshift) | (sets << sshift));
-                SCB->DCISW = sw;
-            } while (tmpways--);
-        } while (sets--);
-
-        __DSB();
-        __ISB();
-#endif
-    }
-
-    /** \brief Clean D-Cache
-
-    The function cleans D-Cache
-  */
-    __STATIC_INLINE void SCB_CleanDCache(void)
-    {
-#if (__DCACHE_PRESENT == 1)
-        uint32_t ccsidr, sshift, wshift, sw;
-        uint32_t sets, ways;
-
-        ccsidr = SCB->CCSIDR;
-        sets = CCSIDR_SETS(ccsidr);
-        sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
-        ways = CCSIDR_WAYS(ccsidr);
-        wshift = __CLZ(ways) & 0x1f;
-
-        __DSB();
-
-        do
-        { // clean D-Cache
-            int32_t tmpways = ways;
-            do
-            {
-                sw = ((tmpways << wshift) | (sets << sshift));
-                SCB->DCCSW = sw;
-            } while (tmpways--);
-        } while (sets--);
-
-        __DSB();
-        __ISB();
-#endif
-    }
-
-    /** \brief Clean & Invalidate D-Cache
-
-    The function cleans and Invalidates D-Cache
-  */
-    __STATIC_INLINE void SCB_CleanInvalidateDCache(void)
-    {
-#if (__DCACHE_PRESENT == 1)
-        uint32_t ccsidr, sshift, wshift, sw;
-        uint32_t sets, ways;
-
-        ccsidr = SCB->CCSIDR;
-        sets = CCSIDR_SETS(ccsidr);
-        sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
-        ways = CCSIDR_WAYS(ccsidr);
-        wshift = __CLZ(ways) & 0x1f;
-
-        __DSB();
-
-        do
-        { // clean & invalidate D-Cache
-            int32_t tmpways = ways;
-            do
-            {
-                sw = ((tmpways << wshift) | (sets << sshift));
-                SCB->DCCISW = sw;
-            } while (tmpways--);
-        } while (sets--);
-
-        __DSB();
-        __ISB();
-#endif
-    }
-
-    /*@} end of CMSIS_Core_CacheFunctions */
-
-    /* ##################################    SysTick function  ############################################ */
-    /** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-    /** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-    __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-    {
-        if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)
-            return (1); /* Reload value impossible */
-
-        SysTick->LOAD = ticks - 1;                                   /* set reload register */
-        NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
-        SysTick->VAL = 0;                                            /* Load the SysTick Counter Value */
-        SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-                        SysTick_CTRL_TICKINT_Msk |
-                        SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
-        return (0);                              /* Function successful */
-    }
-
-#endif
-
-    /*@} end of CMSIS_Core_SysTickFunctions */
-
-    /* ##################################### Debug In/Output function ########################################### */
-    /** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-    extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters.                         */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5     /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-    /** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-    __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
-    {
-        if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
-            (ITM->TER & (1UL << 0)))           /* ITM Port #0 enabled */
-        {
-            while (ITM->PORT[0].u32 == 0)
-                ;
-            ITM->PORT[0].u8 = (uint8_t)ch;
-        }
-        return (ch);
-    }
-
-    /** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-    __STATIC_INLINE int32_t ITM_ReceiveChar(void)
-    {
-        int32_t ch = -1; /* no character available */
-
-        if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-        {
-            ch = ITM_RxBuffer;
-            ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
-        }
-
-        return (ch);
-    }
-
-    /** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-    __STATIC_INLINE int32_t ITM_CheckChar(void)
-    {
-
-        if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-        {
-            return (0); /* no character available */
-        }
-        else
-        {
-            return (1); /*    character available */
-        }
-    }
-
-    /*@} end of CMSIS_core_DebugFunctions */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

bsp/swm320/libraries/CMSIS/CoreSupport/core_cmSimd.h

@@ -1,830 +0,0 @@
-/**************************************************************************/ /**
- * @file     core_cmSimd.h
- * @brief    CMSIS Cortex-M SIMD Header File
- * @version  V4.00
- * @date     22. August 2014
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-#if defined(__ICCARM__)
-#pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CMSIMD_H
-#define __CORE_CMSIMD_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-    /*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-    /* ###################  Compiler specific Intrinsics  ########################### */
-    /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-#define __SADD8 __sadd8
-#define __QADD8 __qadd8
-#define __SHADD8 __shadd8
-#define __UADD8 __uadd8
-#define __UQADD8 __uqadd8
-#define __UHADD8 __uhadd8
-#define __SSUB8 __ssub8
-#define __QSUB8 __qsub8
-#define __SHSUB8 __shsub8
-#define __USUB8 __usub8
-#define __UQSUB8 __uqsub8
-#define __UHSUB8 __uhsub8
-#define __SADD16 __sadd16
-#define __QADD16 __qadd16
-#define __SHADD16 __shadd16
-#define __UADD16 __uadd16
-#define __UQADD16 __uqadd16
-#define __UHADD16 __uhadd16
-#define __SSUB16 __ssub16
-#define __QSUB16 __qsub16
-#define __SHSUB16 __shsub16
-#define __USUB16 __usub16
-#define __UQSUB16 __uqsub16
-#define __UHSUB16 __uhsub16
-#define __SASX __sasx
-#define __QASX __qasx
-#define __SHASX __shasx
-#define __UASX __uasx
-#define __UQASX __uqasx
-#define __UHASX __uhasx
-#define __SSAX __ssax
-#define __QSAX __qsax
-#define __SHSAX __shsax
-#define __USAX __usax
-#define __UQSAX __uqsax
-#define __UHSAX __uhsax
-#define __USAD8 __usad8
-#define __USADA8 __usada8
-#define __SSAT16 __ssat16
-#define __USAT16 __usat16
-#define __UXTB16 __uxtb16
-#define __UXTAB16 __uxtab16
-#define __SXTB16 __sxtb16
-#define __SXTAB16 __sxtab16
-#define __SMUAD __smuad
-#define __SMUADX __smuadx
-#define __SMLAD __smlad
-#define __SMLADX __smladx
-#define __SMLALD __smlald
-#define __SMLALDX __smlaldx
-#define __SMUSD __smusd
-#define __SMUSDX __smusdx
-#define __SMLSD __smlsd
-#define __SMLSDX __smlsdx
-#define __SMLSLD __smlsld
-#define __SMLSLDX __smlsldx
-#define __SEL __sel
-#define __QADD __qadd
-#define __QSUB __qsub
-
-#define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | \
-                                   ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL))
-
-#define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | \
-                                   ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL))
-
-#define __SMMLA(ARG1, ARG2, ARG3) ((int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                              ((int64_t)(ARG3) << 32)) >>  \
-                                             32))
-
-#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("sadd8 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("qadd8 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("shadd8 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("uadd8 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("uqadd8 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("uhadd8 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("ssub8 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("qsub8 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("shsub8 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("usub8 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("uqsub8 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("uhsub8 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("sadd16 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("qadd16 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("shadd16 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("uadd16 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("uqadd16 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("uhadd16 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("ssub16 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("qsub16 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("shsub16 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("usub16 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("uqsub16 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("uhsub16 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("sasx %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("qasx %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("shasx %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("uasx %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("uqasx %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("uhasx %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("ssax %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("qsax %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("shsax %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("usax %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("uqsax %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("uhsax %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("usad8 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile("usada8 %0, %1, %2, %3"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2), "r"(op3));
-    return (result);
-}
-
-#define __SSAT16(ARG1, ARG2)                 \
-    (                                        \
-        {                                    \
-            uint32_t __RES, __ARG1 = (ARG1); \
-            __ASM("ssat16 %0, %1, %2"        \
-                  : "=r"(__RES)              \
-                  : "I"(ARG2), "r"(__ARG1)); \
-            __RES;                           \
-        })
-
-#define __USAT16(ARG1, ARG2)                 \
-    (                                        \
-        {                                    \
-            uint32_t __RES, __ARG1 = (ARG1); \
-            __ASM("usat16 %0, %1, %2"        \
-                  : "=r"(__RES)              \
-                  : "I"(ARG2), "r"(__ARG1)); \
-            __RES;                           \
-        })
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-    uint32_t result;
-
-    __ASM volatile("uxtb16 %0, %1"
-                   : "=r"(result)
-                   : "r"(op1));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("uxtab16 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-    uint32_t result;
-
-    __ASM volatile("sxtb16 %0, %1"
-                   : "=r"(result)
-                   : "r"(op1));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("sxtab16 %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("smuad %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("smuadx %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile("smlad %0, %1, %2, %3"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2), "r"(op3));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile("smladx %0, %1, %2, %3"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2), "r"(op3));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u
-    {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__ // Little endian
-    __ASM volatile("smlald %0, %1, %2, %3"
-                   : "=r"(llr.w32[0]), "=r"(llr.w32[1])
-                   : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
-#else             // Big endian
-    __ASM volatile("smlald %0, %1, %2, %3"
-                   : "=r"(llr.w32[1]), "=r"(llr.w32[0])
-                   : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
-#endif
-
-    return (llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u
-    {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__ // Little endian
-    __ASM volatile("smlaldx %0, %1, %2, %3"
-                   : "=r"(llr.w32[0]), "=r"(llr.w32[1])
-                   : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
-#else             // Big endian
-    __ASM volatile("smlaldx %0, %1, %2, %3"
-                   : "=r"(llr.w32[1]), "=r"(llr.w32[0])
-                   : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
-#endif
-
-    return (llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("smusd %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("smusdx %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile("smlsd %0, %1, %2, %3"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2), "r"(op3));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile("smlsdx %0, %1, %2, %3"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2), "r"(op3));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u
-    {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__ // Little endian
-    __ASM volatile("smlsld %0, %1, %2, %3"
-                   : "=r"(llr.w32[0]), "=r"(llr.w32[1])
-                   : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
-#else             // Big endian
-    __ASM volatile("smlsld %0, %1, %2, %3"
-                   : "=r"(llr.w32[1]), "=r"(llr.w32[0])
-                   : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
-#endif
-
-    return (llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u
-    {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__ // Little endian
-    __ASM volatile("smlsldx %0, %1, %2, %3"
-                   : "=r"(llr.w32[0]), "=r"(llr.w32[1])
-                   : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
-#else             // Big endian
-    __ASM volatile("smlsldx %0, %1, %2, %3"
-                   : "=r"(llr.w32[1]), "=r"(llr.w32[0])
-                   : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
-#endif
-
-    return (llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("sel %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("qadd %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile("qsub %0, %1, %2"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2));
-    return (result);
-}
-
-#define __PKHBT(ARG1, ARG2, ARG3)                             \
-    (                                                         \
-        {                                                     \
-            uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-            __ASM("pkhbt %0, %1, %2, lsl %3"                  \
-                  : "=r"(__RES)                               \
-                  : "r"(__ARG1), "r"(__ARG2), "I"(ARG3));     \
-            __RES;                                            \
-        })
-
-#define __PKHTB(ARG1, ARG2, ARG3)                             \
-    (                                                         \
-        {                                                     \
-            uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-            if (ARG3 == 0)                                    \
-                __ASM("pkhtb %0, %1, %2"                      \
-                      : "=r"(__RES)                           \
-                      : "r"(__ARG1), "r"(__ARG2));            \
-            else                                              \
-                __ASM("pkhtb %0, %1, %2, asr %3"              \
-                      : "=r"(__RES)                           \
-                      : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \
-            __RES;                                            \
-        })
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3)
-{
-    int32_t result;
-
-    __ASM volatile("smmla %0, %1, %2, %3"
-                   : "=r"(result)
-                   : "r"(op1), "r"(op2), "r"(op3));
-    return (result);
-}
-
-#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include <cmsis_iar.h>
-
-#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include <cmsis_ccs.h>
-
-#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/* not yet supported */
-
-#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include <cmsis_csm.h>
-
-#endif
-
-    /*@} end of group CMSIS_SIMD_intrinsics */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CMSIMD_H */

bsp/swm320/libraries/CMSIS/DeviceSupport/SWM320.h

@@ -1,3117 +0,0 @@
-#ifndef __SWM320_H__
-#define __SWM320_H__
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-typedef enum IRQn
-{
-    /******  Cortex-M0 Processor Exceptions Numbers **********************************************/
-    NonMaskableInt_IRQn = -14,   /*!< 2 Non Maskable Interrupt                        */
-    MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt         */
-    BusFault_IRQn = -11,         /*!< 5 Cortex-M4 Bus Fault Interrupt                 */
-    UsageFault_IRQn = -10,       /*!< 6 Cortex-M4 Usage Fault Interrupt               */
-    SVCall_IRQn = -5,            /*!< 11 Cortex-M4 SV Call Interrupt                  */
-    DebugMonitor_IRQn = -4,      /*!< 12 Cortex-M4 Debug Monitor Interrupt            */
-    PendSV_IRQn = -2,            /*!< 14 Cortex-M4 Pend SV Interrupt                  */
-    SysTick_IRQn = -1,           /*!< 15 Cortex-M4 System Tick Interrupt              */
-
-    /******  Cortex-M4 specific Interrupt Numbers ************************************************/
-    GPIOA0_IRQn = 0,
-    GPIOA1_IRQn = 1,
-    GPIOA2_IRQn = 2,
-    GPIOA3_IRQn = 3,
-    GPIOA4_IRQn = 4,
-    GPIOA5_IRQn = 5,
-    GPIOA6_IRQn = 6,
-    GPIOA7_IRQn = 7,
-    GPIOB0_IRQn = 8,
-    GPIOB1_IRQn = 9,
-    GPIOB2_IRQn = 10,
-    GPIOB3_IRQn = 11,
-    GPIOB4_IRQn = 12,
-    GPIOB5_IRQn = 13,
-    GPIOB6_IRQn = 14,
-    GPIOB7_IRQn = 15,
-    GPIOC0_IRQn = 16,
-    GPIOC1_IRQn = 17,
-    GPIOC2_IRQn = 18,
-    GPIOC3_IRQn = 19,
-    GPIOC4_IRQn = 20,
-    GPIOC5_IRQn = 21,
-    GPIOC6_IRQn = 22,
-    GPIOC7_IRQn = 23,
-    GPIOM0_IRQn = 24,
-    GPIOM1_IRQn = 25,
-    GPIOM2_IRQn = 26,
-    GPIOM3_IRQn = 27,
-    GPIOM4_IRQn = 28,
-    GPIOM5_IRQn = 29,
-    GPIOM6_IRQn = 30,
-    GPIOM7_IRQn = 31,
-    DMA_IRQn = 32,
-    LCD_IRQn = 33,
-    NORFLC_IRQn = 34,
-    CAN_IRQn = 35,
-    PULSE_IRQn = 36,
-    WDT_IRQn = 37,
-    PWM_IRQn = 38,
-    UART0_IRQn = 39,
-    UART1_IRQn = 40,
-    UART2_IRQn = 41,
-    UART3_IRQn = 42,
-    UART4_IRQn = 43,
-    I2C0_IRQn = 44,
-    I2C1_IRQn = 45,
-    SPI0_IRQn = 46,
-    ADC0_IRQn = 47,
-    RTC_IRQn = 48,
-    BOD_IRQn = 49,
-    SDIO_IRQn = 50,
-    GPIOA_IRQn = 51,
-    GPIOB_IRQn = 52,
-    GPIOC_IRQn = 53,
-    GPIOM_IRQn = 54,
-    GPION_IRQn = 55,
-    GPIOP_IRQn = 56,
-    ADC1_IRQn = 57,
-    FPU_IRQn = 58,
-    SPI1_IRQn = 59,
-    TIMR0_IRQn = 60,
-    TIMR1_IRQn = 61,
-    TIMR2_IRQn = 62,
-    TIMR3_IRQn = 63,
-    TIMR4_IRQn = 64,
-    TIMR5_IRQn = 65,
-} IRQn_Type;
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M0 Processor and Core Peripherals */
-#define __CM4_REV 0x0001         /*!< Core revision r0p1                            */
-#define __MPU_PRESENT 1          /*!< SWM320 provides an MPU                       */
-#define __NVIC_PRIO_BITS 3       /*!< SWM320 uses 3 Bits for the Priority Levels   */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT 0          /*!< FPU present                                   */
-
-#if defined(__CC_ARM)
-#pragma anon_unions
-#endif
-
-#include <stdio.h>
-#include "core_cm4.h" /* Cortex-M0 processor and core peripherals            */
-#include "system_SWM320.h"
-
-/******************************************************************************/
-/*              Device Specific Peripheral registers structures          */
-/******************************************************************************/
-typedef struct
-{
-    __IO uint32_t CLKSEL; //Clock Select
-
-    __IO uint32_t CLKDIV;
-
-    __IO uint32_t CLKEN; //Clock Enable
-
-    __IO uint32_t SLEEP;
-
-    uint32_t RESERVED0[6];
-
-    __IO uint32_t RTCBKP_ISO; //[0] 1 RTC备份电源域处于隔离状态    0 RTC备份电源域可访问
-
-    __IO uint32_t RTCWKEN; //[0] 1 使能RTC唤醒功能
-
-    uint32_t RESERVED[52 + 64];
-
-    __IO uint32_t PAWKEN; //Port A Wakeup Enable
-    __IO uint32_t PBWKEN;
-    __IO uint32_t PCWKEN;
-
-    uint32_t RESERVED2[1 + 4];
-
-    __IO uint32_t PAWKSR; //Port A Wakeup Status Register，写1清零
-    __IO uint32_t PBWKSR;
-    __IO uint32_t PCWKSR;
-
-    uint32_t RESERVED3[64 - 10];
-
-    __IO uint32_t RSTCR; //Reset Control Register
-    __IO uint32_t RSTSR; //Reset Status Register
-
-    uint32_t RESERVED4[61 + 64];
-
-    __IO uint32_t BKP[3]; //数据备份寄存器
-
-    //RTC Power Domain: 0x4001E000
-    uint32_t RESERVED5[(0x4001E000 - 0x40000508) / 4 - 1];
-
-    __IO uint32_t RTCBKP[8]; //RTC电源域数据备份寄存器
-
-    __IO uint32_t LRCCR;    //Low speed RC Control Register
-    __IO uint32_t LRCTRIM0; //Low speed RC Trim
-    __IO uint32_t LRCTRIM1;
-
-    uint32_t RESERVED6;
-
-    __IO uint32_t RTCLDOTRIM; //RTC Power Domain LDO Trim
-
-    //Analog Control: 0x40031000
-    uint32_t RESERVED7[(0x40031000 - 0x4001E030) / 4 - 1];
-
-    __IO uint32_t HRCCR; //High speed RC Control Register
-
-    uint32_t RESERVED8[7];
-
-    __IO uint32_t XTALCR;
-
-    __IO uint32_t PLLCR;
-    __IO uint32_t PLLDIV;
-    __IO uint32_t PLLSET;
-    __IO uint32_t PLLLOCK; //[0] 1 PLL已锁定
-
-    __IO uint32_t BODIE;
-    __IO uint32_t BODIF;
-
-    __IO uint32_t ADC1IN7;
-} SYS_TypeDef;
-
-#define SYS_CLKSEL_LFCK_Pos 0 //Low Frequency Clock Source  0 LRC   1 PLL
-#define SYS_CLKSEL_LFCK_Msk (0x01 << SYS_CLKSEL_LFCK_Pos)
-#define SYS_CLKSEL_HFCK_Pos 1 //High Frequency Clock Source 0 HRC   1 XTAL
-#define SYS_CLKSEL_HFCK_Msk (0x01 << SYS_CLKSEL_HFCK_Pos)
-#define SYS_CLKSEL_SYS_Pos 2 //系统时钟选择   0 LFCK  1 HFCK
-#define SYS_CLKSEL_SYS_Msk (0x01 << SYS_CLKSEL_SYS_Pos)
-
-#define SYS_CLKDIV_SYS_Pos 0 //系统时钟分频  0 1分频    1 2分频
-#define SYS_CLKDIV_SYS_Msk (0x01 << SYS_CLKDIV_SYS_Pos)
-#define SYS_CLKDIV_PWM_Pos 1 //PWM 时钟分频  0 1分频    1 8分频
-#define SYS_CLKDIV_PWM_Msk (0x01 << SYS_CLKDIV_PWM_Pos)
-#define SYS_CLKDIV_SDRAM_Pos 2 //SDRAM时钟分频 0 1分频    1 2分频    2 4分频
-#define SYS_CLKDIV_SDRAM_Msk (0x03 << SYS_CLKDIV_SDRAM_Pos)
-#define SYS_CLKDIV_SDIO_Pos 4 //SDIO时钟分频  0 1分频    1 2分频    2 4分频     3 8分频
-#define SYS_CLKDIV_SDIO_Msk (0x03 << SYS_CLKDIV_SDIO_Pos)
-
-#define SYS_CLKEN_GPIOA_Pos 0
-#define SYS_CLKEN_GPIOA_Msk (0x01 << SYS_CLKEN_GPIOA_Pos)
-#define SYS_CLKEN_GPIOB_Pos 1
-#define SYS_CLKEN_GPIOB_Msk (0x01 << SYS_CLKEN_GPIOB_Pos)
-#define SYS_CLKEN_GPIOC_Pos 2
-#define SYS_CLKEN_GPIOC_Msk (0x01 << SYS_CLKEN_GPIOC_Pos)
-#define SYS_CLKEN_GPIOM_Pos 4
-#define SYS_CLKEN_GPIOM_Msk (0x01 << SYS_CLKEN_GPIOM_Pos)
-#define SYS_CLKEN_GPION_Pos 5
-#define SYS_CLKEN_GPION_Msk (0x01 << SYS_CLKEN_GPION_Pos)
-#define SYS_CLKEN_TIMR_Pos 6
-#define SYS_CLKEN_TIMR_Msk (0x01 << SYS_CLKEN_TIMR_Pos)
-#define SYS_CLKEN_WDT_Pos 7
-#define SYS_CLKEN_WDT_Msk (0x01 << SYS_CLKEN_WDT_Pos)
-#define SYS_CLKEN_ADC0_Pos 8
-#define SYS_CLKEN_ADC0_Msk (0x01 << SYS_CLKEN_ADC0_Pos)
-#define SYS_CLKEN_PWM_Pos 9
-#define SYS_CLKEN_PWM_Msk (0x01 << SYS_CLKEN_PWM_Pos)
-#define SYS_CLKEN_RTC_Pos 10
-#define SYS_CLKEN_RTC_Msk (0x01 << SYS_CLKEN_RTC_Pos)
-#define SYS_CLKEN_UART0_Pos 11
-#define SYS_CLKEN_UART0_Msk (0x01 << SYS_CLKEN_UART0_Pos)
-#define SYS_CLKEN_UART1_Pos 12
-#define SYS_CLKEN_UART1_Msk (0x01 << SYS_CLKEN_UART1_Pos)
-#define SYS_CLKEN_UART2_Pos 13
-#define SYS_CLKEN_UART2_Msk (0x01 << SYS_CLKEN_UART2_Pos)
-#define SYS_CLKEN_UART3_Pos 14
-#define SYS_CLKEN_UART3_Msk (0x01 << SYS_CLKEN_UART3_Pos)
-#define SYS_CLKEN_UART4_Pos 15
-#define SYS_CLKEN_UART4_Msk (0x01 << SYS_CLKEN_UART4_Pos)
-#define SYS_CLKEN_SPI0_Pos 16
-#define SYS_CLKEN_SPI0_Msk (0x01 << SYS_CLKEN_SPI0_Pos)
-#define SYS_CLKEN_I2C0_Pos 17
-#define SYS_CLKEN_I2C0_Msk (0x01 << SYS_CLKEN_I2C0_Pos)
-#define SYS_CLKEN_I2C1_Pos 18
-#define SYS_CLKEN_I2C1_Msk (0x01 << SYS_CLKEN_I2C1_Pos)
-#define SYS_CLKEN_I2C2_Pos 19
-#define SYS_CLKEN_I2C2_Msk (0x01 << SYS_CLKEN_I2C2_Pos)
-#define SYS_CLKEN_LCD_Pos 20
-#define SYS_CLKEN_LCD_Msk (0x01 << SYS_CLKEN_LCD_Pos)
-#define SYS_CLKEN_GPIOP_Pos 21
-#define SYS_CLKEN_GPIOP_Msk (0x01 << SYS_CLKEN_GPIOP_Pos)
-#define SYS_CLKEN_ANAC_Pos 22 //模拟控制单元时钟使能
-#define SYS_CLKEN_ANAC_Msk (0x01 << SYS_CLKEN_ANAC_Pos)
-#define SYS_CLKEN_CRC_Pos 23
-#define SYS_CLKEN_CRC_Msk (0x01 << SYS_CLKEN_CRC_Pos)
-#define SYS_CLKEN_RTCBKP_Pos 24
-#define SYS_CLKEN_RTCBKP_Msk (0x01 << SYS_CLKEN_RTCBKP_Pos)
-#define SYS_CLKEN_CAN_Pos 25
-#define SYS_CLKEN_CAN_Msk (0x01 << SYS_CLKEN_CAN_Pos)
-#define SYS_CLKEN_SDRAM_Pos 26
-#define SYS_CLKEN_SDRAM_Msk (0x01 << SYS_CLKEN_SDRAM_Pos)
-#define SYS_CLKEN_NORFL_Pos 27 //NOR Flash
-#define SYS_CLKEN_NORFL_Msk (0x01 << SYS_CLKEN_NORFL_Pos)
-#define SYS_CLKEN_RAMC_Pos 28
-#define SYS_CLKEN_RAMC_Msk (0x01 << SYS_CLKEN_RAMC_Pos)
-#define SYS_CLKEN_SDIO_Pos 29
-#define SYS_CLKEN_SDIO_Msk (0x01 << SYS_CLKEN_SDIO_Pos)
-#define SYS_CLKEN_ADC1_Pos 30
-#define SYS_CLKEN_ADC1_Msk (0x01 << SYS_CLKEN_ADC1_Pos)
-#define SYS_CLKEN_ALIVE_Pos 31 //CHIPALIVE电源域系统时钟使能
-#define SYS_CLKEN_ALIVE_Msk (0x01 << SYS_CLKEN_ALIVE_Pos)
-
-#define SYS_SLEEP_SLEEP_Pos 0 //将该位置1后，系统将进入SLEEP模式
-#define SYS_SLEEP_SLEEP_Msk (0x01 << SYS_SLEEP_SLEEP_Pos)
-#define SYS_SLEEP_DEEP_Pos 1 //将该位置1后，系统将进入STOP SLEEP模式
-#define SYS_SLEEP_DEEP_Msk (0x01 << SYS_SLEEP_DEEP_Pos)
-
-#define SYS_RSTCR_SYS_Pos 0 //写1进行系统复位，硬件自动清零
-#define SYS_RSTCR_SYS_Msk (0x01 << SYS_RSTCR_SYS_Pos)
-#define SYS_RSTCR_FLASH_Pos 1 //写1对FLASH控制器进行一次复位，硬件自动清零
-#define SYS_RSTCR_FLASH_Msk (0x01 << SYS_RSTCR_FLASH_Pos)
-#define SYS_RSTCR_PWM_Pos 2 //写1对PWM进行一次复位，硬件自动清零
-#define SYS_RSTCR_PWM_Msk (0x01 << SYS_RSTCR_PWM_Pos)
-#define SYS_RSTCR_CPU_Pos 3 //写1对CPU进行一次复位，硬件自动清零
-#define SYS_RSTCR_CPU_Msk (0x01 << SYS_RSTCR_CPU_Pos)
-#define SYS_RSTCR_DMA_Pos 4 //写1对DMA进行一次复位，硬件自动清零
-#define SYS_RSTCR_DMA_Msk (0x01 << SYS_RSTCR_DMA_Pos)
-#define SYS_RSTCR_NORFLASH_Pos 5 //写1对NOR Flash控制器进行一次复位，硬件自动清零
-#define SYS_RSTCR_NORFLASH_Msk (0x01 << SYS_RSTCR_NORFLASH_Pos)
-#define SYS_RSTCR_SRAM_Pos 6 //写1对SRAM控制器进行一次复位，硬件自动清零
-#define SYS_RSTCR_SRAM_Msk (0x01 << SYS_RSTCR_SRAM_Pos)
-#define SYS_RSTCR_SDRAM_Pos 7 //写1对SDRAM控制器进行一次复位，硬件自动清零
-#define SYS_RSTCR_SDRAM_Msk (0x01 << SYS_RSTCR_SDRAM_Pos)
-#define SYS_RSTCR_SDIO_Pos 8 //写1对SDIO进行一次复位，硬件自动清零
-#define SYS_RSTCR_SDIO_Msk (0x01 << SYS_RSTCR_SDIO_Pos)
-#define SYS_RSTCR_LCD_Pos 9 //写1对LCD进行一次复位，硬件自动清零
-#define SYS_RSTCR_LCD_Msk (0x01 << SYS_RSTCR_LCD_Pos)
-#define SYS_RSTCR_CAN_Pos 10 //写1对CAN进行一次复位，硬件自动清零
-#define SYS_RSTCR_CAN_Msk (0x01 << SYS_RSTCR_CAN_Pos)
-
-#define SYS_RSTSR_POR_Pos 0 //1 出现过POR复位，写1清零
-#define SYS_RSTSR_POR_Msk (0x01 << SYS_RSTSR_POR_Pos)
-#define SYS_RSTSR_BOD_Pos 1 //1 出现过BOD复位，写1清零
-#define SYS_RSTSR_BOD_Msk (0x01 << SYS_RSTSR_BOD_Pos)
-#define SYS_RSTSR_PIN_Pos 2 //1 出现过外部引脚复位，写1清零
-#define SYS_RSTSR_PIN_Msk (0x01 << SYS_RSTSR_PIN_Pos)
-#define SYS_RSTSR_WDT_Pos 3 //1 出现过WDT复位，写1清零
-#define SYS_RSTSR_WDT_Msk (0x01 << SYS_RSTSR_WDT_Pos)
-#define SYS_RSTSR_SWRST_Pos 4 //Software Reset, 1 出现过软件复位，写1清零
-#define SYS_RSTSR_SWRST_Msk (0x01 << SYS_RSTSR_SWRST_Pos)
-
-#define SYS_LRCCR_OFF_Pos 0 //Low Speed RC Off
-#define SYS_LRCCR_OFF_Msk (0x01 << SYS_LRCCR_OFF_Pos)
-
-#define SYS_LRCTRIM0_R_Pos 0 //LRC粗调控制位
-#define SYS_LRCTRIM0_R_Msk (0x7FFF << SYS_LRCTRIM0_R_Pos)
-#define SYS_LRCTRIM0_M_Pos 15 //LRC中调控制位
-#define SYS_LRCTRIM0_M_Msk (0x3F << SYS_LRCTRIM2_M_Pos)
-#define SYS_LRCTRIM0_F_Pos 21 //LRC细调控制位
-#define SYS_LRCTRIM0_F_Msk (0x7FF << SYS_LRCTRIM0_F_Pos)
-
-#define SYS_LRCTRIM1_U_Pos 0 //LRC U调控制位
-#define SYS_LRCTRIM1_U_Msk (0x7FFF << SYS_LRCTRIM1_U_Pos)
-
-#define SYS_HRCCR_DBL_Pos 0 //Double Frequency  0 20MHz 1 40MHz
-#define SYS_HRCCR_DBL_Msk (0x01 << SYS_HRCCR_DBL_Pos)
-#define SYS_HRCCR_OFF_Pos 1 //High speed RC Off
-#define SYS_HRCCR_OFF_Msk (0x01 << SYS_HRCCR_OFF_Pos)
-
-#define SYS_XTALCR_EN_Pos 0
-#define SYS_XTALCR_EN_Msk (0x01 << SYS_XTALCR_EN_Pos)
-
-#define SYS_PLLCR_OUTEN_Pos 0 //只能LOCK后设置
-#define SYS_PLLCR_OUTEN_Msk (0x01 << SYS_PLLCR_OUTEN_Pos)
-#define SYS_PLLCR_INSEL_Pos 1 //0 XTAL    1 HRC
-#define SYS_PLLCR_INSEL_Msk (0x01 << SYS_PLLCR_INSEL_Pos)
-#define SYS_PLLCR_OFF_Pos 2
-#define SYS_PLLCR_OFF_Msk (0x01 << SYS_PLLCR_OFF_Pos)
-
-#define SYS_PLLDIV_FBDIV_Pos 0 /*   PLL FeedBack分频寄存器                           \
-                                    VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV \
-                                    PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV   */
-#define SYS_PLLDIV_FBDIV_Msk (0x1FF << SYS_PLLDIV_FBDIV_Pos)
-#define SYS_PLLDIV_ADDIV_Pos 9 //ADC时钟基（即VCO输出分频后的时钟）经ADDIV分频后作为ADC的转换时钟
-#define SYS_PLLDIV_ADDIV_Msk (0x1F << SYS_PLLDIV_ADDIV_Pos)
-#define SYS_PLLDIV_ADVCO_Pos 14 //0 VCO输出16分频作为ADC时钟基    1 VCO输出经过32分频作为ADC时钟基    2 VCO输出经过64分频作为ADC时钟基
-#define SYS_PLLDIV_ADVCO_Msk (0x03 << SYS_PLLDIV_ADVCO_Pos)
-#define SYS_PLLDIV_INDIV_Pos 16 //PLL 输入源时钟分频
-#define SYS_PLLDIV_INDIV_Msk (0x1F << SYS_PLLDIV_INDIV_Pos)
-#define SYS_PLLDIV_OUTDIV_Pos 24 //PLL 输出分频，0 8分频    1 4分频    0 2分频
-#define SYS_PLLDIV_OUTDIV_Msk (0x03 << SYS_PLLDIV_OUTDIV_Pos)
-
-#define SYS_PLLSET_LPFBW_Pos 0 //PLL Low Pass Filter Bandwidth
-#define SYS_PLLSET_LPFBW_Msk (0x0F << SYS_PLLSET_LPFBW_Pos)
-#define SYS_PLLSET_BIASADJ_Pos 4 //PLL Current Bias Adjustment
-#define SYS_PLLSET_BIASADJ_Msk (0x03 << SYS_PLLSET_BIASADJ_Pos)
-#define SYS_PLLSET_REFVSEL_Pos 6 //PLL Reference Voltage Select
-#define SYS_PLLSET_REFVSEL_Msk (0x03 << SYS_PLLSET_REFVSEL_Pos)
-#define SYS_PLLSET_CHPADJL_Pos 8 //PLL charge pump LSB current Adjustment
-#define SYS_PLLSET_CHPADJL_Msk (0x07 << SYS_PLLSET_CHPADJL_Pos)
-#define SYS_PLLSET_CHPADJM_Pos 11 //PLL charge pump MSB current Adjustment
-#define SYS_PLLSET_CHPADJM_Msk (0x03 << SYS_PLLSET_CHPADJM_Pos)
-
-#define SYS_BODIE_2V2_Pos 1 //BOD 2.2V等级触发中断使能
-#define SYS_BODIE_2V2_Msk (0x01 << SYS_BODIE_2V2_Pos)
-
-#define SYS_BODIF_2V2_Pos 1 //BOD 2.2V等级触发中断状态，写1清零
-#define SYS_BODIF_2V2_Msk (0x01 << SYS_BODIF_2V2_Pos)
-
-#define SYS_ADC1IN7_SEL_Pos 0 //ADC1模块模拟通道7，1 温度传感器    2 电池电压    3 RTC电源域BG    4 主电源域BG   5 PDM33
-#define SYS_ADC1IN7_SEL_Msk (0x0F << SYS_ADC1IN7_SEL_Pos)
-#define SYS_ADC1IN7_IOON_Pos 4 //ADC1模块模拟通道7所用IO开关
-#define SYS_ADC1IN7_IOON_Msk (0x01 << SYS_ADC1IN7_IOON_Pos)
-
-typedef struct
-{
-    __IO uint32_t PORTA_SEL; /*给PORTA_SEL[2n+2:2n]赋相应的值，将PORTA.PINn引脚配置成GPIO、模拟、数字等功能
-                             当赋值为PORTA_PINn_FUNMUX时，PORTA.PINn引脚可通过PORTA_MUX寄存器连接到各种数字外设 */
-    __IO uint32_t PORTB_SEL;
-
-    __IO uint32_t PORTC_SEL;
-
-    uint32_t RESERVED[5];
-
-    __IO uint32_t PORTM_SEL0;
-
-    __IO uint32_t PORTM_SEL1;
-
-    uint32_t RESERVED2[2];
-
-    __IO uint32_t PORTN_SEL0;
-
-    __IO uint32_t PORTN_SEL1;
-
-    uint32_t RESERVED3[2];
-
-    __IO uint32_t PORTP_SEL0;
-
-    __IO uint32_t PORTP_SEL1;
-
-    uint32_t RESERVED4[46];
-
-    __IO uint32_t PORTA_MUX0;
-
-    __IO uint32_t PORTA_MUX1;
-
-    uint32_t RESERVED5[2];
-
-    __IO uint32_t PORTB_MUX0;
-
-    __IO uint32_t PORTB_MUX1;
-
-    uint32_t RESERVED6[2];
-
-    __IO uint32_t PORTC_MUX0;
-
-    __IO uint32_t PORTC_MUX1;
-
-    uint32_t RESERVED7[14];
-
-    __IO uint32_t PORTM_MUX0;
-
-    __IO uint32_t PORTM_MUX1;
-
-    __IO uint32_t PORTM_MUX2;
-
-    __IO uint32_t PORTM_MUX3;
-
-    __IO uint32_t PORTN_MUX0;
-
-    __IO uint32_t PORTN_MUX1;
-
-    __IO uint32_t PORTN_MUX2;
-
-    uint32_t RESERVED8;
-
-    __IO uint32_t PORTP_MUX0;
-
-    __IO uint32_t PORTP_MUX1;
-
-    __IO uint32_t PORTP_MUX2;
-
-    __IO uint32_t PORTP_MUX3;
-
-    uint32_t RESERVED9[28];
-
-    __IO uint32_t PORTA_PULLU; //上拉使能
-
-    uint32_t RESERVED10[3];
-
-    __IO uint32_t PORTC_PULLU;
-
-    uint32_t RESERVED11[3];
-
-    __IO uint32_t PORTM_PULLU;
-
-    uint32_t RESERVED12[3];
-
-    __IO uint32_t PORTP_PULLU;
-
-    uint32_t RESERVED13[51];
-
-    __IO uint32_t PORTB_PULLD; //下拉使能
-
-    uint32_t RESERVED14[3];
-
-    __IO uint32_t PORTD_PULLD;
-
-    uint32_t RESERVED15[3];
-
-    __IO uint32_t PORTN_PULLD;
-
-    uint32_t RESERVED16[135];
-
-    __IO uint32_t PORTM_DRIVS; //驱动强度
-
-    uint32_t RESERVED17[3];
-
-    __IO uint32_t PORTN_DRIVS;
-
-    uint32_t RESERVED18[3];
-
-    __IO uint32_t PORTP_DRIVS;
-
-    uint32_t RESERVED19[39];
-
-    __IO uint32_t PORTA_INEN; //输入使能
-
-    uint32_t RESERVED20[3];
-
-    __IO uint32_t PORTB_INEN;
-
-    uint32_t RESERVED21[3];
-
-    __IO uint32_t PORTC_INEN;
-
-    uint32_t RESERVED22[7];
-
-    __IO uint32_t PORTM_INEN;
-
-    uint32_t RESERVED23[3];
-
-    __IO uint32_t PORTN_INEN;
-
-    uint32_t RESERVED24[3];
-
-    __IO uint32_t PORTP_INEN;
-} PORT_TypeDef;
-
-#define PORT_PORTA_PULLU_PIN0_Pos 0
-#define PORT_PORTA_PULLU_PIN0_Msk (0x01 << PORT_PORTA_PULLU_PIN0_Pos)
-#define PORT_PORTA_PULLU_PIN1_Pos 1
-#define PORT_PORTA_PULLU_PIN1_Msk (0x01 << PORT_PORTA_PULLU_PIN1_Pos)
-#define PORT_PORTA_PULLU_PIN2_Pos 2
-#define PORT_PORTA_PULLU_PIN2_Msk (0x01 << PORT_PORTA_PULLU_PIN2_Pos)
-#define PORT_PORTA_PULLU_PIN3_Pos 3
-#define PORT_PORTA_PULLU_PIN3_Msk (0x01 << PORT_PORTA_PULLU_PIN3_Pos)
-#define PORT_PORTA_PULLU_PIN4_Pos 4
-#define PORT_PORTA_PULLU_PIN4_Msk (0x01 << PORT_PORTA_PULLU_PIN4_Pos)
-#define PORT_PORTA_PULLU_PIN5_Pos 5
-#define PORT_PORTA_PULLU_PIN5_Msk (0x01 << PORT_PORTA_PULLU_PIN5_Pos)
-#define PORT_PORTA_PULLU_PIN6_Pos 6
-#define PORT_PORTA_PULLU_PIN6_Msk (0x01 << PORT_PORTA_PULLU_PIN6_Pos)
-#define PORT_PORTA_PULLU_PIN7_Pos 7
-#define PORT_PORTA_PULLU_PIN7_Msk (0x01 << PORT_PORTA_PULLU_PIN7_Pos)
-#define PORT_PORTA_PULLU_PIN8_Pos 8
-#define PORT_PORTA_PULLU_PIN8_Msk (0x01 << PORT_PORTA_PULLU_PIN8_Pos)
-#define PORT_PORTA_PULLU_PIN9_Pos 9
-#define PORT_PORTA_PULLU_PIN9_Msk (0x01 << PORT_PORTA_PULLU_PIN9_Pos)
-#define PORT_PORTA_PULLU_PIN10_Pos 10
-#define PORT_PORTA_PULLU_PIN10_Msk (0x01 << PORT_PORTA_PULLU_PIN10_Pos)
-#define PORT_PORTA_PULLU_PIN11_Pos 11
-#define PORT_PORTA_PULLU_PIN11_Msk (0x01 << PORT_PORTA_PULLU_PIN11_Pos)
-#define PORT_PORTA_PULLU_PIN12_Pos 12
-#define PORT_PORTA_PULLU_PIN12_Msk (0x01 << PORT_PORTA_PULLU_PIN12_Pos)
-#define PORT_PORTA_PULLU_PIN13_Pos 13
-#define PORT_PORTA_PULLU_PIN13_Msk (0x01 << PORT_PORTA_PULLU_PIN13_Pos)
-#define PORT_PORTA_PULLU_PIN14_Pos 14
-#define PORT_PORTA_PULLU_PIN14_Msk (0x01 << PORT_PORTA_PULLU_PIN14_Pos)
-#define PORT_PORTA_PULLU_PIN15_Pos 15
-#define PORT_PORTA_PULLU_PIN15_Msk (0x01 << PORT_PORTA_PULLU_PIN15_Pos)
-
-#define PORT_PORTC_PULLU_PIN0_Pos 0
-#define PORT_PORTC_PULLU_PIN0_Msk (0x01 << PORT_PORTC_PULLU_PIN0_Pos)
-#define PORT_PORTC_PULLU_PIN1_Pos 1
-#define PORT_PORTC_PULLU_PIN1_Msk (0x01 << PORT_PORTC_PULLU_PIN1_Pos)
-#define PORT_PORTC_PULLU_PIN2_Pos 2
-#define PORT_PORTC_PULLU_PIN2_Msk (0x01 << PORT_PORTC_PULLU_PIN2_Pos)
-#define PORT_PORTC_PULLU_PIN3_Pos 3
-#define PORT_PORTC_PULLU_PIN3_Msk (0x01 << PORT_PORTC_PULLU_PIN3_Pos)
-#define PORT_PORTC_PULLU_PIN4_Pos 4
-#define PORT_PORTC_PULLU_PIN4_Msk (0x01 << PORT_PORTC_PULLU_PIN4_Pos)
-#define PORT_PORTC_PULLU_PIN5_Pos 5
-#define PORT_PORTC_PULLU_PIN5_Msk (0x01 << PORT_PORTC_PULLU_PIN5_Pos)
-#define PORT_PORTC_PULLU_PIN6_Pos 6
-#define PORT_PORTC_PULLU_PIN6_Msk (0x01 << PORT_PORTC_PULLU_PIN6_Pos)
-#define PORT_PORTC_PULLU_PIN7_Pos 7
-#define PORT_PORTC_PULLU_PIN7_Msk (0x01 << PORT_PORTC_PULLU_PIN7_Pos)
-#define PORT_PORTC_PULLU_PIN8_Pos 8
-#define PORT_PORTC_PULLU_PIN8_Msk (0x01 << PORT_PORTC_PULLU_PIN8_Pos)
-#define PORT_PORTC_PULLU_PIN9_Pos 9
-#define PORT_PORTC_PULLU_PIN9_Msk (0x01 << PORT_PORTC_PULLU_PIN9_Pos)
-#define PORT_PORTC_PULLU_PIN10_Pos 10
-#define PORT_PORTC_PULLU_PIN10_Msk (0x01 << PORT_PORTC_PULLU_PIN10_Pos)
-#define PORT_PORTC_PULLU_PIN11_Pos 11
-#define PORT_PORTC_PULLU_PIN11_Msk (0x01 << PORT_PORTC_PULLU_PIN11_Pos)
-#define PORT_PORTC_PULLU_PIN12_Pos 12
-#define PORT_PORTC_PULLU_PIN12_Msk (0x01 << PORT_PORTC_PULLU_PIN12_Pos)
-#define PORT_PORTC_PULLU_PIN13_Pos 13
-#define PORT_PORTC_PULLU_PIN13_Msk (0x01 << PORT_PORTC_PULLU_PIN13_Pos)
-#define PORT_PORTC_PULLU_PIN14_Pos 14
-#define PORT_PORTC_PULLU_PIN14_Msk (0x01 << PORT_PORTC_PULLU_PIN14_Pos)
-#define PORT_PORTC_PULLU_PIN15_Pos 15
-#define PORT_PORTC_PULLU_PIN15_Msk (0x01 << PORT_PORTC_PULLU_PIN15_Pos)
-
-#define PORT_PORTM_PULLU_PIN0_Pos 0
-#define PORT_PORTM_PULLU_PIN0_Msk (0x01 << PORT_PORTM_PULLU_PIN0_Pos)
-#define PORT_PORTM_PULLU_PIN1_Pos 1
-#define PORT_PORTM_PULLU_PIN1_Msk (0x01 << PORT_PORTM_PULLU_PIN1_Pos)
-#define PORT_PORTM_PULLU_PIN2_Pos 2
-#define PORT_PORTM_PULLU_PIN2_Msk (0x01 << PORT_PORTM_PULLU_PIN2_Pos)
-#define PORT_PORTM_PULLU_PIN3_Pos 3
-#define PORT_PORTM_PULLU_PIN3_Msk (0x01 << PORT_PORTM_PULLU_PIN3_Pos)
-#define PORT_PORTM_PULLU_PIN4_Pos 4
-#define PORT_PORTM_PULLU_PIN4_Msk (0x01 << PORT_PORTM_PULLU_PIN4_Pos)
-#define PORT_PORTM_PULLU_PIN5_Pos 5
-#define PORT_PORTM_PULLU_PIN5_Msk (0x01 << PORT_PORTM_PULLU_PIN5_Pos)
-#define PORT_PORTM_PULLU_PIN6_Pos 6
-#define PORT_PORTM_PULLU_PIN6_Msk (0x01 << PORT_PORTM_PULLU_PIN6_Pos)
-#define PORT_PORTM_PULLU_PIN7_Pos 7
-#define PORT_PORTM_PULLU_PIN7_Msk (0x01 << PORT_PORTM_PULLU_PIN7_Pos)
-#define PORT_PORTM_PULLU_PIN8_Pos 8
-#define PORT_PORTM_PULLU_PIN8_Msk (0x01 << PORT_PORTM_PULLU_PIN8_Pos)
-#define PORT_PORTM_PULLU_PIN9_Pos 9
-#define PORT_PORTM_PULLU_PIN9_Msk (0x01 << PORT_PORTM_PULLU_PIN9_Pos)
-#define PORT_PORTM_PULLU_PIN10_Pos 10
-#define PORT_PORTM_PULLU_PIN10_Msk (0x01 << PORT_PORTM_PULLU_PIN10_Pos)
-#define PORT_PORTM_PULLU_PIN11_Pos 11
-#define PORT_PORTM_PULLU_PIN11_Msk (0x01 << PORT_PORTM_PULLU_PIN11_Pos)
-#define PORT_PORTM_PULLU_PIN12_Pos 12
-#define PORT_PORTM_PULLU_PIN12_Msk (0x01 << PORT_PORTM_PULLU_PIN12_Pos)
-#define PORT_PORTM_PULLU_PIN13_Pos 13
-#define PORT_PORTM_PULLU_PIN13_Msk (0x01 << PORT_PORTM_PULLU_PIN13_Pos)
-#define PORT_PORTM_PULLU_PIN14_Pos 14
-#define PORT_PORTM_PULLU_PIN14_Msk (0x01 << PORT_PORTM_PULLU_PIN14_Pos)
-#define PORT_PORTM_PULLU_PIN15_Pos 15
-#define PORT_PORTM_PULLU_PIN15_Msk (0x01 << PORT_PORTM_PULLU_PIN15_Pos)
-#define PORT_PORTM_PULLU_PIN16_Pos 16
-#define PORT_PORTM_PULLU_PIN16_Msk (0x01 << PORT_PORTM_PULLU_PIN16_Pos)
-#define PORT_PORTM_PULLU_PIN17_Pos 17
-#define PORT_PORTM_PULLU_PIN17_Msk (0x01 << PORT_PORTM_PULLU_PIN17_Pos)
-#define PORT_PORTM_PULLU_PIN18_Pos 18
-#define PORT_PORTM_PULLU_PIN18_Msk (0x01 << PORT_PORTM_PULLU_PIN18_Pos)
-#define PORT_PORTM_PULLU_PIN19_Pos 19
-#define PORT_PORTM_PULLU_PIN19_Msk (0x01 << PORT_PORTM_PULLU_PIN19_Pos)
-#define PORT_PORTM_PULLU_PIN20_Pos 20
-#define PORT_PORTM_PULLU_PIN20_Msk (0x01 << PORT_PORTM_PULLU_PIN20_Pos)
-#define PORT_PORTM_PULLU_PIN21_Pos 21
-#define PORT_PORTM_PULLU_PIN21_Msk (0x01 << PORT_PORTM_PULLU_PIN21_Pos)
-#define PORT_PORTM_PULLU_PIN22_Pos 22
-#define PORT_PORTM_PULLU_PIN22_Msk (0x01 << PORT_PORTM_PULLU_PIN22_Pos)
-#define PORT_PORTM_PULLU_PIN23_Pos 23
-#define PORT_PORTM_PULLU_PIN23_Msk (0x01 << PORT_PORTM_PULLU_PIN23_Pos)
-
-#define PORT_PORTP_PULLU_PIN0_Pos 0
-#define PORT_PORTP_PULLU_PIN0_Msk (0x01 << PORT_PORTP_PULLU_PIN0_Pos)
-#define PORT_PORTP_PULLU_PIN1_Pos 1
-#define PORT_PORTP_PULLU_PIN1_Msk (0x01 << PORT_PORTP_PULLU_PIN1_Pos)
-#define PORT_PORTP_PULLU_PIN2_Pos 2
-#define PORT_PORTP_PULLU_PIN2_Msk (0x01 << PORT_PORTP_PULLU_PIN2_Pos)
-#define PORT_PORTP_PULLU_PIN3_Pos 3
-#define PORT_PORTP_PULLU_PIN3_Msk (0x01 << PORT_PORTP_PULLU_PIN3_Pos)
-#define PORT_PORTP_PULLU_PIN4_Pos 4
-#define PORT_PORTP_PULLU_PIN4_Msk (0x01 << PORT_PORTP_PULLU_PIN4_Pos)
-#define PORT_PORTP_PULLU_PIN5_Pos 5
-#define PORT_PORTP_PULLU_PIN5_Msk (0x01 << PORT_PORTP_PULLU_PIN5_Pos)
-#define PORT_PORTP_PULLU_PIN6_Pos 6
-#define PORT_PORTP_PULLU_PIN6_Msk (0x01 << PORT_PORTP_PULLU_PIN6_Pos)
-#define PORT_PORTP_PULLU_PIN7_Pos 7
-#define PORT_PORTP_PULLU_PIN7_Msk (0x01 << PORT_PORTP_PULLU_PIN7_Pos)
-#define PORT_PORTP_PULLU_PIN8_Pos 8
-#define PORT_PORTP_PULLU_PIN8_Msk (0x01 << PORT_PORTP_PULLU_PIN8_Pos)
-#define PORT_PORTP_PULLU_PIN9_Pos 9
-#define PORT_PORTP_PULLU_PIN9_Msk (0x01 << PORT_PORTP_PULLU_PIN9_Pos)
-#define PORT_PORTP_PULLU_PIN10_Pos 10
-#define PORT_PORTP_PULLU_PIN10_Msk (0x01 << PORT_PORTP_PULLU_PIN10_Pos)
-#define PORT_PORTP_PULLU_PIN11_Pos 11
-#define PORT_PORTP_PULLU_PIN11_Msk (0x01 << PORT_PORTP_PULLU_PIN11_Pos)
-#define PORT_PORTP_PULLU_PIN12_Pos 12
-#define PORT_PORTP_PULLU_PIN12_Msk (0x01 << PORT_PORTP_PULLU_PIN12_Pos)
-#define PORT_PORTP_PULLU_PIN13_Pos 13
-#define PORT_PORTP_PULLU_PIN13_Msk (0x01 << PORT_PORTP_PULLU_PIN13_Pos)
-#define PORT_PORTP_PULLU_PIN14_Pos 14
-#define PORT_PORTP_PULLU_PIN14_Msk (0x01 << PORT_PORTP_PULLU_PIN14_Pos)
-#define PORT_PORTP_PULLU_PIN15_Pos 15
-#define PORT_PORTP_PULLU_PIN15_Msk (0x01 << PORT_PORTP_PULLU_PIN15_Pos)
-#define PORT_PORTP_PULLU_PIN16_Pos 16
-#define PORT_PORTP_PULLU_PIN16_Msk (0x01 << PORT_PORTP_PULLU_PIN16_Pos)
-#define PORT_PORTP_PULLU_PIN17_Pos 17
-#define PORT_PORTP_PULLU_PIN17_Msk (0x01 << PORT_PORTP_PULLU_PIN17_Pos)
-#define PORT_PORTP_PULLU_PIN18_Pos 18
-#define PORT_PORTP_PULLU_PIN18_Msk (0x01 << PORT_PORTP_PULLU_PIN18_Pos)
-#define PORT_PORTP_PULLU_PIN19_Pos 19
-#define PORT_PORTP_PULLU_PIN19_Msk (0x01 << PORT_PORTP_PULLU_PIN19_Pos)
-#define PORT_PORTP_PULLU_PIN20_Pos 20
-#define PORT_PORTP_PULLU_PIN20_Msk (0x01 << PORT_PORTP_PULLU_PIN20_Pos)
-#define PORT_PORTP_PULLU_PIN21_Pos 21
-#define PORT_PORTP_PULLU_PIN21_Msk (0x01 << PORT_PORTP_PULLU_PIN21_Pos)
-#define PORT_PORTP_PULLU_PIN22_Pos 22
-#define PORT_PORTP_PULLU_PIN22_Msk (0x01 << PORT_PORTP_PULLU_PIN22_Pos)
-#define PORT_PORTP_PULLU_PIN23_Pos 23
-#define PORT_PORTP_PULLU_PIN23_Msk (0x01 << PORT_PORTP_PULLU_PIN23_Pos)
-
-#define PORT_PORTB_PULLD_PIN0_Pos 0
-#define PORT_PORTB_PULLD_PIN0_Msk (0x01 << PORT_PORTB_PULLD_PIN0_Pos)
-#define PORT_PORTB_PULLD_PIN1_Pos 1
-#define PORT_PORTB_PULLD_PIN1_Msk (0x01 << PORT_PORTB_PULLD_PIN1_Pos)
-#define PORT_PORTB_PULLD_PIN2_Pos 2
-#define PORT_PORTB_PULLD_PIN2_Msk (0x01 << PORT_PORTB_PULLD_PIN2_Pos)
-#define PORT_PORTB_PULLD_PIN3_Pos 3
-#define PORT_PORTB_PULLD_PIN3_Msk (0x01 << PORT_PORTB_PULLD_PIN3_Pos)
-#define PORT_PORTB_PULLD_PIN4_Pos 4
-#define PORT_PORTB_PULLD_PIN4_Msk (0x01 << PORT_PORTB_PULLD_PIN4_Pos)
-#define PORT_PORTB_PULLD_PIN5_Pos 5
-#define PORT_PORTB_PULLD_PIN5_Msk (0x01 << PORT_PORTB_PULLD_PIN5_Pos)
-#define PORT_PORTB_PULLD_PIN6_Pos 6
-#define PORT_PORTB_PULLD_PIN6_Msk (0x01 << PORT_PORTB_PULLD_PIN6_Pos)
-#define PORT_PORTB_PULLD_PIN7_Pos 7
-#define PORT_PORTB_PULLD_PIN7_Msk (0x01 << PORT_PORTB_PULLD_PIN7_Pos)
-#define PORT_PORTB_PULLD_PIN8_Pos 8
-#define PORT_PORTB_PULLD_PIN8_Msk (0x01 << PORT_PORTB_PULLD_PIN8_Pos)
-#define PORT_PORTB_PULLD_PIN9_Pos 9
-#define PORT_PORTB_PULLD_PIN9_Msk (0x01 << PORT_PORTB_PULLD_PIN9_Pos)
-#define PORT_PORTB_PULLD_PIN10_Pos 10
-#define PORT_PORTB_PULLD_PIN10_Msk (0x01 << PORT_PORTB_PULLD_PIN10_Pos)
-#define PORT_PORTB_PULLD_PIN11_Pos 11
-#define PORT_PORTB_PULLD_PIN11_Msk (0x01 << PORT_PORTB_PULLD_PIN11_Pos)
-#define PORT_PORTB_PULLD_PIN12_Pos 12
-#define PORT_PORTB_PULLD_PIN12_Msk (0x01 << PORT_PORTB_PULLD_PIN12_Pos)
-#define PORT_PORTB_PULLD_PIN13_Pos 13
-#define PORT_PORTB_PULLD_PIN13_Msk (0x01 << PORT_PORTB_PULLD_PIN13_Pos)
-#define PORT_PORTB_PULLD_PIN14_Pos 14
-#define PORT_PORTB_PULLD_PIN14_Msk (0x01 << PORT_PORTB_PULLD_PIN14_Pos)
-#define PORT_PORTB_PULLD_PIN15_Pos 15
-#define PORT_PORTB_PULLD_PIN15_Msk (0x01 << PORT_PORTB_PULLD_PIN15_Pos)
-
-#define PORT_PORTN_PULLD_PIN0_Pos 0
-#define PORT_PORTN_PULLD_PIN0_Msk (0x01 << PORT_PORTN_PULLD_PIN0_Pos)
-#define PORT_PORTN_PULLD_PIN1_Pos 1
-#define PORT_PORTN_PULLD_PIN1_Msk (0x01 << PORT_PORTN_PULLD_PIN1_Pos)
-#define PORT_PORTN_PULLD_PIN2_Pos 2
-#define PORT_PORTN_PULLD_PIN2_Msk (0x01 << PORT_PORTN_PULLD_PIN2_Pos)
-#define PORT_PORTN_PULLD_PIN3_Pos 3
-#define PORT_PORTN_PULLD_PIN3_Msk (0x01 << PORT_PORTN_PULLD_PIN3_Pos)
-#define PORT_PORTN_PULLD_PIN4_Pos 4
-#define PORT_PORTN_PULLD_PIN4_Msk (0x01 << PORT_PORTN_PULLD_PIN4_Pos)
-#define PORT_PORTN_PULLD_PIN5_Pos 5
-#define PORT_PORTN_PULLD_PIN5_Msk (0x01 << PORT_PORTN_PULLD_PIN5_Pos)
-#define PORT_PORTN_PULLD_PIN6_Pos 6
-#define PORT_PORTN_PULLD_PIN6_Msk (0x01 << PORT_PORTN_PULLD_PIN6_Pos)
-#define PORT_PORTN_PULLD_PIN7_Pos 7
-#define PORT_PORTN_PULLD_PIN7_Msk (0x01 << PORT_PORTN_PULLD_PIN7_Pos)
-#define PORT_PORTN_PULLD_PIN8_Pos 8
-#define PORT_PORTN_PULLD_PIN8_Msk (0x01 << PORT_PORTN_PULLD_PIN8_Pos)
-#define PORT_PORTN_PULLD_PIN9_Pos 9
-#define PORT_PORTN_PULLD_PIN9_Msk (0x01 << PORT_PORTN_PULLD_PIN9_Pos)
-#define PORT_PORTN_PULLD_PIN10_Pos 10
-#define PORT_PORTN_PULLD_PIN10_Msk (0x01 << PORT_PORTN_PULLD_PIN10_Pos)
-#define PORT_PORTN_PULLD_PIN11_Pos 11
-#define PORT_PORTN_PULLD_PIN11_Msk (0x01 << PORT_PORTN_PULLD_PIN11_Pos)
-#define PORT_PORTN_PULLD_PIN12_Pos 12
-#define PORT_PORTN_PULLD_PIN12_Msk (0x01 << PORT_PORTN_PULLD_PIN12_Pos)
-#define PORT_PORTN_PULLD_PIN13_Pos 13
-#define PORT_PORTN_PULLD_PIN13_Msk (0x01 << PORT_PORTN_PULLD_PIN13_Pos)
-#define PORT_PORTN_PULLD_PIN14_Pos 14
-#define PORT_PORTN_PULLD_PIN14_Msk (0x01 << PORT_PORTN_PULLD_PIN14_Pos)
-#define PORT_PORTN_PULLD_PIN15_Pos 15
-#define PORT_PORTN_PULLD_PIN15_Msk (0x01 << PORT_PORTN_PULLD_PIN15_Pos)
-#define PORT_PORTN_PULLD_PIN16_Pos 16
-#define PORT_PORTN_PULLD_PIN16_Msk (0x01 << PORT_PORTN_PULLD_PIN16_Pos)
-#define PORT_PORTN_PULLD_PIN17_Pos 17
-#define PORT_PORTN_PULLD_PIN17_Msk (0x01 << PORT_PORTN_PULLD_PIN17_Pos)
-#define PORT_PORTN_PULLD_PIN18_Pos 18
-#define PORT_PORTN_PULLD_PIN18_Msk (0x01 << PORT_PORTN_PULLD_PIN18_Pos)
-#define PORT_PORTN_PULLD_PIN19_Pos 19
-#define PORT_PORTN_PULLD_PIN19_Msk (0x01 << PORT_PORTN_PULLD_PIN19_Pos)
-#define PORT_PORTN_PULLD_PIN20_Pos 20
-#define PORT_PORTN_PULLD_PIN20_Msk (0x01 << PORT_PORTN_PULLD_PIN20_Pos)
-#define PORT_PORTN_PULLD_PIN21_Pos 21
-#define PORT_PORTN_PULLD_PIN21_Msk (0x01 << PORT_PORTN_PULLD_PIN21_Pos)
-#define PORT_PORTN_PULLD_PIN22_Pos 22
-#define PORT_PORTN_PULLD_PIN22_Msk (0x01 << PORT_PORTN_PULLD_PIN22_Pos)
-#define PORT_PORTN_PULLD_PIN23_Pos 23
-#define PORT_PORTN_PULLD_PIN23_Msk (0x01 << PORT_PORTN_PULLD_PIN23_Pos)
-
-#define PORT_PORTM_DRIVS_PIN0_Pos 0
-#define PORT_PORTM_DRIVS_PIN0_Msk (0x01 << PORT_PORTM_DRIVS_PIN0_Pos)
-#define PORT_PORTM_DRIVS_PIN1_Pos 1
-#define PORT_PORTM_DRIVS_PIN1_Msk (0x01 << PORT_PORTM_DRIVS_PIN1_Pos)
-#define PORT_PORTM_DRIVS_PIN2_Pos 2
-#define PORT_PORTM_DRIVS_PIN2_Msk (0x01 << PORT_PORTM_DRIVS_PIN2_Pos)
-#define PORT_PORTM_DRIVS_PIN3_Pos 3
-#define PORT_PORTM_DRIVS_PIN3_Msk (0x01 << PORT_PORTM_DRIVS_PIN3_Pos)
-#define PORT_PORTM_DRIVS_PIN4_Pos 4
-#define PORT_PORTM_DRIVS_PIN4_Msk (0x01 << PORT_PORTM_DRIVS_PIN4_Pos)
-#define PORT_PORTM_DRIVS_PIN5_Pos 5
-#define PORT_PORTM_DRIVS_PIN5_Msk (0x01 << PORT_PORTM_DRIVS_PIN5_Pos)
-#define PORT_PORTM_DRIVS_PIN6_Pos 6
-#define PORT_PORTM_DRIVS_PIN6_Msk (0x01 << PORT_PORTM_DRIVS_PIN6_Pos)
-#define PORT_PORTM_DRIVS_PIN7_Pos 7
-#define PORT_PORTM_DRIVS_PIN7_Msk (0x01 << PORT_PORTM_DRIVS_PIN7_Pos)
-#define PORT_PORTM_DRIVS_PIN8_Pos 8
-#define PORT_PORTM_DRIVS_PIN8_Msk (0x01 << PORT_PORTM_DRIVS_PIN8_Pos)
-#define PORT_PORTM_DRIVS_PIN9_Pos 9
-#define PORT_PORTM_DRIVS_PIN9_Msk (0x01 << PORT_PORTM_DRIVS_PIN9_Pos)
-#define PORT_PORTM_DRIVS_PIN10_Pos 10
-#define PORT_PORTM_DRIVS_PIN10_Msk (0x01 << PORT_PORTM_DRIVS_PIN10_Pos)
-#define PORT_PORTM_DRIVS_PIN11_Pos 11
-#define PORT_PORTM_DRIVS_PIN11_Msk (0x01 << PORT_PORTM_DRIVS_PIN11_Pos)
-#define PORT_PORTM_DRIVS_PIN12_Pos 12
-#define PORT_PORTM_DRIVS_PIN12_Msk (0x01 << PORT_PORTM_DRIVS_PIN12_Pos)
-#define PORT_PORTM_DRIVS_PIN13_Pos 13
-#define PORT_PORTM_DRIVS_PIN13_Msk (0x01 << PORT_PORTM_DRIVS_PIN13_Pos)
-#define PORT_PORTM_DRIVS_PIN14_Pos 14
-#define PORT_PORTM_DRIVS_PIN14_Msk (0x01 << PORT_PORTM_DRIVS_PIN14_Pos)
-#define PORT_PORTM_DRIVS_PIN15_Pos 15
-#define PORT_PORTM_DRIVS_PIN15_Msk (0x01 << PORT_PORTM_DRIVS_PIN15_Pos)
-#define PORT_PORTM_DRIVS_PIN16_Pos 16
-#define PORT_PORTM_DRIVS_PIN16_Msk (0x01 << PORT_PORTM_DRIVS_PIN16_Pos)
-#define PORT_PORTM_DRIVS_PIN17_Pos 17
-#define PORT_PORTM_DRIVS_PIN17_Msk (0x01 << PORT_PORTM_DRIVS_PIN17_Pos)
-#define PORT_PORTM_DRIVS_PIN18_Pos 18
-#define PORT_PORTM_DRIVS_PIN18_Msk (0x01 << PORT_PORTM_DRIVS_PIN18_Pos)
-#define PORT_PORTM_DRIVS_PIN19_Pos 19
-#define PORT_PORTM_DRIVS_PIN19_Msk (0x01 << PORT_PORTM_DRIVS_PIN19_Pos)
-#define PORT_PORTM_DRIVS_PIN20_Pos 20
-#define PORT_PORTM_DRIVS_PIN20_Msk (0x01 << PORT_PORTM_DRIVS_PIN20_Pos)
-#define PORT_PORTM_DRIVS_PIN21_Pos 21
-#define PORT_PORTM_DRIVS_PIN21_Msk (0x01 << PORT_PORTM_DRIVS_PIN21_Pos)
-#define PORT_PORTM_DRIVS_PIN22_Pos 22
-#define PORT_PORTM_DRIVS_PIN22_Msk (0x01 << PORT_PORTM_DRIVS_PIN22_Pos)
-#define PORT_PORTM_DRIVS_PIN23_Pos 23
-#define PORT_PORTM_DRIVS_PIN23_Msk (0x01 << PORT_PORTM_DRIVS_PIN23_Pos)
-
-#define PORT_PORTN_DRIVS_PIN0_Pos 0
-#define PORT_PORTN_DRIVS_PIN0_Msk (0x01 << PORT_PORTN_DRIVS_PIN0_Pos)
-#define PORT_PORTN_DRIVS_PIN1_Pos 1
-#define PORT_PORTN_DRIVS_PIN1_Msk (0x01 << PORT_PORTN_DRIVS_PIN1_Pos)
-#define PORT_PORTN_DRIVS_PIN2_Pos 2
-#define PORT_PORTN_DRIVS_PIN2_Msk (0x01 << PORT_PORTN_DRIVS_PIN2_Pos)
-#define PORT_PORTN_DRIVS_PIN3_Pos 3
-#define PORT_PORTN_DRIVS_PIN3_Msk (0x01 << PORT_PORTN_DRIVS_PIN3_Pos)
-#define PORT_PORTN_DRIVS_PIN4_Pos 4
-#define PORT_PORTN_DRIVS_PIN4_Msk (0x01 << PORT_PORTN_DRIVS_PIN4_Pos)
-#define PORT_PORTN_DRIVS_PIN5_Pos 5
-#define PORT_PORTN_DRIVS_PIN5_Msk (0x01 << PORT_PORTN_DRIVS_PIN5_Pos)
-#define PORT_PORTN_DRIVS_PIN6_Pos 6
-#define PORT_PORTN_DRIVS_PIN6_Msk (0x01 << PORT_PORTN_DRIVS_PIN6_Pos)
-#define PORT_PORTN_DRIVS_PIN7_Pos 7
-#define PORT_PORTN_DRIVS_PIN7_Msk (0x01 << PORT_PORTN_DRIVS_PIN7_Pos)
-#define PORT_PORTN_DRIVS_PIN8_Pos 8
-#define PORT_PORTN_DRIVS_PIN8_Msk (0x01 << PORT_PORTN_DRIVS_PIN8_Pos)
-#define PORT_PORTN_DRIVS_PIN9_Pos 9
-#define PORT_PORTN_DRIVS_PIN9_Msk (0x01 << PORT_PORTN_DRIVS_PIN9_Pos)
-#define PORT_PORTN_DRIVS_PIN10_Pos 10
-#define PORT_PORTN_DRIVS_PIN10_Msk (0x01 << PORT_PORTN_DRIVS_PIN10_Pos)
-#define PORT_PORTN_DRIVS_PIN11_Pos 11
-#define PORT_PORTN_DRIVS_PIN11_Msk (0x01 << PORT_PORTN_DRIVS_PIN11_Pos)
-#define PORT_PORTN_DRIVS_PIN12_Pos 12
-#define PORT_PORTN_DRIVS_PIN12_Msk (0x01 << PORT_PORTN_DRIVS_PIN12_Pos)
-#define PORT_PORTN_DRIVS_PIN13_Pos 13
-#define PORT_PORTN_DRIVS_PIN13_Msk (0x01 << PORT_PORTN_DRIVS_PIN13_Pos)
-#define PORT_PORTN_DRIVS_PIN14_Pos 14
-#define PORT_PORTN_DRIVS_PIN14_Msk (0x01 << PORT_PORTN_DRIVS_PIN14_Pos)
-#define PORT_PORTN_DRIVS_PIN15_Pos 15
-#define PORT_PORTN_DRIVS_PIN15_Msk (0x01 << PORT_PORTN_DRIVS_PIN15_Pos)
-#define PORT_PORTN_DRIVS_PIN16_Pos 16
-#define PORT_PORTN_DRIVS_PIN16_Msk (0x01 << PORT_PORTN_DRIVS_PIN16_Pos)
-#define PORT_PORTN_DRIVS_PIN17_Pos 17
-#define PORT_PORTN_DRIVS_PIN17_Msk (0x01 << PORT_PORTN_DRIVS_PIN17_Pos)
-#define PORT_PORTN_DRIVS_PIN18_Pos 18
-#define PORT_PORTN_DRIVS_PIN18_Msk (0x01 << PORT_PORTN_DRIVS_PIN18_Pos)
-#define PORT_PORTN_DRIVS_PIN19_Pos 19
-#define PORT_PORTN_DRIVS_PIN19_Msk (0x01 << PORT_PORTN_DRIVS_PIN19_Pos)
-#define PORT_PORTN_DRIVS_PIN20_Pos 20
-#define PORT_PORTN_DRIVS_PIN20_Msk (0x01 << PORT_PORTN_DRIVS_PIN20_Pos)
-#define PORT_PORTN_DRIVS_PIN21_Pos 21
-#define PORT_PORTN_DRIVS_PIN21_Msk (0x01 << PORT_PORTN_DRIVS_PIN21_Pos)
-#define PORT_PORTN_DRIVS_PIN22_Pos 22
-#define PORT_PORTN_DRIVS_PIN22_Msk (0x01 << PORT_PORTN_DRIVS_PIN22_Pos)
-#define PORT_PORTN_DRIVS_PIN23_Pos 23
-#define PORT_PORTN_DRIVS_PIN23_Msk (0x01 << PORT_PORTN_DRIVS_PIN23_Pos)
-
-#define PORT_PORTP_DRIVS_PIN0_Pos 0
-#define PORT_PORTP_DRIVS_PIN0_Msk (0x01 << PORT_PORTP_DRIVS_PIN0_Pos)
-#define PORT_PORTP_DRIVS_PIN1_Pos 1
-#define PORT_PORTP_DRIVS_PIN1_Msk (0x01 << PORT_PORTP_DRIVS_PIN1_Pos)
-#define PORT_PORTP_DRIVS_PIN2_Pos 2
-#define PORT_PORTP_DRIVS_PIN2_Msk (0x01 << PORT_PORTP_DRIVS_PIN2_Pos)
-#define PORT_PORTP_DRIVS_PIN3_Pos 3
-#define PORT_PORTP_DRIVS_PIN3_Msk (0x01 << PORT_PORTP_DRIVS_PIN3_Pos)
-#define PORT_PORTP_DRIVS_PIN4_Pos 4
-#define PORT_PORTP_DRIVS_PIN4_Msk (0x01 << PORT_PORTP_DRIVS_PIN4_Pos)
-#define PORT_PORTP_DRIVS_PIN5_Pos 5
-#define PORT_PORTP_DRIVS_PIN5_Msk (0x01 << PORT_PORTP_DRIVS_PIN5_Pos)
-#define PORT_PORTP_DRIVS_PIN6_Pos 6
-#define PORT_PORTP_DRIVS_PIN6_Msk (0x01 << PORT_PORTP_DRIVS_PIN6_Pos)
-#define PORT_PORTP_DRIVS_PIN7_Pos 7
-#define PORT_PORTP_DRIVS_PIN7_Msk (0x01 << PORT_PORTP_DRIVS_PIN7_Pos)
-#define PORT_PORTP_DRIVS_PIN8_Pos 8
-#define PORT_PORTP_DRIVS_PIN8_Msk (0x01 << PORT_PORTP_DRIVS_PIN8_Pos)
-#define PORT_PORTP_DRIVS_PIN9_Pos 9
-#define PORT_PORTP_DRIVS_PIN9_Msk (0x01 << PORT_PORTP_DRIVS_PIN9_Pos)
-#define PORT_PORTP_DRIVS_PIN10_Pos 10
-#define PORT_PORTP_DRIVS_PIN10_Msk (0x01 << PORT_PORTP_DRIVS_PIN10_Pos)
-#define PORT_PORTP_DRIVS_PIN11_Pos 11
-#define PORT_PORTP_DRIVS_PIN11_Msk (0x01 << PORT_PORTP_DRIVS_PIN11_Pos)
-#define PORT_PORTP_DRIVS_PIN12_Pos 12
-#define PORT_PORTP_DRIVS_PIN12_Msk (0x01 << PORT_PORTP_DRIVS_PIN12_Pos)
-#define PORT_PORTP_DRIVS_PIN13_Pos 13
-#define PORT_PORTP_DRIVS_PIN13_Msk (0x01 << PORT_PORTP_DRIVS_PIN13_Pos)
-#define PORT_PORTP_DRIVS_PIN14_Pos 14
-#define PORT_PORTP_DRIVS_PIN14_Msk (0x01 << PORT_PORTP_DRIVS_PIN14_Pos)
-#define PORT_PORTP_DRIVS_PIN15_Pos 15
-#define PORT_PORTP_DRIVS_PIN15_Msk (0x01 << PORT_PORTP_DRIVS_PIN15_Pos)
-#define PORT_PORTP_DRIVS_PIN16_Pos 16
-#define PORT_PORTP_DRIVS_PIN16_Msk (0x01 << PORT_PORTP_DRIVS_PIN16_Pos)
-#define PORT_PORTP_DRIVS_PIN17_Pos 17
-#define PORT_PORTP_DRIVS_PIN17_Msk (0x01 << PORT_PORTP_DRIVS_PIN17_Pos)
-#define PORT_PORTP_DRIVS_PIN18_Pos 18
-#define PORT_PORTP_DRIVS_PIN18_Msk (0x01 << PORT_PORTP_DRIVS_PIN18_Pos)
-#define PORT_PORTP_DRIVS_PIN19_Pos 19
-#define PORT_PORTP_DRIVS_PIN19_Msk (0x01 << PORT_PORTP_DRIVS_PIN19_Pos)
-#define PORT_PORTP_DRIVS_PIN20_Pos 20
-#define PORT_PORTP_DRIVS_PIN20_Msk (0x01 << PORT_PORTP_DRIVS_PIN20_Pos)
-#define PORT_PORTP_DRIVS_PIN21_Pos 21
-#define PORT_PORTP_DRIVS_PIN21_Msk (0x01 << PORT_PORTP_DRIVS_PIN21_Pos)
-#define PORT_PORTP_DRIVS_PIN22_Pos 22
-#define PORT_PORTP_DRIVS_PIN22_Msk (0x01 << PORT_PORTP_DRIVS_PIN22_Pos)
-#define PORT_PORTP_DRIVS_PIN23_Pos 23
-#define PORT_PORTP_DRIVS_PIN23_Msk (0x01 << PORT_PORTP_DRIVS_PIN23_Pos)
-
-#define PORT_PORTA_INEN_PIN0_Pos 0
-#define PORT_PORTA_INEN_PIN0_Msk (0x01 << PORT_PORTA_INEN_PIN0_Pos)
-#define PORT_PORTA_INEN_PIN1_Pos 1
-#define PORT_PORTA_INEN_PIN1_Msk (0x01 << PORT_PORTA_INEN_PIN1_Pos)
-#define PORT_PORTA_INEN_PIN2_Pos 2
-#define PORT_PORTA_INEN_PIN2_Msk (0x01 << PORT_PORTA_INEN_PIN2_Pos)
-#define PORT_PORTA_INEN_PIN3_Pos 3
-#define PORT_PORTA_INEN_PIN3_Msk (0x01 << PORT_PORTA_INEN_PIN3_Pos)
-#define PORT_PORTA_INEN_PIN4_Pos 4
-#define PORT_PORTA_INEN_PIN4_Msk (0x01 << PORT_PORTA_INEN_PIN4_Pos)
-#define PORT_PORTA_INEN_PIN5_Pos 5
-#define PORT_PORTA_INEN_PIN5_Msk (0x01 << PORT_PORTA_INEN_PIN5_Pos)
-#define PORT_PORTA_INEN_PIN6_Pos 6
-#define PORT_PORTA_INEN_PIN6_Msk (0x01 << PORT_PORTA_INEN_PIN6_Pos)
-#define PORT_PORTA_INEN_PIN7_Pos 7
-#define PORT_PORTA_INEN_PIN7_Msk (0x01 << PORT_PORTA_INEN_PIN7_Pos)
-#define PORT_PORTA_INEN_PIN8_Pos 8
-#define PORT_PORTA_INEN_PIN8_Msk (0x01 << PORT_PORTA_INEN_PIN8_Pos)
-#define PORT_PORTA_INEN_PIN9_Pos 9
-#define PORT_PORTA_INEN_PIN9_Msk (0x01 << PORT_PORTA_INEN_PIN9_Pos)
-#define PORT_PORTA_INEN_PIN10_Pos 10
-#define PORT_PORTA_INEN_PIN10_Msk (0x01 << PORT_PORTA_INEN_PIN10_Pos)
-#define PORT_PORTA_INEN_PIN11_Pos 11
-#define PORT_PORTA_INEN_PIN11_Msk (0x01 << PORT_PORTA_INEN_PIN11_Pos)
-#define PORT_PORTA_INEN_PIN12_Pos 12
-#define PORT_PORTA_INEN_PIN12_Msk (0x01 << PORT_PORTA_INEN_PIN12_Pos)
-#define PORT_PORTA_INEN_PIN13_Pos 13
-#define PORT_PORTA_INEN_PIN13_Msk (0x01 << PORT_PORTA_INEN_PIN13_Pos)
-#define PORT_PORTA_INEN_PIN14_Pos 14
-#define PORT_PORTA_INEN_PIN14_Msk (0x01 << PORT_PORTA_INEN_PIN14_Pos)
-#define PORT_PORTA_INEN_PIN15_Pos 15
-#define PORT_PORTA_INEN_PIN15_Msk (0x01 << PORT_PORTA_INEN_PIN15_Pos)
-
-#define PORT_PORTB_INEN_PIN0_Pos 0
-#define PORT_PORTB_INEN_PIN0_Msk (0x01 << PORT_PORTB_INEN_PIN0_Pos)
-#define PORT_PORTB_INEN_PIN1_Pos 1
-#define PORT_PORTB_INEN_PIN1_Msk (0x01 << PORT_PORTB_INEN_PIN1_Pos)
-#define PORT_PORTB_INEN_PIN2_Pos 2
-#define PORT_PORTB_INEN_PIN2_Msk (0x01 << PORT_PORTB_INEN_PIN2_Pos)
-#define PORT_PORTB_INEN_PIN3_Pos 3
-#define PORT_PORTB_INEN_PIN3_Msk (0x01 << PORT_PORTB_INEN_PIN3_Pos)
-#define PORT_PORTB_INEN_PIN4_Pos 4
-#define PORT_PORTB_INEN_PIN4_Msk (0x01 << PORT_PORTB_INEN_PIN4_Pos)
-#define PORT_PORTB_INEN_PIN5_Pos 5
-#define PORT_PORTB_INEN_PIN5_Msk (0x01 << PORT_PORTB_INEN_PIN5_Pos)
-#define PORT_PORTB_INEN_PIN6_Pos 6
-#define PORT_PORTB_INEN_PIN6_Msk (0x01 << PORT_PORTB_INEN_PIN6_Pos)
-#define PORT_PORTB_INEN_PIN7_Pos 7
-#define PORT_PORTB_INEN_PIN7_Msk (0x01 << PORT_PORTB_INEN_PIN7_Pos)
-#define PORT_PORTB_INEN_PIN8_Pos 8
-#define PORT_PORTB_INEN_PIN8_Msk (0x01 << PORT_PORTB_INEN_PIN8_Pos)
-#define PORT_PORTB_INEN_PIN9_Pos 9
-#define PORT_PORTB_INEN_PIN9_Msk (0x01 << PORT_PORTB_INEN_PIN9_Pos)
-#define PORT_PORTB_INEN_PIN10_Pos 10
-#define PORT_PORTB_INEN_PIN10_Msk (0x01 << PORT_PORTB_INEN_PIN10_Pos)
-#define PORT_PORTB_INEN_PIN11_Pos 11
-#define PORT_PORTB_INEN_PIN11_Msk (0x01 << PORT_PORTB_INEN_PIN11_Pos)
-#define PORT_PORTB_INEN_PIN12_Pos 12
-#define PORT_PORTB_INEN_PIN12_Msk (0x01 << PORT_PORTB_INEN_PIN12_Pos)
-#define PORT_PORTB_INEN_PIN13_Pos 13
-#define PORT_PORTB_INEN_PIN13_Msk (0x01 << PORT_PORTB_INEN_PIN13_Pos)
-#define PORT_PORTB_INEN_PIN14_Pos 14
-#define PORT_PORTB_INEN_PIN14_Msk (0x01 << PORT_PORTB_INEN_PIN14_Pos)
-#define PORT_PORTB_INEN_PIN15_Pos 15
-#define PORT_PORTB_INEN_PIN15_Msk (0x01 << PORT_PORTB_INEN_PIN15_Pos)
-
-#define PORT_PORTC_INEN_PIN0_Pos 0
-#define PORT_PORTC_INEN_PIN0_Msk (0x01 << PORT_PORTC_INEN_PIN0_Pos)
-#define PORT_PORTC_INEN_PIN1_Pos 1
-#define PORT_PORTC_INEN_PIN1_Msk (0x01 << PORT_PORTC_INEN_PIN1_Pos)
-#define PORT_PORTC_INEN_PIN2_Pos 2
-#define PORT_PORTC_INEN_PIN2_Msk (0x01 << PORT_PORTC_INEN_PIN2_Pos)
-#define PORT_PORTC_INEN_PIN3_Pos 3
-#define PORT_PORTC_INEN_PIN3_Msk (0x01 << PORT_PORTC_INEN_PIN3_Pos)
-#define PORT_PORTC_INEN_PIN4_Pos 4
-#define PORT_PORTC_INEN_PIN4_Msk (0x01 << PORT_PORTC_INEN_PIN4_Pos)
-#define PORT_PORTC_INEN_PIN5_Pos 5
-#define PORT_PORTC_INEN_PIN5_Msk (0x01 << PORT_PORTC_INEN_PIN5_Pos)
-#define PORT_PORTC_INEN_PIN6_Pos 6
-#define PORT_PORTC_INEN_PIN6_Msk (0x01 << PORT_PORTC_INEN_PIN6_Pos)
-#define PORT_PORTC_INEN_PIN7_Pos 7
-#define PORT_PORTC_INEN_PIN7_Msk (0x01 << PORT_PORTC_INEN_PIN7_Pos)
-#define PORT_PORTC_INEN_PIN8_Pos 8
-#define PORT_PORTC_INEN_PIN8_Msk (0x01 << PORT_PORTC_INEN_PIN8_Pos)
-#define PORT_PORTC_INEN_PIN9_Pos 9
-#define PORT_PORTC_INEN_PIN9_Msk (0x01 << PORT_PORTC_INEN_PIN9_Pos)
-#define PORT_PORTC_INEN_PIN10_Pos 10
-#define PORT_PORTC_INEN_PIN10_Msk (0x01 << PORT_PORTC_INEN_PIN10_Pos)
-#define PORT_PORTC_INEN_PIN11_Pos 11
-#define PORT_PORTC_INEN_PIN11_Msk (0x01 << PORT_PORTC_INEN_PIN11_Pos)
-#define PORT_PORTC_INEN_PIN12_Pos 12
-#define PORT_PORTC_INEN_PIN12_Msk (0x01 << PORT_PORTC_INEN_PIN12_Pos)
-#define PORT_PORTC_INEN_PIN13_Pos 13
-#define PORT_PORTC_INEN_PIN13_Msk (0x01 << PORT_PORTC_INEN_PIN13_Pos)
-#define PORT_PORTC_INEN_PIN14_Pos 14
-#define PORT_PORTC_INEN_PIN14_Msk (0x01 << PORT_PORTC_INEN_PIN14_Pos)
-#define PORT_PORTC_INEN_PIN15_Pos 15
-#define PORT_PORTC_INEN_PIN15_Msk (0x01 << PORT_PORTC_INEN_PIN15_Pos)
-
-#define PORT_PORTM_INEN_PIN0_Pos 0
-#define PORT_PORTM_INEN_PIN0_Msk (0x01 << PORT_PORTM_INEN_PIN0_Pos)
-#define PORT_PORTM_INEN_PIN1_Pos 1
-#define PORT_PORTM_INEN_PIN1_Msk (0x01 << PORT_PORTM_INEN_PIN1_Pos)
-#define PORT_PORTM_INEN_PIN2_Pos 2
-#define PORT_PORTM_INEN_PIN2_Msk (0x01 << PORT_PORTM_INEN_PIN2_Pos)
-#define PORT_PORTM_INEN_PIN3_Pos 3
-#define PORT_PORTM_INEN_PIN3_Msk (0x01 << PORT_PORTM_INEN_PIN3_Pos)
-#define PORT_PORTM_INEN_PIN4_Pos 4
-#define PORT_PORTM_INEN_PIN4_Msk (0x01 << PORT_PORTM_INEN_PIN4_Pos)
-#define PORT_PORTM_INEN_PIN5_Pos 5
-#define PORT_PORTM_INEN_PIN5_Msk (0x01 << PORT_PORTM_INEN_PIN5_Pos)
-#define PORT_PORTM_INEN_PIN6_Pos 6
-#define PORT_PORTM_INEN_PIN6_Msk (0x01 << PORT_PORTM_INEN_PIN6_Pos)
-#define PORT_PORTM_INEN_PIN7_Pos 7
-#define PORT_PORTM_INEN_PIN7_Msk (0x01 << PORT_PORTM_INEN_PIN7_Pos)
-#define PORT_PORTM_INEN_PIN8_Pos 8
-#define PORT_PORTM_INEN_PIN8_Msk (0x01 << PORT_PORTM_INEN_PIN8_Pos)
-#define PORT_PORTM_INEN_PIN9_Pos 9
-#define PORT_PORTM_INEN_PIN9_Msk (0x01 << PORT_PORTM_INEN_PIN9_Pos)
-#define PORT_PORTM_INEN_PIN10_Pos 10
-#define PORT_PORTM_INEN_PIN10_Msk (0x01 << PORT_PORTM_INEN_PIN10_Pos)
-#define PORT_PORTM_INEN_PIN11_Pos 11
-#define PORT_PORTM_INEN_PIN11_Msk (0x01 << PORT_PORTM_INEN_PIN11_Pos)
-#define PORT_PORTM_INEN_PIN12_Pos 12
-#define PORT_PORTM_INEN_PIN12_Msk (0x01 << PORT_PORTM_INEN_PIN12_Pos)
-#define PORT_PORTM_INEN_PIN13_Pos 13
-#define PORT_PORTM_INEN_PIN13_Msk (0x01 << PORT_PORTM_INEN_PIN13_Pos)
-#define PORT_PORTM_INEN_PIN14_Pos 14
-#define PORT_PORTM_INEN_PIN14_Msk (0x01 << PORT_PORTM_INEN_PIN14_Pos)
-#define PORT_PORTM_INEN_PIN15_Pos 15
-#define PORT_PORTM_INEN_PIN15_Msk (0x01 << PORT_PORTM_INEN_PIN15_Pos)
-#define PORT_PORTM_INEN_PIN16_Pos 16
-#define PORT_PORTM_INEN_PIN16_Msk (0x01 << PORT_PORTM_INEN_PIN16_Pos)
-#define PORT_PORTM_INEN_PIN17_Pos 17
-#define PORT_PORTM_INEN_PIN17_Msk (0x01 << PORT_PORTM_INEN_PIN17_Pos)
-#define PORT_PORTM_INEN_PIN18_Pos 18
-#define PORT_PORTM_INEN_PIN18_Msk (0x01 << PORT_PORTM_INEN_PIN18_Pos)
-#define PORT_PORTM_INEN_PIN19_Pos 19
-#define PORT_PORTM_INEN_PIN19_Msk (0x01 << PORT_PORTM_INEN_PIN19_Pos)
-#define PORT_PORTM_INEN_PIN20_Pos 20
-#define PORT_PORTM_INEN_PIN20_Msk (0x01 << PORT_PORTM_INEN_PIN20_Pos)
-#define PORT_PORTM_INEN_PIN21_Pos 21
-#define PORT_PORTM_INEN_PIN21_Msk (0x01 << PORT_PORTM_INEN_PIN21_Pos)
-#define PORT_PORTM_INEN_PIN22_Pos 22
-#define PORT_PORTM_INEN_PIN22_Msk (0x01 << PORT_PORTM_INEN_PIN22_Pos)
-#define PORT_PORTM_INEN_PIN23_Pos 23
-#define PORT_PORTM_INEN_PIN23_Msk (0x01 << PORT_PORTM_INEN_PIN23_Pos)
-
-#define PORT_PORTN_INEN_PIN0_Pos 0
-#define PORT_PORTN_INEN_PIN0_Msk (0x01 << PORT_PORTN_INEN_PIN0_Pos)
-#define PORT_PORTN_INEN_PIN1_Pos 1
-#define PORT_PORTN_INEN_PIN1_Msk (0x01 << PORT_PORTN_INEN_PIN1_Pos)
-#define PORT_PORTN_INEN_PIN2_Pos 2
-#define PORT_PORTN_INEN_PIN2_Msk (0x01 << PORT_PORTN_INEN_PIN2_Pos)
-#define PORT_PORTN_INEN_PIN3_Pos 3
-#define PORT_PORTN_INEN_PIN3_Msk (0x01 << PORT_PORTN_INEN_PIN3_Pos)
-#define PORT_PORTN_INEN_PIN4_Pos 4
-#define PORT_PORTN_INEN_PIN4_Msk (0x01 << PORT_PORTN_INEN_PIN4_Pos)
-#define PORT_PORTN_INEN_PIN5_Pos 5
-#define PORT_PORTN_INEN_PIN5_Msk (0x01 << PORT_PORTN_INEN_PIN5_Pos)
-#define PORT_PORTN_INEN_PIN6_Pos 6
-#define PORT_PORTN_INEN_PIN6_Msk (0x01 << PORT_PORTN_INEN_PIN6_Pos)
-#define PORT_PORTN_INEN_PIN7_Pos 7
-#define PORT_PORTN_INEN_PIN7_Msk (0x01 << PORT_PORTN_INEN_PIN7_Pos)
-#define PORT_PORTN_INEN_PIN8_Pos 8
-#define PORT_PORTN_INEN_PIN8_Msk (0x01 << PORT_PORTN_INEN_PIN8_Pos)
-#define PORT_PORTN_INEN_PIN9_Pos 9
-#define PORT_PORTN_INEN_PIN9_Msk (0x01 << PORT_PORTN_INEN_PIN9_Pos)
-#define PORT_PORTN_INEN_PIN10_Pos 10
-#define PORT_PORTN_INEN_PIN10_Msk (0x01 << PORT_PORTN_INEN_PIN10_Pos)
-#define PORT_PORTN_INEN_PIN11_Pos 11
-#define PORT_PORTN_INEN_PIN11_Msk (0x01 << PORT_PORTN_INEN_PIN11_Pos)
-#define PORT_PORTN_INEN_PIN12_Pos 12
-#define PORT_PORTN_INEN_PIN12_Msk (0x01 << PORT_PORTN_INEN_PIN12_Pos)
-#define PORT_PORTN_INEN_PIN13_Pos 13
-#define PORT_PORTN_INEN_PIN13_Msk (0x01 << PORT_PORTN_INEN_PIN13_Pos)
-#define PORT_PORTN_INEN_PIN14_Pos 14
-#define PORT_PORTN_INEN_PIN14_Msk (0x01 << PORT_PORTN_INEN_PIN14_Pos)
-#define PORT_PORTN_INEN_PIN15_Pos 15
-#define PORT_PORTN_INEN_PIN15_Msk (0x01 << PORT_PORTN_INEN_PIN15_Pos)
-#define PORT_PORTN_INEN_PIN16_Pos 16
-#define PORT_PORTN_INEN_PIN16_Msk (0x01 << PORT_PORTN_INEN_PIN16_Pos)
-#define PORT_PORTN_INEN_PIN17_Pos 17
-#define PORT_PORTN_INEN_PIN17_Msk (0x01 << PORT_PORTN_INEN_PIN17_Pos)
-#define PORT_PORTN_INEN_PIN18_Pos 18
-#define PORT_PORTN_INEN_PIN18_Msk (0x01 << PORT_PORTN_INEN_PIN18_Pos)
-#define PORT_PORTN_INEN_PIN19_Pos 19
-#define PORT_PORTN_INEN_PIN19_Msk (0x01 << PORT_PORTN_INEN_PIN19_Pos)
-#define PORT_PORTN_INEN_PIN20_Pos 20
-#define PORT_PORTN_INEN_PIN20_Msk (0x01 << PORT_PORTN_INEN_PIN20_Pos)
-#define PORT_PORTN_INEN_PIN21_Pos 21
-#define PORT_PORTN_INEN_PIN21_Msk (0x01 << PORT_PORTN_INEN_PIN21_Pos)
-#define PORT_PORTN_INEN_PIN22_Pos 22
-#define PORT_PORTN_INEN_PIN22_Msk (0x01 << PORT_PORTN_INEN_PIN22_Pos)
-#define PORT_PORTN_INEN_PIN23_Pos 23
-#define PORT_PORTN_INEN_PIN23_Msk (0x01 << PORT_PORTN_INEN_PIN23_Pos)
-
-#define PORT_PORTP_INEN_PIN0_Pos 0
-#define PORT_PORTP_INEN_PIN0_Msk (0x01 << PORT_PORTP_INEN_PIN0_Pos)
-#define PORT_PORTP_INEN_PIN1_Pos 1
-#define PORT_PORTP_INEN_PIN1_Msk (0x01 << PORT_PORTP_INEN_PIN1_Pos)
-#define PORT_PORTP_INEN_PIN2_Pos 2
-#define PORT_PORTP_INEN_PIN2_Msk (0x01 << PORT_PORTP_INEN_PIN2_Pos)
-#define PORT_PORTP_INEN_PIN3_Pos 3
-#define PORT_PORTP_INEN_PIN3_Msk (0x01 << PORT_PORTP_INEN_PIN3_Pos)
-#define PORT_PORTP_INEN_PIN4_Pos 4
-#define PORT_PORTP_INEN_PIN4_Msk (0x01 << PORT_PORTP_INEN_PIN4_Pos)
-#define PORT_PORTP_INEN_PIN5_Pos 5
-#define PORT_PORTP_INEN_PIN5_Msk (0x01 << PORT_PORTP_INEN_PIN5_Pos)
-#define PORT_PORTP_INEN_PIN6_Pos 6
-#define PORT_PORTP_INEN_PIN6_Msk (0x01 << PORT_PORTP_INEN_PIN6_Pos)
-#define PORT_PORTP_INEN_PIN7_Pos 7
-#define PORT_PORTP_INEN_PIN7_Msk (0x01 << PORT_PORTP_INEN_PIN7_Pos)
-#define PORT_PORTP_INEN_PIN8_Pos 8
-#define PORT_PORTP_INEN_PIN8_Msk (0x01 << PORT_PORTP_INEN_PIN8_Pos)
-#define PORT_PORTP_INEN_PIN9_Pos 9
-#define PORT_PORTP_INEN_PIN9_Msk (0x01 << PORT_PORTP_INEN_PIN9_Pos)
-#define PORT_PORTP_INEN_PIN10_Pos 10
-#define PORT_PORTP_INEN_PIN10_Msk (0x01 << PORT_PORTP_INEN_PIN10_Pos)
-#define PORT_PORTP_INEN_PIN11_Pos 11
-#define PORT_PORTP_INEN_PIN11_Msk (0x01 << PORT_PORTP_INEN_PIN11_Pos)
-#define PORT_PORTP_INEN_PIN12_Pos 12
-#define PORT_PORTP_INEN_PIN12_Msk (0x01 << PORT_PORTP_INEN_PIN12_Pos)
-#define PORT_PORTP_INEN_PIN13_Pos 13
-#define PORT_PORTP_INEN_PIN13_Msk (0x01 << PORT_PORTP_INEN_PIN13_Pos)
-#define PORT_PORTP_INEN_PIN14_Pos 14
-#define PORT_PORTP_INEN_PIN14_Msk (0x01 << PORT_PORTP_INEN_PIN14_Pos)
-#define PORT_PORTP_INEN_PIN15_Pos 15
-#define PORT_PORTP_INEN_PIN15_Msk (0x01 << PORT_PORTP_INEN_PIN15_Pos)
-#define PORT_PORTP_INEN_PIN16_Pos 16
-#define PORT_PORTP_INEN_PIN16_Msk (0x01 << PORT_PORTP_INEN_PIN16_Pos)
-#define PORT_PORTP_INEN_PIN17_Pos 17
-#define PORT_PORTP_INEN_PIN17_Msk (0x01 << PORT_PORTP_INEN_PIN17_Pos)
-#define PORT_PORTP_INEN_PIN18_Pos 18
-#define PORT_PORTP_INEN_PIN18_Msk (0x01 << PORT_PORTP_INEN_PIN18_Pos)
-#define PORT_PORTP_INEN_PIN19_Pos 19
-#define PORT_PORTP_INEN_PIN19_Msk (0x01 << PORT_PORTP_INEN_PIN19_Pos)
-#define PORT_PORTP_INEN_PIN20_Pos 20
-#define PORT_PORTP_INEN_PIN20_Msk (0x01 << PORT_PORTP_INEN_PIN20_Pos)
-#define PORT_PORTP_INEN_PIN21_Pos 21
-#define PORT_PORTP_INEN_PIN21_Msk (0x01 << PORT_PORTP_INEN_PIN21_Pos)
-#define PORT_PORTP_INEN_PIN22_Pos 22
-#define PORT_PORTP_INEN_PIN22_Msk (0x01 << PORT_PORTP_INEN_PIN22_Pos)
-#define PORT_PORTP_INEN_PIN23_Pos 23
-#define PORT_PORTP_INEN_PIN23_Msk (0x01 << PORT_PORTP_INEN_PIN23_Pos)
-
-typedef struct
-{
-    __IO uint32_t DATA;
-#define PIN0 0
-#define PIN1 1
-#define PIN2 2
-#define PIN3 3
-#define PIN4 4
-#define PIN5 5
-#define PIN6 6
-#define PIN7 7
-#define PIN8 8
-#define PIN9 9
-#define PIN10 10
-#define PIN11 11
-#define PIN12 12
-#define PIN13 13
-#define PIN14 14
-#define PIN15 15
-#define PIN16 16
-#define PIN17 17
-#define PIN18 18
-#define PIN19 19
-#define PIN20 20
-#define PIN21 21
-#define PIN22 22
-#define PIN23 23
-#define PIN24 24
-
-    __IO uint32_t DIR; //0 输入   1 输出
-
-    __IO uint32_t INTLVLTRG; //Interrupt Level Trigger  1 电平触发中断    0 边沿触发中断
-
-    __IO uint32_t INTBE; //Both Edge，当INTLVLTRG设为边沿触发中断时，此位置1表示上升沿和下降沿都触发中断，置0时触发边沿由INTRISEEN选择
-
-    __IO uint32_t INTRISEEN; //Interrupt Rise Edge Enable   1 上升沿/高电平触发中断   0 下降沿/低电平触发中断
-
-    __IO uint32_t INTEN; //1 中断使能   0 中断禁止
-
-    __IO uint32_t INTRAWSTAT; //中断检测单元是否检测到了触发中断的条件 1 检测到了中断触发条件    0 没有检测到中断触发条件
-
-    __IO uint32_t INTSTAT; //INTSTAT.PIN0 = INTRAWSTAT.PIN0 & INTEN.PIN0
-
-    __IO uint32_t INTCLR; //写1清除中断标志，只对边沿触发中断有用
-} GPIO_TypeDef;
-
-typedef struct
-{
-    __IO uint32_t LDVAL; //定时器加载值，使能后定时器从此数值开始向下递减计数
-
-    __I uint32_t CVAL; //定时器当前值，LDVAL-CVAL 可计算出计时时长
-
-    __IO uint32_t CTRL;
-} TIMR_TypeDef;
-
-#define TIMR_CTRL_EN_Pos 0 //此位赋1导致TIMR从LDVAL开始向下递减计数
-#define TIMR_CTRL_EN_Msk (0x01 << TIMR_CTRL_EN_Pos)
-#define TIMR_CTRL_CLKSRC_Pos 1 //时钟源：0 内部系统时钟   1 外部引脚脉冲计数
-#define TIMR_CTRL_CLKSRC_Msk (0x01 << TIMR_CTRL_CLKSRC_Pos)
-#define TIMR_CTRL_CASCADE_Pos 2 //1 TIMRx的计数时钟为TIMRx-1的溢出信号
-#define TIMR_CTRL_CASCADE_Msk (0x01 << TIMR_CTRL_CASCADE_Pos)
-
-typedef struct
-{
-    __IO uint32_t PCTRL; //Pulse Control，脉宽测量模块控制寄存器
-
-    __I uint32_t PCVAL; //脉宽测量定时器当前值
-
-    uint32_t RESERVED[2];
-
-    __IO uint32_t IE;
-
-    __IO uint32_t IF;
-
-    __IO uint32_t HALT;
-} TIMRG_TypeDef;
-
-#define TIMRG_PCTRL_EN_Pos 0 //开始测量脉宽，脉宽内32位计数器从0开始向上计数
-#define TIMRG_PCTRL_EN_Msk (0x01 << TIMRG_PCTRL_EN_Pos)
-#define TIMRG_PCTRL_HIGH_Pos 1 //0 测量低电平长度  1 测量高电平长度
-#define TIMRG_PCTRL_HIGH_Msk (0x01 << TIMRG_PCTRL_HIGH_Pos)
-#define TIMRG_PCTRL_CLKSRC_Pos 2 //时钟源：0 内部系统时钟 1 脉宽测量模块变成一个计数器，不再具有脉宽测量功能
-#define TIMRG_PCTRL_CLKSRC_Msk (0x01 << TIMRG_PCTRL_CLKSRC_Pos)
-
-#define TIMRG_IE_TIMR0_Pos 0
-#define TIMRG_IE_TIMR0_Msk (0x01 << TIMRG_IE_TIMR0_Pos)
-#define TIMRG_IE_TIMR1_Pos 1
-#define TIMRG_IE_TIMR1_Msk (0x01 << TIMRG_IE_TIMR1_Pos)
-#define TIMRG_IE_TIMR2_Pos 2
-#define TIMRG_IE_TIMR2_Msk (0x01 << TIMRG_IE_TIMR2_Pos)
-#define TIMRG_IE_TIMR3_Pos 3
-#define TIMRG_IE_TIMR3_Msk (0x01 << TIMRG_IE_TIMR3_Pos)
-#define TIMRG_IE_TIMR4_Pos 4
-#define TIMRG_IE_TIMR4_Msk (0x01 << TIMRG_IE_TIMR4_Pos)
-#define TIMRG_IE_TIMR5_Pos 5
-#define TIMRG_IE_TIMR5_Msk (0x01 << TIMRG_IE_TIMR5_Pos)
-#define TIMRG_IE_PULSE_Pos 16
-#define TIMRG_IE_PULSE_Msk (0x01 << TIMRG_IE_PULSE_Pos)
-
-#define TIMRG_IF_TIMR0_Pos 0 //写1清零
-#define TIMRG_IF_TIMR0_Msk (0x01 << TIMRG_IF_TIMR0_Pos)
-#define TIMRG_IF_TIMR1_Pos 1
-#define TIMRG_IF_TIMR1_Msk (0x01 << TIMRG_IF_TIMR1_Pos)
-#define TIMRG_IF_TIMR2_Pos 2
-#define TIMRG_IF_TIMR2_Msk (0x01 << TIMRG_IF_TIMR2_Pos)
-#define TIMRG_IF_TIMR3_Pos 3
-#define TIMRG_IF_TIMR3_Msk (0x01 << TIMRG_IF_TIMR3_Pos)
-#define TIMRG_IF_TIMR4_Pos 4
-#define TIMRG_IF_TIMR4_Msk (0x01 << TIMRG_IF_TIMR4_Pos)
-#define TIMRG_IF_TIMR5_Pos 5
-#define TIMRG_IF_TIMR5_Msk (0x01 << TIMRG_IF_TIMR5_Pos)
-#define TIMRG_IF_PULSE_Pos 16
-#define TIMRG_IF_PULSE_Msk (0x01 << TIMRG_IF_PULSE_Pos)
-
-#define TIMRG_HALT_TIMR0_Pos 0 //1 暂停计数
-#define TIMRG_HALT_TIMR0_Msk (0x01 << TIMRG_HALT_TIMR0_Pos)
-#define TIMRG_HALT_TIMR1_Pos 1
-#define TIMRG_HALT_TIMR1_Msk (0x01 << TIMRG_HALT_TIMR1_Pos)
-#define TIMRG_HALT_TIMR2_Pos 2
-#define TIMRG_HALT_TIMR2_Msk (0x01 << TIMRG_HALT_TIMR2_Pos)
-#define TIMRG_HALT_TIMR3_Pos 3
-#define TIMRG_HALT_TIMR3_Msk (0x01 << TIMRG_HALT_TIMR3_Pos)
-#define TIMRG_HALT_TIMR4_Pos 4
-#define TIMRG_HALT_TIMR4_Msk (0x01 << TIMRG_HALT_TIMR4_Pos)
-#define TIMRG_HALT_TIMR5_Pos 5
-#define TIMRG_HALT_TIMR5_Msk (0x01 << TIMRG_HALT_TIMR5_Pos)
-
-typedef struct
-{
-    __IO uint32_t DATA;
-
-    __IO uint32_t CTRL;
-
-    __IO uint32_t BAUD;
-
-    __IO uint32_t FIFO;
-
-    __IO uint32_t LINCR;
-
-    union
-    {
-        __IO uint32_t CTSCR;
-
-        __IO uint32_t RTSCR;
-    };
-} UART_TypeDef;
-
-#define UART_DATA_DATA_Pos 0
-#define UART_DATA_DATA_Msk (0x1FF << UART_DATA_DATA_Pos)
-#define UART_DATA_VALID_Pos 9 //当DATA字段有有效的接收数据时，该位硬件置1，读取数据后自动清零
-#define UART_DATA_VALID_Msk (0x01 << UART_DATA_VALID_Pos)
-#define UART_DATA_PAERR_Pos 10 //Parity Error
-#define UART_DATA_PAERR_Msk (0x01 << UART_DATA_PAERR_Pos)
-
-#define UART_CTRL_TXIDLE_Pos 0 //TX IDLE: 0 正在发送数据  1 空闲状态，没有数据发送
-#define UART_CTRL_TXIDLE_Msk (0x01 << UART_CTRL_TXIDLE_Pos)
-#define UART_CTRL_TXFF_Pos 1 //TX FIFO Full
-#define UART_CTRL_TXFF_Msk (0x01 << UART_CTRL_TXFF_Pos)
-#define UART_CTRL_TXIE_Pos 2 //TX 中断使能: 1 TX FF 中数据少于设定个数时产生中断
-#define UART_CTRL_TXIE_Msk (0x01 << UART_CTRL_TXIE_Pos)
-#define UART_CTRL_RXNE_Pos 3 //RX FIFO Not Empty
-#define UART_CTRL_RXNE_Msk (0x01 << UART_CTRL_RXNE_Pos)
-#define UART_CTRL_RXIE_Pos 4 //RX 中断使能: 1 RX FF 中数据达到设定个数时产生中断
-#define UART_CTRL_RXIE_Msk (0x01 << UART_CTRL_RXIE_Pos)
-#define UART_CTRL_RXOV_Pos 5 //RX FIFO Overflow，写1清零
-#define UART_CTRL_RXOV_Msk (0x01 << UART_CTRL_RXOV_Pos)
-#define UART_CTRL_TXDOIE_Pos 6 //TX Done 中断使能，发送FIFO空且发送发送移位寄存器已将最后一位发送出去
-#define UART_CTRL_TXDOIE_Msk (0x01 << UART_CTRL_TXDOIE_Pos)
-#define UART_CTRL_EN_Pos 9
-#define UART_CTRL_EN_Msk (0x01 << UART_CTRL_EN_Pos)
-#define UART_CTRL_LOOP_Pos 10
-#define UART_CTRL_LOOP_Msk (0x01 << UART_CTRL_LOOP_Pos)
-#define UART_CTRL_BAUDEN_Pos 13 //必须写1
-#define UART_CTRL_BAUDEN_Msk (0x01 << UART_CTRL_BAUDEN_Pos)
-#define UART_CTRL_TOIE_Pos 14 //TimeOut 中断使能，接收到上个字符后，超过 TOTIME/BAUDRAUD 秒没有接收到新的数据
-#define UART_CTRL_TOIE_Msk (0x01 << UART_CTRL_TOIE_Pos)
-#define UART_CTRL_BRKDET_Pos 15 //LIN Break Detect，检测到LIN Break，即RX线上检测到连续11位低电平
-#define UART_CTRL_BRKDET_Msk (0x01 << UART_CTRL_BRKDET_Pos)
-#define UART_CTRL_BRKIE_Pos 16 //LIN Break Detect 中断使能
-#define UART_CTRL_BRKIE_Msk (0x01 << UART_CTRL_BRKIE_Pos)
-#define UART_CTRL_GENBRK_Pos 17 //Generate LIN Break，发送LIN Break
-#define UART_CTRL_GENBRK_Msk (0x01 << UART_CTRL_GENBRK_Pos)
-#define UART_CTRL_DATA9b_Pos 18 //1 9位数据位    0 8位数据位
-#define UART_CTRL_DATA9b_Msk (0x01 << UART_CTRL_DATA9b_Pos)
-#define UART_CTRL_PARITY_Pos 19 //000 无校验    001 奇校验   011 偶校验   101 固定为1    111 固定为0
-#define UART_CTRL_PARITY_Msk (0x07 << UART_CTRL_PARITY_Pos)
-#define UART_CTRL_STOP2b_Pos 22 //1 2位停止位    0 1位停止位
-#define UART_CTRL_STOP2b_Msk (0x03 << UART_CTRL_STOP2b_Pos)
-#define UART_CTRL_TOTIME_Pos 24 //TimeOut 时长 = TOTIME/(BAUDRAUD/10) 秒
-#define UART_CTRL_TOTIME_Msk (0xFFu << UART_CTRL_TOTIME_Pos)
-
-#define UART_BAUD_BAUD_Pos 0 //串口波特率 = SYS_Freq/16/BAUD - 1
-#define UART_BAUD_BAUD_Msk (0x3FFF << UART_BAUD_BAUD_Pos)
-#define UART_BAUD_TXD_Pos 14 //通过此位可直接读取串口TXD引脚上的电平
-#define UART_BAUD_TXD_Msk (0x01 << UART_BAUD_TXD_Pos)
-#define UART_BAUD_RXD_Pos 15 //通过此位可直接读取串口RXD引脚上的电平
-#define UART_BAUD_RXD_Msk (0x01 << UART_BAUD_RXD_Pos)
-#define UART_BAUD_RXTOIF_Pos 16 //接收&超时的中断标志 = RXIF | TOIF
-#define UART_BAUD_RXTOIF_Msk (0x01 << UART_BAUD_RXTOIF_Pos)
-#define UART_BAUD_TXIF_Pos 17 //发送中断标志 = TXTHRF & TXIE
-#define UART_BAUD_TXIF_Msk (0x01 << UART_BAUD_TXIF_Pos)
-#define UART_BAUD_BRKIF_Pos 18 //LIN Break Detect 中断标志，检测到LIN Break时若BRKIE=1，此位由硬件置位
-#define UART_BAUD_BRKIF_Msk (0x01 << UART_BAUD_BRKIF_Pos)
-#define UART_BAUD_RXTHRF_Pos 19 //RX FIFO Threshold Flag，RX FIFO中数据达到设定个数（RXLVL >= RXTHR）时硬件置1
-#define UART_BAUD_RXTHRF_Msk (0x01 << UART_BAUD_RXTHRF_Pos)
-#define UART_BAUD_TXTHRF_Pos 20 //TX FIFO Threshold Flag，TX FIFO中数据少于设定个数（TXLVL <= TXTHR）时硬件置1
-#define UART_BAUD_TXTHRF_Msk (0x01 << UART_BAUD_TXTHRF_Pos)
-#define UART_BAUD_TOIF_Pos 21 //TimeOut 中断标志，超过 TOTIME/BAUDRAUD 秒没有接收到新的数据时若TOIE=1，此位由硬件置位
-#define UART_BAUD_TOIF_Msk (0x01 << UART_BAUD_TOIF_Pos)
-#define UART_BAUD_RXIF_Pos 22 //接收中断标志 = RXTHRF & RXIE
-#define UART_BAUD_RXIF_Msk (0x01 << UART_BAUD_RXIF_Pos)
-#define UART_BAUD_ABREN_Pos 23 //Auto Baudrate Enable，写1启动自动波特率校准，完成后自动清零
-#define UART_BAUD_ABREN_Msk (0x01 << UART_BAUD_ABREN_Pos)
-#define UART_BAUD_ABRBIT_Pos 24 /*Auto Baudrate Bit，用于计算波特率的检测位长，0 1位，通过测起始位           脉宽计算波特率，要求发送端发送0xFF \
-                                //                                             1 2位，通过测起始位加1位数据位脉宽计算波特率，要求发送端发送0xFE          \
-                                //                                             1 4位，通过测起始位加3位数据位脉宽计算波特率，要求发送端发送0xF8          \
-                                //                                             1 8位，通过测起始位加7位数据位脉宽计算波特率，要求发送端发送0x80 */
-#define UART_BAUD_ABRBIT_Msk (0x03 << UART_BAUD_ABRBIT_Pos)
-#define UART_BAUD_ABRERR_Pos 26 //Auto Baudrate Error，0 自动波特率校准成功     1 自动波特率校准失败
-#define UART_BAUD_ABRERR_Msk (0x01 << UART_BAUD_ABRERR_Pos)
-#define UART_BAUD_TXDOIF_Pos 27 //TX Done 中断标志，发送FIFO空且发送发送移位寄存器已将最后一位发送出去
-#define UART_BAUD_TXDOIF_Msk (0x01 << UART_BAUD_TXDOIF_Pos)
-
-#define UART_FIFO_RXLVL_Pos 0 //RX FIFO Level，RX FIFO 中字符个数
-#define UART_FIFO_RXLVL_Msk (0xFF << UART_FIFO_RXLVL_Pos)
-#define UART_FIFO_TXLVL_Pos 8 //TX FIFO Level，TX FIFO 中字符个数
-#define UART_FIFO_TXLVL_Msk (0xFF << UART_FIFO_TXLVL_Pos)
-#define UART_FIFO_RXTHR_Pos 16 //RX FIFO Threshold，RX中断触发门限，中断使能时 RXLVL >= RXTHR 触发RX中断
-#define UART_FIFO_RXTHR_Msk (0xFF << UART_FIFO_RXTHR_Pos)
-#define UART_FIFO_TXTHR_Pos 24 //TX FIFO Threshold，TX中断触发门限，中断使能时 TXLVL <= TXTHR 触发TX中断
-#define UART_FIFO_TXTHR_Msk (0xFFu << UART_FIFO_TXTHR_Pos)
-
-#define UART_LINCR_BRKDETIE_Pos 0 //检测到LIN Break中断使能
-#define UART_LINCR_BRKDETIE_Msk (0x01 << UART_LINCR_BRKDETIE_Pos)
-#define UART_LINCR_BRKDETIF_Pos 1 //检测到LIN Break中断状态
-#define UART_LINCR_BRKDETIF_Msk (0x01 << UART_LINCR_BRKDETIF_Pos)
-#define UART_LINCR_GENBRKIE_Pos 2 //发送LIN Break完成中断使能
-#define UART_LINCR_GENBRKIE_Msk (0x01 << UART_LINCR_GENBRKIE_Pos)
-#define UART_LINCR_GENBRKIF_Pos 3 //发送LIN Break完成中断状态
-#define UART_LINCR_GENBRKIF_Msk (0x01 << UART_LINCR_GENBRKIF_Pos)
-#define UART_LINCR_GENBRK_Pos 4 //发送LIN Break，发送完成自动清零
-#define UART_LINCR_GENBRK_Msk (0x01 << UART_LINCR_GENBRK_Pos)
-
-#define UART_CTSCR_EN_Pos 0 //CTS流控使能
-#define UART_CTSCR_EN_Msk (0x01 << UART_CTSCR_EN_Pos)
-#define UART_CTSCR_POL_Pos 2 //CTS信号极性，0 低有效，CTS输入为低表示可以发送数据
-#define UART_CTSCR_POL_Msk (0x01 << UART_CTSCR_POL_Pos)
-#define UART_CTSCR_STAT_Pos 7 //CTS信号的当前状态
-#define UART_CTSCR_STAT_Msk (0x01 << UART_CTSCR_STAT_Pos)
-
-#define UART_RTSCR_EN_Pos 1 //RTS流控使能
-#define UART_RTSCR_EN_Msk (0x01 << UART_RTSCR_EN_Pos)
-#define UART_RTSCR_POL_Pos 3 //RTS信号极性    0 低有效，RTS输入为低表示可以接收数据
-#define UART_RTSCR_POL_Msk (0x01 << UART_RTSCR_POL_Pos)
-#define UART_RTSCR_THR_Pos 4 //RTS流控的触发阈值    0 1字节    1 2字节    2 4字节    3 6字节
-#define UART_RTSCR_THR_Msk (0x07 << UART_RTSCR_THR_Pos)
-#define UART_RTSCR_STAT_Pos 8 //RTS信号的当前状态
-#define UART_RTSCR_STAT_Msk (0x01 << UART_RTSCR_STAT_Pos)
-
-typedef struct
-{
-    __IO uint32_t CTRL;
-
-    __IO uint32_t DATA;
-
-    __IO uint32_t STAT;
-
-    __IO uint32_t IE;
-
-    __IO uint32_t IF;
-} SPI_TypeDef;
-
-#define SPI_CTRL_CLKDIV_Pos 0 //Clock Divider, SPI工作时钟 = SYS_Freq/pow(2, CLKDIV+2)
-#define SPI_CTRL_CLKDIV_Msk (0x07 << SPI_CTRL_CLKDIV_Pos)
-#define SPI_CTRL_EN_Pos 3
-#define SPI_CTRL_EN_Msk (0x01 << SPI_CTRL_EN_Pos)
-#define SPI_CTRL_SIZE_Pos 4 //Data Size Select, 取值3--15，表示4--16位
-#define SPI_CTRL_SIZE_Msk (0x0F << SPI_CTRL_SIZE_Pos)
-#define SPI_CTRL_CPHA_Pos 8 //0 在SCLK的第一个跳变沿采样数据    1 在SCLK的第二个跳变沿采样数据
-#define SPI_CTRL_CPHA_Msk (0x01 << SPI_CTRL_CPHA_Pos)
-#define SPI_CTRL_CPOL_Pos 9 //0 空闲状态下SCLK为低电平         1 空闲状态下SCLK为高电平
-#define SPI_CTRL_CPOL_Msk (0x01 << SPI_CTRL_CPOL_Pos)
-#define SPI_CTRL_FFS_Pos 10 //Frame Format Select, 0 SPI    1 TI SSI    2 SPI   3 SPI
-#define SPI_CTRL_FFS_Msk (0x03 << SPI_CTRL_FFS_Pos)
-#define SPI_CTRL_MSTR_Pos 12 //Master, 1 主模式    0 从模式
-#define SPI_CTRL_MSTR_Msk (0x01 << SPI_CTRL_MSTR_Pos)
-#define SPI_CTRL_FAST_Pos 13 //1 SPI工作时钟 = SYS_Freq/2    0 SPI工作时钟由SPI->CTRL.CLKDIV设置
-#define SPI_CTRL_FAST_Msk (0x01 << SPI_CTRL_FAST_Pos)
-#define SPI_CTRL_FILTE_Pos 16 //1 对SPI输入信号进行去抖操作    0 对SPI输入信号不进行去抖操作
-#define SPI_CTRL_FILTE_Msk (0x01 << SPI_CTRL_FILTE_Pos)
-#define SPI_CTRL_SSN_H_Pos 17 //0 传输过程中SSN始终为0       1 传输过程中每字符之间会将SSN拉高半个SCLK周期
-#define SPI_CTRL_SSN_H_Msk (0x01 << SPI_CTRL_SSN_H_Pos)
-#define SPI_CTRL_TFCLR_Pos 24 //TX FIFO Clear
-#define SPI_CTRL_TFCLR_Msk (0x01 << SPI_CTRL_TFCLR_Pos)
-#define SPI_CTRL_RFCLR_Pos 25 //RX FIFO Clear
-#define SPI_CTRL_RFCLR_Msk (0x01 << SPI_CTRL_RFCLR_Pos)
-
-#define SPI_STAT_WTC_Pos 0 //Word Transmit Complete，每传输完成一个数据字由硬件置1，软件写1清零
-#define SPI_STAT_WTC_Msk (0x01 << SPI_STAT_WTC_Pos)
-#define SPI_STAT_TFE_Pos 1 //发送FIFO Empty
-#define SPI_STAT_TFE_Msk (0x01 << SPI_STAT_TFE_Pos)
-#define SPI_STAT_TFNF_Pos 2 //发送FIFO Not Full
-#define SPI_STAT_TFNF_Msk (0x01 << SPI_STAT_TFNF_Pos)
-#define SPI_STAT_RFNE_Pos 3 //接收FIFO Not Empty
-#define SPI_STAT_RFNE_Msk (0x01 << SPI_STAT_RFNE_Pos)
-#define SPI_STAT_RFF_Pos 4 //接收FIFO Full
-#define SPI_STAT_RFF_Msk (0x01 << SPI_STAT_RFF_Pos)
-#define SPI_STAT_RFOVF_Pos 5 //接收FIFO Overflow
-#define SPI_STAT_RFOVF_Msk (0x01 << SPI_STAT_RFOVF_Pos)
-#define SPI_STAT_TFLVL_Pos 6 //发送FIFO中数据个数， 0 TFNF=0时表示FIFO内有8个数据，TFNF=1时表示FIFO内有0个数据   1--7 FIFO内有1--7个数据
-#define SPI_STAT_TFLVL_Msk (0x07 << SPI_STAT_TFLVL_Pos)
-#define SPI_STAT_RFLVL_Pos 9 //接收FIFO中数据个数， 0 RFF=1时表示FIFO内有8个数据， RFF=0时表示FIFO内有0个数据    1--7 FIFO内有1--7个数据
-#define SPI_STAT_RFLVL_Msk (0x07 << SPI_STAT_RFLVL_Pos)
-#define SPI_STAT_BUSY_Pos 15
-#define SPI_STAT_BUSY_Msk (0x01 << SPI_STAT_BUSY_Pos)
-
-#define SPI_IE_RFOVF_Pos 0
-#define SPI_IE_RFOVF_Msk (0x01 << SPI_IE_RFOVF_Pos)
-#define SPI_IE_RFF_Pos 1
-#define SPI_IE_RFF_Msk (0x01 << SPI_IE_RFF_Pos)
-#define SPI_IE_RFHF_Pos 2
-#define SPI_IE_RFHF_Msk (0x01 << SPI_IE_RFHF_Pos)
-#define SPI_IE_TFE_Pos 3
-#define SPI_IE_TFE_Msk (0x01 << SPI_IE_TFE_Pos)
-#define SPI_IE_TFHF_Pos 4
-#define SPI_IE_TFHF_Msk (0x01 << SPI_IE_TFHF_Pos)
-#define SPI_IE_WTC_Pos 8 //Word Transmit Complete
-#define SPI_IE_WTC_Msk (0x01 << SPI_IE_WTC_Pos)
-#define SPI_IE_FTC_Pos 9 //Frame Transmit Complete
-#define SPI_IE_FTC_Msk (0x01 << SPI_IE_FTC_Pos)
-
-#define SPI_IF_RFOVF_Pos 0 //写1清零
-#define SPI_IF_RFOVF_Msk (0x01 << SPI_IF_RFOVF_Pos)
-#define SPI_IF_RFF_Pos 1
-#define SPI_IF_RFF_Msk (0x01 << SPI_IF_RFF_Pos)
-#define SPI_IF_RFHF_Pos 2
-#define SPI_IF_RFHF_Msk (0x01 << SPI_IF_RFHF_Pos)
-#define SPI_IF_TFE_Pos 3
-#define SPI_IF_TFE_Msk (0x01 << SPI_IF_TFE_Pos)
-#define SPI_IF_TFHF_Pos 4
-#define SPI_IF_TFHF_Msk (0x01 << SPI_IF_TFHF_Pos)
-#define SPI_IF_WTC_Pos 8 //Word Transmit Complete，每传输完成一个数据字由硬件置1
-#define SPI_IF_WTC_Msk (0x01 << SPI_IF_WTC_Pos)
-#define SPI_IF_FTC_Pos 9 //Frame Transmit Complete，WTC置位时若TX FIFO是空的，则FTC置位
-#define SPI_IF_FTC_Msk (0x01 << SPI_IF_FTC_Pos)
-
-typedef struct
-{
-    __IO uint32_t CLKDIV; //[15:0] 须将内部工作频率分到SCL频率的5倍，即CLKDIV = SYS_Freq/5/SCL_Freq - 1
-
-    __IO uint32_t CTRL;
-
-    __IO uint32_t MSTDAT;
-
-    __IO uint32_t MSTCMD;
-
-    __IO uint32_t SLVCR;
-
-    __IO uint32_t SLVIF;
-
-    __IO uint32_t SLVTX;
-
-    __IO uint32_t SLVRX;
-} I2C_TypeDef;
-
-#define I2C_CTRL_MSTIE_Pos 6
-#define I2C_CTRL_MSTIE_Msk (0x01 << I2C_CTRL_MSTIE_Pos)
-#define I2C_CTRL_EN_Pos 7
-#define I2C_CTRL_EN_Msk (0x01 << I2C_CTRL_EN_Pos)
-
-#define I2C_MSTCMD_IF_Pos 0 //1 有等待处理的中断，写1清零   有两种情况下此位硬件置位：1、一个字节传输完成  2、总线访问权丢失
-#define I2C_MSTCMD_IF_Msk (0x01 << I2C_MSTCMD_IF_Pos)
-#define I2C_MSTCMD_TIP_Pos 1 //Transmission In Process
-#define I2C_MSTCMD_TIP_Msk (0x01 << I2C_MSTCMD_TIP_Pos)
-#define I2C_MSTCMD_ACK_Pos 3 //接收模式下，0 向发送端反馈ACK    1 向发送端反馈NACK
-#define I2C_MSTCMD_ACK_Msk (0x01 << I2C_MSTCMD_ACK_Pos)
-#define I2C_MSTCMD_WR_Pos 4 //    向Slave写数据时，把这一位写1，自动清零
-#define I2C_MSTCMD_WR_Msk (0x01 << I2C_MSTCMD_WR_Pos)
-#define I2C_MSTCMD_RD_Pos 5 //写：从Slave读数据时，把这一位写1，自动清零  读：当I2C模块失去总线的访问权时硬件置1
-#define I2C_MSTCMD_RD_Msk (0x01 << I2C_MSTCMD_RD_Pos)
-#define I2C_MSTCMD_BUSY_Pos 6 //读：当检测到START之后，这一位变1；当检测到STOP之后，这一位变0
-#define I2C_MSTCMD_BUSY_Msk (0x01 << I2C_MSTCMD_BUSY_Pos)
-#define I2C_MSTCMD_STO_Pos 6 //写：产生STOP，自动清零
-#define I2C_MSTCMD_STO_Msk (0x01 << I2C_MSTCMD_STO_Pos)
-#define I2C_MSTCMD_RXACK_Pos 7 //读：接收到的Slave的ACK位，0 收到ACK   1 收到NACK
-#define I2C_MSTCMD_RXACK_Msk (0x01 << I2C_MSTCMD_RXACK_Pos)
-#define I2C_MSTCMD_STA_Pos 7 //写：产生START，自动清零
-#define I2C_MSTCMD_STA_Msk (0x01 << I2C_MSTCMD_STA_Pos)
-
-#define I2C_SLVCR_IM_RXEND_Pos 0 //接收完成中断禁止
-#define I2C_SLVCR_IM_RXEND_Msk (0x01 << I2C_SLVCR_IM_RXEND_Pos)
-#define I2C_SLVCR_IM_TXEND_Pos 1 //发送完成中断禁止
-#define I2C_SLVCR_IM_TXEND_Msk (0x01 << I2C_SLVCR_IM_TXEND_Pos)
-#define I2C_SLVCR_IM_STADET_Pos 2 //检测到起始中断禁止
-#define I2C_SLVCR_IM_STADET_Msk (0x01 << I2C_SLVCR_IM_STADET_Pos)
-#define I2C_SLVCR_IM_STODET_Pos 3 //检测到停止中断禁止
-#define I2C_SLVCR_IM_STODET_Msk (0x01 << I2C_SLVCR_IM_STODET_Pos)
-#define I2C_SLVCR_IM_RDREQ_Pos 4 //接收到读请求中断禁止
-#define I2C_SLVCR_IM_RDREQ_Msk (0x01 << I2C_SLVCR_IM_RDREQ_Pos)
-#define I2C_SLVCR_IM_WRREQ_Pos 5 //接收到写请求中断禁止
-#define I2C_SLVCR_IM_WRREQ_Msk (0x01 << I2C_SLVCR_IM_WRREQ_Pos)
-#define I2C_SLVCR_ADDR7b_Pos 16 //1 7位地址模式    0 10位地址模式
-#define I2C_SLVCR_ADDR7b_Msk (0x01 << I2C_SLVCR_ADDR7b_Pos)
-#define I2C_SLVCR_ACK_Pos 17 //1 应答ACK    0 应答NACK
-#define I2C_SLVCR_ACK_Msk (0x01 << I2C_SLVCR_ACK_Pos)
-#define I2C_SLVCR_SLAVE_Pos 18 //1 从机模式   0 主机模式
-#define I2C_SLVCR_SLAVE_Msk (0x01 << I2C_SLVCR_SLAVE_Pos)
-#define I2C_SLVCR_DEBOUNCE_Pos 19 //去抖动使能
-#define I2C_SLVCR_DEBOUNCE_Msk (0x01 << I2C_SLVCR_DEBOUNCE_Pos)
-#define I2C_SLVCR_ADDR_Pos 20 //从机地址
-#define I2C_SLVCR_ADDR_Msk (0x3FF << I2C_SLVCR_ADDR_Pos)
-
-#define I2C_SLVIF_RXEND_Pos 0 //接收完成中断标志，写1清零
-#define I2C_SLVIF_RXEND_Msk (0x01 << I2C_SLVIF_RXEND_Pos)
-#define I2C_SLVIF_TXEND_Pos 1 //发送完成中断标志，写1清零
-#define I2C_SLVIF_TXEND_Msk (0x01 << I2C_SLVIF_TXEND_Pos)
-#define I2C_SLVIF_STADET_Pos 2 //检测到起始中断标志，写1清零
-#define I2C_SLVIF_STADET_Msk (0x01 << I2C_SLVIF_STADET_Pos)
-#define I2C_SLVIF_STODET_Pos 3 //检测到停止中断标志，写1清零
-#define I2C_SLVIF_STODET_Msk (0x01 << I2C_SLVIF_STODET_Pos)
-#define I2C_SLVIF_RDREQ_Pos 4 //接收到读请求中断标志
-#define I2C_SLVIF_RDREQ_Msk (0x01 << I2C_SLVIF_RDREQ_Pos)
-#define I2C_SLVIF_WRREQ_Pos 5 //接收到写请求中断标志
-#define I2C_SLVIF_WRREQ_Msk (0x01 << I2C_SLVIF_WRREQ_Pos)
-#define I2C_SLVIF_ACTIVE_Pos 6 //slave 有效
-#define I2C_SLVIF_ACTIVE_Msk (0x01 << I2C_SLVIF_ACTIVE_Pos)
-
-typedef struct
-{
-    __IO uint32_t CTRL;
-
-    __IO uint32_t START;
-
-    __IO uint32_t IE;
-
-    __IO uint32_t IF;
-
-    struct
-    {
-        __IO uint32_t STAT;
-
-        __IO uint32_t DATA;
-
-        uint32_t RESERVED[2];
-    } CH[8];
-
-    __IO uint32_t CTRL1;
-
-    __IO uint32_t CTRL2;
-
-    uint32_t RESERVED[2];
-
-    __IO uint32_t CALIBSET;
-
-    __IO uint32_t CALIBEN;
-} ADC_TypeDef;
-
-#define ADC_CTRL_CH0_Pos 0 //通道选中
-#define ADC_CTRL_CH0_Msk (0x01 << ADC_CTRL_CH0_Pos)
-#define ADC_CTRL_CH1_Pos 1
-#define ADC_CTRL_CH1_Msk (0x01 << ADC_CTRL_CH1_Pos)
-#define ADC_CTRL_CH2_Pos 2
-#define ADC_CTRL_CH2_Msk (0x01 << ADC_CTRL_CH2_Pos)
-#define ADC_CTRL_CH3_Pos 3
-#define ADC_CTRL_CH3_Msk (0x01 << ADC_CTRL_CH3_Pos)
-#define ADC_CTRL_CH4_Pos 4
-#define ADC_CTRL_CH4_Msk (0x01 << ADC_CTRL_CH4_Pos)
-#define ADC_CTRL_CH5_Pos 5
-#define ADC_CTRL_CH5_Msk (0x01 << ADC_CTRL_CH5_Pos)
-#define ADC_CTRL_CH6_Pos 6
-#define ADC_CTRL_CH6_Msk (0x01 << ADC_CTRL_CH6_Pos)
-#define ADC_CTRL_CH7_Pos 7
-#define ADC_CTRL_CH7_Msk (0x01 << ADC_CTRL_CH7_Pos)
-#define ADC_CTRL_AVG_Pos 8 //0 1次采样   1 2次采样取平均值      3 4次采样取平均值      7 8次采样取平均值      15 16次采样取平均值
-#define ADC_CTRL_AVG_Msk (0x0F << ADC_CTRL_AVG_Pos)
-#define ADC_CTRL_EN_Pos 12
-#define ADC_CTRL_EN_Msk (0x01 << ADC_CTRL_EN_Pos)
-#define ADC_CTRL_CONT_Pos 13                          //Continuous conversion，只在软件启动模式下有效，0 单次转换，转换完成后START位自动清除停止转换
-#define ADC_CTRL_CONT_Msk (0x01 << ADC_CTRL_CONT_Pos) //   1 连续转换，启动后一直采样、转换，直到软件清除START位
-#define ADC_CTRL_TRIG_Pos 14                          //转换触发方式：0 软件启动转换   1 PWM触发
-#define ADC_CTRL_TRIG_Msk (0x01 << ADC_CTRL_TRIG_Pos)
-#define ADC_CTRL_CLKSRC_Pos 15 //0 VCO    1 HRC
-#define ADC_CTRL_CLKSRC_Msk (0x01 << ADC_CTRL_CLKSRC_Pos)
-#define ADC_CTRL_FIFOCLR_Pos 24 //[24] CH0_FIFO_CLR   [25] CH1_FIFO_CLR    ...    [31] CH7_FIFO_CLR
-#define ADC_CTRL_FIFOCLR_Msk (0xFFu << ADC_CTRL_FIFOCLR_Pos)
-
-#define ADC_START_GO_Pos 0 //软件触发模式下，写1启动ADC采样和转换，在单次模式下转换完成后硬件自动清零，在扫描模式下必须软件写0停止ADC转换
-#define ADC_START_GO_Msk (0x01 << ADC_START_GO_Pos)
-#define ADC_START_BUSY_Pos 4
-#define ADC_START_BUSY_Msk (0x01 << ADC_START_BUSY_Pos)
-
-#define ADC_IE_CH0EOC_Pos 0 //End Of Convertion
-#define ADC_IE_CH0EOC_Msk (0x01 << ADC_IE_CH0EOC_Pos)
-#define ADC_IE_CH0OVF_Pos 1 //Overflow
-#define ADC_IE_CH0OVF_Msk (0x01 << ADC_IE_CH0OVF_Pos)
-#define ADC_IE_CH0HFULL_Pos 2 //FIFO Half Full
-#define ADC_IE_CH0HFULL_Msk (0x01 << ADC_IE_CH0HFULL_Pos)
-#define ADC_IE_CH0FULL_Pos 3 //FIFO Full
-#define ADC_IE_CH0FULL_Msk (0x01 << ADC_IE_CH0FULL_Pos)
-#define ADC_IE_CH1EOC_Pos 4
-#define ADC_IE_CH1EOC_Msk (0x01 << ADC_IE_CH1EOC_Pos)
-#define ADC_IE_CH1OVF_Pos 5
-#define ADC_IE_CH1OVF_Msk (0x01 << ADC_IE_CH1OVF_Pos)
-#define ADC_IE_CH1HFULL_Pos 6
-#define ADC_IE_CH1HFULL_Msk (0x01 << ADC_IE_CH1HFULL_Pos)
-#define ADC_IE_CH1FULL_Pos 7
-#define ADC_IE_CH1FULL_Msk (0x01 << ADC_IE_CH1FULL_Pos)
-#define ADC_IE_CH2EOC_Pos 8
-#define ADC_IE_CH2EOC_Msk (0x01 << ADC_IE_CH2EOC_Pos)
-#define ADC_IE_CH2OVF_Pos 9
-#define ADC_IE_CH2OVF_Msk (0x01 << ADC_IE_CH2OVF_Pos)
-#define ADC_IE_CH2HFULL_Pos 10
-#define ADC_IE_CH2HFULL_Msk (0x01 << ADC_IE_CH2HFULL_Pos)
-#define ADC_IE_CH2FULL_Pos 11
-#define ADC_IE_CH2FULL_Msk (0x01 << ADC_IE_CH2FULL_Pos)
-#define ADC_IE_CH3EOC_Pos 12
-#define ADC_IE_CH3EOC_Msk (0x01 << ADC_IE_CH3EOC_Pos)
-#define ADC_IE_CH3OVF_Pos 13
-#define ADC_IE_CH3OVF_Msk (0x01 << ADC_IE_CH3OVF_Pos)
-#define ADC_IE_CH3HFULL_Pos 14
-#define ADC_IE_CH3HFULL_Msk (0x01 << ADC_IE_CH3HFULL_Pos)
-#define ADC_IE_CH3FULL_Pos 15
-#define ADC_IE_CH3FULL_Msk (0x01 << ADC_IE_CH3FULL_Pos)
-#define ADC_IE_CH4EOC_Pos 16
-#define ADC_IE_CH4EOC_Msk (0x01 << ADC_IE_CH4EOC_Pos)
-#define ADC_IE_CH4OVF_Pos 17
-#define ADC_IE_CH4OVF_Msk (0x01 << ADC_IE_CH4OVF_Pos)
-#define ADC_IE_CH4HFULL_Pos 18
-#define ADC_IE_CH4HFULL_Msk (0x01 << ADC_IE_CH4HFULL_Pos)
-#define ADC_IE_CH4FULL_Pos 19
-#define ADC_IE_CH4FULL_Msk (0x01 << ADC_IE_CH4FULL_Pos)
-#define ADC_IE_CH5EOC_Pos 20
-#define ADC_IE_CH5EOC_Msk (0x01 << ADC_IE_CH5EOC_Pos)
-#define ADC_IE_CH5OVF_Pos 21
-#define ADC_IE_CH5OVF_Msk (0x01 << ADC_IE_CH5OVF_Pos)
-#define ADC_IE_CH5HFULL_Pos 22
-#define ADC_IE_CH5HFULL_Msk (0x01 << ADC_IE_CH5HFULL_Pos)
-#define ADC_IE_CH5FULL_Pos 23
-#define ADC_IE_CH5FULL_Msk (0x01 << ADC_IE_CH5FULL_Pos)
-#define ADC_IE_CH6EOC_Pos 24
-#define ADC_IE_CH6EOC_Msk (0x01 << ADC_IE_CH6EOC_Pos)
-#define ADC_IE_CH6OVF_Pos 25
-#define ADC_IE_CH6OVF_Msk (0x01 << ADC_IE_CH6OVF_Pos)
-#define ADC_IE_CH6HFULL_Pos 26
-#define ADC_IE_CH6HFULL_Msk (0x01 << ADC_IE_CH6HFULL_Pos)
-#define ADC_IE_CH6FULL_Pos 27
-#define ADC_IE_CH6FULL_Msk (0x01 << ADC_IE_CH6FULL_Pos)
-#define ADC_IE_CH7EOC_Pos 28
-#define ADC_IE_CH7EOC_Msk (0x01 << ADC_IE_CH7EOC_Pos)
-#define ADC_IE_CH7OVF_Pos 29
-#define ADC_IE_CH7OVF_Msk (0x01 << ADC_IE_CH7OVF_Pos)
-#define ADC_IE_CH7HFULL_Pos 30
-#define ADC_IE_CH7HFULL_Msk (0x01 << ADC_IE_CH7HFULL_Pos)
-#define ADC_IE_CH7FULL_Pos 31
-#define ADC_IE_CH7FULL_Msk (0x01u << ADC_IE_CH7FULL_Pos)
-
-#define ADC_IF_CH0EOC_Pos 0 //写1清零
-#define ADC_IF_CH0EOC_Msk (0x01 << ADC_IF_CH0EOC_Pos)
-#define ADC_IF_CH0OVF_Pos 1 //写1清零
-#define ADC_IF_CH0OVF_Msk (0x01 << ADC_IF_CH0OVF_Pos)
-#define ADC_IF_CH0HFULL_Pos 2 //写1清零
-#define ADC_IF_CH0HFULL_Msk (0x01 << ADC_IF_CH0HFULL_Pos)
-#define ADC_IF_CH0FULL_Pos 3 //写1清零
-#define ADC_IF_CH0FULL_Msk (0x01 << ADC_IF_CH0FULL_Pos)
-#define ADC_IF_CH1EOC_Pos 4
-#define ADC_IF_CH1EOC_Msk (0x01 << ADC_IF_CH1EOC_Pos)
-#define ADC_IF_CH1OVF_Pos 5
-#define ADC_IF_CH1OVF_Msk (0x01 << ADC_IF_CH1OVF_Pos)
-#define ADC_IF_CH1HFULL_Pos 6
-#define ADC_IF_CH1HFULL_Msk (0x01 << ADC_IF_CH1HFULL_Pos)
-#define ADC_IF_CH1FULL_Pos 7
-#define ADC_IF_CH1FULL_Msk (0x01 << ADC_IF_CH1FULL_Pos)
-#define ADC_IF_CH2EOC_Pos 8
-#define ADC_IF_CH2EOC_Msk (0x01 << ADC_IF_CH2EOC_Pos)
-#define ADC_IF_CH2OVF_Pos 9
-#define ADC_IF_CH2OVF_Msk (0x01 << ADC_IF_CH2OVF_Pos)
-#define ADC_IF_CH2HFULL_Pos 10
-#define ADC_IF_CH2HFULL_Msk (0x01 << ADC_IF_CH2HFULL_Pos)
-#define ADC_IF_CH2FULL_Pos 11
-#define ADC_IF_CH2FULL_Msk (0x01 << ADC_IF_CH2FULL_Pos)
-#define ADC_IF_CH3EOC_Pos 12
-#define ADC_IF_CH3EOC_Msk (0x01 << ADC_IF_CH3EOC_Pos)
-#define ADC_IF_CH3OVF_Pos 13
-#define ADC_IF_CH3OVF_Msk (0x01 << ADC_IF_CH3OVF_Pos)
-#define ADC_IF_CH3HFULL_Pos 14
-#define ADC_IF_CH3HFULL_Msk (0x01 << ADC_IF_CH3HFULL_Pos)
-#define ADC_IF_CH3FULL_Pos 15
-#define ADC_IF_CH3FULL_Msk (0x01 << ADC_IF_CH3FULL_Pos)
-#define ADC_IF_CH4EOC_Pos 16
-#define ADC_IF_CH4EOC_Msk (0x01 << ADC_IF_CH4EOC_Pos)
-#define ADC_IF_CH4OVF_Pos 17
-#define ADC_IF_CH4OVF_Msk (0x01 << ADC_IF_CH4OVF_Pos)
-#define ADC_IF_CH4HFULL_Pos 18
-#define ADC_IF_CH4HFULL_Msk (0x01 << ADC_IF_CH4HFULL_Pos)
-#define ADC_IF_CH4FULL_Pos 19
-#define ADC_IF_CH4FULL_Msk (0x01 << ADC_IF_CH4FULL_Pos)
-#define ADC_IF_CH5EOC_Pos 20
-#define ADC_IF_CH5EOC_Msk (0x01 << ADC_IF_CH5EOC_Pos)
-#define ADC_IF_CH5OVF_Pos 21
-#define ADC_IF_CH5OVF_Msk (0x01 << ADC_IF_CH5OVF_Pos)
-#define ADC_IF_CH5HFULL_Pos 22
-#define ADC_IF_CH5HFULL_Msk (0x01 << ADC_IF_CH5HFULL_Pos)
-#define ADC_IF_CH5FULL_Pos 23
-#define ADC_IF_CH5FULL_Msk (0x01 << ADC_IF_CH5FULL_Pos)
-#define ADC_IF_CH6EOC_Pos 24
-#define ADC_IF_CH6EOC_Msk (0x01 << ADC_IF_CH6EOC_Pos)
-#define ADC_IF_CH6OVF_Pos 25
-#define ADC_IF_CH6OVF_Msk (0x01 << ADC_IF_CH6OVF_Pos)
-#define ADC_IF_CH6HFULL_Pos 26
-#define ADC_IF_CH6HFULL_Msk (0x01 << ADC_IF_CH6HFULL_Pos)
-#define ADC_IF_CH6FULL_Pos 27
-#define ADC_IF_CH6FULL_Msk (0x01 << ADC_IF_CH6FULL_Pos)
-#define ADC_IF_CH7EOC_Pos 28
-#define ADC_IF_CH7EOC_Msk (0x01 << ADC_IF_CH7EOC_Pos)
-#define ADC_IF_CH7OVF_Pos 29
-#define ADC_IF_CH7OVF_Msk (0x01 << ADC_IF_CH7OVF_Pos)
-#define ADC_IF_CH7HFULL_Pos 30
-#define ADC_IF_CH7HFULL_Msk (0x01 << ADC_IF_CH7HFULL_Pos)
-#define ADC_IF_CH7FULL_Pos 31
-#define ADC_IF_CH7FULL_Msk (0x01 << ADC_IF_CH7FULL_Pos)
-
-#define ADC_STAT_EOC_Pos 0 //写1清零
-#define ADC_STAT_EOC_Msk (0x01 << ADC_STAT_EOC_Pos)
-#define ADC_STAT_OVF_Pos 1 //读数据寄存器清除
-#define ADC_STAT_OVF_Msk (0x01 << ADC_STAT_OVF_Pos)
-#define ADC_STAT_HFULL_Pos 2
-#define ADC_STAT_HFULL_Msk (0x01 << ADC_STAT_HFULL_Pos)
-#define ADC_STAT_FULL_Pos 3
-#define ADC_STAT_FULL_Msk (0x01 << ADC_STAT_FULL_Pos)
-#define ADC_STAT_EMPTY_Pos 4
-#define ADC_STAT_EMPTY_Msk (0x01 << ADC_STAT_EMPTY_Pos)
-
-#define ADC_CTRL1_RIN_Pos 4 //输入阻抗：0 无穷大   1 105K   2 90K   3 75K   4 60K   5 45K   6 30K   7 15K
-#define ADC_CTRL1_RIN_Msk (0x07 << ADC_CTRL1_RIN_Pos)
-
-#define ADC_CTRL2_RESET_Pos 0 //数字电路复位
-#define ADC_CTRL2_RESET_Msk (0x01 << ADC_CTRL2_RESET_Pos)
-#define ADC_CTRL2_ADCEVCM_Pos 1 //ADC External VCM，ADC与PGA输出共模电平选择
-#define ADC_CTRL2_ADCEVCM_Msk (0x01 << ADC_CTRL2_ADCEVCM_Pos)
-#define ADC_CTRL2_PGAIVCM_Pos 2 //PGA Internal VCM，PGA输入共模电平选择
-#define ADC_CTRL2_PGAIVCM_Msk (0x01 << ADC_CTRL2_PGAIVCM_Pos)
-#define ADC_CTRL2_PGAGAIN_Pos 3 //0 25.1dB    1 21.6dB    2 11.1dB    3 3.5dB    4 0dB(1.8V)    5 -2.9dB    6 -5.3dB
-#define ADC_CTRL2_PGAGAIN_Msk (0x07 << ADC_CTRL2_PGAGAIN_Pos)
-#define ADC_CTRL2_REFPOUT_Pos 23 //1 ADC 内部 1.2V REFP电压输出到外部REFP引脚，用于测量，或在需要1.2V外部REFP时节省成本
-#define ADC_CTRL2_REFPOUT_Msk       (0x01 << ADC_CTRL2_REFPOUT_Pos
-#define ADC_CTRL2_CLKDIV_Pos 24 //时钟分频，只在时钟源为HRC时有效
-#define ADC_CTRL2_CLKDIV_Msk (0x1F << ADC_CTRL2_CLKDIV_Pos)
-#define ADC_CTRL2_PGAVCM_Pos 29
-#define ADC_CTRL2_PGAVCM_Msk (0x07u << ADC_CTRL2_PGAVCM_Pos)
-
-#define ADC_CALIBSET_OFFSET_Pos 0
-#define ADC_CALIBSET_OFFSET_Msk (0x1FF << ADC_CALIBSET_OFFSET_Pos)
-#define ADC_CALIBSET_K_Pos 16
-#define ADC_CALIBSET_K_Msk (0x1FF << ADC_CALIBSET_K_Pos)
-
-#define ADC_CALIBEN_OFFSET_Pos 0
-#define ADC_CALIBEN_OFFSET_Msk (0x01 << ADC_CALIBEN_OFFSET_Pos)
-#define ADC_CALIBEN_K_Pos 1
-#define ADC_CALIBEN_K_Msk (0x01 << ADC_CALIBEN_K_Pos)
-
-typedef struct
-{
-    __IO uint32_t MODE; //0 普通模式，A、B两路输出互相独立
-                        //1 互补模式，A、B两路输出都由PERA、HIGHA控制，B路输出与A路输出极性相反，且DZA、DZB控制A、B路输出上升沿推迟时间
-                        //2 单次模式，同普通模式，但一个周期后自动停止
-                        //3 对称模式，A、B两路输出互相独立，以两个计数周期产生一个波形输出周期，分辨率提升一倍、频率降低一倍
-                        //4 对称互补模式，对称模式和互补模式的综合
-
-    __IO uint32_t PERA; //[15:0] 周期
-
-    __IO uint32_t HIGHA; //[15:0] 高电平持续时长
-
-    __IO uint32_t DZA; //[9:0] 死区，即上升沿推迟时长，必须小于HIGHA
-
-    __IO uint32_t PERB;
-
-    __IO uint32_t HIGHB;
-
-    __IO uint32_t DZB;
-
-    __IO uint32_t INIOUT; //Init Output level，初始输出电平
-} PWM_TypeDef;
-
-#define PWM_INIOUT_PWMA_Pos 0
-#define PWM_INIOUT_PWMA_Msk (0x01 << PWM_INIOUT_PWMA_Pos)
-#define PWM_INIOUT_PWMB_Pos 1
-#define PWM_INIOUT_PWMB_Msk (0x01 << PWM_INIOUT_PWMB_Pos)
-
-typedef struct
-{
-    __IO uint32_t FORCEH;
-
-    __IO uint32_t ADTRG0A;
-    __IO uint32_t ADTRG0B;
-
-    __IO uint32_t ADTRG1A;
-    __IO uint32_t ADTRG1B;
-
-    __IO uint32_t ADTRG2A;
-    __IO uint32_t ADTRG2B;
-
-    __IO uint32_t ADTRG3A;
-    __IO uint32_t ADTRG3B;
-
-    __IO uint32_t ADTRG4A;
-    __IO uint32_t ADTRG4B;
-
-    __IO uint32_t ADTRG5A;
-    __IO uint32_t ADTRG5B;
-
-    uint32_t RESERVED[3];
-
-    __IO uint32_t HALT; //刹车控制
-
-    __IO uint32_t CHEN;
-
-    __IO uint32_t IE;
-
-    __IO uint32_t IF;
-
-    __IO uint32_t IM; //Interrupt Mask
-
-    __IO uint32_t IRS; //Interrupt Raw Stat
-} PWMG_TypeDef;
-
-#define PWMG_FORCEH_PWM0_Pos 0
-#define PWMG_FORCEH_PWM0_Msk (0x01 << PWMG_FORCEH_PWM0_Pos)
-#define PWMG_FORCEH_PWM1_Pos 1
-#define PWMG_FORCEH_PWM1_Msk (0x01 << PWMG_FORCEH_PWM1_Pos)
-#define PWMG_FORCEH_PWM2_Pos 2
-#define PWMG_FORCEH_PWM2_Msk (0x01 << PWMG_FORCEH_PWM2_Pos)
-#define PWMG_FORCEH_PWM3_Pos 3
-#define PWMG_FORCEH_PWM3_Msk (0x01 << PWMG_FORCEH_PWM3_Pos)
-#define PWMG_FORCEH_PWM4_Pos 4
-#define PWMG_FORCEH_PWM4_Msk (0x01 << PWMG_FORCEH_PWM4_Pos)
-#define PWMG_FORCEH_PWM5_Pos 5
-#define PWMG_FORCEH_PWM5_Msk (0x01 << PWMG_FORCEH_PWM5_Pos)
-
-#define PWMG_ADTRG_VALUE_Pos 0
-#define PWMG_ADTRG_VALUE_Msk (0xFFFF << PWMG_ADTRG0A_VALUE_Pos)
-#define PWMG_ADTRG_EVEN_Pos 16 //1 偶数周期生效    0 奇数周期生效
-#define PWMG_ADTRG_EVEN_Msk (0x01 << PWMG_ADTRG0A_EVEN_Pos)
-#define PWMG_ADTRG_EN_Pos 17
-#define PWMG_ADTRG_EN_Msk (0x01 << PWMG_ADTRG0A_EN_Pos)
-
-#define PWMG_HALT_EN_Pos 0
-#define PWMG_HALT_EN_Msk (0x01 << PWMG_HALT_EN_Pos)
-#define PWMG_HALT_PWM0_Pos 1
-#define PWMG_HALT_PWM0_Msk (0x01 << PWMG_HALT_PWM0_Pos)
-#define PWMG_HALT_PWM1_Pos 2
-#define PWMG_HALT_PWM1_Msk (0x01 << PWMG_HALT_PWM1_Pos)
-#define PWMG_HALT_PWM2_Pos 3
-#define PWMG_HALT_PWM2_Msk (0x01 << PWMG_HALT_PWM2_Pos)
-#define PWMG_HALT_PWM3_Pos 4
-#define PWMG_HALT_PWM3_Msk (0x01 << PWMG_HALT_PWM3_Pos)
-#define PWMG_HALT_PWM4_Pos 5
-#define PWMG_HALT_PWM4_Msk (0x01 << PWMG_HALT_PWM4_Pos)
-#define PWMG_HALT_PWM5_Pos 6
-#define PWMG_HALT_PWM5_Msk (0x01 << PWMG_HALT_PWM5_Pos)
-#define PWMG_HALT_STOPCNT_Pos 7 //1 刹车时将PWM计数器清零，停止计数    0 刹车时，PWM计数器继续计数
-#define PWMG_HALT_STOPCNT_Msk (0x01 << PWMG_HALT_STOPCNT_Pos)
-#define PWMG_HALT_INLVL_Pos 8 //1 刹车输入高电平有效
-#define PWMG_HALT_INLVL_Msk (0x01 << PWMG_HALT_INLVL_Pos)
-#define PWMG_HALT_OUTLVL_Pos 9 //1 刹车过程中输出高电平
-#define PWMG_HALT_OUTLVL_Msk (0x01 << PWMG_HALT_OUTLVL_Pos)
-#define PWMG_HALT_STAT_Pos 10 //1 正在刹车
-#define PWMG_HALT_STAT_Msk (0x01 << PWMG_HALT_STAT_Pos)
-
-#define PWMG_CHEN_PWM0A_Pos 0
-#define PWMG_CHEN_PWM0A_Msk (0x01 << PWMG_CHEN_PWM0A_Pos)
-#define PWMG_CHEN_PWM0B_Pos 1
-#define PWMG_CHEN_PWM0B_Msk (0x01 << PWMG_CHEN_PWM0B_Pos)
-#define PWMG_CHEN_PWM1A_Pos 2
-#define PWMG_CHEN_PWM1A_Msk (0x01 << PWMG_CHEN_PWM1A_Pos)
-#define PWMG_CHEN_PWM1B_Pos 3
-#define PWMG_CHEN_PWM1B_Msk (0x01 << PWMG_CHEN_PWM1B_Pos)
-#define PWMG_CHEN_PWM2A_Pos 4
-#define PWMG_CHEN_PWM2A_Msk (0x01 << PWMG_CHEN_PWM2A_Pos)
-#define PWMG_CHEN_PWM2B_Pos 5
-#define PWMG_CHEN_PWM2B_Msk (0x01 << PWMG_CHEN_PWM2B_Pos)
-#define PWMG_CHEN_PWM3A_Pos 6
-#define PWMG_CHEN_PWM3A_Msk (0x01 << PWMG_CHEN_PWM3A_Pos)
-#define PWMG_CHEN_PWM3B_Pos 7
-#define PWMG_CHEN_PWM3B_Msk (0x01 << PWMG_CHEN_PWM3B_Pos)
-#define PWMG_CHEN_PWM4A_Pos 8
-#define PWMG_CHEN_PWM4A_Msk (0x01 << PWMG_CHEN_PWM4A_Pos)
-#define PWMG_CHEN_PWM4B_Pos 9
-#define PWMG_CHEN_PWM4B_Msk (0x01 << PWMG_CHEN_PWM4B_Pos)
-#define PWMG_CHEN_PWM5A_Pos 10
-#define PWMG_CHEN_PWM5A_Msk (0x01 << PWMG_CHEN_PWM5A_Pos)
-#define PWMG_CHEN_PWM5B_Pos 11
-#define PWMG_CHEN_PWM5B_Msk (0x01 << PWMG_CHEN_PWM5B_Pos)
-
-#define PWMG_IE_NEWP0A_Pos 0
-#define PWMG_IE_NEWP0A_Msk (0x01 << PWMG_IE_NEWP0A_Pos)
-#define PWMG_IE_NEWP0B_Pos 1
-#define PWMG_IE_NEWP0B_Msk (0x01 << PWMG_IE_NEWP0B_Pos)
-#define PWMG_IE_NEWP1A_Pos 2
-#define PWMG_IE_NEWP1A_Msk (0x01 << PWMG_IE_NEWP1A_Pos)
-#define PWMG_IE_NEWP1B_Pos 3
-#define PWMG_IE_NEWP1B_Msk (0x01 << PWMG_IE_NEWP1B_Pos)
-#define PWMG_IE_NEWP2A_Pos 4
-#define PWMG_IE_NEWP2A_Msk (0x01 << PWMG_IE_NEWP2A_Pos)
-#define PWMG_IE_NEWP2B_Pos 5
-#define PWMG_IE_NEWP2B_Msk (0x01 << PWMG_IE_NEWP2B_Pos)
-#define PWMG_IE_NEWP3A_Pos 6
-#define PWMG_IE_NEWP3A_Msk (0x01 << PWMG_IE_NEWP3A_Pos)
-#define PWMG_IE_NEWP3B_Pos 7
-#define PWMG_IE_NEWP3B_Msk (0x01 << PWMG_IE_NEWP3B_Pos)
-#define PWMG_IE_NEWP4A_Pos 8
-#define PWMG_IE_NEWP4A_Msk (0x01 << PWMG_IE_NEWP4A_Pos)
-#define PWMG_IE_NEWP4B_Pos 9
-#define PWMG_IE_NEWP4B_Msk (0x01 << PWMG_IE_NEWP4B_Pos)
-#define PWMG_IE_NEWP5A_Pos 10
-#define PWMG_IE_NEWP5A_Msk (0x01 << PWMG_IE_NEWP5A_Pos)
-#define PWMG_IE_NEWP5B_Pos 11
-#define PWMG_IE_NEWP5B_Msk (0x01 << PWMG_IE_NEWP5B_Pos)
-#define PWMG_IE_HEND0A_Pos 12
-#define PWMG_IE_HEND0A_Msk (0x01 << PWMG_IE_HEND0A_Pos)
-#define PWMG_IE_HEND0B_Pos 13
-#define PWMG_IE_HEND0B_Msk (0x01 << PWMG_IE_HEND0B_Pos)
-#define PWMG_IE_HEND1A_Pos 14
-#define PWMG_IE_HEND1A_Msk (0x01 << PWMG_IE_HEND1A_Pos)
-#define PWMG_IE_HEND1B_Pos 15
-#define PWMG_IE_HEND1B_Msk (0x01 << PWMG_IE_HEND1B_Pos)
-#define PWMG_IE_HEND2A_Pos 16
-#define PWMG_IE_HEND2A_Msk (0x01 << PWMG_IE_HEND2A_Pos)
-#define PWMG_IE_HEND2B_Pos 17
-#define PWMG_IE_HEND2B_Msk (0x01 << PWMG_IE_HEND2B_Pos)
-#define PWMG_IE_HEND3A_Pos 18
-#define PWMG_IE_HEND3A_Msk (0x01 << PWMG_IE_HEND3A_Pos)
-#define PWMG_IE_HEND3B_Pos 19
-#define PWMG_IE_HEND3B_Msk (0x01 << PWMG_IE_HEND3B_Pos)
-#define PWMG_IE_HEND4A_Pos 20
-#define PWMG_IE_HEND4A_Msk (0x01 << PWMG_IE_HEND4A_Pos)
-#define PWMG_IE_HEND4B_Pos 21
-#define PWMG_IE_HEND4B_Msk (0x01 << PWMG_IE_HEND4B_Pos)
-#define PWMG_IE_HEND5A_Pos 22
-#define PWMG_IE_HEND5A_Msk (0x01 << PWMG_IE_HEND5A_Pos)
-#define PWMG_IE_HEND5B_Pos 23
-#define PWMG_IE_HEND5B_Msk (0x01 << PWMG_IE_HEND5B_Pos)
-#define PWMG_IE_HALT_Pos 24
-#define PWMG_IE_HALT_Msk (0x01 << PWMG_IE_HALT_Pos)
-
-#define PWMG_IF_NEWP0A_Pos 0
-#define PWMG_IF_NEWP0A_Msk (0x01 << PWMG_IF_NEWP0A_Pos)
-#define PWMG_IF_NEWP0B_Pos 1
-#define PWMG_IF_NEWP0B_Msk (0x01 << PWMG_IF_NEWP0B_Pos)
-#define PWMG_IF_NEWP1A_Pos 2
-#define PWMG_IF_NEWP1A_Msk (0x01 << PWMG_IF_NEWP1A_Pos)
-#define PWMG_IF_NEWP1B_Pos 3
-#define PWMG_IF_NEWP1B_Msk (0x01 << PWMG_IF_NEWP1B_Pos)
-#define PWMG_IF_NEWP2A_Pos 4
-#define PWMG_IF_NEWP2A_Msk (0x01 << PWMG_IF_NEWP2A_Pos)
-#define PWMG_IF_NEWP2B_Pos 5
-#define PWMG_IF_NEWP2B_Msk (0x01 << PWMG_IF_NEWP2B_Pos)
-#define PWMG_IF_NEWP3A_Pos 6
-#define PWMG_IF_NEWP3A_Msk (0x01 << PWMG_IF_NEWP3A_Pos)
-#define PWMG_IF_NEWP3B_Pos 7
-#define PWMG_IF_NEWP3B_Msk (0x01 << PWMG_IF_NEWP3B_Pos)
-#define PWMG_IF_NEWP4A_Pos 8
-#define PWMG_IF_NEWP4A_Msk (0x01 << PWMG_IF_NEWP4A_Pos)
-#define PWMG_IF_NEWP4B_Pos 9
-#define PWMG_IF_NEWP4B_Msk (0x01 << PWMG_IF_NEWP4B_Pos)
-#define PWMG_IF_NEWP5A_Pos 10
-#define PWMG_IF_NEWP5A_Msk (0x01 << PWMG_IF_NEWP5A_Pos)
-#define PWMG_IF_NEWP5B_Pos 11
-#define PWMG_IF_NEWP5B_Msk (0x01 << PWMG_IF_NEWP5B_Pos)
-#define PWMG_IF_HEND0A_Pos 12
-#define PWMG_IF_HEND0A_Msk (0x01 << PWMG_IF_HEND0A_Pos)
-#define PWMG_IF_HEND0B_Pos 13
-#define PWMG_IF_HEND0B_Msk (0x01 << PWMG_IF_HEND0B_Pos)
-#define PWMG_IF_HEND1A_Pos 14
-#define PWMG_IF_HEND1A_Msk (0x01 << PWMG_IF_HEND1A_Pos)
-#define PWMG_IF_HEND1B_Pos 15
-#define PWMG_IF_HEND1B_Msk (0x01 << PWMG_IF_HEND1B_Pos)
-#define PWMG_IF_HEND2A_Pos 16
-#define PWMG_IF_HEND2A_Msk (0x01 << PWMG_IF_HEND2A_Pos)
-#define PWMG_IF_HEND2B_Pos 17
-#define PWMG_IF_HEND2B_Msk (0x01 << PWMG_IF_HEND2B_Pos)
-#define PWMG_IF_HEND3A_Pos 18
-#define PWMG_IF_HEND3A_Msk (0x01 << PWMG_IF_HEND3A_Pos)
-#define PWMG_IF_HEND3B_Pos 19
-#define PWMG_IF_HEND3B_Msk (0x01 << PWMG_IF_HEND3B_Pos)
-#define PWMG_IF_HEND4A_Pos 20
-#define PWMG_IF_HEND4A_Msk (0x01 << PWMG_IF_HEND4A_Pos)
-#define PWMG_IF_HEND4B_Pos 21
-#define PWMG_IF_HEND4B_Msk (0x01 << PWMG_IF_HEND4B_Pos)
-#define PWMG_IF_HEND5A_Pos 22
-#define PWMG_IF_HEND5A_Msk (0x01 << PWMG_IF_HEND5A_Pos)
-#define PWMG_IF_HEND5B_Pos 23
-#define PWMG_IF_HEND5B_Msk (0x01 << PWMG_IF_HEND5B_Pos)
-#define PWMG_IF_HALT_Pos 24
-#define PWMG_IF_HALT_Msk (0x01 << PWMG_IF_HALT_Pos)
-
-#define PWMG_IM_NEWP0A_Pos 0 //Interrupt Mask
-#define PWMG_IM_NEWP0A_Msk (0x01 << PWMG_IM_NEWP0A_Pos)
-#define PWMG_IM_NEWP0B_Pos 1
-#define PWMG_IM_NEWP0B_Msk (0x01 << PWMG_IM_NEWP0B_Pos)
-#define PWMG_IM_NEWP1A_Pos 2
-#define PWMG_IM_NEWP1A_Msk (0x01 << PWMG_IM_NEWP1A_Pos)
-#define PWMG_IM_NEWP1B_Pos 3
-#define PWMG_IM_NEWP1B_Msk (0x01 << PWMG_IM_NEWP1B_Pos)
-#define PWMG_IM_NEWP2A_Pos 4
-#define PWMG_IM_NEWP2A_Msk (0x01 << PWMG_IM_NEWP2A_Pos)
-#define PWMG_IM_NEWP2B_Pos 5
-#define PWMG_IM_NEWP2B_Msk (0x01 << PWMG_IM_NEWP2B_Pos)
-#define PWMG_IM_NEWP3A_Pos 6
-#define PWMG_IM_NEWP3A_Msk (0x01 << PWMG_IM_NEWP3A_Pos)
-#define PWMG_IM_NEWP3B_Pos 7
-#define PWMG_IM_NEWP3B_Msk (0x01 << PWMG_IM_NEWP3B_Pos)
-#define PWMG_IM_NEWP4A_Pos 8
-#define PWMG_IM_NEWP4A_Msk (0x01 << PWMG_IM_NEWP4A_Pos)
-#define PWMG_IM_NEWP4B_Pos 9
-#define PWMG_IM_NEWP4B_Msk (0x01 << PWMG_IM_NEWP4B_Pos)
-#define PWMG_IM_NEWP5A_Pos 10
-#define PWMG_IM_NEWP5A_Msk (0x01 << PWMG_IM_NEWP5A_Pos)
-#define PWMG_IM_NEWP5B_Pos 11
-#define PWMG_IM_NEWP5B_Msk (0x01 << PWMG_IM_NEWP5B_Pos)
-#define PWMG_IM_HEND0A_Pos 12
-#define PWMG_IM_HEND0A_Msk (0x01 << PWMG_IM_HEND0A_Pos)
-#define PWMG_IM_HEND0B_Pos 13
-#define PWMG_IM_HEND0B_Msk (0x01 << PWMG_IM_HEND0B_Pos)
-#define PWMG_IM_HEND1A_Pos 14
-#define PWMG_IM_HEND1A_Msk (0x01 << PWMG_IM_HEND1A_Pos)
-#define PWMG_IM_HEND1B_Pos 15
-#define PWMG_IM_HEND1B_Msk (0x01 << PWMG_IM_HEND1B_Pos)
-#define PWMG_IM_HEND2A_Pos 16
-#define PWMG_IM_HEND2A_Msk (0x01 << PWMG_IM_HEND2A_Pos)
-#define PWMG_IM_HEND2B_Pos 17
-#define PWMG_IM_HEND2B_Msk (0x01 << PWMG_IM_HEND2B_Pos)
-#define PWMG_IM_HEND3A_Pos 18
-#define PWMG_IM_HEND3A_Msk (0x01 << PWMG_IM_HEND3A_Pos)
-#define PWMG_IM_HEND3B_Pos 19
-#define PWMG_IM_HEND3B_Msk (0x01 << PWMG_IM_HEND3B_Pos)
-#define PWMG_IM_HEND4A_Pos 20
-#define PWMG_IM_HEND4A_Msk (0x01 << PWMG_IM_HEND4A_Pos)
-#define PWMG_IM_HEND4B_Pos 21
-#define PWMG_IM_HEND4B_Msk (0x01 << PWMG_IM_HEND4B_Pos)
-#define PWMG_IM_HEND5A_Pos 22
-#define PWMG_IM_HEND5A_Msk (0x01 << PWMG_IM_HEND5A_Pos)
-#define PWMG_IM_HEND5B_Pos 23
-#define PWMG_IM_HEND5B_Msk (0x01 << PWMG_IM_HEND5B_Pos)
-#define PWMG_IM_HALT_Pos 24
-#define PWMG_IM_HALT_Msk (0x01 << PWMG_IM_HALT_Pos)
-
-#define PWMG_IRS_NEWP0A_Pos 0 //Interrupt Raw State
-#define PWMG_IRS_NEWP0A_Msk (0x01 << PWMG_IRS_NEWP0A_Pos)
-#define PWMG_IRS_NEWP0B_Pos 1
-#define PWMG_IRS_NEWP0B_Msk (0x01 << PWMG_IRS_NEWP0B_Pos)
-#define PWMG_IRS_NEWP1A_Pos 2
-#define PWMG_IRS_NEWP1A_Msk (0x01 << PWMG_IRS_NEWP1A_Pos)
-#define PWMG_IRS_NEWP1B_Pos 3
-#define PWMG_IRS_NEWP1B_Msk (0x01 << PWMG_IRS_NEWP1B_Pos)
-#define PWMG_IRS_NEWP2A_Pos 4
-#define PWMG_IRS_NEWP2A_Msk (0x01 << PWMG_IRS_NEWP2A_Pos)
-#define PWMG_IRS_NEWP2B_Pos 5
-#define PWMG_IRS_NEWP2B_Msk (0x01 << PWMG_IRS_NEWP2B_Pos)
-#define PWMG_IRS_NEWP3A_Pos 6
-#define PWMG_IRS_NEWP3A_Msk (0x01 << PWMG_IRS_NEWP3A_Pos)
-#define PWMG_IRS_NEWP3B_Pos 7
-#define PWMG_IRS_NEWP3B_Msk (0x01 << PWMG_IRS_NEWP3B_Pos)
-#define PWMG_IRS_NEWP4A_Pos 8
-#define PWMG_IRS_NEWP4A_Msk (0x01 << PWMG_IRS_NEWP4A_Pos)
-#define PWMG_IRS_NEWP4B_Pos 9
-#define PWMG_IRS_NEWP4B_Msk (0x01 << PWMG_IRS_NEWP4B_Pos)
-#define PWMG_IRS_NEWP5A_Pos 10
-#define PWMG_IRS_NEWP5A_Msk (0x01 << PWMG_IRS_NEWP5A_Pos)
-#define PWMG_IRS_NEWP5B_Pos 11
-#define PWMG_IRS_NEWP5B_Msk (0x01 << PWMG_IRS_NEWP5B_Pos)
-#define PWMG_IRS_HEND0A_Pos 12
-#define PWMG_IRS_HEND0A_Msk (0x01 << PWMG_IRS_HEND0A_Pos)
-#define PWMG_IRS_HEND0B_Pos 13
-#define PWMG_IRS_HEND0B_Msk (0x01 << PWMG_IRS_HEND0B_Pos)
-#define PWMG_IRS_HEND1A_Pos 14
-#define PWMG_IRS_HEND1A_Msk (0x01 << PWMG_IRS_HEND1A_Pos)
-#define PWMG_IRS_HEND1B_Pos 15
-#define PWMG_IRS_HEND1B_Msk (0x01 << PWMG_IRS_HEND1B_Pos)
-#define PWMG_IRS_HEND2A_Pos 16
-#define PWMG_IRS_HEND2A_Msk (0x01 << PWMG_IRS_HEND2A_Pos)
-#define PWMG_IRS_HEND2B_Pos 17
-#define PWMG_IRS_HEND2B_Msk (0x01 << PWMG_IRS_HEND2B_Pos)
-#define PWMG_IRS_HEND3A_Pos 18
-#define PWMG_IRS_HEND3A_Msk (0x01 << PWMG_IRS_HEND3A_Pos)
-#define PWMG_IRS_HEND3B_Pos 19
-#define PWMG_IRS_HEND3B_Msk (0x01 << PWMG_IRS_HEND3B_Pos)
-#define PWMG_IRS_HEND4A_Pos 20
-#define PWMG_IRS_HEND4A_Msk (0x01 << PWMG_IRS_HEND4A_Pos)
-#define PWMG_IRS_HEND4B_Pos 21
-#define PWMG_IRS_HEND4B_Msk (0x01 << PWMG_IRS_HEND4B_Pos)
-#define PWMG_IRS_HEND5A_Pos 22
-#define PWMG_IRS_HEND5A_Msk (0x01 << PWMG_IRS_HEND5A_Pos)
-#define PWMG_IRS_HEND5B_Pos 23
-#define PWMG_IRS_HEND5B_Msk (0x01 << PWMG_IRS_HEND5B_Pos)
-#define PWMG_IRS_HALT_Pos 24
-#define PWMG_IRS_HALT_Msk (0x01 << PWMG_IRS_HALT_Pos)
-
-typedef struct
-{
-    __IO uint32_t EN; //[0] ENABLE
-
-    __IO uint32_t IE; //只有为1时，IF[CHx]在DMA传输结束时才能变为1，否则将一直保持在0
-
-    __IO uint32_t IM; //当为1时，即使IF[CHx]为1，dma_int也不会因此变1
-
-    __IO uint32_t IF; //写1清零
-
-    uint32_t RESERVED[12];
-
-    struct
-    {
-        __IO uint32_t CR;
-
-        __IO uint32_t AM; //Adress Mode
-
-        __IO uint32_t SRC;
-
-        __IO uint32_t SRCSGADDR1; //只在Scatter Gather模式下使用
-
-        __IO uint32_t SRCSGADDR2; //只在Scatter Gather模式下使用
-
-        __IO uint32_t SRCSGADDR3; //只在Scatter Gather模式下使用
-
-        __IO uint32_t SRCSGLEN; //只在Scatter Gather模式下使用
-
-        __IO uint32_t DST;
-
-        __IO uint32_t DSTSGADDR1; //只在Scatter Gather模式下使用
-
-        __IO uint32_t DSTSGADDR2; //只在Scatter Gather模式下使用
-
-        __IO uint32_t DSTSGADDR3; //只在Scatter Gather模式下使用
-
-        __IO uint32_t DSTSGLEN; //只在Scatter Gather模式下使用
-
-        uint32_t RESERVED[4];
-    } CH[3];
-} DMA_TypeDef;
-
-#define DMA_IE_CH0_Pos 0
-#define DMA_IE_CH0_Msk (0x01 << DMA_IE_CH0_Pos)
-#define DMA_IE_CH1_Pos 1
-#define DMA_IE_CH1_Msk (0x01 << DMA_IE_CH1_Pos)
-#define DMA_IE_CH2_Pos 2
-#define DMA_IE_CH2_Msk (0x01 << DMA_IE_CH2_Pos)
-#define DMA_IE_CH3_Pos 3
-#define DMA_IE_CH3_Msk (0x01 << DMA_IE_CH3_Pos)
-#define DMA_IE_CH4_Pos 4
-#define DMA_IE_CH4_Msk (0x01 << DMA_IE_CH4_Pos)
-#define DMA_IE_CH5_Pos 5
-#define DMA_IE_CH5_Msk (0x01 << DMA_IE_CH5_Pos)
-#define DMA_IE_CH6_Pos 6
-#define DMA_IE_CH6_Msk (0x01 << DMA_IE_CH6_Pos)
-#define DMA_IE_CH7_Pos 7
-#define DMA_IE_CH7_Msk (0x01 << DMA_IE_CH7_Pos)
-
-#define DMA_IM_CH0_Pos 0
-#define DMA_IM_CH0_Msk (0x01 << DMA_IM_CH0_Pos)
-#define DMA_IM_CH1_Pos 1
-#define DMA_IM_CH1_Msk (0x01 << DMA_IM_CH1_Pos)
-#define DMA_IM_CH2_Pos 2
-#define DMA_IM_CH2_Msk (0x01 << DMA_IM_CH2_Pos)
-#define DMA_IM_CH3_Pos 3
-#define DMA_IM_CH3_Msk (0x01 << DMA_IM_CH3_Pos)
-#define DMA_IM_CH4_Pos 4
-#define DMA_IM_CH4_Msk (0x01 << DMA_IM_CH4_Pos)
-#define DMA_IM_CH5_Pos 5
-#define DMA_IM_CH5_Msk (0x01 << DMA_IM_CH5_Pos)
-#define DMA_IM_CH6_Pos 6
-#define DMA_IM_CH6_Msk (0x01 << DMA_IM_CH6_Pos)
-#define DMA_IM_CH7_Pos 7
-#define DMA_IM_CH7_Msk (0x01 << DMA_IM_CH7_Pos)
-
-#define DMA_IF_CH0_Pos 0
-#define DMA_IF_CH0_Msk (0x01 << DMA_IF_CH0_Pos)
-#define DMA_IF_CH1_Pos 1
-#define DMA_IF_CH1_Msk (0x01 << DMA_IF_CH1_Pos)
-#define DMA_IF_CH2_Pos 2
-#define DMA_IF_CH2_Msk (0x01 << DMA_IF_CH2_Pos)
-#define DMA_IF_CH3_Pos 3
-#define DMA_IF_CH3_Msk (0x01 << DMA_IF_CH3_Pos)
-#define DMA_IF_CH4_Pos 4
-#define DMA_IF_CH4_Msk (0x01 << DMA_IF_CH4_Pos)
-#define DMA_IF_CH5_Pos 5
-#define DMA_IF_CH5_Msk (0x01 << DMA_IF_CH5_Pos)
-#define DMA_IF_CH6_Pos 6
-#define DMA_IF_CH6_Msk (0x01 << DMA_IF_CH6_Pos)
-#define DMA_IF_CH7_Pos 7
-#define DMA_IF_CH7_Msk (0x01 << DMA_IF_CH7_Pos)
-
-#define DMA_CR_LEN_Pos 0 //此通道传输总长度，0对应1字节，最大4096字节
-#define DMA_CR_LEN_Msk (0xFFF << DMA_CR_LEN_Pos)
-#define DMA_CR_RXEN_Pos 16
-#define DMA_CR_RXEN_Msk (0x01 << DMA_CR_RXEN_Pos)
-#define DMA_CR_TXEN_Pos 17
-#define DMA_CR_TXEN_Msk (0x01 << DMA_CR_TXEN_Pos)
-#define DMA_CR_AUTORE_Pos 18 //Auto Restart, 通道在传输完成后，是否自动重新启动
-#define DMA_CR_AUTORE_Msk (0x01 << DMA_CR_AUTORE_Pos)
-
-#define DMA_AM_SRCAM_Pos 0 //Address Mode   0 地址固定    1 地址递增    2 scatter gather模式
-#define DMA_AM_SRCAM_Msk (0x03 << DMA_AM_SRCAM_Pos)
-#define DMA_AM_DSTAM_Pos 8
-#define DMA_AM_DSTAM_Msk (0x03 << DMA_AM_DSTAM_Pos)
-#define DMA_AM_BURST_Pos 16
-#define DMA_AM_BURST_Msk (0x01 << DMA_AM_BURST_Pos)
-
-typedef struct
-{
-    __IO uint32_t CR; //Control Register
-
-    __O uint32_t CMD; //Command Register
-
-    __I uint32_t SR; //Status Register
-
-    __I uint32_t IF; //Interrupt Flag，读取清零
-
-    __IO uint32_t IE; //Interrupt Enable
-
-    uint32_t RESERVED;
-
-    __IO uint32_t BT0; //Bit Time Register 0
-
-    __IO uint32_t BT1; //Bit Time Register 1
-
-    uint32_t RESERVED2[3];
-
-    __I uint32_t ALC; //Arbitration Lost Capture, 仲裁丢失捕捉
-
-    __I uint32_t ECC; //Error code capture, 错误代码捕捉
-
-    __IO uint32_t EWLIM; //Error Warning Limit, 错误报警限制
-
-    __IO uint32_t RXERR; //RX错误计数
-
-    __IO uint32_t TXERR; //TX错误计数
-
-    union
-    {
-        struct
-        {                         //在复位时可读写，正常工作模式下不可访问
-            __IO uint32_t ACR[4]; //Acceptance Check Register, 验收寄存器
-
-            __IO uint32_t AMR[4]; //Acceptance Mask Register, 验收屏蔽寄存器；对应位写0，ID必须和验收寄存器匹配
-
-            uint32_t RESERVED[5];
-        } FILTER;
-
-        struct
-        { //在正常工作模式下可读写，复位时不可访问
-            __IO uint32_t INFO;
-
-            __IO uint32_t DATA[12];
-        } FRAME;
-    };
-
-    __I uint32_t RMCNT; //Receive Message Count
-
-    uint32_t RESERVED3[66];
-
-    struct
-    { //TXFRAME的读接口
-        __I uint32_t INFO;
-
-        __I uint32_t DATA[12];
-    } TXFRAME_R;
-} CAN_TypeDef;
-
-#define CAN_CR_RST_Pos 0
-#define CAN_CR_RST_Msk (0x01 << CAN_CR_RST_Pos)
-#define CAN_CR_LOM_Pos 1 //Listen Only Mode
-#define CAN_CR_LOM_Msk (0x01 << CAN_CR_LOM_Pos)
-#define CAN_CR_STM_Pos 2 //Self Test Mode, 此模式下即使没有应答，CAN控制器也可以成功发送
-#define CAN_CR_STM_Msk (0x01 << CAN_CR_STM_Pos)
-#define CAN_CR_AFM_Pos 3 //Acceptance Filter Mode, 1 单个验收滤波器（32位）   0 两个验收滤波器（16位）
-#define CAN_CR_AFM_Msk (0x01 << CAN_CR_AFM_Pos)
-#define CAN_CR_SLEEP_Pos 4 //写1进入睡眠模式，有总线活动或中断时唤醒并自动清零此位
-#define CAN_CR_SLEEP_Msk (0x01 << CAN_CR_SLEEP_Pos)
-
-#define CAN_CMD_TXREQ_Pos 0 //Transmission Request
-#define CAN_CMD_TXREQ_Msk (0x01 << CAN_CMD_TXREQ_Pos)
-#define CAN_CMD_ABTTX_Pos 1 //Abort Transmission
-#define CAN_CMD_ABTTX_Msk (0x01 << CAN_CMD_ABTTX_Pos)
-#define CAN_CMD_RRB_Pos 2 //Release Receive Buffer
-#define CAN_CMD_RRB_Msk (0x01 << CAN_CMD_RRB_Pos)
-#define CAN_CMD_CLROV_Pos 3 //Clear Data Overrun
-#define CAN_CMD_CLROV_Msk (0x01 << CAN_CMD_CLROV_Pos)
-#define CAN_CMD_SRR_Pos 4 //Self Reception Request
-#define CAN_CMD_SRR_Msk (0x01 << CAN_CMD_SRR_Pos)
-
-#define CAN_SR_RXDA_Pos 0 //Receive Data Available，接收FIFO中有完整消息可以读取
-#define CAN_SR_RXDA_Msk (0x01 << CAN_SR_RXDA_Pos)
-#define CAN_SR_RXOV_Pos 1 //Receive FIFO Overrun，新接收的信息由于接收FIFO已满而丢掉
-#define CAN_SR_RXOV_Msk (0x01 << CAN_SR_RXOV_Pos)
-#define CAN_SR_TXBR_Pos 2 //Transmit Buffer Release，0 正在处理前面的发送，现在不能写新的消息    1 可以写入新的消息发送
-#define CAN_SR_TXBR_Msk (0x01 << CAN_SR_TXBR_Pos)
-#define CAN_SR_TXOK_Pos 3 //Transmit OK，successfully completed
-#define CAN_SR_TXOK_Msk (0x01 << CAN_SR_TXOK_Pos)
-#define CAN_SR_RXBUSY_Pos 4 //Receive Busy，正在接收
-#define CAN_SR_RXBUSY_Msk (0x01 << CAN_SR_RXBUSY_Pos)
-#define CAN_SR_TXBUSY_Pos 5 //Transmit Busy，正在发送
-#define CAN_SR_TXBUSY_Msk (0x01 << CAN_SR_TXBUSY_Pos)
-#define CAN_SR_ERRWARN_Pos 6 //1 至少一个错误计数器达到 Warning Limit
-#define CAN_SR_ERRWARN_Msk (0x01 << CAN_SR_ERRWARN_Pos)
-#define CAN_SR_BUSOFF_Pos 7 //1 CAN 控制器处于总线关闭状态，没有参与到总线活动
-#define CAN_SR_BUSOFF_Msk (0x01 << CAN_SR_BUSOFF_Pos)
-
-#define CAN_IF_RXDA_Pos 0 //IF.RXDA = SR.RXDA & IE.RXDA
-#define CAN_IF_RXDA_Msk (0x01 << CAN_IF_RXDA_Pos)
-#define CAN_IF_TXBR_Pos 1 //当IE.TXBR=1时，SR.TXBR由0变成1将置位此位
-#define CAN_IF_TXBR_Msk (0x01 << CAN_IF_TXBR_Pos)
-#define CAN_IF_ERRWARN_Pos 2 //当IE.ERRWARN=1时，SR.ERRWARN或SR.BUSOFF 0-to-1 或 1-to-0将置位此位
-#define CAN_IF_ERRWARN_Msk (0x01 << CAN_IF_ERRWARN_Pos)
-#define CAN_IF_RXOV_Pos 3 //IF.RXOV = SR.RXOV & IE.RXOV
-#define CAN_IF_RXOV_Msk (0x01 << CAN_IF_RXOV_Pos)
-#define CAN_IF_WKUP_Pos 4 //当IE.WKUP=1时，在睡眠模式下的CAN控制器检测到总线活动时硬件置位
-#define CAN_IF_WKUP_Msk (0x01 << CAN_IF_WKUP_Pos)
-#define CAN_IF_ERRPASS_Pos 5 //
-#define CAN_IF_ERRPASS_Msk (0x01 << CAN_IF_ERRPASS_Pos)
-#define CAN_IF_ARBLOST_Pos 6 //Arbitration Lost，当IE.ARBLOST=1时，CAN控制器丢失仲裁变成接收方时硬件置位
-#define CAN_IF_ARBLOST_Msk (0x01 << CAN_IF_ARBLOST_Pos)
-#define CAN_IF_BUSERR_Pos 7 //当IE.BUSERR=1时，CAN控制器检测到总线错误时硬件置位
-#define CAN_IF_BUSERR_Msk (0x01 << CAN_IF_BUSERR_Pos)
-
-#define CAN_IE_RXDA_Pos 0
-#define CAN_IE_RXDA_Msk (0x01 << CAN_IE_RXDA_Pos)
-#define CAN_IE_TXBR_Pos 1
-#define CAN_IE_TXBR_Msk (0x01 << CAN_IE_TXBR_Pos)
-#define CAN_IE_ERRWARN_Pos 2
-#define CAN_IE_ERRWARN_Msk (0x01 << CAN_IE_ERRWARN_Pos)
-#define CAN_IE_RXOV_Pos 3
-#define CAN_IE_RXOV_Msk (0x01 << CAN_IE_RXOV_Pos)
-#define CAN_IE_WKUP_Pos 4
-#define CAN_IE_WKUP_Msk (0x01 << CAN_IE_WKUP_Pos)
-#define CAN_IE_ERRPASS_Pos 5
-#define CAN_IE_ERRPASS_Msk (0x01 << CAN_IE_ERRPASS_Pos)
-#define CAN_IE_ARBLOST_Pos 6
-#define CAN_IE_ARBLOST_Msk (0x01 << CAN_IE_ARBLOST_Pos)
-#define CAN_IE_BUSERR_Pos 7
-#define CAN_IE_BUSERR_Msk (0x01 << CAN_IE_BUSERR_Pos)
-
-#define CAN_BT0_BRP_Pos 0 //Baud Rate Prescaler，CAN时间单位=2*Tsysclk*(BRP+1)
-#define CAN_BT0_BRP_Msk (0x3F << CAN_BT0_BRP_Pos)
-#define CAN_BT0_SJW_Pos 6 //Synchronization Jump Width
-#define CAN_BT0_SJW_Msk (0x03 << CAN_BT0_SJW_Pos)
-
-#define CAN_BT1_TSEG1_Pos 0 //t_tseg1 = CAN时间单位 * (TSEG1+1)
-#define CAN_BT1_TSEG1_Msk (0x0F << CAN_BT1_TSEG1_Pos)
-#define CAN_BT1_TSEG2_Pos 4 //t_tseg2 = CAN时间单位 * (TSEG2+1)
-#define CAN_BT1_TSEG2_Msk (0x07 << CAN_BT1_TSEG2_Pos)
-#define CAN_BT1_SAM_Pos 7 //采样次数  0: sampled once  1: sampled three times
-#define CAN_BT1_SAM_Msk (0x01 << CAN_BT1_SAM_Pos)
-
-#define CAN_ECC_SEGCODE_Pos 0 //Segment Code
-#define CAN_ECC_SEGCODE_Msk (0x1F << CAN_ECC_SEGCODE_Pos)
-#define CAN_ECC_DIR_Pos 5 //0 error occurred during transmission   1 during reception
-#define CAN_ECC_DIR_Msk (0x01 << CAN_ECC_DIR_Pos)
-#define CAN_ECC_ERRCODE_Pos 6 //Error Code：0 Bit error   1 Form error   2 Stuff error   3 other error
-#define CAN_ECC_ERRCODE_Msk (0x03 << CAN_ECC_ERRCODE_Pos)
-
-#define CAN_INFO_DLC_Pos 0 //Data Length Control
-#define CAN_INFO_DLC_Msk (0x0F << CAN_INFO_DLC_Pos)
-#define CAN_INFO_RTR_Pos 6 //Remote Frame，1 远程帧    0 数据帧
-#define CAN_INFO_RTR_Msk (0x01 << CAN_INFO_RTR_Pos)
-#define CAN_INFO_FF_Pos 7 //Frame Format，0 标准帧格式    1 扩展帧格式
-#define CAN_INFO_FF_Msk (0x01 << CAN_INFO_FF_Pos)
-
-typedef struct
-{
-    __IO uint32_t IE; //[0] 为0的时候，IF[0]维持为0
-
-    __IO uint32_t IF; //[0] 当完成指定长度的数据传输时置1，写1清零
-
-    __IO uint32_t IM; //[0] 当该寄存器为1时，LCDC的中断不会输出给系统的中断控制寄存器
-
-    __IO uint32_t START;
-
-    __IO uint32_t SRCADDR; //数据源地址寄存器，必须字对齐（即地址的低2位必须是0）
-
-    __IO uint32_t CR0;
-
-    __IO uint32_t CR1;
-
-    __IO uint32_t PRECMDV; //在MPU接口中，发送数据前，RS拉低的那一拍，数据总线上的值
-} LCD_TypeDef;
-
-#define LCD_START_GO_Pos 1 //写1开始传输数据，数据传输结束后自动清零
-#define LCD_START_GO_Msk (0x01 << LCD_START_GO_Pos)
-#define LCD_START_BURST_Pos 2
-#define LCD_START_BURST_Msk (0x01 << LCD_START_BURST_Pos)
-
-#define LCD_CR0_VPIX_Pos 0 /*当portrait为0时，表示垂直方向的像素个数，0表示1个，最大为767 \
-                           //当portrait为1时，表示水平方向的像素个数，0表示1个，最大为767 */
-#define LCD_CR0_VPIX_Msk (0x3FF << LCD_CR0_VPIX_Pos)
-#define LCD_CR0_HPIX_Pos 10 /*当portrait为0时，表示水平方向的像素个数，0表示1个，最大为1023 \
-                            //当portrait为1时，表示垂直方向的像素个数，0表示1个，最大为1023 */
-#define LCD_CR0_HPIX_Msk (0x3FF << LCD_CR0_HPIX_Pos)
-#define LCD_CR0_DCLK_Pos 20 //0 DOTCLK一直翻转    1 DOTCLK在空闲时停在1
-#define LCD_CR0_DCLK_Msk (0x01 << LCD_CR0_DCLK_Pos)
-#define LCD_CR0_HLOW_Pos 21 //输出HSYNC低电平持续多少个DOTCLK周期，0表示1个周期
-#define LCD_CR0_HLOW_Msk (0x03 << LCD_CR0_HLOW_Pos)
-
-#define LCD_CR1_VFP_Pos 1
-#define LCD_CR1_VFP_Msk (0x07 << LCD_CR1_VFP_Pos)
-#define LCD_CR1_VBP_Pos 4
-#define LCD_CR1_VBP_Msk (0x1F << LCD_CR1_VBP_Pos)
-#define LCD_CR1_HFP_Pos 9
-#define LCD_CR1_HFP_Msk (0x1F << LCD_CR1_HFP_Pos)
-#define LCD_CR1_HBP_Pos 14
-#define LCD_CR1_HBP_Msk (0x7F << LCD_CR1_HBP_Pos)
-#define LCD_CR1_DCLKDIV_Pos 21 //DOTCLK相对于模块时钟的分频比，0表示2分频，1表示4分频 ...
-#define LCD_CR1_DCLKDIV_Msk (0x1F << LCD_CR1_DCLKDIV_Pos)
-#define LCD_CR1_DCLKINV_Pos 26 //1 输出DOTCLK反向，应用于用DOTCLK下降沿采样数据的屏
-#define LCD_CR1_DCLKINV_Msk (0x01 << LCD_CR1_DCLKINV_Pos)
-
-typedef struct
-{
-    __IO uint32_t DMA_MEM_ADDR;
-
-    __IO uint32_t BLK; //Block Size and Count
-
-    __IO uint32_t ARG; //Argument
-
-    __IO uint32_t CMD; //Command
-
-    __IO uint32_t RESP[4]; //Response
-
-    __IO uint32_t DATA;
-
-    __IO uint32_t STAT;
-
-    __IO uint32_t CR1;
-
-    __IO uint32_t CR2;
-
-    __IO uint32_t IF;
-
-    __IO uint32_t IFE; //Interrupt Flag Enable
-
-    __IO uint32_t IE; //Interrupt Enalbe
-
-    __IO uint32_t CMD12ERR;
-
-    __IO uint32_t INFO;
-
-    __IO uint32_t MAXCURR;
-} SDIO_TypeDef;
-
-#define SDIO_BLK_SIZE_Pos 0 //0x200 512字节   0x400 1024字节   0x800 2048字节
-#define SDIO_BLK_SIZE_Msk (0xFFF << SDIO_BLK_SIZE_Pos)
-#define SDIO_BLK_COUNT_Pos 16 //0 Stop Transfer    1 1块    2 2块    ... ...
-#define SDIO_BLK_COUNT_Msk (0xFFF << SDIO_BLK_COUNT_Pos)
-
-#define SDIO_CMD_DMAEN_Pos 0
-#define SDIO_CMD_DMAEN_Msk (0x01 << SDIO_CMD_DMAEN_Pos)
-#define SDIO_CMD_BLKCNTEN_Pos 1
-#define SDIO_CMD_BLKCNTEN_Msk (0x01 << SDIO_CMD_BLKCNTEN_Pos)
-#define SDIO_CMD_AUTOCMD12_Pos 2
-#define SDIO_CMD_AUTOCMD12_Msk (0x01 << SDIO_CMD_AUTOCMD12_Pos)
-#define SDIO_CMD_DIRREAD_Pos 4 //0 Write, Host to Card    1 Read, Card to Host
-#define SDIO_CMD_DIRREAD_Msk (0x01 << SDIO_CMD_DIRREAD_Pos)
-#define SDIO_CMD_MULTBLK_Pos 5 //0 Single Block    1  Multiple Block
-#define SDIO_CMD_MULTBLK_Msk (0x01 << SDIO_CMD_MULTBLK_Pos)
-#define SDIO_CMD_RESPTYPE_Pos 16 //响应类型，0 无响应    1 136位响应    2 48位响应    3 48位响应，Busy after response
-#define SDIO_CMD_RESPTYPE_Msk (0x03 << SDIO_CMD_RESPTYPE_Pos)
-#define SDIO_CMD_CRCCHECK_Pos 19 //Command CRC Check Enable
-#define SDIO_CMD_CRCCHECK_Msk (0x01 << SDIO_CMD_CRCCHECK_Pos)
-#define SDIO_CMD_IDXCHECK_Pos 20 //Command Index Check Enable
-#define SDIO_CMD_IDXCHECK_Msk (0x01 << SDIO_CMD_IDXCHECK_Pos)
-#define SDIO_CMD_HAVEDATA_Pos 21 //0 No Data Present    1 Data Present
-#define SDIO_CMD_HAVEDATA_Msk (0x01 << SDIO_CMD_HAVEDATA_Pos)
-#define SDIO_CMD_CMDTYPE_Pos 22 //0 NORMAL   1 SUSPEND    2 RESUME    3 ABORT
-#define SDIO_CMD_CMDTYPE_Msk (0x03 << SDIO_CMD_CMDTYPE_Pos)
-#define SDIO_CMD_CMDINDX_Pos 24 //Command Index，CMD0-63、ACMD0-63
-#define SDIO_CMD_CMDINDX_Msk (0x3F << SDIO_CMD_CMDINDX_Pos)
-
-#define SDIO_CR1_4BIT_Pos 1 //1 4 bit mode    0 1 bit mode
-#define SDIO_CR1_4BIT_Msk (0x01 << SDIO_CR1_4BIT_Pos)
-#define SDIO_CR1_8BIT_Pos 5 //1 8 bit mode is selected    0 8 bit mode is not selected
-#define SDIO_CR1_8BIT_Msk (0x01 << SDIO_CR1_8BIT_Pos)
-#define SDIO_CR1_CDBIT_Pos 6 //0 No Card    1 Card Inserted
-#define SDIO_CR1_CDBIT_Msk (0x01 << SDIO_CR1_CDBIT_Pos)
-#define SDIO_CR1_CDSRC_Pos 7 //Card Detect Source, 1 CR1.CDBIT位    0 SD_Detect引脚
-#define SDIO_CR1_CDSRC_Msk (0x01 << SDIO_CR1_CDSRC_Pos)
-#define SDIO_CR1_PWRON_Pos 8 //1 Power on    0 Power off
-#define SDIO_CR1_PWRON_Msk (0x01 << SDIO_CR1_PWRON_Pos)
-#define SDIO_CR1_VOLT_Pos 9 //7 3.3V    6 3.0V    5 1.8V
-#define SDIO_CR1_VOLT_Msk (0x07 << SDIO_CR1_VOLT_Pos)
-
-#define SDIO_CR2_CLKEN_Pos 0 //Internal Clock Enable
-#define SDIO_CR2_CLKEN_Msk (0x01 << SDIO_CR2_CLKEN_Pos)
-#define SDIO_CR2_CLKRDY_Pos 1 //Internal Clock Stable/Ready
-#define SDIO_CR2_CLKRDY_Msk (0x01 << SDIO_CR2_CLKRDY_Pos)
-#define SDIO_CR2_SDCLKEN_Pos 2 //SDCLK Enable
-#define SDIO_CR2_SDCLKEN_Msk (0x01 << SDIO_CR2_SDCLKEN_Pos)
-#define SDIO_CR2_SDCLKDIV_Pos 8 //SDCLK Frequency Div, 0x00 不分频    0x01 2分频    0x02 4分频    0x04 8分频    0x08    16分频    ...    0x80 256分频
-#define SDIO_CR2_SDCLKDIV_Msk (0xFF << SDIO_CR2_SDCLKDIV_Pos)
-#define SDIO_CR2_TIMEOUT_Pos 16 //0 TMCLK*2^13   1 TMCLK*2^14   ...   14 TMCLK*2^27
-#define SDIO_CR2_TIMEOUT_Msk (0x0F << SDIO_CR2_TIMEOUT_Pos)
-#define SDIO_CR2_RSTALL_Pos 24 //Software Reset for All
-#define SDIO_CR2_RSTALL_Msk (0x01 << SDIO_CR2_RSTALL_Pos)
-#define SDIO_CR2_RSTCMD_Pos 25 //Software Reset for CMD Line
-#define SDIO_CR2_RSTCMD_Msk (0x01 << SDIO_CR2_RSTCMD_Pos)
-#define SDIO_CR2_RSTDAT_Pos 26 //Software Reset for DAT Line
-#define SDIO_CR2_RSTDAT_Msk (0x01 << SDIO_CR2_RSTDAT_Pos)
-
-#define SDIO_IF_CMDDONE_Pos 0
-#define SDIO_IF_CMDDONE_Msk (0x01 << SDIO_IF_CMDDONE_Pos)
-#define SDIO_IF_TRXDONE_Pos 1
-#define SDIO_IF_TRXDONE_Msk (0x01 << SDIO_IF_TRXDONE_Pos)
-#define SDIO_IF_BLKGAP_Pos 2
-#define SDIO_IF_BLKGAP_Msk (0x01 << SDIO_IF_BLKGAP_Pos)
-#define SDIO_IF_DMADONE_Pos 3
-#define SDIO_IF_DMADONE_Msk (0x01 << SDIO_IF_DMADONE_Pos)
-#define SDIO_IF_BUFWRRDY_Pos 4
-#define SDIO_IF_BUFWRRDY_Msk (0x01 << SDIO_IF_BUFWRRDY_Pos)
-#define SDIO_IF_BUFRDRDY_Pos 5
-#define SDIO_IF_BUFRDRDY_Msk (0x01 << SDIO_IF_BUFRDRDY_Pos)
-#define SDIO_IF_CARDINSR_Pos 6
-#define SDIO_IF_CARDINSR_Msk (0x01 << SDIO_IF_CARDINSR_Pos)
-#define SDIO_IF_CARDRMOV_Pos 7
-#define SDIO_IF_CARDRMOV_Msk (0x01 << SDIO_IF_CARDRMOV_Pos)
-#define SDIO_IF_CARD_Pos 8
-#define SDIO_IF_CARD_Msk (0x01 << SDIO_IF_CARD_Pos)
-#define SDIO_IF_ERROR_Pos 15
-#define SDIO_IF_ERROR_Msk (0x01 << SDIO_IF_ERROR_Pos)
-#define SDIO_IF_CMDTIMEOUT_Pos 16
-#define SDIO_IF_CMDTIMEOUT_Msk (0x01 << SDIO_IF_CMDTIMEOUT_Pos)
-#define SDIO_IF_CMDCRCERR_Pos 17
-#define SDIO_IF_CMDCRCERR_Msk (0x01 << SDIO_IF_CMDCRCERR_Pos)
-#define SDIO_IF_CMDENDERR_Pos 18
-#define SDIO_IF_CMDENDERR_Msk (0x01 << SDIO_IF_CMDENDCERR_Pos)
-#define SDIO_IF_CMDIDXERR_Pos 19
-#define SDIO_IF_CMDIDXERR_Msk (0x01 << SDIO_IF_CMDIDXCERR_Pos)
-#define SDIO_IF_DATTIMEOUT_Pos 20
-#define SDIO_IF_DATTIMEOUT_Msk (0x01 << SDIO_IF_DATTIMEOUT_Pos)
-#define SDIO_IF_DATCRCERR_Pos 21
-#define SDIO_IF_DATCRCERR_Msk (0x01 << SDIO_IF_DATCRCERR_Pos)
-#define SDIO_IF_DATENDERR_Pos 22
-#define SDIO_IF_DATENDERR_Msk (0x01 << SDIO_IF_DATENDCERR_Pos)
-#define SDIO_IF_CURLIMERR_Pos 23
-#define SDIO_IF_CURLIMERR_Msk (0x01 << SDIO_IF_CURLIMERR_Pos)
-#define SDIO_IF_CMD12ERR_Pos 24
-#define SDIO_IF_CMD12ERR_Msk (0x01 << SDIO_IF_CMD12ERR_Pos)
-#define SDIO_IF_DMAERR_Pos 25
-#define SDIO_IF_DMAERR_Msk (0x01 << SDIO_IF_DMAERR_Pos)
-#define SDIO_IF_RESPERR_Pos 28
-#define SDIO_IF_RESPERR_Msk (0x01 << SDIO_IF_RESPERR_Pos)
-
-#define SDIO_IE_CMDDONE_Pos 0 //Command Complete Status Enable
-#define SDIO_IE_CMDDONE_Msk (0x01 << SDIO_IE_CMDDONE_Pos)
-#define SDIO_IE_TRXDONE_Pos 1 //Transfer Complete Status Enable
-#define SDIO_IE_TRXDONE_Msk (0x01 << SDIO_IE_TRXDONE_Pos)
-#define SDIO_IE_BLKGAP_Pos 2 //Block Gap Event Status Enable
-#define SDIO_IE_BLKGAP_Msk (0x01 << SDIO_IE_BLKGAP_Pos)
-#define SDIO_IE_DMADONE_Pos 3 //DMA Interrupt Status Enable
-#define SDIO_IE_DMADONE_Msk (0x01 << SDIO_IE_DMADONE_Pos)
-#define SDIO_IE_BUFWRRDY_Pos 4 //Buffer Write Ready Status Enable
-#define SDIO_IE_BUFWRRDY_Msk (0x01 << SDIO_IE_BUFWRRDY_Pos)
-#define SDIO_IE_BUFRDRDY_Pos 5 //Buffer Read Ready Status Enable
-#define SDIO_IE_BUFRDRDY_Msk (0x01 << SDIO_IE_BUFRDRDY_Pos)
-#define SDIO_IE_CARDINSR_Pos 6 //Card Insertion Status Enable
-#define SDIO_IE_CARDINSR_Msk (0x01 << SDIO_IE_CARDINSR_Pos)
-#define SDIO_IE_CARDRMOV_Pos 7 //Card Removal Status Enable
-#define SDIO_IE_CARDRMOV_Msk (0x01 << SDIO_IE_CARDRMOV_Pos)
-#define SDIO_IE_CARD_Pos 8
-#define SDIO_IE_CARD_Msk (0x01 << SDIO_IE_CARD_Pos)
-#define SDIO_IE_CMDTIMEOUT_Pos 16 //Command Timeout Error Status Enable
-#define SDIO_IE_CMDTIMEOUT_Msk (0x01 << SDIO_IE_CMDTIMEOUT_Pos)
-#define SDIO_IE_CMDCRCERR_Pos 17 //Command CRC Error Status Enable
-#define SDIO_IE_CMDCRCERR_Msk (0x01 << SDIO_IE_CMDCRCERR_Pos)
-#define SDIO_IE_CMDENDERR_Pos 18 //Command End Bit Error Status Enable
-#define SDIO_IE_CMDENDERR_Msk (0x01 << SDIO_IE_CMDENDCERR_Pos)
-#define SDIO_IE_CMDIDXERR_Pos 19 //Command Index Error Status Enable
-#define SDIO_IE_CMDIDXERR_Msk (0x01 << SDIO_IE_CMDIDXCERR_Pos)
-#define SDIO_IE_DATTIMEOUT_Pos 20 //Data Timeout Error Status Enable
-#define SDIO_IE_DATTIMEOUT_Msk (0x01 << SDIO_IE_DATTIMEOUT_Pos)
-#define SDIO_IE_DATCRCERR_Pos 21 //Data CRC Error Status Enable
-#define SDIO_IE_DATCRCERR_Msk (0x01 << SDIO_IE_DATCRCERR_Pos)
-#define SDIO_IE_DATENDERR_Pos 22 //Data End Bit Error Status Enable
-#define SDIO_IE_DATENDERR_Msk (0x01 << SDIO_IE_DATENDCERR_Pos)
-#define SDIO_IE_CURLIMERR_Pos 23 //Current Limit Error Status Enable
-#define SDIO_IE_CURLIMERR_Msk (0x01 << SDIO_IE_CURLIMERR_Pos)
-#define SDIO_IE_CMD12ERR_Pos 24 //Auto CMD12 Error Status Enable
-#define SDIO_IE_CMD12ERR_Msk (0x01 << SDIO_IE_CMD12ERR_Pos)
-#define SDIO_IE_DMAERR_Pos 25 //ADMA Error Status Enable
-#define SDIO_IE_DMAERR_Msk (0x01 << SDIO_IE_DMAERR_Pos)
-#define SDIO_IE_RESPERR_Pos 28 //Target Response Error Status Enable
-#define SDIO_IE_RESPERR_Msk (0x01 << SDIO_IE_RESPERR_Pos)
-
-#define SDIO_IM_CMDDONE_Pos 0
-#define SDIO_IM_CMDDONE_Msk (0x01 << SDIO_IM_CMDDONE_Pos)
-#define SDIO_IM_TRXDONE_Pos 1
-#define SDIO_IM_TRXDONE_Msk (0x01 << SDIO_IM_TRXDONE_Pos)
-#define SDIO_IM_BLKGAP_Pos 2
-#define SDIO_IM_BLKGAP_Msk (0x01 << SDIO_IM_BLKGAP_Pos)
-#define SDIO_IM_DMADONE_Pos 3
-#define SDIO_IM_DMADONE_Msk (0x01 << SDIO_IM_DMADONE_Pos)
-#define SDIO_IM_BUFWRRDY_Pos 4
-#define SDIO_IM_BUFWRRDY_Msk (0x01 << SDIO_IM_BUFWRRDY_Pos)
-#define SDIO_IM_BUFRDRDY_Pos 5
-#define SDIO_IM_BUFRDRDY_Msk (0x01 << SDIO_IM_BUFRDRDY_Pos)
-#define SDIO_IM_CARDINSR_Pos 6
-#define SDIO_IM_CARDINSR_Msk (0x01 << SDIO_IM_CARDINSR_Pos)
-#define SDIO_IM_CARDRMOV_Pos 7
-#define SDIO_IM_CARDRMOV_Msk (0x01 << SDIO_IM_CARDRMOV_Pos)
-#define SDIO_IM_CARD_Pos 8
-#define SDIO_IM_CARD_Msk (0x01 << SDIO_IM_CARD_Pos)
-#define SDIO_IM_CMDTIMEOUT_Pos 16
-#define SDIO_IM_CMDTIMEOUT_Msk (0x01 << SDIO_IM_CMDTIMEOUT_Pos)
-#define SDIO_IM_CMDCRCERR_Pos 17
-#define SDIO_IM_CMDCRCERR_Msk (0x01 << SDIO_IM_CMDCRCERR_Pos)
-#define SDIO_IM_CMDENDERR_Pos 18
-#define SDIO_IM_CMDENDERR_Msk (0x01 << SDIO_IM_CMDENDCERR_Pos)
-#define SDIO_IM_CMDIDXERR_Pos 19
-#define SDIO_IM_CMDIDXERR_Msk (0x01 << SDIO_IM_CMDIDXCERR_Pos)
-#define SDIO_IM_DATTIMEOUT_Pos 20
-#define SDIO_IM_DATTIMEOUT_Msk (0x01 << SDIO_IM_DATTIMEOUT_Pos)
-#define SDIO_IM_DATCRCERR_Pos 21
-#define SDIO_IM_DATCRCERR_Msk (0x01 << SDIO_IM_DATCRCERR_Pos)
-#define SDIO_IM_DATENDERR_Pos 22
-#define SDIO_IM_DATENDERR_Msk (0x01 << SDIO_IM_DATENDCERR_Pos)
-#define SDIO_IM_CURLIMERR_Pos 23
-#define SDIO_IM_CURLIMERR_Msk (0x01 << SDIO_IM_CURLIMERR_Pos)
-#define SDIO_IM_CMD12ERR_Pos 24
-#define SDIO_IM_CMD12ERR_Msk (0x01 << SDIO_IM_CMD12ERR_Pos)
-#define SDIO_IM_DMAERR_Pos 25
-#define SDIO_IM_DMAERR_Msk (0x01 << SDIO_IM_DMAERR_Pos)
-#define SDIO_IM_RESPERR_Pos 28
-#define SDIO_IM_RESPERR_Msk (0x01 << SDIO_IM_RESPERR_Pos)
-
-typedef struct
-{
-    __IO uint32_t DATA;
-    __IO uint32_t ADDR;
-    __IO uint32_t SWM_ERASE;
-    __IO uint32_t CACHE;
-    __IO uint32_t CFG0;
-    __IO uint32_t CFG1;
-    __IO uint32_t CFG2;
-    __IO uint32_t CFG3;
-    __IO uint32_t STAT;
-} FLASH_Typedef;
-
-#define FLASH_ERASE_REQ_Pos 31
-#define FLASH_ERASE_REQ_Msk (0x01u << FLASH_ERASE_REQ_Pos)
-
-#define FLASH_CACHE_PROG_Pos 2
-#define FLASH_CACHE_PROG_Msk (0x01 << FLASH_CACHE_PROG_Pos)
-#define FLASH_CACHE_CLEAR_Pos 3
-#define FLASH_CACHE_CLEAR_Msk (0x01 << FLASH_CACHE_CLEAR_Pos)
-
-#define FLASH_STAT_ERASE_GOING_Pos 0
-#define FLASH_STAT_ERASE_GOING_Msk (0X01 << FLASH_STAT_ERASE_GOING_Pos)
-#define FLASH_STAT_PROG_GOING_Pos 1
-#define FLASH_STAT_PROG_GOING_Msk (0x01 << FLASH_STAT_PROG_GOING_Pos)
-#define FALSH_STAT_FIFO_EMPTY_Pos 3
-#define FLASH_STAT_FIFO_EMPTY_Msk (0x01 << FALSH_STAT_FIFO_EMPTY_Pos)
-#define FALSH_STAT_FIFO_FULL_Pos 4
-#define FLASH_STAT_FIFO_FULL_Msk (0x01 << FALSH_STAT_FIFO_FULL_Pos)
-
-typedef struct
-{
-    __IO uint32_t CR;
-} SRAMC_TypeDef;
-
-#define SRAMC_CR_RWTIME_Pos 0 //读写操作持续多少个时钟周期。0表示1个时钟周期。最小设置为4
-#define SRAMC_CR_RWTIME_Msk (0x0F << SRAMC_CR_RWTIME_Pos)
-#define SRAMC_CR_BYTEIF_Pos 4 //外部SRAM数据宽度，0 16位    1 8位
-#define SRAMC_CR_BYTEIF_Msk (0x01 << SRAMC_CR_BYTEIF_Pos)
-#define SRAMC_CR_HBLBDIS_Pos 5 //1 ADDR[23:22]为地址线   0 ADDR[23]为高字节使能，ADDR[22]为低字节使能
-#define SRAMC_CR_HBLBDIS_Msk (0x01 << SRAMC_CR_HBLBDIS_Pos)
-
-typedef struct
-{
-    __IO uint32_t CR0;
-
-    __IO uint32_t CR1;
-
-    __IO uint32_t REFRESH;
-
-    __IO uint32_t NOPNUM; //[15:0] 初始化完成后，在正常操作之前，发送多少个NOP命令
-
-    __IO uint32_t LATCH;
-
-    __IO uint32_t REFDONE; //[0] Frefresh Done，上电初始化完成
-} SDRAMC_TypeDef;
-
-#define SDRAMC_CR0_BURSTLEN_Pos 0 //必须取2，表示Burst Length为4
-#define SDRAMC_CR0_BURSTLEN_Msk (0x07 << SDRAMC_CR0_BURSTLEN_Pos)
-#define SDRAMC_CR0_CASDELAY_Pos 4 //CAS Latency， 2 2    3 3
-#define SDRAMC_CR0_CASDELAY_Msk (0x07 << SDRAMC_CR0_CASDELAY_Pos)
-
-#define SDRAMC_CR1_TRP_Pos 0
-#define SDRAMC_CR1_TRP_Msk (0x07 << SDRAMC_CR1_TRP_Pos)
-#define SDRAMC_CR1_TRCD_Pos 3
-#define SDRAMC_CR1_TRCD_Msk (0x07 << SDRAMC_CR1_TRCD_Pos)
-#define SDRAMC_CR1_TRC_Pos 6
-#define SDRAMC_CR1_TRC_Msk (0x0F << SDRAMC_CR1_TRC_Pos)
-#define SDRAMC_CR1_TRAS_Pos 10
-#define SDRAMC_CR1_TRAS_Msk (0x07 << SDRAMC_CR1_TRAS_Pos)
-#define SDRAMC_CR1_TRRD_Pos 13
-#define SDRAMC_CR1_TRRD_Msk (0x03 << SDRAMC_CR1_TRRD_Pos)
-#define SDRAMC_CR1_TMRD_Pos 15
-#define SDRAMC_CR1_TMRD_Msk (0x07 << SDRAMC_CR1_TMRD_Pos)
-#define SDRAMC_CR1_32BIT_Pos 18 //SDRAMC的接口数据位宽，1 32bit    0 16bit
-#define SDRAMC_CR1_32BIT_Msk (0x01 << SDRAMC_CR1_32BIT_Pos)
-#define SDRAMC_CR1_BANK_Pos 19 //SDRAM每个颗粒有几个bank，0 2 banks    1 4 banks
-#define SDRAMC_CR1_BANK_Msk (0x01 << SDRAMC_CR1_BANK_Pos)
-#define SDRAMC_CR1_CELL32BIT_Pos 20 //SDRAM颗粒的位宽，1 32bit    0 16bit
-#define SDRAMC_CR1_CELL32BIT_Msk (0x01 << SDRAMC_CR1_CELL32BIT_Pos)
-#define SDRAMC_CR1_CELLSIZE_Pos 21 //SDRAM颗粒的容量，0 64Mb    1 128Mb    2 256Mb    3 16Mb
-#define SDRAMC_CR1_CELLSIZE_Msk (0x03 << SDRAMC_CR1_CELLSIZE_Pos)
-#define SDRAMC_CR1_HIGHSPEED_Pos 23 //当hclk大于100MHz时，这一位必须配置为1，否则为0
-#define SDRAMC_CR1_HIGHSPEED_Msk (0x01 << SDRAMC_CR1_HIGHSPEED_Pos)
-
-#define SDRAMC_REFRESH_RATE_Pos 0
-#define SDRAMC_REFRESH_RATE_Msk (0xFFF << SDRAMC_REFRESH_RATE_Pos)
-#define SDRAMC_REFRESH_EN_Pos 12
-#define SDRAMC_REFRESH_EN_Msk (0x01 << SDRAMC_REFRESH_EN_Pos)
-
-#define SDRAMC_LATCH_INEDGE_Pos 0 //哪个沿来锁存从SDRAM中读回的数据，0 上升沿    1 下降沿
-#define SDRAMC_LATCH_INEDGE_Msk (0x01 << SDRAMC_LATCH_INEDGE_Pos)
-#define SDRAMC_LATCH_OUTEDGE_Pos 1 //哪个沿去锁存送给SDRAM的数据，1 上升沿    0 下降沿
-#define SDRAMC_LATCH_OUTEDGE_Msk (0x01 << SDRAMC_LATCH_OUTEDGE_Pos)
-#define SDRAMC_LATCH_WAITST_Pos 2
-#define SDRAMC_LATCH_WAITST_Msk (0x01 << SDRAMC_LATCH_WAITST_Pos)
-
-typedef struct
-{
-    __IO uint32_t IE;
-
-    __IO uint32_t IF; //写1清零
-
-    __IO uint32_t IM;
-
-    __IO uint32_t CR;
-
-    __IO uint32_t ADDR;
-
-    __IO uint32_t CMD;
-} NORFLC_TypeDef;
-
-#define NORFLC_IE_FINISH_Pos 0
-#define NORFLC_IE_FINISH_Msk (0x01 << NORFLC_IE_FINISH_Pos)
-#define NORFLC_IE_TIMEOUT_Pos 1
-#define NORFLC_IE_TIMEOUT_Msk (0x01 << NORFLC_IE_TIMEOUT_Pos)
-
-#define NORFLC_IF_FINISH_Pos 0
-#define NORFLC_IF_FINISH_Msk (0x01 << NORFLC_IF_FINISH_Pos)
-#define NORFLC_IF_TIMEOUT_Pos 1
-#define NORFLC_IF_TIMEOUT_Msk (0x01 << NORFLC_IF_TIMEOUT_Pos)
-
-#define NORFLC_IM_FINISH_Pos 0
-#define NORFLC_IM_FINISH_Msk (0x01 << NORFLC_IM_FINISH_Pos)
-#define NORFLC_IM_TIMEOUT_Pos 1
-#define NORFLC_IM_TIMEOUT_Msk (0x01 << NORFLC_IM_TIMEOUT_Pos)
-
-#define NORFLC_CR_RDTIME_Pos 0 //Oen下降沿后多少个时钟周期后采样读回的数据。0表示1个时钟周期
-#define NORFLC_CR_RDTIME_Msk (0x1F << NORFLC_CR_RDTIME_Pos)
-#define NORFLC_CR_WRTIME_Pos 5 //输出Wen的低电平宽度。0表示1个时钟周期
-#define NORFLC_CR_WRTIME_Msk (0x07 << NORFLC_CR_WRTIME_Pos)
-#define NORFLC_CR_BYTEIF_Pos 8 //外部NOR FLASH数据宽度，1 8位    0 16位
-#define NORFLC_CR_BYTEIF_Msk (0x01 << NORFLC_CR_BYTEIF_Pos)
-
-#define NORFLC_CMD_DATA_Pos 0 //在PROGRAM命令中，DATA是要写入NOR FLASH的数据；在READ命令中，DATA是从NOR FLASH读回的数据
-#define NORFLC_CMD_DATA_Msk (0xFFFF << NORFLC_CMD_DATA_Pos)
-#define NORFLC_CMD_CMD_Pos 16 //需要执行的命令，0 READ   1 RESET   2 AUTOMATIC SELECT   3 PROGRAM   4 CHIP ERASE   5 SECTOR ERASE
-#define NORFLC_CMD_CMD_Msk (0x07 << NORFLC_CMD_CMD_Pos)
-
-typedef struct
-{
-    __IO uint32_t CR;
-
-    __O uint32_t DATAIN;
-
-    __IO uint32_t INIVAL;
-
-    __I uint32_t RESULT;
-} CRC_TypeDef;
-
-#define CRC_CR_EN_Pos 0
-#define CRC_CR_EN_Msk (0x01 << CRC_CR_EN_Pos)
-#define CRC_CR_OREV_Pos 1 //输出结果是否翻转
-#define CRC_CR_OREV_Msk (0x01 << CRC_CR_OREV_Pos)
-#define CRC_CR_ONOT_Pos 2 //输出结果是否取反
-#define CRC_CR_ONOT_Msk (0x01 << CRC_CR_ONOT_Pos)
-#define CRC_CR_CRC16_Pos 3 //1 CRC16    0 CRC32
-#define CRC_CR_CRC16_Msk (0x01 << CRC_CR_CRC16_Pos)
-#define CRC_CR_IBITS_Pos 4 //输入数据有效位数 0 32位    1 16位    2 8位
-#define CRC_CR_IBITS_Msk (0x03 << CRC_CR_IBITS_Pos)
-
-typedef struct
-{
-    __IO uint32_t MINSEC; //分秒计数
-
-    __IO uint32_t DATHUR; //日时计数
-
-    __IO uint32_t MONDAY; //月周计数
-
-    __IO uint32_t YEAR; //[11:0] 年计数，支持1901-2199
-
-    __IO uint32_t MINSECAL; //分秒闹铃设置
-
-    __IO uint32_t DAYHURAL; //周时闹铃设置
-
-    __IO uint32_t LOAD; //将设置寄存器中的值同步到RTC中，同步完成自动清零
-
-    __IO uint32_t IE;
-
-    __IO uint32_t IF; //写1清零
-
-    __IO uint32_t EN; //[0] 1 RTC使能
-
-    __IO uint32_t CFGABLE; //[0] 1 RTC可配置
-
-    __IO uint32_t TRIM; //时钟调整
-
-    __IO uint32_t TRIMM; //时钟微调整
-} RTC_TypeDef;
-
-#define RTC_LOAD_TIME_Pos 0
-#define RTC_LOAD_TIME_Msk (0x01 << RTC_LOAD_TIME_Pos)
-#define RTC_LOAD_ALARM_Pos 1
-#define RTC_LOAD_ALARM_Msk (0x01 << RTC_LOAD_ALARM_Pos)
-
-#define RTC_MINSEC_SEC_Pos 0 //秒计数，取值0--59
-#define RTC_MINSEC_SEC_Msk (0x3F << RTC_MINSEC_SEC_Pos)
-#define RTC_MINSEC_MIN_Pos 6 //分钟计数，取值0--59
-#define RTC_MINSEC_MIN_Msk (0x3F << RTC_MINSEC_MIN_Pos)
-
-#define RTC_DATHUR_HOUR_Pos 0 //小时计数，取值0--23
-#define RTC_DATHUR_HOUR_Msk (0x1F << RTC_DATHUR_HOUR_Pos)
-#define RTC_DATHUR_DATE_Pos 5 //date of month，取值1--31
-#define RTC_DATHUR_DATE_Msk (0x1F << RTC_DATHUR_DATE_Pos)
-
-#define RTC_MONDAY_DAY_Pos 0 //day of week，取值0--6
-#define RTC_MONDAY_DAY_Msk (0x07 << RTC_MONDAY_DAY_Pos)
-#define RTC_MONDAY_MON_Pos 3 //月份计数，取值1--12
-#define RTC_MONDAY_MON_Msk (0x0F << RTC_MONDAY_MON_Pos)
-
-#define RTC_MINSECAL_SEC_Pos 0 //闹钟秒设置
-#define RTC_MINSECAL_SEC_Msk (0x3F << RTC_MINSECAL_SEC_Pos)
-#define RTC_MINSECAL_MIN_Pos 6 //闹钟分钟设置
-#define RTC_MINSECAL_MIN_Msk (0x3F << RTC_MINSECAL_MIN_Pos)
-
-#define RTC_DAYHURAL_HOUR_Pos 0 //闹钟小时设置
-#define RTC_DAYHURAL_HOUR_Msk (0x1F << RTC_DAYHURAL_HOUR_Pos)
-#define RTC_DAYHURAL_SUN_Pos 5 //周日闹钟有效
-#define RTC_DAYHURAL_SUN_Msk (0x01 << RTC_DAYHURAL_SUN_Pos)
-#define RTC_DAYHURAL_MON_Pos 6 //周一闹钟有效
-#define RTC_DAYHURAL_MON_Msk (0x01 << RTC_DAYHURAL_MON_Pos)
-#define RTC_DAYHURAL_TUE_Pos 7 //周二闹钟有效
-#define RTC_DAYHURAL_TUE_Msk (0x01 << RTC_DAYHURAL_TUE_Pos)
-#define RTC_DAYHURAL_WED_Pos 8 //周三闹钟有效
-#define RTC_DAYHURAL_WED_Msk (0x01 << RTC_DAYHURAL_WED_Pos)
-#define RTC_DAYHURAL_THU_Pos 9 //周四闹钟有效
-#define RTC_DAYHURAL_THU_Msk (0x01 << RTC_DAYHURAL_THU_Pos)
-#define RTC_DAYHURAL_FRI_Pos 10 //周五闹钟有效
-#define RTC_DAYHURAL_FRI_Msk (0x01 << RTC_DAYHURAL_FRI_Pos)
-#define RTC_DAYHURAL_SAT_Pos 11 //周六闹钟有效
-#define RTC_DAYHURAL_SAT_Msk (0x01 << RTC_DAYHURAL_SAT_Pos)
-
-#define RTC_IE_SEC_Pos 0 //秒中断使能
-#define RTC_IE_SEC_Msk (0x01 << RTC_IE_SEC_Pos)
-#define RTC_IE_MIN_Pos 1
-#define RTC_IE_MIN_Msk (0x01 << RTC_IE_MIN_Pos)
-#define RTC_IE_HOUR_Pos 2
-#define RTC_IE_HOUR_Msk (0x01 << RTC_IE_HOUR_Pos)
-#define RTC_IE_DATE_Pos 3
-#define RTC_IE_DATE_Msk (0x01 << RTC_IE_DATE_Pos)
-#define RTC_IE_ALARM_Pos 4
-#define RTC_IE_ALARM_Msk (0x01 << RTC_IE_ALARM_Pos)
-
-#define RTC_IF_SEC_Pos 0 //写1清零
-#define RTC_IF_SEC_Msk (0x01 << RTC_IF_SEC_Pos)
-#define RTC_IF_MIN_Pos 1
-#define RTC_IF_MIN_Msk (0x01 << RTC_IF_MIN_Pos)
-#define RTC_IF_HOUR_Pos 2
-#define RTC_IF_HOUR_Msk (0x01 << RTC_IF_HOUR_Pos)
-#define RTC_IF_DATE_Pos 3
-#define RTC_IF_DATE_Msk (0x01 << RTC_IF_DATE_Pos)
-#define RTC_IF_ALARM_Pos 4
-#define RTC_IF_ALARM_Msk (0x01 << RTC_IF_ALARM_Pos)
-
-#define RTC_TRIM_ADJ_Pos 0 //用于调整BASECNT的计数周期，默认为32768，如果DEC为1，则计数周期调整为32768-ADJ，否则调整为32768+ADJ
-#define RTC_TRIM_ADJ_Msk (0xFF << RTC_TRIM_ADJ_Pos)
-#define RTC_TRIM_DEC_Pos 8
-#define RTC_TRIM_DEC_Msk (0x01 << RTC_TRIM_DEC_Pos)
-
-#define RTC_TRIMM_CYCLE_Pos 0 /* 用于计数周期微调，如果INC为1，则第n个计数周期调整为(32768±ADJ)+1,否则调整为(32768±ADJ)-1 \
-                              //cycles=0时，不进行微调整；cycles=1，则n为2；cycles=7，则n为8；以此类推 */
-#define RTC_TRIMM_CYCLE_Msk (0x07 << RTC_TRIMM_CYCLE_Pos)
-#define RTC_TRIMM_INC_Pos 3
-#define RTC_TRIMM_INC_Msk (0x01 << RTC_TRIMM_INC_Pos)
-
-typedef struct
-{
-    __IO uint32_t LOAD; //喂狗使计数器装载LOAD值
-
-    __I uint32_t VALUE;
-
-    __IO uint32_t CR;
-
-    __IO uint32_t IF; //计数到0时硬件置位，软件写1清除标志
-
-    __IO uint32_t FEED; //写0x55喂狗
-} WDT_TypeDef;
-
-#define WDT_CR_EN_Pos 0
-#define WDT_CR_EN_Msk (0x01 << WDT_CR_EN_Pos)
-#define WDT_CR_RSTEN_Pos 1
-#define WDT_CR_RSTEN_Msk (0x01 << WDT_CR_RSTEN_Pos)
-
-/******************************************************************************/
-/*                       Peripheral memory map                            */
-/******************************************************************************/
-#define RAM_BASE 0x20000000
-#define AHB_BASE 0x40000000
-#define APB_BASE 0x40010000
-
-#define NORFLC_BASE 0x60000000
-#define NORFLM_BASE 0x61000000
-
-#define SRAMC_BASE 0x68000000
-#define SRAMM_BASE 0x69000000
-
-#define SDRAMC_BASE 0x78000000
-#define SDRAMM_BASE 0x70000000
-
-/* AHB Peripheral memory map */
-#define SYS_BASE (AHB_BASE + 0x00000)
-
-#define DMA_BASE (AHB_BASE + 0x01000)
-
-#define LCD_BASE (AHB_BASE + 0x02000)
-
-#define CRC_BASE (AHB_BASE + 0x03000)
-
-#define SDIO_BASE (AHB_BASE + 0x04000)
-
-/* APB Peripheral memory map */
-#define PORT_BASE (APB_BASE + 0x00000)
-
-#define GPIOA_BASE (APB_BASE + 0x01000)
-#define GPIOB_BASE (APB_BASE + 0x02000)
-#define GPIOC_BASE (APB_BASE + 0x03000)
-#define GPIOD_BASE (APB_BASE + 0x04000)
-#define GPIOM_BASE (APB_BASE + 0x05000)
-#define GPION_BASE (APB_BASE + 0x06000)
-#define GPIOP_BASE (APB_BASE + 0x08000)
-
-#define TIMR0_BASE (APB_BASE + 0x07000)
-#define TIMR1_BASE (APB_BASE + 0x0700C)
-#define TIMR2_BASE (APB_BASE + 0x07018)
-#define TIMR3_BASE (APB_BASE + 0x07024)
-#define TIMR4_BASE (APB_BASE + 0x07030)
-#define TIMR5_BASE (APB_BASE + 0x0703C)
-#define TIMRG_BASE (APB_BASE + 0x07060)
-
-#define WDT_BASE (APB_BASE + 0x09000)
-
-#define PWM0_BASE (APB_BASE + 0x0A000)
-#define PWM1_BASE (APB_BASE + 0x0A020)
-#define PWM2_BASE (APB_BASE + 0x0A040)
-#define PWM3_BASE (APB_BASE + 0x0A060)
-#define PWM4_BASE (APB_BASE + 0x0A080)
-#define PWM5_BASE (APB_BASE + 0x0A0A0)
-#define PWMG_BASE (APB_BASE + 0x0A180)
-
-#define RTC_BASE (APB_BASE + 0x0B000)
-
-#define ADC0_BASE (APB_BASE + 0x0C000)
-#define ADC1_BASE (APB_BASE + 0x0D000)
-
-#define FLASH_BASE (APB_BASE + 0x0F000)
-
-#define UART0_BASE (APB_BASE + 0x10000)
-#define UART1_BASE (APB_BASE + 0x11000)
-#define UART2_BASE (APB_BASE + 0x12000)
-#define UART3_BASE (APB_BASE + 0x13000)
-
-#define I2C0_BASE (APB_BASE + 0x18000)
-#define I2C1_BASE (APB_BASE + 0x19000)
-
-#define SPI0_BASE (APB_BASE + 0x1C000)
-#define SPI1_BASE (APB_BASE + 0x1D000)
-
-#define CAN_BASE (APB_BASE + 0x20000)
-
-/******************************************************************************/
-/*                       Peripheral declaration                          */
-/******************************************************************************/
-#define SYS ((SYS_TypeDef *)SYS_BASE)
-
-#define PORT ((PORT_TypeDef *)PORT_BASE)
-
-#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
-#define GPIOM ((GPIO_TypeDef *)GPIOM_BASE)
-#define GPION ((GPIO_TypeDef *)GPION_BASE)
-#define GPIOP ((GPIO_TypeDef *)GPIOP_BASE)
-
-#define TIMR0 ((TIMR_TypeDef *)TIMR0_BASE)
-#define TIMR1 ((TIMR_TypeDef *)TIMR1_BASE)
-#define TIMR2 ((TIMR_TypeDef *)TIMR2_BASE)
-#define TIMR3 ((TIMR_TypeDef *)TIMR3_BASE)
-#define TIMR4 ((TIMR_TypeDef *)TIMR4_BASE)
-#define TIMR5 ((TIMR_TypeDef *)TIMR5_BASE)
-#define TIMRG ((TIMRG_TypeDef *)TIMRG_BASE)
-
-#define UART0 ((UART_TypeDef *)UART0_BASE)
-#define UART1 ((UART_TypeDef *)UART1_BASE)
-#define UART2 ((UART_TypeDef *)UART2_BASE)
-#define UART3 ((UART_TypeDef *)UART3_BASE)
-
-#define SPI0 ((SPI_TypeDef *)SPI0_BASE)
-#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
-
-#define I2C0 ((I2C_TypeDef *)I2C0_BASE)
-#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
-
-#define ADC0 ((ADC_TypeDef *)ADC0_BASE)
-#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
-
-#define PWM0 ((PWM_TypeDef *)PWM0_BASE)
-#define PWM1 ((PWM_TypeDef *)PWM1_BASE)
-#define PWM2 ((PWM_TypeDef *)PWM2_BASE)
-#define PWM3 ((PWM_TypeDef *)PWM3_BASE)
-#define PWM4 ((PWM_TypeDef *)PWM4_BASE)
-#define PWM5 ((PWM_TypeDef *)PWM5_BASE)
-#define PWMG ((PWMG_TypeDef *)PWMG_BASE)
-
-#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
-
-#define DMA ((DMA_TypeDef *)DMA_BASE)
-
-#define CAN ((CAN_TypeDef *)CAN_BASE)
-
-#define LCD ((LCD_TypeDef *)LCD_BASE)
-
-#define CRC ((CRC_TypeDef *)CRC_BASE)
-
-#define RTC ((RTC_TypeDef *)RTC_BASE)
-
-#define WDT ((WDT_TypeDef *)WDT_BASE)
-
-#define FLASH ((FLASH_Typedef *)FLASH_BASE)
-
-#define SRAMC ((SRAMC_TypeDef *)SRAMC_BASE)
-
-#define NORFLC ((NORFLC_TypeDef *)NORFLC_BASE)
-
-#define SDRAMC ((SDRAMC_TypeDef *)SDRAMC_BASE)
-
-typedef void (*Func_void_void)(void);
-
-#include "SWM320_port.h"
-#include "SWM320_gpio.h"
-#include "SWM320_exti.h"
-#include "SWM320_timr.h"
-#include "SWM320_uart.h"
-#include "SWM320_spi.h"
-#include "SWM320_i2c.h"
-#include "SWM320_pwm.h"
-#include "SWM320_adc.h"
-#include "SWM320_dma.h"
-#include "SWM320_lcd.h"
-#include "SWM320_can.h"
-#include "SWM320_sdio.h"
-#include "SWM320_flash.h"
-#include "SWM320_norflash.h"
-#include "SWM320_sdram.h"
-#include "SWM320_sram.h"
-#include "SWM320_crc.h"
-#include "SWM320_rtc.h"
-#include "SWM320_wdt.h"
-
-#endif //__SWM320_H__

bsp/swm320/libraries/CMSIS/DeviceSupport/system_SWM320.h

@@ -1,28 +0,0 @@
-#ifndef __SYSTEM_SWM320_H__
-#define __SYSTEM_SWM320_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-    extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock)
-    extern uint32_t CyclesPerUs;     // Cycles per micro second
-
-    extern void SystemInit(void);
-
-    extern void SystemCoreClockUpdate(void);
-
-    extern void switchCLK_20MHz(void);
-    extern void switchCLK_40MHz(void);
-    extern void switchCLK_32KHz(void);
-    extern void switchCLK_XTAL(void);
-    extern void switchCLK_PLL(void);
-
-    extern void PLLInit(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__SYSTEM_SWM320_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_adc.h

@@ -1,77 +0,0 @@
-#ifndef __SWM320_ADC_H__
-#define __SWM320_ADC_H__
-
-typedef struct
-{
-    uint8_t clk_src;   //ADC转换时钟源：ADC_CLKSRC_HRC、ADC_CLKSRC_VCO_DIV16、ADC_CLKSRC_VCO_DIV32、ADC_CLKSRC_VCO_DIV32
-    uint8_t clk_div;   //ADC转换时钟分频，取值1--31
-    uint8_t pga_ref;   //PGA基准：PGA_REF_INTERNAL、PGA_REF_EXTERNAL
-    uint8_t channels;  //ADC转换通道选中，ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算）
-    uint8_t samplAvg;  //采样取平均，触发启动ADC转换后，ADC在一个通道上连续采样、转换多次，并将它们的平均值作为该通道转换结果
-    uint8_t trig_src;  //ADC触发方式：ADC_TRIGSRC_SW、ADC_TRIGSRC_PWM、ADC_TRIGSRC_TIMR2、ADC_TRIGSRC_TIMR3
-    uint8_t Continue;  //在软件触发模式下：1 连续转换模式，启动后一直采样、转换，直到软件清除START位
-                       //                  0 单次转换模式，转换完成后START位自动清除停止转换
-    uint8_t EOC_IEn;   //EOC中断使能，可针对每个通道设置，其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算）
-    uint8_t OVF_IEn;   //OVF中断使能，可针对每个通道设置，其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算）
-    uint8_t HFULL_IEn; //FIFO半满中断使能，可针对每个通道设置，其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算）
-    uint8_t FULL_IEn;  //FIFO  满中断使能，可针对每个通道设置，其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算）
-} ADC_InitStructure;
-
-#define ADC_CH0 0x01
-#define ADC_CH1 0x02
-#define ADC_CH2 0x04
-#define ADC_CH3 0x08
-#define ADC_CH4 0x10
-#define ADC_CH5 0x20
-#define ADC_CH6 0x40
-#define ADC_CH7 0x80
-
-#define ADC_CLKSRC_HRC 1
-#define ADC_CLKSRC_VCO_DIV16 2
-#define ADC_CLKSRC_VCO_DIV32 3
-#define ADC_CLKSRC_VCO_DIV64 4
-
-#define ADC_AVG_SAMPLE1 0
-#define ADC_AVG_SAMPLE2 1 //一次启动连续采样、转换2次，并计算两次结果的平均值作为转换结果
-#define ADC_AVG_SAMPLE4 3
-#define ADC_AVG_SAMPLE8 7
-#define ADC_AVG_SAMPLE16 15
-
-#define ADC_TRIGSRC_SW 0 //软件触发，即ADC->START.GO写1启动转换
-#define ADC_TRIGSRC_PWM 1
-
-#define PGA_REF_INTERNAL 1 //PGA输入共模电平由内部电路产生，ADC_REFP和ADC_REFN可悬空
-#define PGA_REF_EXTERNAL 0 //PGA输入共模电平由外部引脚提供，(ADC_REFP + ADC_REFN) 电平值须与量程相同
-
-void ADC_Init(ADC_TypeDef *ADCx, ADC_InitStructure *initStruct); //ADC模数转换器初始化
-void ADC_Open(ADC_TypeDef *ADCx);                                //ADC开启，可以软件启动、或硬件触发ADC转换
-void ADC_Close(ADC_TypeDef *ADCx);                               //ADC关闭，无法软件启动、或硬件触发ADC转换
-void ADC_Start(ADC_TypeDef *ADCx);                               //启动指定ADC，开始模数转换
-void ADC_Stop(ADC_TypeDef *ADCx);                                //关闭指定ADC，停止模数转换
-
-uint32_t ADC_Read(ADC_TypeDef *ADCx, uint32_t chn);  //从指定通道读取转换结果
-uint32_t ADC_IsEOC(ADC_TypeDef *ADCx, uint32_t chn); //指定通道是否End Of Conversion
-
-void ADC_ChnSelect(ADC_TypeDef *ADCx, uint32_t chns);
-
-void ADC_IntEOCEn(ADC_TypeDef *ADCx, uint32_t chn);       //转换完成中断使能
-void ADC_IntEOCDis(ADC_TypeDef *ADCx, uint32_t chn);      //转换完成中断禁止
-void ADC_IntEOCClr(ADC_TypeDef *ADCx, uint32_t chn);      //转换完成中断标志清除
-uint32_t ADC_IntEOCStat(ADC_TypeDef *ADCx, uint32_t chn); //转换完成中断状态
-
-void ADC_IntOVFEn(ADC_TypeDef *ADCx, uint32_t chn);       //数据溢出中断使能
-void ADC_IntOVFDis(ADC_TypeDef *ADCx, uint32_t chn);      //数据溢出中断禁止
-void ADC_IntOVFClr(ADC_TypeDef *ADCx, uint32_t chn);      //数据溢出中断标志清除
-uint32_t ADC_IntOVFStat(ADC_TypeDef *ADCx, uint32_t chn); //数据溢出中断状态
-
-void ADC_IntHFULLEn(ADC_TypeDef *ADCx, uint32_t chn);       //FIFO半满中断使能
-void ADC_IntHFULLDis(ADC_TypeDef *ADCx, uint32_t chn);      //FIFO半满中断禁止
-void ADC_IntHFULLClr(ADC_TypeDef *ADCx, uint32_t chn);      //FIFO半满中断标志清除
-uint32_t ADC_IntHFULLStat(ADC_TypeDef *ADCx, uint32_t chn); //FIFO半满中断状态
-
-void ADC_IntFULLEn(ADC_TypeDef *ADCx, uint32_t chn);       //FIFO满中断使能
-void ADC_IntFULLDis(ADC_TypeDef *ADCx, uint32_t chn);      //FIFO满中断禁止
-void ADC_IntFULLClr(ADC_TypeDef *ADCx, uint32_t chn);      //FIFO满中断标志清除
-uint32_t ADC_IntFULLStat(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断状态
-
-#endif //__SWM320_ADC_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_can.h

@@ -1,134 +0,0 @@
-#ifndef __SWM320_CAN_H__
-#define __SWM320_CAN_H__
-
-#define CAN_FRAME_STD 0
-#define CAN_FRAME_EXT 1
-
-typedef struct
-{
-    uint8_t Mode;       //CAN_MODE_NORMAL、CAN_MODE_LISTEN、CAN_MODE_SELFTEST
-    uint8_t CAN_BS1;    //CAN_BS1_1tq、CAN_BS1_2tq、... ... 、CAN_BS1_16tq
-    uint8_t CAN_BS2;    //CAN_BS2_1tq、CAN_BS2_2tq、... ... 、CAN_BS2_8tq
-    uint8_t CAN_SJW;    //CAN_SJW_1tq、CAN_SJW_2tq、CAN_SJW_3tq、CAN_SJW_4tq
-    uint32_t Baudrate;  //波特率，即位传输速率，取值1--1000000
-    uint8_t FilterMode; //CAN_FILTER_16b、CAN_FILTER_32b
-    union
-    {
-        uint32_t FilterMask32b; //FilterCheck & (~FilterMask) == ID & (~FilterMask)的Message通过过滤
-        struct
-        { // 0 must match    1 don't care
-            uint16_t FilterMask16b1;
-            uint16_t FilterMask16b2;
-        };
-    };
-    union
-    {
-        uint32_t FilterCheck32b;
-        struct
-        {
-            uint16_t FilterCheck16b1;
-            uint16_t FilterCheck16b2;
-        };
-    };
-    uint8_t RXNotEmptyIEn; //接收FIFO非空，有数据可读
-    uint8_t RXOverflowIEn; //接收FIFO溢出，有数据丢失
-    uint8_t ArbitrLostIEn; //控制器丢失仲裁变成接收方
-    uint8_t ErrPassiveIEn; //接收/发送错误计数值达到127
-} CAN_InitStructure;
-
-#define CAN_MODE_NORMAL 0   //常规模式
-#define CAN_MODE_LISTEN 1   //监听模式
-#define CAN_MODE_SELFTEST 2 //自测模式
-
-#define CAN_BS1_1tq 0
-#define CAN_BS1_2tq 1
-#define CAN_BS1_3tq 2
-#define CAN_BS1_4tq 3
-#define CAN_BS1_5tq 4
-#define CAN_BS1_6tq 5
-#define CAN_BS1_7tq 6
-#define CAN_BS1_8tq 7
-#define CAN_BS1_9tq 8
-#define CAN_BS1_10tq 9
-#define CAN_BS1_11tq 10
-#define CAN_BS1_12tq 11
-#define CAN_BS1_13tq 12
-#define CAN_BS1_14tq 13
-#define CAN_BS1_15tq 14
-#define CAN_BS1_16tq 15
-
-#define CAN_BS2_1tq 0
-#define CAN_BS2_2tq 1
-#define CAN_BS2_3tq 2
-#define CAN_BS2_4tq 3
-#define CAN_BS2_5tq 4
-#define CAN_BS2_6tq 5
-#define CAN_BS2_7tq 6
-#define CAN_BS2_8tq 7
-
-#define CAN_SJW_1tq 0
-#define CAN_SJW_2tq 1
-#define CAN_SJW_3tq 2
-#define CAN_SJW_4tq 3
-
-#define CAN_FILTER_16b 0 //两个16位过滤器
-#define CAN_FILTER_32b 1 //一个32位过滤器
-
-typedef struct
-{
-    uint32_t id;     //消息ID
-    uint8_t format;  //帧格式：CAN_FRAME_STD、CAN_FRAME_EXT
-    uint8_t remote;  //消息是否为远程帧
-    uint8_t size;    //接收到的数据个数
-    uint8_t data[8]; //接收到的数据
-} CAN_RXMessage;
-
-void CAN_Init(CAN_TypeDef *CANx, CAN_InitStructure *initStruct);
-void CAN_Open(CAN_TypeDef *CANx);
-void CAN_Close(CAN_TypeDef *CANx);
-
-void CAN_Transmit(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint8_t data[], uint32_t size, uint32_t once);
-void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32_t once);
-void CAN_Receive(CAN_TypeDef *CANx, CAN_RXMessage *msg);
-
-uint32_t CAN_TXComplete(CAN_TypeDef *CANx);
-uint32_t CAN_TXSuccess(CAN_TypeDef *CANx);
-
-void CAN_AbortTransmit(CAN_TypeDef *CANx);
-
-uint32_t CAN_TXBufferReady(CAN_TypeDef *CANx);
-uint32_t CAN_RXDataAvailable(CAN_TypeDef *CANx);
-
-void CAN_SetBaudrate(CAN_TypeDef *CANx, uint32_t baudrate, uint32_t CAN_BS1, uint32_t CAN_BS2, uint32_t CAN_SJW);
-
-void CAN_SetFilter32b(CAN_TypeDef *CANx, uint32_t check, uint32_t mask);
-void CAN_SetFilter16b(CAN_TypeDef *CANx, uint16_t check1, uint16_t mask1, uint16_t check2, uint16_t mask2);
-
-void CAN_INTRXNotEmptyEn(CAN_TypeDef *CANx);
-void CAN_INTRXNotEmptyDis(CAN_TypeDef *CANx);
-
-void CAN_INTTXBufEmptyEn(CAN_TypeDef *CANx);
-void CAN_INTTXBufEmptyDis(CAN_TypeDef *CANx);
-
-void CAN_INTErrWarningEn(CAN_TypeDef *CANx);
-void CAN_INTErrWarningDis(CAN_TypeDef *CANx);
-
-void CAN_INTRXOverflowEn(CAN_TypeDef *CANx);
-void CAN_INTRXOverflowDis(CAN_TypeDef *CANx);
-void CAN_INTRXOverflowClear(CAN_TypeDef *CANx);
-
-void CAN_INTWakeupEn(CAN_TypeDef *CANx);
-void CAN_INTWakeupDis(CAN_TypeDef *CANx);
-
-void CAN_INTErrPassiveEn(CAN_TypeDef *CANx);
-void CAN_INTErrPassiveDis(CAN_TypeDef *CANx);
-
-void CAN_INTArbitrLostEn(CAN_TypeDef *CANx);
-void CAN_INTArbitrLostDis(CAN_TypeDef *CANx);
-
-void CAN_INTBusErrorEn(CAN_TypeDef *CANx);
-void CAN_INTBusErrorDis(CAN_TypeDef *CANx);
-
-uint32_t CAN_INTStat(CAN_TypeDef *CANx);
-
-#endif //__SWM320_CAN_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_dma.h

@@ -1,17 +0,0 @@
-#ifndef __SWM320_DMA_H__
-#define __SWM320_DMA_H__
-
-#define DMA_CH0 0
-#define DMA_CH1 1
-#define DMA_CH2 2
-
-void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uint32_t dst_addr, uint32_t dst_addr_incr, uint32_t num_word, uint32_t int_en); //DMA通道配置，用于存储器间（如Flash和RAM间）搬运数据
-void DMA_CH_Open(uint32_t chn);                                                                                                                              //DMA通道打开
-void DMA_CH_Close(uint32_t chn);                                                                                                                             //DMA通道关闭
-
-void DMA_CH_INTEn(uint32_t chn);       //DMA中断使能，数据搬运完成后触发中断
-void DMA_CH_INTDis(uint32_t chn);      //DMA中断禁止，数据搬运完成后不触发中断
-void DMA_CH_INTClr(uint32_t chn);      //DMA中断标志清除
-uint32_t DMA_CH_INTStat(uint32_t chn); //DMA中断状态查询，1 数据搬运完成    0 数据搬运未完成
-
-#endif //__SWM320_DMA_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_exti.h

@@ -1,18 +0,0 @@
-#ifndef __SWM320_EXTI_H__
-#define __SWM320_EXTI_H__
-
-void EXTI_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t mode); //指定引脚外部中断初始化
-void EXTI_Open(GPIO_TypeDef *GPIOx, uint32_t n);                //指定引脚外部中断打开（即使能）
-void EXTI_Close(GPIO_TypeDef *GPIOx, uint32_t n);               //指定引脚外部中断关闭（即禁能）
-
-uint32_t EXTI_State(GPIO_TypeDef *GPIOx, uint32_t n);    //指定引脚是否触发了中断
-uint32_t EXTI_RawState(GPIO_TypeDef *GPIOx, uint32_t n); //指定引脚是否满足过/了中断触发条件，当此中断关闭时可通过调用此函数以查询的方式检测引脚上是否满足过/了中断触发条件
-void EXTI_Clear(GPIO_TypeDef *GPIOx, uint32_t n);        //指定引脚外部中断清除（即清除中断标志，以免再次进入此中断）
-
-#define EXTI_FALL_EDGE 0x00  //下降沿触发中断
-#define EXTI_RISE_EDGE 0x01  //上升沿触发中断
-#define EXTI_BOTH_EDGE 0x02  //双边沿触发中断
-#define EXTI_LOW_LEVEL 0x10  //低电平触发中断
-#define EXTI_HIGH_LEVEL 0x11 //高电平触发中断
-
-#endif //__SWM320_EXTI_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h

@@ -1,22 +0,0 @@
-#ifndef __SWM320_GPIO_H__
-#define __SWM320_GPIO_H__
-
-void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down); //引脚初始化，包含引脚方向、上拉电阻、下拉电阻
-
-void GPIO_SetBit(GPIO_TypeDef *GPIOx, uint32_t n);                  //将参数指定的引脚电平置高
-void GPIO_ClrBit(GPIO_TypeDef *GPIOx, uint32_t n);                  //将参数指定的引脚电平置低
-void GPIO_InvBit(GPIO_TypeDef *GPIOx, uint32_t n);                  //将参数指定的引脚电平反转
-uint32_t GPIO_GetBit(GPIO_TypeDef *GPIOx, uint32_t n);              //读取参数指定的引脚的电平状态
-void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w);     //将参数指定的从n开始的w位连续引脚的电平置高
-void GPIO_ClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w);     //将参数指定的从n开始的w位连续引脚的电平置低
-void GPIO_InvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w);     //将参数指定的从n开始的w位连续引脚的电平反转
-uint32_t GPIO_GetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //读取参数指定的从n开始的w位连续引脚的电平状态
-
-void GPIO_AtomicSetBit(GPIO_TypeDef *GPIOx, uint32_t n);
-void GPIO_AtomicClrBit(GPIO_TypeDef *GPIOx, uint32_t n);
-void GPIO_AtomicInvBit(GPIO_TypeDef *GPIOx, uint32_t n);
-void GPIO_AtomicSetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w);
-void GPIO_AtomicClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w);
-void GPIO_AtomicInvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w);
-
-#endif //__SWM320_GPIO_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h

@@ -1,31 +0,0 @@
-#ifndef __SWM320_I2C_H__
-#define __SWM320_I2C_H__
-
-typedef struct
-{
-    uint8_t Master; //1 主机模式
-    uint8_t Addr7b; //1 7位地址     0 10位地址
-
-    uint32_t MstClk; //主机传输时钟频率
-    uint8_t MstIEn;  //主机模式中断使能
-
-    uint16_t SlvAddr;     //从机地址
-    uint8_t SlvRxEndIEn;  //从机接收完成中断使能
-    uint8_t SlvTxEndIEn;  //从机发送完成中断使能
-    uint8_t SlvSTADetIEn; //从机检测到起始中断使能
-    uint8_t SlvSTODetIEn; //从机检测到终止中断使能
-    uint8_t SlvRdReqIEn;  //从机接收到读请求中断使能
-    uint8_t SlvWrReqIEn;  //从机接收到写请求中断使能
-} I2C_InitStructure;
-
-void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct);
-
-void I2C_Open(I2C_TypeDef *I2Cx);
-void I2C_Close(I2C_TypeDef *I2Cx);
-
-uint8_t I2C_Start(I2C_TypeDef *I2Cx, uint8_t addr);
-void I2C_Stop(I2C_TypeDef *I2Cx);
-uint8_t I2C_Write(I2C_TypeDef *I2Cx, uint8_t data);
-uint8_t I2C_Read(I2C_TypeDef *I2Cx, uint8_t ack);
-
-#endif //__SWM320_I2C_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h

@@ -1,70 +0,0 @@
-#ifndef __SWM320_LCD_H__
-#define __SWM320_LCD_H__
-
-typedef struct
-{
-    uint16_t HnPixel;   //水平方向像素个数，最大取值1024
-    uint16_t VnPixel;   //垂直方向像素个数，最大取值 768
-    uint8_t Hfp;        //horizonal front porch，最大取值32
-    uint8_t Hbp;        //horizonal back porch， 最大取值128
-    uint8_t Vfp;        //vertical front porch， 最大取值8
-    uint8_t Vbp;        //vertical back porch，  最大取值32
-    uint8_t ClkDiv;     //系统时钟经ClkDiv分频后产生DOCCLK，0 2分频    1 4分频    2 6分频    ... ...    31 64分频
-    uint8_t SamplEdge;  //屏幕在DOTCLK的哪个边沿采样数据：LCD_SAMPLEDGE_RISE、LCD_SAMPLEDGE_FALL
-    uint8_t ClkAlways;  //1 一直输出DOTCLK    0 只在传输数据时输出DOTCLK
-    uint8_t HsyncWidth; //HSYNC低电平持续多少个DOTCLK，取值：LCD_HSYNC_1DOTCLK、LCD_HSYNC_2DOTCLK、LCD_HSYNC_3DOTCLK、LCD_HSYNC_4DOTCLK
-
-    uint8_t IntEOTEn; //End of Transter（传输完成）中断使能
-} LCD_InitStructure;
-
-#define LCD_SAMPLEDGE_RISE 0 //屏幕在DOTCLK的上升沿采样数据
-#define LCD_SAMPLEDGE_FALL 1 //屏幕在DOTCLK的下降沿采样数据
-
-#define LCD_HSYNC_1DOTCLK 0 //1个DOTCLK
-#define LCD_HSYNC_2DOTCLK 1
-#define LCD_HSYNC_3DOTCLK 2
-#define LCD_HSYNC_4DOTCLK 3
-
-#define LCD_CLKDIV_2 0
-#define LCD_CLKDIV_4 1
-#define LCD_CLKDIV_6 2
-#define LCD_CLKDIV_8 3
-#define LCD_CLKDIV_10 4
-#define LCD_CLKDIV_12 5
-#define LCD_CLKDIV_14 6
-#define LCD_CLKDIV_16 7
-#define LCD_CLKDIV_18 8
-#define LCD_CLKDIV_20 9
-#define LCD_CLKDIV_22 10
-#define LCD_CLKDIV_24 11
-#define LCD_CLKDIV_26 12
-#define LCD_CLKDIV_28 13
-#define LCD_CLKDIV_30 14
-#define LCD_CLKDIV_32 15
-#define LCD_CLKDIV_34 16
-#define LCD_CLKDIV_36 17
-#define LCD_CLKDIV_38 18
-#define LCD_CLKDIV_40 19
-#define LCD_CLKDIV_42 20
-#define LCD_CLKDIV_44 21
-#define LCD_CLKDIV_46 22
-#define LCD_CLKDIV_48 23
-#define LCD_CLKDIV_50 24
-#define LCD_CLKDIV_52 25
-#define LCD_CLKDIV_54 26
-#define LCD_CLKDIV_56 27
-#define LCD_CLKDIV_58 28
-#define LCD_CLKDIV_60 29
-#define LCD_CLKDIV_62 30
-#define LCD_CLKDIV_64 31
-
-void LCD_Init(LCD_TypeDef *LCDx, LCD_InitStructure *initStruct);
-void LCD_Start(LCD_TypeDef *LCDx);
-uint32_t LCD_IsBusy(LCD_TypeDef *LCDx);
-
-void LCD_INTEn(LCD_TypeDef *LCDx);
-void LCD_INTDis(LCD_TypeDef *LCDx);
-void LCD_INTClr(LCD_TypeDef *LCDx);
-uint32_t LCD_INTStat(LCD_TypeDef *LCDx);
-
-#endif //__SWM320_LCD_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h

@@ -1,34 +0,0 @@
-#ifndef __SWM320_NORFLASH_H__
-#define __SWM320_NORFLASH_H__
-
-typedef struct
-{
-    uint8_t DataWidth; // 8、16
-
-    uint8_t WELowPulseTime; // WE# pulse width，单位为系统时钟周期，最大值为7
-    uint8_t OEPreValidTime; // Valid data output after OE# low，单位为系统时钟周期，最大值为15
-
-    uint8_t OperFinishIEn; // 操作(写入、擦除)完成中断使能
-    uint8_t OperTimeoutIEn;
-} NORFL_InitStructure;
-
-void NORFL_Init(NORFL_InitStructure *initStruct);
-uint32_t NORFL_ChipErase(void);
-uint32_t NORFL_SectorErase(uint32_t addr);
-uint32_t NORFL_Write(uint32_t addr, uint32_t data);
-uint32_t NORFL_Read(uint32_t addr);
-uint16_t NORFL_ReadID(uint32_t id_addr);
-
-/* 当前版本总线读只支持字读
-#define NORFL_Read8(addr)   *((volatile uint8_t  *)(NORFLM_BASE + addr))
-#define NORFL_Read16(addr)  *((volatile uint16_t *)(NORFLM_BASE + addr))    */
-#define NORFL_Read32(addr) *((volatile uint32_t *)(NORFLM_BASE + addr))
-
-#define NORFL_CMD_READ 0
-#define NORFL_CMD_RESET 1
-#define NORFL_CMD_AUTO_SELECT 2
-#define NORFL_CMD_PROGRAM 3
-#define NORFL_CMD_CHIP_ERASE 4
-#define NORFL_CMD_SECTOR_ERASE 5
-
-#endif // __SWM320_NORFLASH_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_port.c

@@ -1,220 +0,0 @@
-/******************************************************************************************************************************************
-* 文件名称: SWM320_port.c
-* 功能说明: SWM320单片机的端口引脚功能选择库函数
-* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1
-* 注意事项:
-* 版本日期: V1.1.0      2017年10月25日
-* 升级记录:
-*
-*
-*******************************************************************************************************************************************
-* @attention
-*
-* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
-* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
-* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
-* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
-* -ECTION WITH THEIR PRODUCTS.
-*
-* COPYRIGHT 2012 Synwit Technology
-*******************************************************************************************************************************************/
-#include "SWM320.h"
-#include "SWM320_port.h"
-
-/******************************************************************************************************************************************
-* 函数名称: PORT_Init()
-* 功能说明: 端口引脚功能选择，可用的功能见"SWM320_port.h"文件
-* 输    入: uint32_t PORTx            指定PORT端口，有效值包括PORTA、PORTB、PORTC、PORTM、PORTN、PORTP
-*           uint32_t n              指定PORT引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23
-*           uint32_t func           指定端口引脚要设定的功能，其可取值见"SWM320_port.h"文件
-*           uint32_t digit_in_en    数字输入使能
-* 输    出: 无
-* 注意事项: 当引脚标号n为偶数时，func取值只能是FUNMUX0开头的，如FUNMUX0_UART0_RXD
-*           当引脚标号n为奇数时，func取值只能是FUNMUX1开头的，如FUNMUX1_UART0_TXD
-******************************************************************************************************************************************/
-void PORT_Init(uint32_t PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en)
-{
-    switch ((uint32_t)PORTx)
-    {
-    case ((uint32_t)PORTA):
-        if (func > 99)
-        {
-            if (n < PIN6)
-            {
-                PORT->PORTA_MUX0 &= ~(0x1F << (n * 5));
-                PORT->PORTA_MUX0 |= (func - 100) << (n * 5);
-            }
-            else if (n < PIN12)
-            {
-                PORT->PORTA_MUX1 &= ~(0x1F << ((n - 6) * 5));
-                PORT->PORTA_MUX1 |= (func - 100) << ((n - 6) * 5);
-            }
-        }
-
-        PORT->PORTA_SEL &= ~(0x03 << (n * 2));
-        PORT->PORTA_SEL |= (func > 99 ? 1 : func) << (n * 2);
-
-        PORT->PORTA_INEN &= ~(0x01 << n);
-        PORT->PORTA_INEN |= (digit_in_en << n);
-        break;
-
-    case ((uint32_t)PORTB):
-        if (func > 99)
-        {
-            if (n < PIN6)
-            {
-                PORT->PORTB_MUX0 &= ~(0x1F << (n * 5));
-                PORT->PORTB_MUX0 |= (func - 100) << (n * 5);
-            }
-            else if (n < PIN12)
-            {
-                PORT->PORTB_MUX1 &= ~(0x1F << ((n - 6) * 5));
-                PORT->PORTB_MUX1 |= (func - 100) << ((n - 6) * 5);
-            }
-        }
-
-        PORT->PORTB_SEL &= ~(0x03 << (n * 2));
-        PORT->PORTB_SEL |= (func > 99 ? 1 : func) << (n * 2);
-
-        PORT->PORTB_INEN &= ~(0x01 << n);
-        PORT->PORTB_INEN |= (digit_in_en << n);
-        break;
-
-    case ((uint32_t)PORTC):
-        if (func > 99)
-        {
-            if (n < PIN6)
-            {
-                PORT->PORTC_MUX0 &= ~(0x1F << (n * 5));
-                PORT->PORTC_MUX0 |= (func - 100) << (n * 5);
-            }
-            else if (n < PIN12)
-            {
-                PORT->PORTC_MUX1 &= ~(0x1F << ((n - 6) * 5));
-                PORT->PORTC_MUX1 |= (func - 100) << ((n - 6) * 5);
-            }
-        }
-
-        PORT->PORTC_SEL &= ~(0x03 << (n * 2));
-        PORT->PORTC_SEL |= (func > 99 ? 1 : func) << (n * 2);
-
-        PORT->PORTC_INEN &= ~(0x01 << n);
-        PORT->PORTC_INEN |= (digit_in_en << n);
-        break;
-
-    case ((uint32_t)PORTM):
-        if (func > 99)
-        {
-            if (n < PIN6)
-            {
-                PORT->PORTM_MUX0 &= ~(0x1F << (n * 5));
-                PORT->PORTM_MUX0 |= (func - 100) << (n * 5);
-            }
-            else if (n < PIN12)
-            {
-                PORT->PORTM_MUX1 &= ~(0x1F << ((n - 6) * 5));
-                PORT->PORTM_MUX1 |= (func - 100) << ((n - 6) * 5);
-            }
-            else if (n < PIN18)
-            {
-                PORT->PORTM_MUX2 &= ~(0x1F << ((n - 12) * 5));
-                PORT->PORTM_MUX2 |= (func - 100) << ((n - 12) * 5);
-            }
-            else if (n < PIN24)
-            {
-                PORT->PORTM_MUX3 &= ~(0x1F << ((n - 18) * 5));
-                PORT->PORTM_MUX3 |= (func - 100) << ((n - 18) * 5);
-            }
-        }
-
-        if (n < 16)
-        {
-            PORT->PORTM_SEL0 &= ~(0x03 << (n * 2));
-            PORT->PORTM_SEL0 |= (func > 99 ? 1 : func) << (n * 2);
-        }
-        else
-        {
-            PORT->PORTM_SEL1 &= ~(0x03 << ((n - 16) * 2));
-            PORT->PORTM_SEL1 |= (func > 99 ? 1 : func) << ((n - 16) * 2);
-        }
-
-        PORT->PORTM_INEN &= ~(0x01 << n);
-        PORT->PORTM_INEN |= (digit_in_en << n);
-        break;
-
-    case ((uint32_t)PORTN):
-        if (func > 99)
-        {
-            if (n < PIN6)
-            {
-                PORT->PORTN_MUX0 &= ~(0x1F << (n * 5));
-                PORT->PORTN_MUX0 |= (func - 100) << (n * 5);
-            }
-            else if (n < PIN12)
-            {
-                PORT->PORTN_MUX1 &= ~(0x1F << ((n - 6) * 5));
-                PORT->PORTN_MUX1 |= (func - 100) << ((n - 6) * 5);
-            }
-            else if (n < PIN18)
-            {
-                PORT->PORTN_MUX2 &= ~(0x1F << ((n - 12) * 5));
-                PORT->PORTN_MUX2 |= (func - 100) << ((n - 12) * 5);
-            }
-        }
-
-        if (n < 16)
-        {
-            PORT->PORTN_SEL0 &= ~(0x03 << (n * 2));
-            PORT->PORTN_SEL0 |= (func > 99 ? 1 : func) << (n * 2);
-        }
-        else
-        {
-            PORT->PORTN_SEL1 &= ~(0x03 << ((n - 16) * 2));
-            PORT->PORTN_SEL1 |= (func > 99 ? 1 : func) << ((n - 16) * 2);
-        }
-
-        PORT->PORTN_INEN &= ~(0x01 << n);
-        PORT->PORTN_INEN |= (digit_in_en << n);
-        break;
-
-    case ((uint32_t)PORTP):
-        if (func > 99)
-        {
-            if (n < PIN6)
-            {
-                PORT->PORTP_MUX0 &= ~(0x1F << (n * 5));
-                PORT->PORTP_MUX0 |= (func - 100) << (n * 5);
-            }
-            else if (n < PIN12)
-            {
-                PORT->PORTP_MUX1 &= ~(0x1F << ((n - 6) * 5));
-                PORT->PORTP_MUX1 |= (func - 100) << ((n - 6) * 5);
-            }
-            else if (n < PIN18)
-            {
-                PORT->PORTP_MUX2 &= ~(0x1F << ((n - 12) * 5));
-                PORT->PORTP_MUX2 |= (func - 100) << ((n - 12) * 5);
-            }
-            else if (n < PIN24)
-            {
-                PORT->PORTP_MUX3 &= ~(0x1F << ((n - 18) * 5));
-                PORT->PORTP_MUX3 |= (func - 100) << ((n - 18) * 5);
-            }
-        }
-
-        if (n < 16)
-        {
-            PORT->PORTP_SEL0 &= ~(0x03 << (n * 2));
-            PORT->PORTP_SEL0 |= (func > 99 ? 1 : func) << (n * 2);
-        }
-        else
-        {
-            PORT->PORTP_SEL1 &= ~(0x03 << ((n - 16) * 2));
-            PORT->PORTP_SEL1 |= (func > 99 ? 1 : func) << ((n - 16) * 2);
-        }
-
-        PORT->PORTP_INEN &= ~(0x01 << n);
-        PORT->PORTP_INEN |= (digit_in_en << n);
-        break;
-    }
-}

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_port.h

@@ -1,474 +0,0 @@
-#ifndef __SWM320_PORT_H__
-#define __SWM320_PORT_H__
-
-void PORT_Init(uint32_t PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en); //端口引脚功能选择，其可取值如下：
-
-#define PORTA 0
-#define PORTB 1
-#define PORTC 2
-#define PORTM 3
-#define PORTN 4
-#define PORTP 5
-
-#define PORTA_PIN0_GPIO 0
-#define PORTA_PIN0_FUNMUX 1
-#define PORTA_PIN0_SWCLK 2
-
-#define PORTA_PIN1_GPIO 0
-#define PORTA_PIN1_FUNMUX 1
-#define PORTA_PIN1_SWDIO 2
-
-#define PORTA_PIN2_GPIO 0
-#define PORTA_PIN2_FUNMUX 1
-
-#define PORTA_PIN3_GPIO 0
-#define PORTA_PIN3_FUNMUX 1
-
-#define PORTA_PIN4_GPIO 0
-#define PORTA_PIN4_FUNMUX 1
-
-#define PORTA_PIN5_GPIO 0
-#define PORTA_PIN5_FUNMUX 1
-
-#define PORTA_PIN6_GPIO 0
-#define PORTA_PIN6_FUNMUX 1
-
-#define PORTA_PIN7_GPIO 0
-#define PORTA_PIN7_FUNMUX 1
-
-#define PORTA_PIN8_GPIO 0
-#define PORTA_PIN8_FUNMUX 1
-
-#define PORTA_PIN9_GPIO 0
-#define PORTA_PIN9_FUNMUX 1
-#define PORTA_PIN9_ADC0_IN7 3
-
-#define PORTA_PIN10_GPIO 0
-#define PORTA_PIN10_FUNMUX 1
-#define PORTA_PIN10_ADC0_IN6 3
-
-#define PORTA_PIN11_GPIO 0
-#define PORTA_PIN11_FUNMUX 1
-#define PORTA_PIN11_ADC0_IN5 3
-
-#define PORTA_PIN12_GPIO 0
-#define PORTA_PIN12_ADC0_IN4 3
-
-#define PORTB_PIN0_GPIO 0
-#define PORTB_PIN0_FUNMUX 1
-#define PORTB_PIN0_SD_DETECT 2
-
-#define PORTB_PIN1_GPIO 0
-#define PORTB_PIN1_FUNMUX 1
-#define PORTB_PIN1_SD_CLK 2
-
-#define PORTB_PIN2_GPIO 0
-#define PORTB_PIN2_FUNMUX 1
-#define PORTB_PIN2_SD_CMD 2
-
-#define PORTB_PIN3_GPIO 0
-#define PORTB_PIN3_FUNMUX 1
-#define PORTB_PIN3_SD_D0 2
-
-#define PORTB_PIN4_GPIO 0
-#define PORTB_PIN4_FUNMUX 1
-#define PORTB_PIN4_SD_D1 2
-
-#define PORTB_PIN5_GPIO 0
-#define PORTB_PIN5_FUNMUX 1
-#define PORTB_PIN5_SD_D2 2
-
-#define PORTB_PIN6_GPIO 0
-#define PORTB_PIN6_FUNMUX 1
-#define PORTB_PIN6_SD_D3 2
-
-#define PORTB_PIN7_GPIO 0
-#define PORTB_PIN7_FUNMUX 1
-#define PORTB_PIN7_SD_D4 2
-
-#define PORTB_PIN8_GPIO 0
-#define PORTB_PIN8_FUNMUX 1
-#define PORTB_PIN8_SD_D5 2
-
-#define PORTB_PIN9_GPIO 0
-#define PORTB_PIN9_FUNMUX 1
-#define PORTB_PIN9_SD_D6 2
-
-#define PORTB_PIN10_GPIO 0
-#define PORTB_PIN10_FUNMUX 1
-#define PORTB_PIN10_SD_D7 2
-
-#define PORTB_PIN11_GPIO 0
-#define PORTB_PIN11_FUNMUX 1
-
-#define PORTB_PIN12_GPIO 0
-
-#define PORTC_PIN0_GPIO 0
-#define PORTC_PIN0_FUNMUX 1
-
-#define PORTC_PIN1_GPIO 0
-#define PORTC_PIN1_FUNMUX 1
-
-#define PORTC_PIN2_GPIO 0
-#define PORTC_PIN2_FUNMUX 1
-
-#define PORTC_PIN3_GPIO 0
-#define PORTC_PIN3_FUNMUX 1
-
-#define PORTC_PIN4_GPIO 0
-#define PORTC_PIN4_FUNMUX 1
-#define PORTC_PIN4_ADC1_IN3 3
-
-#define PORTC_PIN5_GPIO 0
-#define PORTC_PIN5_FUNMUX 1
-#define PORTC_PIN5_ADC1_IN2 3
-
-#define PORTC_PIN6_GPIO 0
-#define PORTC_PIN6_FUNMUX 1
-#define PORTC_PIN6_ADC1_IN1 3
-
-#define PORTC_PIN7_GPIO 0
-#define PORTC_PIN7_FUNMUX 1
-#define PORTC_PIN7_ADC1_IN0 3
-
-#define PORTM_PIN0_GPIO 0
-#define PORTM_PIN0_FUNMUX 1
-#define PORTM_PIN0_NORFL_D15 2
-
-#define PORTM_PIN1_GPIO 0
-#define PORTM_PIN1_FUNMUX 1
-#define PORTM_PIN1_NORFL_D14 2
-
-#define PORTM_PIN2_GPIO 0
-#define PORTM_PIN2_FUNMUX 1
-#define PORTM_PIN2_NORFL_D13 2
-
-#define PORTM_PIN3_GPIO 0
-#define PORTM_PIN3_FUNMUX 1
-#define PORTM_PIN3_NORFL_D12 2
-
-#define PORTM_PIN4_GPIO 0
-#define PORTM_PIN4_FUNMUX 1
-#define PORTM_PIN4_NORFL_D11 2
-
-#define PORTM_PIN5_GPIO 0
-#define PORTM_PIN5_FUNMUX 1
-#define PORTM_PIN5_NORFL_D10 2
-
-#define PORTM_PIN6_GPIO 0
-#define PORTM_PIN6_FUNMUX 1
-#define PORTM_PIN6_NORFL_D9 2
-
-#define PORTM_PIN7_GPIO 0
-#define PORTM_PIN7_FUNMUX 1
-#define PORTM_PIN7_NORFL_D8 2
-
-#define PORTM_PIN8_GPIO 0
-#define PORTM_PIN8_FUNMUX 1
-#define PORTM_PIN8_NORFL_D7 2
-
-#define PORTM_PIN9_GPIO 0
-#define PORTM_PIN9_FUNMUX 1
-#define PORTM_PIN9_NORFL_D6 2
-
-#define PORTM_PIN10_GPIO 0
-#define PORTM_PIN10_FUNMUX 1
-#define PORTM_PIN10_NORFL_D5 2
-
-#define PORTM_PIN11_GPIO 0
-#define PORTM_PIN11_FUNMUX 1
-#define PORTM_PIN11_NORFL_D4 2
-
-#define PORTM_PIN12_GPIO 0
-#define PORTM_PIN12_FUNMUX 1
-#define PORTM_PIN12_NORFL_D3 2
-
-#define PORTM_PIN13_GPIO 0
-#define PORTM_PIN13_FUNMUX 1
-#define PORTM_PIN13_NORFL_D2 2
-
-#define PORTM_PIN14_GPIO 0
-#define PORTM_PIN14_FUNMUX 1
-#define PORTM_PIN14_NORFL_D1 2
-
-#define PORTM_PIN15_GPIO 0
-#define PORTM_PIN15_FUNMUX 1
-#define PORTM_PIN15_NORFL_D0 2
-
-#define PORTM_PIN16_GPIO 0
-#define PORTM_PIN16_FUNMUX 1
-#define PORTM_PIN16_NORFL_OEN 2
-
-#define PORTM_PIN17_GPIO 0
-#define PORTM_PIN17_FUNMUX 1
-#define PORTM_PIN17_NORFL_WEN 2
-
-#define PORTM_PIN18_GPIO 0
-#define PORTM_PIN18_FUNMUX 1
-#define PORTM_PIN18_NORFL_CSN 2
-
-#define PORTM_PIN19_GPIO 0
-#define PORTM_PIN19_FUNMUX 1
-#define PORTM_PIN19_SDRAM_CSN 2
-
-#define PORTM_PIN20_GPIO 0
-#define PORTM_PIN20_FUNMUX 1
-#define PORTM_PIN20_SRAM_CSN 2
-
-#define PORTM_PIN21_GPIO 0
-#define PORTM_PIN21_FUNMUX 1
-#define PORTM_PIN21_SDRAM_CKE 2
-
-#define PORTN_PIN0_GPIO 0
-#define PORTN_PIN0_FUNMUX 1
-#define PORTN_PIN0_LCD_D0 2
-#define PORTN_PIN0_ADC1_IN4 3
-
-#define PORTN_PIN1_GPIO 0
-#define PORTN_PIN1_FUNMUX 1
-#define PORTN_PIN1_LCD_D1 2
-#define PORTN_PIN1_ADC1_IN5 3
-
-#define PORTN_PIN2_GPIO 0
-#define PORTN_PIN2_FUNMUX 1
-#define PORTN_PIN2_LCD_D2 2
-#define PORTN_PIN2_ADC1_IN6 3
-
-#define PORTN_PIN3_GPIO 0
-#define PORTN_PIN3_FUNMUX 1
-#define PORTN_PIN3_LCD_D3 2
-
-#define PORTN_PIN4_GPIO 0
-#define PORTN_PIN4_FUNMUX 1
-#define PORTN_PIN4_LCD_D4 2
-
-#define PORTN_PIN5_GPIO 0
-#define PORTN_PIN5_FUNMUX 1
-#define PORTN_PIN5_LCD_D5 2
-
-#define PORTN_PIN6_GPIO 0
-#define PORTN_PIN6_FUNMUX 1
-#define PORTN_PIN6_LCD_D6 2
-
-#define PORTN_PIN7_GPIO 0
-#define PORTN_PIN7_FUNMUX 1
-#define PORTN_PIN7_LCD_D7 2
-
-#define PORTN_PIN8_GPIO 0
-#define PORTN_PIN8_FUNMUX 1
-#define PORTN_PIN8_LCD_D8 2
-
-#define PORTN_PIN9_GPIO 0
-#define PORTN_PIN9_FUNMUX 1
-#define PORTN_PIN9_LCD_D9 2
-
-#define PORTN_PIN10_GPIO 0
-#define PORTN_PIN10_FUNMUX 1
-#define PORTN_PIN10_LCD_D10 2
-
-#define PORTN_PIN11_GPIO 0
-#define PORTN_PIN11_FUNMUX 1
-#define PORTN_PIN11_LCD_D11 2
-
-#define PORTN_PIN12_GPIO 0
-#define PORTN_PIN12_FUNMUX 1
-#define PORTN_PIN12_LCD_D12 2
-
-#define PORTN_PIN13_GPIO 0
-#define PORTN_PIN13_FUNMUX 1
-#define PORTN_PIN13_LCD_D13 2
-
-#define PORTN_PIN14_GPIO 0
-#define PORTN_PIN14_FUNMUX 1
-#define PORTN_PIN14_LCD_D14 2
-
-#define PORTN_PIN15_GPIO 0
-#define PORTN_PIN15_FUNMUX 1
-#define PORTN_PIN15_LCD_D15 2
-
-#define PORTN_PIN16_GPIO 0
-#define PORTN_PIN16_FUNMUX 1
-#define PORTN_PIN16_LCD_RD 2
-#define PORTN_PIN16_LCD_DOTCK 2
-
-#define PORTN_PIN17_GPIO 0
-#define PORTN_PIN17_FUNMUX 1
-#define PORTN_PIN17_LCD_CS 2
-#define PORTN_PIN17_LCD_VSYNC 2
-
-#define PORTN_PIN18_GPIO 0
-#define PORTN_PIN18_LCD_RS 2
-#define PORTN_PIN18_LCD_DATEN 2 //Data Enable
-
-#define PORTN_PIN19_GPIO 0
-#define PORTN_PIN19_LCD_WR 2
-#define PORTN_PIN19_LCD_HSYNC 2
-
-#define PORTP_PIN0_GPIO 0
-#define PORTP_PIN0_FUNMUX 1
-#define PORTP_PIN0_NORFL_A0 2
-
-#define PORTP_PIN1_GPIO 0
-#define PORTP_PIN1_FUNMUX 1
-#define PORTP_PIN1_NORFL_A1 2
-
-#define PORTP_PIN2_GPIO 0
-#define PORTP_PIN2_FUNMUX 1
-#define PORTP_PIN2_NORFL_A2 2
-#define PORTP_PIN2_SD_D7 3
-
-#define PORTP_PIN3_GPIO 0
-#define PORTP_PIN3_FUNMUX 1
-#define PORTP_PIN3_NORFL_A3 2
-#define PORTP_PIN3_SD_D6 3
-
-#define PORTP_PIN4_GPIO 0
-#define PORTP_PIN4_FUNMUX 1
-#define PORTP_PIN4_NORFL_A4 2
-#define PORTP_PIN4_SD_D5 3
-
-#define PORTP_PIN5_GPIO 0
-#define PORTP_PIN5_FUNMUX 1
-#define PORTP_PIN5_NORFL_A5 2
-#define PORTP_PIN5_SD_D4 3
-
-#define PORTP_PIN6_GPIO 0
-#define PORTP_PIN6_FUNMUX 1
-#define PORTP_PIN6_NORFL_A6 2
-#define PORTP_PIN6_SD_D3 3
-
-#define PORTP_PIN7_GPIO 0
-#define PORTP_PIN7_FUNMUX 1
-#define PORTP_PIN7_NORFL_A7 2
-#define PORTP_PIN7_SD_D2 3
-
-#define PORTP_PIN8_GPIO 0
-#define PORTP_PIN8_FUNMUX 1
-#define PORTP_PIN8_NORFL_A8 2
-#define PORTP_PIN8_SD_D1 3
-
-#define PORTP_PIN9_GPIO 0
-#define PORTP_PIN9_FUNMUX 1
-#define PORTP_PIN9_NORFL_A9 2
-#define PORTP_PIN9_SD_D0 3
-
-#define PORTP_PIN10_GPIO 0
-#define PORTP_PIN10_FUNMUX 1
-#define PORTP_PIN10_NORFL_A10 2
-#define PORTP_PIN10_SD_CMD 3
-
-#define PORTP_PIN11_GPIO 0
-#define PORTP_PIN11_FUNMUX 1
-#define PORTP_PIN11_NORFL_A11 2
-#define PORTP_PIN11_SD_CLK 3
-
-#define PORTP_PIN12_GPIO 0
-#define PORTP_PIN12_FUNMUX 1
-#define PORTP_PIN12_NORFL_A12 2
-#define PORTP_PIN12_SD_DETECT 3
-
-#define PORTP_PIN13_GPIO 0
-#define PORTP_PIN13_FUNMUX 1
-#define PORTP_PIN13_NORFL_A13 2
-#define PORTP_PIN13_SDRAM_CLK 2
-
-#define PORTP_PIN14_GPIO 0
-#define PORTP_PIN14_FUNMUX 1
-#define PORTP_PIN14_NORFL_A14 2
-#define PORTP_PIN14_SDRAM_CAS 2
-
-#define PORTP_PIN15_GPIO 0
-#define PORTP_PIN15_FUNMUX 1
-#define PORTP_PIN15_NORFL_A15 2
-#define PORTP_PIN15_SDRAM_RAS 2
-
-#define PORTP_PIN16_GPIO 0
-#define PORTP_PIN16_FUNMUX 1
-#define PORTP_PIN16_NORFL_A16 2
-#define PORTP_PIN16_SDRAM_LDQ 2
-
-#define PORTP_PIN17_GPIO 0
-#define PORTP_PIN17_FUNMUX 1
-#define PORTP_PIN17_NORFL_A17 2
-#define PORTP_PIN17_SDRAM_UDQ 2
-
-#define PORTP_PIN18_GPIO 0
-#define PORTP_PIN18_FUNMUX 1
-#define PORTP_PIN18_NORFL_A18 2
-
-#define PORTP_PIN19_GPIO 0
-#define PORTP_PIN19_FUNMUX 1
-#define PORTP_PIN19_NORFL_A19 2
-
-#define PORTP_PIN20_GPIO 0
-#define PORTP_PIN20_FUNMUX 1
-#define PORTP_PIN20_NORFL_A20 2
-#define PORTP_PIN20_SDRAM_BA0 2
-
-#define PORTP_PIN21_GPIO 0
-#define PORTP_PIN21_FUNMUX 1
-#define PORTP_PIN21_NORFL_A21 2
-#define PORTP_PIN21_SDRAM_BA1 2
-
-#define PORTP_PIN22_GPIO 0
-#define PORTP_PIN22_FUNMUX 1
-#define PORTP_PIN22_NORFL_A22 2
-
-#define PORTP_PIN23_GPIO 0
-#define PORTP_PIN23_FUNMUX 1
-#define PORTP_PIN23_NORFL_A23 2
-
-/* 下面宏定义的取值全部在正确值的基础上“加100”，以区分上面宏定义的值，从而方便库函数的编写*/
-/* 下面这些值是偶数编号引脚的功能取值，如PIN0、PIN2、... */
-#define FUNMUX0_UART0_RXD 100
-#define FUNMUX0_UART1_RXD 101
-#define FUNMUX0_UART2_RXD 102
-#define FUNMUX0_UART3_RXD 103
-#define FUNMUX0_I2C0_SCL 105
-#define FUNMUX0_I2C1_SCL 106
-#define FUNMUX0_PWM0A_OUT 107
-#define FUNMUX0_PWM2A_OUT 108
-#define FUNMUX0_PWM4A_OUT 109
-#define FUNMUX0_PWM0B_OUT 110
-#define FUNMUX0_PWM2B_OUT 111
-#define FUNMUX0_PWM4B_OUT 112
-#define FUNMUX0_PWM_BREAK 113
-#define FUNMUX0_TIMR0_IN 114
-#define FUNMUX0_TIMR2_IN 115
-#define FUNMUX0_CAN_RX 116
-#define FUNMUX0_SPI0_SSEL 117
-#define FUNMUX0_SPI0_MOSI 118
-#define FUNMUX0_SPI1_SSEL 119
-#define FUNMUX0_SPI1_MOSI 120
-#define FUNMUX0_UART0_CTS 121
-#define FUNMUX0_UART1_CTS 122
-#define FUNMUX0_UART2_CTS 123
-#define FUNMUX0_UART3_CTS 124
-
-/* 下面这些值是奇数编号引脚的功能取值，如PIN1、PIN3、... */
-#define FUNMUX1_UART0_TXD 100
-#define FUNMUX1_UART1_TXD 101
-#define FUNMUX1_UART2_TXD 102
-#define FUNMUX1_UART3_TXD 103
-#define FUNMUX1_I2C0_SDA 105
-#define FUNMUX1_I2C1_SDA 106
-#define FUNMUX1_PWM1A_OUT 107
-#define FUNMUX1_PWM3A_OUT 108
-#define FUNMUX1_PWM5A_OUT 109
-#define FUNMUX1_PWM1B_OUT 110
-#define FUNMUX1_PWM3B_OUT 111
-#define FUNMUX1_PWM5B_OUT 112
-#define FUNMUX1_PULSE_IN 113
-#define FUNMUX1_TIMR1_IN 114
-#define FUNMUX1_TIMR3_IN 115
-#define FUNMUX1_CAN_TX 116
-#define FUNMUX1_SPI0_SCLK 117
-#define FUNMUX1_SPI0_MISO 118
-#define FUNMUX1_SPI1_SCLK 119
-#define FUNMUX1_SPI1_MISO 120
-#define FUNMUX1_UART0_RTS 121
-#define FUNMUX1_UART1_RTS 122
-#define FUNMUX1_UART2_RTS 123
-#define FUNMUX1_UART3_RTS 124
-
-#endif //__SWM320_PORT_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_pwm.h

@@ -1,57 +0,0 @@
-#ifndef __SWM320_PWM_H__
-#define __SWM320_PWM_H__
-
-typedef struct
-{
-    uint8_t clk_div; //PWM_CLKDIV_1、PWM_CLKDIV_8
-
-    uint8_t mode; //PWM_MODE_INDEP、PWM_MODE_COMPL、PWM_MODE_INDEP_CALIGN、PWM_MODE_COMPL_CALIGN
-
-    uint16_t cycleA;    //A路周期
-    uint16_t hdutyA;    //A路占空比
-    uint16_t deadzoneA; //A路死区时长，取值0--1023
-    uint8_t initLevelA; //A路初始输出电平，0 低电平    1 高电平
-
-    uint16_t cycleB;    //B路周期
-    uint16_t hdutyB;    //B路占空比
-    uint16_t deadzoneB; //B路死区时长，取值0--1023
-    uint8_t initLevelB; //B路初始输出电平，0 低电平    1 高电平
-
-    uint8_t HEndAIEn;   //A路高电平结束中断使能
-    uint8_t NCycleAIEn; //A路新周期开始中断使能
-    uint8_t HEndBIEn;   //B路高电平结束中断使能
-    uint8_t NCycleBIEn; //B路新周期开始中断使能
-} PWM_InitStructure;
-
-#define PWM_CLKDIV_1 0
-#define PWM_CLKDIV_8 1
-
-#define PWM_MODE_INDEP 0        //A路和B路为两路独立输出
-#define PWM_MODE_COMPL 1        //A路和B路为一路互补输出
-#define PWM_MODE_INDEP_CALIGN 3 //A路和B路为两路独立输出，中心对齐
-#define PWM_MODE_COMPL_CALIGN 4 //A路和B路为一路互补输出，中心对齐
-
-#define PWM_CH_A 0
-#define PWM_CH_B 1
-
-void PWM_Init(PWM_TypeDef *PWMx, PWM_InitStructure *initStruct); //PWM初始化
-void PWM_Start(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB);   //启动PWM，开始PWM输出
-void PWM_Stop(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB);    //关闭PWM，停止PWM输出
-
-void PWM_SetCycle(PWM_TypeDef *PWMx, uint32_t chn, uint16_t cycle);      //设置周期
-uint16_t PWM_GetCycle(PWM_TypeDef *PWMx, uint32_t chn);                  //获取周期
-void PWM_SetHDuty(PWM_TypeDef *PWMx, uint32_t chn, uint16_t hduty);      //设置高电平时长
-uint16_t PWM_GetHDuty(PWM_TypeDef *PWMx, uint32_t chn);                  //获取高电平时长
-void PWM_SetDeadzone(PWM_TypeDef *PWMx, uint32_t chn, uint8_t deadzone); //设置死区时长
-uint8_t PWM_GetDeadzone(PWM_TypeDef *PWMx, uint32_t chn);                //获取死区时长
-
-void PWM_IntNCycleEn(PWM_TypeDef *PWMx, uint32_t chn);       //新周期开始中断使能
-void PWM_IntNCycleDis(PWM_TypeDef *PWMx, uint32_t chn);      //新周期开始中断禁能
-void PWM_IntNCycleClr(PWM_TypeDef *PWMx, uint32_t chn);      //新周期开始中断标志清除
-uint32_t PWM_IntNCycleStat(PWM_TypeDef *PWMx, uint32_t chn); //新周期开始中断是否发生
-void PWM_IntHEndEn(PWM_TypeDef *PWMx, uint32_t chn);         //高电平结束中断使能
-void PWM_IntHEndDis(PWM_TypeDef *PWMx, uint32_t chn);        //高电平结束中断禁能
-void PWM_IntHEndClr(PWM_TypeDef *PWMx, uint32_t chn);        //高电平结束中断标志清除
-uint32_t PWM_IntHEndStat(PWM_TypeDef *PWMx, uint32_t chn);   //高电平结束中断是否发生
-
-#endif //__SWM320_PWM_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h

@@ -1,73 +0,0 @@
-#ifndef __SWM320_RTC_H__
-#define __SWM320_RTC_H__
-
-#define RTC_SUN 0x01
-#define RTC_MON 0x02
-#define RTC_TUE 0x04
-#define RTC_WED 0x08
-#define RTC_THU 0x10
-#define RTC_FRI 0x20
-#define RTC_SAT 0x40
-
-typedef struct
-{
-    uint16_t Year;
-    uint8_t Month;  //取值1--12
-    uint8_t Date;   //取值1--31
-    uint8_t Hour;   //取值0--23
-    uint8_t Minute; //取值0--59
-    uint8_t Second; //取值0--59
-    uint8_t SecondIEn;
-    uint8_t MinuteIEn;
-} RTC_InitStructure;
-
-typedef struct
-{
-    uint8_t Days; //RTC_SUN、RTC_MON、RTC_TUE、RTC_WED、RTC_THU、RTC_FRI、RTC_SAT及其或运算组合
-    uint8_t Hour;
-    uint8_t Minute;
-    uint8_t Second;
-    uint8_t AlarmIEn;
-} RTC_AlarmStructure;
-
-typedef struct
-{
-    uint16_t Year;
-    uint8_t Month;
-    uint8_t Date;
-    uint8_t Day; //RTC_SUN、RTC_MON、RTC_TUE、RTC_WED、RTC_THU、RTC_FRI、RTC_SAT
-    uint8_t Hour;
-    uint8_t Minute;
-    uint8_t Second;
-} RTC_DateTime;
-
-void RTC_Init(RTC_TypeDef *RTCx, RTC_InitStructure *initStruct);
-void RTC_Start(RTC_TypeDef *RTCx);
-void RTC_Stop(RTC_TypeDef *RTCx);
-
-void RTC_GetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime);
-
-void RTC_AlarmSetup(RTC_TypeDef *RTCx, RTC_AlarmStructure *alarmStruct);
-
-void RTC_IntSecondEn(RTC_TypeDef *RTCx);
-void RTC_IntSecondDis(RTC_TypeDef *RTCx);
-void RTC_IntSecondClr(RTC_TypeDef *RTCx);
-uint32_t RTC_IntSecondStat(RTC_TypeDef *RTCx);
-void RTC_IntMinuteEn(RTC_TypeDef *RTCx);
-void RTC_IntMinuteDis(RTC_TypeDef *RTCx);
-void RTC_IntMinuteClr(RTC_TypeDef *RTCx);
-uint32_t RTC_IntMinuteStat(RTC_TypeDef *RTCx);
-void RTC_IntHourEn(RTC_TypeDef *RTCx);
-void RTC_IntHourDis(RTC_TypeDef *RTCx);
-void RTC_IntHourClr(RTC_TypeDef *RTCx);
-uint32_t RTC_IntHourStat(RTC_TypeDef *RTCx);
-void RTC_IntDateEn(RTC_TypeDef *RTCx);
-void RTC_IntDateDis(RTC_TypeDef *RTCx);
-void RTC_IntDateClr(RTC_TypeDef *RTCx);
-uint32_t RTC_IntDateStat(RTC_TypeDef *RTCx);
-void RTC_IntAlarmEn(RTC_TypeDef *RTCx);
-void RTC_IntAlarmDis(RTC_TypeDef *RTCx);
-void RTC_IntAlarmClr(RTC_TypeDef *RTCx);
-uint32_t RTC_IntAlarmStat(RTC_TypeDef *RTCx);
-
-#endif //__SWM320_RTC_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h

@@ -1,141 +0,0 @@
-#ifndef __SWM320_SDIO_H__
-#define __SWM320_SDIO_H__
-
-#define SD_CMD_GO_IDLE_STATE ((uint8_t)0)
-#define SD_CMD_SEND_OP_COND ((uint8_t)1)
-#define SD_CMD_ALL_SEND_CID ((uint8_t)2)
-#define SD_CMD_SET_REL_ADDR ((uint8_t)3)
-#define SD_CMD_SET_DSR ((uint8_t)4)
-#define SD_CMD_HS_SWITCH ((uint8_t)6)
-#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7)
-#define SD_CMD_SEND_IF_COND ((uint8_t)8)
-#define SD_CMD_SEND_CSD ((uint8_t)9)
-#define SD_CMD_SEND_CID ((uint8_t)10)
-#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12)
-#define SD_CMD_SEND_STATUS ((uint8_t)13)
-#define SD_CMD_SET_BLOCKLEN ((uint8_t)16)
-#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17)
-#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18)
-#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24)
-#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25)
-#define SD_CMD_PROG_CID ((uint8_t)26)
-#define SD_CMD_PROG_CSD ((uint8_t)27)
-#define SD_CMD_APP_CMD ((uint8_t)55)
-
-/*Following commands are SD Card Specific commands.
-  SDIO_APP_CMD should be sent before sending these commands. */
-#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6)
-#define SD_CMD_SD_APP_STAUS ((uint8_t)13)
-#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22)
-#define SD_CMD_SD_APP_OP_COND ((uint8_t)41)
-#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42)
-#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51)
-#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52)
-#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53)
-
-#define SD_RESP_NO 0       //0 无响应
-#define SD_RESP_32b 2      //2 32位响应
-#define SD_RESP_128b 1     //1 128位响应
-#define SD_RESP_32b_busy 3 //3 32位响应，check Busy after response
-
-#define SD_BUSWIDTH_1b 0
-#define SD_BUSWIDTH_4b 2
-
-#define SD_RES_OK 0
-#define SD_RES_ERR 1
-#define SD_RES_TIMEOUT 2
-
-typedef struct
-{
-    __IO uint8_t CSDStruct;           // CSD structure
-    __IO uint8_t SysSpecVersion;      // System specification version
-    __IO uint8_t Reserved1;           // Reserved
-    __IO uint8_t TAAC;                // Data read access-time 1
-    __IO uint8_t NSAC;                // Data read access-time 2 in CLK cycles
-    __IO uint8_t MaxBusClkFrec;       // Max. bus clock frequency
-    __IO uint16_t CardComdClasses;    //< Card command classes
-    __IO uint8_t RdBlockLen;          // Max. read data block length
-    __IO uint8_t PartBlockRead;       // Partial blocks for read allowed
-    __IO uint8_t WrBlockMisalign;     // Write block misalignment
-    __IO uint8_t RdBlockMisalign;     // Read block misalignment
-    __IO uint8_t DSRImpl;             // DSR implemented
-    __IO uint8_t Reserved2;           // Reserved
-    __IO uint32_t DeviceSize;         // Device Size
-    __IO uint8_t MaxRdCurrentVDDMin;  // Max. read current @ VDD min
-    __IO uint8_t MaxRdCurrentVDDMax;  // Max. read current @ VDD max
-    __IO uint8_t MaxWrCurrentVDDMin;  // Max. write current @ VDD min
-    __IO uint8_t MaxWrCurrentVDDMax;  // Max. write current @ VDD max
-    __IO uint8_t DeviceSizeMul;       // Device size multiplier
-    __IO uint8_t EraseGrSize;         // Erase group size
-    __IO uint8_t EraseGrMul;          // Erase group size multiplier
-    __IO uint8_t WrProtectGrSize;     // Write protect group size
-    __IO uint8_t WrProtectGrEnable;   // Write protect group enable
-    __IO uint8_t ManDeflECC;          // Manufacturer default ECC
-    __IO uint8_t WrSpeedFact;         // Write speed factor
-    __IO uint8_t MaxWrBlockLen;       // Max. write data block length
-    __IO uint8_t WriteBlockPaPartial; // Partial blocks for write allowed
-    __IO uint8_t Reserved3;           // Reserded
-    __IO uint8_t ContentProtectAppli; // Content protection application
-    __IO uint8_t FileFormatGrouop;    // File format group
-    __IO uint8_t CopyFlag;            // Copy flag (OTP)
-    __IO uint8_t PermWrProtect;       // Permanent write protection
-    __IO uint8_t TempWrProtect;       // Temporary write protection
-    __IO uint8_t FileFormat;          // File Format
-    __IO uint8_t ECC;                 // ECC code
-} SD_CSD;
-
-typedef struct
-{
-    __IO uint8_t ManufacturerID; // ManufacturerID
-    __IO uint16_t OEM_AppliID;   // OEM/Application ID
-    __IO uint32_t ProdName1;     // Product Name part1
-    __IO uint8_t ProdName2;      // Product Name part2
-    __IO uint8_t ProdRev;        // Product Revision
-    __IO uint32_t ProdSN;        // Product Serial Number
-    __IO uint8_t Reserved1;      // Reserved1
-    __IO uint16_t ManufactDate;  // Manufacturing Date
-} SD_CID;
-
-#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)
-#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)
-#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)
-#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003)
-#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)
-#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)
-#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)
-#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)
-
-typedef struct
-{
-    SD_CSD SD_csd;
-    SD_CID SD_cid;
-    uint64_t CardCapacity;  // Card Capacity
-    uint32_t CardBlockSize; // Card Block Size
-    uint16_t RCA;
-    uint8_t CardType;
-} SD_CardInfo;
-
-extern SD_CardInfo SD_cardInfo;
-
-uint32_t SDIO_Init(uint32_t freq);
-uint32_t SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[]);
-uint32_t SDIO_BlockRead(uint32_t block_addr, uint32_t buff[]);
-
-uint32_t SDIO_MultiBlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]);
-uint32_t SDIO_MultiBlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]);
-
-uint32_t SDIO_DMABlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]);
-uint32_t SDIO_DMABlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]);
-
-uint32_t _SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read, uint16_t block_cnt, uint32_t use_dma);
-
-#define SDIO_SendCmd(cmd, arg, resp_type, resp_data) _SDIO_SendCmd(cmd, arg, resp_type, resp_data, 0, 0, 0, 0)
-#define SDIO_SendCmdWithData(cmd, arg, resp_type, resp_data, data_read, block_cnt) _SDIO_SendCmd(cmd, arg, resp_type, resp_data, 1, data_read, block_cnt, 0)
-#define SDIO_SendCmdWithDataByDMA(cmd, arg, resp_type, resp_data, data_read, block_cnt) _SDIO_SendCmd(cmd, arg, resp_type, resp_data, 1, data_read, block_cnt, 1)
-
-void parseCID(uint32_t CID_Tab[4]);
-void parseCSD(uint32_t CID_Tab[4]);
-
-uint32_t calcSDCLKDiv(uint32_t freq_sel);
-
-#endif //__SWM320_SDIO_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h

@@ -1,81 +0,0 @@
-#ifndef __SWM320_SDRAM_H__
-#define __SWM320_SDRAM_H__
-
-typedef struct
-{
-    uint8_t CellSize;   // SDRAM颗粒的容量，SDRAM_CELLSIZE_16Mb、SDRAM_CELLSIZE_64Mb、SDRAM_CELLSIZE_128Mb、SDRAM_CELLSIZE_256Mb
-    uint8_t CellBank;   // SDRAM颗粒有几个bank，SDRAM_CELLBANK_2、SDRAM_CELLBANK_4
-    uint8_t CellWidth;  // SDRAM颗粒的位宽，SDRAM_CELLWIDTH_16、SDRAM_CELLWIDTH_32
-    uint8_t CASLatency; // 列地址到有效数据输出间隔，SDRAM_CASLATENCY_2、SDRAM_CASLATENCY_3
-
-    uint8_t TimeTMRD; // MRS to New Command
-    uint8_t TimeTRRD; // Activate to activate on different banks
-    uint8_t TimeTRAS; // Self refresh time，最小Self-refresh周期
-    uint8_t TimeTRC;  // Row cycle delay，Refresh命令到Activate命令间延时，也是两个连续Refresh命令间延时
-    uint8_t TimeTRCD; // Row to column delay，行地址到列地址间延时，也即Activate命令到读写命令间延时
-    uint8_t TimeTRP;  // Row precharge delay，Precharge命令到另一个命令间延时
-} SDRAM_InitStructure;
-
-#define SDRAM_CELLSIZE_16Mb 3
-#define SDRAM_CELLSIZE_64Mb 0
-#define SDRAM_CELLSIZE_128Mb 1
-#define SDRAM_CELLSIZE_256Mb 2
-
-#define SDRAM_CELLBANK_2 0
-#define SDRAM_CELLBANK_4 1
-
-#define SDRAM_CELLWIDTH_16 0
-#define SDRAM_CELLWIDTH_32 1
-
-#define SDRAM_CASLATENCY_2 2
-#define SDRAM_CASLATENCY_3 3
-
-#define SDRAM_TMRD_3 3
-#define SDRAM_TMRD_4 4
-#define SDRAM_TMRD_5 5
-#define SDRAM_TMRD_6 6
-#define SDRAM_TMRD_7 7
-
-#define SDRAM_TRRD_2 2
-#define SDRAM_TRRD_3 3
-
-#define SDRAM_TRAS_2 2
-#define SDRAM_TRAS_3 3
-#define SDRAM_TRAS_4 4
-#define SDRAM_TRAS_5 5
-#define SDRAM_TRAS_6 6
-#define SDRAM_TRAS_7 7
-
-#define SDRAM_TRC_2 2
-#define SDRAM_TRC_3 3
-#define SDRAM_TRC_4 4
-#define SDRAM_TRC_5 5
-#define SDRAM_TRC_6 6
-#define SDRAM_TRC_7 7
-#define SDRAM_TRC_8 8
-#define SDRAM_TRC_9 9
-#define SDRAM_TRC_10 10
-#define SDRAM_TRC_11 11
-#define SDRAM_TRC_12 12
-#define SDRAM_TRC_13 13
-#define SDRAM_TRC_14 14
-#define SDRAM_TRC_15 15
-
-#define SDRAM_TRCD_3 3
-#define SDRAM_TRCD_4 4
-#define SDRAM_TRCD_5 5
-#define SDRAM_TRCD_6 6
-#define SDRAM_TRCD_7 7
-
-#define SDRAM_TRP_3 3
-#define SDRAM_TRP_4 4
-#define SDRAM_TRP_5 5
-#define SDRAM_TRP_6 6
-#define SDRAM_TRP_7 7
-
-void SDRAM_Init(SDRAM_InitStructure *initStruct);
-
-void SDRAM_Enable(void);
-void SDRAM_Disable(void);
-
-#endif //__SWM320_SDRAM_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_spi.h

@@ -1,80 +0,0 @@
-#ifndef __SWM320_SPI_H__
-#define __SWM320_SPI_H__
-
-typedef struct
-{
-    uint8_t FrameFormat; //帧格式：SPI_FORMAT_SPI、SPI_FORMAT_TI_SSI
-    uint8_t SampleEdge;  //在SPI帧格式下，选择数据采样边沿：SPI_FIRST_EDGE、SPI_SECOND_EDGE
-    uint8_t IdleLevel;   //在SPI帧格式下，选择空闲时（无数据传输时）时钟线的电平：SPI_LOW_LEVEL、SPI_HIGH_LEVEL
-    uint8_t WordSize;    //字长度, 有效值4-16
-    uint8_t Master;      //1 主机模式    0 从机模式
-    uint8_t clkDiv;      //SPI_CLK = SYS_CLK / clkDiv，有效值：SPI_CLKDIV_4、SPI_CLKDIV_8、... ... 、SPI_CLKDIV_512
-
-    uint8_t RXHFullIEn;    //接收FIFO半满中断使能
-    uint8_t TXEmptyIEn;    //发送FIFO  空中断使能
-    uint8_t TXCompleteIEn; //发送FIFO  空且发送移位寄存器空中断使能
-} SPI_InitStructure;
-
-#define SPI_FORMAT_SPI 0    //Motorola SPI 格式
-#define SPI_FORMAT_TI_SSI 1 //TI SSI 格式
-
-#define SPI_FIRST_EDGE 0  //第一个时钟沿开始采样
-#define SPI_SECOND_EDGE 1 //第二个时钟沿开始采样
-
-#define SPI_LOW_LEVEL 0  //空闲时时钟线保持低电平
-#define SPI_HIGH_LEVEL 1 //空闲时时钟线保持高电平
-
-#define SPI_CLKDIV_4 0
-#define SPI_CLKDIV_8 1
-#define SPI_CLKDIV_16 2
-#define SPI_CLKDIV_32 3
-#define SPI_CLKDIV_64 4
-#define SPI_CLKDIV_128 5
-#define SPI_CLKDIV_256 6
-#define SPI_CLKDIV_512 7
-
-void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct); //SPI初始化
-void SPI_Open(SPI_TypeDef *SPIx);                                //SPI打开，允许收发
-void SPI_Close(SPI_TypeDef *SPIx);                               //SPI关闭，禁止收发
-
-uint32_t SPI_Read(SPI_TypeDef *SPIx);
-void SPI_Write(SPI_TypeDef *SPIx, uint32_t data);
-void SPI_WriteWithWait(SPI_TypeDef *SPIx, uint32_t data);
-uint32_t SPI_ReadWrite(SPI_TypeDef *SPIx, uint32_t data);
-
-uint32_t SPI_IsRXEmpty(SPI_TypeDef *SPIx); //接收FIFO是否空，如果不空则可以继续SPI_Read()
-uint32_t SPI_IsTXFull(SPI_TypeDef *SPIx);  //发送FIFO是否满，如果不满则可以继续SPI_Write()
-uint32_t SPI_IsTXEmpty(SPI_TypeDef *SPIx); //发送FIFO是否空
-
-void SPI_INTRXHalfFullEn(SPI_TypeDef *SPIx);
-void SPI_INTRXHalfFullDis(SPI_TypeDef *SPIx);
-void SPI_INTRXHalfFullClr(SPI_TypeDef *SPIx);
-uint32_t SPI_INTRXHalfFullStat(SPI_TypeDef *SPIx);
-void SPI_INTRXFullEn(SPI_TypeDef *SPIx);
-void SPI_INTRXFullDis(SPI_TypeDef *SPIx);
-void SPI_INTRXFullClr(SPI_TypeDef *SPIx);
-uint32_t SPI_INTRXFullStat(SPI_TypeDef *SPIx);
-void SPI_INTRXOverflowEn(SPI_TypeDef *SPIx);
-void SPI_INTRXOverflowDis(SPI_TypeDef *SPIx);
-void SPI_INTRXOverflowClr(SPI_TypeDef *SPIx);
-uint32_t SPI_INTRXOverflowStat(SPI_TypeDef *SPIx);
-
-void SPI_INTTXHalfFullEn(SPI_TypeDef *SPIx);
-void SPI_INTTXHalfFullDis(SPI_TypeDef *SPIx);
-void SPI_INTTXHalfFullClr(SPI_TypeDef *SPIx);
-uint32_t SPI_INTTXHalfFullStat(SPI_TypeDef *SPIx);
-void SPI_INTTXEmptyEn(SPI_TypeDef *SPIx);
-void SPI_INTTXEmptyDis(SPI_TypeDef *SPIx);
-void SPI_INTTXEmptyClr(SPI_TypeDef *SPIx);
-uint32_t SPI_INTTXEmptyStat(SPI_TypeDef *SPIx);
-void SPI_INTTXCompleteEn(SPI_TypeDef *SPIx);
-void SPI_INTTXCompleteDis(SPI_TypeDef *SPIx);
-void SPI_INTTXCompleteClr(SPI_TypeDef *SPIx);
-uint32_t SPI_INTTXCompleteStat(SPI_TypeDef *SPIx);
-
-void SPI_INTTXWordCompleteEn(SPI_TypeDef *SPIx);
-void SPI_INTTXWordCompleteDis(SPI_TypeDef *SPIx);
-void SPI_INTTXWordCompleteClr(SPI_TypeDef *SPIx);
-uint32_t SPI_INTTXWordCompleteStat(SPI_TypeDef *SPIx);
-
-#endif //__SWM320_SPI_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_sram.h

@@ -1,29 +0,0 @@
-#ifndef __SWM320_SRAM_H__
-#define __SWM320_SRAM_H__
-
-typedef struct
-{
-    uint8_t ClkDiv;    //SRAM_CLKDIV_5...SRAM_CLKDIV_16，根据SRAM芯片所能跑的最高频率选择合适分频
-    uint8_t DataWidth; //SRAM_DATAWIDTH_8、SRAM_DATAWIDTH_16
-} SRAM_InitStructure;
-
-#define SRAM_CLKDIV_4 3
-#define SRAM_CLKDIV_5 4
-#define SRAM_CLKDIV_6 5
-#define SRAM_CLKDIV_7 6
-#define SRAM_CLKDIV_8 7
-#define SRAM_CLKDIV_9 8
-#define SRAM_CLKDIV_10 9
-#define SRAM_CLKDIV_11 10
-#define SRAM_CLKDIV_12 11
-#define SRAM_CLKDIV_13 12
-#define SRAM_CLKDIV_14 13
-#define SRAM_CLKDIV_15 14
-#define SRAM_CLKDIV_16 15
-
-#define SRAM_DATAWIDTH_8 1
-#define SRAM_DATAWIDTH_16 0
-
-void SRAM_Init(SRAM_InitStructure *initStruct);
-
-#endif //__SWM320_SRAM_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_timr.h

@@ -1,29 +0,0 @@
-#ifndef __SWM320_TIMR_H__
-#define __SWM320_TIMR_H__
-
-#define TIMR_MODE_TIMER 0
-#define TIMR_MODE_COUNTER 1
-
-void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int_en); //定时器/计数器初始化
-void TIMR_Start(TIMR_TypeDef *TIMRx);                                                 //启动定时器，从初始值开始计时/计数
-void TIMR_Stop(TIMR_TypeDef *TIMRx);                                                  //停止定时器
-void TIMR_Halt(TIMR_TypeDef *TIMRx);                                                  //暂停定时器，计数值保持不变
-void TIMR_Resume(TIMR_TypeDef *TIMRx);                                                //恢复定时器，从暂停处继续计数
-
-void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period); //设置定时/计数周期
-uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx);              //获取定时/计数周期
-uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx);            //获取当前计数值
-
-void TIMR_INTEn(TIMR_TypeDef *TIMRx);       //使能中断
-void TIMR_INTDis(TIMR_TypeDef *TIMRx);      //禁能中断
-void TIMR_INTClr(TIMR_TypeDef *TIMRx);      //清除中断标志
-uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx); //获取中断状态
-
-#define PULSE_LOW 0
-#define PULSE_HIGH 1
-
-void Pulse_Init(uint32_t pulse, uint32_t int_en);
-void Pulse_Start(void);
-uint32_t Pulse_Done(void);
-
-#endif //__SWM320_TIMR_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_uart.h

@@ -1,90 +0,0 @@
-#ifndef __SWM320_UART_H__
-#define __SWM320_UART_H__
-
-typedef struct
-{
-    uint32_t Baudrate;
-
-    uint8_t DataBits; //数据位位数，可取值UART_DATA_8BIT、UART_DATA_9BIT
-
-    uint8_t Parity; //奇偶校验位，可取值UART_PARITY_NONE、UART_PARITY_ODD、UART_PARITY_EVEN、UART_PARITY_ONE、UART_PARITY_ZERO
-
-    uint8_t StopBits; //停止位位数，可取值UART_STOP_1BIT、UART_STOP_2BIT
-
-    uint8_t RXThreshold;    //取值0--7
-    uint8_t RXThresholdIEn; //当RX FIFO中数据个数 >  RXThreshold时触发中断
-
-    uint8_t TXThreshold;    //取值0--7
-    uint8_t TXThresholdIEn; //当TX FIFO中数据个数 <= TXThreshold时触发中断
-
-    uint8_t TimeoutTime; //超时时长 = TimeoutTime/(Baudrate/10) 秒
-    uint8_t TimeoutIEn;  //超时中断，RX FIFO非空，且超过 TimeoutTime/(Baudrate/10) 秒没有在RX线上接收到数据时触发中断
-} UART_InitStructure;
-
-#define UART_DATA_8BIT 0
-#define UART_DATA_9BIT 1
-
-#define UART_PARITY_NONE 0
-#define UART_PARITY_ODD 1
-#define UART_PARITY_EVEN 3
-#define UART_PARITY_ONE 5
-#define UART_PARITY_ZERO 7
-
-#define UART_STOP_1BIT 0
-#define UART_STOP_2BIT 1
-
-#define UART_RTS_1BYTE 0
-#define UART_RTS_2BYTE 1
-#define UART_RTS_4BYTE 2
-#define UART_RTS_6BYTE 3
-
-#define UART_ABR_RES_OK 1
-#define UART_ABR_RES_ERR 2
-
-#define UART_ERR_FRAME 1
-#define UART_ERR_PARITY 2
-#define UART_ERR_NOISE 3
-
-void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct); //UART串口初始化
-void UART_Open(UART_TypeDef *UARTx);
-void UART_Close(UART_TypeDef *UARTx);
-
-void UART_WriteByte(UART_TypeDef *UARTx, uint32_t data);     //发送一个字节数据
-uint32_t UART_ReadByte(UART_TypeDef *UARTx, uint32_t *data); //读取一个字节数据，并指出数据是否Valid
-
-uint32_t UART_IsTXBusy(UART_TypeDef *UARTx);
-uint32_t UART_IsRXFIFOEmpty(UART_TypeDef *UARTx); //接收FIFO是否空，如果不空则可以继续UART_ReadByte()
-uint32_t UART_IsTXFIFOFull(UART_TypeDef *UARTx);  //发送FIFO是否满，如果不满则可以继续UART_WriteByte()
-
-void UART_SetBaudrate(UART_TypeDef *UARTx, uint32_t baudrate); //设置波特率
-uint32_t UART_GetBaudrate(UART_TypeDef *UARTx);                //获取当前使用的波特率
-
-void UART_CTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity);
-uint32_t UART_CTSLineState(UART_TypeDef *UARTx);
-
-void UART_RTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity, uint32_t threshold);
-uint32_t UART_RTSLineState(UART_TypeDef *UARTx);
-
-void UART_LINConfig(UART_TypeDef *UARTx, uint32_t detectedIEn, uint32_t generatedIEn);
-void UART_LINGenerate(UART_TypeDef *UARTx);
-uint32_t UART_LINIsDetected(UART_TypeDef *UARTx);
-uint32_t UART_LINIsGenerated(UART_TypeDef *UARTx);
-
-void UART_ABRStart(UART_TypeDef *UARTx, uint32_t detectChar);
-uint32_t UART_ABRIsDone(UART_TypeDef *UARTx);
-
-void UART_INTRXThresholdEn(UART_TypeDef *UARTx);
-void UART_INTRXThresholdDis(UART_TypeDef *UARTx);
-uint32_t UART_INTRXThresholdStat(UART_TypeDef *UARTx);
-void UART_INTTXThresholdEn(UART_TypeDef *UARTx);
-void UART_INTTXThresholdDis(UART_TypeDef *UARTx);
-uint32_t UART_INTTXThresholdStat(UART_TypeDef *UARTx);
-void UART_INTTimeoutEn(UART_TypeDef *UARTx);
-void UART_INTTimeoutDis(UART_TypeDef *UARTx);
-uint32_t UART_INTTimeoutStat(UART_TypeDef *UARTx);
-
-void UART_INTTXDoneEn(UART_TypeDef *UARTx);
-void UART_INTTXDoneDis(UART_TypeDef *UARTx);
-uint32_t UART_INTTXDoneStat(UART_TypeDef *UARTx);
-
-#endif //__SWM320_UART_H__

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h

@@ -1,18 +0,0 @@
-#ifndef __SWM320_WDT_H__
-#define __SWM320_WDT_H__
-
-#define WDT_MODE_RESET 0
-#define WDT_MODE_INTERRUPT 1
-
-void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode); //WDT看门狗初始化
-void WDT_Start(WDT_TypeDef *WDTx);                                //启动指定WDT，开始倒计时
-void WDT_Stop(WDT_TypeDef *WDTx);                                 //关闭指定WDT，停止倒计时
-
-void WDT_Feed(WDT_TypeDef *WDTx); //喂狗，重新从装载值开始倒计时
-
-int32_t WDT_GetValue(WDT_TypeDef *WDTx); //获取指定看门狗定时器的当前倒计时值
-
-void WDT_INTClr(WDT_TypeDef *WDTx);      //中断标志清除
-uint32_t WDT_INTStat(WDT_TypeDef *WDTx); //中断状态查询
-
-#endif //__SWM320_WDT_H__

bsp/swm320/project.uvoptx

@@ -1,185 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
-
-  <SchemaVersion>1.0</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Extensions>
-    <cExt>*.c</cExt>
-    <aExt>*.s*; *.src; *.a*</aExt>
-    <oExt>*.obj; *.o</oExt>
-    <lExt>*.lib</lExt>
-    <tExt>*.txt; *.h; *.inc</tExt>
-    <pExt>*.plm</pExt>
-    <CppX>*.cpp</CppX>
-    <nMigrate>0</nMigrate>
-  </Extensions>
-
-  <DaveTm>
-    <dwLowDateTime>0</dwLowDateTime>
-    <dwHighDateTime>0</dwHighDateTime>
-  </DaveTm>
-
-  <Target>
-    <TargetName>rtthread</TargetName>
-    <ToolsetNumber>0x4</ToolsetNumber>
-    <ToolsetName>ARM-ADS</ToolsetName>
-    <TargetOption>
-      <CLKADS>12000000</CLKADS>
-      <OPTTT>
-        <gFlags>1</gFlags>
-        <BeepAtEnd>1</BeepAtEnd>
-        <RunSim>0</RunSim>
-        <RunTarget>1</RunTarget>
-        <RunAbUc>0</RunAbUc>
-      </OPTTT>
-      <OPTHX>
-        <HexSelection>1</HexSelection>
-        <FlashByte>65535</FlashByte>
-        <HexRangeLowAddress>0</HexRangeLowAddress>
-        <HexRangeHighAddress>0</HexRangeHighAddress>
-        <HexOffset>0</HexOffset>
-      </OPTHX>
-      <OPTLEX>
-        <PageWidth>79</PageWidth>
-        <PageLength>66</PageLength>
-        <TabStop>8</TabStop>
-        <ListingPath>.\build\keil\List\</ListingPath>
-      </OPTLEX>
-      <ListingPage>
-        <CreateCListing>1</CreateCListing>
-        <CreateAListing>1</CreateAListing>
-        <CreateLListing>1</CreateLListing>
-        <CreateIListing>0</CreateIListing>
-        <AsmCond>1</AsmCond>
-        <AsmSymb>1</AsmSymb>
-        <AsmXref>0</AsmXref>
-        <CCond>1</CCond>
-        <CCode>0</CCode>
-        <CListInc>0</CListInc>
-        <CSymb>0</CSymb>
-        <LinkerCodeListing>0</LinkerCodeListing>
-      </ListingPage>
-      <OPTXL>
-        <LMap>1</LMap>
-        <LComments>1</LComments>
-        <LGenerateSymbols>1</LGenerateSymbols>
-        <LLibSym>1</LLibSym>
-        <LLines>1</LLines>
-        <LLocSym>1</LLocSym>
-        <LPubSym>1</LPubSym>
-        <LXref>0</LXref>
-        <LExpSel>0</LExpSel>
-      </OPTXL>
-      <OPTFL>
-        <tvExp>1</tvExp>
-        <tvExpOptDlg>0</tvExpOptDlg>
-        <IsCurrentTarget>1</IsCurrentTarget>
-      </OPTFL>
-      <CpuCode>255</CpuCode>
-      <DebugOpt>
-        <uSim>0</uSim>
-        <uTrg>1</uTrg>
-        <sLdApp>1</sLdApp>
-        <sGomain>1</sGomain>
-        <sRbreak>1</sRbreak>
-        <sRwatch>1</sRwatch>
-        <sRmem>1</sRmem>
-        <sRfunc>1</sRfunc>
-        <sRbox>1</sRbox>
-        <tLdApp>1</tLdApp>
-        <tGomain>1</tGomain>
-        <tRbreak>1</tRbreak>
-        <tRwatch>1</tRwatch>
-        <tRmem>1</tRmem>
-        <tRfunc>0</tRfunc>
-        <tRbox>1</tRbox>
-        <tRtrace>1</tRtrace>
-        <sRSysVw>1</sRSysVw>
-        <tRSysVw>1</tRSysVw>
-        <sRunDeb>0</sRunDeb>
-        <sLrtime>0</sLrtime>
-        <bEvRecOn>1</bEvRecOn>
-        <bSchkAxf>0</bSchkAxf>
-        <bTchkAxf>0</bTchkAxf>
-        <nTsel>4</nTsel>
-        <sDll></sDll>
-        <sDllPa></sDllPa>
-        <sDlgDll></sDlgDll>
-        <sDlgPa></sDlgPa>
-        <sIfile></sIfile>
-        <tDll></tDll>
-        <tDllPa></tDllPa>
-        <tDlgDll></tDlgDll>
-        <tDlgPa></tDlgPa>
-        <tIfile></tIfile>
-        <pMon>Segger\JL2CM3.dll</pMon>
-      </DebugOpt>
-      <TargetDriverDllRegistry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>UL2CM3</Key>
-          <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0SWM320xE -FL080000 -FS00 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM)</Name>
-        </SetRegEntry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>JL2CM3</Key>
-          <Name>-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN1 -FF0SWM320xE -FS00 -FL080000 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM)</Name>
-        </SetRegEntry>
-      </TargetDriverDllRegistry>
-      <Breakpoint/>
-      <Tracepoint>
-        <THDelay>0</THDelay>
-      </Tracepoint>
-      <DebugFlag>
-        <trace>0</trace>
-        <periodic>0</periodic>
-        <aLwin>0</aLwin>
-        <aCover>0</aCover>
-        <aSer1>0</aSer1>
-        <aSer2>0</aSer2>
-        <aPa>0</aPa>
-        <viewmode>0</viewmode>
-        <vrSel>0</vrSel>
-        <aSym>0</aSym>
-        <aTbox>0</aTbox>
-        <AscS1>0</AscS1>
-        <AscS2>0</AscS2>
-        <AscS3>0</AscS3>
-        <aSer3>0</aSer3>
-        <eProf>0</eProf>
-        <aLa>0</aLa>
-        <aPa1>0</aPa1>
-        <AscS4>0</AscS4>
-        <aSer4>0</aSer4>
-        <StkLoc>0</StkLoc>
-        <TrcWin>0</TrcWin>
-        <newCpu>0</newCpu>
-        <uProt>0</uProt>
-      </DebugFlag>
-      <LintExecutable></LintExecutable>
-      <LintConfigFile></LintConfigFile>
-      <bLintAuto>0</bLintAuto>
-      <bAutoGenD>0</bAutoGenD>
-      <LntExFlags>0</LntExFlags>
-      <pMisraName></pMisraName>
-      <pszMrule></pszMrule>
-      <pSingCmds></pSingCmds>
-      <pMultCmds></pMultCmds>
-      <pMisraNamep></pMisraNamep>
-      <pszMrulep></pszMrulep>
-      <pSingCmdsp></pSingCmdsp>
-      <pMultCmdsp></pMultCmdsp>
-    </TargetOption>
-  </Target>
-
-  <Group>
-    <GroupName>Source Group 1</GroupName>
-    <tvExp>0</tvExp>
-    <tvExpOptDlg>0</tvExpOptDlg>
-    <cbSel>0</cbSel>
-    <RteFlg>0</RteFlg>
-  </Group>
-
-</ProjectOpt>

bsp/swm341/drivers/.config

@@ -1,42 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# RootMenu
-#
-
-#
-# Hardware Drivers Config
-#
-CONFIG_SOC_SWM341=y
-
-#
-# On-chip Peripheral Drivers
-#
-CONFIG_BSP_USING_UART=y
-CONFIG_BSP_USING_UART0=y
-# CONFIG_BSP_USING_UART1 is not set
-# CONFIG_BSP_USING_UART2 is not set
-# CONFIG_BSP_USING_UART3 is not set
-CONFIG_BSP_USING_GPIO=y
-# CONFIG_BSP_USING_ADC is not set
-# CONFIG_BSP_USING_DAC is not set
-# CONFIG_BSP_USING_CAN is not set
-# CONFIG_BSP_USING_TIM is not set
-# CONFIG_BSP_USING_I2C is not set
-# CONFIG_BSP_USING_PWM is not set
-# CONFIG_BSP_USING_RTC is not set
-# CONFIG_BSP_USING_SPI is not set
-# CONFIG_BSP_USING_WDT is not set
-# CONFIG_BSP_USING_CRC is not set
-# CONFIG_BSP_USING_RNG is not set
-# CONFIG_BSP_USING_SDIO is not set
-# CONFIG_BSP_USING_SDRAM is not set
-# CONFIG_BSP_USING_GT9147 is not set
-# CONFIG_BSP_USING_RGB_LCD is not set
-
-#
-# Onboard Peripheral Drivers
-#
-
-#
-# Offboard Peripheral Drivers
-#

bsp/swm320/.config → bsp/synwit/swm320/.config

@@ -661,64 +661,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_MFBD is not set
 # CONFIG_PKG_USING_SLCAN2RTT is not set
 # CONFIG_PKG_USING_SOEM is not set
-# CONFIG_PKG_USING_QPARAM is not set
-
-#
-# Privated Packages of RealThread
-#
-# CONFIG_PKG_USING_CODEC is not set
-# CONFIG_PKG_USING_PLAYER is not set
-# CONFIG_PKG_USING_MPLAYER is not set
-# CONFIG_PKG_USING_PERSIMMON_SRC is not set
-# CONFIG_PKG_USING_JS_PERSIMMON is not set
-# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
-
-#
-# Network Utilities
-#
-# CONFIG_PKG_USING_WICED is not set
-# CONFIG_PKG_USING_CLOUDSDK is not set
-# CONFIG_PKG_USING_POWER_MANAGER is not set
-# CONFIG_PKG_USING_RT_OTA is not set
-# CONFIG_PKG_USING_RTINSIGHT is not set
-# CONFIG_PKG_USING_SMARTCONFIG is not set
-# CONFIG_PKG_USING_RTX is not set
-# CONFIG_RT_USING_TESTCASE is not set
-# CONFIG_PKG_USING_NGHTTP2 is not set
-# CONFIG_PKG_USING_AVS is not set
-# CONFIG_PKG_USING_ALI_LINKKIT is not set
-# CONFIG_PKG_USING_STS is not set
-# CONFIG_PKG_USING_DLMS is not set
-# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
-# CONFIG_PKG_USING_ZBAR is not set
-# CONFIG_PKG_USING_MCF is not set
-# CONFIG_PKG_USING_URPC is not set
-# CONFIG_PKG_USING_DCM is not set
-# CONFIG_PKG_USING_EMQ is not set
-# CONFIG_PKG_USING_CFGM is not set
-# CONFIG_PKG_USING_RT_CMSIS_DAP is not set
-# CONFIG_PKG_USING_SMODULE is not set
-# CONFIG_PKG_USING_SNFD is not set
-# CONFIG_PKG_USING_UDBD is not set
-# CONFIG_PKG_USING_BENCHMARK is not set
-# CONFIG_PKG_USING_UBJSON is not set
-# CONFIG_PKG_USING_DATATYPE is not set
-# CONFIG_PKG_USING_FASTFS is not set
-# CONFIG_PKG_USING_RIL is not set
-# CONFIG_PKG_USING_WATCH_DCM_SVC is not set
-# CONFIG_PKG_USING_WATCH_APP_FWK is not set
-# CONFIG_PKG_USING_GUI_TEST is not set
-# CONFIG_PKG_USING_PMEM is not set
-# CONFIG_PKG_USING_LWRDP is not set
-# CONFIG_PKG_USING_MASAN is not set
-# CONFIG_PKG_USING_BSDIFF_LIB is not set
-# CONFIG_PKG_USING_PRC_DIFF is not set
-
-#
-# RT-Thread Smart
-#
-# CONFIG_PKG_USING_UKERNEL is not set
-# CONFIG_PKG_USING_TRACE_AGENT is not set
 
 #
 # Hardware Drivers Config

bsp/swm320/Kconfig → bsp/synwit/swm320/Kconfig

@@ -8,7 +8,7 @@ config BSP_DIR
 config RTT_DIR
     string
     option env="RTT_ROOT"
-    default "../.."
+    default "../../.."
 
 config PKGS_DIR
     string

bsp/swm320/README.md → bsp/synwit/swm320/README.md

@@ -103,7 +103,7 @@
 
 > 工程默认配置使用 Jlink 仿真器下载程序，在通过 Jlink 连接开发板到 PC 的基础上，点击下载按钮即可下载程序到开发板
 
-推荐熟悉 RT_Thread 的用户使用[env工具](https://www.rt-thread.org/page/download.html)，可以在console下进入到 `bsp/swm320` 目录中，运行以下命令：
+推荐熟悉 RT_Thread 的用户使用[env工具](https://www.rt-thread.org/page/download.html)，可以在console下进入到 `bsp/synwit/swm320` 目录中，运行以下命令：
 
 `scons`
 

bsp/swm341/SConstruct → bsp/synwit/swm320/SConstruct

@@ -5,7 +5,7 @@ import rtconfig
 if os.getenv('RTT_ROOT'):
     RTT_ROOT = os.getenv('RTT_ROOT')
 else:
-    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
 
 sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
 

bsp/swm320/applications/main.c → bsp/synwit/swm320/applications/main.c

@@ -9,8 +9,9 @@
 
 #include <rtthread.h>
 #include <rtdevice.h>
+#include "board.h"
 
-#define LED_PIN 32
+#define LED_PIN GET_PIN(C,6)
 
 int main(void)
 {
@@ -20,32 +21,32 @@ int main(void)
     while (count++)
     {
         rt_pin_write(LED_PIN, PIN_HIGH);
-        rt_thread_mdelay(1000);
+        rt_thread_mdelay(500);
         rt_pin_write(LED_PIN, PIN_LOW);
-        rt_thread_mdelay(1000);
+        rt_thread_mdelay(500);
     }
 
     return RT_EOK;
 }
 
-// #ifdef RT_USING_PIN
-// #define KEY1_PIN 31
-// void key1_cb(void *args)
-// {
-//     rt_kprintf("key1 irq!\n");
-// }
-// static int pin_sample(int argc, char *argv[])
-// {
-//     rt_pin_mode(KEY1_PIN, PIN_IRQ_MODE_FALLING);
-//     rt_pin_attach_irq(KEY1_PIN, PIN_IRQ_MODE_FALLING, key1_cb, RT_NULL);
-//     rt_pin_irq_enable(KEY1_PIN, PIN_IRQ_ENABLE);
-
-//     return RT_EOK;
-// }
-// MSH_CMD_EXPORT(pin_sample, pin sample);
-// #endif
-
-#ifdef RT_USING_ADC
+#ifdef BSP_USING_GPIO
+#define KEY1_PIN GET_PIN(C,5)
+void key1_cb(void *args)
+{
+    rt_kprintf("key1 irq!\n");
+}
+static int pin_sample(int argc, char *argv[])
+{
+    rt_pin_mode(KEY1_PIN, PIN_IRQ_MODE_FALLING);
+    rt_pin_attach_irq(KEY1_PIN, PIN_IRQ_MODE_FALLING, key1_cb, RT_NULL);
+    rt_pin_irq_enable(KEY1_PIN, PIN_IRQ_ENABLE);
+
+    return RT_EOK;
+}
+MSH_CMD_EXPORT(pin_sample, pin sample);
+#endif
+
+#ifdef BSP_USING_ADC
 #define ADC_DEV_NAME "adc1"
 #define ADC_DEV_CHANNEL 0
 #define REFER_VOLTAGE 330
@@ -79,7 +80,7 @@ static int adc_vol_sample(int argc, char *argv[])
 MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample);
 #endif
 
-#ifdef RT_USING_HWTIMER
+#ifdef BSP_USING_TIM
 #define HWTIMER_DEV_NAME "timer0"
 
 static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
@@ -141,7 +142,7 @@ static int hwtimer_sample(int argc, char *argv[])
 MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);
 #endif
 
-#ifdef RT_USING_PWM
+#ifdef BSP_USING_PWM
 #define PWM_DEV_NAME "pwm0" /* PWM设备名称 */
 #define PWM_DEV_CHANNEL 0   /* PWM通道 */
 
@@ -168,7 +169,7 @@ static int pwm_sample(int argc, char *argv[])
 MSH_CMD_EXPORT(pwm_sample, pwm sample);
 #endif
 
-#ifdef RT_USING_RTC
+#ifdef BSP_USING_RTC
 #include <sys/time.h>
 static int rtc_sample(int argc, char *argv[])
 {
@@ -198,7 +199,7 @@ static int rtc_sample(int argc, char *argv[])
 MSH_CMD_EXPORT(rtc_sample, rtc sample);
 #endif
 
-#ifdef RT_USING_WDT
+#ifdef BSP_USING_WDT
 #define WDT_DEVICE_NAME "wdt"
 
 static rt_device_t wdg_dev;
@@ -212,7 +213,7 @@ static void idle_hook(void)
 static int wdt_sample(int argc, char *argv[])
 {
     rt_err_t ret = RT_EOK;
-    rt_uint32_t timeout = 1;
+    rt_uint32_t timeout = 2;
     char device_name[RT_NAME_MAX];
 
     if (argc == 2)
@@ -247,28 +248,24 @@ static int wdt_sample(int argc, char *argv[])
         rt_kprintf("start %s failed!\n", device_name);
         return -RT_ERROR;
     }
-    // rt_thread_idle_sethook(idle_hook);
+    rt_thread_idle_sethook(idle_hook);
 
     return ret;
 }
 MSH_CMD_EXPORT(wdt_sample, wdt sample);
 #endif
 
-#ifdef RT_USING_SPI
+#ifdef BSP_USING_SPI
 #define W25Q_SPI_DEVICE_NAME "spi00"
 #define W25Q_FLASH_NAME "norflash0"
 
 #include "drv_spi.h"
+#ifdef RT_USING_SFUD
 #include "spi_flash_sfud.h"
-#include <dfs_file.h>
-#include <unistd.h>
-#include <stdio.h>
-#include <sys/stat.h>
-#include <sys/statfs.h>
 
 static int rt_hw_spi_flash_init(void)
 {
-    rt_hw_spi_device_attach("spi0", "spi00", GPIOP, PIN22);
+    rt_hw_spi_device_attach("spi0", W25Q_SPI_DEVICE_NAME, GPIOP, PIN22);
 
     if (RT_NULL == rt_sfud_flash_probe(W25Q_FLASH_NAME, W25Q_SPI_DEVICE_NAME))
     {
@@ -334,6 +331,11 @@ static void spi_w25q_sample(int argc, char *argv[])
         rt_kprintf("use rt_spi_transfer_message() read w25q ID is:%x%x\n", id[3], id[4]);
     }
 }
+MSH_CMD_EXPORT(spi_w25q_sample, spi w25q sample);
+
+#ifdef RT_USING_DFS_ELMFAT
+#include <dfs_file.h>
+#include <unistd.h>
 static void spi_flash_elmfat_sample(void)
 {
     int fd, size;
@@ -376,80 +378,77 @@ static void spi_flash_elmfat_sample(void)
     }
 }
 MSH_CMD_EXPORT(spi_flash_elmfat_sample, spi flash elmfat sample);
-MSH_CMD_EXPORT(spi_w25q_sample, spi w25q sample);
+#endif
+#endif
+#endif
+
+#ifdef BSP_USING_SPI
+#ifdef RT_USING_SPI_MSD
+#define SD_SPI_DEVICE_NAME "spi10"
+#define SDCARD_NAME "sd0"
+
+#include "drv_spi.h"
+#include "spi_msd.h"
+#include <dfs_file.h>
+#include <unistd.h>
+
+static int rt_hw_spi1_tfcard(void)
+{
+   rt_hw_spi_device_attach("spi1", SD_SPI_DEVICE_NAME, GPIOB, PIN6);
+   return msd_init(SDCARD_NAME, SD_SPI_DEVICE_NAME);
+}
+INIT_DEVICE_EXPORT(rt_hw_spi1_tfcard);
+
+static void elmfat_sample(void)
+{
+   int fd, size;
+   struct statfs elm_stat;
+   char str[] = "elmfat mount to sdcard.", buf[80];
+
+   if (dfs_mkfs("elm", SDCARD_NAME) == 0)
+       rt_kprintf("make elmfat filesystem success.\n");
+
+   if (dfs_mount(SDCARD_NAME, "/", "elm", 0, 0) == 0)
+       rt_kprintf("elmfat filesystem mount success.\n");
+
+   if (statfs("/", &elm_stat) == 0)
+       rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n",
+                  elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree);
+
+   if (mkdir("/user", 0x777) == 0)
+       rt_kprintf("make a directory: '/user'.\n");
+
+   rt_kprintf("Write string '%s' to /user/test.txt.\n", str);
+
+   fd = open("/user/test.txt", O_WRONLY | O_CREAT);
+   if (fd >= 0)
+   {
+       if (write(fd, str, sizeof(str)) == sizeof(str))
+           rt_kprintf("Write data done.\n");
+
+       close(fd);
+   }
+
+   fd = open("/user/test.txt", O_RDONLY);
+   if (fd >= 0)
+   {
+       size = read(fd, buf, sizeof(buf));
+
+       close(fd);
+
+       if (size == sizeof(str))
+           rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf);
+   }
+}
+MSH_CMD_EXPORT(elmfat_sample, elmfat sample);
+#endif
 #endif
 
-//#ifdef RT_USING_SPI
-//#define SD_SPI_DEVICE_NAME "spi10"
-//#define SDCARD_NAME "sd0"
-
-//#include "drv_spi.h"
-// #include <dfs_file.h>
-// #include <unistd.h>
-// #include <stdio.h>
-// #include <sys/stat.h>
-// #include <sys/statfs.h>
-//#include "spi_msd.h"
-
-//static int rt_hw_spi1_tfcard(void)
-//{
-//    rt_hw_spi_device_attach("spi1", SD_SPI_DEVICE_NAME, GPIOB, PIN6);
-//    return msd_init(SDCARD_NAME, SD_SPI_DEVICE_NAME);
-//}
-//INIT_DEVICE_EXPORT(rt_hw_spi1_tfcard);
-
-//static void elmfat_sample(void)
-//{
-//    int fd, size;
-//    struct statfs elm_stat;
-//    char str[] = "elmfat mount to sdcard.", buf[80];
-
-//    if (dfs_mkfs("elm", SDCARD_NAME) == 0)
-//        rt_kprintf("make elmfat filesystem success.\n");
-
-//    if (dfs_mount(SDCARD_NAME, "/", "elm", 0, 0) == 0)
-//        rt_kprintf("elmfat filesystem mount success.\n");
-
-//    if (statfs("/", &elm_stat) == 0)
-//        rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n",
-//                   elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree);
-
-//    if (mkdir("/user", 0x777) == 0)
-//        rt_kprintf("make a directory: '/user'.\n");
-
-//    rt_kprintf("Write string '%s' to /user/test.txt.\n", str);
-
-//    fd = open("/user/test.txt", O_WRONLY | O_CREAT);
-//    if (fd >= 0)
-//    {
-//        if (write(fd, str, sizeof(str)) == sizeof(str))
-//            rt_kprintf("Write data done.\n");
-
-//        close(fd);
-//    }
-
-//    fd = open("/user/test.txt", O_RDONLY);
-//    if (fd >= 0)
-//    {
-//        size = read(fd, buf, sizeof(buf));
-
-//        close(fd);
-
-//        if (size == sizeof(str))
-//            rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf);
-//    }
-//}
-//MSH_CMD_EXPORT(elmfat_sample, elmfat sample);
-//#endif
-
-#ifdef RT_USING_SDIO
+#ifdef BSP_USING_SDIO
 #define SDCARD_NAME "sd0"
 
 #include <dfs_file.h>
 #include <unistd.h>
-#include <stdio.h>
-#include <sys/stat.h>
-#include <sys/statfs.h>
 
 static void sdio_elmfat_sample(void)
 {

bsp/swm320/drivers/board.c → bsp/synwit/swm320/drivers/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,52 +29,28 @@ void SysTick_Handler(void)
     rt_interrupt_leave();
 }
 
-/**
- * This function will delay for some us.
- *
- * @param us the delay time of us
- */
-void rt_hw_us_delay(rt_uint32_t us)
-{
-    rt_uint32_t ticks;
-    rt_uint32_t told, tnow, tcnt = 0;
-    rt_uint32_t reload = SysTick->LOAD;
-
-    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
-    told = SysTick->VAL;
-    while (1)
-    {
-        tnow = SysTick->VAL;
-        if (tnow != told)
-        {
-            if (tnow < told)
-            {
-                tcnt += told - tnow;
-            }
-            else
-            {
-                tcnt += reload - tnow + told;
-            }
-            told = tnow;
-            if (tcnt >= ticks)
-            {
-                break;
-            }
-        }
-    }
-}
-
 void rt_hw_board_init()
 {
     bsp_clock_config();
-
+    /* Heap initialization */
 #ifdef RT_USING_HEAP
     rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
 #endif
-#ifdef RT_USING_COMPONENTS_INIT
-    rt_components_board_init();
+    /* Pin driver initialization is open by default */
+#ifdef RT_USING_PIN
+    swm_pin_init();
 #endif
+    /* USART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    swm_uart_init();
+#endif
+    /* Set the shell console output device */
 #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
+    /* Board underlying hardware initialization */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
 }

bsp/swm320/drivers/board.h → bsp/synwit/swm320/drivers/board.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,6 +18,9 @@
 #include <string.h>
 #include <SWM320.h>
 
+#include "drv_gpio.h"
+#include "drv_uart.h"
+
 #ifdef __cplusplus
 extern "C"
 {

bsp/synwit/swm320/drivers/drv_adc.c

@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-5-26      lik          first version
+ */
+
+#include "drv_adc.h"
+
+#ifdef RT_USING_ADC
+#ifdef BSP_USING_ADC
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.adc"
+#include <drv_log.h>
+
+#if !defined(BSP_USING_ADC0) && !defined(BSP_USING_ADC1)
+#error "Please define at least one BSP_USING_ADCx"
+/* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */
+#endif
+
+#ifdef BSP_USING_ADC0
+#ifndef ADC0_CFG
+#define ADC0_CFG                                        \
+    {                                                   \
+        .name = "adc0",                                 \
+        .ADCx = ADC0,                                   \
+        .adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \
+        .adc_initstruct.clk_div = 25,                   \
+        .adc_initstruct.pga_ref = PGA_REF_INTERNAL,     \
+        .adc_initstruct.channels = 0,                   \
+        .adc_initstruct.samplAvg = ADC_AVG_SAMPLE1,     \
+        .adc_initstruct.trig_src = ADC_TRIGSRC_SW,      \
+        .adc_initstruct.Continue = 0,                   \
+        .adc_initstruct.EOC_IEn = 0,                    \
+        .adc_initstruct.OVF_IEn = 0,                    \
+        .adc_initstruct.HFULL_IEn = 0,                  \
+        .adc_initstruct.FULL_IEn = 0,                   \
+    }
+#endif /* ADC0_CFG */
+#endif /* BSP_USING_ADC0 */
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CFG
+#define ADC1_CFG                                        \
+    {                                                   \
+        .name = "adc1",                                 \
+        .ADCx = ADC1,                                   \
+        .adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \
+        .adc_initstruct.clk_div = 25,                   \
+        .adc_initstruct.pga_ref = PGA_REF_INTERNAL,     \
+        .adc_initstruct.channels = 0,                   \
+        .adc_initstruct.samplAvg = ADC_AVG_SAMPLE1,     \
+        .adc_initstruct.trig_src = ADC_TRIGSRC_SW,      \
+        .adc_initstruct.Continue = 0,                   \
+        .adc_initstruct.EOC_IEn = 0,                    \
+        .adc_initstruct.OVF_IEn = 0,                    \
+        .adc_initstruct.HFULL_IEn = 0,                  \
+        .adc_initstruct.FULL_IEn = 0,                   \
+    }
+#endif /* ADC1_CFG */
+#endif /* BSP_USING_ADC1 */
+
+struct swm_adc_cfg
+{
+    const char *name;
+    ADC_TypeDef *ADCx;
+    ADC_InitStructure adc_initstruct;
+};
+
+struct swm_adc_device
+{
+    struct swm_adc_cfg *adc_cfg;
+    struct rt_adc_device adc_device;
+};
+
+static struct swm_adc_cfg swm_adc_cfg[] =
+    {
+#ifdef BSP_USING_ADC0
+        ADC0_CFG,
+#endif
+#ifdef BSP_USING_ADC1
+        ADC1_CFG,
+#endif
+
+};
+
+static struct swm_adc_device adc_obj[sizeof(swm_adc_cfg) / sizeof(swm_adc_cfg[0])];
+
+static rt_uint32_t swm_adc_get_channel(rt_uint32_t channel)
+{
+    rt_uint32_t swm_channel = 0;
+
+    switch (channel)
+    {
+    case 0:
+        swm_channel = ADC_CH0;
+        break;
+    case 1:
+        swm_channel = ADC_CH1;
+        break;
+    case 2:
+        swm_channel = ADC_CH2;
+        break;
+    case 3:
+        swm_channel = ADC_CH3;
+        break;
+    case 4:
+        swm_channel = ADC_CH4;
+        break;
+    case 5:
+        swm_channel = ADC_CH5;
+        break;
+    case 6:
+        swm_channel = ADC_CH6;
+        break;
+    case 7:
+        swm_channel = ADC_CH7;
+        break;
+    }
+
+    return swm_channel;
+}
+
+static rt_err_t swm_adc_enabled(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_bool_t enabled)
+{
+    uint32_t adc_chn;
+    struct swm_adc_cfg *adc_cfg;
+    RT_ASSERT(adc_device != RT_NULL);
+    adc_cfg = adc_device->parent.user_data;
+
+    if (channel < 8)
+    {
+        /* set swm ADC channel */
+        adc_chn = swm_adc_get_channel(channel);
+    }
+    else
+    {
+        LOG_E("ADC channel must be between 0 and 7.");
+        return -RT_ERROR;
+    }
+
+    if (enabled)
+    {
+        adc_cfg->ADCx->CTRL |= (adc_chn << ADC_CTRL_CH0_Pos);
+    }
+    else
+    {
+        adc_cfg->ADCx->CTRL &= ~(adc_chn << ADC_CTRL_CH0_Pos);
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t swm_adc_convert(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    uint32_t adc_chn;
+    struct swm_adc_cfg *adc_cfg;
+    RT_ASSERT(adc_device != RT_NULL);
+    RT_ASSERT(value != RT_NULL);
+    adc_cfg = adc_device->parent.user_data;
+
+    if (channel < 8)
+    {
+        /* set swm ADC channel */
+        adc_chn = swm_adc_get_channel(channel);
+    }
+    else
+    {
+        LOG_E("ADC channel must be between 0 and 7.");
+        return -RT_ERROR;
+    }
+
+    /* start ADC */
+    ADC_Start(adc_cfg->ADCx);
+    /* Wait for the ADC to convert */
+    while ((adc_cfg->ADCx->CH[channel].STAT & 0x01) == 0)
+        ;
+
+    /* get ADC value */
+    *value = (rt_uint32_t)ADC_Read(adc_cfg->ADCx, adc_chn);
+
+    return RT_EOK;
+}
+
+static const struct rt_adc_ops swm_adc_ops =
+    {
+        .enabled = swm_adc_enabled,
+        .convert = swm_adc_convert,
+};
+
+static int swm_adc_init(void)
+{
+    int i = 0;
+    int result = RT_EOK;
+
+    for (i = 0; i < sizeof(swm_adc_cfg) / sizeof(swm_adc_cfg[0]); i++)
+    {
+        /* ADC init */
+        adc_obj[i].adc_cfg = &swm_adc_cfg[i];
+
+        if (adc_obj[i].adc_cfg->ADCx == ADC0)
+        {
+#ifdef BSP_USING_ADC0_CHN0
+            adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH0;
+#endif
+#ifdef BSP_USING_ADC0_CHN1
+            adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH1;
+#endif
+#ifdef BSP_USING_ADC0_CHN2
+            adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH2;
+#endif
+#ifdef BSP_USING_ADC0_CHN3
+            adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH3;
+#endif
+#ifdef BSP_USING_ADC0_CHN4
+            adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH4;
+            PORT_Init(PORTA, PIN12, PORTA_PIN12_ADC0_IN4, 0); //PA.12 => ADC0.CH4
+#endif
+#ifdef BSP_USING_ADC0_CHN5
+            adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH5;
+            PORT_Init(PORTA, PIN11, PORTA_PIN11_ADC0_IN5, 0); //PA.11 => ADC0.CH5
+#endif
+#ifdef BSP_USING_ADC0_CHN6
+            adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH6;
+            PORT_Init(PORTA, PIN10, PORTA_PIN10_ADC0_IN6, 0); //PA.10 => ADC0.CH6
+#endif
+#ifdef BSP_USING_ADC0_CHN7
+            adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH7;
+            PORT_Init(PORTA, PIN9, PORTA_PIN9_ADC0_IN7, 0); //PA.9  => ADC0.CH7
+#endif
+        }
+        else if (adc_obj[i].adc_cfg->ADCx == ADC1)
+        {
+#ifdef BSP_USING_ADC1_CHN0
+            adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH0;
+            PORT_Init(PORTC, PIN7, PORTC_PIN7_ADC1_IN0, 0); //PC.7 => ADC1.CH0
+#endif
+#ifdef BSP_USING_ADC1_CHN1
+            adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH1;
+            PORT_Init(PORTC, PIN6, PORTC_PIN6_ADC1_IN1, 0); //PC.6 => ADC1.CH1
+#endif
+#ifdef BSP_USING_ADC1_CHN2
+            adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH2;
+            PORT_Init(PORTC, PIN5, PORTC_PIN5_ADC1_IN2, 0); //PC.5 => ADC1.CH2
+#endif
+#ifdef BSP_USING_ADC1_CHN3
+            adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH3;
+            PORT_Init(PORTC, PIN4, PORTC_PIN4_ADC1_IN3, 0); //PC.4 => ADC1.CH3
+#endif
+#ifdef BSP_USING_ADC1_CHN4
+            adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH4;
+            PORT_Init(PORTN, PIN0, PORTN_PIN0_ADC1_IN4, 0); //PN.0 => ADC1.CH4
+#endif
+#ifdef BSP_USING_ADC1_CHN5
+            adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH5;
+            PORT_Init(PORTN, PIN1, PORTN_PIN1_ADC1_IN5, 0); //PN.1 => ADC1.CH5
+#endif
+#ifdef BSP_USING_ADC1_CHN6
+            adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH6;
+            PORT_Init(PORTN, PIN2, PORTN_PIN2_ADC1_IN6, 0); //PN.2 => ADC1.CH6
+#endif
+#ifdef BSP_USING_ADC1_CHN7
+            adc_obj[i].adc_cfg->adc_initstruct.channels |= ADC_CH7;
+#endif
+        }
+
+        ADC_Init(adc_obj[i].adc_cfg->ADCx, &(adc_obj[i].adc_cfg->adc_initstruct));
+        ADC_Open(adc_obj[i].adc_cfg->ADCx);
+        /* register ADC device */
+        result = rt_hw_adc_register(&adc_obj[i].adc_device, adc_obj[i].adc_cfg->name, &swm_adc_ops, adc_obj[i].adc_cfg);
+        if(result != RT_EOK)
+        {
+            LOG_E("%s register fail.", adc_obj[i].adc_cfg->name);
+        }
+        else
+        {
+            LOG_D("%s register success.", adc_obj[i].adc_cfg->name);
+        }
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(swm_adc_init);
+#endif /* BSP_USING_ADC */
+#endif /* RT_USING_ADC */

bsp/synwit/swm320/drivers/drv_adc.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-5-26      lik          first version
+ */
+
+#ifndef __DRV_ADC_H__
+#define __DRV_ADC_H__
+
+#include "board.h"
+
+int swm_adc_init(void);
+
+#endif /* __DRV_ADC_H__ */

bsp/synwit/swm320/drivers/drv_crypto.c

@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-07-10     lik          first version
+ */
+
+#include "drv_crypto.h"
+#include <string.h>
+
+#ifdef RT_USING_HWCRYPTO
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.crypto"
+#include <drv_log.h>
+
+struct swm_hwcrypto_device
+{
+    struct rt_hwcrypto_device dev;
+    struct rt_mutex mutex;
+};
+
+static struct swm_hwcrypto_device hwcrypto_obj;
+
+#ifdef BSP_USING_CRC
+
+#define DEFAULT_CRC (CRC)
+#define DEFAULT_INIVAL (0x00000000)
+#define DEFAULT_INBITS (2)
+#define DEFAULT_CRC1632 (0)
+#define DEFAULT_OUT_NOT (0)
+#define DEFAULT_OUT_REV (0)
+
+
+struct swm_crc_cfg
+{
+    CRC_TypeDef *CRCx;
+    uint32_t inival;
+    uint8_t crc_inbits;
+    uint8_t crc_1632;
+    uint8_t crc_out_not;
+    uint8_t crc_out_rev;
+};
+
+static struct hwcrypto_crc_cfg swm_crc_cfg;
+
+static rt_uint32_t swm_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)
+{
+    rt_uint32_t result = 0;
+    struct swm_hwcrypto_device *hwcrypto_dev = (struct swm_hwcrypto_device *)ctx->parent.device->user_data;
+
+    struct swm_crc_cfg *crc_cfg = (struct swm_crc_cfg *)(ctx->parent.contex);
+
+    rt_mutex_take(&hwcrypto_dev->mutex, RT_WAITING_FOREVER);
+
+    if (memcmp(&swm_crc_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)) != 0)
+    {
+        crc_cfg->CRCx = CRC;
+
+        crc_cfg->inival = ctx->crc_cfg.last_val;
+
+        switch (ctx->crc_cfg.poly)
+        {
+        case 0x1021:
+            crc_cfg->crc_1632 = 1;
+            break;
+        case 0x04C11DB7:
+            crc_cfg->crc_1632 = 0;
+            break;
+        default:
+            goto _exit;
+        }
+
+        switch (ctx->crc_cfg.width)
+        {
+        case 8:
+            crc_cfg->crc_inbits = 2;
+            break;
+        case 16:
+            crc_cfg->crc_inbits = 1;
+            break;
+        case 32:
+            crc_cfg->crc_inbits = 0;
+            break;
+        default:
+            goto _exit;
+        }
+
+        crc_cfg->crc_out_not = 0;
+
+        switch (ctx->crc_cfg.flags)
+        {
+        case 0:
+        case CRC_FLAG_REFIN:
+            crc_cfg->crc_out_rev = 0;
+            break;
+        case CRC_FLAG_REFOUT:
+        case CRC_FLAG_REFIN | CRC_FLAG_REFOUT:
+            crc_cfg->crc_out_rev = 1;
+            break;
+        default:
+            goto _exit;
+        }
+
+        CRC_Init(crc_cfg->CRCx, (crc_cfg->crc_inbits << 1) | crc_cfg->crc_1632, crc_cfg->crc_out_not, crc_cfg->crc_out_rev, crc_cfg->inival);
+        memcpy(&swm_crc_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg));
+    }
+
+    for (uint32_t i = 0; i < length; i++)
+        CRC_Write((uint32_t)in[i]);
+    result = CRC_Result();
+
+    ctx->crc_cfg.last_val = result;
+
+    swm_crc_cfg.last_val = ctx->crc_cfg.last_val;
+    result = (result ? result ^ (ctx->crc_cfg.xorout) : result);
+
+_exit:
+    rt_mutex_release(&hwcrypto_dev->mutex);
+
+    return result;
+}
+
+static const struct hwcrypto_crc_ops swm_crc_ops =
+    {
+        .update = swm_crc_update,
+};
+#endif /* BSP_USING_CRC */
+
+static rt_err_t swm_crypto_create(struct rt_hwcrypto_ctx *ctx)
+{
+    rt_err_t res = RT_EOK;
+
+    switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+#if defined(BSP_USING_CRC)
+    case HWCRYPTO_TYPE_CRC:
+    {
+        struct swm_crc_cfg *crc_cfg = rt_calloc(1, sizeof(struct swm_crc_cfg));
+        if (RT_NULL == crc_cfg)
+        {
+            res = -RT_ERROR;
+            break;
+        }
+        crc_cfg->CRCx = DEFAULT_CRC;
+        crc_cfg->inival = DEFAULT_INIVAL;
+        crc_cfg->crc_inbits = DEFAULT_INBITS;
+        crc_cfg->crc_1632 = DEFAULT_CRC1632;
+        crc_cfg->crc_out_not = DEFAULT_OUT_NOT;
+        crc_cfg->crc_out_rev = DEFAULT_OUT_REV;
+
+        ctx->contex = crc_cfg;
+        ((struct hwcrypto_crc *)ctx)->ops = &swm_crc_ops;
+        break;
+    }
+#endif /* BSP_USING_CRC */
+    default:
+        res = -RT_ERROR;
+        break;
+    }
+    return res;
+}
+
+static void swm_crypto_destroy(struct rt_hwcrypto_ctx *ctx)
+{
+    struct swm_crc_cfg *crc_cfg = (struct swm_crc_cfg *)(ctx->contex);
+    switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+#if defined(BSP_USING_CRC)
+    case HWCRYPTO_TYPE_CRC:
+        crc_cfg->CRCx->CR &= ~CRC_CR_EN_Msk;
+        break;
+#endif /* BSP_USING_CRC */
+    default:
+        break;
+    }
+
+    rt_free(ctx->contex);
+}
+
+static rt_err_t swm_crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src)
+{
+    rt_err_t res = RT_EOK;
+
+    switch (src->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+#if defined(BSP_USING_CRC)
+    case HWCRYPTO_TYPE_CRC:
+        if (des->contex && src->contex)
+        {
+            rt_memcpy(des->contex, src->contex, sizeof(struct swm_crc_cfg));
+        }
+        break;
+#endif /* BSP_USING_CRC */
+    default:
+        res = -RT_ERROR;
+        break;
+    }
+    return res;
+}
+
+static void swm_crypto_reset(struct rt_hwcrypto_ctx *ctx)
+{
+    struct swm_crc_cfg *crc_cfg = (struct swm_crc_cfg *)(ctx->contex);
+    switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+#if defined(BSP_USING_CRC)
+    case HWCRYPTO_TYPE_CRC:
+        crc_cfg->CRCx->CR &= ~CRC_CR_EN_Msk;
+        break;
+#endif /* BSP_USING_CRC */
+    default:
+        break;
+    }
+}
+
+static const struct rt_hwcrypto_ops swm_hwcrypto_ops =
+    {
+        .create = swm_crypto_create,
+        .destroy = swm_crypto_destroy,
+        .copy = swm_crypto_clone,
+        .reset = swm_crypto_reset,
+};
+
+int swm_crypto_init(void)
+{
+    rt_uint32_t cpuid[2] = {0};
+
+    hwcrypto_obj.dev.ops = &swm_hwcrypto_ops;
+
+    cpuid[0] = SCB->CPUID;
+    hwcrypto_obj.dev.id = 0;
+    rt_memcpy(&hwcrypto_obj.dev.id, cpuid, 8);
+
+    hwcrypto_obj.dev.user_data = &hwcrypto_obj;
+
+    if (rt_hwcrypto_register(&hwcrypto_obj.dev, RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK)
+    {
+        return -1;
+    }
+    rt_mutex_init(&hwcrypto_obj.mutex, RT_HWCRYPTO_DEFAULT_NAME, RT_IPC_FLAG_PRIO);
+    return 0;
+}
+INIT_BOARD_EXPORT(swm_crypto_init);
+
+
+#endif /* RT_USING_HWCRYPTO */

bsp/synwit/swm320/drivers/drv_crypto.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-07-10     lik          first version
+ */
+
+#ifndef __DRV_CRYPTO_H__
+#define __DRV_CRYPTO_H__
+
+#include "board.h"
+
+int swm_crypto_init(void);
+
+#endif /* __DRV_CRYPTO_H__ */

bsp/swm320/drivers/drv_gpio.c → bsp/synwit/swm320/drivers/drv_gpio.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,7 +15,26 @@
 #ifdef RT_USING_PIN
 #ifdef BSP_USING_GPIO
 
-static const struct swm_pin_index pins[] =
+//#define DRV_DEBUG
+#define LOG_TAG "drv.gpio"
+#include <drv_log.h>
+
+#define __SWM_PIN(index, gpio, pin_index)                    \
+    {                                                        \
+        index, GPIO##gpio, PIN##pin_index, GPIO##gpio##_IRQn \
+    }
+#define GPIO0 ((GPIO_TypeDef *)(0))
+#define GPIO0_IRQn (GPIOA0_IRQn)
+
+struct swm_pin_device
+{
+    uint32_t index;
+    GPIO_TypeDef *gpio;
+    uint32_t pin;
+    IRQn_Type irq;
+};
+
+static const struct swm_pin_device pin_obj[] =
     {
         __SWM_PIN(0, A, 0),
         __SWM_PIN(1, A, 1),
@@ -228,64 +247,31 @@ static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
 
 #define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
 
-static const struct swm_pin_index *get_pin(uint8_t pin)
+static const struct swm_pin_device *_pin2struct(uint8_t pin)
 {
-    const struct swm_pin_index *index;
+    const struct swm_pin_device *gpio_obj;
 
-    if (pin < ITEM_NUM(pins))
+    if (pin < ITEM_NUM(pin_obj))
     {
-        index = &pins[pin];
-        if (index->gpio == GPIO0)
-            index = RT_NULL;
+        gpio_obj = &pin_obj[pin];
     }
     else
     {
-        index = RT_NULL;
+        gpio_obj = RT_NULL;
     }
 
-    return index;
-}
-
-static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
-{
-    const struct swm_pin_index *index;
-
-    index = get_pin(pin);
-    if (index == RT_NULL)
-    {
-        return;
-    }
-    if (value)
-    {
-        GPIO_SetBit(index->gpio, index->pin);
-    }
-    else
-    {
-        GPIO_ClrBit(index->gpio, index->pin);
-    }
-}
-
-static int swm_pin_read(rt_device_t dev, rt_base_t pin)
-{
-    const struct swm_pin_index *index;
-
-    index = get_pin(pin);
-    if (index == RT_NULL)
-    {
-        return PIN_LOW;
-    }
-    return (int)GPIO_GetBit(index->gpio, index->pin);
+    return gpio_obj;
 }
 
 static void swm_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 {
-    const struct swm_pin_index *index;
+    const struct swm_pin_device *gpio_obj;
     int dir = 0;
     int pull_up = 0;
     int pull_down = 0;
 
-    index = get_pin(pin);
-    if (index == RT_NULL)
+    gpio_obj = _pin2struct(pin);
+    if (gpio_obj == RT_NULL)
     {
         return;
     }
@@ -317,7 +303,38 @@ static void swm_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
         break;
     }
 
-    GPIO_Init(index->gpio, index->pin, dir, pull_up, pull_down);
+    GPIO_Init(gpio_obj->gpio, gpio_obj->pin, dir, pull_up, pull_down);
+}
+
+static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    const struct swm_pin_device *gpio_obj;
+
+    gpio_obj = _pin2struct(pin);
+    if (gpio_obj == RT_NULL)
+    {
+        return;
+    }
+    if (value)
+    {
+        GPIO_AtomicSetBit(gpio_obj->gpio, gpio_obj->pin);
+    }
+    else
+    {
+        GPIO_AtomicClrBit(gpio_obj->gpio, gpio_obj->pin);
+    }
+}
+
+static int swm_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    const struct swm_pin_device *gpio_obj;
+
+    gpio_obj = _pin2struct(pin);
+    if (gpio_obj == RT_NULL)
+    {
+        return PIN_LOW;
+    }
+    return (int)GPIO_GetBit(gpio_obj->gpio, gpio_obj->pin);
 }
 
 static rt_err_t swm_pin_attach_irq(struct rt_device *device,
@@ -326,15 +343,8 @@ static rt_err_t swm_pin_attach_irq(struct rt_device *device,
                                    void (*hdr)(void *args),
                                    void *args)
 {
-    const struct swm_pin_index *index;
     rt_base_t level;
 
-    index = get_pin(pin);
-    if (index == RT_NULL)
-    {
-        return RT_ENOSYS;
-    }
-
     level = rt_hw_interrupt_disable();
     if (pin_irq_hdr_tab[pin].pin == pin &&
         pin_irq_hdr_tab[pin].mode == mode &&
@@ -354,15 +364,8 @@ static rt_err_t swm_pin_attach_irq(struct rt_device *device,
 
 static rt_err_t swm_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 {
-    const struct swm_pin_index *index;
     rt_base_t level;
 
-    index = get_pin(pin);
-    if (index == RT_NULL)
-    {
-        return RT_ENOSYS;
-    }
-
     level = rt_hw_interrupt_disable();
     pin_irq_hdr_tab[pin].mode = 0;
     pin_irq_hdr_tab[pin].hdr = RT_NULL;
@@ -375,11 +378,11 @@ static rt_err_t swm_pin_irq_enable(struct rt_device *device,
                                    rt_base_t pin,
                                    rt_uint32_t enabled)
 {
-    const struct swm_pin_index *index;
+    const struct swm_pin_device *gpio_obj;
     rt_base_t level = 0;
 
-    index = get_pin(pin);
-    if (index == RT_NULL)
+    gpio_obj = _pin2struct(pin);
+    if (gpio_obj == RT_NULL)
     {
         return RT_ENOSYS;
     }
@@ -389,39 +392,39 @@ static rt_err_t swm_pin_irq_enable(struct rt_device *device,
         switch (pin_irq_hdr_tab[pin].mode)
         {
         case PIN_IRQ_MODE_RISING:
-            GPIO_Init(index->gpio, index->pin, 0, 0, 1);
-            EXTI_Init(index->gpio, index->pin, EXTI_RISE_EDGE);
+            GPIO_Init(gpio_obj->gpio, gpio_obj->pin, 0, 0, 1);
+            EXTI_Init(gpio_obj->gpio, gpio_obj->pin, EXTI_RISE_EDGE);
             break;
         case PIN_IRQ_MODE_FALLING:
-            GPIO_Init(index->gpio, index->pin, 0, 1, 0);
-            EXTI_Init(index->gpio, index->pin, EXTI_FALL_EDGE);
+            GPIO_Init(gpio_obj->gpio, gpio_obj->pin, 0, 1, 0);
+            EXTI_Init(gpio_obj->gpio, gpio_obj->pin, EXTI_FALL_EDGE);
             break;
         case PIN_IRQ_MODE_RISING_FALLING:
-            GPIO_Init(index->gpio, index->pin, 0, 1, 1);
-            EXTI_Init(index->gpio, index->pin, EXTI_BOTH_EDGE);
+            GPIO_Init(gpio_obj->gpio, gpio_obj->pin, 0, 1, 1);
+            EXTI_Init(gpio_obj->gpio, gpio_obj->pin, EXTI_BOTH_EDGE);
             break;
         case PIN_IRQ_MODE_HIGH_LEVEL:
-            GPIO_Init(index->gpio, index->pin, 0, 0, 1);
-            EXTI_Init(index->gpio, index->pin, EXTI_HIGH_LEVEL);
+            GPIO_Init(gpio_obj->gpio, gpio_obj->pin, 0, 0, 1);
+            EXTI_Init(gpio_obj->gpio, gpio_obj->pin, EXTI_HIGH_LEVEL);
             break;
         case PIN_IRQ_MODE_LOW_LEVEL:
-            GPIO_Init(index->gpio, index->pin, 0, 1, 0);
-            EXTI_Init(index->gpio, index->pin, EXTI_LOW_LEVEL);
+            GPIO_Init(gpio_obj->gpio, gpio_obj->pin, 0, 1, 0);
+            EXTI_Init(gpio_obj->gpio, gpio_obj->pin, EXTI_LOW_LEVEL);
             break;
         default:
             return RT_EINVAL;
         }
 
         level = rt_hw_interrupt_disable();
-        NVIC_EnableIRQ(index->irq);
-        EXTI_Open(index->gpio, index->pin);
+        NVIC_EnableIRQ(gpio_obj->irq);
+        EXTI_Open(gpio_obj->gpio, gpio_obj->pin);
         rt_hw_interrupt_enable(level);
     }
     else if (enabled == PIN_IRQ_DISABLE)
     {
         level = rt_hw_interrupt_disable();
-        NVIC_DisableIRQ(index->irq);
-        EXTI_Close(index->gpio, index->pin);
+        // NVIC_DisableIRQ(gpio_obj->irq);
+        EXTI_Close(gpio_obj->gpio, gpio_obj->pin);
         rt_hw_interrupt_enable(level);
     }
     else
@@ -431,6 +434,64 @@ static rt_err_t swm_pin_irq_enable(struct rt_device *device,
     return RT_EOK;
 }
 
+static rt_base_t swm_pin_get(const char *name)
+{
+    rt_base_t pin = 0;
+    int pin_num = 0;
+    int i, name_len;
+
+    name_len = rt_strlen(name);
+
+    if ((name_len < 4) || (name_len >= 6))
+    {
+        return -RT_EINVAL;
+    }
+    if ((name[0] != 'P') || (name[2] != '.'))
+    {
+        return -RT_EINVAL;
+    }
+
+    switch(name[1])
+    {
+        case 'A':
+            pin = 0;
+        break;
+        case 'B':
+            pin = 13;
+        break;
+        case 'C':
+            pin = 26;
+        break;
+        case 'M':
+            pin = 34;
+        break;
+        case 'N':
+            pin = 56;
+        break;
+        case 'P':
+            pin = 76;
+        break;
+        default:
+            return -RT_EINVAL;
+    }
+
+    for (i = 3; i < name_len; i++)
+    {
+        pin_num *= 10;
+        pin_num += name[i] - '0';
+    }
+    if(pin_num < 24)
+    {
+        pin += pin_num;
+    }
+    else
+    {
+        return -RT_EINVAL;
+    }
+
+    return pin;
+}
+
 const static struct rt_pin_ops swm_pin_ops =
     {
         .pin_mode = swm_pin_mode,
@@ -438,25 +499,26 @@ const static struct rt_pin_ops swm_pin_ops =
         .pin_read = swm_pin_read,
         .pin_attach_irq = swm_pin_attach_irq,
         .pin_detach_irq = swm_pin_detach_irq,
-        .pin_irq_enable = swm_pin_irq_enable};
+        .pin_irq_enable = swm_pin_irq_enable,
+        .pin_get = swm_pin_get};
 
-static void rt_hw_pin_isr(GPIO_TypeDef *GPIOx)
+static void swm_pin_isr(GPIO_TypeDef *GPIOx)
 {
     static int gpio[24];
     int index = 0;
     static int init = 0;
-    const struct swm_pin_index *pin;
+    const struct swm_pin_device *gpio_obj;
 
     if (init == 0)
     {
         init = 1;
-        for (pin = &pins[0];
-             pin->index < ITEM_NUM(pins);
-             pin++)
+        for (gpio_obj = &pin_obj[0];
+             gpio_obj->index < ITEM_NUM(pin_obj);
+             gpio_obj++)
         {
-            if (pin->gpio == GPIOx)
+            if (gpio_obj->gpio == GPIOx)
             {
-                gpio[index] = pin->index;
+                gpio[index] = gpio_obj->index;
                 index++;
                 RT_ASSERT(index <= 24)
             }
@@ -464,13 +526,13 @@ static void rt_hw_pin_isr(GPIO_TypeDef *GPIOx)
     }
     for (index = 0; index < 24; index++)
     {
-        pin = get_pin(gpio[index]);
-        if (EXTI_State(pin->gpio, pin->pin))
+        gpio_obj = _pin2struct(gpio[index]);
+        if (EXTI_State(gpio_obj->gpio, gpio_obj->pin))
         {
-            EXTI_Clear(pin->gpio, pin->pin);
-            if (pin_irq_hdr_tab[pin->index].hdr)
+            EXTI_Clear(gpio_obj->gpio, gpio_obj->pin);
+            if (pin_irq_hdr_tab[gpio_obj->index].hdr)
             {
-                pin_irq_hdr_tab[pin->index].hdr(pin_irq_hdr_tab[pin->index].args);
+                pin_irq_hdr_tab[gpio_obj->index].hdr(pin_irq_hdr_tab[gpio_obj->index].args);
             }
         }
     }
@@ -479,50 +541,49 @@ static void rt_hw_pin_isr(GPIO_TypeDef *GPIOx)
 void GPIOA_Handler(void)
 {
     rt_interrupt_enter();
-    rt_hw_pin_isr(GPIOA);
+    swm_pin_isr(GPIOA);
     rt_interrupt_leave();
 }
 
 void GPIOB_Handler(void)
 {
     rt_interrupt_enter();
-    rt_hw_pin_isr(GPIOB);
+    swm_pin_isr(GPIOB);
     rt_interrupt_leave();
 }
 
 void GPIOC_Handler(void)
 {
     rt_interrupt_enter();
-    rt_hw_pin_isr(GPIOC);
+    swm_pin_isr(GPIOC);
     rt_interrupt_leave();
 }
 
 void GPIOM_Handler(void)
 {
     rt_interrupt_enter();
-    rt_hw_pin_isr(GPIOM);
+    swm_pin_isr(GPIOM);
     rt_interrupt_leave();
 }
 
 void GPION_Handler(void)
 {
     rt_interrupt_enter();
-    rt_hw_pin_isr(GPION);
+    swm_pin_isr(GPION);
     rt_interrupt_leave();
 }
 
 void GPIOP_Handler(void)
 {
     rt_interrupt_enter();
-    rt_hw_pin_isr(GPIOP);
+    swm_pin_isr(GPIOP);
     rt_interrupt_leave();
 }
 
-int rt_hw_pin_init(void)
+int swm_pin_init(void)
 {
     return rt_device_pin_register("pin", &swm_pin_ops, RT_NULL);
 }
-INIT_BOARD_EXPORT(rt_hw_pin_init);
 
 #endif /* BSP_USING_GPIO */
 #endif /* RT_USING_PIN */

bsp/synwit/swm320/drivers/drv_gpio.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          rewrite
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include "board.h"
+
+#define GET_PIN(GPIOx,PIN) (rt_uint8_t)__SWM_GET_PIN_##GPIOx(PIN)
+
+#define __SWM_GET_PIN_A(PIN)  (PIN)
+#define __SWM_GET_PIN_B(PIN)  (13 + PIN)
+#define __SWM_GET_PIN_C(PIN)  (26 + PIN)
+#define __SWM_GET_PIN_M(PIN)  (34 + PIN)
+#define __SWM_GET_PIN_N(PIN)  (56 + PIN)
+#define __SWM_GET_PIN_P(PIN)  (76 + PIN)
+
+int swm_pin_init(void);
+
+#endif /* __DRV_GPIO_H__ */

bsp/synwit/swm320/drivers/drv_hwtimer.c

@@ -0,0 +1,350 @@
+/*
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10    Zohar_Lee    first version
+ * 2020-07-10    lik          format file
+ */
+
+#include "drv_hwtimer.h"
+
+#ifdef RT_USING_HWTIMER
+#ifdef BSP_USING_TIM
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.hwtimer"
+#include <drv_log.h>
+
+#if !defined(BSP_USING_TIM0) && !defined(BSP_USING_TIM1) && !defined(BSP_USING_TIM2) && !defined(BSP_USING_TIM3)     \
+&& !defined(BSP_USING_TIM4) && !defined(BSP_USING_TIM5)
+#error "Please define at least one BSP_USING_TIMx"
+/* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG            \
+    {                                  \
+        .maxfreq = 120000000,          \
+        .minfreq = 120000000,          \
+        .maxcnt = 0xFFFFFFFF,          \
+        .cntmode = HWTIMER_CNTMODE_DW, \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM0
+#ifndef TIM0_CFG
+#define TIM0_CFG          \
+    {                     \
+        .name = "timer0", \
+        .TIMRx = TIMR0,   \
+    }
+#endif /* TIM0_CFG */
+#endif /* BSP_USING_TIM0 */
+
+#ifdef BSP_USING_TIM1
+#ifndef TIM1_CFG
+#define TIM1_CFG          \
+    {                     \
+        .name = "timer1", \
+        .TIMRx = TIMR1,   \
+    }
+#endif /* TIM1_CFG */
+#endif /* BSP_USING_TIM1 */
+
+#ifdef BSP_USING_TIM2
+#ifndef TIM2_CFG
+#define TIM2_CFG          \
+    {                     \
+        .name = "timer2", \
+        .TIMRx = TIMR2,   \
+    }
+#endif /* TIM2_CFG */
+#endif /* BSP_USING_TIM2 */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CFG
+#define TIM3_CFG          \
+    {                     \
+        .name = "timer3", \
+        .TIMRx = TIMR3,   \
+    }
+#endif /* TIM3_CFG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef BSP_USING_TIM4
+#ifndef TIM4_CFG
+#define TIM4_CFG          \
+    {                     \
+        .name = "timer4", \
+        .TIMRx = TIMR4,   \
+    }
+#endif /* TIM4_CFG */
+#endif /* BSP_USING_TIM4 */
+
+#ifdef BSP_USING_TIM5
+#ifndef TIM5_CFG
+#define TIM5_CFG          \
+    {                     \
+        .name = "timer5", \
+        .TIMRx = TIMR5,   \
+    }
+#endif /* TIM5_CFG */
+#endif /* BSP_USING_TIM5 */
+
+struct swm_hwtimer_cfg
+{
+    char *name;
+    TIMR_TypeDef *TIMRx;
+};
+
+struct swm_hwtimer_device
+{
+    struct swm_hwtimer_cfg *hwtimer_cfg;
+    rt_hwtimer_t time_device;
+};
+
+enum
+{
+#ifdef BSP_USING_TIM0
+    TIM0_INDEX,
+#endif
+#ifdef BSP_USING_TIM1
+    TIM1_INDEX,
+#endif
+#ifdef BSP_USING_TIM2
+    TIM2_INDEX,
+#endif
+#ifdef BSP_USING_TIM3
+    TIM3_INDEX,
+#endif
+#ifdef BSP_USING_TIM4
+    TIM4_INDEX,
+#endif
+#ifdef BSP_USING_TIM5
+    TIM5_INDEX,
+#endif
+};
+
+static struct swm_hwtimer_cfg swm_hwtimer_cfg[] =
+    {
+#ifdef BSP_USING_TIM0
+        TIM0_CFG,
+#endif
+#ifdef BSP_USING_TIM1
+        TIM1_CFG,
+#endif
+#ifdef BSP_USING_TIM2
+        TIM2_CFG,
+#endif
+#ifdef BSP_USING_TIM3
+        TIM3_CFG,
+#endif
+#ifdef BSP_USING_TIM4
+        TIM4_CFG,
+#endif
+#ifdef BSP_USING_TIM5
+        TIM5_CFG,
+#endif
+};
+
+static struct swm_hwtimer_device hwtimer_obj[sizeof(swm_hwtimer_cfg) / sizeof(swm_hwtimer_cfg[0])] = {0};
+
+static void swm_timer_configure(struct rt_hwtimer_device *timer_device, rt_uint32_t state)
+{
+    struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL;
+    RT_ASSERT(timer_device != RT_NULL);
+
+    if (state)
+    {
+        hwtimer_cfg = timer_device->parent.user_data;
+        TIMR_Init(hwtimer_cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock, 1);
+        timer_device->freq = SystemCoreClock;
+    }
+}
+
+static rt_err_t swm_timer_start(rt_hwtimer_t *timer_device, rt_uint32_t cnt, rt_hwtimer_mode_t opmode)
+{
+    rt_err_t result = RT_EOK;
+    struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL;
+    RT_ASSERT(timer_device != RT_NULL);
+    hwtimer_cfg = timer_device->parent.user_data;
+
+    if (opmode == HWTIMER_MODE_ONESHOT)
+    {
+        /* set timer to single mode */
+        timer_device->mode = HWTIMER_MODE_ONESHOT;
+    }
+    else
+    {
+        timer_device->mode = HWTIMER_MODE_PERIOD;
+    }
+    TIMR_SetPeriod(hwtimer_cfg->TIMRx, cnt);
+    TIMR_Stop(hwtimer_cfg->TIMRx);
+    TIMR_Start(hwtimer_cfg->TIMRx);
+
+    return result;
+}
+
+static void swm_timer_stop(rt_hwtimer_t *timer_device)
+{
+    struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL;
+    RT_ASSERT(timer_device != RT_NULL);
+    hwtimer_cfg = timer_device->parent.user_data;
+
+    /* stop timer */
+    TIMR_Stop(hwtimer_cfg->TIMRx);
+}
+
+static rt_uint32_t swm_timer_count_get(rt_hwtimer_t *timer_device)
+{
+    struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL;
+    RT_ASSERT(timer_device != RT_NULL);
+    hwtimer_cfg = timer_device->parent.user_data;
+
+    return TIMR_GetCurValue(hwtimer_cfg->TIMRx);
+}
+
+static rt_err_t swm_timer_control(rt_hwtimer_t *timer_device, rt_uint32_t cmd, void *args)
+{
+    struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL;
+    rt_err_t result = RT_EOK;
+    RT_ASSERT(timer_device != RT_NULL);
+    RT_ASSERT(args != RT_NULL);
+    hwtimer_cfg = timer_device->parent.user_data;
+
+    switch (cmd)
+    {
+    case HWTIMER_CTRL_FREQ_SET:
+    {
+        rt_uint32_t freq;
+        freq = *(rt_uint32_t *)args;
+
+        TIMR_Init(hwtimer_cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock / freq, 1);
+    }
+    break;
+    default:
+    {
+        result = -RT_ENOSYS;
+    }
+    break;
+    }
+
+    return result;
+}
+
+static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
+
+static const struct rt_hwtimer_ops swm_timer_ops =
+    {
+        .init = swm_timer_configure,
+        .start = swm_timer_start,
+        .stop = swm_timer_stop,
+        .count_get = swm_timer_count_get,
+        .control = swm_timer_control};
+
+void swm_timer_isr(rt_hwtimer_t *timer_device)
+{
+    struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL;
+    RT_ASSERT(timer_device != RT_NULL);
+    hwtimer_cfg = timer_device->parent.user_data;
+
+    TIMR_INTClr(hwtimer_cfg->TIMRx);
+    rt_device_hwtimer_isr(timer_device);
+}
+
+#ifdef BSP_USING_TIM0
+void TIMR0_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    swm_timer_isr(&(hwtimer_obj[TIM0_INDEX].time_device));
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif //BSP_USING_TIM0
+
+#ifdef BSP_USING_TIM1
+void TIMR1_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    swm_timer_isr(&(hwtimer_obj[TIM1_INDEX].time_device));
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif //BSP_USING_TIM1
+
+#ifdef BSP_USING_TIM2
+void TIMR2_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    swm_timer_isr(&(hwtimer_obj[TIM2_INDEX].time_device));
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif //BSP_USING_TIM2
+
+#ifdef BSP_USING_TIM3
+void TIMR3_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    swm_timer_isr(&(hwtimer_obj[TIM3_INDEX].time_device));
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif //BSP_USING_TIM3
+
+#ifdef BSP_USING_TIM4
+void TIMR4_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    swm_timer_isr(&(hwtimer_obj[TIM4_INDEX].time_device));
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif //BSP_USING_TIM4
+
+#ifdef BSP_USING_TIM5
+void TIMR5_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    swm_timer_isr(&(hwtimer_obj[TIM5_INDEX].time_device));
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif //BSP_USING_TIM5
+
+static int swm_timer_init(void)
+{
+    int i = 0;
+    int result = RT_EOK;
+
+    for (i = 0; i < sizeof(swm_hwtimer_cfg) / sizeof(swm_hwtimer_cfg[0]); i++)
+    {
+        hwtimer_obj[i].hwtimer_cfg = &swm_hwtimer_cfg[i];
+        hwtimer_obj[i].time_device.info = &_info;
+        hwtimer_obj[i].time_device.ops = &swm_timer_ops;
+        result = rt_device_hwtimer_register(&hwtimer_obj[i].time_device, hwtimer_obj[i].hwtimer_cfg->name, hwtimer_obj[i].hwtimer_cfg);
+        if (result != RT_EOK)
+        {
+            LOG_E("%s register fail.", hwtimer_obj[i].hwtimer_cfg->name);
+        }
+        else
+        {
+            LOG_D("%s register success.", hwtimer_obj[i].hwtimer_cfg->name);
+        }
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(swm_timer_init);
+
+#endif /* BSP_USING_TIM */
+#endif /* RT_USING_HWTIMER */

bsp/synwit/swm320/drivers/drv_hwtimer.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          rewrite
+ */
+
+#ifndef __DRV_HWTIMER_H__
+#define __DRV_HWTIMER_H__
+
+#include "board.h"
+
+int swm_timer_init(void);
+
+#endif /* __DRV_HWTIMER_H__ */

bsp/swm320/drivers/drv_nor_flash.c → bsp/synwit/swm320/drivers/drv_nor_flash.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,6 +18,10 @@
 #define LOG_TAG "drv.norflash"
 #include <drv_log.h>
 
+#define BLOCK_SIZE (64 * 1024)
+#define FLASH_SIZE (BSP_NOR_FLASH_SIZE)
+#define BLOCK_COUNTER (FLASH_SIZE / BLOCK_SIZE)
+
 static struct rt_mutex flash_lock;
 
 /* RT-Thread MTD device interface */
@@ -64,15 +68,16 @@ static rt_err_t swm_norflash_erase_block(struct rt_mtd_nor_device *device,
     return RT_EOK;
 }
 
-const static struct rt_mtd_nor_driver_ops mtd_ops =
+const static struct rt_mtd_nor_driver_ops swm_mtd_ops =
     {
         swm_norflash_read_id,
         swm_norflash_read,
         swm_norflash_write,
         swm_norflash_erase_block};
 
-static struct rt_mtd_nor_device mtd;
-int rt_hw_norflash_init(void)
+static struct rt_mtd_nor_device mtd_device;
+
+int swm_norflash_init(void)
 {
     NORFL_InitStructure NORFL_InitStruct;
 
@@ -92,8 +97,8 @@ int rt_hw_norflash_init(void)
     NORFL_Init(&NORFL_InitStruct);
 
     /* set page size and block size */
-    mtd.block_size = BLOCK_SIZE; /* 64kByte */
-    mtd.ops = &mtd_ops;
+    mtd_device.block_size = BLOCK_SIZE; /* 64kByte */
+    mtd_device.ops = &swm_mtd_ops;
 
     /* initialize mutex */
     if (rt_mutex_init(&flash_lock, "nor", RT_IPC_FLAG_PRIO) != RT_EOK)
@@ -101,13 +106,13 @@ int rt_hw_norflash_init(void)
         rt_kprintf("init sd lock mutex failed\n");
         return -RT_ERROR;
     }
-    mtd.block_start = 0;
-    mtd.block_end = BLOCK_COUNTER;
+    mtd_device.block_start = 0;
+    mtd_device.block_end = BLOCK_COUNTER;
 
     /* register MTD device */
-    rt_mtd_nor_register_device("nor", &mtd);
+    rt_mtd_nor_register_device("nor", &mtd_device);
     return RT_EOK;
 }
-INIT_DEVICE_EXPORT(rt_hw_norflash_init);
+INIT_DEVICE_EXPORT(swm_norflash_init);
 
 #endif /* BSP_USING_NOR_FLASH */

bsp/swm320/drivers/drv_nor_flash.h → bsp/synwit/swm320/drivers/drv_nor_flash.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,10 +14,6 @@
 
 #include "board.h"
 
-#define BLOCK_SIZE (64 * 1024)
-#define FLASH_SIZE (BSP_NOR_FLASH_SIZE)
-#define BLOCK_COUNTER (FLASH_SIZE / BLOCK_SIZE)
-
-int rt_hw_norflash_init(void);
+int swm_norflash_init(void);
 
 #endif

bsp/synwit/swm320/drivers/drv_pwm.c

@@ -0,0 +1,382 @@
+/*
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          format file
+ */
+
+#include "drv_pwm.h"
+
+#ifdef RT_USING_PWM
+#ifdef BSP_USING_PWM
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.pwm"
+#include <drv_log.h>
+
+#if !defined(BSP_USING_PWM0) && !defined(BSP_USING_PWM1) && !defined(BSP_USING_PWM2) && !defined(BSP_USING_PWM3) && !defined(BSP_USING_PWM4) && !defined(BSP_USING_PWM5)
+#error "Please define at least one BSP_USING_PWMx"
+/* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */
+#endif
+
+#define MIN_PERIOD 2
+#define MIN_PULSE 1
+
+#ifdef BSP_USING_PWM0
+#ifndef PWM0_CFG
+#define PWM0_CFG                                \
+    {                                           \
+        .name = "pwm0",                         \
+        .PWMx = PWM0,                           \
+        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
+        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
+        .pwm_initstruct.cycleA = 10000,         \
+        .pwm_initstruct.hdutyA = 5000,          \
+        .pwm_initstruct.initLevelA = 1,         \
+        .pwm_initstruct.cycleB = 10000,         \
+        .pwm_initstruct.hdutyB = 5000,          \
+        .pwm_initstruct.initLevelB = 1,         \
+        .pwm_initstruct.HEndAIEn = 0,           \
+        .pwm_initstruct.NCycleAIEn = 0,         \
+        .pwm_initstruct.HEndBIEn = 0,           \
+        .pwm_initstruct.NCycleBIEn = 0,         \
+    }
+#endif /* PWM0_CFG */
+#endif /* BSP_USING_PWM0 */
+
+#ifdef BSP_USING_PWM1
+#ifndef PWM1_CFG
+#define PWM1_CFG                                \
+    {                                           \
+        .name = "pwm1",                         \
+        .PWMx = PWM1,                           \
+        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
+        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
+        .pwm_initstruct.cycleA = 10000,         \
+        .pwm_initstruct.hdutyA = 5000,          \
+        .pwm_initstruct.initLevelA = 1,         \
+        .pwm_initstruct.cycleB = 10000,         \
+        .pwm_initstruct.hdutyB = 5000,          \
+        .pwm_initstruct.initLevelB = 1,         \
+        .pwm_initstruct.HEndAIEn = 0,           \
+        .pwm_initstruct.NCycleAIEn = 0,         \
+        .pwm_initstruct.HEndBIEn = 0,           \
+        .pwm_initstruct.NCycleBIEn = 0,         \
+    }
+#endif /* PWM1_CFG */
+#endif /* BSP_USING_PWM1 */
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CFG
+#define PWM2_CFG                                \
+    {                                           \
+        .name = "pwm2",                         \
+        .PWMx = PWM2,                           \
+        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
+        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
+        .pwm_initstruct.cycleA = 10000,         \
+        .pwm_initstruct.hdutyA = 5000,          \
+        .pwm_initstruct.initLevelA = 1,         \
+        .pwm_initstruct.cycleB = 10000,         \
+        .pwm_initstruct.hdutyB = 5000,          \
+        .pwm_initstruct.initLevelB = 1,         \
+        .pwm_initstruct.HEndAIEn = 0,           \
+        .pwm_initstruct.NCycleAIEn = 0,         \
+        .pwm_initstruct.HEndBIEn = 0,           \
+        .pwm_initstruct.NCycleBIEn = 0,         \
+    }
+#endif /* PWM2_CFG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CFG
+#define PWM3_CFG                                \
+    {                                           \
+        .name = "pwm3",                         \
+        .PWMx = PWM3,                           \
+        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
+        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
+        .pwm_initstruct.cycleA = 10000,         \
+        .pwm_initstruct.hdutyA = 5000,          \
+        .pwm_initstruct.initLevelA = 1,         \
+        .pwm_initstruct.cycleB = 10000,         \
+        .pwm_initstruct.hdutyB = 5000,          \
+        .pwm_initstruct.initLevelB = 1,         \
+        .pwm_initstruct.HEndAIEn = 0,           \
+        .pwm_initstruct.NCycleAIEn = 0,         \
+        .pwm_initstruct.HEndBIEn = 0,           \
+        .pwm_initstruct.NCycleBIEn = 0,         \
+    }
+#endif /* PWM3_CFG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CFG
+#define PWM4_CFG                                \
+    {                                           \
+        .name = "pwm4",                         \
+        .PWMx = PWM4,                           \
+        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
+        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
+        .pwm_initstruct.cycleA = 10000,         \
+        .pwm_initstruct.hdutyA = 5000,          \
+        .pwm_initstruct.initLevelA = 1,         \
+        .pwm_initstruct.cycleB = 10000,         \
+        .pwm_initstruct.hdutyB = 5000,          \
+        .pwm_initstruct.initLevelB = 1,         \
+        .pwm_initstruct.HEndAIEn = 0,           \
+        .pwm_initstruct.NCycleAIEn = 0,         \
+        .pwm_initstruct.HEndBIEn = 0,           \
+        .pwm_initstruct.NCycleBIEn = 0,         \
+    }
+#endif /* PWM4_CFG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CFG
+#define PWM5_CFG                                \
+    {                                           \
+        .name = "pwm5",                         \
+        .PWMx = PWM5,                           \
+        .pwm_initstruct.clk_div = PWM_CLKDIV_8, \
+        .pwm_initstruct.mode = PWM_MODE_INDEP,  \
+        .pwm_initstruct.cycleA = 10000,         \
+        .pwm_initstruct.hdutyA = 5000,          \
+        .pwm_initstruct.initLevelA = 1,         \
+        .pwm_initstruct.cycleB = 10000,         \
+        .pwm_initstruct.hdutyB = 5000,          \
+        .pwm_initstruct.initLevelB = 1,         \
+        .pwm_initstruct.HEndAIEn = 0,           \
+        .pwm_initstruct.NCycleAIEn = 0,         \
+        .pwm_initstruct.HEndBIEn = 0,           \
+        .pwm_initstruct.NCycleBIEn = 0,         \
+    }
+#endif /* PWM5_CFG */
+#endif /* BSP_USING_PWM5 */
+
+struct swm_pwm_cfg
+{
+    const char *name;
+    PWM_TypeDef *PWMx;
+    PWM_InitStructure pwm_initstruct;
+};
+
+struct swm_pwm_device
+{
+    struct swm_pwm_cfg *pwm_cfg;
+    struct rt_device_pwm pwm_device;
+};
+
+static struct swm_pwm_cfg swm_pwm_cfg[] =
+    {
+#ifdef BSP_USING_PWM0
+        PWM0_CFG,
+#endif
+#ifdef BSP_USING_PWM1
+        PWM1_CFG,
+#endif
+#ifdef BSP_USING_PWM2
+        PWM2_CFG,
+#endif
+#ifdef BSP_USING_PWM3
+        PWM3_CFG,
+#endif
+#ifdef BSP_USING_PWM4
+        PWM4_CFG,
+#endif
+#ifdef BSP_USING_PWM5
+        PWM5_CFG,
+#endif
+};
+
+static struct swm_pwm_device pwm_obj[sizeof(swm_pwm_cfg) / sizeof(swm_pwm_cfg[0])] = {0};
+
+static rt_err_t swm_pwm_enable(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration, rt_bool_t enable)
+{
+    struct swm_pwm_cfg *pwm_cfg = RT_NULL;
+    RT_ASSERT(pwm_device != RT_NULL);
+    pwm_cfg = pwm_device->parent.user_data;
+
+    if (!enable)
+    {
+        if (PWM_CH_A == configuration->channel)
+        {
+            PWM_Stop(pwm_cfg->PWMx, 1, 0);
+        }
+        if (PWM_CH_B == configuration->channel)
+        {
+            PWM_Stop(pwm_cfg->PWMx, 0, 1);
+        }
+    }
+    else
+    {
+        if (PWM_CH_A == configuration->channel)
+        {
+            PWM_Start(pwm_cfg->PWMx, 1, 0);
+        }
+        if (PWM_CH_B == configuration->channel)
+        {
+            PWM_Start(pwm_cfg->PWMx, 0, 1);
+        }
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t swm_pwm_get(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration)
+{
+    rt_uint64_t tim_clock;
+    tim_clock = SystemCoreClock / 8;
+
+    struct swm_pwm_cfg *pwm_cfg = RT_NULL;
+    RT_ASSERT(pwm_device != RT_NULL);
+    pwm_cfg = pwm_device->parent.user_data;
+
+    /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
+    tim_clock /= 1000000UL;
+    configuration->period = PWM_GetCycle(pwm_cfg->PWMx, configuration->channel) * 1000UL / tim_clock;
+    configuration->pulse = PWM_GetHDuty(pwm_cfg->PWMx, configuration->channel) * 1000UL / tim_clock;
+
+    return RT_EOK;
+}
+
+static rt_err_t swm_pwm_set(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration)
+{
+    rt_uint32_t period, pulse;
+    rt_uint64_t tim_clock;
+    tim_clock = SystemCoreClock / 8;
+
+    struct swm_pwm_cfg *pwm_cfg = RT_NULL;
+    RT_ASSERT(pwm_device != RT_NULL);
+    pwm_cfg = pwm_device->parent.user_data;
+
+    /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
+    /* when SystemCoreClock = 120MHz, configuration->period max 4.369ms */
+    /* when SystemCoreClock = 20MHz, configuration->period max 26.214ms */
+    tim_clock /= 1000000UL;
+    period = (unsigned long long)configuration->period * tim_clock / 1000ULL;
+    pulse = (unsigned long long)configuration->pulse * tim_clock / 1000ULL;
+    if (period < MIN_PERIOD)
+    {
+        period = MIN_PERIOD;
+    }
+    if (pulse < MIN_PULSE)
+    {
+        pulse = MIN_PULSE;
+    }
+    PWM_SetCycle(pwm_cfg->PWMx, configuration->channel, period);
+    PWM_SetHDuty(pwm_cfg->PWMx, configuration->channel, pulse);
+
+    return RT_EOK;
+}
+
+static rt_err_t swm_pwm_control(struct rt_device_pwm *pwm_device, int cmd, void *arg)
+{
+    RT_ASSERT(pwm_device != RT_NULL);
+
+    struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
+
+    switch (cmd)
+    {
+    case PWM_CMD_ENABLE:
+        return swm_pwm_enable(pwm_device, configuration, RT_TRUE);
+    case PWM_CMD_DISABLE:
+        return swm_pwm_enable(pwm_device, configuration, RT_FALSE);
+    case PWM_CMD_SET:
+        return swm_pwm_set(pwm_device, configuration);
+    case PWM_CMD_GET:
+        return swm_pwm_get(pwm_device, configuration);
+    default:
+        return RT_EINVAL;
+    }
+}
+
+static struct rt_pwm_ops pwm_ops =
+    {
+        swm_pwm_control};
+
+int swm_pwm_init(void)
+{
+    int i = 0;
+    int result = RT_EOK;
+
+    for (i = 0; i < sizeof(swm_pwm_cfg) / sizeof(swm_pwm_cfg[0]); i++)
+    {
+        pwm_obj[i].pwm_cfg = &swm_pwm_cfg[i];
+
+        if (pwm_obj[i].pwm_cfg->PWMx == PWM0)
+        {
+#ifdef BSP_USING_PWM0A
+            PORT_Init(PORTC, PIN2, FUNMUX0_PWM0A_OUT, 0);
+#endif
+#ifdef BSP_USING_PWM0B
+            PORT_Init(PORTC, PIN4, FUNMUX0_PWM0B_OUT, 0);
+#endif
+        }
+        else if (pwm_obj[i].pwm_cfg->PWMx == PWM1)
+        {
+#ifdef BSP_USING_PWM1A
+            PORT_Init(PORTC, PIN3, FUNMUX1_PWM1A_OUT, 0);
+#endif
+#ifdef BSP_USING_PWM1B
+            PORT_Init(PORTC, PIN5, FUNMUX1_PWM1B_OUT, 0);
+#endif
+        }
+        else if (pwm_obj[i].pwm_cfg->PWMx == PWM2)
+        {
+#ifdef BSP_USING_PWM2A
+            PORT_Init(PORTN, PIN4, FUNMUX0_PWM2A_OUT, 0);
+#endif
+#ifdef BSP_USING_PWM2B
+            PORT_Init(PORTN, PIN6, FUNMUX0_PWM2B_OUT, 0);
+#endif
+        }
+        else if (pwm_obj[i].pwm_cfg->PWMx == PWM3)
+        {
+#ifdef BSP_USING_PWM3A
+            PORT_Init(PORTN, PIN3, FUNMUX1_PWM3A_OUT, 0);
+#endif
+#ifdef BSP_USING_PWM3B
+            PORT_Init(PORTN, PIN5, FUNMUX1_PWM3B_OUT, 0);
+#endif
+        }
+        else if (pwm_obj[i].pwm_cfg->PWMx == PWM4)
+        {
+#ifdef BSP_USING_PWM4A
+            PORT_Init(PORTN, PIN8, FUNMUX0_PWM4A_OUT, 0);
+#endif
+#ifdef BSP_USING_PWM4B
+            PORT_Init(PORTN, PIN10, FUNMUX0_PWM4B_OUT, 0);
+#endif
+        }
+        else if (pwm_obj[i].pwm_cfg->PWMx == PWM5)
+        {
+#ifdef BSP_USING_PWM5A
+            PORT_Init(PORTN, PIN7, FUNMUX1_PWM5A_OUT, 0);
+#endif
+#ifdef BSP_USING_PWM5B
+            PORT_Init(PORTN, PIN9, FUNMUX1_PWM5B_OUT, 0);
+#endif
+        }
+
+        PWM_Init(pwm_obj[i].pwm_cfg->PWMx, &(pwm_obj[i].pwm_cfg->pwm_initstruct));
+        result = rt_device_pwm_register(&pwm_obj[i].pwm_device, pwm_obj[i].pwm_cfg->name, &pwm_ops, pwm_obj[i].pwm_cfg);
+        if(result != RT_EOK)
+        {
+            LOG_E("%s register fail.", pwm_obj[i].pwm_cfg->name);
+        }
+        else
+        {
+            LOG_D("%s register success.", pwm_obj[i].pwm_cfg->name);
+        }
+    }
+    return result;
+}
+INIT_DEVICE_EXPORT(swm_pwm_init);
+
+#endif /* BSP_USING_PWM */
+#endif /* RT_USING_PWM */

bsp/synwit/swm320/drivers/drv_pwm.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          rewrite
+ */
+
+#ifndef __DRV_PWM_H__
+#define __DRV_PWM_H__
+
+#include "board.h"
+
+int swm_pwm_init(void);
+
+#endif /* __DRV_PWM_H__ */

bsp/swm320/drivers/drv_rtc.c → bsp/synwit/swm320/drivers/drv_rtc.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -10,7 +10,6 @@
  */
 
 #include "drv_rtc.h"
-#include <sys/time.h>
 
 #ifdef RT_USING_RTC
 #ifdef BSP_USING_RTC
@@ -19,6 +18,8 @@
 #define LOG_TAG "drv.rtc"
 #include <drv_log.h>
 
+static rt_rtc_dev_t swm_rtc_device;
+
 static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date)
 {
     uint32_t i, cnt = 0;
@@ -54,8 +55,8 @@ static time_t swm_get_rtc_time_stamp(void)
     tm_new.tm_min = get_datetime.Minute;
     tm_new.tm_hour = get_datetime.Hour;
     tm_new.tm_mday = get_datetime.Date;
-    tm_new.tm_mon = get_datetime.Month;
-    tm_new.tm_year = get_datetime.Year;
+    tm_new.tm_mon = get_datetime.Month - 1;
+    tm_new.tm_year = get_datetime.Year - 1900;
 
     LOG_D("get rtc time.");
     return mktime(&tm_new);
@@ -70,8 +71,8 @@ static rt_err_t swm_set_rtc_time_stamp(time_t time_stamp)
     set_datetime.Minute = now.tm_min;
     set_datetime.Hour = now.tm_hour;
     set_datetime.Date = now.tm_mday;
-    set_datetime.Month = now.tm_mon;
-    set_datetime.Year = now.tm_year;
+    set_datetime.Month = now.tm_mon + 1;
+    set_datetime.Year = now.tm_year + 1900;
     // set_datetime.Day = now.tm_wday;
 
     RTC_Stop(RTC);
@@ -92,73 +93,75 @@ static rt_err_t swm_set_rtc_time_stamp(time_t time_stamp)
     return RT_EOK;
 }
 
-static rt_err_t swm_rtc_init(void)
+static rt_err_t swm_rtc_configure(void)
 {
     RTC_InitStructure rtc_initstruct;
 
     rtc_initstruct.Year = 2020;
-    rtc_initstruct.Month = 6;
-    rtc_initstruct.Date = 8;
-    rtc_initstruct.Hour = 12;
-    rtc_initstruct.Minute = 0;
-    rtc_initstruct.Second = 0;
+    rtc_initstruct.Month = 2;
+    rtc_initstruct.Date = 28;
+    rtc_initstruct.Hour = 23;
+    rtc_initstruct.Minute = 59;
+    rtc_initstruct.Second = 55;
     rtc_initstruct.SecondIEn = 0;
     rtc_initstruct.MinuteIEn = 0;
     RTC_Init(RTC, &rtc_initstruct);
     RTC_Start(RTC);
-
+    
     return RT_EOK;
 }
 
-static rt_err_t swm_rtc_get_secs(void *args)
+static rt_err_t swm_rtc_get_secs(time_t *args)
 {
-    *(rt_uint32_t *)args = swm_get_rtc_time_stamp();
-    LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
+    *args = swm_get_rtc_time_stamp();
+    LOG_D("RTC: get rtc_time %x\n", *args);
 
     return RT_EOK;
 }
 
-static rt_err_t swm_rtc_set_secs(void *args)
+static rt_err_t swm_rtc_set_secs(time_t *args)
 {
     rt_err_t result = RT_EOK;
 
-    if (swm_set_rtc_time_stamp(*(rt_uint32_t *)args))
+    if (swm_set_rtc_time_stamp(*args))
     {
         result = -RT_ERROR;
     }
-    LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
+    LOG_D("RTC: set rtc_time %x\n", *args);
 
     return result;
 }
 
 static const struct rt_rtc_ops swm_rtc_ops =
 {
-    swm_rtc_init,
-    swm_rtc_get_secs,
-    swm_rtc_set_secs,
+    .init = swm_rtc_configure,
+    .get_secs = swm_rtc_get_secs,
+    .set_secs = swm_rtc_set_secs,
     RT_NULL,
     RT_NULL,
     RT_NULL,
     RT_NULL,
 };
 
-static rt_rtc_dev_t swm_rtc_device;
-
-int rt_hw_rtc_init(void)
+int swm_rtc_init(void)
 {
     rt_err_t result;
 
+    swm_rtc_configure();
+    
     swm_rtc_device.ops = &swm_rtc_ops;
     result = rt_hw_rtc_register(&swm_rtc_device, "rtc", RT_DEVICE_FLAG_RDWR,RT_NULL);
     if (result != RT_EOK)
     {
         LOG_E("rtc register err code: %d", result);
-        return result;
     }
-    LOG_D("rtc init success");
-    return RT_EOK;
+    else
+    {
+        LOG_D("rtc register success.");
+    }
+    return result;
 }
-INIT_DEVICE_EXPORT(rt_hw_rtc_init);
+INIT_DEVICE_EXPORT(swm_rtc_init);
 
 #endif /* BSP_USING_RTC */
 #endif /* RT_USING_RTC */

bsp/swm320/drivers/drv_rtc.h → bsp/synwit/swm320/drivers/drv_rtc.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,6 +14,6 @@
 
 #include "board.h"
 
-int rt_hw_rtc_init(void);
+int swm_rtc_init(void);
 
 #endif /* __DRV_RTC_H__ */

bsp/swm320/drivers/drv_sdio.c → bsp/synwit/swm320/drivers/drv_sdio.c

@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2020-07-10     lik          first version
+ * 2021-07-01     lik          first version
  */
 
 #include "drv_sdio.h"
@@ -17,18 +17,44 @@
 #define LOG_TAG "drv.sdio"
 #include <drv_log.h>
 
+#define SDIO_BUFF_SIZE 4096
+#define SDIO_ALIGN_LEN 4
+
+#ifndef SDIO_MAX_FREQ
+#define SDIO_MAX_FREQ (30000000)
+#endif
+
+struct swm_sdio_pkg
+{
+    struct rt_mmcsd_cmd *cmd;
+    void *buff;
+    rt_uint32_t flag;
+};
+
+typedef rt_err_t (*sdio_txconfig)(struct swm_sdio_pkg *pkg, rt_uint32_t *buff, int size);
+typedef rt_err_t (*sdio_rxconfig)(struct swm_sdio_pkg *pkg, rt_uint32_t *buff, int size);
+typedef rt_uint32_t (*sdio_clk_get)(SDIO_TypeDef *swm_sdio);
+
+struct swm_sdio_des
+{
+    SDIO_TypeDef *swm_sdio;
+    sdio_txconfig txconfig;
+    sdio_rxconfig rxconfig;
+    sdio_clk_get clk_get;
+};
+
 static struct rt_mmcsd_host *host;
 
 #define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER)
 #define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex);
 
-struct rthw_sdio
+struct swm_sdio_device
 {
     struct rt_mmcsd_host *host;
     struct swm_sdio_des sdio_des;
     struct rt_event event;
     struct rt_mutex mutex;
-    struct sdio_pkg *pkg;
+    struct swm_sdio_pkg *pkg;
 };
 
 ALIGN(SDIO_ALIGN_LEN)
@@ -36,18 +62,18 @@ static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
 
 /**
   * @brief  This function wait sdio completed.
-  * @param  sdio  rthw_sdio
+  * @param  sdio  swm_sdio_device
   * @retval None
   */
-static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
+static void swm_sdio_wait_completed(struct swm_sdio_device *sdio)
 {
     rt_uint32_t status;
     struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd;
     struct rt_mmcsd_data *data = cmd->data;
-    SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio;
+    SDIO_TypeDef *swm_sdio = sdio->sdio_des.swm_sdio;
 
     if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
-                      rt_tick_from_millisecond(1000), &status) != RT_EOK)
+                      rt_tick_from_millisecond(2000), &status) != RT_EOK)
     {
         LOG_E("wait completed timeout");
         cmd->err = -RT_ETIMEOUT;
@@ -65,14 +91,15 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
     }
     else if (resp_type(cmd) == RESP_R2)
     {
-        cmd->resp[0] = (hw_sdio->RESP[3] << 8) + ((hw_sdio->RESP[2] >> 24) & 0xFF);
-        cmd->resp[1] = (hw_sdio->RESP[2] << 8) + ((hw_sdio->RESP[1] >> 24) & 0xFF);
-        cmd->resp[2] = (hw_sdio->RESP[1] << 8) + ((hw_sdio->RESP[0] >> 24) & 0xFF);
-        cmd->resp[3] = (hw_sdio->RESP[0] << 8) + 0x00;
+        LOG_D("R2");
+        cmd->resp[0] = (swm_sdio->RESP[3] << 8) + ((swm_sdio->RESP[2] >> 24) & 0xFF);
+        cmd->resp[1] = (swm_sdio->RESP[2] << 8) + ((swm_sdio->RESP[1] >> 24) & 0xFF);
+        cmd->resp[2] = (swm_sdio->RESP[1] << 8) + ((swm_sdio->RESP[0] >> 24) & 0xFF);
+        cmd->resp[3] = (swm_sdio->RESP[0] << 8) + 0x00;
     }
     else
     {
-        cmd->resp[0] = hw_sdio->RESP[0];
+        cmd->resp[0] = swm_sdio->RESP[0];
     }
 
     if (status & SDIO_IF_ERROR_Msk)
@@ -86,18 +113,27 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
             cmd->err = -RT_ERROR;
         }
 
+        if (status & SDIO_IF_CMDCRCERR_Msk)
+        {
+            SDIO->CR2 |= (1 << SDIO_CR2_RSTCMD_Pos);
+            data->err = -RT_ERROR;
+        }
+        
         if (status & SDIO_IF_CMDTIMEOUT_Msk)
         {
+            SDIO->CR2 |= (1 << SDIO_CR2_RSTCMD_Pos);
             cmd->err = -RT_ETIMEOUT;
         }
-
+        
         if (status & SDIO_IF_DATCRCERR_Msk)
         {
+            SDIO->CR2 |= (1 << SDIO_CR2_RSTDAT_Pos);
             data->err = -RT_ERROR;
         }
 
         if (status & SDIO_IF_DATTIMEOUT_Msk)
         {
+            SDIO->CR2 |= (1 << SDIO_CR2_RSTDAT_Pos);
             data->err = -RT_ETIMEOUT;
         }
 
@@ -107,8 +143,12 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
         }
         else
         {
-            LOG_D("err:0x%08x, %s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d",
+            LOG_D("err:0x%08x, %s%s%s%s%s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d",
                   status,
+                  status & SDIO_IF_CMDCRCERR_Msk  ? "CCRCFAIL "    : "",
+                  status & SDIO_IF_DATCRCERR_Msk  ? "DCRCFAIL "    : "",
+                  status & SDIO_IF_CMDTIMEOUT_Msk ? "CTIMEOUT "    : "",
+                  status & SDIO_IF_DATTIMEOUT_Msk ? "DTIMEOUT "    : "",
                   status == 0 ? "NULL" : "",
                   cmd->cmd_code,
                   cmd->arg,
@@ -126,11 +166,11 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
 
 /**
   * @brief  This function transfer data by dma.
-  * @param  sdio  rthw_sdio
+  * @param  sdio  swm_sdio_device
   * @param  pkg   sdio package
   * @retval None
   */
-static void rthw_sdio_transfer(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
+static void swm_sdio_transfer(struct swm_sdio_device *sdio, struct swm_sdio_pkg *pkg)
 {
     struct rt_mmcsd_data *data;
     int size;
@@ -138,21 +178,21 @@ static void rthw_sdio_transfer(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
 
     if ((RT_NULL == pkg) || (RT_NULL == sdio))
     {
-        LOG_E("rthw_sdio_transfer invalid args");
+        LOG_E("swm_sdio_transfer invalid args");
         return;
     }
 
     data = pkg->cmd->data;
     if (RT_NULL == data)
     {
-        LOG_E("rthw_sdio_transfer invalid args");
+        LOG_E("swm_sdio_transfer invalid args");
         return;
     }
 
     buff = pkg->buff;
     if (RT_NULL == buff)
     {
-        LOG_E("rthw_sdio_transfer invalid args");
+        LOG_E("swm_sdio_transfer invalid args");
         return;
     }
 
@@ -170,15 +210,15 @@ static void rthw_sdio_transfer(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
 
 /**
   * @brief  This function send command.
-  * @param  sdio  rthw_sdio
+  * @param  sdio  swm_sdio_device
   * @param  pkg   sdio package
   * @retval None
   */
-static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
+static void swm_sdio_send_command(struct swm_sdio_device *sdio, struct swm_sdio_pkg *pkg)
 {
     struct rt_mmcsd_cmd *cmd = pkg->cmd;
     struct rt_mmcsd_data *data = cmd->data;
-    SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio;
+    SDIO_TypeDef *swm_sdio = sdio->sdio_des.swm_sdio;
     rt_uint32_t reg_cmd;
 
     /* save pkg */
@@ -219,7 +259,7 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
         rt_uint32_t dir = 0;
         dir = (data->flags & DATA_DIR_READ) ? 1 : 0;
 
-        hw_sdio->BLK = (data->blks << SDIO_BLK_COUNT_Pos) | (data->blksize << SDIO_BLK_SIZE_Pos);
+        swm_sdio->BLK = (data->blks << SDIO_BLK_COUNT_Pos) | (data->blksize << SDIO_BLK_SIZE_Pos);
 
         reg_cmd |= (1 << SDIO_CMD_HAVEDATA_Pos) |
                    (dir << SDIO_CMD_DIRREAD_Pos) |
@@ -232,21 +272,18 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
         reg_cmd |= (0 << SDIO_CMD_HAVEDATA_Pos);
     }
 
-    if (cmd->cmd_code != SD_IO_SEND_OP_COND)
-    {
-        /* send cmd */
-        hw_sdio->ARG = cmd->arg;
-        hw_sdio->CMD = reg_cmd;
-    }
+    /* send cmd */
+    swm_sdio->ARG = cmd->arg;
+    swm_sdio->CMD = reg_cmd;
 
     /* transfer config */
     if (data != RT_NULL)
     {
-        rthw_sdio_transfer(sdio, pkg);
+        swm_sdio_transfer(sdio, pkg);
     }
 
     /* wait completed */
-    rthw_sdio_wait_completed(sdio);
+    swm_sdio_wait_completed(sdio);
 
     /* clear pkg */
     sdio->pkg = RT_NULL;
@@ -254,14 +291,14 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
 
 /**
   * @brief  This function send sdio request.
-  * @param  sdio  rthw_sdio
+  * @param  sdio  swm_sdio_device
   * @param  req   request
   * @retval None
   */
-static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
+static void swm_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
 {
-    struct sdio_pkg pkg;
-    struct rthw_sdio *sdio = host->private_data;
+    struct swm_sdio_pkg pkg;
+    struct swm_sdio_device *sdio = host->private_data;
     struct rt_mmcsd_data *data;
 
     RTHW_SDIO_LOCK(sdio);
@@ -289,7 +326,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
             }
         }
 
-        rthw_sdio_send_command(sdio, &pkg);
+        swm_sdio_send_command(sdio, &pkg);
 
         if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)))
         {
@@ -301,7 +338,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
     {
         rt_memset(&pkg, 0, sizeof(pkg));
         pkg.cmd = req->stop;
-        rthw_sdio_send_command(sdio, &pkg);
+        swm_sdio_send_command(sdio, &pkg);
     }
 
     RTHW_SDIO_UNLOCK(sdio);
@@ -315,14 +352,14 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
   * @param  io_cfg  rt_mmcsd_io_cfg
   * @retval None
   */
-static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
+static void swm_sdio_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
 {
     rt_uint32_t clkcr, div, clk_src;
     rt_uint32_t clk = io_cfg->clock;
-    struct rthw_sdio *sdio = host->private_data;
-    SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio;
+    struct swm_sdio_device *sdio = host->private_data;
+    SDIO_TypeDef *swm_sdio = sdio->sdio_des.swm_sdio;
 
-    clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.hw_sdio);
+    clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.swm_sdio);
     if (clk_src < 400 * 1000)
     {
         LOG_E("The clock rate is too low! rata:%d", clk_src);
@@ -349,31 +386,31 @@ static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *
 
     RTHW_SDIO_LOCK(sdio);
 
-    hw_sdio->CR1 = (1 << SDIO_CR1_CDSRC_Pos) | (7 << SDIO_CR1_VOLT_Pos);
+    swm_sdio->CR1 = (1 << SDIO_CR1_CDSRC_Pos) | (7 << SDIO_CR1_VOLT_Pos);
     if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8)
     {
-        hw_sdio->CR1 |= (1 << SDIO_CR1_8BIT_Pos);
+        swm_sdio->CR1 |= (1 << SDIO_CR1_8BIT_Pos);
     }
     else
     {
-        hw_sdio->CR1 &= ~SDIO_CR1_8BIT_Msk;
+        swm_sdio->CR1 &= ~SDIO_CR1_8BIT_Msk;
         if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
         {
-            hw_sdio->CR1 |= (1 << SDIO_CR1_4BIT_Pos);
+            swm_sdio->CR1 |= (1 << SDIO_CR1_4BIT_Pos);
         }
         else
         {
-            hw_sdio->CR1 &= ~SDIO_CR1_4BIT_Msk;
+            swm_sdio->CR1 &= ~SDIO_CR1_4BIT_Msk;
         }
     }
     switch (io_cfg->power_mode)
     {
     case MMCSD_POWER_OFF:
-        hw_sdio->CR1 &= ~SDIO_CR1_PWRON_Msk;
+        swm_sdio->CR1 &= ~SDIO_CR1_PWRON_Msk;
         break;
     case MMCSD_POWER_UP:
     case MMCSD_POWER_ON:
-        hw_sdio->CR1 |= (1 << SDIO_CR1_PWRON_Pos);
+        swm_sdio->CR1 |= (1 << SDIO_CR1_PWRON_Pos);
         break;
     default:
         LOG_W("unknown power_mode %d", io_cfg->power_mode);
@@ -423,7 +460,7 @@ static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *
   * @param  host    rt_mmcsd_host
   * @retval 0x01
   */
-static rt_int32_t rthw_sdio_delect(struct rt_mmcsd_host *host)
+static rt_int32_t swm_sdio_get_card_status(struct rt_mmcsd_host *host)
 {
     LOG_D("try to detect device");
     return 0x01;
@@ -435,37 +472,37 @@ static rt_int32_t rthw_sdio_delect(struct rt_mmcsd_host *host)
   * @param  enable
   * @retval None
   */
-void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable)
+void swm_sdio_enable_irq(struct rt_mmcsd_host *host, rt_int32_t enable)
 {
-    struct rthw_sdio *sdio = host->private_data;
-    SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio;
+    struct swm_sdio_device *sdio = host->private_data;
+    SDIO_TypeDef *swm_sdio = sdio->sdio_des.swm_sdio;
 
     if (enable)
     {
         LOG_D("enable sdio irq");
-        hw_sdio->IFE = 0xFFFFFFFF;
-        hw_sdio->IE = 0xFFFF000F;
+        swm_sdio->IM = 0xFFFFFFFF;
+        swm_sdio->IE = 0xFFFF000F;
     }
     else
     {
         LOG_D("disable sdio irq");
-        hw_sdio->IFE &= ~0xFFFFFFFF;
-        hw_sdio->IE &= ~0xFFFFFFFF;
+        swm_sdio->IM &= ~0xFFFFFFFF;
+        swm_sdio->IE &= ~0xFFFFFFFF;
     }
 }
 
 static const struct rt_mmcsd_host_ops swm_sdio_ops =
     {
-        rthw_sdio_request,
-        rthw_sdio_iocfg,
-        rthw_sdio_delect,
-        rthw_sdio_irq_update,
+        .request = swm_sdio_request,
+        .set_iocfg = swm_sdio_set_iocfg,
+        .get_card_status = swm_sdio_get_card_status,
+        .enable_sdio_irq = swm_sdio_enable_irq,
 };
 
-struct rt_mmcsd_host *sdio_host_create(struct swm_sdio_des *sdio_des)
+struct rt_mmcsd_host *swm_sdio_host_create(struct swm_sdio_des *sdio_des)
 {
     struct rt_mmcsd_host *host;
-    struct rthw_sdio *sdio = RT_NULL;
+    struct swm_sdio_device *sdio = RT_NULL;
 
     if ((sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL))
     {
@@ -476,13 +513,13 @@ struct rt_mmcsd_host *sdio_host_create(struct swm_sdio_des *sdio_des)
         return RT_NULL;
     }
 
-    sdio = rt_malloc(sizeof(struct rthw_sdio));
+    sdio = rt_malloc(sizeof(struct swm_sdio_device));
     if (sdio == RT_NULL)
     {
-        LOG_E("L:%d F:%s malloc rthw_sdio fail");
+        LOG_E("L:%d F:%s malloc swm_sdio_device fail");
         return RT_NULL;
     }
-    rt_memset(sdio, 0, sizeof(struct rthw_sdio));
+    rt_memset(sdio, 0, sizeof(struct swm_sdio_device));
 
     host = mmcsd_alloc_host();
     if (host == RT_NULL)
@@ -495,7 +532,7 @@ struct rt_mmcsd_host *sdio_host_create(struct swm_sdio_des *sdio_des)
     rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct swm_sdio_des));
 
     rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO);
-    rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_PRIO);
+    rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO);
 
     /* set host defautl attributes */
     host->ops = &swm_sdio_ops;
@@ -516,7 +553,7 @@ struct rt_mmcsd_host *sdio_host_create(struct swm_sdio_des *sdio_des)
     sdio->host = host;
     host->private_data = sdio;
 
-    rthw_sdio_irq_update(host, 1);
+    swm_sdio_enable_irq(host, 1);
 
     /* ready to change */
     mmcsd_change(host);
@@ -524,13 +561,13 @@ struct rt_mmcsd_host *sdio_host_create(struct swm_sdio_des *sdio_des)
     return host;
 }
 
-static rt_uint32_t swm_sdio_clock_get(SDIO_TypeDef *hw_sdio)
+static rt_uint32_t swm_sdio_clock_get(SDIO_TypeDef *swm_sdio)
 {
     uint32_t prediv = ((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos);
     return (SystemCoreClock / (1 << prediv));
 }
 
-static rt_err_t swm_sdio_rxconfig(struct sdio_pkg *pkg, rt_uint32_t *buff, int size)
+static rt_err_t swm_sdio_rxconfig(struct swm_sdio_pkg *pkg, rt_uint32_t *buff, int size)
 {
     struct rt_mmcsd_cmd *cmd = pkg->cmd;
     struct rt_mmcsd_data *data = cmd->data;
@@ -549,7 +586,7 @@ static rt_err_t swm_sdio_rxconfig(struct sdio_pkg *pkg, rt_uint32_t *buff, int s
     return RT_EOK;
 }
 
-static rt_err_t swm_sdio_txconfig(struct sdio_pkg *pkg, rt_uint32_t *buff, int size)
+static rt_err_t swm_sdio_txconfig(struct swm_sdio_pkg *pkg, rt_uint32_t *buff, int size)
 {
     struct rt_mmcsd_cmd *cmd = pkg->cmd;
     struct rt_mmcsd_data *data = cmd->data;
@@ -561,7 +598,9 @@ static rt_err_t swm_sdio_txconfig(struct sdio_pkg *pkg, rt_uint32_t *buff, int s
             __NOP();
         SDIO->IF = SDIO_IF_BUFWRRDY_Msk;
         for (uint32_t j = 0; j < data->blksize / 4; j++)
+        {
             SDIO->DATA = buff[offset + j];
+        }
     }
     return RT_EOK;
 }
@@ -571,23 +610,23 @@ static rt_err_t swm_sdio_txconfig(struct sdio_pkg *pkg, rt_uint32_t *buff, int s
   * @param  host  rt_mmcsd_host
   * @retval None
   */
-void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
+static void swm_sdio_irq_process(struct rt_mmcsd_host *host)
 {
     int complete = 0;
-    struct rthw_sdio *sdio = host->private_data;
-    SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio;
-    rt_uint32_t intstatus = hw_sdio->IF;
+    struct swm_sdio_device *sdio = host->private_data;
+    SDIO_TypeDef *swm_sdio = sdio->sdio_des.swm_sdio;
+    rt_uint32_t intstatus = swm_sdio->IF;
 
     if (intstatus & SDIO_IF_ERROR_Msk)
     {
-        hw_sdio->IF = 0xFFFFFFFF;
+        swm_sdio->IF = 0xFFFFFFFF;
         complete = 1;
     }
     else
     {
         if (intstatus & SDIO_IF_CMDDONE_Msk)
         {
-            hw_sdio->IF = SDIO_IF_CMDDONE_Msk;
+            swm_sdio->IF = SDIO_IF_CMDDONE_Msk;
             if (sdio->pkg != RT_NULL)
             {
                 if (!sdio->pkg->cmd->data)
@@ -599,7 +638,7 @@ void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
 
         if (intstatus & SDIO_IF_TRXDONE_Msk)
         {
-            hw_sdio->IF = SDIO_IF_TRXDONE_Msk;
+            swm_sdio->IF = SDIO_IF_TRXDONE_Msk;
             complete = 1;
         }
     }
@@ -615,13 +654,14 @@ void SDIO_Handler(void)
     /* enter interrupt */
     rt_interrupt_enter();
     /* Process All SDIO Interrupt Sources */
-    rthw_sdio_irq_process(host);
+    swm_sdio_irq_process(host);
     /* leave interrupt */
     rt_interrupt_leave();
 }
 
-int rt_hw_sdio_init(void)
+int swm_sdio_init(void)
 {
+    int result = RT_EOK;
     struct swm_sdio_des sdio_des;
 
 #if 1
@@ -652,19 +692,24 @@ int rt_hw_sdio_init(void)
 
     NVIC_EnableIRQ(SDIO_IRQn);
     sdio_des.clk_get = swm_sdio_clock_get;
-    sdio_des.hw_sdio = SDIO;
+    sdio_des.swm_sdio = SDIO;
     sdio_des.rxconfig = swm_sdio_rxconfig;
     sdio_des.txconfig = swm_sdio_txconfig;
 
-    host = sdio_host_create(&sdio_des);
+    host = swm_sdio_host_create(&sdio_des);
     if (host == RT_NULL)
     {
-        LOG_E("host create fail");
-        return -1;
+        LOG_E("host create fail.");
+        result = -1;
+    }
+    else
+    {
+        LOG_D("host create success.");
+        result = 0;
     }
-    return 0;
+    return result;
 }
-INIT_DEVICE_EXPORT(rt_hw_sdio_init);
+INIT_DEVICE_EXPORT(swm_sdio_init);
 
 #endif /* BSP_USING_SDIO */
 #endif /* RT_USING_SDIO */

bsp/swm341/drivers/drv_sdio.h → bsp/synwit/swm320/drivers/drv_sdio.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, Synwit Technology Co.,Ltd.
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/synwit/swm320/drivers/drv_soft_i2c.c

@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-31     ZYH          first version
+ * 2018-12-10     Zohar_Lee    format file
+ * 2020-07-10     lik          rewrite
+ */
+
+#include "drv_soft_i2c.h"
+
+#ifdef RT_USING_I2C
+#ifdef BSP_USING_I2C
+
+/***************************************************************
+*!!!!!!!!!!!!!!!!!!!!!!!!!!!!NOTICE!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+*In order to use swm drv_soft_i2c,you need to commented out
+line 114 (SDA_H(ops);) and line 167 (SDA_H(ops);) in i2c-bit-ops.c
+At the same time, add one line (SDA_L(ops);)after line 154 (SCL_L(ops);)
+in i2c-bit-ops.c
+***************************************************************/
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.i2c"
+#include <drv_log.h>
+
+#if !defined(BSP_USING_I2C0) && !defined(BSP_USING_I2C1)
+#error "Please define at least one BSP_USING_I2Cx"
+/* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */
+#endif
+
+#ifdef BSP_USING_I2C0
+#define I2C0_BUS_CFG             \
+    {                            \
+        .scl = BSP_I2C0_SCL_PIN, \
+        .sda = BSP_I2C0_SDA_PIN, \
+        .name = "i2c0",          \
+    }
+#endif
+
+#ifdef BSP_USING_I2C1
+#define I2C1_BUS_CFG             \
+    {                            \
+        .scl = BSP_I2C1_SCL_PIN, \
+        .sda = BSP_I2C1_SDA_PIN, \
+        .name = "i2c1",          \
+    }
+#endif
+
+/* swm config class */
+struct swm_soft_i2c_cfg
+{
+    rt_uint8_t scl;
+    rt_uint8_t sda;
+    const char *name;
+};
+/* swm i2c dirver class */
+struct swm_soft_i2c_device
+{
+    struct rt_i2c_bit_ops ops;
+    struct rt_i2c_bus_device i2c2_bus;
+};
+static const struct swm_soft_i2c_cfg swm_soft_i2c_cfg[] =
+    {
+#ifdef BSP_USING_I2C0
+        I2C0_BUS_CFG,
+#endif
+#ifdef BSP_USING_I2C1
+        I2C1_BUS_CFG,
+#endif
+};
+
+static struct swm_soft_i2c_device i2c_obj[sizeof(swm_soft_i2c_cfg) / sizeof(swm_soft_i2c_cfg[0])];
+
+/**
+ * This function initializes the i2c pin.
+ *
+ * @param swm i2c dirver class.
+ */
+static void swm_i2c_gpio_init(struct swm_soft_i2c_device *i2c)
+{
+    struct swm_soft_i2c_cfg *soft_i2c_cfg = (struct swm_soft_i2c_cfg *)i2c->ops.data;
+
+    rt_pin_mode(soft_i2c_cfg->scl, PIN_MODE_OUTPUT_OD);
+    rt_pin_mode(soft_i2c_cfg->sda, PIN_MODE_OUTPUT_OD);
+
+    rt_pin_write(soft_i2c_cfg->scl, PIN_HIGH);
+    rt_pin_write(soft_i2c_cfg->sda, PIN_HIGH);
+}
+
+/**
+ * This function sets the sda pin.
+ *
+ * @param swm config class.
+ * @param The sda pin state.
+ */
+static void swm_i2c_set_sda(void *data, rt_int32_t state)
+{
+    struct swm_soft_i2c_cfg *soft_i2c_cfg = (struct swm_soft_i2c_cfg *)data;
+    rt_pin_mode(soft_i2c_cfg->sda, PIN_MODE_OUTPUT_OD);
+    if (state)
+    {
+        rt_pin_write(soft_i2c_cfg->sda, PIN_HIGH);
+    }
+    else
+    {
+        rt_pin_write(soft_i2c_cfg->sda, PIN_LOW);
+    }
+}
+
+/**
+ * This function sets the scl pin.
+ *
+ * @param swm config class.
+ * @param The scl pin state.
+ */
+static void swm_i2c_set_scl(void *data, rt_int32_t state)
+{
+    struct swm_soft_i2c_cfg *soft_i2c_cfg = (struct swm_soft_i2c_cfg *)data;
+    rt_pin_mode(soft_i2c_cfg->scl, PIN_MODE_OUTPUT_OD);
+    if (state)
+    {
+        rt_pin_write(soft_i2c_cfg->scl, PIN_HIGH);
+    }
+    else
+    {
+        rt_pin_write(soft_i2c_cfg->scl, PIN_LOW);
+    }
+}
+
+/**
+ * This function gets the sda pin state.
+ *
+ * @param The sda pin state.
+ */
+static rt_int32_t swm_i2c_get_sda(void *data)
+{
+    struct swm_soft_i2c_cfg *soft_i2c_cfg = (struct swm_soft_i2c_cfg *)data;
+    rt_pin_mode(soft_i2c_cfg->sda, PIN_MODE_INPUT_PULLUP);
+    return rt_pin_read(soft_i2c_cfg->sda);
+}
+
+/**
+ * This function gets the scl pin state.
+ *
+ * @param The scl pin state.
+ */
+static rt_int32_t swm_i2c_get_scl(void *data)
+{
+    struct swm_soft_i2c_cfg *soft_i2c_cfg = (struct swm_soft_i2c_cfg *)data;
+    rt_pin_mode(soft_i2c_cfg->scl, PIN_MODE_INPUT_PULLUP);
+    return rt_pin_read(soft_i2c_cfg->scl);
+}
+
+/**
+ * The time delay function.
+ *
+ * @param microseconds.
+ */
+static void swm_i2c_udelay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1)
+    {
+        tnow = SysTick->VAL;
+        if (tnow != told)
+        {
+            if (tnow < told)
+            {
+                tcnt += told - tnow;
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
+static const struct rt_i2c_bit_ops swm_i2c_bit_ops =
+    {
+        .data = RT_NULL,
+        .set_sda = swm_i2c_set_sda,
+        .set_scl = swm_i2c_set_scl,
+        .get_sda = swm_i2c_get_sda,
+        .get_scl = swm_i2c_get_scl,
+        .udelay = swm_i2c_udelay,
+        .delay_us = 1,
+        .timeout = 100};
+
+/* I2C initialization function */
+int swm_i2c_init(void)
+{
+    rt_err_t result;
+
+    for (int i = 0; i < sizeof(i2c_obj) / sizeof(struct swm_soft_i2c_device); i++)
+    {
+        i2c_obj[i].ops = swm_i2c_bit_ops;
+        i2c_obj[i].ops.data = (void *)&swm_soft_i2c_cfg[i];
+        i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops;
+        swm_i2c_gpio_init(&i2c_obj[i]);
+        result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, swm_soft_i2c_cfg[i].name);
+        RT_ASSERT(result == RT_EOK);
+
+        LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
+              swm_soft_i2c_cfg[i].name,
+              swm_soft_i2c_cfg[i].scl,
+              swm_soft_i2c_cfg[i].sda);
+    }
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(swm_i2c_init);
+#endif /* BSP_USING_I2C */
+#endif /* RT_USING_I2C */

bsp/synwit/swm320/drivers/drv_soft_i2c.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          rewrite
+ */
+
+#ifndef __DRV_SOFT_I2C_H__
+#define __DRV_SOFT_I2C_H__
+
+#include "board.h"
+
+int swm_i2c_init(void);
+
+#endif /* __DRV_SOFT_I2C_H__ */

bsp/swm320/drivers/drv_spi.c → bsp/synwit/swm320/drivers/drv_spi.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -19,7 +19,71 @@
 #define LOG_TAG "drv.spi"
 #include <drv_log.h>
 
-static struct swm_spi_cfg spi_cfg[] =
+#if !defined(BSP_USING_SPI0) && !defined(BSP_USING_SPI1)
+#error "Please define at least one BSP_USING_SPIx"
+/* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */
+#endif
+
+struct swm_spi_cs
+{
+    GPIO_TypeDef *GPIOx;
+    uint32_t gpio_pin;
+};
+
+struct swm_spi_cfg
+{
+    const char *name;
+    SPI_TypeDef *SPIx;
+    SPI_InitStructure spi_initstruct;
+};
+
+/* swm spi dirver class */
+struct swm_spi_device
+{
+    struct swm_spi_cfg *spi_cfg;
+    struct rt_spi_configuration *configure;
+    struct rt_spi_bus spi_bus;
+};
+
+#ifdef BSP_USING_SPI0
+#ifndef SPI0_BUS_CONFIG
+#define SPI0_BUS_CONFIG                               \
+    {                                                 \
+        .name = "spi0",                               \
+        .SPIx = SPI0,                                 \
+        .spi_initstruct.clkDiv = SPI_CLKDIV_32,       \
+        .spi_initstruct.FrameFormat = SPI_FORMAT_SPI, \
+        .spi_initstruct.SampleEdge = SPI_SECOND_EDGE, \
+        .spi_initstruct.IdleLevel = SPI_HIGH_LEVEL,   \
+        .spi_initstruct.WordSize = 8,                 \
+        .spi_initstruct.Master = 1,                   \
+        .spi_initstruct.RXHFullIEn = 0,               \
+        .spi_initstruct.TXEmptyIEn = 0,               \
+        .spi_initstruct.TXCompleteIEn = 0,            \
+    }
+#endif /* SPI0_BUS_CONFIG */
+#endif /* BSP_USING_SPI0 */
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                               \
+    {                                                 \
+        .name = "spi1",                               \
+        .SPIx = SPI1,                                 \
+        .spi_initstruct.clkDiv = SPI_CLKDIV_32,       \
+        .spi_initstruct.FrameFormat = SPI_FORMAT_SPI, \
+        .spi_initstruct.SampleEdge = SPI_SECOND_EDGE, \
+        .spi_initstruct.IdleLevel = SPI_HIGH_LEVEL,   \
+        .spi_initstruct.WordSize = 8,                 \
+        .spi_initstruct.Master = 1,                   \
+        .spi_initstruct.RXHFullIEn = 0,               \
+        .spi_initstruct.TXEmptyIEn = 0,               \
+        .spi_initstruct.TXCompleteIEn = 0,            \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+
+static struct swm_spi_cfg swm_spi_cfg[] =
     {
 #ifdef BSP_USING_SPI0
         SPI0_BUS_CONFIG,
@@ -29,22 +93,25 @@ static struct swm_spi_cfg spi_cfg[] =
 #endif
 };
 
-static struct swm_spi spi_bus_drv[sizeof(spi_cfg) / sizeof(spi_cfg[0])] = {0};
+static struct swm_spi_device spi_bus_obj[sizeof(swm_spi_cfg) / sizeof(swm_spi_cfg[0])] = {0};
 
-static rt_err_t swm_spi_init(struct swm_spi *spi_drv, struct rt_spi_configuration *configure)
+static rt_err_t swm_spi_configure(struct rt_spi_device *device,
+                                  struct rt_spi_configuration *configure)
 {
-    RT_ASSERT(spi_drv != RT_NULL);
+    RT_ASSERT(device != RT_NULL);
     RT_ASSERT(configure != RT_NULL);
 
-    struct swm_spi_cfg *cfg = spi_drv->cfg;
+    struct swm_spi_device *spi_drv = rt_container_of(device->bus, struct swm_spi_device, spi_bus);
+    spi_drv->configure = configure;
+    struct swm_spi_cfg *spi_cfg = spi_drv->spi_cfg;
 
     if (configure->mode & RT_SPI_SLAVE)
     {
-        cfg->spi_initstruct.Master = 0;
+        spi_cfg->spi_initstruct.Master = 0;
     }
     else
     {
-        cfg->spi_initstruct.Master = 1;
+        spi_cfg->spi_initstruct.Master = 1;
     }
 
     if (configure->mode & RT_SPI_3WIRE)
@@ -54,11 +121,11 @@ static rt_err_t swm_spi_init(struct swm_spi *spi_drv, struct rt_spi_configuratio
 
     if (configure->data_width == 8)
     {
-        cfg->spi_initstruct.WordSize = 8;
+        spi_cfg->spi_initstruct.WordSize = 8;
     }
     else if (configure->data_width == 16)
     {
-        cfg->spi_initstruct.WordSize = 16;
+        spi_cfg->spi_initstruct.WordSize = 16;
     }
     else
     {
@@ -67,59 +134,59 @@ static rt_err_t swm_spi_init(struct swm_spi *spi_drv, struct rt_spi_configuratio
 
     if (configure->mode & RT_SPI_CPHA)
     {
-        cfg->spi_initstruct.SampleEdge = SPI_SECOND_EDGE;
+        spi_cfg->spi_initstruct.SampleEdge = SPI_SECOND_EDGE;
     }
     else
     {
-        cfg->spi_initstruct.SampleEdge = SPI_FIRST_EDGE;
+        spi_cfg->spi_initstruct.SampleEdge = SPI_FIRST_EDGE;
     }
 
     if (configure->mode & RT_SPI_CPOL)
     {
-        cfg->spi_initstruct.IdleLevel = SPI_HIGH_LEVEL;
+        spi_cfg->spi_initstruct.IdleLevel = SPI_HIGH_LEVEL;
     }
     else
     {
-        cfg->spi_initstruct.IdleLevel = SPI_LOW_LEVEL;
+        spi_cfg->spi_initstruct.IdleLevel = SPI_LOW_LEVEL;
     }
 
     if (configure->max_hz >= SystemCoreClock / 4)
     {
-        cfg->spi_initstruct.clkDiv = SPI_CLKDIV_4;
+        spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_4;
     }
     else if (configure->max_hz >= SystemCoreClock / 8)
     {
-        cfg->spi_initstruct.clkDiv = SPI_CLKDIV_8;
+        spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_8;
     }
     else if (configure->max_hz >= SystemCoreClock / 16)
     {
-        cfg->spi_initstruct.clkDiv = SPI_CLKDIV_16;
+        spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_16;
     }
     else if (configure->max_hz >= SystemCoreClock / 32)
     {
-        cfg->spi_initstruct.clkDiv = SPI_CLKDIV_32;
+        spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_32;
     }
     else if (configure->max_hz >= SystemCoreClock / 64)
     {
-        cfg->spi_initstruct.clkDiv = SPI_CLKDIV_64;
+        spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_64;
     }
     else if (configure->max_hz >= SystemCoreClock / 128)
     {
-        cfg->spi_initstruct.clkDiv = SPI_CLKDIV_128;
+        spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_128;
     }
     else if (configure->max_hz >= SystemCoreClock / 256)
     {
-        cfg->spi_initstruct.clkDiv = SPI_CLKDIV_256;
+        spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_256;
     }
     else
     {
         /*  min prescaler 512 */
-        cfg->spi_initstruct.clkDiv = SPI_CLKDIV_512;
+        spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_512;
     }
 
-    SPI_Init(cfg->SPIx, &(cfg->spi_initstruct));
-    SPI_Open(cfg->SPIx);
-    LOG_D("%s init done", cfg->name);
+    SPI_Init(spi_cfg->SPIx, &(spi_cfg->spi_initstruct));
+    SPI_Open(spi_cfg->SPIx);
+    LOG_D("%s init done", spi_cfg->name);
     return RT_EOK;
 }
 
@@ -149,7 +216,7 @@ static rt_err_t swm_spi_init(struct swm_spi *spi_drv, struct rt_spi_configuratio
         }                                 \
     } while (0)
 
-static rt_err_t spitxrx1b(struct swm_spi *spi_drv, void *rcvb, const void *sndb)
+static rt_err_t swm_spi_txrx1b(struct swm_spi_device *spi_drv, void *rcvb, const void *sndb)
 {
     rt_uint32_t padrcv = 0;
     rt_uint32_t padsnd = 0xFF;
@@ -165,12 +232,12 @@ static rt_err_t spitxrx1b(struct swm_spi *spi_drv, void *rcvb, const void *sndb)
     {
         sndb = &padsnd;
     }
-    while (SPI_IsTXFull(spi_drv->cfg->SPIx))
+    while (SPI_IsTXFull(spi_drv->spi_cfg->SPIx))
         ;
-    SPISEND_1(spi_drv->cfg->SPIx->DATA, sndb, spi_drv->cfg->spi_initstruct.WordSize);
-    while (SPI_IsRXEmpty(spi_drv->cfg->SPIx))
+    SPISEND_1(spi_drv->spi_cfg->SPIx->DATA, sndb, spi_drv->spi_cfg->spi_initstruct.WordSize);
+    while (SPI_IsRXEmpty(spi_drv->spi_cfg->SPIx))
         ;
-    SPIRECV_1(spi_drv->cfg->SPIx->DATA, rcvb, spi_drv->cfg->spi_initstruct.WordSize);
+    SPIRECV_1(spi_drv->spi_cfg->SPIx->DATA, rcvb, spi_drv->spi_cfg->spi_initstruct.WordSize);
     return RT_EOK;
 }
 
@@ -183,8 +250,8 @@ static rt_uint32_t swm_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess
     RT_ASSERT(device->bus->parent.user_data != RT_NULL);
     RT_ASSERT(message != RT_NULL);
 
-    struct swm_spi *spi_drv = rt_container_of(device->bus, struct swm_spi, spi_bus);
-    struct swm_spi_cfg *cfg = spi_drv->cfg;
+    struct swm_spi_device *spi_drv = rt_container_of(device->bus, struct swm_spi_device, spi_bus);
+    struct swm_spi_cfg *spi_cfg = spi_drv->spi_cfg;
     struct swm_spi_cs *cs = device->parent.user_data;
 
     if (message->cs_take)
@@ -192,9 +259,9 @@ static rt_uint32_t swm_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess
         GPIO_ClrBit(cs->GPIOx, cs->gpio_pin);
     }
 
-    LOG_D("%s transfer prepare and start", cfg->name);
+    LOG_D("%s transfer prepare and start", spi_cfg->name);
     LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
-          cfg->name, (uint32_t)message->send_buf, (uint32_t)message->recv_buf, message->length);
+          spi_cfg->name, (uint32_t)message->send_buf, (uint32_t)message->recv_buf, message->length);
 
     const rt_uint8_t *sndb = message->send_buf;
     rt_uint8_t *rcvb = message->recv_buf;
@@ -202,14 +269,14 @@ static rt_uint32_t swm_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess
 
     while (length)
     {
-        res = spitxrx1b(spi_drv, rcvb, sndb);
+        res = swm_spi_txrx1b(spi_drv, rcvb, sndb);
         if (rcvb)
         {
-            rcvb += SPISTEP(cfg->spi_initstruct.WordSize);
+            rcvb += SPISTEP(spi_cfg->spi_initstruct.WordSize);
         }
         if (sndb)
         {
-            sndb += SPISTEP(cfg->spi_initstruct.WordSize);
+            sndb += SPISTEP(spi_cfg->spi_initstruct.WordSize);
         }
         if (res != RT_EOK)
         {
@@ -218,7 +285,7 @@ static rt_uint32_t swm_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess
         length--;
     }
     /* Wait until Busy flag is reset before disabling SPI */
-    while (!SPI_IsTXEmpty(cfg->SPIx) && !SPI_IsRXEmpty(cfg->SPIx))
+    while (!SPI_IsTXEmpty(spi_cfg->SPIx) && !SPI_IsRXEmpty(spi_cfg->SPIx))
         ;
     if (message->cs_release)
     {
@@ -227,17 +294,6 @@ static rt_uint32_t swm_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess
     return message->length - length;
 }
 
-static rt_err_t swm_spi_configure(struct rt_spi_device *device,
-                                  struct rt_spi_configuration *configure)
-{
-    RT_ASSERT(device != RT_NULL);
-    RT_ASSERT(configure != RT_NULL);
-
-    struct swm_spi *spi_drv = rt_container_of(device->bus, struct swm_spi, spi_bus);
-    spi_drv->configure = configure;
-
-    return swm_spi_init(spi_drv, configure);
-}
 const static struct rt_spi_ops swm_spi_ops =
     {
         .configure = swm_spi_configure,
@@ -274,7 +330,7 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
     return result;
 }
 
-int rt_hw_spi_init(void)
+int swm_spi_init(void)
 {
     rt_err_t result;
 
@@ -289,19 +345,24 @@ int rt_hw_spi_init(void)
     PORT_Init(PORTB, PIN2, FUNMUX0_SPI1_MOSI, 0);
     PORT_Init(PORTB, PIN3, FUNMUX1_SPI1_MISO, 1);
 #endif //BSP_USING_SPI1
-    for (int i = 0; i < sizeof(spi_cfg) / sizeof(spi_cfg[0]); i++)
+    for (int i = 0; i < sizeof(swm_spi_cfg) / sizeof(swm_spi_cfg[0]); i++)
     {
-        spi_bus_drv[i].cfg = &spi_cfg[i];
-        spi_bus_drv[i].spi_bus.parent.user_data = &spi_cfg[i];
-        result = rt_spi_bus_register(&spi_bus_drv[i].spi_bus, spi_cfg[i].name, &swm_spi_ops);
-        RT_ASSERT(result == RT_EOK);
-
-        LOG_D("%s bus init done", spi_config[i].bus_name);
+        spi_bus_obj[i].spi_cfg = &swm_spi_cfg[i];
+        spi_bus_obj[i].spi_bus.parent.user_data = &swm_spi_cfg[i];
+        result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, swm_spi_cfg[i].name, &swm_spi_ops);
+        if (result != RT_EOK)
+        {
+            LOG_E("%s bus register fail.", swm_spi_cfg[i].name);
+        }
+        else
+        {
+            LOG_D("%s bus register success.", swm_spi_cfg[i].name);
+        }
     }
 
     return result;
 }
-INIT_BOARD_EXPORT(rt_hw_spi_init);
+INIT_BOARD_EXPORT(swm_spi_init);
 
 #endif /* BSP_USING_SPI */
 #endif /* RT_USING_SPI */

bsp/synwit/swm320/drivers/drv_spi.h

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          rewrite
+ */
+
+#ifndef __DRV_SPI_H__
+#define __DRV_SPI_H__
+
+#include "board.h"
+
+//cannot be used before completion init
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *GPIOx, uint32_t n);
+int swm_spi_init(void);
+
+#endif /* __DRV_SPI_H__ */

bsp/swm320/drivers/drv_sram.c → bsp/synwit/swm320/drivers/drv_sram.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/swm320/drivers/drv_sram.h → bsp/synwit/swm320/drivers/drv_sram.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/synwit/swm320/drivers/drv_uart.c

@@ -0,0 +1,376 @@
+/*
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-31     ZYH          first version
+ * 2018-12-10     Zohar_Lee    format file
+ * 2020-07-10     lik          format file
+ */
+
+#include "drv_uart.h"
+
+#ifdef RT_USING_SERIAL
+#ifdef BSP_USING_UART
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.uart"
+#include <drv_log.h>
+
+#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \
+    !defined(BSP_USING_UART3)
+#error "Please define at least one BSP_USING_UARTx"
+/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+#ifdef BSP_USING_UART0
+#ifndef UART0_CFG
+#define UART0_CFG                                   \
+    {                                               \
+        .name = "uart0",                            \
+        .UARTx = UART0,                             \
+        .irq = UART0_IRQn,                          \
+        .uart_initstruct.Baudrate = 115200,         \
+        .uart_initstruct.DataBits = UART_DATA_8BIT, \
+        .uart_initstruct.Parity = UART_PARITY_NONE, \
+        .uart_initstruct.StopBits = UART_STOP_1BIT, \
+        .uart_initstruct.RXThreshold = 0,           \
+        .uart_initstruct.RXThresholdIEn = 1,        \
+        .uart_initstruct.TXThresholdIEn = 0,        \
+        .uart_initstruct.TimeoutTime = 10,          \
+        .uart_initstruct.TimeoutIEn = 1,            \
+    }
+#endif /* UART0_CFG */
+#endif /* BSP_USING_UART0 */
+
+#ifdef BSP_USING_UART1
+#ifndef UART1_CFG
+#define UART1_CFG                                   \
+    {                                               \
+        .name = "uart1",                            \
+        .UARTx = UART1,                             \
+        .irq = UART1_IRQn,                          \
+        .uart_initstruct.Baudrate = 115200,         \
+        .uart_initstruct.DataBits = UART_DATA_8BIT, \
+        .uart_initstruct.Parity = UART_PARITY_NONE, \
+        .uart_initstruct.StopBits = UART_STOP_1BIT, \
+        .uart_initstruct.RXThreshold = 0,           \
+        .uart_initstruct.RXThresholdIEn = 1,        \
+        .uart_initstruct.TXThresholdIEn = 0,        \
+        .uart_initstruct.TimeoutTime = 10,          \
+        .uart_initstruct.TimeoutIEn = 1,            \
+    }
+#endif /* UART1_CFG */
+#endif /* BSP_USING_UART1 */
+
+#ifdef BSP_USING_UART2
+#ifndef UART2_CFG
+#define UART2_CFG                                   \
+    {                                               \
+        .name = "uart2",                            \
+        .UARTx = UART2,                             \
+        .irq = UART2_IRQn,                          \
+        .uart_initstruct.Baudrate = 115200,         \
+        .uart_initstruct.DataBits = UART_DATA_8BIT, \
+        .uart_initstruct.Parity = UART_PARITY_NONE, \
+        .uart_initstruct.StopBits = UART_STOP_1BIT, \
+        .uart_initstruct.RXThreshold = 0,           \
+        .uart_initstruct.RXThresholdIEn = 1,        \
+        .uart_initstruct.TXThresholdIEn = 0,        \
+        .uart_initstruct.TimeoutTime = 10,          \
+        .uart_initstruct.TimeoutIEn = 1,            \
+    }
+#endif /* UART2_CFG */
+#endif /* BSP_USING_UART2 */
+
+#ifdef BSP_USING_UART3
+#ifndef UART3_CFG
+#define UART3_CFG                                   \
+    {                                               \
+        .name = "uart3",                            \
+        .UARTx = UART3,                             \
+        .irq = UART3_IRQn,                          \
+        .uart_initstruct.Baudrate = 115200,         \
+        .uart_initstruct.DataBits = UART_DATA_8BIT, \
+        .uart_initstruct.Parity = UART_PARITY_NONE, \
+        .uart_initstruct.StopBits = UART_STOP_1BIT, \
+        .uart_initstruct.RXThreshold = 0,           \
+        .uart_initstruct.RXThresholdIEn = 1,        \
+        .uart_initstruct.TXThresholdIEn = 0,        \
+        .uart_initstruct.TimeoutTime = 10,          \
+        .uart_initstruct.TimeoutIEn = 1,            \
+    }
+#endif /* UART3_CFG */
+#endif /* BSP_USING_UART3 */
+
+/* swm config class */
+struct swm_uart_cfg
+{
+    const char *name;
+    UART_TypeDef *UARTx;
+    IRQn_Type irq;
+    UART_InitStructure uart_initstruct;
+};
+
+/* swm uart dirver class */
+struct swm_uart
+{
+    struct swm_uart_cfg *uart_cfg;
+    struct rt_serial_device serial_device;
+};
+
+enum
+{
+#ifdef BSP_USING_UART0
+    UART0_INDEX,
+#endif
+#ifdef BSP_USING_UART1
+    UART1_INDEX,
+#endif
+#ifdef BSP_USING_UART2
+    UART2_INDEX,
+#endif
+#ifdef BSP_USING_UART3
+    UART3_INDEX,
+#endif
+};
+
+static struct swm_uart_cfg swm_uart_cfg[] =
+    {
+#ifdef BSP_USING_UART0
+        UART0_CFG,
+#endif
+#ifdef BSP_USING_UART1
+        UART1_CFG,
+#endif
+#ifdef BSP_USING_UART2
+        UART2_CFG,
+#endif
+#ifdef BSP_USING_UART3
+        UART3_CFG,
+#endif
+};
+
+static struct swm_uart uart_obj[sizeof(swm_uart_cfg) / sizeof(swm_uart_cfg[0])] = {0};
+
+static rt_err_t swm_uart_configure(struct rt_serial_device *serial_device, struct serial_configure *configure)
+{
+    struct swm_uart_cfg *uart_cfg;
+    RT_ASSERT(serial_device != RT_NULL);
+    RT_ASSERT(configure != RT_NULL);
+    uart_cfg = serial_device->parent.user_data;
+
+    uart_cfg->uart_initstruct.Baudrate = configure->baud_rate;
+    switch (configure->data_bits)
+    {
+    case DATA_BITS_8:
+        uart_cfg->uart_initstruct.DataBits = UART_DATA_8BIT;
+        break;
+    case DATA_BITS_9:
+        uart_cfg->uart_initstruct.DataBits = UART_DATA_9BIT;
+        break;
+    default:
+        uart_cfg->uart_initstruct.DataBits = UART_DATA_8BIT;
+        break;
+    }
+    switch (configure->stop_bits)
+    {
+    case STOP_BITS_1:
+        uart_cfg->uart_initstruct.StopBits = UART_STOP_1BIT;
+        break;
+    case STOP_BITS_2:
+        uart_cfg->uart_initstruct.StopBits = UART_STOP_2BIT;
+        break;
+    default:
+        uart_cfg->uart_initstruct.StopBits = UART_STOP_1BIT;
+        break;
+    }
+    switch (configure->parity)
+    {
+    case PARITY_NONE:
+        uart_cfg->uart_initstruct.Parity = UART_PARITY_NONE;
+        break;
+    case PARITY_ODD:
+        uart_cfg->uart_initstruct.Parity = UART_PARITY_ODD;
+        break;
+    case PARITY_EVEN:
+        uart_cfg->uart_initstruct.Parity = UART_PARITY_EVEN;
+        break;
+    default:
+        uart_cfg->uart_initstruct.Parity = UART_PARITY_NONE;
+        break;
+    }
+
+    UART_Init(uart_cfg->UARTx, &(uart_cfg->uart_initstruct));
+    UART_Open(uart_cfg->UARTx);
+    return RT_EOK;
+}
+
+static rt_err_t swm_uart_control(struct rt_serial_device *serial_device, int cmd, void *arg)
+{
+    struct swm_uart_cfg *uart_cfg;
+    RT_ASSERT(serial_device != RT_NULL);
+    uart_cfg = serial_device->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        NVIC_DisableIRQ(uart_cfg->irq);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        NVIC_EnableIRQ(uart_cfg->irq);
+        break;
+    }
+    return RT_EOK;
+}
+
+static int swm_uart_putc(struct rt_serial_device *serial_device, char c)
+{
+    struct swm_uart_cfg *uart_cfg;
+    RT_ASSERT(serial_device != RT_NULL);
+    uart_cfg = serial_device->parent.user_data;
+
+    while (UART_IsTXFIFOFull(uart_cfg->UARTx))
+        ;
+    UART_WriteByte(uart_cfg->UARTx, c);
+    while (UART_IsTXBusy(uart_cfg->UARTx))
+        ;
+    return 1;
+}
+
+static int swm_uart_getc(struct rt_serial_device *serial_device)
+{
+    int ch;
+    struct swm_uart_cfg *uart_cfg;
+    RT_ASSERT(serial_device != RT_NULL);
+    uart_cfg = serial_device->parent.user_data;
+
+    ch = -1;
+    if (UART_IsRXFIFOEmpty(uart_cfg->UARTx) == 0)
+    {
+        UART_ReadByte(uart_cfg->UARTx, (uint32_t *)&ch);
+    }
+    return ch;
+}
+
+static const struct rt_uart_ops swm_uart_ops =
+    {
+        .configure = swm_uart_configure,
+        .control = swm_uart_control,
+        .putc = swm_uart_putc,
+        .getc = swm_uart_getc,
+        .dma_transmit = RT_NULL};
+
+/**
+ * Uart common interrupt process. This need add to uart ISR.
+ *
+ * @param serial serial device
+ */
+static void rt_hw_uart_isr(struct rt_serial_device *serial_device)
+{
+    struct swm_uart_cfg *uart_cfg;
+    RT_ASSERT(serial_device != RT_NULL);
+    uart_cfg = serial_device->parent.user_data;
+
+    /* UART in mode Receiver -------------------------------------------------*/
+    if (UART_INTRXThresholdStat(uart_cfg->UARTx) || UART_INTTimeoutStat(uart_cfg->UARTx))
+    {
+        rt_hw_serial_isr(serial_device, RT_SERIAL_EVENT_RX_IND);
+    }
+}
+
+#if defined(BSP_USING_UART0)
+void UART0_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_hw_uart_isr(&(uart_obj[UART0_INDEX].serial_device));
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART0 */
+
+#if defined(BSP_USING_UART1)
+void UART1_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_hw_uart_isr(&(uart_obj[UART1_INDEX].serial_device));
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+void UART2_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_hw_uart_isr(&(uart_obj[UART2_INDEX].serial_device));
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+void UART3_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_hw_uart_isr(&(uart_obj[UART3_INDEX].serial_device));
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART3 */
+
+int swm_uart_init(void)
+{
+    struct serial_configure serial_cfg = RT_SERIAL_CONFIG_DEFAULT;
+    int i = 0;
+    rt_err_t result = RT_EOK;
+
+#ifdef BSP_USING_UART0
+        PORT_Init(PORTA, PIN2, FUNMUX0_UART0_RXD, 1);
+        PORT_Init(PORTA, PIN3, FUNMUX1_UART0_TXD, 0);
+#endif
+#ifdef BSP_USING_UART1
+        PORT_Init(PORTC, PIN2, FUNMUX0_UART1_RXD, 1);
+        PORT_Init(PORTC, PIN3, FUNMUX1_UART1_TXD, 0);
+#endif
+#ifdef BSP_USING_UART2
+        PORT_Init(PORTC, PIN4, FUNMUX0_UART2_RXD, 1);
+        PORT_Init(PORTC, PIN5, FUNMUX1_UART2_TXD, 0);
+#endif
+#ifdef BSP_USING_UART3
+        PORT_Init(PORTC, PIN6, FUNMUX0_UART3_RXD, 1);
+        PORT_Init(PORTC, PIN7, FUNMUX1_UART3_TXD, 0);
+#endif
+
+    for (i = 0; i < sizeof(swm_uart_cfg) / sizeof(swm_uart_cfg[0]); i++)
+    {
+        uart_obj[i].uart_cfg = &swm_uart_cfg[i];
+        uart_obj[i].serial_device.ops = &swm_uart_ops;
+        uart_obj[i].serial_device.config = serial_cfg;
+        /* register UART device */
+        result = rt_hw_serial_register(&uart_obj[i].serial_device, uart_obj[i].uart_cfg->name,
+                                       RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart_obj[i].uart_cfg);
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    return result;
+}
+
+#endif /* BSP_USING_UART */
+#endif /* RT_USING_SERIAL */

bsp/synwit/swm320/drivers/drv_uart.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          rewrite
+ */
+
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+#include "board.h"
+
+int swm_uart_init(void);
+
+#endif /* __DRV_UART_H__ */

bsp/synwit/swm320/drivers/drv_wdt.c

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Zohar_Lee    first version
+ * 2020-07-10     lik          format file
+ */
+
+#include "drv_wdt.h"
+
+#ifdef RT_USING_WDT
+#ifdef BSP_USING_WDT
+//#define DRV_DEBUG
+#define LOG_TAG "drv.wdt"
+#include <drv_log.h>
+
+struct swm_wdt_cfg
+{
+    const char *name;
+    WDT_TypeDef *WDTx;
+};
+
+struct swm_wdt_device
+{
+    struct swm_wdt_cfg *wdt_cfg;
+    struct rt_watchdog_device wdt_device;
+};
+
+static struct swm_wdt_cfg swm_wdt_cfg =
+    {
+        .name = "wdt",
+        .WDTx = WDT,
+};
+
+static struct swm_wdt_device wdt_obj;
+
+static rt_err_t swm_wdt_configure(rt_watchdog_t *wdt_device)
+{
+    return RT_EOK;
+}
+
+static rt_err_t swm_wdt_control(rt_watchdog_t *wdt_device, int cmd, void *arg)
+{
+    struct swm_wdt_cfg *wdt_cfg;
+    RT_ASSERT(wdt_device != RT_NULL);
+    wdt_cfg = wdt_device->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+        WDT_Feed(wdt_cfg->WDTx);
+        break;
+    case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+        WDT_Init(wdt_cfg->WDTx, (SystemCoreClock * (*(rt_uint32_t *)arg)), WDT_MODE_RESET);
+        break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+        *(rt_uint32_t *)arg = (wdt_cfg->WDTx->LOAD) / SystemCoreClock;
+        break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMELEFT:
+        *(rt_uint32_t *)arg = WDT_GetValue(wdt_cfg->WDTx) / SystemCoreClock;
+        break;
+    case RT_DEVICE_CTRL_WDT_START:
+        WDT_Start(wdt_cfg->WDTx);
+        break;
+    case RT_DEVICE_CTRL_WDT_STOP:
+        WDT_Stop(wdt_cfg->WDTx);
+        break;
+    default:
+        LOG_W("This command is not supported.");
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static const struct rt_watchdog_ops swm_wdt_ops =
+    {
+        .init = swm_wdt_configure,
+        .control = swm_wdt_control};
+
+int swm_wdt_init(void)
+{
+    int result = RT_EOK;
+
+    wdt_obj.wdt_cfg = &swm_wdt_cfg;
+    wdt_obj.wdt_device.ops = &swm_wdt_ops;
+
+    result = rt_hw_watchdog_register(&wdt_obj.wdt_device, wdt_obj.wdt_cfg->name, RT_DEVICE_FLAG_RDWR, wdt_obj.wdt_cfg);
+    if(result != RT_EOK)
+    {
+        LOG_E("wdt device register fail.");
+    }
+    else
+    {
+        LOG_D("wdt device register success.");
+    }
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(swm_wdt_init);
+
+#endif /* BSP_USING_WDT */
+#endif /* RT_USING_WDT */

bsp/swm320/drivers/drv_wdt.h → bsp/synwit/swm320/drivers/drv_wdt.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,18 +14,6 @@
 
 #include "board.h"
 
-struct swm_wdt_cfg
-{
-    const char *name;
-    WDT_TypeDef *WDTx;
-};
-
-struct swm_wdt
-{
-    struct swm_wdt_cfg *cfg;
-    struct rt_watchdog_device wdt_device;
-};
-
-int rt_hw_wdt_init(void);
+int swm_wdt_init(void);
 
 #endif /* __DRV_WDT_H__ */

bsp/swm320/libraries/CMSIS/CoreSupport/arm_common_tables.h → bsp/synwit/swm320/libraries/CMSIS/CoreSupport/arm_common_tables.h

@@ -85,13 +85,14 @@ extern const float32_t twiddleCoef_rfft_1024[1024];
 extern const float32_t twiddleCoef_rfft_2048[2048];
 extern const float32_t twiddleCoef_rfft_4096[4096];
 
+
 /* floating-point bit reversal tables */
-#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20)
-#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48)
-#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56)
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
 #define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
 #define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
 #define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
@@ -107,13 +108,13 @@ extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENG
 extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
 
 /* fixed-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12)
-#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24)
-#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56)
-#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112)
-#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240)
-#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480)
-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
 #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
 #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
 

bsp/swm320/libraries/CMSIS/CoreSupport/arm_const_structs.h → bsp/synwit/swm320/libraries/CMSIS/CoreSupport/arm_const_structs.h

@@ -46,34 +46,34 @@
 #include "arm_math.h"
 #include "arm_common_tables.h"
 
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
 
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
 
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
 
 #endif

bsp/synwit/swm320/libraries/CMSIS/CoreSupport/core_cm0.h

@@ -0,0 +1,711 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #if ( __CSMC__ & 0x400)       // FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/synwit/swm320/libraries/CMSIS/CoreSupport/core_cm0plus.h

@@ -0,0 +1,822 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #if ( __CSMC__ & 0x400)       // FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/synwit/swm320/libraries/CMSIS/CoreSupport/core_cm3.h

@@ -0,0 +1,1650 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #if ( __CSMC__ & 0x400)       // FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/synwit/swm320/libraries/CMSIS/CoreSupport/core_cm4.h

@@ -0,0 +1,1802 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #if ( __CSMC__ & 0x400)       // FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/synwit/swm320/libraries/CMSIS/CoreSupport/core_cm7.h

@@ -0,0 +1,2221 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     01. September 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M7
+  @{
+ */
+
+/*  CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM7_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM7_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x07)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #if ( __CSMC__ & 0x400)       // FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x07)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x07)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHPR[12];                /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t ID_PFR[2];               /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t ID_DFR;                  /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ID_AFR;                  /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t ID_MFR[4];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ID_ISAR[5];              /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[1];
+  __I  uint32_t CLIDR;                   /*!< Offset: 0x078 (R/ )  Cache Level ID register                               */
+  __I  uint32_t CTR;                     /*!< Offset: 0x07C (R/ )  Cache Type register                                   */
+  __I  uint32_t CCSIDR;                  /*!< Offset: 0x080 (R/ )  Cache Size ID Register                                */
+  __IO uint32_t CSSELR;                  /*!< Offset: 0x084 (R/W)  Cache Size Selection Register                         */
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+       uint32_t RESERVED3[93];
+  __O  uint32_t STIR;                    /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register                 */
+       uint32_t RESERVED4[15];
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0                      */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1                      */
+  __I  uint32_t MVFR2;                   /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1                      */
+       uint32_t RESERVED5[1];
+  __O  uint32_t ICIALLU;                 /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU                         */
+       uint32_t RESERVED6[1];
+  __O  uint32_t ICIMVAU;                 /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU                      */
+  __O  uint32_t DCIMVAU;                 /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC                      */
+  __O  uint32_t DCISW;                   /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way                         */
+  __O  uint32_t DCCMVAU;                 /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU                           */
+  __O  uint32_t DCCMVAC;                 /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC                           */
+  __O  uint32_t DCCSW;                   /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way                              */
+  __O  uint32_t DCCIMVAC;                /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC            */
+  __O  uint32_t DCCISW;                  /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way               */
+       uint32_t RESERVED7[6];
+  __IO uint32_t ITCMCR;                  /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register   */
+  __IO uint32_t DTCMCR;                  /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers         */
+  __IO uint32_t AHBPCR;                  /*!< Offset: 0x298 (R/W)  AHBP Control Register                                 */
+  __IO uint32_t CACR;                    /*!< Offset: 0x29C (R/W)  L1 Cache Control Register                             */
+  __IO uint32_t AHBSCR;                  /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register                            */
+       uint32_t RESERVED8[1];
+  __IO uint32_t ABFSR;                   /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18                                            /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17                                            /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16                                            /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/* Cache Level ID register */
+#define SCB_CLIDR_LOUU_Pos                 27                                             /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24                                             /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_FORMAT_Pos)                  /*!< SCB CLIDR: LoC Mask */
+
+/* Cache Type register */
+#define SCB_CTR_FORMAT_Pos                 29                                             /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24                                             /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20                                             /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16                                             /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0                                             /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL << SCB_CTR_IMINLINE_Pos)                /*!< SCB CTR: ImInLine Mask */
+
+/* Cache Size ID Register */
+#define SCB_CCSIDR_WT_Pos                  31                                             /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (7UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30                                             /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (7UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29                                             /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (7UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28                                             /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (7UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13                                             /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3                                             /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0                                             /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL << SCB_CCSIDR_LINESIZE_Pos)               /*!< SCB CCSIDR: LineSize Mask */
+
+/* Cache Size Selection Register */
+#define SCB_CSSELR_LEVEL_Pos                0                                             /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (1UL << SCB_CSSELR_LEVEL_Pos)                    /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0                                             /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL << SCB_CSSELR_IND_Pos)                    /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register */
+#define SCB_STIR_INTID_Pos                  0                                             /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL << SCB_STIR_INTID_Pos)                /*!< SCB STIR: INTID Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register*/
+#define SCB_ITCMCR_SZ_Pos                   3                                             /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2                                             /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1FFUL << SCB_ITCMCR_RETEN_Pos)                /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1                                             /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1FFUL << SCB_ITCMCR_RMW_Pos)                  /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0                                             /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1FFUL << SCB_ITCMCR_EN_Pos)                   /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Registers */
+#define SCB_DTCMCR_SZ_Pos                   3                                             /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2                                             /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1                                             /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0                                             /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL << SCB_DTCMCR_EN_Pos)                     /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register */
+#define SCB_AHBPCR_SZ_Pos                   1                                             /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0                                             /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL << SCB_AHBPCR_EN_Pos)                     /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register */
+#define SCB_CACR_FORCEWT_Pos                2                                             /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1                                             /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0                                             /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL << SCB_CACR_SIWT_Pos)                     /*!< SCB CACR: SIWT Mask */
+
+/* AHBS control register */
+#define SCB_AHBSCR_INITCOUNT_Pos           11                                             /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2                                             /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0                                             /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL << SCB_AHBPCR_CTL_Pos)                    /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register */
+#define SCB_ABFSR_AXIMTYPE_Pos              8                                             /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4                                             /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3                                             /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2                                             /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1                                             /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0                                             /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL << SCB_ABFSR_ITCM_Pos)                    /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12                                          /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11                                          /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10                                          /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+       uint32_t RESERVED3[981];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 (  W)  Lock Access Register                      */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R  )  Lock Status Register                      */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+  __I  uint32_t MVFR2;                   /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)]            = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]            >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  Cache functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_CacheFunctions Cache Functions
+    \brief      Functions that configure Instruction and Data cache.
+    @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+#define CCSIDR_LSSHIFT(x)      (((x) & SCB_CCSIDR_LINESIZE_Msk     ) >> SCB_CCSIDR_LINESIZE_Pos     )
+
+
+/** \brief Enable I-Cache
+
+    The function turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache(void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0;                       // invalidate I-Cache
+    SCB->CCR |=  SCB_CCR_IC_Msk;            // enable I-Cache
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Disable I-Cache
+
+    The function turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache(void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~SCB_CCR_IC_Msk;            // disable I-Cache
+    SCB->ICIALLU = 0;                       // invalidate I-Cache
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Invalidate I-Cache
+
+    The function invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache(void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Enable D-Cache
+
+    The function turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // invalidate D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+    __DSB();
+
+    SCB->CCR |=  SCB_CCR_DC_Msk;            // enable D-Cache
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Disable D-Cache
+
+    The function turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    SCB->CCR &= ~SCB_CCR_DC_Msk;            // disable D-Cache
+
+    do {                                    // clean & invalidate D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+
+    __DSB();
+    __ISB();
+ #endif
+}
+
+
+/** \brief Invalidate D-Cache
+
+    The function invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // invalidate D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+ #endif
+}
+
+
+/** \brief Clean D-Cache
+
+    The function cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // clean D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCSW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+ #endif
+}
+
+
+/** \brief Clean & Invalidate D-Cache
+
+    The function cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // clean & invalidate D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+ #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/swm320/libraries/CMSIS/CoreSupport/core_cmFunc.h → bsp/synwit/swm320/libraries/CMSIS/CoreSupport/core_cmFunc.h

@@ -1,4 +1,4 @@
-/**************************************************************************/ /**
+/**************************************************************************//**
  * @file     core_cmFunc.h
  * @brief    CMSIS Cortex-M Core Function Access Header File
  * @version  V4.00
@@ -34,20 +34,22 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
+
 #ifndef __CORE_CMFUNC_H
 #define __CORE_CMFUNC_H
 
+
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
   @{
  */
 
-#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
 #if (__ARMCC_VERSION < 400677)
-#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
 #endif
 
 /* intrinsic void __enable_irq();     */
@@ -61,10 +63,11 @@
  */
 __STATIC_INLINE uint32_t __get_CONTROL(void)
 {
-    register uint32_t __regControl __ASM("control");
-    return (__regControl);
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
 }
 
+
 /** \brief  Set Control Register
 
     This function writes the given value to the Control Register.
@@ -73,10 +76,11 @@ __STATIC_INLINE uint32_t __get_CONTROL(void)
  */
 __STATIC_INLINE void __set_CONTROL(uint32_t control)
 {
-    register uint32_t __regControl __ASM("control");
-    __regControl = control;
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
 }
 
+
 /** \brief  Get IPSR Register
 
     This function returns the content of the IPSR Register.
@@ -85,10 +89,11 @@ __STATIC_INLINE void __set_CONTROL(uint32_t control)
  */
 __STATIC_INLINE uint32_t __get_IPSR(void)
 {
-    register uint32_t __regIPSR __ASM("ipsr");
-    return (__regIPSR);
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
 }
 
+
 /** \brief  Get APSR Register
 
     This function returns the content of the APSR Register.
@@ -97,10 +102,11 @@ __STATIC_INLINE uint32_t __get_IPSR(void)
  */
 __STATIC_INLINE uint32_t __get_APSR(void)
 {
-    register uint32_t __regAPSR __ASM("apsr");
-    return (__regAPSR);
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
 }
 
+
 /** \brief  Get xPSR Register
 
     This function returns the content of the xPSR Register.
@@ -109,10 +115,11 @@ __STATIC_INLINE uint32_t __get_APSR(void)
  */
 __STATIC_INLINE uint32_t __get_xPSR(void)
 {
-    register uint32_t __regXPSR __ASM("xpsr");
-    return (__regXPSR);
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
 }
 
+
 /** \brief  Get Process Stack Pointer
 
     This function returns the current value of the Process Stack Pointer (PSP).
@@ -121,10 +128,11 @@ __STATIC_INLINE uint32_t __get_xPSR(void)
  */
 __STATIC_INLINE uint32_t __get_PSP(void)
 {
-    register uint32_t __regProcessStackPointer __ASM("psp");
-    return (__regProcessStackPointer);
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
 }
 
+
 /** \brief  Set Process Stack Pointer
 
     This function assigns the given value to the Process Stack Pointer (PSP).
@@ -133,10 +141,11 @@ __STATIC_INLINE uint32_t __get_PSP(void)
  */
 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
 {
-    register uint32_t __regProcessStackPointer __ASM("psp");
-    __regProcessStackPointer = topOfProcStack;
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
 }
 
+
 /** \brief  Get Main Stack Pointer
 
     This function returns the current value of the Main Stack Pointer (MSP).
@@ -145,10 +154,11 @@ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
  */
 __STATIC_INLINE uint32_t __get_MSP(void)
 {
-    register uint32_t __regMainStackPointer __ASM("msp");
-    return (__regMainStackPointer);
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
 }
 
+
 /** \brief  Set Main Stack Pointer
 
     This function assigns the given value to the Main Stack Pointer (MSP).
@@ -157,10 +167,11 @@ __STATIC_INLINE uint32_t __get_MSP(void)
  */
 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
 {
-    register uint32_t __regMainStackPointer __ASM("msp");
-    __regMainStackPointer = topOfMainStack;
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
 }
 
+
 /** \brief  Get Priority Mask
 
     This function returns the current state of the priority mask bit from the Priority Mask Register.
@@ -169,10 +180,11 @@ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
  */
 __STATIC_INLINE uint32_t __get_PRIMASK(void)
 {
-    register uint32_t __regPriMask __ASM("primask");
-    return (__regPriMask);
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
 }
 
+
 /** \brief  Set Priority Mask
 
     This function assigns the given value to the Priority Mask Register.
@@ -181,25 +193,28 @@ __STATIC_INLINE uint32_t __get_PRIMASK(void)
  */
 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
 {
-    register uint32_t __regPriMask __ASM("primask");
-    __regPriMask = (priMask);
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
 }
 
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
 
 /** \brief  Enable FIQ
 
     This function enables FIQ interrupts by clearing the F-bit in the CPSR.
     Can only be executed in Privileged modes.
  */
-#define __enable_fault_irq __enable_fiq
+#define __enable_fault_irq                __enable_fiq
+
 
 /** \brief  Disable FIQ
 
     This function disables FIQ interrupts by setting the F-bit in the CPSR.
     Can only be executed in Privileged modes.
  */
-#define __disable_fault_irq __disable_fiq
+#define __disable_fault_irq               __disable_fiq
+
 
 /** \brief  Get Base Priority
 
@@ -207,12 +222,13 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
 
     \return               Base Priority register value
  */
-__STATIC_INLINE uint32_t __get_BASEPRI(void)
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
 {
-    register uint32_t __regBasePri __ASM("basepri");
-    return (__regBasePri);
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
 }
 
+
 /** \brief  Set Base Priority
 
     This function assigns the given value to the Base Priority register.
@@ -221,10 +237,11 @@ __STATIC_INLINE uint32_t __get_BASEPRI(void)
  */
 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
 {
-    register uint32_t __regBasePri __ASM("basepri");
-    __regBasePri = (basePri & 0xff);
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
 }
 
+
 /** \brief  Get Fault Mask
 
     This function returns the current value of the Fault Mask register.
@@ -233,10 +250,11 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
  */
 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
 {
-    register uint32_t __regFaultMask __ASM("faultmask");
-    return (__regFaultMask);
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
 }
 
+
 /** \brief  Set Fault Mask
 
     This function assigns the given value to the Fault Mask register.
@@ -245,13 +263,14 @@ __STATIC_INLINE uint32_t __get_FAULTMASK(void)
  */
 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
-    register uint32_t __regFaultMask __ASM("faultmask");
-    __regFaultMask = (faultMask & (uint32_t)1);
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
 }
 
 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
 
-#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
 
 /** \brief  Get FPSCR
 
@@ -262,13 +281,14 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
 __STATIC_INLINE uint32_t __get_FPSCR(void)
 {
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    register uint32_t __regfpscr __ASM("fpscr");
-    return (__regfpscr);
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
 #else
-    return (0);
+   return(0);
 #endif
 }
 
+
 /** \brief  Set FPSCR
 
     This function assigns the given value to the Floating Point Status/Control register.
@@ -278,14 +298,15 @@ __STATIC_INLINE uint32_t __get_FPSCR(void)
 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 {
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    register uint32_t __regfpscr __ASM("fpscr");
-    __regfpscr = (fpscr);
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
 #endif
 }
 
 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
 
-#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  Enable IRQ Interrupts
@@ -293,277 +314,257 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
   This function enables IRQ interrupts by clearing the I-bit in the CPSR.
   Can only be executed in Privileged modes.
  */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
 {
-    __ASM volatile("cpsie i"
-                   :
-                   :
-                   : "memory");
+  __ASM volatile ("cpsie i" : : : "memory");
 }
 
+
 /** \brief  Disable IRQ Interrupts
 
   This function disables IRQ interrupts by setting the I-bit in the CPSR.
   Can only be executed in Privileged modes.
  */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
 {
-    __ASM volatile("cpsid i"
-                   :
-                   :
-                   : "memory");
+  __ASM volatile ("cpsid i" : : : "memory");
 }
 
+
 /** \brief  Get Control Register
 
     This function returns the content of the Control Register.
 
     \return               Control Register value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
 {
-    uint32_t result;
+  uint32_t result;
 
-    __ASM volatile("MRS %0, control"
-                   : "=r"(result));
-    return (result);
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
 }
 
+
 /** \brief  Set Control Register
 
     This function writes the given value to the Control Register.
 
     \param [in]    control  Control Register value to set
  */
-__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
 {
-    __ASM volatile("MSR control, %0"
-                   :
-                   : "r"(control)
-                   : "memory");
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
 }
 
+
 /** \brief  Get IPSR Register
 
     This function returns the content of the IPSR Register.
 
     \return               IPSR Register value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
 {
-    uint32_t result;
+  uint32_t result;
 
-    __ASM volatile("MRS %0, ipsr"
-                   : "=r"(result));
-    return (result);
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
 }
 
+
 /** \brief  Get APSR Register
 
     This function returns the content of the APSR Register.
 
     \return               APSR Register value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
 {
-    uint32_t result;
+  uint32_t result;
 
-    __ASM volatile("MRS %0, apsr"
-                   : "=r"(result));
-    return (result);
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
 }
 
+
 /** \brief  Get xPSR Register
 
     This function returns the content of the xPSR Register.
 
     \return               xPSR Register value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
 {
-    uint32_t result;
+  uint32_t result;
 
-    __ASM volatile("MRS %0, xpsr"
-                   : "=r"(result));
-    return (result);
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
 }
 
+
 /** \brief  Get Process Stack Pointer
 
     This function returns the current value of the Process Stack Pointer (PSP).
 
     \return               PSP Register value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
 {
-    register uint32_t result;
+  register uint32_t result;
 
-    __ASM volatile("MRS %0, psp\n"
-                   : "=r"(result));
-    return (result);
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
 }
 
+
 /** \brief  Set Process Stack Pointer
 
     This function assigns the given value to the Process Stack Pointer (PSP).
 
     \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
 {
-    __ASM volatile("MSR psp, %0\n"
-                   :
-                   : "r"(topOfProcStack)
-                   : "sp");
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
 }
 
+
 /** \brief  Get Main Stack Pointer
 
     This function returns the current value of the Main Stack Pointer (MSP).
 
     \return               MSP Register value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
 {
-    register uint32_t result;
+  register uint32_t result;
 
-    __ASM volatile("MRS %0, msp\n"
-                   : "=r"(result));
-    return (result);
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
 }
 
+
 /** \brief  Set Main Stack Pointer
 
     This function assigns the given value to the Main Stack Pointer (MSP).
 
     \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
 {
-    __ASM volatile("MSR msp, %0\n"
-                   :
-                   : "r"(topOfMainStack)
-                   : "sp");
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
 }
 
+
 /** \brief  Get Priority Mask
 
     This function returns the current state of the priority mask bit from the Priority Mask Register.
 
     \return               Priority Mask value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
 {
-    uint32_t result;
+  uint32_t result;
 
-    __ASM volatile("MRS %0, primask"
-                   : "=r"(result));
-    return (result);
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
 }
 
+
 /** \brief  Set Priority Mask
 
     This function assigns the given value to the Priority Mask Register.
 
     \param [in]    priMask  Priority Mask
  */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
 {
-    __ASM volatile("MSR primask, %0"
-                   :
-                   : "r"(priMask)
-                   : "memory");
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
 }
 
-#if (__CORTEX_M >= 0x03)
+
+#if       (__CORTEX_M >= 0x03)
 
 /** \brief  Enable FIQ
 
     This function enables FIQ interrupts by clearing the F-bit in the CPSR.
     Can only be executed in Privileged modes.
  */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
 {
-    __ASM volatile("cpsie f"
-                   :
-                   :
-                   : "memory");
+  __ASM volatile ("cpsie f" : : : "memory");
 }
 
+
 /** \brief  Disable FIQ
 
     This function disables FIQ interrupts by setting the F-bit in the CPSR.
     Can only be executed in Privileged modes.
  */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
 {
-    __ASM volatile("cpsid f"
-                   :
-                   :
-                   : "memory");
+  __ASM volatile ("cpsid f" : : : "memory");
 }
 
+
 /** \brief  Get Base Priority
 
     This function returns the current value of the Base Priority register.
 
     \return               Base Priority register value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
 {
-    uint32_t result;
+  uint32_t result;
 
-    __ASM volatile("MRS %0, basepri_max"
-                   : "=r"(result));
-    return (result);
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
 }
 
+
 /** \brief  Set Base Priority
 
     This function assigns the given value to the Base Priority register.
 
     \param [in]    basePri  Base Priority value to set
  */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
 {
-    __ASM volatile("MSR basepri, %0"
-                   :
-                   : "r"(value)
-                   : "memory");
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
 }
 
+
 /** \brief  Get Fault Mask
 
     This function returns the current value of the Fault Mask register.
 
     \return               Fault Mask register value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
 {
-    uint32_t result;
+  uint32_t result;
 
-    __ASM volatile("MRS %0, faultmask"
-                   : "=r"(result));
-    return (result);
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
 }
 
+
 /** \brief  Set Fault Mask
 
     This function assigns the given value to the Fault Mask register.
 
     \param [in]    faultMask  Fault Mask value to set
  */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
-    __ASM volatile("MSR faultmask, %0"
-                   :
-                   : "r"(faultMask)
-                   : "memory");
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
 }
 
 #endif /* (__CORTEX_M >= 0x03) */
 
-#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
 
 /** \brief  Get FPSCR
 
@@ -571,52 +572,52 @@ __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t fau
 
     \return               Floating Point Status/Control register value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
 {
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    uint32_t result;
-
-    /* Empty asm statement works as a scheduling barrier */
-    __ASM volatile("");
-    __ASM volatile("VMRS %0, fpscr"
-                   : "=r"(result));
-    __ASM volatile("");
-    return (result);
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
 #else
-    return (0);
+   return(0);
 #endif
 }
 
+
 /** \brief  Set FPSCR
 
     This function assigns the given value to the Floating Point Status/Control register.
 
     \param [in]    fpscr  Floating Point Status/Control value to set
  */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 {
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    /* Empty asm statement works as a scheduling barrier */
-    __ASM volatile("");
-    __ASM volatile("VMSR fpscr, %0"
-                   :
-                   : "r"(fpscr)
-                   : "vfpcc");
-    __ASM volatile("");
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
 #endif
 }
 
 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
 
-#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 #include <cmsis_iar.h>
 
-#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
 /* TI CCS specific functions */
 #include <cmsis_ccs.h>
 
-#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 /*
  * The CMSIS functions have been implemented as intrinsics in the compiler.
@@ -624,7 +625,8 @@ __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
  * Including the CMSIS ones.
  */
 
-#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
 /* Cosmic specific functions */
 #include <cmsis_csm.h>
 

bsp/swm320/libraries/CMSIS/CoreSupport/core_cmInstr.h → bsp/synwit/swm320/libraries/CMSIS/CoreSupport/core_cmInstr.h

@@ -1,4 +1,4 @@
-/**************************************************************************/ /**
+/**************************************************************************//**
  * @file     core_cmInstr.h
  * @brief    CMSIS Cortex-M Core Instruction Access Header File
  * @version  V4.00
@@ -34,47 +34,54 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
+
 #ifndef __CORE_CMINSTR_H
 #define __CORE_CMINSTR_H
 
+
 /* ##########################  Core Instruction Access  ######################### */
 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
   Access to dedicated instructions
   @{
 */
 
-#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
 #if (__ARMCC_VERSION < 400677)
-#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
 #endif
 
+
 /** \brief  No Operation
 
     No Operation does nothing. This instruction can be used for code alignment purposes.
  */
-#define __NOP __nop
+#define __NOP                             __nop
+
 
 /** \brief  Wait For Interrupt
 
     Wait For Interrupt is a hint instruction that suspends execution
     until one of a number of events occurs.
  */
-#define __WFI __wfi
+#define __WFI                             __wfi
+
 
 /** \brief  Wait For Event
 
     Wait For Event is a hint instruction that permits the processor to enter
     a low-power state until one of a number of events occurs.
  */
-#define __WFE __wfe
+#define __WFE                             __wfe
+
 
 /** \brief  Send Event
 
     Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  */
-#define __SEV __sev
+#define __SEV                             __sev
+
 
 /** \brief  Instruction Synchronization Barrier
 
@@ -82,21 +89,24 @@
     so that all instructions following the ISB are fetched from cache or
     memory, after the instruction has been completed.
  */
-#define __ISB() __isb(0xF)
+#define __ISB()                           __isb(0xF)
+
 
 /** \brief  Data Synchronization Barrier
 
     This function acts as a special kind of Data Memory Barrier.
     It completes when all explicit memory accesses before this instruction complete.
  */
-#define __DSB() __dsb(0xF)
+#define __DSB()                           __dsb(0xF)
+
 
 /** \brief  Data Memory Barrier
 
     This function ensures the apparent order of the explicit memory operations before
     and after the instruction, without ensuring their completion.
  */
-#define __DMB() __dmb(0xF)
+#define __DMB()                           __dmb(0xF)
+
 
 /** \brief  Reverse byte order (32 bit)
 
@@ -105,7 +115,8 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#define __REV __rev
+#define __REV                             __rev
+
 
 /** \brief  Reverse byte order (16 bit)
 
@@ -117,8 +128,8 @@
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
 {
-    rev16 r0, r0
-                  bx lr
+  rev16 r0, r0
+  bx lr
 }
 #endif
 
@@ -132,11 +143,12 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
 {
-    revsh r0, r0
-                  bx lr
+  revsh r0, r0
+  bx lr
 }
 #endif
 
+
 /** \brief  Rotate Right in unsigned value (32 bit)
 
     This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
@@ -145,7 +157,8 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    value  Number of Bits to rotate
     \return               Rotated value
  */
-#define __ROR __ror
+#define __ROR                             __ror
+
 
 /** \brief  Breakpoint
 
@@ -155,9 +168,10 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    value  is ignored by the processor.
                    If required, a debugger can use it to store additional information about the breakpoint.
  */
-#define __BKPT(value) __breakpoint(value)
+#define __BKPT(value)                       __breakpoint(value)
 
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
 
 /** \brief  Reverse bit order of value
 
@@ -166,7 +180,8 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#define __RBIT __rbit
+#define __RBIT                            __rbit
+
 
 /** \brief  LDR Exclusive (8 bit)
 
@@ -175,7 +190,8 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    ptr  Pointer to data
     \return             value of type uint8_t at (*ptr)
  */
-#define __LDREXB(ptr) ((uint8_t)__ldrex(ptr))
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
 
 /** \brief  LDR Exclusive (16 bit)
 
@@ -184,7 +200,8 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    ptr  Pointer to data
     \return        value of type uint16_t at (*ptr)
  */
-#define __LDREXH(ptr) ((uint16_t)__ldrex(ptr))
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
 
 /** \brief  LDR Exclusive (32 bit)
 
@@ -193,7 +210,8 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    ptr  Pointer to data
     \return        value of type uint32_t at (*ptr)
  */
-#define __LDREXW(ptr) ((uint32_t)__ldrex(ptr))
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
 
 /** \brief  STR Exclusive (8 bit)
 
@@ -204,7 +222,8 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \return          0  Function succeeded
     \return          1  Function failed
  */
-#define __STREXB(value, ptr) __strex(value, ptr)
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
 
 /** \brief  STR Exclusive (16 bit)
 
@@ -215,7 +234,8 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \return          0  Function succeeded
     \return          1  Function failed
  */
-#define __STREXH(value, ptr) __strex(value, ptr)
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
 
 /** \brief  STR Exclusive (32 bit)
 
@@ -226,14 +246,16 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \return          0  Function succeeded
     \return          1  Function failed
  */
-#define __STREXW(value, ptr) __strex(value, ptr)
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
 
 /** \brief  Remove the exclusive lock
 
     This function removes the exclusive lock which is created by LDREX.
 
  */
-#define __CLREX __clrex
+#define __CLREX                           __clrex
+
 
 /** \brief  Signed Saturate
 
@@ -243,7 +265,8 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    sat  Bit position to saturate to (1..32)
     \return             Saturated value
  */
-#define __SSAT __ssat
+#define __SSAT                            __ssat
+
 
 /** \brief  Unsigned Saturate
 
@@ -253,7 +276,8 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    sat  Bit position to saturate to (0..31)
     \return             Saturated value
  */
-#define __USAT __usat
+#define __USAT                            __usat
+
 
 /** \brief  Count leading zeros
 
@@ -262,7 +286,8 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]  value  Value to count the leading zeros
     \return             number of leading zeros in value
  */
-#define __CLZ __clz
+#define __CLZ                             __clz
+
 
 /** \brief  Rotate Right with Extend (32 bit)
 
@@ -274,11 +299,12 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
 {
-    rrx r0, r0
-                bx lr
+  rrx r0, r0
+  bx lr
 }
 #endif
 
+
 /** \brief  LDRT Unprivileged (8 bit)
 
     This function executes a Unprivileged LDRT instruction for 8 bit value.
@@ -286,7 +312,8 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
     \param [in]    ptr  Pointer to data
     \return             value of type uint8_t at (*ptr)
  */
-#define __LDRBT(ptr) ((uint8_t)__ldrt(ptr))
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
 
 /** \brief  LDRT Unprivileged (16 bit)
 
@@ -295,7 +322,8 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
     \param [in]    ptr  Pointer to data
     \return        value of type uint16_t at (*ptr)
  */
-#define __LDRHT(ptr) ((uint16_t)__ldrt(ptr))
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
 
 /** \brief  LDRT Unprivileged (32 bit)
 
@@ -304,7 +332,8 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
     \param [in]    ptr  Pointer to data
     \return        value of type uint32_t at (*ptr)
  */
-#define __LDRT(ptr) ((uint32_t)__ldrt(ptr))
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
 
 /** \brief  STRT Unprivileged (8 bit)
 
@@ -313,7 +342,8 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
  */
-#define __STRBT(value, ptr) __strt(value, ptr)
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
 
 /** \brief  STRT Unprivileged (16 bit)
 
@@ -322,7 +352,8 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
  */
-#define __STRHT(value, ptr) __strt(value, ptr)
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
 
 /** \brief  STRT Unprivileged (32 bit)
 
@@ -331,93 +362,101 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
  */
-#define __STRT(value, ptr) __strt(value, ptr)
+#define __STRT(value, ptr)                __strt(value, ptr)
 
 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
 
-#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /* Define macros for porting to both thumb1 and thumb2.
  * For thumb1, use low register (r0-r7), specified by constrant "l"
  * Otherwise, use general registers, specified by constrant "r" */
-#if defined(__thumb__) && !defined(__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l"(r)
-#define __CMSIS_GCC_USE_REG(r) "l"(r)
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
 #else
-#define __CMSIS_GCC_OUT_REG(r) "=r"(r)
-#define __CMSIS_GCC_USE_REG(r) "r"(r)
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
 #endif
 
 /** \brief  No Operation
 
     No Operation does nothing. This instruction can be used for code alignment purposes.
  */
-__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
 {
-    __ASM volatile("nop");
+  __ASM volatile ("nop");
 }
 
+
 /** \brief  Wait For Interrupt
 
     Wait For Interrupt is a hint instruction that suspends execution
     until one of a number of events occurs.
  */
-__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
 {
-    __ASM volatile("wfi");
+  __ASM volatile ("wfi");
 }
 
+
 /** \brief  Wait For Event
 
     Wait For Event is a hint instruction that permits the processor to enter
     a low-power state until one of a number of events occurs.
  */
-__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
 {
-    __ASM volatile("wfe");
+  __ASM volatile ("wfe");
 }
 
+
 /** \brief  Send Event
 
     Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  */
-__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
 {
-    __ASM volatile("sev");
+  __ASM volatile ("sev");
 }
 
+
 /** \brief  Instruction Synchronization Barrier
 
     Instruction Synchronization Barrier flushes the pipeline in the processor,
     so that all instructions following the ISB are fetched from cache or
     memory, after the instruction has been completed.
  */
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
 {
-    __ASM volatile("isb");
+  __ASM volatile ("isb");
 }
 
+
 /** \brief  Data Synchronization Barrier
 
     This function acts as a special kind of Data Memory Barrier.
     It completes when all explicit memory accesses before this instruction complete.
  */
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
 {
-    __ASM volatile("dsb");
+  __ASM volatile ("dsb");
 }
 
+
 /** \brief  Data Memory Barrier
 
     This function ensures the apparent order of the explicit memory operations before
     and after the instruction, without ensuring their completion.
  */
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
 {
-    __ASM volatile("dmb");
+  __ASM volatile ("dmb");
 }
 
+
 /** \brief  Reverse byte order (32 bit)
 
     This function reverses the byte order in integer value.
@@ -425,20 +464,19 @@ __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
 {
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-    return __builtin_bswap32(value);
+  return __builtin_bswap32(value);
 #else
-    uint32_t result;
+  uint32_t result;
 
-    __ASM volatile("rev %0, %1"
-                   : __CMSIS_GCC_OUT_REG(result)
-                   : __CMSIS_GCC_USE_REG(value));
-    return (result);
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
 #endif
 }
 
+
 /** \brief  Reverse byte order (16 bit)
 
     This function reverses the byte order in two unsigned short values.
@@ -446,16 +484,15 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
 {
-    uint32_t result;
+  uint32_t result;
 
-    __ASM volatile("rev16 %0, %1"
-                   : __CMSIS_GCC_OUT_REG(result)
-                   : __CMSIS_GCC_USE_REG(value));
-    return (result);
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
 }
 
+
 /** \brief  Reverse byte order in signed short value
 
     This function reverses the byte order in a signed short value with sign extension to integer.
@@ -463,20 +500,19 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
 {
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-    return (short)__builtin_bswap16(value);
+  return (short)__builtin_bswap16(value);
 #else
-    uint32_t result;
+  uint32_t result;
 
-    __ASM volatile("revsh %0, %1"
-                   : __CMSIS_GCC_OUT_REG(result)
-                   : __CMSIS_GCC_USE_REG(value));
-    return (result);
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
 #endif
 }
 
+
 /** \brief  Rotate Right in unsigned value (32 bit)
 
     This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
@@ -485,11 +521,12 @@ __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
     \param [in]    value  Number of Bits to rotate
     \return               Rotated value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
 {
-    return (op1 >> op2) | (op1 << (32 - op2));
+  return (op1 >> op2) | (op1 << (32 - op2));
 }
 
+
 /** \brief  Breakpoint
 
     This function causes the processor to enter Debug state.
@@ -498,9 +535,10 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint
     \param [in]    value  is ignored by the processor.
                    If required, a debugger can use it to store additional information about the breakpoint.
  */
-#define __BKPT(value) __ASM volatile("bkpt " #value)
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
 
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
 
 /** \brief  Reverse bit order of value
 
@@ -509,16 +547,15 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 {
-    uint32_t result;
+  uint32_t result;
 
-    __ASM volatile("rbit %0, %1"
-                   : "=r"(result)
-                   : "r"(value));
-    return (result);
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
 }
 
+
 /** \brief  LDR Exclusive (8 bit)
 
     This function executes a exclusive LDR instruction for 8 bit value.
@@ -526,26 +563,22 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
     \param [in]    ptr  Pointer to data
     \return             value of type uint8_t at (*ptr)
  */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
 {
     uint32_t result;
 
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-    __ASM volatile("ldrexb %0, %1"
-                   : "=r"(result)
-                   : "Q"(*addr));
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
 #else
     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
        accepted by assembler. So has to use following less efficient pattern.
     */
-    __ASM volatile("ldrexb %0, [%1]"
-                   : "=r"(result)
-                   : "r"(addr)
-                   : "memory");
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 #endif
-    return ((uint8_t)result); /* Add explicit type cast here */
+   return ((uint8_t) result);    /* Add explicit type cast here */
 }
 
+
 /** \brief  LDR Exclusive (16 bit)
 
     This function executes a exclusive LDR instruction for 16 bit values.
@@ -553,26 +586,22 @@ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t
     \param [in]    ptr  Pointer to data
     \return        value of type uint16_t at (*ptr)
  */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
 {
     uint32_t result;
 
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-    __ASM volatile("ldrexh %0, %1"
-                   : "=r"(result)
-                   : "Q"(*addr));
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
 #else
     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
        accepted by assembler. So has to use following less efficient pattern.
     */
-    __ASM volatile("ldrexh %0, [%1]"
-                   : "=r"(result)
-                   : "r"(addr)
-                   : "memory");
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 #endif
-    return ((uint16_t)result); /* Add explicit type cast here */
+   return ((uint16_t) result);    /* Add explicit type cast here */
 }
 
+
 /** \brief  LDR Exclusive (32 bit)
 
     This function executes a exclusive LDR instruction for 32 bit values.
@@ -580,16 +609,15 @@ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16
     \param [in]    ptr  Pointer to data
     \return        value of type uint32_t at (*ptr)
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
 {
     uint32_t result;
 
-    __ASM volatile("ldrex %0, %1"
-                   : "=r"(result)
-                   : "Q"(*addr));
-    return (result);
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
 }
 
+
 /** \brief  STR Exclusive (8 bit)
 
     This function executes a exclusive STR instruction for 8 bit values.
@@ -599,16 +627,15 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32
     \return          0  Function succeeded
     \return          1  Function failed
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
 {
-    uint32_t result;
+   uint32_t result;
 
-    __ASM volatile("strexb %0, %2, %1"
-                   : "=&r"(result), "=Q"(*addr)
-                   : "r"((uint32_t)value));
-    return (result);
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
 }
 
+
 /** \brief  STR Exclusive (16 bit)
 
     This function executes a exclusive STR instruction for 16 bit values.
@@ -618,16 +645,15 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value,
     \return          0  Function succeeded
     \return          1  Function failed
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
 {
-    uint32_t result;
+   uint32_t result;
 
-    __ASM volatile("strexh %0, %2, %1"
-                   : "=&r"(result), "=Q"(*addr)
-                   : "r"((uint32_t)value));
-    return (result);
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
 }
 
+
 /** \brief  STR Exclusive (32 bit)
 
     This function executes a exclusive STR instruction for 32 bit values.
@@ -637,27 +663,26 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value,
     \return          0  Function succeeded
     \return          1  Function failed
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
 {
-    uint32_t result;
+   uint32_t result;
 
-    __ASM volatile("strex %0, %2, %1"
-                   : "=&r"(result), "=Q"(*addr)
-                   : "r"(value));
-    return (result);
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
 }
 
+
 /** \brief  Remove the exclusive lock
 
     This function removes the exclusive lock which is created by LDREX.
 
  */
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
 {
-    __ASM volatile("clrex" ::
-                       : "memory");
+  __ASM volatile ("clrex" ::: "memory");
 }
 
+
 /** \brief  Signed Saturate
 
     This function saturates a signed value.
@@ -666,15 +691,13 @@ __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
     \param [in]    sat  Bit position to saturate to (1..32)
     \return             Saturated value
  */
-#define __SSAT(ARG1, ARG2)                   \
-    (                                        \
-        {                                    \
-            uint32_t __RES, __ARG1 = (ARG1); \
-            __ASM("ssat %0, %1, %2"          \
-                  : "=r"(__RES)              \
-                  : "I"(ARG2), "r"(__ARG1)); \
-            __RES;                           \
-        })
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
 
 /** \brief  Unsigned Saturate
 
@@ -684,15 +707,13 @@ __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
     \param [in]    sat  Bit position to saturate to (0..31)
     \return             Saturated value
  */
-#define __USAT(ARG1, ARG2)                   \
-    (                                        \
-        {                                    \
-            uint32_t __RES, __ARG1 = (ARG1); \
-            __ASM("usat %0, %1, %2"          \
-                  : "=r"(__RES)              \
-                  : "I"(ARG2), "r"(__ARG1)); \
-            __RES;                           \
-        })
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
 
 /** \brief  Count leading zeros
 
@@ -701,16 +722,15 @@ __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
     \param [in]  value  Value to count the leading zeros
     \return             number of leading zeros in value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
 {
-    uint32_t result;
+  uint32_t result;
 
-    __ASM volatile("clz %0, %1"
-                   : "=r"(result)
-                   : "r"(value));
-    return ((uint8_t)result); /* Add explicit type cast here */
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+   return ((uint8_t) result);    /* Add explicit type cast here */
 }
 
+
 /** \brief  Rotate Right with Extend (32 bit)
 
     This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
@@ -718,16 +738,15 @@ __attribute__((always_inline)) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
     \param [in]    value  Value to rotate
     \return               Rotated value
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
 {
-    uint32_t result;
+  uint32_t result;
 
-    __ASM volatile("rrx %0, %1"
-                   : __CMSIS_GCC_OUT_REG(result)
-                   : __CMSIS_GCC_USE_REG(value));
-    return (result);
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
 }
 
+
 /** \brief  LDRT Unprivileged (8 bit)
 
     This function executes a Unprivileged LDRT instruction for 8 bit value.
@@ -735,26 +754,22 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
     \param [in]    ptr  Pointer to data
     \return             value of type uint8_t at (*ptr)
  */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
 {
     uint32_t result;
 
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-    __ASM volatile("ldrbt %0, %1"
-                   : "=r"(result)
-                   : "Q"(*addr));
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
 #else
     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
        accepted by assembler. So has to use following less efficient pattern.
     */
-    __ASM volatile("ldrbt %0, [%1]"
-                   : "=r"(result)
-                   : "r"(addr)
-                   : "memory");
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 #endif
-    return ((uint8_t)result); /* Add explicit type cast here */
+   return ((uint8_t) result);    /* Add explicit type cast here */
 }
 
+
 /** \brief  LDRT Unprivileged (16 bit)
 
     This function executes a Unprivileged LDRT instruction for 16 bit values.
@@ -762,26 +777,22 @@ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t
     \param [in]    ptr  Pointer to data
     \return        value of type uint16_t at (*ptr)
  */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
 {
     uint32_t result;
 
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-    __ASM volatile("ldrht %0, %1"
-                   : "=r"(result)
-                   : "Q"(*addr));
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
 #else
     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
        accepted by assembler. So has to use following less efficient pattern.
     */
-    __ASM volatile("ldrht %0, [%1]"
-                   : "=r"(result)
-                   : "r"(addr)
-                   : "memory");
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 #endif
-    return ((uint16_t)result); /* Add explicit type cast here */
+   return ((uint16_t) result);    /* Add explicit type cast here */
 }
 
+
 /** \brief  LDRT Unprivileged (32 bit)
 
     This function executes a Unprivileged LDRT instruction for 32 bit values.
@@ -789,16 +800,15 @@ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_
     \param [in]    ptr  Pointer to data
     \return        value of type uint32_t at (*ptr)
  */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
 {
     uint32_t result;
 
-    __ASM volatile("ldrt %0, %1"
-                   : "=r"(result)
-                   : "Q"(*addr));
-    return (result);
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
 }
 
+
 /** \brief  STRT Unprivileged (8 bit)
 
     This function executes a Unprivileged STRT instruction for 8 bit values.
@@ -806,13 +816,12 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
  */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
 {
-    __ASM volatile("strbt %1, %0"
-                   : "=Q"(*addr)
-                   : "r"((uint32_t)value));
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
 }
 
+
 /** \brief  STRT Unprivileged (16 bit)
 
     This function executes a Unprivileged STRT instruction for 16 bit values.
@@ -820,13 +829,12 @@ __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volat
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
  */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
 {
-    __ASM volatile("strht %1, %0"
-                   : "=Q"(*addr)
-                   : "r"((uint32_t)value));
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
 }
 
+
 /** \brief  STRT Unprivileged (32 bit)
 
     This function executes a Unprivileged STRT instruction for 32 bit values.
@@ -834,24 +842,25 @@ __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, vola
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
  */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
 {
-    __ASM volatile("strt %1, %0"
-                   : "=Q"(*addr)
-                   : "r"(value));
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
 }
 
 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
 
-#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 #include <cmsis_iar.h>
 
-#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
 /* TI CCS specific functions */
 #include <cmsis_ccs.h>
 
-#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 /*
  * The CMSIS functions have been implemented as intrinsics in the compiler.
@@ -859,7 +868,8 @@ __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volat
  * Including the CMSIS ones.
  */
 
-#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
 /* Cosmic specific functions */
 #include <cmsis_csm.h>
 

bsp/synwit/swm320/libraries/CMSIS/CoreSupport/core_cmSimd.h

@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */

bsp/synwit/swm320/libraries/CMSIS/DeviceSupport/SWM320.h

@@ -0,0 +1,3181 @@
+#ifndef __SWM320_H__
+#define __SWM320_H__
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+typedef enum IRQn
+{
+/******  Cortex-M0 Processor Exceptions Numbers **********************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                        */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt         */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                 */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt               */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                  */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt            */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                  */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt              */
+
+/******  Cortex-M4 specific Interrupt Numbers ************************************************/
+  GPIOA0_IRQn         = 0,
+  GPIOA1_IRQn         = 1,
+  GPIOA2_IRQn         = 2,
+  GPIOA3_IRQn         = 3,
+  GPIOA4_IRQn         = 4,
+  GPIOA5_IRQn         = 5,
+  GPIOA6_IRQn         = 6,
+  GPIOA7_IRQn         = 7,
+  GPIOB0_IRQn         = 8,
+  GPIOB1_IRQn         = 9,
+  GPIOB2_IRQn         = 10,
+  GPIOB3_IRQn         = 11,
+  GPIOB4_IRQn         = 12,
+  GPIOB5_IRQn         = 13,
+  GPIOB6_IRQn         = 14,
+  GPIOB7_IRQn         = 15,
+  GPIOC0_IRQn         = 16,
+  GPIOC1_IRQn         = 17,
+  GPIOC2_IRQn         = 18,
+  GPIOC3_IRQn         = 19,
+  GPIOC4_IRQn         = 20,
+  GPIOC5_IRQn         = 21,
+  GPIOC6_IRQn         = 22,
+  GPIOC7_IRQn         = 23,
+  GPIOM0_IRQn         = 24,
+  GPIOM1_IRQn         = 25,
+  GPIOM2_IRQn         = 26,
+  GPIOM3_IRQn         = 27,
+  GPIOM4_IRQn         = 28,
+  GPIOM5_IRQn         = 29,
+  GPIOM6_IRQn         = 30,
+  GPIOM7_IRQn         = 31,
+  DMA_IRQn            = 32,
+  LCD_IRQn            = 33,
+  NORFLC_IRQn         = 34,
+  CAN_IRQn            = 35,
+  PULSE_IRQn          = 36,
+  WDT_IRQn            = 37,
+  PWM_IRQn            = 38,
+  UART0_IRQn          = 39,
+  UART1_IRQn          = 40,
+  UART2_IRQn          = 41,
+  UART3_IRQn          = 42,
+  UART4_IRQn          = 43,
+  I2C0_IRQn           = 44,
+  I2C1_IRQn           = 45,
+  SPI0_IRQn           = 46,
+  ADC0_IRQn           = 47,
+  RTC_IRQn            = 48,
+  BOD_IRQn            = 49,
+  SDIO_IRQn           = 50,
+  GPIOA_IRQn          = 51,
+  GPIOB_IRQn          = 52,
+  GPIOC_IRQn          = 53,
+  GPIOM_IRQn          = 54,
+  GPION_IRQn          = 55,
+  GPIOP_IRQn          = 56,
+  ADC1_IRQn           = 57,
+  FPU_IRQn            = 58,
+  SPI1_IRQn           = 59,
+  TIMR0_IRQn          = 60,
+  TIMR1_IRQn          = 61,
+  TIMR2_IRQn          = 62,
+  TIMR3_IRQn          = 63,
+  TIMR4_IRQn          = 64,
+  TIMR5_IRQn          = 65,
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M0 Processor and Core Peripherals */
+#define __CM4_REV                 0x0001  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             0       /*!< SWM320 not provides an MPU                    */
+#define __NVIC_PRIO_BITS          3       /*!< SWM320 uses 3 Bits for the Priority Levels    */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             0       /*!< FPU present                                   */
+
+#if   defined ( __CC_ARM )
+  #pragma anon_unions
+#endif
+
+#include <stdio.h>
+#include "core_cm4.h"                  /* Cortex-M0 processor and core peripherals           */
+#include "system_SWM320.h"
+
+
+/******************************************************************************/
+/*              Device Specific Peripheral registers structures          */
+/******************************************************************************/
+typedef struct {
+    __IO uint32_t CLKSEL;                   //Clock Select
+
+    __IO uint32_t CLKDIV;
+
+    __IO uint32_t CLKEN;                    //Clock Enable
+
+    __IO uint32_t SLEEP;
+
+         uint32_t RESERVED0[6];
+
+    __IO uint32_t RTCBKP_ISO;               //[0] 1 RTC备份电源域处于隔离状态    0 RTC备份电源域可访问
+
+    __IO uint32_t RTCWKEN;                  //[0] 1 使能RTC唤醒功能
+
+         uint32_t RESERVED[52+64];
+
+    __IO uint32_t PAWKEN;                   //Port A Wakeup Enable
+    __IO uint32_t PBWKEN;
+    __IO uint32_t PCWKEN;
+
+         uint32_t RESERVED2[1+4];
+
+    __IO uint32_t PAWKSR;                   //Port A Wakeup Status Register，写1清零
+    __IO uint32_t PBWKSR;
+    __IO uint32_t PCWKSR;
+
+         uint32_t RESERVED3[64-10];
+
+    __IO uint32_t RSTCR;                    //Reset Control Register
+    __IO uint32_t RSTSR;                    //Reset Status Register
+
+         uint32_t RESERVED4[61+64];
+
+    __IO uint32_t BKP[3];                   //数据备份寄存器
+
+    //RTC Power Domain: 0x4001E000
+         uint32_t RESERVED5[(0x4001E000-0x40000508)/4-1];
+
+    __IO uint32_t RTCBKP[8];                //RTC电源域数据备份寄存器
+
+    __IO uint32_t LRCCR;                    //Low speed RC Control Register
+    __IO uint32_t LRCTRIM0;                 //Low speed RC Trim
+    __IO uint32_t LRCTRIM1;
+
+         uint32_t RESERVED6;
+
+    __IO uint32_t RTCLDOTRIM;               //RTC Power Domain LDO Trim
+
+    //Analog Control: 0x40031000
+         uint32_t RESERVED7[(0x40031000-0x4001E030)/4-1];
+
+    __IO uint32_t HRCCR;                    //High speed RC Control Register
+
+         uint32_t RESERVED8[7];
+
+    __IO uint32_t XTALCR;
+
+    __IO uint32_t PLLCR;
+    __IO uint32_t PLLDIV;
+    __IO uint32_t PLLSET;
+    __IO uint32_t PLLLOCK;                  //[0] 1 PLL已锁定
+
+    __IO uint32_t BODIE;
+    __IO uint32_t BODIF;
+
+    __IO uint32_t ADC1IN7;
+} SYS_TypeDef;
+
+
+#define SYS_CLKSEL_LFCK_Pos         0       //Low Frequency Clock Source    0 LRC   1 PLL
+#define SYS_CLKSEL_LFCK_Msk         (0x01 << SYS_CLKSEL_LFCK_Pos)
+#define SYS_CLKSEL_HFCK_Pos         1       //High Frequency Clock Source   0 HRC   1 XTAL
+#define SYS_CLKSEL_HFCK_Msk         (0x01 << SYS_CLKSEL_HFCK_Pos)
+#define SYS_CLKSEL_SYS_Pos          2       //系统时钟选择    0 LFCK  1 HFCK
+#define SYS_CLKSEL_SYS_Msk          (0x01 << SYS_CLKSEL_SYS_Pos)
+
+#define SYS_CLKDIV_SYS_Pos          0       //系统时钟分频  0 1分频    1 2分频
+#define SYS_CLKDIV_SYS_Msk          (0x01 << SYS_CLKDIV_SYS_Pos)
+#define SYS_CLKDIV_PWM_Pos          1       //PWM 时钟分频  0 1分频    1 8分频
+#define SYS_CLKDIV_PWM_Msk          (0x01 << SYS_CLKDIV_PWM_Pos)
+#define SYS_CLKDIV_SDRAM_Pos        2       //SDRAM时钟分频 0 1分频    1 2分频    2 4分频
+#define SYS_CLKDIV_SDRAM_Msk        (0x03 << SYS_CLKDIV_SDRAM_Pos)
+#define SYS_CLKDIV_SDIO_Pos         4       //SDIO时钟分频  0 1分频    1 2分频    2 4分频     3 8分频
+#define SYS_CLKDIV_SDIO_Msk         (0x03 << SYS_CLKDIV_SDIO_Pos)
+
+#define SYS_CLKEN_GPIOA_Pos         0
+#define SYS_CLKEN_GPIOA_Msk         (0x01 << SYS_CLKEN_GPIOA_Pos)
+#define SYS_CLKEN_GPIOB_Pos         1
+#define SYS_CLKEN_GPIOB_Msk         (0x01 << SYS_CLKEN_GPIOB_Pos)
+#define SYS_CLKEN_GPIOC_Pos         2
+#define SYS_CLKEN_GPIOC_Msk         (0x01 << SYS_CLKEN_GPIOC_Pos)
+#define SYS_CLKEN_GPIOM_Pos         4
+#define SYS_CLKEN_GPIOM_Msk         (0x01 << SYS_CLKEN_GPIOM_Pos)
+#define SYS_CLKEN_GPION_Pos         5
+#define SYS_CLKEN_GPION_Msk         (0x01 << SYS_CLKEN_GPION_Pos)
+#define SYS_CLKEN_TIMR_Pos          6
+#define SYS_CLKEN_TIMR_Msk          (0x01 << SYS_CLKEN_TIMR_Pos)
+#define SYS_CLKEN_WDT_Pos           7
+#define SYS_CLKEN_WDT_Msk           (0x01 << SYS_CLKEN_WDT_Pos)
+#define SYS_CLKEN_ADC0_Pos          8
+#define SYS_CLKEN_ADC0_Msk          (0x01 << SYS_CLKEN_ADC0_Pos)
+#define SYS_CLKEN_PWM_Pos           9
+#define SYS_CLKEN_PWM_Msk           (0x01 << SYS_CLKEN_PWM_Pos)
+#define SYS_CLKEN_RTC_Pos           10
+#define SYS_CLKEN_RTC_Msk           (0x01 << SYS_CLKEN_RTC_Pos)
+#define SYS_CLKEN_UART0_Pos         11
+#define SYS_CLKEN_UART0_Msk         (0x01 << SYS_CLKEN_UART0_Pos)
+#define SYS_CLKEN_UART1_Pos         12
+#define SYS_CLKEN_UART1_Msk         (0x01 << SYS_CLKEN_UART1_Pos)
+#define SYS_CLKEN_UART2_Pos         13
+#define SYS_CLKEN_UART2_Msk         (0x01 << SYS_CLKEN_UART2_Pos)
+#define SYS_CLKEN_UART3_Pos         14
+#define SYS_CLKEN_UART3_Msk         (0x01 << SYS_CLKEN_UART3_Pos)
+#define SYS_CLKEN_UART4_Pos         15
+#define SYS_CLKEN_UART4_Msk         (0x01 << SYS_CLKEN_UART4_Pos)
+#define SYS_CLKEN_SPI0_Pos          16
+#define SYS_CLKEN_SPI0_Msk          (0x01 << SYS_CLKEN_SPI0_Pos)
+#define SYS_CLKEN_I2C0_Pos          17
+#define SYS_CLKEN_I2C0_Msk          (0x01 << SYS_CLKEN_I2C0_Pos)
+#define SYS_CLKEN_I2C1_Pos          18
+#define SYS_CLKEN_I2C1_Msk          (0x01 << SYS_CLKEN_I2C1_Pos)
+#define SYS_CLKEN_I2C2_Pos          19
+#define SYS_CLKEN_I2C2_Msk          (0x01 << SYS_CLKEN_I2C2_Pos)
+#define SYS_CLKEN_LCD_Pos           20
+#define SYS_CLKEN_LCD_Msk           (0x01 << SYS_CLKEN_LCD_Pos)
+#define SYS_CLKEN_GPIOP_Pos         21
+#define SYS_CLKEN_GPIOP_Msk         (0x01 << SYS_CLKEN_GPIOP_Pos)
+#define SYS_CLKEN_ANAC_Pos          22      //模拟控制单元时钟使能
+#define SYS_CLKEN_ANAC_Msk          (0x01 << SYS_CLKEN_ANAC_Pos)
+#define SYS_CLKEN_CRC_Pos           23
+#define SYS_CLKEN_CRC_Msk           (0x01 << SYS_CLKEN_CRC_Pos)
+#define SYS_CLKEN_RTCBKP_Pos        24
+#define SYS_CLKEN_RTCBKP_Msk        (0x01 << SYS_CLKEN_RTCBKP_Pos)
+#define SYS_CLKEN_CAN_Pos           25
+#define SYS_CLKEN_CAN_Msk           (0x01 << SYS_CLKEN_CAN_Pos)
+#define SYS_CLKEN_SDRAM_Pos         26
+#define SYS_CLKEN_SDRAM_Msk         (0x01 << SYS_CLKEN_SDRAM_Pos)
+#define SYS_CLKEN_NORFL_Pos         27      //NOR Flash
+#define SYS_CLKEN_NORFL_Msk         (0x01 << SYS_CLKEN_NORFL_Pos)
+#define SYS_CLKEN_RAMC_Pos          28
+#define SYS_CLKEN_RAMC_Msk          (0x01 << SYS_CLKEN_RAMC_Pos)
+#define SYS_CLKEN_SDIO_Pos          29
+#define SYS_CLKEN_SDIO_Msk          (0x01 << SYS_CLKEN_SDIO_Pos)
+#define SYS_CLKEN_ADC1_Pos          30
+#define SYS_CLKEN_ADC1_Msk          (0x01 << SYS_CLKEN_ADC1_Pos)
+#define SYS_CLKEN_ALIVE_Pos         31      //CHIPALIVE电源域系统时钟使能
+#define SYS_CLKEN_ALIVE_Msk         (0x01 << SYS_CLKEN_ALIVE_Pos)
+
+#define SYS_SLEEP_SLEEP_Pos         0       //将该位置1后，系统将进入SLEEP模式
+#define SYS_SLEEP_SLEEP_Msk         (0x01 << SYS_SLEEP_SLEEP_Pos)
+#define SYS_SLEEP_DEEP_Pos          1       //将该位置1后，系统将进入STOP SLEEP模式
+#define SYS_SLEEP_DEEP_Msk          (0x01 << SYS_SLEEP_DEEP_Pos)
+
+#define SYS_RSTCR_SYS_Pos           0       //写1进行系统复位，硬件自动清零
+#define SYS_RSTCR_SYS_Msk           (0x01 << SYS_RSTCR_SYS_Pos)
+#define SYS_RSTCR_FLASH_Pos         1       //写1对FLASH控制器进行一次复位，硬件自动清零
+#define SYS_RSTCR_FLASH_Msk         (0x01 << SYS_RSTCR_FLASH_Pos)
+#define SYS_RSTCR_PWM_Pos           2       //写1对PWM进行一次复位，硬件自动清零
+#define SYS_RSTCR_PWM_Msk           (0x01 << SYS_RSTCR_PWM_Pos)
+#define SYS_RSTCR_CPU_Pos           3       //写1对CPU进行一次复位，硬件自动清零
+#define SYS_RSTCR_CPU_Msk           (0x01 << SYS_RSTCR_CPU_Pos)
+#define SYS_RSTCR_DMA_Pos           4       //写1对DMA进行一次复位，硬件自动清零
+#define SYS_RSTCR_DMA_Msk           (0x01 << SYS_RSTCR_DMA_Pos)
+#define SYS_RSTCR_NORFLASH_Pos      5       //写1对NOR Flash控制器进行一次复位，硬件自动清零
+#define SYS_RSTCR_NORFLASH_Msk      (0x01 << SYS_RSTCR_NORFLASH_Pos)
+#define SYS_RSTCR_SRAM_Pos          6       //写1对SRAM控制器进行一次复位，硬件自动清零
+#define SYS_RSTCR_SRAM_Msk          (0x01 << SYS_RSTCR_SRAM_Pos)
+#define SYS_RSTCR_SDRAM_Pos         7       //写1对SDRAM控制器进行一次复位，硬件自动清零
+#define SYS_RSTCR_SDRAM_Msk         (0x01 << SYS_RSTCR_SDRAM_Pos)
+#define SYS_RSTCR_SDIO_Pos          8       //写1对SDIO进行一次复位，硬件自动清零
+#define SYS_RSTCR_SDIO_Msk          (0x01 << SYS_RSTCR_SDIO_Pos)
+#define SYS_RSTCR_LCD_Pos           9       //写1对LCD进行一次复位，硬件自动清零
+#define SYS_RSTCR_LCD_Msk           (0x01 << SYS_RSTCR_LCD_Pos)
+#define SYS_RSTCR_CAN_Pos           10      //写1对CAN进行一次复位，硬件自动清零
+#define SYS_RSTCR_CAN_Msk           (0x01 << SYS_RSTCR_CAN_Pos)
+
+#define SYS_RSTSR_POR_Pos           0       //1 出现过POR复位，写1清零
+#define SYS_RSTSR_POR_Msk           (0x01 << SYS_RSTSR_POR_Pos)
+#define SYS_RSTSR_BOD_Pos           1       //1 出现过BOD复位，写1清零
+#define SYS_RSTSR_BOD_Msk           (0x01 << SYS_RSTSR_BOD_Pos)
+#define SYS_RSTSR_PIN_Pos           2       //1 出现过外部引脚复位，写1清零
+#define SYS_RSTSR_PIN_Msk           (0x01 << SYS_RSTSR_PIN_Pos)
+#define SYS_RSTSR_WDT_Pos           3       //1 出现过WDT复位，写1清零
+#define SYS_RSTSR_WDT_Msk           (0x01 << SYS_RSTSR_WDT_Pos)
+#define SYS_RSTSR_SWRST_Pos         4       //Software Reset, 1 出现过软件复位，写1清零
+#define SYS_RSTSR_SWRST_Msk         (0x01 << SYS_RSTSR_SWRST_Pos)
+
+#define SYS_LRCCR_OFF_Pos           0       //Low Speed RC Off
+#define SYS_LRCCR_OFF_Msk           (0x01 << SYS_LRCCR_OFF_Pos)
+
+#define SYS_LRCTRIM0_R_Pos          0       //LRC粗调控制位
+#define SYS_LRCTRIM0_R_Msk          (0x7FFF << SYS_LRCTRIM0_R_Pos)
+#define SYS_LRCTRIM0_M_Pos          15      //LRC中调控制位
+#define SYS_LRCTRIM0_M_Msk          (0x3F << SYS_LRCTRIM2_M_Pos)
+#define SYS_LRCTRIM0_F_Pos          21      //LRC细调控制位
+#define SYS_LRCTRIM0_F_Msk          (0x7FF << SYS_LRCTRIM0_F_Pos)
+
+#define SYS_LRCTRIM1_U_Pos          0       //LRC U调控制位
+#define SYS_LRCTRIM1_U_Msk          (0x7FFF << SYS_LRCTRIM1_U_Pos)
+
+
+#define SYS_HRCCR_DBL_Pos           0       //Double Frequency  0 20MHz 1 40MHz
+#define SYS_HRCCR_DBL_Msk           (0x01 << SYS_HRCCR_DBL_Pos)
+#define SYS_HRCCR_OFF_Pos           1       //High speed RC Off
+#define SYS_HRCCR_OFF_Msk           (0x01 << SYS_HRCCR_OFF_Pos)
+
+#define SYS_XTALCR_EN_Pos           0
+#define SYS_XTALCR_EN_Msk           (0x01 << SYS_XTALCR_EN_Pos)
+
+#define SYS_PLLCR_OUTEN_Pos         0       //只能LOCK后设置
+#define SYS_PLLCR_OUTEN_Msk         (0x01 << SYS_PLLCR_OUTEN_Pos)
+#define SYS_PLLCR_INSEL_Pos         1       //0 XTAL    1 HRC
+#define SYS_PLLCR_INSEL_Msk         (0x01 << SYS_PLLCR_INSEL_Pos)
+#define SYS_PLLCR_OFF_Pos           2
+#define SYS_PLLCR_OFF_Msk           (0x01 << SYS_PLLCR_OFF_Pos)
+
+#define SYS_PLLDIV_FBDIV_Pos        0       //PLL FeedBack分频寄存器
+                                            //VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV
+                                            //PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV
+#define SYS_PLLDIV_FBDIV_Msk        (0x1FF << SYS_PLLDIV_FBDIV_Pos)
+#define SYS_PLLDIV_ADDIV_Pos        9       //ADC时钟基（即VCO输出分频后的时钟）经ADDIV分频后作为ADC的转换时钟
+#define SYS_PLLDIV_ADDIV_Msk        (0x1F << SYS_PLLDIV_ADDIV_Pos)
+#define SYS_PLLDIV_ADVCO_Pos        14      //0 VCO输出16分频作为ADC时钟基    1 VCO输出经过32分频作为ADC时钟基    2 VCO输出经过64分频作为ADC时钟基
+#define SYS_PLLDIV_ADVCO_Msk        (0x03 << SYS_PLLDIV_ADVCO_Pos)
+#define SYS_PLLDIV_INDIV_Pos        16      //PLL 输入源时钟分频
+#define SYS_PLLDIV_INDIV_Msk        (0x1F << SYS_PLLDIV_INDIV_Pos)
+#define SYS_PLLDIV_OUTDIV_Pos       24      //PLL 输出分频，0 8分频    1 4分频    0 2分频
+#define SYS_PLLDIV_OUTDIV_Msk       (0x03 << SYS_PLLDIV_OUTDIV_Pos)
+
+#define SYS_PLLSET_LPFBW_Pos        0       //PLL Low Pass Filter Bandwidth
+#define SYS_PLLSET_LPFBW_Msk        (0x0F << SYS_PLLSET_LPFBW_Pos)
+#define SYS_PLLSET_BIASADJ_Pos      4       //PLL Current Bias Adjustment
+#define SYS_PLLSET_BIASADJ_Msk      (0x03 << SYS_PLLSET_BIASADJ_Pos)
+#define SYS_PLLSET_REFVSEL_Pos      6       //PLL Reference Voltage Select
+#define SYS_PLLSET_REFVSEL_Msk      (0x03 << SYS_PLLSET_REFVSEL_Pos)
+#define SYS_PLLSET_CHPADJL_Pos      8       //PLL charge pump LSB current Adjustment
+#define SYS_PLLSET_CHPADJL_Msk      (0x07 << SYS_PLLSET_CHPADJL_Pos)
+#define SYS_PLLSET_CHPADJM_Pos      11      //PLL charge pump MSB current Adjustment
+#define SYS_PLLSET_CHPADJM_Msk      (0x03 << SYS_PLLSET_CHPADJM_Pos)
+
+#define SYS_BODIE_2V2_Pos           1       //BOD 2.2V等级触发中断使能
+#define SYS_BODIE_2V2_Msk           (0x01 << SYS_BODIE_2V2_Pos)
+
+#define SYS_BODIF_2V2_Pos           1       //BOD 2.2V等级触发中断状态，写1清零
+#define SYS_BODIF_2V2_Msk           (0x01 << SYS_BODIF_2V2_Pos)
+
+#define SYS_ADC1IN7_SEL_Pos         0       //ADC1模块模拟通道7，1 温度传感器    2 电池电压    3 RTC电源域BG    4 主电源域BG   5 PDM33
+#define SYS_ADC1IN7_SEL_Msk         (0x0F << SYS_ADC1IN7_SEL_Pos)
+#define SYS_ADC1IN7_IOON_Pos        4       //ADC1模块模拟通道7所用IO开关
+#define SYS_ADC1IN7_IOON_Msk        (0x01 << SYS_ADC1IN7_IOON_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t PORTA_SEL;                //给PORTA_SEL[2n+2:2n]赋相应的值，将PORTA.PINn引脚配置成GPIO、模拟、数字等功能
+                                            //当赋值为PORTA_PINn_FUNMUX时，PORTA.PINn引脚可通过PORTA_MUX寄存器连接到各种数字外设
+    __IO uint32_t PORTB_SEL;
+
+    __IO uint32_t PORTC_SEL;
+
+         uint32_t RESERVED[5];
+
+    __IO uint32_t PORTM_SEL0;
+
+    __IO uint32_t PORTM_SEL1;
+
+         uint32_t RESERVED2[2];
+
+    __IO uint32_t PORTN_SEL0;
+
+    __IO uint32_t PORTN_SEL1;
+
+         uint32_t RESERVED3[2];
+
+    __IO uint32_t PORTP_SEL0;
+
+    __IO uint32_t PORTP_SEL1;
+
+         uint32_t RESERVED4[46];
+
+    __IO uint32_t PORTA_MUX0;
+
+    __IO uint32_t PORTA_MUX1;
+
+         uint32_t RESERVED5[2];
+
+    __IO uint32_t PORTB_MUX0;
+
+    __IO uint32_t PORTB_MUX1;
+
+         uint32_t RESERVED6[2];
+
+    __IO uint32_t PORTC_MUX0;
+
+    __IO uint32_t PORTC_MUX1;
+
+         uint32_t RESERVED7[14];
+
+    __IO uint32_t PORTM_MUX0;
+
+    __IO uint32_t PORTM_MUX1;
+
+    __IO uint32_t PORTM_MUX2;
+
+    __IO uint32_t PORTM_MUX3;
+
+    __IO uint32_t PORTN_MUX0;
+
+    __IO uint32_t PORTN_MUX1;
+
+    __IO uint32_t PORTN_MUX2;
+
+         uint32_t RESERVED8;
+
+    __IO uint32_t PORTP_MUX0;
+
+    __IO uint32_t PORTP_MUX1;
+
+    __IO uint32_t PORTP_MUX2;
+
+    __IO uint32_t PORTP_MUX3;
+
+         uint32_t RESERVED9[28];
+
+    __IO uint32_t PORTA_PULLU;              //上拉使能
+
+         uint32_t RESERVED10[3];
+
+    __IO uint32_t PORTC_PULLU;
+
+         uint32_t RESERVED11[3];
+
+    __IO uint32_t PORTM_PULLU;
+
+         uint32_t RESERVED12[3];
+
+    __IO uint32_t PORTP_PULLU;
+
+         uint32_t RESERVED13[51];
+
+    __IO uint32_t PORTB_PULLD;              //下拉使能
+
+         uint32_t RESERVED14[3];
+
+    __IO uint32_t PORTD_PULLD;
+
+         uint32_t RESERVED15[3];
+
+    __IO uint32_t PORTN_PULLD;
+
+         uint32_t RESERVED16[135];
+
+    __IO uint32_t PORTM_DRIVS;              //驱动强度
+
+         uint32_t RESERVED17[3];
+
+    __IO uint32_t PORTN_DRIVS;
+
+         uint32_t RESERVED18[3];
+
+    __IO uint32_t PORTP_DRIVS;
+
+         uint32_t RESERVED19[39];
+
+    __IO uint32_t PORTA_INEN;               //输入使能
+
+         uint32_t RESERVED20[3];
+
+    __IO uint32_t PORTB_INEN;
+
+         uint32_t RESERVED21[3];
+
+    __IO uint32_t PORTC_INEN;
+
+         uint32_t RESERVED22[7];
+
+    __IO uint32_t PORTM_INEN;
+
+         uint32_t RESERVED23[3];
+
+    __IO uint32_t PORTN_INEN;
+
+         uint32_t RESERVED24[3];
+
+    __IO uint32_t PORTP_INEN;
+} PORT_TypeDef;
+
+
+#define PORT_PORTA_PULLU_PIN0_Pos   0
+#define PORT_PORTA_PULLU_PIN0_Msk   (0x01 << PORT_PORTA_PULLU_PIN0_Pos)
+#define PORT_PORTA_PULLU_PIN1_Pos   1
+#define PORT_PORTA_PULLU_PIN1_Msk   (0x01 << PORT_PORTA_PULLU_PIN1_Pos)
+#define PORT_PORTA_PULLU_PIN2_Pos   2
+#define PORT_PORTA_PULLU_PIN2_Msk   (0x01 << PORT_PORTA_PULLU_PIN2_Pos)
+#define PORT_PORTA_PULLU_PIN3_Pos   3
+#define PORT_PORTA_PULLU_PIN3_Msk   (0x01 << PORT_PORTA_PULLU_PIN3_Pos)
+#define PORT_PORTA_PULLU_PIN4_Pos   4
+#define PORT_PORTA_PULLU_PIN4_Msk   (0x01 << PORT_PORTA_PULLU_PIN4_Pos)
+#define PORT_PORTA_PULLU_PIN5_Pos   5
+#define PORT_PORTA_PULLU_PIN5_Msk   (0x01 << PORT_PORTA_PULLU_PIN5_Pos)
+#define PORT_PORTA_PULLU_PIN6_Pos   6
+#define PORT_PORTA_PULLU_PIN6_Msk   (0x01 << PORT_PORTA_PULLU_PIN6_Pos)
+#define PORT_PORTA_PULLU_PIN7_Pos   7
+#define PORT_PORTA_PULLU_PIN7_Msk   (0x01 << PORT_PORTA_PULLU_PIN7_Pos)
+#define PORT_PORTA_PULLU_PIN8_Pos   8
+#define PORT_PORTA_PULLU_PIN8_Msk   (0x01 << PORT_PORTA_PULLU_PIN8_Pos)
+#define PORT_PORTA_PULLU_PIN9_Pos   9
+#define PORT_PORTA_PULLU_PIN9_Msk   (0x01 << PORT_PORTA_PULLU_PIN9_Pos)
+#define PORT_PORTA_PULLU_PIN10_Pos  10
+#define PORT_PORTA_PULLU_PIN10_Msk  (0x01 << PORT_PORTA_PULLU_PIN10_Pos)
+#define PORT_PORTA_PULLU_PIN11_Pos  11
+#define PORT_PORTA_PULLU_PIN11_Msk  (0x01 << PORT_PORTA_PULLU_PIN11_Pos)
+#define PORT_PORTA_PULLU_PIN12_Pos  12
+#define PORT_PORTA_PULLU_PIN12_Msk  (0x01 << PORT_PORTA_PULLU_PIN12_Pos)
+#define PORT_PORTA_PULLU_PIN13_Pos  13
+#define PORT_PORTA_PULLU_PIN13_Msk  (0x01 << PORT_PORTA_PULLU_PIN13_Pos)
+#define PORT_PORTA_PULLU_PIN14_Pos  14
+#define PORT_PORTA_PULLU_PIN14_Msk  (0x01 << PORT_PORTA_PULLU_PIN14_Pos)
+#define PORT_PORTA_PULLU_PIN15_Pos  15
+#define PORT_PORTA_PULLU_PIN15_Msk  (0x01 << PORT_PORTA_PULLU_PIN15_Pos)
+
+#define PORT_PORTC_PULLU_PIN0_Pos   0
+#define PORT_PORTC_PULLU_PIN0_Msk   (0x01 << PORT_PORTC_PULLU_PIN0_Pos)
+#define PORT_PORTC_PULLU_PIN1_Pos   1
+#define PORT_PORTC_PULLU_PIN1_Msk   (0x01 << PORT_PORTC_PULLU_PIN1_Pos)
+#define PORT_PORTC_PULLU_PIN2_Pos   2
+#define PORT_PORTC_PULLU_PIN2_Msk   (0x01 << PORT_PORTC_PULLU_PIN2_Pos)
+#define PORT_PORTC_PULLU_PIN3_Pos   3
+#define PORT_PORTC_PULLU_PIN3_Msk   (0x01 << PORT_PORTC_PULLU_PIN3_Pos)
+#define PORT_PORTC_PULLU_PIN4_Pos   4
+#define PORT_PORTC_PULLU_PIN4_Msk   (0x01 << PORT_PORTC_PULLU_PIN4_Pos)
+#define PORT_PORTC_PULLU_PIN5_Pos   5
+#define PORT_PORTC_PULLU_PIN5_Msk   (0x01 << PORT_PORTC_PULLU_PIN5_Pos)
+#define PORT_PORTC_PULLU_PIN6_Pos   6
+#define PORT_PORTC_PULLU_PIN6_Msk   (0x01 << PORT_PORTC_PULLU_PIN6_Pos)
+#define PORT_PORTC_PULLU_PIN7_Pos   7
+#define PORT_PORTC_PULLU_PIN7_Msk   (0x01 << PORT_PORTC_PULLU_PIN7_Pos)
+#define PORT_PORTC_PULLU_PIN8_Pos   8
+#define PORT_PORTC_PULLU_PIN8_Msk   (0x01 << PORT_PORTC_PULLU_PIN8_Pos)
+#define PORT_PORTC_PULLU_PIN9_Pos   9
+#define PORT_PORTC_PULLU_PIN9_Msk   (0x01 << PORT_PORTC_PULLU_PIN9_Pos)
+#define PORT_PORTC_PULLU_PIN10_Pos  10
+#define PORT_PORTC_PULLU_PIN10_Msk  (0x01 << PORT_PORTC_PULLU_PIN10_Pos)
+#define PORT_PORTC_PULLU_PIN11_Pos  11
+#define PORT_PORTC_PULLU_PIN11_Msk  (0x01 << PORT_PORTC_PULLU_PIN11_Pos)
+#define PORT_PORTC_PULLU_PIN12_Pos  12
+#define PORT_PORTC_PULLU_PIN12_Msk  (0x01 << PORT_PORTC_PULLU_PIN12_Pos)
+#define PORT_PORTC_PULLU_PIN13_Pos  13
+#define PORT_PORTC_PULLU_PIN13_Msk  (0x01 << PORT_PORTC_PULLU_PIN13_Pos)
+#define PORT_PORTC_PULLU_PIN14_Pos  14
+#define PORT_PORTC_PULLU_PIN14_Msk  (0x01 << PORT_PORTC_PULLU_PIN14_Pos)
+#define PORT_PORTC_PULLU_PIN15_Pos  15
+#define PORT_PORTC_PULLU_PIN15_Msk  (0x01 << PORT_PORTC_PULLU_PIN15_Pos)
+
+#define PORT_PORTM_PULLU_PIN0_Pos   0
+#define PORT_PORTM_PULLU_PIN0_Msk   (0x01 << PORT_PORTM_PULLU_PIN0_Pos)
+#define PORT_PORTM_PULLU_PIN1_Pos   1
+#define PORT_PORTM_PULLU_PIN1_Msk   (0x01 << PORT_PORTM_PULLU_PIN1_Pos)
+#define PORT_PORTM_PULLU_PIN2_Pos   2
+#define PORT_PORTM_PULLU_PIN2_Msk   (0x01 << PORT_PORTM_PULLU_PIN2_Pos)
+#define PORT_PORTM_PULLU_PIN3_Pos   3
+#define PORT_PORTM_PULLU_PIN3_Msk   (0x01 << PORT_PORTM_PULLU_PIN3_Pos)
+#define PORT_PORTM_PULLU_PIN4_Pos   4
+#define PORT_PORTM_PULLU_PIN4_Msk   (0x01 << PORT_PORTM_PULLU_PIN4_Pos)
+#define PORT_PORTM_PULLU_PIN5_Pos   5
+#define PORT_PORTM_PULLU_PIN5_Msk   (0x01 << PORT_PORTM_PULLU_PIN5_Pos)
+#define PORT_PORTM_PULLU_PIN6_Pos   6
+#define PORT_PORTM_PULLU_PIN6_Msk   (0x01 << PORT_PORTM_PULLU_PIN6_Pos)
+#define PORT_PORTM_PULLU_PIN7_Pos   7
+#define PORT_PORTM_PULLU_PIN7_Msk   (0x01 << PORT_PORTM_PULLU_PIN7_Pos)
+#define PORT_PORTM_PULLU_PIN8_Pos   8
+#define PORT_PORTM_PULLU_PIN8_Msk   (0x01 << PORT_PORTM_PULLU_PIN8_Pos)
+#define PORT_PORTM_PULLU_PIN9_Pos   9
+#define PORT_PORTM_PULLU_PIN9_Msk   (0x01 << PORT_PORTM_PULLU_PIN9_Pos)
+#define PORT_PORTM_PULLU_PIN10_Pos  10
+#define PORT_PORTM_PULLU_PIN10_Msk  (0x01 << PORT_PORTM_PULLU_PIN10_Pos)
+#define PORT_PORTM_PULLU_PIN11_Pos  11
+#define PORT_PORTM_PULLU_PIN11_Msk  (0x01 << PORT_PORTM_PULLU_PIN11_Pos)
+#define PORT_PORTM_PULLU_PIN12_Pos  12
+#define PORT_PORTM_PULLU_PIN12_Msk  (0x01 << PORT_PORTM_PULLU_PIN12_Pos)
+#define PORT_PORTM_PULLU_PIN13_Pos  13
+#define PORT_PORTM_PULLU_PIN13_Msk  (0x01 << PORT_PORTM_PULLU_PIN13_Pos)
+#define PORT_PORTM_PULLU_PIN14_Pos  14
+#define PORT_PORTM_PULLU_PIN14_Msk  (0x01 << PORT_PORTM_PULLU_PIN14_Pos)
+#define PORT_PORTM_PULLU_PIN15_Pos  15
+#define PORT_PORTM_PULLU_PIN15_Msk  (0x01 << PORT_PORTM_PULLU_PIN15_Pos)
+#define PORT_PORTM_PULLU_PIN16_Pos  16
+#define PORT_PORTM_PULLU_PIN16_Msk  (0x01 << PORT_PORTM_PULLU_PIN16_Pos)
+#define PORT_PORTM_PULLU_PIN17_Pos  17
+#define PORT_PORTM_PULLU_PIN17_Msk  (0x01 << PORT_PORTM_PULLU_PIN17_Pos)
+#define PORT_PORTM_PULLU_PIN18_Pos  18
+#define PORT_PORTM_PULLU_PIN18_Msk  (0x01 << PORT_PORTM_PULLU_PIN18_Pos)
+#define PORT_PORTM_PULLU_PIN19_Pos  19
+#define PORT_PORTM_PULLU_PIN19_Msk  (0x01 << PORT_PORTM_PULLU_PIN19_Pos)
+#define PORT_PORTM_PULLU_PIN20_Pos  20
+#define PORT_PORTM_PULLU_PIN20_Msk  (0x01 << PORT_PORTM_PULLU_PIN20_Pos)
+#define PORT_PORTM_PULLU_PIN21_Pos  21
+#define PORT_PORTM_PULLU_PIN21_Msk  (0x01 << PORT_PORTM_PULLU_PIN21_Pos)
+#define PORT_PORTM_PULLU_PIN22_Pos  22
+#define PORT_PORTM_PULLU_PIN22_Msk  (0x01 << PORT_PORTM_PULLU_PIN22_Pos)
+#define PORT_PORTM_PULLU_PIN23_Pos  23
+#define PORT_PORTM_PULLU_PIN23_Msk  (0x01 << PORT_PORTM_PULLU_PIN23_Pos)
+
+#define PORT_PORTP_PULLU_PIN0_Pos   0
+#define PORT_PORTP_PULLU_PIN0_Msk   (0x01 << PORT_PORTP_PULLU_PIN0_Pos)
+#define PORT_PORTP_PULLU_PIN1_Pos   1
+#define PORT_PORTP_PULLU_PIN1_Msk   (0x01 << PORT_PORTP_PULLU_PIN1_Pos)
+#define PORT_PORTP_PULLU_PIN2_Pos   2
+#define PORT_PORTP_PULLU_PIN2_Msk   (0x01 << PORT_PORTP_PULLU_PIN2_Pos)
+#define PORT_PORTP_PULLU_PIN3_Pos   3
+#define PORT_PORTP_PULLU_PIN3_Msk   (0x01 << PORT_PORTP_PULLU_PIN3_Pos)
+#define PORT_PORTP_PULLU_PIN4_Pos   4
+#define PORT_PORTP_PULLU_PIN4_Msk   (0x01 << PORT_PORTP_PULLU_PIN4_Pos)
+#define PORT_PORTP_PULLU_PIN5_Pos   5
+#define PORT_PORTP_PULLU_PIN5_Msk   (0x01 << PORT_PORTP_PULLU_PIN5_Pos)
+#define PORT_PORTP_PULLU_PIN6_Pos   6
+#define PORT_PORTP_PULLU_PIN6_Msk   (0x01 << PORT_PORTP_PULLU_PIN6_Pos)
+#define PORT_PORTP_PULLU_PIN7_Pos   7
+#define PORT_PORTP_PULLU_PIN7_Msk   (0x01 << PORT_PORTP_PULLU_PIN7_Pos)
+#define PORT_PORTP_PULLU_PIN8_Pos   8
+#define PORT_PORTP_PULLU_PIN8_Msk   (0x01 << PORT_PORTP_PULLU_PIN8_Pos)
+#define PORT_PORTP_PULLU_PIN9_Pos   9
+#define PORT_PORTP_PULLU_PIN9_Msk   (0x01 << PORT_PORTP_PULLU_PIN9_Pos)
+#define PORT_PORTP_PULLU_PIN10_Pos  10
+#define PORT_PORTP_PULLU_PIN10_Msk  (0x01 << PORT_PORTP_PULLU_PIN10_Pos)
+#define PORT_PORTP_PULLU_PIN11_Pos  11
+#define PORT_PORTP_PULLU_PIN11_Msk  (0x01 << PORT_PORTP_PULLU_PIN11_Pos)
+#define PORT_PORTP_PULLU_PIN12_Pos  12
+#define PORT_PORTP_PULLU_PIN12_Msk  (0x01 << PORT_PORTP_PULLU_PIN12_Pos)
+#define PORT_PORTP_PULLU_PIN13_Pos  13
+#define PORT_PORTP_PULLU_PIN13_Msk  (0x01 << PORT_PORTP_PULLU_PIN13_Pos)
+#define PORT_PORTP_PULLU_PIN14_Pos  14
+#define PORT_PORTP_PULLU_PIN14_Msk  (0x01 << PORT_PORTP_PULLU_PIN14_Pos)
+#define PORT_PORTP_PULLU_PIN15_Pos  15
+#define PORT_PORTP_PULLU_PIN15_Msk  (0x01 << PORT_PORTP_PULLU_PIN15_Pos)
+#define PORT_PORTP_PULLU_PIN16_Pos  16
+#define PORT_PORTP_PULLU_PIN16_Msk  (0x01 << PORT_PORTP_PULLU_PIN16_Pos)
+#define PORT_PORTP_PULLU_PIN17_Pos  17
+#define PORT_PORTP_PULLU_PIN17_Msk  (0x01 << PORT_PORTP_PULLU_PIN17_Pos)
+#define PORT_PORTP_PULLU_PIN18_Pos  18
+#define PORT_PORTP_PULLU_PIN18_Msk  (0x01 << PORT_PORTP_PULLU_PIN18_Pos)
+#define PORT_PORTP_PULLU_PIN19_Pos  19
+#define PORT_PORTP_PULLU_PIN19_Msk  (0x01 << PORT_PORTP_PULLU_PIN19_Pos)
+#define PORT_PORTP_PULLU_PIN20_Pos  20
+#define PORT_PORTP_PULLU_PIN20_Msk  (0x01 << PORT_PORTP_PULLU_PIN20_Pos)
+#define PORT_PORTP_PULLU_PIN21_Pos  21
+#define PORT_PORTP_PULLU_PIN21_Msk  (0x01 << PORT_PORTP_PULLU_PIN21_Pos)
+#define PORT_PORTP_PULLU_PIN22_Pos  22
+#define PORT_PORTP_PULLU_PIN22_Msk  (0x01 << PORT_PORTP_PULLU_PIN22_Pos)
+#define PORT_PORTP_PULLU_PIN23_Pos  23
+#define PORT_PORTP_PULLU_PIN23_Msk  (0x01 << PORT_PORTP_PULLU_PIN23_Pos)
+
+#define PORT_PORTB_PULLD_PIN0_Pos   0
+#define PORT_PORTB_PULLD_PIN0_Msk   (0x01 << PORT_PORTB_PULLD_PIN0_Pos)
+#define PORT_PORTB_PULLD_PIN1_Pos   1
+#define PORT_PORTB_PULLD_PIN1_Msk   (0x01 << PORT_PORTB_PULLD_PIN1_Pos)
+#define PORT_PORTB_PULLD_PIN2_Pos   2
+#define PORT_PORTB_PULLD_PIN2_Msk   (0x01 << PORT_PORTB_PULLD_PIN2_Pos)
+#define PORT_PORTB_PULLD_PIN3_Pos   3
+#define PORT_PORTB_PULLD_PIN3_Msk   (0x01 << PORT_PORTB_PULLD_PIN3_Pos)
+#define PORT_PORTB_PULLD_PIN4_Pos   4
+#define PORT_PORTB_PULLD_PIN4_Msk   (0x01 << PORT_PORTB_PULLD_PIN4_Pos)
+#define PORT_PORTB_PULLD_PIN5_Pos   5
+#define PORT_PORTB_PULLD_PIN5_Msk   (0x01 << PORT_PORTB_PULLD_PIN5_Pos)
+#define PORT_PORTB_PULLD_PIN6_Pos   6
+#define PORT_PORTB_PULLD_PIN6_Msk   (0x01 << PORT_PORTB_PULLD_PIN6_Pos)
+#define PORT_PORTB_PULLD_PIN7_Pos   7
+#define PORT_PORTB_PULLD_PIN7_Msk   (0x01 << PORT_PORTB_PULLD_PIN7_Pos)
+#define PORT_PORTB_PULLD_PIN8_Pos   8
+#define PORT_PORTB_PULLD_PIN8_Msk   (0x01 << PORT_PORTB_PULLD_PIN8_Pos)
+#define PORT_PORTB_PULLD_PIN9_Pos   9
+#define PORT_PORTB_PULLD_PIN9_Msk   (0x01 << PORT_PORTB_PULLD_PIN9_Pos)
+#define PORT_PORTB_PULLD_PIN10_Pos  10
+#define PORT_PORTB_PULLD_PIN10_Msk  (0x01 << PORT_PORTB_PULLD_PIN10_Pos)
+#define PORT_PORTB_PULLD_PIN11_Pos  11
+#define PORT_PORTB_PULLD_PIN11_Msk  (0x01 << PORT_PORTB_PULLD_PIN11_Pos)
+#define PORT_PORTB_PULLD_PIN12_Pos  12
+#define PORT_PORTB_PULLD_PIN12_Msk  (0x01 << PORT_PORTB_PULLD_PIN12_Pos)
+#define PORT_PORTB_PULLD_PIN13_Pos  13
+#define PORT_PORTB_PULLD_PIN13_Msk  (0x01 << PORT_PORTB_PULLD_PIN13_Pos)
+#define PORT_PORTB_PULLD_PIN14_Pos  14
+#define PORT_PORTB_PULLD_PIN14_Msk  (0x01 << PORT_PORTB_PULLD_PIN14_Pos)
+#define PORT_PORTB_PULLD_PIN15_Pos  15
+#define PORT_PORTB_PULLD_PIN15_Msk  (0x01 << PORT_PORTB_PULLD_PIN15_Pos)
+
+#define PORT_PORTN_PULLD_PIN0_Pos   0
+#define PORT_PORTN_PULLD_PIN0_Msk   (0x01 << PORT_PORTN_PULLD_PIN0_Pos)
+#define PORT_PORTN_PULLD_PIN1_Pos   1
+#define PORT_PORTN_PULLD_PIN1_Msk   (0x01 << PORT_PORTN_PULLD_PIN1_Pos)
+#define PORT_PORTN_PULLD_PIN2_Pos   2
+#define PORT_PORTN_PULLD_PIN2_Msk   (0x01 << PORT_PORTN_PULLD_PIN2_Pos)
+#define PORT_PORTN_PULLD_PIN3_Pos   3
+#define PORT_PORTN_PULLD_PIN3_Msk   (0x01 << PORT_PORTN_PULLD_PIN3_Pos)
+#define PORT_PORTN_PULLD_PIN4_Pos   4
+#define PORT_PORTN_PULLD_PIN4_Msk   (0x01 << PORT_PORTN_PULLD_PIN4_Pos)
+#define PORT_PORTN_PULLD_PIN5_Pos   5
+#define PORT_PORTN_PULLD_PIN5_Msk   (0x01 << PORT_PORTN_PULLD_PIN5_Pos)
+#define PORT_PORTN_PULLD_PIN6_Pos   6
+#define PORT_PORTN_PULLD_PIN6_Msk   (0x01 << PORT_PORTN_PULLD_PIN6_Pos)
+#define PORT_PORTN_PULLD_PIN7_Pos   7
+#define PORT_PORTN_PULLD_PIN7_Msk   (0x01 << PORT_PORTN_PULLD_PIN7_Pos)
+#define PORT_PORTN_PULLD_PIN8_Pos   8
+#define PORT_PORTN_PULLD_PIN8_Msk   (0x01 << PORT_PORTN_PULLD_PIN8_Pos)
+#define PORT_PORTN_PULLD_PIN9_Pos   9
+#define PORT_PORTN_PULLD_PIN9_Msk   (0x01 << PORT_PORTN_PULLD_PIN9_Pos)
+#define PORT_PORTN_PULLD_PIN10_Pos  10
+#define PORT_PORTN_PULLD_PIN10_Msk  (0x01 << PORT_PORTN_PULLD_PIN10_Pos)
+#define PORT_PORTN_PULLD_PIN11_Pos  11
+#define PORT_PORTN_PULLD_PIN11_Msk  (0x01 << PORT_PORTN_PULLD_PIN11_Pos)
+#define PORT_PORTN_PULLD_PIN12_Pos  12
+#define PORT_PORTN_PULLD_PIN12_Msk  (0x01 << PORT_PORTN_PULLD_PIN12_Pos)
+#define PORT_PORTN_PULLD_PIN13_Pos  13
+#define PORT_PORTN_PULLD_PIN13_Msk  (0x01 << PORT_PORTN_PULLD_PIN13_Pos)
+#define PORT_PORTN_PULLD_PIN14_Pos  14
+#define PORT_PORTN_PULLD_PIN14_Msk  (0x01 << PORT_PORTN_PULLD_PIN14_Pos)
+#define PORT_PORTN_PULLD_PIN15_Pos  15
+#define PORT_PORTN_PULLD_PIN15_Msk  (0x01 << PORT_PORTN_PULLD_PIN15_Pos)
+#define PORT_PORTN_PULLD_PIN16_Pos  16
+#define PORT_PORTN_PULLD_PIN16_Msk  (0x01 << PORT_PORTN_PULLD_PIN16_Pos)
+#define PORT_PORTN_PULLD_PIN17_Pos  17
+#define PORT_PORTN_PULLD_PIN17_Msk  (0x01 << PORT_PORTN_PULLD_PIN17_Pos)
+#define PORT_PORTN_PULLD_PIN18_Pos  18
+#define PORT_PORTN_PULLD_PIN18_Msk  (0x01 << PORT_PORTN_PULLD_PIN18_Pos)
+#define PORT_PORTN_PULLD_PIN19_Pos  19
+#define PORT_PORTN_PULLD_PIN19_Msk  (0x01 << PORT_PORTN_PULLD_PIN19_Pos)
+#define PORT_PORTN_PULLD_PIN20_Pos  20
+#define PORT_PORTN_PULLD_PIN20_Msk  (0x01 << PORT_PORTN_PULLD_PIN20_Pos)
+#define PORT_PORTN_PULLD_PIN21_Pos  21
+#define PORT_PORTN_PULLD_PIN21_Msk  (0x01 << PORT_PORTN_PULLD_PIN21_Pos)
+#define PORT_PORTN_PULLD_PIN22_Pos  22
+#define PORT_PORTN_PULLD_PIN22_Msk  (0x01 << PORT_PORTN_PULLD_PIN22_Pos)
+#define PORT_PORTN_PULLD_PIN23_Pos  23
+#define PORT_PORTN_PULLD_PIN23_Msk  (0x01 << PORT_PORTN_PULLD_PIN23_Pos)
+
+#define PORT_PORTM_DRIVS_PIN0_Pos   0
+#define PORT_PORTM_DRIVS_PIN0_Msk   (0x01 << PORT_PORTM_DRIVS_PIN0_Pos)
+#define PORT_PORTM_DRIVS_PIN1_Pos   1
+#define PORT_PORTM_DRIVS_PIN1_Msk   (0x01 << PORT_PORTM_DRIVS_PIN1_Pos)
+#define PORT_PORTM_DRIVS_PIN2_Pos   2
+#define PORT_PORTM_DRIVS_PIN2_Msk   (0x01 << PORT_PORTM_DRIVS_PIN2_Pos)
+#define PORT_PORTM_DRIVS_PIN3_Pos   3
+#define PORT_PORTM_DRIVS_PIN3_Msk   (0x01 << PORT_PORTM_DRIVS_PIN3_Pos)
+#define PORT_PORTM_DRIVS_PIN4_Pos   4
+#define PORT_PORTM_DRIVS_PIN4_Msk   (0x01 << PORT_PORTM_DRIVS_PIN4_Pos)
+#define PORT_PORTM_DRIVS_PIN5_Pos   5
+#define PORT_PORTM_DRIVS_PIN5_Msk   (0x01 << PORT_PORTM_DRIVS_PIN5_Pos)
+#define PORT_PORTM_DRIVS_PIN6_Pos   6
+#define PORT_PORTM_DRIVS_PIN6_Msk   (0x01 << PORT_PORTM_DRIVS_PIN6_Pos)
+#define PORT_PORTM_DRIVS_PIN7_Pos   7
+#define PORT_PORTM_DRIVS_PIN7_Msk   (0x01 << PORT_PORTM_DRIVS_PIN7_Pos)
+#define PORT_PORTM_DRIVS_PIN8_Pos   8
+#define PORT_PORTM_DRIVS_PIN8_Msk   (0x01 << PORT_PORTM_DRIVS_PIN8_Pos)
+#define PORT_PORTM_DRIVS_PIN9_Pos   9
+#define PORT_PORTM_DRIVS_PIN9_Msk   (0x01 << PORT_PORTM_DRIVS_PIN9_Pos)
+#define PORT_PORTM_DRIVS_PIN10_Pos  10
+#define PORT_PORTM_DRIVS_PIN10_Msk  (0x01 << PORT_PORTM_DRIVS_PIN10_Pos)
+#define PORT_PORTM_DRIVS_PIN11_Pos  11
+#define PORT_PORTM_DRIVS_PIN11_Msk  (0x01 << PORT_PORTM_DRIVS_PIN11_Pos)
+#define PORT_PORTM_DRIVS_PIN12_Pos  12
+#define PORT_PORTM_DRIVS_PIN12_Msk  (0x01 << PORT_PORTM_DRIVS_PIN12_Pos)
+#define PORT_PORTM_DRIVS_PIN13_Pos  13
+#define PORT_PORTM_DRIVS_PIN13_Msk  (0x01 << PORT_PORTM_DRIVS_PIN13_Pos)
+#define PORT_PORTM_DRIVS_PIN14_Pos  14
+#define PORT_PORTM_DRIVS_PIN14_Msk  (0x01 << PORT_PORTM_DRIVS_PIN14_Pos)
+#define PORT_PORTM_DRIVS_PIN15_Pos  15
+#define PORT_PORTM_DRIVS_PIN15_Msk  (0x01 << PORT_PORTM_DRIVS_PIN15_Pos)
+#define PORT_PORTM_DRIVS_PIN16_Pos  16
+#define PORT_PORTM_DRIVS_PIN16_Msk  (0x01 << PORT_PORTM_DRIVS_PIN16_Pos)
+#define PORT_PORTM_DRIVS_PIN17_Pos  17
+#define PORT_PORTM_DRIVS_PIN17_Msk  (0x01 << PORT_PORTM_DRIVS_PIN17_Pos)
+#define PORT_PORTM_DRIVS_PIN18_Pos  18
+#define PORT_PORTM_DRIVS_PIN18_Msk  (0x01 << PORT_PORTM_DRIVS_PIN18_Pos)
+#define PORT_PORTM_DRIVS_PIN19_Pos  19
+#define PORT_PORTM_DRIVS_PIN19_Msk  (0x01 << PORT_PORTM_DRIVS_PIN19_Pos)
+#define PORT_PORTM_DRIVS_PIN20_Pos  20
+#define PORT_PORTM_DRIVS_PIN20_Msk  (0x01 << PORT_PORTM_DRIVS_PIN20_Pos)
+#define PORT_PORTM_DRIVS_PIN21_Pos  21
+#define PORT_PORTM_DRIVS_PIN21_Msk  (0x01 << PORT_PORTM_DRIVS_PIN21_Pos)
+#define PORT_PORTM_DRIVS_PIN22_Pos  22
+#define PORT_PORTM_DRIVS_PIN22_Msk  (0x01 << PORT_PORTM_DRIVS_PIN22_Pos)
+#define PORT_PORTM_DRIVS_PIN23_Pos  23
+#define PORT_PORTM_DRIVS_PIN23_Msk  (0x01 << PORT_PORTM_DRIVS_PIN23_Pos)
+
+#define PORT_PORTN_DRIVS_PIN0_Pos   0
+#define PORT_PORTN_DRIVS_PIN0_Msk   (0x01 << PORT_PORTN_DRIVS_PIN0_Pos)
+#define PORT_PORTN_DRIVS_PIN1_Pos   1
+#define PORT_PORTN_DRIVS_PIN1_Msk   (0x01 << PORT_PORTN_DRIVS_PIN1_Pos)
+#define PORT_PORTN_DRIVS_PIN2_Pos   2
+#define PORT_PORTN_DRIVS_PIN2_Msk   (0x01 << PORT_PORTN_DRIVS_PIN2_Pos)
+#define PORT_PORTN_DRIVS_PIN3_Pos   3
+#define PORT_PORTN_DRIVS_PIN3_Msk   (0x01 << PORT_PORTN_DRIVS_PIN3_Pos)
+#define PORT_PORTN_DRIVS_PIN4_Pos   4
+#define PORT_PORTN_DRIVS_PIN4_Msk   (0x01 << PORT_PORTN_DRIVS_PIN4_Pos)
+#define PORT_PORTN_DRIVS_PIN5_Pos   5
+#define PORT_PORTN_DRIVS_PIN5_Msk   (0x01 << PORT_PORTN_DRIVS_PIN5_Pos)
+#define PORT_PORTN_DRIVS_PIN6_Pos   6
+#define PORT_PORTN_DRIVS_PIN6_Msk   (0x01 << PORT_PORTN_DRIVS_PIN6_Pos)
+#define PORT_PORTN_DRIVS_PIN7_Pos   7
+#define PORT_PORTN_DRIVS_PIN7_Msk   (0x01 << PORT_PORTN_DRIVS_PIN7_Pos)
+#define PORT_PORTN_DRIVS_PIN8_Pos   8
+#define PORT_PORTN_DRIVS_PIN8_Msk   (0x01 << PORT_PORTN_DRIVS_PIN8_Pos)
+#define PORT_PORTN_DRIVS_PIN9_Pos   9
+#define PORT_PORTN_DRIVS_PIN9_Msk   (0x01 << PORT_PORTN_DRIVS_PIN9_Pos)
+#define PORT_PORTN_DRIVS_PIN10_Pos  10
+#define PORT_PORTN_DRIVS_PIN10_Msk  (0x01 << PORT_PORTN_DRIVS_PIN10_Pos)
+#define PORT_PORTN_DRIVS_PIN11_Pos  11
+#define PORT_PORTN_DRIVS_PIN11_Msk  (0x01 << PORT_PORTN_DRIVS_PIN11_Pos)
+#define PORT_PORTN_DRIVS_PIN12_Pos  12
+#define PORT_PORTN_DRIVS_PIN12_Msk  (0x01 << PORT_PORTN_DRIVS_PIN12_Pos)
+#define PORT_PORTN_DRIVS_PIN13_Pos  13
+#define PORT_PORTN_DRIVS_PIN13_Msk  (0x01 << PORT_PORTN_DRIVS_PIN13_Pos)
+#define PORT_PORTN_DRIVS_PIN14_Pos  14
+#define PORT_PORTN_DRIVS_PIN14_Msk  (0x01 << PORT_PORTN_DRIVS_PIN14_Pos)
+#define PORT_PORTN_DRIVS_PIN15_Pos  15
+#define PORT_PORTN_DRIVS_PIN15_Msk  (0x01 << PORT_PORTN_DRIVS_PIN15_Pos)
+#define PORT_PORTN_DRIVS_PIN16_Pos  16
+#define PORT_PORTN_DRIVS_PIN16_Msk  (0x01 << PORT_PORTN_DRIVS_PIN16_Pos)
+#define PORT_PORTN_DRIVS_PIN17_Pos  17
+#define PORT_PORTN_DRIVS_PIN17_Msk  (0x01 << PORT_PORTN_DRIVS_PIN17_Pos)
+#define PORT_PORTN_DRIVS_PIN18_Pos  18
+#define PORT_PORTN_DRIVS_PIN18_Msk  (0x01 << PORT_PORTN_DRIVS_PIN18_Pos)
+#define PORT_PORTN_DRIVS_PIN19_Pos  19
+#define PORT_PORTN_DRIVS_PIN19_Msk  (0x01 << PORT_PORTN_DRIVS_PIN19_Pos)
+#define PORT_PORTN_DRIVS_PIN20_Pos  20
+#define PORT_PORTN_DRIVS_PIN20_Msk  (0x01 << PORT_PORTN_DRIVS_PIN20_Pos)
+#define PORT_PORTN_DRIVS_PIN21_Pos  21
+#define PORT_PORTN_DRIVS_PIN21_Msk  (0x01 << PORT_PORTN_DRIVS_PIN21_Pos)
+#define PORT_PORTN_DRIVS_PIN22_Pos  22
+#define PORT_PORTN_DRIVS_PIN22_Msk  (0x01 << PORT_PORTN_DRIVS_PIN22_Pos)
+#define PORT_PORTN_DRIVS_PIN23_Pos  23
+#define PORT_PORTN_DRIVS_PIN23_Msk  (0x01 << PORT_PORTN_DRIVS_PIN23_Pos)
+
+#define PORT_PORTP_DRIVS_PIN0_Pos   0
+#define PORT_PORTP_DRIVS_PIN0_Msk   (0x01 << PORT_PORTP_DRIVS_PIN0_Pos)
+#define PORT_PORTP_DRIVS_PIN1_Pos   1
+#define PORT_PORTP_DRIVS_PIN1_Msk   (0x01 << PORT_PORTP_DRIVS_PIN1_Pos)
+#define PORT_PORTP_DRIVS_PIN2_Pos   2
+#define PORT_PORTP_DRIVS_PIN2_Msk   (0x01 << PORT_PORTP_DRIVS_PIN2_Pos)
+#define PORT_PORTP_DRIVS_PIN3_Pos   3
+#define PORT_PORTP_DRIVS_PIN3_Msk   (0x01 << PORT_PORTP_DRIVS_PIN3_Pos)
+#define PORT_PORTP_DRIVS_PIN4_Pos   4
+#define PORT_PORTP_DRIVS_PIN4_Msk   (0x01 << PORT_PORTP_DRIVS_PIN4_Pos)
+#define PORT_PORTP_DRIVS_PIN5_Pos   5
+#define PORT_PORTP_DRIVS_PIN5_Msk   (0x01 << PORT_PORTP_DRIVS_PIN5_Pos)
+#define PORT_PORTP_DRIVS_PIN6_Pos   6
+#define PORT_PORTP_DRIVS_PIN6_Msk   (0x01 << PORT_PORTP_DRIVS_PIN6_Pos)
+#define PORT_PORTP_DRIVS_PIN7_Pos   7
+#define PORT_PORTP_DRIVS_PIN7_Msk   (0x01 << PORT_PORTP_DRIVS_PIN7_Pos)
+#define PORT_PORTP_DRIVS_PIN8_Pos   8
+#define PORT_PORTP_DRIVS_PIN8_Msk   (0x01 << PORT_PORTP_DRIVS_PIN8_Pos)
+#define PORT_PORTP_DRIVS_PIN9_Pos   9
+#define PORT_PORTP_DRIVS_PIN9_Msk   (0x01 << PORT_PORTP_DRIVS_PIN9_Pos)
+#define PORT_PORTP_DRIVS_PIN10_Pos  10
+#define PORT_PORTP_DRIVS_PIN10_Msk  (0x01 << PORT_PORTP_DRIVS_PIN10_Pos)
+#define PORT_PORTP_DRIVS_PIN11_Pos  11
+#define PORT_PORTP_DRIVS_PIN11_Msk  (0x01 << PORT_PORTP_DRIVS_PIN11_Pos)
+#define PORT_PORTP_DRIVS_PIN12_Pos  12
+#define PORT_PORTP_DRIVS_PIN12_Msk  (0x01 << PORT_PORTP_DRIVS_PIN12_Pos)
+#define PORT_PORTP_DRIVS_PIN13_Pos  13
+#define PORT_PORTP_DRIVS_PIN13_Msk  (0x01 << PORT_PORTP_DRIVS_PIN13_Pos)
+#define PORT_PORTP_DRIVS_PIN14_Pos  14
+#define PORT_PORTP_DRIVS_PIN14_Msk  (0x01 << PORT_PORTP_DRIVS_PIN14_Pos)
+#define PORT_PORTP_DRIVS_PIN15_Pos  15
+#define PORT_PORTP_DRIVS_PIN15_Msk  (0x01 << PORT_PORTP_DRIVS_PIN15_Pos)
+#define PORT_PORTP_DRIVS_PIN16_Pos  16
+#define PORT_PORTP_DRIVS_PIN16_Msk  (0x01 << PORT_PORTP_DRIVS_PIN16_Pos)
+#define PORT_PORTP_DRIVS_PIN17_Pos  17
+#define PORT_PORTP_DRIVS_PIN17_Msk  (0x01 << PORT_PORTP_DRIVS_PIN17_Pos)
+#define PORT_PORTP_DRIVS_PIN18_Pos  18
+#define PORT_PORTP_DRIVS_PIN18_Msk  (0x01 << PORT_PORTP_DRIVS_PIN18_Pos)
+#define PORT_PORTP_DRIVS_PIN19_Pos  19
+#define PORT_PORTP_DRIVS_PIN19_Msk  (0x01 << PORT_PORTP_DRIVS_PIN19_Pos)
+#define PORT_PORTP_DRIVS_PIN20_Pos  20
+#define PORT_PORTP_DRIVS_PIN20_Msk  (0x01 << PORT_PORTP_DRIVS_PIN20_Pos)
+#define PORT_PORTP_DRIVS_PIN21_Pos  21
+#define PORT_PORTP_DRIVS_PIN21_Msk  (0x01 << PORT_PORTP_DRIVS_PIN21_Pos)
+#define PORT_PORTP_DRIVS_PIN22_Pos  22
+#define PORT_PORTP_DRIVS_PIN22_Msk  (0x01 << PORT_PORTP_DRIVS_PIN22_Pos)
+#define PORT_PORTP_DRIVS_PIN23_Pos  23
+#define PORT_PORTP_DRIVS_PIN23_Msk  (0x01 << PORT_PORTP_DRIVS_PIN23_Pos)
+
+#define PORT_PORTA_INEN_PIN0_Pos    0
+#define PORT_PORTA_INEN_PIN0_Msk    (0x01 << PORT_PORTA_INEN_PIN0_Pos)
+#define PORT_PORTA_INEN_PIN1_Pos    1
+#define PORT_PORTA_INEN_PIN1_Msk    (0x01 << PORT_PORTA_INEN_PIN1_Pos)
+#define PORT_PORTA_INEN_PIN2_Pos    2
+#define PORT_PORTA_INEN_PIN2_Msk    (0x01 << PORT_PORTA_INEN_PIN2_Pos)
+#define PORT_PORTA_INEN_PIN3_Pos    3
+#define PORT_PORTA_INEN_PIN3_Msk    (0x01 << PORT_PORTA_INEN_PIN3_Pos)
+#define PORT_PORTA_INEN_PIN4_Pos    4
+#define PORT_PORTA_INEN_PIN4_Msk    (0x01 << PORT_PORTA_INEN_PIN4_Pos)
+#define PORT_PORTA_INEN_PIN5_Pos    5
+#define PORT_PORTA_INEN_PIN5_Msk    (0x01 << PORT_PORTA_INEN_PIN5_Pos)
+#define PORT_PORTA_INEN_PIN6_Pos    6
+#define PORT_PORTA_INEN_PIN6_Msk    (0x01 << PORT_PORTA_INEN_PIN6_Pos)
+#define PORT_PORTA_INEN_PIN7_Pos    7
+#define PORT_PORTA_INEN_PIN7_Msk    (0x01 << PORT_PORTA_INEN_PIN7_Pos)
+#define PORT_PORTA_INEN_PIN8_Pos    8
+#define PORT_PORTA_INEN_PIN8_Msk    (0x01 << PORT_PORTA_INEN_PIN8_Pos)
+#define PORT_PORTA_INEN_PIN9_Pos    9
+#define PORT_PORTA_INEN_PIN9_Msk    (0x01 << PORT_PORTA_INEN_PIN9_Pos)
+#define PORT_PORTA_INEN_PIN10_Pos   10
+#define PORT_PORTA_INEN_PIN10_Msk   (0x01 << PORT_PORTA_INEN_PIN10_Pos)
+#define PORT_PORTA_INEN_PIN11_Pos   11
+#define PORT_PORTA_INEN_PIN11_Msk   (0x01 << PORT_PORTA_INEN_PIN11_Pos)
+#define PORT_PORTA_INEN_PIN12_Pos   12
+#define PORT_PORTA_INEN_PIN12_Msk   (0x01 << PORT_PORTA_INEN_PIN12_Pos)
+#define PORT_PORTA_INEN_PIN13_Pos   13
+#define PORT_PORTA_INEN_PIN13_Msk   (0x01 << PORT_PORTA_INEN_PIN13_Pos)
+#define PORT_PORTA_INEN_PIN14_Pos   14
+#define PORT_PORTA_INEN_PIN14_Msk   (0x01 << PORT_PORTA_INEN_PIN14_Pos)
+#define PORT_PORTA_INEN_PIN15_Pos   15
+#define PORT_PORTA_INEN_PIN15_Msk   (0x01 << PORT_PORTA_INEN_PIN15_Pos)
+
+#define PORT_PORTB_INEN_PIN0_Pos    0
+#define PORT_PORTB_INEN_PIN0_Msk    (0x01 << PORT_PORTB_INEN_PIN0_Pos)
+#define PORT_PORTB_INEN_PIN1_Pos    1
+#define PORT_PORTB_INEN_PIN1_Msk    (0x01 << PORT_PORTB_INEN_PIN1_Pos)
+#define PORT_PORTB_INEN_PIN2_Pos    2
+#define PORT_PORTB_INEN_PIN2_Msk    (0x01 << PORT_PORTB_INEN_PIN2_Pos)
+#define PORT_PORTB_INEN_PIN3_Pos    3
+#define PORT_PORTB_INEN_PIN3_Msk    (0x01 << PORT_PORTB_INEN_PIN3_Pos)
+#define PORT_PORTB_INEN_PIN4_Pos    4
+#define PORT_PORTB_INEN_PIN4_Msk    (0x01 << PORT_PORTB_INEN_PIN4_Pos)
+#define PORT_PORTB_INEN_PIN5_Pos    5
+#define PORT_PORTB_INEN_PIN5_Msk    (0x01 << PORT_PORTB_INEN_PIN5_Pos)
+#define PORT_PORTB_INEN_PIN6_Pos    6
+#define PORT_PORTB_INEN_PIN6_Msk    (0x01 << PORT_PORTB_INEN_PIN6_Pos)
+#define PORT_PORTB_INEN_PIN7_Pos    7
+#define PORT_PORTB_INEN_PIN7_Msk    (0x01 << PORT_PORTB_INEN_PIN7_Pos)
+#define PORT_PORTB_INEN_PIN8_Pos    8
+#define PORT_PORTB_INEN_PIN8_Msk    (0x01 << PORT_PORTB_INEN_PIN8_Pos)
+#define PORT_PORTB_INEN_PIN9_Pos    9
+#define PORT_PORTB_INEN_PIN9_Msk    (0x01 << PORT_PORTB_INEN_PIN9_Pos)
+#define PORT_PORTB_INEN_PIN10_Pos   10
+#define PORT_PORTB_INEN_PIN10_Msk   (0x01 << PORT_PORTB_INEN_PIN10_Pos)
+#define PORT_PORTB_INEN_PIN11_Pos   11
+#define PORT_PORTB_INEN_PIN11_Msk   (0x01 << PORT_PORTB_INEN_PIN11_Pos)
+#define PORT_PORTB_INEN_PIN12_Pos   12
+#define PORT_PORTB_INEN_PIN12_Msk   (0x01 << PORT_PORTB_INEN_PIN12_Pos)
+#define PORT_PORTB_INEN_PIN13_Pos   13
+#define PORT_PORTB_INEN_PIN13_Msk   (0x01 << PORT_PORTB_INEN_PIN13_Pos)
+#define PORT_PORTB_INEN_PIN14_Pos   14
+#define PORT_PORTB_INEN_PIN14_Msk   (0x01 << PORT_PORTB_INEN_PIN14_Pos)
+#define PORT_PORTB_INEN_PIN15_Pos   15
+#define PORT_PORTB_INEN_PIN15_Msk   (0x01 << PORT_PORTB_INEN_PIN15_Pos)
+
+#define PORT_PORTC_INEN_PIN0_Pos    0
+#define PORT_PORTC_INEN_PIN0_Msk    (0x01 << PORT_PORTC_INEN_PIN0_Pos)
+#define PORT_PORTC_INEN_PIN1_Pos    1
+#define PORT_PORTC_INEN_PIN1_Msk    (0x01 << PORT_PORTC_INEN_PIN1_Pos)
+#define PORT_PORTC_INEN_PIN2_Pos    2
+#define PORT_PORTC_INEN_PIN2_Msk    (0x01 << PORT_PORTC_INEN_PIN2_Pos)
+#define PORT_PORTC_INEN_PIN3_Pos    3
+#define PORT_PORTC_INEN_PIN3_Msk    (0x01 << PORT_PORTC_INEN_PIN3_Pos)
+#define PORT_PORTC_INEN_PIN4_Pos    4
+#define PORT_PORTC_INEN_PIN4_Msk    (0x01 << PORT_PORTC_INEN_PIN4_Pos)
+#define PORT_PORTC_INEN_PIN5_Pos    5
+#define PORT_PORTC_INEN_PIN5_Msk    (0x01 << PORT_PORTC_INEN_PIN5_Pos)
+#define PORT_PORTC_INEN_PIN6_Pos    6
+#define PORT_PORTC_INEN_PIN6_Msk    (0x01 << PORT_PORTC_INEN_PIN6_Pos)
+#define PORT_PORTC_INEN_PIN7_Pos    7
+#define PORT_PORTC_INEN_PIN7_Msk    (0x01 << PORT_PORTC_INEN_PIN7_Pos)
+#define PORT_PORTC_INEN_PIN8_Pos    8
+#define PORT_PORTC_INEN_PIN8_Msk    (0x01 << PORT_PORTC_INEN_PIN8_Pos)
+#define PORT_PORTC_INEN_PIN9_Pos    9
+#define PORT_PORTC_INEN_PIN9_Msk    (0x01 << PORT_PORTC_INEN_PIN9_Pos)
+#define PORT_PORTC_INEN_PIN10_Pos   10
+#define PORT_PORTC_INEN_PIN10_Msk   (0x01 << PORT_PORTC_INEN_PIN10_Pos)
+#define PORT_PORTC_INEN_PIN11_Pos   11
+#define PORT_PORTC_INEN_PIN11_Msk   (0x01 << PORT_PORTC_INEN_PIN11_Pos)
+#define PORT_PORTC_INEN_PIN12_Pos   12
+#define PORT_PORTC_INEN_PIN12_Msk   (0x01 << PORT_PORTC_INEN_PIN12_Pos)
+#define PORT_PORTC_INEN_PIN13_Pos   13
+#define PORT_PORTC_INEN_PIN13_Msk   (0x01 << PORT_PORTC_INEN_PIN13_Pos)
+#define PORT_PORTC_INEN_PIN14_Pos   14
+#define PORT_PORTC_INEN_PIN14_Msk   (0x01 << PORT_PORTC_INEN_PIN14_Pos)
+#define PORT_PORTC_INEN_PIN15_Pos   15
+#define PORT_PORTC_INEN_PIN15_Msk   (0x01 << PORT_PORTC_INEN_PIN15_Pos)
+
+#define PORT_PORTM_INEN_PIN0_Pos    0
+#define PORT_PORTM_INEN_PIN0_Msk    (0x01 << PORT_PORTM_INEN_PIN0_Pos)
+#define PORT_PORTM_INEN_PIN1_Pos    1
+#define PORT_PORTM_INEN_PIN1_Msk    (0x01 << PORT_PORTM_INEN_PIN1_Pos)
+#define PORT_PORTM_INEN_PIN2_Pos    2
+#define PORT_PORTM_INEN_PIN2_Msk    (0x01 << PORT_PORTM_INEN_PIN2_Pos)
+#define PORT_PORTM_INEN_PIN3_Pos    3
+#define PORT_PORTM_INEN_PIN3_Msk    (0x01 << PORT_PORTM_INEN_PIN3_Pos)
+#define PORT_PORTM_INEN_PIN4_Pos    4
+#define PORT_PORTM_INEN_PIN4_Msk    (0x01 << PORT_PORTM_INEN_PIN4_Pos)
+#define PORT_PORTM_INEN_PIN5_Pos    5
+#define PORT_PORTM_INEN_PIN5_Msk    (0x01 << PORT_PORTM_INEN_PIN5_Pos)
+#define PORT_PORTM_INEN_PIN6_Pos    6
+#define PORT_PORTM_INEN_PIN6_Msk    (0x01 << PORT_PORTM_INEN_PIN6_Pos)
+#define PORT_PORTM_INEN_PIN7_Pos    7
+#define PORT_PORTM_INEN_PIN7_Msk    (0x01 << PORT_PORTM_INEN_PIN7_Pos)
+#define PORT_PORTM_INEN_PIN8_Pos    8
+#define PORT_PORTM_INEN_PIN8_Msk    (0x01 << PORT_PORTM_INEN_PIN8_Pos)
+#define PORT_PORTM_INEN_PIN9_Pos    9
+#define PORT_PORTM_INEN_PIN9_Msk    (0x01 << PORT_PORTM_INEN_PIN9_Pos)
+#define PORT_PORTM_INEN_PIN10_Pos   10
+#define PORT_PORTM_INEN_PIN10_Msk   (0x01 << PORT_PORTM_INEN_PIN10_Pos)
+#define PORT_PORTM_INEN_PIN11_Pos   11
+#define PORT_PORTM_INEN_PIN11_Msk   (0x01 << PORT_PORTM_INEN_PIN11_Pos)
+#define PORT_PORTM_INEN_PIN12_Pos   12
+#define PORT_PORTM_INEN_PIN12_Msk   (0x01 << PORT_PORTM_INEN_PIN12_Pos)
+#define PORT_PORTM_INEN_PIN13_Pos   13
+#define PORT_PORTM_INEN_PIN13_Msk   (0x01 << PORT_PORTM_INEN_PIN13_Pos)
+#define PORT_PORTM_INEN_PIN14_Pos   14
+#define PORT_PORTM_INEN_PIN14_Msk   (0x01 << PORT_PORTM_INEN_PIN14_Pos)
+#define PORT_PORTM_INEN_PIN15_Pos   15
+#define PORT_PORTM_INEN_PIN15_Msk   (0x01 << PORT_PORTM_INEN_PIN15_Pos)
+#define PORT_PORTM_INEN_PIN16_Pos   16
+#define PORT_PORTM_INEN_PIN16_Msk   (0x01 << PORT_PORTM_INEN_PIN16_Pos)
+#define PORT_PORTM_INEN_PIN17_Pos   17
+#define PORT_PORTM_INEN_PIN17_Msk   (0x01 << PORT_PORTM_INEN_PIN17_Pos)
+#define PORT_PORTM_INEN_PIN18_Pos   18
+#define PORT_PORTM_INEN_PIN18_Msk   (0x01 << PORT_PORTM_INEN_PIN18_Pos)
+#define PORT_PORTM_INEN_PIN19_Pos   19
+#define PORT_PORTM_INEN_PIN19_Msk   (0x01 << PORT_PORTM_INEN_PIN19_Pos)
+#define PORT_PORTM_INEN_PIN20_Pos   20
+#define PORT_PORTM_INEN_PIN20_Msk   (0x01 << PORT_PORTM_INEN_PIN20_Pos)
+#define PORT_PORTM_INEN_PIN21_Pos   21
+#define PORT_PORTM_INEN_PIN21_Msk   (0x01 << PORT_PORTM_INEN_PIN21_Pos)
+#define PORT_PORTM_INEN_PIN22_Pos   22
+#define PORT_PORTM_INEN_PIN22_Msk   (0x01 << PORT_PORTM_INEN_PIN22_Pos)
+#define PORT_PORTM_INEN_PIN23_Pos   23
+#define PORT_PORTM_INEN_PIN23_Msk   (0x01 << PORT_PORTM_INEN_PIN23_Pos)
+
+#define PORT_PORTN_INEN_PIN0_Pos    0
+#define PORT_PORTN_INEN_PIN0_Msk    (0x01 << PORT_PORTN_INEN_PIN0_Pos)
+#define PORT_PORTN_INEN_PIN1_Pos    1
+#define PORT_PORTN_INEN_PIN1_Msk    (0x01 << PORT_PORTN_INEN_PIN1_Pos)
+#define PORT_PORTN_INEN_PIN2_Pos    2
+#define PORT_PORTN_INEN_PIN2_Msk    (0x01 << PORT_PORTN_INEN_PIN2_Pos)
+#define PORT_PORTN_INEN_PIN3_Pos    3
+#define PORT_PORTN_INEN_PIN3_Msk    (0x01 << PORT_PORTN_INEN_PIN3_Pos)
+#define PORT_PORTN_INEN_PIN4_Pos    4
+#define PORT_PORTN_INEN_PIN4_Msk    (0x01 << PORT_PORTN_INEN_PIN4_Pos)
+#define PORT_PORTN_INEN_PIN5_Pos    5
+#define PORT_PORTN_INEN_PIN5_Msk    (0x01 << PORT_PORTN_INEN_PIN5_Pos)
+#define PORT_PORTN_INEN_PIN6_Pos    6
+#define PORT_PORTN_INEN_PIN6_Msk    (0x01 << PORT_PORTN_INEN_PIN6_Pos)
+#define PORT_PORTN_INEN_PIN7_Pos    7
+#define PORT_PORTN_INEN_PIN7_Msk    (0x01 << PORT_PORTN_INEN_PIN7_Pos)
+#define PORT_PORTN_INEN_PIN8_Pos    8
+#define PORT_PORTN_INEN_PIN8_Msk    (0x01 << PORT_PORTN_INEN_PIN8_Pos)
+#define PORT_PORTN_INEN_PIN9_Pos    9
+#define PORT_PORTN_INEN_PIN9_Msk    (0x01 << PORT_PORTN_INEN_PIN9_Pos)
+#define PORT_PORTN_INEN_PIN10_Pos   10
+#define PORT_PORTN_INEN_PIN10_Msk   (0x01 << PORT_PORTN_INEN_PIN10_Pos)
+#define PORT_PORTN_INEN_PIN11_Pos   11
+#define PORT_PORTN_INEN_PIN11_Msk   (0x01 << PORT_PORTN_INEN_PIN11_Pos)
+#define PORT_PORTN_INEN_PIN12_Pos   12
+#define PORT_PORTN_INEN_PIN12_Msk   (0x01 << PORT_PORTN_INEN_PIN12_Pos)
+#define PORT_PORTN_INEN_PIN13_Pos   13
+#define PORT_PORTN_INEN_PIN13_Msk   (0x01 << PORT_PORTN_INEN_PIN13_Pos)
+#define PORT_PORTN_INEN_PIN14_Pos   14
+#define PORT_PORTN_INEN_PIN14_Msk   (0x01 << PORT_PORTN_INEN_PIN14_Pos)
+#define PORT_PORTN_INEN_PIN15_Pos   15
+#define PORT_PORTN_INEN_PIN15_Msk   (0x01 << PORT_PORTN_INEN_PIN15_Pos)
+#define PORT_PORTN_INEN_PIN16_Pos   16
+#define PORT_PORTN_INEN_PIN16_Msk   (0x01 << PORT_PORTN_INEN_PIN16_Pos)
+#define PORT_PORTN_INEN_PIN17_Pos   17
+#define PORT_PORTN_INEN_PIN17_Msk   (0x01 << PORT_PORTN_INEN_PIN17_Pos)
+#define PORT_PORTN_INEN_PIN18_Pos   18
+#define PORT_PORTN_INEN_PIN18_Msk   (0x01 << PORT_PORTN_INEN_PIN18_Pos)
+#define PORT_PORTN_INEN_PIN19_Pos   19
+#define PORT_PORTN_INEN_PIN19_Msk   (0x01 << PORT_PORTN_INEN_PIN19_Pos)
+#define PORT_PORTN_INEN_PIN20_Pos   20
+#define PORT_PORTN_INEN_PIN20_Msk   (0x01 << PORT_PORTN_INEN_PIN20_Pos)
+#define PORT_PORTN_INEN_PIN21_Pos   21
+#define PORT_PORTN_INEN_PIN21_Msk   (0x01 << PORT_PORTN_INEN_PIN21_Pos)
+#define PORT_PORTN_INEN_PIN22_Pos   22
+#define PORT_PORTN_INEN_PIN22_Msk   (0x01 << PORT_PORTN_INEN_PIN22_Pos)
+#define PORT_PORTN_INEN_PIN23_Pos   23
+#define PORT_PORTN_INEN_PIN23_Msk   (0x01 << PORT_PORTN_INEN_PIN23_Pos)
+
+#define PORT_PORTP_INEN_PIN0_Pos    0
+#define PORT_PORTP_INEN_PIN0_Msk    (0x01 << PORT_PORTP_INEN_PIN0_Pos)
+#define PORT_PORTP_INEN_PIN1_Pos    1
+#define PORT_PORTP_INEN_PIN1_Msk    (0x01 << PORT_PORTP_INEN_PIN1_Pos)
+#define PORT_PORTP_INEN_PIN2_Pos    2
+#define PORT_PORTP_INEN_PIN2_Msk    (0x01 << PORT_PORTP_INEN_PIN2_Pos)
+#define PORT_PORTP_INEN_PIN3_Pos    3
+#define PORT_PORTP_INEN_PIN3_Msk    (0x01 << PORT_PORTP_INEN_PIN3_Pos)
+#define PORT_PORTP_INEN_PIN4_Pos    4
+#define PORT_PORTP_INEN_PIN4_Msk    (0x01 << PORT_PORTP_INEN_PIN4_Pos)
+#define PORT_PORTP_INEN_PIN5_Pos    5
+#define PORT_PORTP_INEN_PIN5_Msk    (0x01 << PORT_PORTP_INEN_PIN5_Pos)
+#define PORT_PORTP_INEN_PIN6_Pos    6
+#define PORT_PORTP_INEN_PIN6_Msk    (0x01 << PORT_PORTP_INEN_PIN6_Pos)
+#define PORT_PORTP_INEN_PIN7_Pos    7
+#define PORT_PORTP_INEN_PIN7_Msk    (0x01 << PORT_PORTP_INEN_PIN7_Pos)
+#define PORT_PORTP_INEN_PIN8_Pos    8
+#define PORT_PORTP_INEN_PIN8_Msk    (0x01 << PORT_PORTP_INEN_PIN8_Pos)
+#define PORT_PORTP_INEN_PIN9_Pos    9
+#define PORT_PORTP_INEN_PIN9_Msk    (0x01 << PORT_PORTP_INEN_PIN9_Pos)
+#define PORT_PORTP_INEN_PIN10_Pos   10
+#define PORT_PORTP_INEN_PIN10_Msk   (0x01 << PORT_PORTP_INEN_PIN10_Pos)
+#define PORT_PORTP_INEN_PIN11_Pos   11
+#define PORT_PORTP_INEN_PIN11_Msk   (0x01 << PORT_PORTP_INEN_PIN11_Pos)
+#define PORT_PORTP_INEN_PIN12_Pos   12
+#define PORT_PORTP_INEN_PIN12_Msk   (0x01 << PORT_PORTP_INEN_PIN12_Pos)
+#define PORT_PORTP_INEN_PIN13_Pos   13
+#define PORT_PORTP_INEN_PIN13_Msk   (0x01 << PORT_PORTP_INEN_PIN13_Pos)
+#define PORT_PORTP_INEN_PIN14_Pos   14
+#define PORT_PORTP_INEN_PIN14_Msk   (0x01 << PORT_PORTP_INEN_PIN14_Pos)
+#define PORT_PORTP_INEN_PIN15_Pos   15
+#define PORT_PORTP_INEN_PIN15_Msk   (0x01 << PORT_PORTP_INEN_PIN15_Pos)
+#define PORT_PORTP_INEN_PIN16_Pos   16
+#define PORT_PORTP_INEN_PIN16_Msk   (0x01 << PORT_PORTP_INEN_PIN16_Pos)
+#define PORT_PORTP_INEN_PIN17_Pos   17
+#define PORT_PORTP_INEN_PIN17_Msk   (0x01 << PORT_PORTP_INEN_PIN17_Pos)
+#define PORT_PORTP_INEN_PIN18_Pos   18
+#define PORT_PORTP_INEN_PIN18_Msk   (0x01 << PORT_PORTP_INEN_PIN18_Pos)
+#define PORT_PORTP_INEN_PIN19_Pos   19
+#define PORT_PORTP_INEN_PIN19_Msk   (0x01 << PORT_PORTP_INEN_PIN19_Pos)
+#define PORT_PORTP_INEN_PIN20_Pos   20
+#define PORT_PORTP_INEN_PIN20_Msk   (0x01 << PORT_PORTP_INEN_PIN20_Pos)
+#define PORT_PORTP_INEN_PIN21_Pos   21
+#define PORT_PORTP_INEN_PIN21_Msk   (0x01 << PORT_PORTP_INEN_PIN21_Pos)
+#define PORT_PORTP_INEN_PIN22_Pos   22
+#define PORT_PORTP_INEN_PIN22_Msk   (0x01 << PORT_PORTP_INEN_PIN22_Pos)
+#define PORT_PORTP_INEN_PIN23_Pos   23
+#define PORT_PORTP_INEN_PIN23_Msk   (0x01 << PORT_PORTP_INEN_PIN23_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t DATA;
+#define PIN0    0
+#define PIN1    1
+#define PIN2    2
+#define PIN3    3
+#define PIN4    4
+#define PIN5    5
+#define PIN6    6
+#define PIN7    7
+#define PIN8    8
+#define PIN9    9
+#define PIN10   10
+#define PIN11   11
+#define PIN12   12
+#define PIN13   13
+#define PIN14   14
+#define PIN15   15
+#define PIN16   16
+#define PIN17   17
+#define PIN18   18
+#define PIN19   19
+#define PIN20   20
+#define PIN21   21
+#define PIN22   22
+#define PIN23   23
+#define PIN24   24
+
+    __IO uint32_t DIR;                      //0 输入  1 输出
+
+    __IO uint32_t INTLVLTRG;                //Interrupt Level Trigger  1 电平触发中断 0 边沿触发中断
+
+    __IO uint32_t INTBE;                    //Both Edge，当INTLVLTRG设为边沿触发中断时，此位置1表示上升沿和下降沿都触发中断，置0时触发边沿由INTRISEEN选择
+
+    __IO uint32_t INTRISEEN;                //Interrupt Rise Edge Enable   1 上升沿/高电平触发中断    0 下降沿/低电平触发中断
+
+    __IO uint32_t INTEN;                    //1 中断使能    0 中断禁止
+
+    __IO uint32_t INTRAWSTAT;               //中断检测单元是否检测到了触发中断的条件 1 检测到了中断触发条件  0 没有检测到中断触发条件
+
+    __IO uint32_t INTSTAT;                  //INTSTAT.PIN0 = INTRAWSTAT.PIN0 & INTEN.PIN0
+
+    __IO uint32_t INTCLR;                   //写1清除中断标志，只对边沿触发中断有用
+} GPIO_TypeDef;
+
+
+
+
+typedef struct {
+    __IO uint32_t LDVAL;                    //定时器加载值，使能后定时器从此数值开始向下递减计数
+
+    __I  uint32_t CVAL;                  //定时器当前值，LDVAL-CVAL 可计算出计时时长
+
+    __IO uint32_t CTRL;
+} TIMR_TypeDef;
+
+
+#define TIMR_CTRL_EN_Pos            0       //此位赋1导致TIMR从LDVAL开始向下递减计数
+#define TIMR_CTRL_EN_Msk            (0x01 << TIMR_CTRL_EN_Pos)
+#define TIMR_CTRL_CLKSRC_Pos        1       //时钟源：0 内部系统时钟  1 外部引脚脉冲计数
+#define TIMR_CTRL_CLKSRC_Msk        (0x01 << TIMR_CTRL_CLKSRC_Pos)
+#define TIMR_CTRL_CASCADE_Pos       2       //1 TIMRx的计数时钟为TIMRx-1的溢出信号
+#define TIMR_CTRL_CASCADE_Msk       (0x01 << TIMR_CTRL_CASCADE_Pos)
+
+
+typedef struct {
+    __IO uint32_t PCTRL;                    //Pulse Control，脉宽测量模块控制寄存器
+
+    __I  uint32_t PCVAL;                    //脉宽测量定时器当前值
+
+         uint32_t RESERVED[2];
+
+    __IO uint32_t IE;
+
+    __IO uint32_t IF;
+
+    __IO uint32_t HALT;
+} TIMRG_TypeDef;
+
+
+#define TIMRG_PCTRL_EN_Pos          0       //开始测量脉宽，脉宽内32位计数器从0开始向上计数
+#define TIMRG_PCTRL_EN_Msk          (0x01 << TIMRG_PCTRL_EN_Pos)
+#define TIMRG_PCTRL_HIGH_Pos        1       //0 测量低电平长度 1 测量高电平长度
+#define TIMRG_PCTRL_HIGH_Msk        (0x01 << TIMRG_PCTRL_HIGH_Pos)
+#define TIMRG_PCTRL_CLKSRC_Pos      2       //时钟源：0 内部系统时钟  1 脉宽测量模块变成一个计数器，不再具有脉宽测量功能
+#define TIMRG_PCTRL_CLKSRC_Msk      (0x01 << TIMRG_PCTRL_CLKSRC_Pos)
+
+#define TIMRG_IE_TIMR0_Pos          0
+#define TIMRG_IE_TIMR0_Msk          (0x01 << TIMRG_IE_TIMR0_Pos)
+#define TIMRG_IE_TIMR1_Pos          1
+#define TIMRG_IE_TIMR1_Msk          (0x01 << TIMRG_IE_TIMR1_Pos)
+#define TIMRG_IE_TIMR2_Pos          2
+#define TIMRG_IE_TIMR2_Msk          (0x01 << TIMRG_IE_TIMR2_Pos)
+#define TIMRG_IE_TIMR3_Pos          3
+#define TIMRG_IE_TIMR3_Msk          (0x01 << TIMRG_IE_TIMR3_Pos)
+#define TIMRG_IE_TIMR4_Pos          4
+#define TIMRG_IE_TIMR4_Msk          (0x01 << TIMRG_IE_TIMR4_Pos)
+#define TIMRG_IE_TIMR5_Pos          5
+#define TIMRG_IE_TIMR5_Msk          (0x01 << TIMRG_IE_TIMR5_Pos)
+#define TIMRG_IE_PULSE_Pos          16
+#define TIMRG_IE_PULSE_Msk          (0x01 << TIMRG_IE_PULSE_Pos)
+
+#define TIMRG_IF_TIMR0_Pos          0       //写1清零
+#define TIMRG_IF_TIMR0_Msk          (0x01 << TIMRG_IF_TIMR0_Pos)
+#define TIMRG_IF_TIMR1_Pos          1
+#define TIMRG_IF_TIMR1_Msk          (0x01 << TIMRG_IF_TIMR1_Pos)
+#define TIMRG_IF_TIMR2_Pos          2
+#define TIMRG_IF_TIMR2_Msk          (0x01 << TIMRG_IF_TIMR2_Pos)
+#define TIMRG_IF_TIMR3_Pos          3
+#define TIMRG_IF_TIMR3_Msk          (0x01 << TIMRG_IF_TIMR3_Pos)
+#define TIMRG_IF_TIMR4_Pos          4
+#define TIMRG_IF_TIMR4_Msk          (0x01 << TIMRG_IF_TIMR4_Pos)
+#define TIMRG_IF_TIMR5_Pos          5
+#define TIMRG_IF_TIMR5_Msk          (0x01 << TIMRG_IF_TIMR5_Pos)
+#define TIMRG_IF_PULSE_Pos          16
+#define TIMRG_IF_PULSE_Msk          (0x01 << TIMRG_IF_PULSE_Pos)
+
+#define TIMRG_HALT_TIMR0_Pos        0       //1 暂停计数
+#define TIMRG_HALT_TIMR0_Msk        (0x01 << TIMRG_HALT_TIMR0_Pos)
+#define TIMRG_HALT_TIMR1_Pos        1
+#define TIMRG_HALT_TIMR1_Msk        (0x01 << TIMRG_HALT_TIMR1_Pos)
+#define TIMRG_HALT_TIMR2_Pos        2
+#define TIMRG_HALT_TIMR2_Msk        (0x01 << TIMRG_HALT_TIMR2_Pos)
+#define TIMRG_HALT_TIMR3_Pos        3
+#define TIMRG_HALT_TIMR3_Msk        (0x01 << TIMRG_HALT_TIMR3_Pos)
+#define TIMRG_HALT_TIMR4_Pos        4
+#define TIMRG_HALT_TIMR4_Msk        (0x01 << TIMRG_HALT_TIMR4_Pos)
+#define TIMRG_HALT_TIMR5_Pos        5
+#define TIMRG_HALT_TIMR5_Msk        (0x01 << TIMRG_HALT_TIMR5_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t DATA;
+
+    __IO uint32_t CTRL;
+
+    __IO uint32_t BAUD;
+
+    __IO uint32_t FIFO;
+
+    __IO uint32_t LINCR;
+
+    union {
+        __IO uint32_t CTSCR;
+
+        __IO uint32_t RTSCR;
+    };
+} UART_TypeDef;
+
+
+#define UART_DATA_DATA_Pos          0
+#define UART_DATA_DATA_Msk          (0x1FF << UART_DATA_DATA_Pos)
+#define UART_DATA_VALID_Pos         9       //当DATA字段有有效的接收数据时，该位硬件置1，读取数据后自动清零
+#define UART_DATA_VALID_Msk         (0x01 << UART_DATA_VALID_Pos)
+#define UART_DATA_PAERR_Pos         10      //Parity Error
+#define UART_DATA_PAERR_Msk         (0x01 << UART_DATA_PAERR_Pos)
+
+#define UART_CTRL_TXIDLE_Pos        0       //TX IDLE: 0 正在发送数据 1 空闲状态，没有数据发送
+#define UART_CTRL_TXIDLE_Msk        (0x01 << UART_CTRL_TXIDLE_Pos)
+#define UART_CTRL_TXFF_Pos          1       //TX FIFO Full
+#define UART_CTRL_TXFF_Msk          (0x01 << UART_CTRL_TXFF_Pos)
+#define UART_CTRL_TXIE_Pos          2       //TX 中断使能: 1 TX FF 中数据少于设定个数时产生中断
+#define UART_CTRL_TXIE_Msk          (0x01 << UART_CTRL_TXIE_Pos)
+#define UART_CTRL_RXNE_Pos          3       //RX FIFO Not Empty
+#define UART_CTRL_RXNE_Msk          (0x01 << UART_CTRL_RXNE_Pos)
+#define UART_CTRL_RXIE_Pos          4       //RX 中断使能: 1 RX FF 中数据达到设定个数时产生中断
+#define UART_CTRL_RXIE_Msk          (0x01 << UART_CTRL_RXIE_Pos)
+#define UART_CTRL_RXOV_Pos          5       //RX FIFO Overflow，写1清零
+#define UART_CTRL_RXOV_Msk          (0x01 << UART_CTRL_RXOV_Pos)
+#define UART_CTRL_TXDOIE_Pos        6       //TX Done 中断使能，发送FIFO空且发送发送移位寄存器已将最后一位发送出去
+#define UART_CTRL_TXDOIE_Msk        (0x01 << UART_CTRL_TXDOIE_Pos)
+#define UART_CTRL_EN_Pos            9
+#define UART_CTRL_EN_Msk            (0x01 << UART_CTRL_EN_Pos)
+#define UART_CTRL_LOOP_Pos          10
+#define UART_CTRL_LOOP_Msk          (0x01 << UART_CTRL_LOOP_Pos)
+#define UART_CTRL_BAUDEN_Pos        13      //必须写1
+#define UART_CTRL_BAUDEN_Msk        (0x01 << UART_CTRL_BAUDEN_Pos)
+#define UART_CTRL_TOIE_Pos          14      //TimeOut 中断使能，接收到上个字符后，超过 TOTIME/BAUDRAUD 秒没有接收到新的数据
+#define UART_CTRL_TOIE_Msk          (0x01 << UART_CTRL_TOIE_Pos)
+#define UART_CTRL_BRKDET_Pos        15      //LIN Break Detect，检测到LIN Break，即RX线上检测到连续11位低电平
+#define UART_CTRL_BRKDET_Msk        (0x01 << UART_CTRL_BRKDET_Pos)
+#define UART_CTRL_BRKIE_Pos         16      //LIN Break Detect 中断使能
+#define UART_CTRL_BRKIE_Msk         (0x01 << UART_CTRL_BRKIE_Pos)
+#define UART_CTRL_GENBRK_Pos        17      //Generate LIN Break，发送LIN Break
+#define UART_CTRL_GENBRK_Msk        (0x01 << UART_CTRL_GENBRK_Pos)
+#define UART_CTRL_DATA9b_Pos        18      //1 9位数据位    0 8位数据位
+#define UART_CTRL_DATA9b_Msk        (0x01 << UART_CTRL_DATA9b_Pos)
+#define UART_CTRL_PARITY_Pos        19      //000 无校验    001 奇校验   011 偶校验   101 固定为1    111 固定为0
+#define UART_CTRL_PARITY_Msk        (0x07 << UART_CTRL_PARITY_Pos)
+#define UART_CTRL_STOP2b_Pos        22      //1 2位停止位    0 1位停止位
+#define UART_CTRL_STOP2b_Msk        (0x03 << UART_CTRL_STOP2b_Pos)
+#define UART_CTRL_TOTIME_Pos        24      //TimeOut 时长 = TOTIME/(BAUDRAUD/10) 秒
+#define UART_CTRL_TOTIME_Msk        (0xFFu<< UART_CTRL_TOTIME_Pos)
+
+#define UART_BAUD_BAUD_Pos          0       //串口波特率 = SYS_Freq/16/BAUD - 1
+#define UART_BAUD_BAUD_Msk          (0x3FFF << UART_BAUD_BAUD_Pos)
+#define UART_BAUD_TXD_Pos           14      //通过此位可直接读取串口TXD引脚上的电平
+#define UART_BAUD_TXD_Msk           (0x01 << UART_BAUD_TXD_Pos)
+#define UART_BAUD_RXD_Pos           15      //通过此位可直接读取串口RXD引脚上的电平
+#define UART_BAUD_RXD_Msk           (0x01 << UART_BAUD_RXD_Pos)
+#define UART_BAUD_RXTOIF_Pos        16      //接收&超时的中断标志 = RXIF | TOIF
+#define UART_BAUD_RXTOIF_Msk        (0x01 << UART_BAUD_RXTOIF_Pos)
+#define UART_BAUD_TXIF_Pos          17      //发送中断标志 = TXTHRF & TXIE
+#define UART_BAUD_TXIF_Msk          (0x01 << UART_BAUD_TXIF_Pos)
+#define UART_BAUD_BRKIF_Pos         18      //LIN Break Detect 中断标志，检测到LIN Break时若BRKIE=1，此位由硬件置位
+#define UART_BAUD_BRKIF_Msk         (0x01 << UART_BAUD_BRKIF_Pos)
+#define UART_BAUD_RXTHRF_Pos        19      //RX FIFO Threshold Flag，RX FIFO中数据达到设定个数（RXLVL >= RXTHR）时硬件置1
+#define UART_BAUD_RXTHRF_Msk        (0x01 << UART_BAUD_RXTHRF_Pos)
+#define UART_BAUD_TXTHRF_Pos        20      //TX FIFO Threshold Flag，TX FIFO中数据少于设定个数（TXLVL <= TXTHR）时硬件置1
+#define UART_BAUD_TXTHRF_Msk        (0x01 << UART_BAUD_TXTHRF_Pos)
+#define UART_BAUD_TOIF_Pos          21      //TimeOut 中断标志，超过 TOTIME/BAUDRAUD 秒没有接收到新的数据时若TOIE=1，此位由硬件置位
+#define UART_BAUD_TOIF_Msk          (0x01 << UART_BAUD_TOIF_Pos)
+#define UART_BAUD_RXIF_Pos          22      //接收中断标志 = RXTHRF & RXIE
+#define UART_BAUD_RXIF_Msk          (0x01 << UART_BAUD_RXIF_Pos)
+#define UART_BAUD_ABREN_Pos         23      //Auto Baudrate Enable，写1启动自动波特率校准，完成后自动清零
+#define UART_BAUD_ABREN_Msk         (0x01 << UART_BAUD_ABREN_Pos)
+#define UART_BAUD_ABRBIT_Pos        24      //Auto Baudrate Bit，用于计算波特率的检测位长，0 1位，通过测起始位           脉宽计算波特率，要求发送端发送0xFF
+                                            //                                             1 2位，通过测起始位加1位数据位脉宽计算波特率，要求发送端发送0xFE
+                                            //                                             1 4位，通过测起始位加3位数据位脉宽计算波特率，要求发送端发送0xF8
+                                            //                                             1 8位，通过测起始位加7位数据位脉宽计算波特率，要求发送端发送0x80
+#define UART_BAUD_ABRBIT_Msk        (0x03 << UART_BAUD_ABRBIT_Pos)
+#define UART_BAUD_ABRERR_Pos        26      //Auto Baudrate Error，0 自动波特率校准成功     1 自动波特率校准失败
+#define UART_BAUD_ABRERR_Msk        (0x01 << UART_BAUD_ABRERR_Pos)
+#define UART_BAUD_TXDOIF_Pos        27      //TX Done 中断标志，发送FIFO空且发送发送移位寄存器已将最后一位发送出去
+#define UART_BAUD_TXDOIF_Msk        (0x01 << UART_BAUD_TXDOIF_Pos)
+
+#define UART_FIFO_RXLVL_Pos         0       //RX FIFO Level，RX FIFO 中字符个数
+#define UART_FIFO_RXLVL_Msk         (0xFF << UART_FIFO_RXLVL_Pos)
+#define UART_FIFO_TXLVL_Pos         8       //TX FIFO Level，TX FIFO 中字符个数
+#define UART_FIFO_TXLVL_Msk         (0xFF << UART_FIFO_TXLVL_Pos)
+#define UART_FIFO_RXTHR_Pos         16      //RX FIFO Threshold，RX中断触发门限，中断使能时 RXLVL >= RXTHR 触发RX中断
+#define UART_FIFO_RXTHR_Msk         (0xFF << UART_FIFO_RXTHR_Pos)
+#define UART_FIFO_TXTHR_Pos         24      //TX FIFO Threshold，TX中断触发门限，中断使能时 TXLVL <= TXTHR 触发TX中断
+#define UART_FIFO_TXTHR_Msk         (0xFFu<< UART_FIFO_TXTHR_Pos)
+
+#define UART_LINCR_BRKDETIE_Pos     0       //检测到LIN Break中断使能
+#define UART_LINCR_BRKDETIE_Msk     (0x01 << UART_LINCR_BRKDETIE_Pos)
+#define UART_LINCR_BRKDETIF_Pos     1       //检测到LIN Break中断状态
+#define UART_LINCR_BRKDETIF_Msk     (0x01 << UART_LINCR_BRKDETIF_Pos)
+#define UART_LINCR_GENBRKIE_Pos     2       //发送LIN Break完成中断使能
+#define UART_LINCR_GENBRKIE_Msk     (0x01 << UART_LINCR_GENBRKIE_Pos)
+#define UART_LINCR_GENBRKIF_Pos     3       //发送LIN Break完成中断状态
+#define UART_LINCR_GENBRKIF_Msk     (0x01 << UART_LINCR_GENBRKIF_Pos)
+#define UART_LINCR_GENBRK_Pos       4       //发送LIN Break，发送完成自动清零
+#define UART_LINCR_GENBRK_Msk       (0x01 << UART_LINCR_GENBRK_Pos)
+
+#define UART_CTSCR_EN_Pos           0       //CTS流控使能
+#define UART_CTSCR_EN_Msk           (0x01 << UART_CTSCR_EN_Pos)
+#define UART_CTSCR_POL_Pos          2       //CTS信号极性，0 低有效，CTS输入为低表示可以发送数据
+#define UART_CTSCR_POL_Msk          (0x01 << UART_CTSCR_POL_Pos)
+#define UART_CTSCR_STAT_Pos         7       //CTS信号的当前状态
+#define UART_CTSCR_STAT_Msk         (0x01 << UART_CTSCR_STAT_Pos)
+
+#define UART_RTSCR_EN_Pos           1       //RTS流控使能
+#define UART_RTSCR_EN_Msk           (0x01 << UART_RTSCR_EN_Pos)
+#define UART_RTSCR_POL_Pos          3       //RTS信号极性    0 低有效，RTS输入为低表示可以接收数据
+#define UART_RTSCR_POL_Msk          (0x01 << UART_RTSCR_POL_Pos)
+#define UART_RTSCR_THR_Pos          4       //RTS流控的触发阈值    0 1字节    1 2字节    2 4字节    3 6字节
+#define UART_RTSCR_THR_Msk          (0x07 << UART_RTSCR_THR_Pos)
+#define UART_RTSCR_STAT_Pos         8       //RTS信号的当前状态
+#define UART_RTSCR_STAT_Msk         (0x01 << UART_RTSCR_STAT_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t CTRL;
+
+    __IO uint32_t DATA;
+
+    __IO uint32_t STAT;
+
+    __IO uint32_t IE;
+
+    __IO uint32_t IF;
+} SPI_TypeDef;
+
+
+#define SPI_CTRL_CLKDIV_Pos         0       //Clock Divider, SPI工作时钟 = SYS_Freq/pow(2, CLKDIV+2)
+#define SPI_CTRL_CLKDIV_Msk         (0x07 << SPI_CTRL_CLKDIV_Pos)
+#define SPI_CTRL_EN_Pos             3
+#define SPI_CTRL_EN_Msk             (0x01 << SPI_CTRL_EN_Pos)
+#define SPI_CTRL_SIZE_Pos           4       //Data Size Select, 取值3--15，表示4--16位
+#define SPI_CTRL_SIZE_Msk           (0x0F << SPI_CTRL_SIZE_Pos)
+#define SPI_CTRL_CPHA_Pos           8       //0 在SCLK的第一个跳变沿采样数据    1 在SCLK的第二个跳变沿采样数据
+#define SPI_CTRL_CPHA_Msk           (0x01 << SPI_CTRL_CPHA_Pos)
+#define SPI_CTRL_CPOL_Pos           9       //0 空闲状态下SCLK为低电平         1 空闲状态下SCLK为高电平
+#define SPI_CTRL_CPOL_Msk           (0x01 << SPI_CTRL_CPOL_Pos)
+#define SPI_CTRL_FFS_Pos            10      //Frame Format Select, 0 SPI    1 TI SSI    2 SPI   3 SPI
+#define SPI_CTRL_FFS_Msk            (0x03 << SPI_CTRL_FFS_Pos)
+#define SPI_CTRL_MSTR_Pos           12      //Master, 1 主模式 0 从模式
+#define SPI_CTRL_MSTR_Msk           (0x01 << SPI_CTRL_MSTR_Pos)
+#define SPI_CTRL_FAST_Pos           13      //1 SPI工作时钟 = SYS_Freq/2    0 SPI工作时钟由SPI->CTRL.CLKDIV设置
+#define SPI_CTRL_FAST_Msk           (0x01 << SPI_CTRL_FAST_Pos)
+#define SPI_CTRL_FILTE_Pos          16      //1 对SPI输入信号进行去抖操作    0 对SPI输入信号不进行去抖操作
+#define SPI_CTRL_FILTE_Msk          (0x01 << SPI_CTRL_FILTE_Pos)
+#define SPI_CTRL_SSN_H_Pos          17      //0 传输过程中SSN始终为0         1 传输过程中每字符之间会将SSN拉高半个SCLK周期
+#define SPI_CTRL_SSN_H_Msk          (0x01 << SPI_CTRL_SSN_H_Pos)
+#define SPI_CTRL_TFCLR_Pos          24      //TX FIFO Clear
+#define SPI_CTRL_TFCLR_Msk          (0x01 << SPI_CTRL_TFCLR_Pos)
+#define SPI_CTRL_RFCLR_Pos          25      //RX FIFO Clear
+#define SPI_CTRL_RFCLR_Msk          (0x01 << SPI_CTRL_RFCLR_Pos)
+
+#define SPI_STAT_WTC_Pos            0       //Word Transmit Complete，每传输完成一个数据字由硬件置1，软件写1清零
+#define SPI_STAT_WTC_Msk            (0x01 << SPI_STAT_WTC_Pos)
+#define SPI_STAT_TFE_Pos            1       //发送FIFO Empty
+#define SPI_STAT_TFE_Msk            (0x01 << SPI_STAT_TFE_Pos)
+#define SPI_STAT_TFNF_Pos           2       //发送FIFO Not Full
+#define SPI_STAT_TFNF_Msk           (0x01 << SPI_STAT_TFNF_Pos)
+#define SPI_STAT_RFNE_Pos           3       //接收FIFO Not Empty
+#define SPI_STAT_RFNE_Msk           (0x01 << SPI_STAT_RFNE_Pos)
+#define SPI_STAT_RFF_Pos            4       //接收FIFO Full
+#define SPI_STAT_RFF_Msk            (0x01 << SPI_STAT_RFF_Pos)
+#define SPI_STAT_RFOVF_Pos          5       //接收FIFO Overflow
+#define SPI_STAT_RFOVF_Msk          (0x01 << SPI_STAT_RFOVF_Pos)
+#define SPI_STAT_TFLVL_Pos          6       //发送FIFO中数据个数， 0 TFNF=0时表示FIFO内有8个数据，TFNF=1时表示FIFO内有0个数据    1--7 FIFO内有1--7个数据
+#define SPI_STAT_TFLVL_Msk          (0x07 << SPI_STAT_TFLVL_Pos)
+#define SPI_STAT_RFLVL_Pos          9       //接收FIFO中数据个数， 0 RFF=1时表示FIFO内有8个数据， RFF=0时表示FIFO内有0个数据 1--7 FIFO内有1--7个数据
+#define SPI_STAT_RFLVL_Msk          (0x07 << SPI_STAT_RFLVL_Pos)
+#define SPI_STAT_BUSY_Pos           15
+#define SPI_STAT_BUSY_Msk           (0x01 << SPI_STAT_BUSY_Pos)
+
+#define SPI_IE_RFOVF_Pos            0
+#define SPI_IE_RFOVF_Msk            (0x01 << SPI_IE_RFOVF_Pos)
+#define SPI_IE_RFF_Pos              1
+#define SPI_IE_RFF_Msk              (0x01 << SPI_IE_RFF_Pos)
+#define SPI_IE_RFHF_Pos             2
+#define SPI_IE_RFHF_Msk             (0x01 << SPI_IE_RFHF_Pos)
+#define SPI_IE_TFE_Pos              3
+#define SPI_IE_TFE_Msk              (0x01 << SPI_IE_TFE_Pos)
+#define SPI_IE_TFHF_Pos             4
+#define SPI_IE_TFHF_Msk             (0x01 << SPI_IE_TFHF_Pos)
+#define SPI_IE_WTC_Pos              8       //Word Transmit Complete
+#define SPI_IE_WTC_Msk              (0x01 << SPI_IE_WTC_Pos)
+#define SPI_IE_FTC_Pos              9       //Frame Transmit Complete
+#define SPI_IE_FTC_Msk              (0x01 << SPI_IE_FTC_Pos)
+
+#define SPI_IF_RFOVF_Pos            0       //写1清零
+#define SPI_IF_RFOVF_Msk            (0x01 << SPI_IF_RFOVF_Pos)
+#define SPI_IF_RFF_Pos              1
+#define SPI_IF_RFF_Msk              (0x01 << SPI_IF_RFF_Pos)
+#define SPI_IF_RFHF_Pos             2
+#define SPI_IF_RFHF_Msk             (0x01 << SPI_IF_RFHF_Pos)
+#define SPI_IF_TFE_Pos              3
+#define SPI_IF_TFE_Msk              (0x01 << SPI_IF_TFE_Pos)
+#define SPI_IF_TFHF_Pos             4
+#define SPI_IF_TFHF_Msk             (0x01 << SPI_IF_TFHF_Pos)
+#define SPI_IF_WTC_Pos              8       //Word Transmit Complete，每传输完成一个数据字由硬件置1
+#define SPI_IF_WTC_Msk              (0x01 << SPI_IF_WTC_Pos)
+#define SPI_IF_FTC_Pos              9       //Frame Transmit Complete，WTC置位时若TX FIFO是空的，则FTC置位
+#define SPI_IF_FTC_Msk              (0x01 << SPI_IF_FTC_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t CLKDIV;                   //[15:0] 须将内部工作频率分到SCL频率的5倍，即CLKDIV = SYS_Freq/5/SCL_Freq - 1
+
+    __IO uint32_t CTRL;
+
+    __IO uint32_t MSTDAT;
+
+    __IO uint32_t MSTCMD;
+
+    __IO uint32_t SLVCR;
+
+    __IO uint32_t SLVIF;
+
+    __IO uint32_t SLVTX;
+
+    __IO uint32_t SLVRX;
+} I2C_TypeDef;
+
+
+#define I2C_CTRL_MSTIE_Pos          6
+#define I2C_CTRL_MSTIE_Msk          (0x01 << I2C_CTRL_MSTIE_Pos)
+#define I2C_CTRL_EN_Pos             7
+#define I2C_CTRL_EN_Msk             (0x01 << I2C_CTRL_EN_Pos)
+
+#define I2C_MSTCMD_IF_Pos           0       //1 有等待处理的中断，写1清零   有两种情况下此位硬件置位：1、一个字节传输完成  2、总线访问权丢失
+#define I2C_MSTCMD_IF_Msk           (0x01 << I2C_MSTCMD_IF_Pos)
+#define I2C_MSTCMD_TIP_Pos          1       //Transmission In Process
+#define I2C_MSTCMD_TIP_Msk          (0x01 << I2C_MSTCMD_TIP_Pos)
+#define I2C_MSTCMD_ACK_Pos          3       //接收模式下，0 向发送端反馈ACK 1 向发送端反馈NACK
+#define I2C_MSTCMD_ACK_Msk          (0x01 << I2C_MSTCMD_ACK_Pos)
+#define I2C_MSTCMD_WR_Pos           4       //    向Slave写数据时，把这一位写1，自动清零
+#define I2C_MSTCMD_WR_Msk           (0x01 << I2C_MSTCMD_WR_Pos)
+#define I2C_MSTCMD_RD_Pos           5       //写：从Slave读数据时，把这一位写1，自动清零  读：当I2C模块失去总线的访问权时硬件置1
+#define I2C_MSTCMD_RD_Msk           (0x01 << I2C_MSTCMD_RD_Pos)
+#define I2C_MSTCMD_BUSY_Pos         6       //读：当检测到START之后，这一位变1；当检测到STOP之后，这一位变0
+#define I2C_MSTCMD_BUSY_Msk         (0x01 << I2C_MSTCMD_BUSY_Pos)
+#define I2C_MSTCMD_STO_Pos          6       //写：产生STOP，自动清零
+#define I2C_MSTCMD_STO_Msk          (0x01 << I2C_MSTCMD_STO_Pos)
+#define I2C_MSTCMD_RXACK_Pos        7       //读：接收到的Slave的ACK位，0 收到ACK  1 收到NACK
+#define I2C_MSTCMD_RXACK_Msk        (0x01 << I2C_MSTCMD_RXACK_Pos)
+#define I2C_MSTCMD_STA_Pos          7       //写：产生START，自动清零
+#define I2C_MSTCMD_STA_Msk          (0x01 << I2C_MSTCMD_STA_Pos)
+
+#define I2C_SLVCR_IM_RXEND_Pos      0       //接收完成中断禁止
+#define I2C_SLVCR_IM_RXEND_Msk      (0x01 << I2C_SLVCR_IM_RXEND_Pos)
+#define I2C_SLVCR_IM_TXEND_Pos      1       //发送完成中断禁止
+#define I2C_SLVCR_IM_TXEND_Msk      (0x01 << I2C_SLVCR_IM_TXEND_Pos)
+#define I2C_SLVCR_IM_STADET_Pos     2       //检测到起始中断禁止
+#define I2C_SLVCR_IM_STADET_Msk     (0x01 << I2C_SLVCR_IM_STADET_Pos)
+#define I2C_SLVCR_IM_STODET_Pos     3       //检测到停止中断禁止
+#define I2C_SLVCR_IM_STODET_Msk     (0x01 << I2C_SLVCR_IM_STODET_Pos)
+#define I2C_SLVCR_IM_RDREQ_Pos      4       //接收到读请求中断禁止
+#define I2C_SLVCR_IM_RDREQ_Msk      (0x01 << I2C_SLVCR_IM_RDREQ_Pos)
+#define I2C_SLVCR_IM_WRREQ_Pos      5       //接收到写请求中断禁止
+#define I2C_SLVCR_IM_WRREQ_Msk      (0x01 << I2C_SLVCR_IM_WRREQ_Pos)
+#define I2C_SLVCR_ADDR7b_Pos        16      //1 7位地址模式    0 10位地址模式
+#define I2C_SLVCR_ADDR7b_Msk        (0x01 << I2C_SLVCR_ADDR7b_Pos)
+#define I2C_SLVCR_ACK_Pos           17      //1 应答ACK    0 应答NACK
+#define I2C_SLVCR_ACK_Msk           (0x01 << I2C_SLVCR_ACK_Pos)
+#define I2C_SLVCR_SLAVE_Pos         18      //1 从机模式   0 主机模式
+#define I2C_SLVCR_SLAVE_Msk         (0x01 << I2C_SLVCR_SLAVE_Pos)
+#define I2C_SLVCR_DEBOUNCE_Pos      19      //去抖动使能
+#define I2C_SLVCR_DEBOUNCE_Msk      (0x01 << I2C_SLVCR_DEBOUNCE_Pos)
+#define I2C_SLVCR_ADDR_Pos          20      //从机地址
+#define I2C_SLVCR_ADDR_Msk          (0x3FF << I2C_SLVCR_ADDR_Pos)
+
+#define I2C_SLVIF_RXEND_Pos         0       //接收完成中断标志，写1清零
+#define I2C_SLVIF_RXEND_Msk         (0x01 << I2C_SLVIF_RXEND_Pos)
+#define I2C_SLVIF_TXEND_Pos         1       //发送完成中断标志，写1清零
+#define I2C_SLVIF_TXEND_Msk         (0x01 << I2C_SLVIF_TXEND_Pos)
+#define I2C_SLVIF_STADET_Pos        2       //检测到起始中断标志，写1清零
+#define I2C_SLVIF_STADET_Msk        (0x01 << I2C_SLVIF_STADET_Pos)
+#define I2C_SLVIF_STODET_Pos        3       //检测到停止中断标志，写1清零
+#define I2C_SLVIF_STODET_Msk        (0x01 << I2C_SLVIF_STODET_Pos)
+#define I2C_SLVIF_RDREQ_Pos         4       //接收到读请求中断标志
+#define I2C_SLVIF_RDREQ_Msk         (0x01 << I2C_SLVIF_RDREQ_Pos)
+#define I2C_SLVIF_WRREQ_Pos         5       //接收到写请求中断标志
+#define I2C_SLVIF_WRREQ_Msk         (0x01 << I2C_SLVIF_WRREQ_Pos)
+#define I2C_SLVIF_ACTIVE_Pos        6       //slave 有效
+#define I2C_SLVIF_ACTIVE_Msk        (0x01 << I2C_SLVIF_ACTIVE_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t CTRL;
+
+    __IO uint32_t START;
+
+    __IO uint32_t IE;
+
+    __IO uint32_t IF;
+
+    struct {
+        __IO uint32_t STAT;
+
+        __IO uint32_t DATA;
+
+             uint32_t RESERVED[2];
+    } CH[8];
+
+    __IO uint32_t CTRL1;
+
+    __IO uint32_t CTRL2;
+
+         uint32_t RESERVED[2];
+
+    __IO uint32_t CALIBSET;
+
+    __IO uint32_t CALIBEN;
+} ADC_TypeDef;
+
+
+#define ADC_CTRL_CH0_Pos            0       //通道选中
+#define ADC_CTRL_CH0_Msk            (0x01 << ADC_CTRL_CH0_Pos)
+#define ADC_CTRL_CH1_Pos            1
+#define ADC_CTRL_CH1_Msk            (0x01 << ADC_CTRL_CH1_Pos)
+#define ADC_CTRL_CH2_Pos            2
+#define ADC_CTRL_CH2_Msk            (0x01 << ADC_CTRL_CH2_Pos)
+#define ADC_CTRL_CH3_Pos            3
+#define ADC_CTRL_CH3_Msk            (0x01 << ADC_CTRL_CH3_Pos)
+#define ADC_CTRL_CH4_Pos            4
+#define ADC_CTRL_CH4_Msk            (0x01 << ADC_CTRL_CH4_Pos)
+#define ADC_CTRL_CH5_Pos            5
+#define ADC_CTRL_CH5_Msk            (0x01 << ADC_CTRL_CH5_Pos)
+#define ADC_CTRL_CH6_Pos            6
+#define ADC_CTRL_CH6_Msk            (0x01 << ADC_CTRL_CH6_Pos)
+#define ADC_CTRL_CH7_Pos            7
+#define ADC_CTRL_CH7_Msk            (0x01 << ADC_CTRL_CH7_Pos)
+#define ADC_CTRL_AVG_Pos            8       //0 1次采样      1 2次采样取平均值      3 4次采样取平均值      7 8次采样取平均值      15 16次采样取平均值
+#define ADC_CTRL_AVG_Msk            (0x0F << ADC_CTRL_AVG_Pos)
+#define ADC_CTRL_EN_Pos             12
+#define ADC_CTRL_EN_Msk             (0x01 << ADC_CTRL_EN_Pos)
+#define ADC_CTRL_CONT_Pos           13      //Continuous conversion，只在软件启动模式下有效，0 单次转换，转换完成后START位自动清除停止转换
+#define ADC_CTRL_CONT_Msk           (0x01 << ADC_CTRL_CONT_Pos)                         //   1 连续转换，启动后一直采样、转换，直到软件清除START位
+#define ADC_CTRL_TRIG_Pos           14      //转换触发方式：0 软件启动转换     1 PWM触发
+#define ADC_CTRL_TRIG_Msk           (0x01 << ADC_CTRL_TRIG_Pos)
+#define ADC_CTRL_CLKSRC_Pos         15      //0 VCO    1 HRC
+#define ADC_CTRL_CLKSRC_Msk         (0x01 << ADC_CTRL_CLKSRC_Pos)
+#define ADC_CTRL_FIFOCLR_Pos        24      //[24] CH0_FIFO_CLR   [25] CH1_FIFO_CLR    ...    [31] CH7_FIFO_CLR
+#define ADC_CTRL_FIFOCLR_Msk        (0xFFu<< ADC_CTRL_FIFOCLR_Pos)
+
+#define ADC_START_GO_Pos            0       //软件触发模式下，写1启动ADC采样和转换，在单次模式下转换完成后硬件自动清零，在扫描模式下必须软件写0停止ADC转换
+#define ADC_START_GO_Msk            (0x01 << ADC_START_GO_Pos)
+#define ADC_START_BUSY_Pos          4
+#define ADC_START_BUSY_Msk          (0x01 << ADC_START_BUSY_Pos)
+
+#define ADC_IE_CH0EOC_Pos           0       //End Of Convertion
+#define ADC_IE_CH0EOC_Msk           (0x01 << ADC_IE_CH0EOC_Pos)
+#define ADC_IE_CH0OVF_Pos           1       //Overflow
+#define ADC_IE_CH0OVF_Msk           (0x01 << ADC_IE_CH0OVF_Pos)
+#define ADC_IE_CH0HFULL_Pos         2       //FIFO Half Full
+#define ADC_IE_CH0HFULL_Msk         (0x01 << ADC_IE_CH0HFULL_Pos)
+#define ADC_IE_CH0FULL_Pos          3       //FIFO Full
+#define ADC_IE_CH0FULL_Msk          (0x01 << ADC_IE_CH0FULL_Pos)
+#define ADC_IE_CH1EOC_Pos           4
+#define ADC_IE_CH1EOC_Msk           (0x01 << ADC_IE_CH1EOC_Pos)
+#define ADC_IE_CH1OVF_Pos           5
+#define ADC_IE_CH1OVF_Msk           (0x01 << ADC_IE_CH1OVF_Pos)
+#define ADC_IE_CH1HFULL_Pos         6
+#define ADC_IE_CH1HFULL_Msk         (0x01 << ADC_IE_CH1HFULL_Pos)
+#define ADC_IE_CH1FULL_Pos          7
+#define ADC_IE_CH1FULL_Msk          (0x01 << ADC_IE_CH1FULL_Pos)
+#define ADC_IE_CH2EOC_Pos           8
+#define ADC_IE_CH2EOC_Msk           (0x01 << ADC_IE_CH2EOC_Pos)
+#define ADC_IE_CH2OVF_Pos           9
+#define ADC_IE_CH2OVF_Msk           (0x01 << ADC_IE_CH2OVF_Pos)
+#define ADC_IE_CH2HFULL_Pos         10
+#define ADC_IE_CH2HFULL_Msk         (0x01 << ADC_IE_CH2HFULL_Pos)
+#define ADC_IE_CH2FULL_Pos          11
+#define ADC_IE_CH2FULL_Msk          (0x01 << ADC_IE_CH2FULL_Pos)
+#define ADC_IE_CH3EOC_Pos           12
+#define ADC_IE_CH3EOC_Msk           (0x01 << ADC_IE_CH3EOC_Pos)
+#define ADC_IE_CH3OVF_Pos           13
+#define ADC_IE_CH3OVF_Msk           (0x01 << ADC_IE_CH3OVF_Pos)
+#define ADC_IE_CH3HFULL_Pos         14
+#define ADC_IE_CH3HFULL_Msk         (0x01 << ADC_IE_CH3HFULL_Pos)
+#define ADC_IE_CH3FULL_Pos          15
+#define ADC_IE_CH3FULL_Msk          (0x01 << ADC_IE_CH3FULL_Pos)
+#define ADC_IE_CH4EOC_Pos           16
+#define ADC_IE_CH4EOC_Msk           (0x01 << ADC_IE_CH4EOC_Pos)
+#define ADC_IE_CH4OVF_Pos           17
+#define ADC_IE_CH4OVF_Msk           (0x01 << ADC_IE_CH4OVF_Pos)
+#define ADC_IE_CH4HFULL_Pos         18
+#define ADC_IE_CH4HFULL_Msk         (0x01 << ADC_IE_CH4HFULL_Pos)
+#define ADC_IE_CH4FULL_Pos          19
+#define ADC_IE_CH4FULL_Msk          (0x01 << ADC_IE_CH4FULL_Pos)
+#define ADC_IE_CH5EOC_Pos           20
+#define ADC_IE_CH5EOC_Msk           (0x01 << ADC_IE_CH5EOC_Pos)
+#define ADC_IE_CH5OVF_Pos           21
+#define ADC_IE_CH5OVF_Msk           (0x01 << ADC_IE_CH5OVF_Pos)
+#define ADC_IE_CH5HFULL_Pos         22
+#define ADC_IE_CH5HFULL_Msk         (0x01 << ADC_IE_CH5HFULL_Pos)
+#define ADC_IE_CH5FULL_Pos          23
+#define ADC_IE_CH5FULL_Msk          (0x01 << ADC_IE_CH5FULL_Pos)
+#define ADC_IE_CH6EOC_Pos           24
+#define ADC_IE_CH6EOC_Msk           (0x01 << ADC_IE_CH6EOC_Pos)
+#define ADC_IE_CH6OVF_Pos           25
+#define ADC_IE_CH6OVF_Msk           (0x01 << ADC_IE_CH6OVF_Pos)
+#define ADC_IE_CH6HFULL_Pos         26
+#define ADC_IE_CH6HFULL_Msk         (0x01 << ADC_IE_CH6HFULL_Pos)
+#define ADC_IE_CH6FULL_Pos          27
+#define ADC_IE_CH6FULL_Msk          (0x01 << ADC_IE_CH6FULL_Pos)
+#define ADC_IE_CH7EOC_Pos           28
+#define ADC_IE_CH7EOC_Msk           (0x01 << ADC_IE_CH7EOC_Pos)
+#define ADC_IE_CH7OVF_Pos           29
+#define ADC_IE_CH7OVF_Msk           (0x01 << ADC_IE_CH7OVF_Pos)
+#define ADC_IE_CH7HFULL_Pos         30
+#define ADC_IE_CH7HFULL_Msk         (0x01 << ADC_IE_CH7HFULL_Pos)
+#define ADC_IE_CH7FULL_Pos          31
+#define ADC_IE_CH7FULL_Msk          (0x01u<< ADC_IE_CH7FULL_Pos)
+
+#define ADC_IF_CH0EOC_Pos           0       //写1清零
+#define ADC_IF_CH0EOC_Msk           (0x01 << ADC_IF_CH0EOC_Pos)
+#define ADC_IF_CH0OVF_Pos           1       //写1清零
+#define ADC_IF_CH0OVF_Msk           (0x01 << ADC_IF_CH0OVF_Pos)
+#define ADC_IF_CH0HFULL_Pos         2       //写1清零
+#define ADC_IF_CH0HFULL_Msk         (0x01 << ADC_IF_CH0HFULL_Pos)
+#define ADC_IF_CH0FULL_Pos          3       //写1清零
+#define ADC_IF_CH0FULL_Msk          (0x01 << ADC_IF_CH0FULL_Pos)
+#define ADC_IF_CH1EOC_Pos           4
+#define ADC_IF_CH1EOC_Msk           (0x01 << ADC_IF_CH1EOC_Pos)
+#define ADC_IF_CH1OVF_Pos           5
+#define ADC_IF_CH1OVF_Msk           (0x01 << ADC_IF_CH1OVF_Pos)
+#define ADC_IF_CH1HFULL_Pos         6
+#define ADC_IF_CH1HFULL_Msk         (0x01 << ADC_IF_CH1HFULL_Pos)
+#define ADC_IF_CH1FULL_Pos          7
+#define ADC_IF_CH1FULL_Msk          (0x01 << ADC_IF_CH1FULL_Pos)
+#define ADC_IF_CH2EOC_Pos           8
+#define ADC_IF_CH2EOC_Msk           (0x01 << ADC_IF_CH2EOC_Pos)
+#define ADC_IF_CH2OVF_Pos           9
+#define ADC_IF_CH2OVF_Msk           (0x01 << ADC_IF_CH2OVF_Pos)
+#define ADC_IF_CH2HFULL_Pos         10
+#define ADC_IF_CH2HFULL_Msk         (0x01 << ADC_IF_CH2HFULL_Pos)
+#define ADC_IF_CH2FULL_Pos          11
+#define ADC_IF_CH2FULL_Msk          (0x01 << ADC_IF_CH2FULL_Pos)
+#define ADC_IF_CH3EOC_Pos           12
+#define ADC_IF_CH3EOC_Msk           (0x01 << ADC_IF_CH3EOC_Pos)
+#define ADC_IF_CH3OVF_Pos           13
+#define ADC_IF_CH3OVF_Msk           (0x01 << ADC_IF_CH3OVF_Pos)
+#define ADC_IF_CH3HFULL_Pos         14
+#define ADC_IF_CH3HFULL_Msk         (0x01 << ADC_IF_CH3HFULL_Pos)
+#define ADC_IF_CH3FULL_Pos          15
+#define ADC_IF_CH3FULL_Msk          (0x01 << ADC_IF_CH3FULL_Pos)
+#define ADC_IF_CH4EOC_Pos           16
+#define ADC_IF_CH4EOC_Msk           (0x01 << ADC_IF_CH4EOC_Pos)
+#define ADC_IF_CH4OVF_Pos           17
+#define ADC_IF_CH4OVF_Msk           (0x01 << ADC_IF_CH4OVF_Pos)
+#define ADC_IF_CH4HFULL_Pos         18
+#define ADC_IF_CH4HFULL_Msk         (0x01 << ADC_IF_CH4HFULL_Pos)
+#define ADC_IF_CH4FULL_Pos          19
+#define ADC_IF_CH4FULL_Msk          (0x01 << ADC_IF_CH4FULL_Pos)
+#define ADC_IF_CH5EOC_Pos           20
+#define ADC_IF_CH5EOC_Msk           (0x01 << ADC_IF_CH5EOC_Pos)
+#define ADC_IF_CH5OVF_Pos           21
+#define ADC_IF_CH5OVF_Msk           (0x01 << ADC_IF_CH5OVF_Pos)
+#define ADC_IF_CH5HFULL_Pos         22
+#define ADC_IF_CH5HFULL_Msk         (0x01 << ADC_IF_CH5HFULL_Pos)
+#define ADC_IF_CH5FULL_Pos          23
+#define ADC_IF_CH5FULL_Msk          (0x01 << ADC_IF_CH5FULL_Pos)
+#define ADC_IF_CH6EOC_Pos           24
+#define ADC_IF_CH6EOC_Msk           (0x01 << ADC_IF_CH6EOC_Pos)
+#define ADC_IF_CH6OVF_Pos           25
+#define ADC_IF_CH6OVF_Msk           (0x01 << ADC_IF_CH6OVF_Pos)
+#define ADC_IF_CH6HFULL_Pos         26
+#define ADC_IF_CH6HFULL_Msk         (0x01 << ADC_IF_CH6HFULL_Pos)
+#define ADC_IF_CH6FULL_Pos          27
+#define ADC_IF_CH6FULL_Msk          (0x01 << ADC_IF_CH6FULL_Pos)
+#define ADC_IF_CH7EOC_Pos           28
+#define ADC_IF_CH7EOC_Msk           (0x01 << ADC_IF_CH7EOC_Pos)
+#define ADC_IF_CH7OVF_Pos           29
+#define ADC_IF_CH7OVF_Msk           (0x01 << ADC_IF_CH7OVF_Pos)
+#define ADC_IF_CH7HFULL_Pos         30
+#define ADC_IF_CH7HFULL_Msk         (0x01 << ADC_IF_CH7HFULL_Pos)
+#define ADC_IF_CH7FULL_Pos          31
+#define ADC_IF_CH7FULL_Msk          (0x01 << ADC_IF_CH7FULL_Pos)
+
+#define ADC_STAT_EOC_Pos            0       //写1清零
+#define ADC_STAT_EOC_Msk            (0x01 << ADC_STAT_EOC_Pos)
+#define ADC_STAT_OVF_Pos            1       //读数据寄存器清除
+#define ADC_STAT_OVF_Msk            (0x01 << ADC_STAT_OVF_Pos)
+#define ADC_STAT_HFULL_Pos          2
+#define ADC_STAT_HFULL_Msk          (0x01 << ADC_STAT_HFULL_Pos)
+#define ADC_STAT_FULL_Pos           3
+#define ADC_STAT_FULL_Msk           (0x01 << ADC_STAT_FULL_Pos)
+#define ADC_STAT_EMPTY_Pos          4
+#define ADC_STAT_EMPTY_Msk          (0x01 << ADC_STAT_EMPTY_Pos)
+
+#define ADC_CTRL1_RIN_Pos           4       //输入阻抗：0 无穷大   1 105K   2 90K   3 75K   4 60K   5 45K   6 30K   7 15K
+#define ADC_CTRL1_RIN_Msk           (0x07 << ADC_CTRL1_RIN_Pos)
+
+#define ADC_CTRL2_RESET_Pos         0       //数字电路复位
+#define ADC_CTRL2_RESET_Msk         (0x01 << ADC_CTRL2_RESET_Pos)
+#define ADC_CTRL2_ADCEVCM_Pos       1       //ADC External VCM，ADC与PGA输出共模电平选择
+#define ADC_CTRL2_ADCEVCM_Msk       (0x01 << ADC_CTRL2_ADCEVCM_Pos)
+#define ADC_CTRL2_PGAIVCM_Pos       2       //PGA Internal VCM，PGA输入共模电平选择
+#define ADC_CTRL2_PGAIVCM_Msk       (0x01 << ADC_CTRL2_PGAIVCM_Pos)
+#define ADC_CTRL2_PGAGAIN_Pos       3       //0 25.1dB    1 21.6dB    2 11.1dB    3 3.5dB    4 0dB(1.8V)    5 -2.9dB    6 -5.3dB
+#define ADC_CTRL2_PGAGAIN_Msk       (0x07 << ADC_CTRL2_PGAGAIN_Pos)
+#define ADC_CTRL2_REFPOUT_Pos       23      //1 ADC 内部 1.2V REFP电压输出到外部REFP引脚，用于测量，或在需要1.2V外部REFP时节省成本
+#define ADC_CTRL2_REFPOUT_Msk       (0x01 << ADC_CTRL2_REFPOUT_Pos
+#define ADC_CTRL2_CLKDIV_Pos        24      //时钟分频，只在时钟源为HRC时有效
+#define ADC_CTRL2_CLKDIV_Msk        (0x1F << ADC_CTRL2_CLKDIV_Pos)
+#define ADC_CTRL2_PGAVCM_Pos        29
+#define ADC_CTRL2_PGAVCM_Msk        (0x07u<< ADC_CTRL2_PGAVCM_Pos)
+
+#define ADC_CALIBSET_OFFSET_Pos     0
+#define ADC_CALIBSET_OFFSET_Msk     (0x1FF<< ADC_CALIBSET_OFFSET_Pos)
+#define ADC_CALIBSET_K_Pos          16
+#define ADC_CALIBSET_K_Msk          (0x1FF<< ADC_CALIBSET_K_Pos)
+
+#define ADC_CALIBEN_OFFSET_Pos      0
+#define ADC_CALIBEN_OFFSET_Msk      (0x01 << ADC_CALIBEN_OFFSET_Pos)
+#define ADC_CALIBEN_K_Pos           1
+#define ADC_CALIBEN_K_Msk           (0x01 << ADC_CALIBEN_K_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t MODE;                     //0 普通模式，A、B两路输出互相独立
+                                            //1 互补模式，A、B两路输出都由PERA、HIGHA控制，B路输出与A路输出极性相反，且DZA、DZB控制A、B路输出上升沿推迟时间
+                                            //2 单次模式，同普通模式，但一个周期后自动停止
+                                            //3 对称模式，A、B两路输出互相独立，以两个计数周期产生一个波形输出周期，分辨率提升一倍、频率降低一倍
+                                            //4 对称互补模式，对称模式和互补模式的综合
+
+    __IO uint32_t PERA;                     //[15:0] 周期
+
+    __IO uint32_t HIGHA;                    //[15:0] 高电平持续时长
+
+    __IO uint32_t DZA;                      //[9:0] 死区，即上升沿推迟时长，必须小于HIGHA
+
+    __IO uint32_t PERB;
+
+    __IO uint32_t HIGHB;
+
+    __IO uint32_t DZB;
+
+    __IO uint32_t INIOUT;                   //Init Output level，初始输出电平
+} PWM_TypeDef;
+
+
+#define PWM_INIOUT_PWMA_Pos     0
+#define PWM_INIOUT_PWMA_Msk     (0x01 << PWM_INIOUT_PWMA_Pos)
+#define PWM_INIOUT_PWMB_Pos     1
+#define PWM_INIOUT_PWMB_Msk     (0x01 << PWM_INIOUT_PWMB_Pos)
+
+
+typedef struct {
+    __IO uint32_t FORCEH;
+
+    __IO uint32_t ADTRG0A;
+    __IO uint32_t ADTRG0B;
+
+    __IO uint32_t ADTRG1A;
+    __IO uint32_t ADTRG1B;
+
+    __IO uint32_t ADTRG2A;
+    __IO uint32_t ADTRG2B;
+
+    __IO uint32_t ADTRG3A;
+    __IO uint32_t ADTRG3B;
+
+    __IO uint32_t ADTRG4A;
+    __IO uint32_t ADTRG4B;
+
+    __IO uint32_t ADTRG5A;
+    __IO uint32_t ADTRG5B;
+
+         uint32_t RESERVED[3];
+
+    __IO uint32_t HALT;                     //刹车控制
+
+    __IO uint32_t CHEN;
+
+    __IO uint32_t IE;
+
+    __IO uint32_t IF;
+
+    __IO uint32_t IM;                       //Interrupt Mask
+
+    __IO uint32_t IRS;                      //Interrupt Raw Stat
+} PWMG_TypeDef;
+
+
+#define PWMG_FORCEH_PWM0_Pos        0
+#define PWMG_FORCEH_PWM0_Msk        (0x01 << PWMG_FORCEH_PWM0_Pos)
+#define PWMG_FORCEH_PWM1_Pos        1
+#define PWMG_FORCEH_PWM1_Msk        (0x01 << PWMG_FORCEH_PWM1_Pos)
+#define PWMG_FORCEH_PWM2_Pos        2
+#define PWMG_FORCEH_PWM2_Msk        (0x01 << PWMG_FORCEH_PWM2_Pos)
+#define PWMG_FORCEH_PWM3_Pos        3
+#define PWMG_FORCEH_PWM3_Msk        (0x01 << PWMG_FORCEH_PWM3_Pos)
+#define PWMG_FORCEH_PWM4_Pos        4
+#define PWMG_FORCEH_PWM4_Msk        (0x01 << PWMG_FORCEH_PWM4_Pos)
+#define PWMG_FORCEH_PWM5_Pos        5
+#define PWMG_FORCEH_PWM5_Msk        (0x01 << PWMG_FORCEH_PWM5_Pos)
+
+#define PWMG_ADTRG_VALUE_Pos        0
+#define PWMG_ADTRG_VALUE_Msk        (0xFFFF << PWMG_ADTRG0A_VALUE_Pos)
+#define PWMG_ADTRG_EVEN_Pos         16      //1 偶数周期生效    0 奇数周期生效
+#define PWMG_ADTRG_EVEN_Msk         (0x01 << PWMG_ADTRG0A_EVEN_Pos)
+#define PWMG_ADTRG_EN_Pos           17
+#define PWMG_ADTRG_EN_Msk           (0x01 << PWMG_ADTRG0A_EN_Pos)
+
+#define PWMG_HALT_EN_Pos            0
+#define PWMG_HALT_EN_Msk            (0x01 << PWMG_HALT_EN_Pos)
+#define PWMG_HALT_PWM0_Pos          1
+#define PWMG_HALT_PWM0_Msk          (0x01 << PWMG_HALT_PWM0_Pos)
+#define PWMG_HALT_PWM1_Pos          2
+#define PWMG_HALT_PWM1_Msk          (0x01 << PWMG_HALT_PWM1_Pos)
+#define PWMG_HALT_PWM2_Pos          3
+#define PWMG_HALT_PWM2_Msk          (0x01 << PWMG_HALT_PWM2_Pos)
+#define PWMG_HALT_PWM3_Pos          4
+#define PWMG_HALT_PWM3_Msk          (0x01 << PWMG_HALT_PWM3_Pos)
+#define PWMG_HALT_PWM4_Pos          5
+#define PWMG_HALT_PWM4_Msk          (0x01 << PWMG_HALT_PWM4_Pos)
+#define PWMG_HALT_PWM5_Pos          6
+#define PWMG_HALT_PWM5_Msk          (0x01 << PWMG_HALT_PWM5_Pos)
+#define PWMG_HALT_STOPCNT_Pos       7       //1 刹车时将PWM计数器清零，停止计数    0 刹车时，PWM计数器继续计数
+#define PWMG_HALT_STOPCNT_Msk       (0x01 << PWMG_HALT_STOPCNT_Pos)
+#define PWMG_HALT_INLVL_Pos         8       //1 刹车输入高电平有效
+#define PWMG_HALT_INLVL_Msk         (0x01 << PWMG_HALT_INLVL_Pos)
+#define PWMG_HALT_OUTLVL_Pos        9       //1 刹车过程中输出高电平
+#define PWMG_HALT_OUTLVL_Msk        (0x01 << PWMG_HALT_OUTLVL_Pos)
+#define PWMG_HALT_STAT_Pos          10      //1 正在刹车
+#define PWMG_HALT_STAT_Msk          (0x01 << PWMG_HALT_STAT_Pos)
+
+#define PWMG_CHEN_PWM0A_Pos         0
+#define PWMG_CHEN_PWM0A_Msk         (0x01 << PWMG_CHEN_PWM0A_Pos)
+#define PWMG_CHEN_PWM0B_Pos         1
+#define PWMG_CHEN_PWM0B_Msk         (0x01 << PWMG_CHEN_PWM0B_Pos)
+#define PWMG_CHEN_PWM1A_Pos         2
+#define PWMG_CHEN_PWM1A_Msk         (0x01 << PWMG_CHEN_PWM1A_Pos)
+#define PWMG_CHEN_PWM1B_Pos         3
+#define PWMG_CHEN_PWM1B_Msk         (0x01 << PWMG_CHEN_PWM1B_Pos)
+#define PWMG_CHEN_PWM2A_Pos         4
+#define PWMG_CHEN_PWM2A_Msk         (0x01 << PWMG_CHEN_PWM2A_Pos)
+#define PWMG_CHEN_PWM2B_Pos         5
+#define PWMG_CHEN_PWM2B_Msk         (0x01 << PWMG_CHEN_PWM2B_Pos)
+#define PWMG_CHEN_PWM3A_Pos         6
+#define PWMG_CHEN_PWM3A_Msk         (0x01 << PWMG_CHEN_PWM3A_Pos)
+#define PWMG_CHEN_PWM3B_Pos         7
+#define PWMG_CHEN_PWM3B_Msk         (0x01 << PWMG_CHEN_PWM3B_Pos)
+#define PWMG_CHEN_PWM4A_Pos         8
+#define PWMG_CHEN_PWM4A_Msk         (0x01 << PWMG_CHEN_PWM4A_Pos)
+#define PWMG_CHEN_PWM4B_Pos         9
+#define PWMG_CHEN_PWM4B_Msk         (0x01 << PWMG_CHEN_PWM4B_Pos)
+#define PWMG_CHEN_PWM5A_Pos         10
+#define PWMG_CHEN_PWM5A_Msk         (0x01 << PWMG_CHEN_PWM5A_Pos)
+#define PWMG_CHEN_PWM5B_Pos         11
+#define PWMG_CHEN_PWM5B_Msk         (0x01 << PWMG_CHEN_PWM5B_Pos)
+
+
+#define PWMG_IE_NEWP0A_Pos          0
+#define PWMG_IE_NEWP0A_Msk          (0x01 << PWMG_IE_NEWP0A_Pos)
+#define PWMG_IE_NEWP0B_Pos          1
+#define PWMG_IE_NEWP0B_Msk          (0x01 << PWMG_IE_NEWP0B_Pos)
+#define PWMG_IE_NEWP1A_Pos          2
+#define PWMG_IE_NEWP1A_Msk          (0x01 << PWMG_IE_NEWP1A_Pos)
+#define PWMG_IE_NEWP1B_Pos          3
+#define PWMG_IE_NEWP1B_Msk          (0x01 << PWMG_IE_NEWP1B_Pos)
+#define PWMG_IE_NEWP2A_Pos          4
+#define PWMG_IE_NEWP2A_Msk          (0x01 << PWMG_IE_NEWP2A_Pos)
+#define PWMG_IE_NEWP2B_Pos          5
+#define PWMG_IE_NEWP2B_Msk          (0x01 << PWMG_IE_NEWP2B_Pos)
+#define PWMG_IE_NEWP3A_Pos          6
+#define PWMG_IE_NEWP3A_Msk          (0x01 << PWMG_IE_NEWP3A_Pos)
+#define PWMG_IE_NEWP3B_Pos          7
+#define PWMG_IE_NEWP3B_Msk          (0x01 << PWMG_IE_NEWP3B_Pos)
+#define PWMG_IE_NEWP4A_Pos          8
+#define PWMG_IE_NEWP4A_Msk          (0x01 << PWMG_IE_NEWP4A_Pos)
+#define PWMG_IE_NEWP4B_Pos          9
+#define PWMG_IE_NEWP4B_Msk          (0x01 << PWMG_IE_NEWP4B_Pos)
+#define PWMG_IE_NEWP5A_Pos          10
+#define PWMG_IE_NEWP5A_Msk          (0x01 << PWMG_IE_NEWP5A_Pos)
+#define PWMG_IE_NEWP5B_Pos          11
+#define PWMG_IE_NEWP5B_Msk          (0x01 << PWMG_IE_NEWP5B_Pos)
+#define PWMG_IE_HEND0A_Pos          12
+#define PWMG_IE_HEND0A_Msk          (0x01 << PWMG_IE_HEND0A_Pos)
+#define PWMG_IE_HEND0B_Pos          13
+#define PWMG_IE_HEND0B_Msk          (0x01 << PWMG_IE_HEND0B_Pos)
+#define PWMG_IE_HEND1A_Pos          14
+#define PWMG_IE_HEND1A_Msk          (0x01 << PWMG_IE_HEND1A_Pos)
+#define PWMG_IE_HEND1B_Pos          15
+#define PWMG_IE_HEND1B_Msk          (0x01 << PWMG_IE_HEND1B_Pos)
+#define PWMG_IE_HEND2A_Pos          16
+#define PWMG_IE_HEND2A_Msk          (0x01 << PWMG_IE_HEND2A_Pos)
+#define PWMG_IE_HEND2B_Pos          17
+#define PWMG_IE_HEND2B_Msk          (0x01 << PWMG_IE_HEND2B_Pos)
+#define PWMG_IE_HEND3A_Pos          18
+#define PWMG_IE_HEND3A_Msk          (0x01 << PWMG_IE_HEND3A_Pos)
+#define PWMG_IE_HEND3B_Pos          19
+#define PWMG_IE_HEND3B_Msk          (0x01 << PWMG_IE_HEND3B_Pos)
+#define PWMG_IE_HEND4A_Pos          20
+#define PWMG_IE_HEND4A_Msk          (0x01 << PWMG_IE_HEND4A_Pos)
+#define PWMG_IE_HEND4B_Pos          21
+#define PWMG_IE_HEND4B_Msk          (0x01 << PWMG_IE_HEND4B_Pos)
+#define PWMG_IE_HEND5A_Pos          22
+#define PWMG_IE_HEND5A_Msk          (0x01 << PWMG_IE_HEND5A_Pos)
+#define PWMG_IE_HEND5B_Pos          23
+#define PWMG_IE_HEND5B_Msk          (0x01 << PWMG_IE_HEND5B_Pos)
+#define PWMG_IE_HALT_Pos            24
+#define PWMG_IE_HALT_Msk            (0x01 << PWMG_IE_HALT_Pos)
+
+#define PWMG_IF_NEWP0A_Pos          0
+#define PWMG_IF_NEWP0A_Msk          (0x01 << PWMG_IF_NEWP0A_Pos)
+#define PWMG_IF_NEWP0B_Pos          1
+#define PWMG_IF_NEWP0B_Msk          (0x01 << PWMG_IF_NEWP0B_Pos)
+#define PWMG_IF_NEWP1A_Pos          2
+#define PWMG_IF_NEWP1A_Msk          (0x01 << PWMG_IF_NEWP1A_Pos)
+#define PWMG_IF_NEWP1B_Pos          3
+#define PWMG_IF_NEWP1B_Msk          (0x01 << PWMG_IF_NEWP1B_Pos)
+#define PWMG_IF_NEWP2A_Pos          4
+#define PWMG_IF_NEWP2A_Msk          (0x01 << PWMG_IF_NEWP2A_Pos)
+#define PWMG_IF_NEWP2B_Pos          5
+#define PWMG_IF_NEWP2B_Msk          (0x01 << PWMG_IF_NEWP2B_Pos)
+#define PWMG_IF_NEWP3A_Pos          6
+#define PWMG_IF_NEWP3A_Msk          (0x01 << PWMG_IF_NEWP3A_Pos)
+#define PWMG_IF_NEWP3B_Pos          7
+#define PWMG_IF_NEWP3B_Msk          (0x01 << PWMG_IF_NEWP3B_Pos)
+#define PWMG_IF_NEWP4A_Pos          8
+#define PWMG_IF_NEWP4A_Msk          (0x01 << PWMG_IF_NEWP4A_Pos)
+#define PWMG_IF_NEWP4B_Pos          9
+#define PWMG_IF_NEWP4B_Msk          (0x01 << PWMG_IF_NEWP4B_Pos)
+#define PWMG_IF_NEWP5A_Pos          10
+#define PWMG_IF_NEWP5A_Msk          (0x01 << PWMG_IF_NEWP5A_Pos)
+#define PWMG_IF_NEWP5B_Pos          11
+#define PWMG_IF_NEWP5B_Msk          (0x01 << PWMG_IF_NEWP5B_Pos)
+#define PWMG_IF_HEND0A_Pos          12
+#define PWMG_IF_HEND0A_Msk          (0x01 << PWMG_IF_HEND0A_Pos)
+#define PWMG_IF_HEND0B_Pos          13
+#define PWMG_IF_HEND0B_Msk          (0x01 << PWMG_IF_HEND0B_Pos)
+#define PWMG_IF_HEND1A_Pos          14
+#define PWMG_IF_HEND1A_Msk          (0x01 << PWMG_IF_HEND1A_Pos)
+#define PWMG_IF_HEND1B_Pos          15
+#define PWMG_IF_HEND1B_Msk          (0x01 << PWMG_IF_HEND1B_Pos)
+#define PWMG_IF_HEND2A_Pos          16
+#define PWMG_IF_HEND2A_Msk          (0x01 << PWMG_IF_HEND2A_Pos)
+#define PWMG_IF_HEND2B_Pos          17
+#define PWMG_IF_HEND2B_Msk          (0x01 << PWMG_IF_HEND2B_Pos)
+#define PWMG_IF_HEND3A_Pos          18
+#define PWMG_IF_HEND3A_Msk          (0x01 << PWMG_IF_HEND3A_Pos)
+#define PWMG_IF_HEND3B_Pos          19
+#define PWMG_IF_HEND3B_Msk          (0x01 << PWMG_IF_HEND3B_Pos)
+#define PWMG_IF_HEND4A_Pos          20
+#define PWMG_IF_HEND4A_Msk          (0x01 << PWMG_IF_HEND4A_Pos)
+#define PWMG_IF_HEND4B_Pos          21
+#define PWMG_IF_HEND4B_Msk          (0x01 << PWMG_IF_HEND4B_Pos)
+#define PWMG_IF_HEND5A_Pos          22
+#define PWMG_IF_HEND5A_Msk          (0x01 << PWMG_IF_HEND5A_Pos)
+#define PWMG_IF_HEND5B_Pos          23
+#define PWMG_IF_HEND5B_Msk          (0x01 << PWMG_IF_HEND5B_Pos)
+#define PWMG_IF_HALT_Pos            24
+#define PWMG_IF_HALT_Msk            (0x01 << PWMG_IF_HALT_Pos)
+
+#define PWMG_IM_NEWP0A_Pos          0       //Interrupt Mask
+#define PWMG_IM_NEWP0A_Msk          (0x01 << PWMG_IM_NEWP0A_Pos)
+#define PWMG_IM_NEWP0B_Pos          1
+#define PWMG_IM_NEWP0B_Msk          (0x01 << PWMG_IM_NEWP0B_Pos)
+#define PWMG_IM_NEWP1A_Pos          2
+#define PWMG_IM_NEWP1A_Msk          (0x01 << PWMG_IM_NEWP1A_Pos)
+#define PWMG_IM_NEWP1B_Pos          3
+#define PWMG_IM_NEWP1B_Msk          (0x01 << PWMG_IM_NEWP1B_Pos)
+#define PWMG_IM_NEWP2A_Pos          4
+#define PWMG_IM_NEWP2A_Msk          (0x01 << PWMG_IM_NEWP2A_Pos)
+#define PWMG_IM_NEWP2B_Pos          5
+#define PWMG_IM_NEWP2B_Msk          (0x01 << PWMG_IM_NEWP2B_Pos)
+#define PWMG_IM_NEWP3A_Pos          6
+#define PWMG_IM_NEWP3A_Msk          (0x01 << PWMG_IM_NEWP3A_Pos)
+#define PWMG_IM_NEWP3B_Pos          7
+#define PWMG_IM_NEWP3B_Msk          (0x01 << PWMG_IM_NEWP3B_Pos)
+#define PWMG_IM_NEWP4A_Pos          8
+#define PWMG_IM_NEWP4A_Msk          (0x01 << PWMG_IM_NEWP4A_Pos)
+#define PWMG_IM_NEWP4B_Pos          9
+#define PWMG_IM_NEWP4B_Msk          (0x01 << PWMG_IM_NEWP4B_Pos)
+#define PWMG_IM_NEWP5A_Pos          10
+#define PWMG_IM_NEWP5A_Msk          (0x01 << PWMG_IM_NEWP5A_Pos)
+#define PWMG_IM_NEWP5B_Pos          11
+#define PWMG_IM_NEWP5B_Msk          (0x01 << PWMG_IM_NEWP5B_Pos)
+#define PWMG_IM_HEND0A_Pos          12
+#define PWMG_IM_HEND0A_Msk          (0x01 << PWMG_IM_HEND0A_Pos)
+#define PWMG_IM_HEND0B_Pos          13
+#define PWMG_IM_HEND0B_Msk          (0x01 << PWMG_IM_HEND0B_Pos)
+#define PWMG_IM_HEND1A_Pos          14
+#define PWMG_IM_HEND1A_Msk          (0x01 << PWMG_IM_HEND1A_Pos)
+#define PWMG_IM_HEND1B_Pos          15
+#define PWMG_IM_HEND1B_Msk          (0x01 << PWMG_IM_HEND1B_Pos)
+#define PWMG_IM_HEND2A_Pos          16
+#define PWMG_IM_HEND2A_Msk          (0x01 << PWMG_IM_HEND2A_Pos)
+#define PWMG_IM_HEND2B_Pos          17
+#define PWMG_IM_HEND2B_Msk          (0x01 << PWMG_IM_HEND2B_Pos)
+#define PWMG_IM_HEND3A_Pos          18
+#define PWMG_IM_HEND3A_Msk          (0x01 << PWMG_IM_HEND3A_Pos)
+#define PWMG_IM_HEND3B_Pos          19
+#define PWMG_IM_HEND3B_Msk          (0x01 << PWMG_IM_HEND3B_Pos)
+#define PWMG_IM_HEND4A_Pos          20
+#define PWMG_IM_HEND4A_Msk          (0x01 << PWMG_IM_HEND4A_Pos)
+#define PWMG_IM_HEND4B_Pos          21
+#define PWMG_IM_HEND4B_Msk          (0x01 << PWMG_IM_HEND4B_Pos)
+#define PWMG_IM_HEND5A_Pos          22
+#define PWMG_IM_HEND5A_Msk          (0x01 << PWMG_IM_HEND5A_Pos)
+#define PWMG_IM_HEND5B_Pos          23
+#define PWMG_IM_HEND5B_Msk          (0x01 << PWMG_IM_HEND5B_Pos)
+#define PWMG_IM_HALT_Pos            24
+#define PWMG_IM_HALT_Msk            (0x01 << PWMG_IM_HALT_Pos)
+
+#define PWMG_IRS_NEWP0A_Pos         0       //Interrupt Raw State
+#define PWMG_IRS_NEWP0A_Msk         (0x01 << PWMG_IRS_NEWP0A_Pos)
+#define PWMG_IRS_NEWP0B_Pos         1
+#define PWMG_IRS_NEWP0B_Msk         (0x01 << PWMG_IRS_NEWP0B_Pos)
+#define PWMG_IRS_NEWP1A_Pos         2
+#define PWMG_IRS_NEWP1A_Msk         (0x01 << PWMG_IRS_NEWP1A_Pos)
+#define PWMG_IRS_NEWP1B_Pos         3
+#define PWMG_IRS_NEWP1B_Msk         (0x01 << PWMG_IRS_NEWP1B_Pos)
+#define PWMG_IRS_NEWP2A_Pos         4
+#define PWMG_IRS_NEWP2A_Msk         (0x01 << PWMG_IRS_NEWP2A_Pos)
+#define PWMG_IRS_NEWP2B_Pos         5
+#define PWMG_IRS_NEWP2B_Msk         (0x01 << PWMG_IRS_NEWP2B_Pos)
+#define PWMG_IRS_NEWP3A_Pos         6
+#define PWMG_IRS_NEWP3A_Msk         (0x01 << PWMG_IRS_NEWP3A_Pos)
+#define PWMG_IRS_NEWP3B_Pos         7
+#define PWMG_IRS_NEWP3B_Msk         (0x01 << PWMG_IRS_NEWP3B_Pos)
+#define PWMG_IRS_NEWP4A_Pos         8
+#define PWMG_IRS_NEWP4A_Msk         (0x01 << PWMG_IRS_NEWP4A_Pos)
+#define PWMG_IRS_NEWP4B_Pos         9
+#define PWMG_IRS_NEWP4B_Msk         (0x01 << PWMG_IRS_NEWP4B_Pos)
+#define PWMG_IRS_NEWP5A_Pos         10
+#define PWMG_IRS_NEWP5A_Msk         (0x01 << PWMG_IRS_NEWP5A_Pos)
+#define PWMG_IRS_NEWP5B_Pos         11
+#define PWMG_IRS_NEWP5B_Msk         (0x01 << PWMG_IRS_NEWP5B_Pos)
+#define PWMG_IRS_HEND0A_Pos         12
+#define PWMG_IRS_HEND0A_Msk         (0x01 << PWMG_IRS_HEND0A_Pos)
+#define PWMG_IRS_HEND0B_Pos         13
+#define PWMG_IRS_HEND0B_Msk         (0x01 << PWMG_IRS_HEND0B_Pos)
+#define PWMG_IRS_HEND1A_Pos         14
+#define PWMG_IRS_HEND1A_Msk         (0x01 << PWMG_IRS_HEND1A_Pos)
+#define PWMG_IRS_HEND1B_Pos         15
+#define PWMG_IRS_HEND1B_Msk         (0x01 << PWMG_IRS_HEND1B_Pos)
+#define PWMG_IRS_HEND2A_Pos         16
+#define PWMG_IRS_HEND2A_Msk         (0x01 << PWMG_IRS_HEND2A_Pos)
+#define PWMG_IRS_HEND2B_Pos         17
+#define PWMG_IRS_HEND2B_Msk         (0x01 << PWMG_IRS_HEND2B_Pos)
+#define PWMG_IRS_HEND3A_Pos         18
+#define PWMG_IRS_HEND3A_Msk         (0x01 << PWMG_IRS_HEND3A_Pos)
+#define PWMG_IRS_HEND3B_Pos         19
+#define PWMG_IRS_HEND3B_Msk         (0x01 << PWMG_IRS_HEND3B_Pos)
+#define PWMG_IRS_HEND4A_Pos         20
+#define PWMG_IRS_HEND4A_Msk         (0x01 << PWMG_IRS_HEND4A_Pos)
+#define PWMG_IRS_HEND4B_Pos         21
+#define PWMG_IRS_HEND4B_Msk         (0x01 << PWMG_IRS_HEND4B_Pos)
+#define PWMG_IRS_HEND5A_Pos         22
+#define PWMG_IRS_HEND5A_Msk         (0x01 << PWMG_IRS_HEND5A_Pos)
+#define PWMG_IRS_HEND5B_Pos         23
+#define PWMG_IRS_HEND5B_Msk         (0x01 << PWMG_IRS_HEND5B_Pos)
+#define PWMG_IRS_HALT_Pos           24
+#define PWMG_IRS_HALT_Msk           (0x01 << PWMG_IRS_HALT_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t EN;                       //[0] ENABLE
+
+    __IO uint32_t IE;                       //只有为1时，IF[CHx]在DMA传输结束时才能变为1，否则将一直保持在0
+
+    __IO uint32_t IM;                       //当为1时，即使IF[CHx]为1，dma_int也不会因此变1
+
+    __IO uint32_t IF;                       //写1清零
+
+         uint32_t RESERVED[12];
+
+    struct {
+        __IO uint32_t CR;
+
+        __IO uint32_t AM;                   //Adress Mode
+
+        __IO uint32_t SRC;
+
+        __IO uint32_t SRCSGADDR1;           //只在Scatter Gather模式下使用
+
+        __IO uint32_t SRCSGADDR2;           //只在Scatter Gather模式下使用
+
+        __IO uint32_t SRCSGADDR3;           //只在Scatter Gather模式下使用
+
+        __IO uint32_t SRCSGLEN;             //只在Scatter Gather模式下使用
+
+        __IO uint32_t DST;
+
+        __IO uint32_t DSTSGADDR1;           //只在Scatter Gather模式下使用
+
+        __IO uint32_t DSTSGADDR2;           //只在Scatter Gather模式下使用
+
+        __IO uint32_t DSTSGADDR3;           //只在Scatter Gather模式下使用
+
+        __IO uint32_t DSTSGLEN;             //只在Scatter Gather模式下使用
+
+             uint32_t RESERVED[4];
+    } CH[3];
+} DMA_TypeDef;
+
+
+#define DMA_IE_CH0_Pos              0
+#define DMA_IE_CH0_Msk              (0x01 << DMA_IE_CH0_Pos)
+#define DMA_IE_CH1_Pos              1
+#define DMA_IE_CH1_Msk              (0x01 << DMA_IE_CH1_Pos)
+#define DMA_IE_CH2_Pos              2
+#define DMA_IE_CH2_Msk              (0x01 << DMA_IE_CH2_Pos)
+#define DMA_IE_CH3_Pos              3
+#define DMA_IE_CH3_Msk              (0x01 << DMA_IE_CH3_Pos)
+#define DMA_IE_CH4_Pos              4
+#define DMA_IE_CH4_Msk              (0x01 << DMA_IE_CH4_Pos)
+#define DMA_IE_CH5_Pos              5
+#define DMA_IE_CH5_Msk              (0x01 << DMA_IE_CH5_Pos)
+#define DMA_IE_CH6_Pos              6
+#define DMA_IE_CH6_Msk              (0x01 << DMA_IE_CH6_Pos)
+#define DMA_IE_CH7_Pos              7
+#define DMA_IE_CH7_Msk              (0x01 << DMA_IE_CH7_Pos)
+
+#define DMA_IM_CH0_Pos              0
+#define DMA_IM_CH0_Msk              (0x01 << DMA_IM_CH0_Pos)
+#define DMA_IM_CH1_Pos              1
+#define DMA_IM_CH1_Msk              (0x01 << DMA_IM_CH1_Pos)
+#define DMA_IM_CH2_Pos              2
+#define DMA_IM_CH2_Msk              (0x01 << DMA_IM_CH2_Pos)
+#define DMA_IM_CH3_Pos              3
+#define DMA_IM_CH3_Msk              (0x01 << DMA_IM_CH3_Pos)
+#define DMA_IM_CH4_Pos              4
+#define DMA_IM_CH4_Msk              (0x01 << DMA_IM_CH4_Pos)
+#define DMA_IM_CH5_Pos              5
+#define DMA_IM_CH5_Msk              (0x01 << DMA_IM_CH5_Pos)
+#define DMA_IM_CH6_Pos              6
+#define DMA_IM_CH6_Msk              (0x01 << DMA_IM_CH6_Pos)
+#define DMA_IM_CH7_Pos              7
+#define DMA_IM_CH7_Msk              (0x01 << DMA_IM_CH7_Pos)
+
+#define DMA_IF_CH0_Pos              0
+#define DMA_IF_CH0_Msk              (0x01 << DMA_IF_CH0_Pos)
+#define DMA_IF_CH1_Pos              1
+#define DMA_IF_CH1_Msk              (0x01 << DMA_IF_CH1_Pos)
+#define DMA_IF_CH2_Pos              2
+#define DMA_IF_CH2_Msk              (0x01 << DMA_IF_CH2_Pos)
+#define DMA_IF_CH3_Pos              3
+#define DMA_IF_CH3_Msk              (0x01 << DMA_IF_CH3_Pos)
+#define DMA_IF_CH4_Pos              4
+#define DMA_IF_CH4_Msk              (0x01 << DMA_IF_CH4_Pos)
+#define DMA_IF_CH5_Pos              5
+#define DMA_IF_CH5_Msk              (0x01 << DMA_IF_CH5_Pos)
+#define DMA_IF_CH6_Pos              6
+#define DMA_IF_CH6_Msk              (0x01 << DMA_IF_CH6_Pos)
+#define DMA_IF_CH7_Pos              7
+#define DMA_IF_CH7_Msk              (0x01 << DMA_IF_CH7_Pos)
+
+#define DMA_CR_LEN_Pos              0       //此通道传输总长度，0对应1字节，最大4096字节
+#define DMA_CR_LEN_Msk              (0xFFF << DMA_CR_LEN_Pos)
+#define DMA_CR_RXEN_Pos             16
+#define DMA_CR_RXEN_Msk             (0x01 << DMA_CR_RXEN_Pos)
+#define DMA_CR_TXEN_Pos             17
+#define DMA_CR_TXEN_Msk             (0x01 << DMA_CR_TXEN_Pos)
+#define DMA_CR_AUTORE_Pos           18      //Auto Restart, 通道在传输完成后，是否自动重新启动
+#define DMA_CR_AUTORE_Msk           (0x01 << DMA_CR_AUTORE_Pos)
+
+#define DMA_AM_SRCAM_Pos            0       //Address Mode  0 地址固定    1 地址递增    2 scatter gather模式
+#define DMA_AM_SRCAM_Msk            (0x03 << DMA_AM_SRCAM_Pos)
+#define DMA_AM_DSTAM_Pos            8
+#define DMA_AM_DSTAM_Msk            (0x03 << DMA_AM_DSTAM_Pos)
+#define DMA_AM_BURST_Pos            16
+#define DMA_AM_BURST_Msk            (0x01 << DMA_AM_BURST_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t CR;                       //Control Register
+
+    __O  uint32_t CMD;                      //Command Register
+
+    __I  uint32_t SR;                       //Status Register
+
+    __I  uint32_t IF;                       //Interrupt Flag，读取清零
+
+    __IO uint32_t IE;                       //Interrupt Enable
+
+         uint32_t RESERVED;
+
+    __IO uint32_t BT0;                      //Bit Time Register 0
+
+    __IO uint32_t BT1;                      //Bit Time Register 1
+
+         uint32_t RESERVED2[3];
+
+    __I  uint32_t ALC;                      //Arbitration Lost Capture, 仲裁丢失捕捉
+
+    __I  uint32_t ECC;                      //Error code capture, 错误代码捕捉
+
+    __IO uint32_t EWLIM;                    //Error Warning Limit, 错误报警限制
+
+    __IO uint32_t RXERR;                    //RX错误计数
+
+    __IO uint32_t TXERR;                    //TX错误计数
+
+    union {
+        struct {                            //在复位时可读写，正常工作模式下不可访问
+            __IO uint32_t ACR[4];           //Acceptance Check Register, 验收寄存器
+
+            __IO uint32_t AMR[4];           //Acceptance Mask Register, 验收屏蔽寄存器；对应位写0，ID必须和验收寄存器匹配
+
+                 uint32_t RESERVED[5];
+        } FILTER;
+
+        struct {                            //在正常工作模式下可读写，复位时不可访问
+            __IO uint32_t INFO;
+
+            __IO uint32_t DATA[12];
+        } FRAME;
+    };
+
+    __I  uint32_t RMCNT;                    //Receive Message Count
+
+         uint32_t RESERVED3[66];
+
+    struct {                                //TXFRAME的读接口
+        __I  uint32_t INFO;
+
+        __I  uint32_t DATA[12];
+    } TXFRAME_R;
+} CAN_TypeDef;
+
+
+#define CAN_CR_RST_Pos              0
+#define CAN_CR_RST_Msk              (0x01 << CAN_CR_RST_Pos)
+#define CAN_CR_LOM_Pos              1       //Listen Only Mode
+#define CAN_CR_LOM_Msk              (0x01 << CAN_CR_LOM_Pos)
+#define CAN_CR_STM_Pos              2       //Self Test Mode, 此模式下即使没有应答，CAN控制器也可以成功发送
+#define CAN_CR_STM_Msk              (0x01 << CAN_CR_STM_Pos)
+#define CAN_CR_AFM_Pos              3       //Acceptance Filter Mode, 1 单个验收滤波器（32位）   0 两个验收滤波器（16位）
+#define CAN_CR_AFM_Msk              (0x01 << CAN_CR_AFM_Pos)
+#define CAN_CR_SLEEP_Pos            4       //写1进入睡眠模式，有总线活动或中断时唤醒并自动清零此位
+#define CAN_CR_SLEEP_Msk            (0x01 << CAN_CR_SLEEP_Pos)
+
+#define CAN_CMD_TXREQ_Pos           0       //Transmission Request
+#define CAN_CMD_TXREQ_Msk           (0x01 << CAN_CMD_TXREQ_Pos)
+#define CAN_CMD_ABTTX_Pos           1       //Abort Transmission
+#define CAN_CMD_ABTTX_Msk           (0x01 << CAN_CMD_ABTTX_Pos)
+#define CAN_CMD_RRB_Pos             2       //Release Receive Buffer
+#define CAN_CMD_RRB_Msk             (0x01 << CAN_CMD_RRB_Pos)
+#define CAN_CMD_CLROV_Pos           3       //Clear Data Overrun
+#define CAN_CMD_CLROV_Msk           (0x01 << CAN_CMD_CLROV_Pos)
+#define CAN_CMD_SRR_Pos             4       //Self Reception Request
+#define CAN_CMD_SRR_Msk             (0x01 << CAN_CMD_SRR_Pos)
+
+#define CAN_SR_RXDA_Pos             0       //Receive Data Available，接收FIFO中有完整消息可以读取
+#define CAN_SR_RXDA_Msk             (0x01 << CAN_SR_RXDA_Pos)
+#define CAN_SR_RXOV_Pos             1       //Receive FIFO Overrun，新接收的信息由于接收FIFO已满而丢掉
+#define CAN_SR_RXOV_Msk             (0x01 << CAN_SR_RXOV_Pos)
+#define CAN_SR_TXBR_Pos             2       //Transmit Buffer Release，0 正在处理前面的发送，现在不能写新的消息    1 可以写入新的消息发送
+#define CAN_SR_TXBR_Msk             (0x01 << CAN_SR_TXBR_Pos)
+#define CAN_SR_TXOK_Pos             3       //Transmit OK，successfully completed
+#define CAN_SR_TXOK_Msk             (0x01 << CAN_SR_TXOK_Pos)
+#define CAN_SR_RXBUSY_Pos           4       //Receive Busy，正在接收
+#define CAN_SR_RXBUSY_Msk           (0x01 << CAN_SR_RXBUSY_Pos)
+#define CAN_SR_TXBUSY_Pos           5       //Transmit Busy，正在发送
+#define CAN_SR_TXBUSY_Msk           (0x01 << CAN_SR_TXBUSY_Pos)
+#define CAN_SR_ERRWARN_Pos          6       //1 至少一个错误计数器达到 Warning Limit
+#define CAN_SR_ERRWARN_Msk          (0x01 << CAN_SR_ERRWARN_Pos)
+#define CAN_SR_BUSOFF_Pos           7       //1 CAN 控制器处于总线关闭状态，没有参与到总线活动
+#define CAN_SR_BUSOFF_Msk           (0x01 << CAN_SR_BUSOFF_Pos)
+
+#define CAN_IF_RXDA_Pos             0       //IF.RXDA = SR.RXDA & IE.RXDA
+#define CAN_IF_RXDA_Msk             (0x01 << CAN_IF_RXDA_Pos)
+#define CAN_IF_TXBR_Pos             1       //当IE.TXBR=1时，SR.TXBR由0变成1将置位此位
+#define CAN_IF_TXBR_Msk             (0x01 << CAN_IF_TXBR_Pos)
+#define CAN_IF_ERRWARN_Pos          2       //当IE.ERRWARN=1时，SR.ERRWARN或SR.BUSOFF 0-to-1 或 1-to-0将置位此位
+#define CAN_IF_ERRWARN_Msk          (0x01 << CAN_IF_ERRWARN_Pos)
+#define CAN_IF_RXOV_Pos             3       //IF.RXOV = SR.RXOV & IE.RXOV
+#define CAN_IF_RXOV_Msk             (0x01 << CAN_IF_RXOV_Pos)
+#define CAN_IF_WKUP_Pos             4       //当IE.WKUP=1时，在睡眠模式下的CAN控制器检测到总线活动时硬件置位
+#define CAN_IF_WKUP_Msk             (0x01 << CAN_IF_WKUP_Pos)
+#define CAN_IF_ERRPASS_Pos          5       //
+#define CAN_IF_ERRPASS_Msk          (0x01 << CAN_IF_ERRPASS_Pos)
+#define CAN_IF_ARBLOST_Pos          6       //Arbitration Lost，当IE.ARBLOST=1时，CAN控制器丢失仲裁变成接收方时硬件置位
+#define CAN_IF_ARBLOST_Msk          (0x01 << CAN_IF_ARBLOST_Pos)
+#define CAN_IF_BUSERR_Pos           7       //当IE.BUSERR=1时，CAN控制器检测到总线错误时硬件置位
+#define CAN_IF_BUSERR_Msk           (0x01 << CAN_IF_BUSERR_Pos)
+
+#define CAN_IE_RXDA_Pos             0
+#define CAN_IE_RXDA_Msk             (0x01 << CAN_IE_RXDA_Pos)
+#define CAN_IE_TXBR_Pos             1
+#define CAN_IE_TXBR_Msk             (0x01 << CAN_IE_TXBR_Pos)
+#define CAN_IE_ERRWARN_Pos          2
+#define CAN_IE_ERRWARN_Msk          (0x01 << CAN_IE_ERRWARN_Pos)
+#define CAN_IE_RXOV_Pos             3
+#define CAN_IE_RXOV_Msk             (0x01 << CAN_IE_RXOV_Pos)
+#define CAN_IE_WKUP_Pos             4
+#define CAN_IE_WKUP_Msk             (0x01 << CAN_IE_WKUP_Pos)
+#define CAN_IE_ERRPASS_Pos          5
+#define CAN_IE_ERRPASS_Msk          (0x01 << CAN_IE_ERRPASS_Pos)
+#define CAN_IE_ARBLOST_Pos          6
+#define CAN_IE_ARBLOST_Msk          (0x01 << CAN_IE_ARBLOST_Pos)
+#define CAN_IE_BUSERR_Pos           7
+#define CAN_IE_BUSERR_Msk           (0x01 << CAN_IE_BUSERR_Pos)
+
+#define CAN_BT0_BRP_Pos             0       //Baud Rate Prescaler，CAN时间单位=2*Tsysclk*(BRP+1)
+#define CAN_BT0_BRP_Msk             (0x3F << CAN_BT0_BRP_Pos)
+#define CAN_BT0_SJW_Pos             6       //Synchronization Jump Width
+#define CAN_BT0_SJW_Msk             (0x03 << CAN_BT0_SJW_Pos)
+
+#define CAN_BT1_TSEG1_Pos           0       //t_tseg1 = CAN时间单位 * (TSEG1+1)
+#define CAN_BT1_TSEG1_Msk           (0x0F << CAN_BT1_TSEG1_Pos)
+#define CAN_BT1_TSEG2_Pos           4       //t_tseg2 = CAN时间单位 * (TSEG2+1)
+#define CAN_BT1_TSEG2_Msk           (0x07 << CAN_BT1_TSEG2_Pos)
+#define CAN_BT1_SAM_Pos             7       //采样次数  0: sampled once  1: sampled three times
+#define CAN_BT1_SAM_Msk             (0x01 << CAN_BT1_SAM_Pos)
+
+#define CAN_ECC_SEGCODE_Pos         0       //Segment Code
+#define CAN_ECC_SEGCODE_Msk         (0x1F << CAN_ECC_SEGCODE_Pos)
+#define CAN_ECC_DIR_Pos             5       //0 error occurred during transmission   1 during reception
+#define CAN_ECC_DIR_Msk             (0x01 << CAN_ECC_DIR_Pos)
+#define CAN_ECC_ERRCODE_Pos         6       //Error Code：0 Bit error   1 Form error   2 Stuff error   3 other error
+#define CAN_ECC_ERRCODE_Msk         (0x03 << CAN_ECC_ERRCODE_Pos)
+
+#define CAN_INFO_DLC_Pos            0       //Data Length Control
+#define CAN_INFO_DLC_Msk            (0x0F << CAN_INFO_DLC_Pos)
+#define CAN_INFO_RTR_Pos            6       //Remote Frame，1 远程帧    0 数据帧
+#define CAN_INFO_RTR_Msk            (0x01 << CAN_INFO_RTR_Pos)
+#define CAN_INFO_FF_Pos             7       //Frame Format，0 标准帧格式    1 扩展帧格式
+#define CAN_INFO_FF_Msk             (0x01 << CAN_INFO_FF_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t IE;                       //[0] 为0的时候，IF[0]维持为0
+
+    __IO uint32_t IF;                       //[0] 当完成指定长度的数据传输时置1，写1清零
+
+    __IO uint32_t IM;                       //[0] 当该寄存器为1时，LCDC的中断不会输出给系统的中断控制寄存器
+
+    __IO uint32_t START;
+
+    __IO uint32_t SRCADDR;                  //数据源地址寄存器，必须字对齐（即地址的低2位必须是0）
+
+    __IO uint32_t CR0;
+
+    __IO uint32_t CR1;
+
+    __IO uint32_t PRECMDV;                  //在MPU接口中，发送数据前，RS拉低的那一拍，数据总线上的值
+} LCD_TypeDef;
+
+
+#define LCD_START_GO_Pos            1       //写1开始传输数据，数据传输结束后自动清零
+#define LCD_START_GO_Msk            (0x01 << LCD_START_GO_Pos)
+#define LCD_START_BURST_Pos         2
+#define LCD_START_BURST_Msk         (0x01 << LCD_START_BURST_Pos)
+
+#define LCD_CR0_VPIX_Pos            0       //当portrait为0时，表示垂直方向的像素个数，0表示1个，最大为767
+                                            //当portrait为1时，表示水平方向的像素个数，0表示1个，最大为767
+#define LCD_CR0_VPIX_Msk            (0x3FF << LCD_CR0_VPIX_Pos)
+#define LCD_CR0_HPIX_Pos            10      //当portrait为0时，表示水平方向的像素个数，0表示1个，最大为1023
+                                            //当portrait为1时，表示垂直方向的像素个数，0表示1个，最大为1023
+#define LCD_CR0_HPIX_Msk            (0x3FF << LCD_CR0_HPIX_Pos)
+#define LCD_CR0_DCLK_Pos            20      //0 DOTCLK一直翻转    1 DOTCLK在空闲时停在1
+#define LCD_CR0_DCLK_Msk            (0x01 << LCD_CR0_DCLK_Pos)
+#define LCD_CR0_HLOW_Pos            21      //输出HSYNC低电平持续多少个DOTCLK周期，0表示1个周期
+#define LCD_CR0_HLOW_Msk            (0x03 << LCD_CR0_HLOW_Pos)
+
+#define LCD_CR1_VFP_Pos             1
+#define LCD_CR1_VFP_Msk             (0x07 << LCD_CR1_VFP_Pos)
+#define LCD_CR1_VBP_Pos             4
+#define LCD_CR1_VBP_Msk             (0x1F << LCD_CR1_VBP_Pos)
+#define LCD_CR1_HFP_Pos             9
+#define LCD_CR1_HFP_Msk             (0x1F << LCD_CR1_HFP_Pos)
+#define LCD_CR1_HBP_Pos             14
+#define LCD_CR1_HBP_Msk             (0x7F << LCD_CR1_HBP_Pos)
+#define LCD_CR1_DCLKDIV_Pos         21      //DOTCLK相对于模块时钟的分频比，0表示2分频，1表示4分频 ...
+#define LCD_CR1_DCLKDIV_Msk         (0x1F << LCD_CR1_DCLKDIV_Pos)
+#define LCD_CR1_DCLKINV_Pos         26      //1 输出DOTCLK反向，应用于用DOTCLK下降沿采样数据的屏
+#define LCD_CR1_DCLKINV_Msk         (0x01 << LCD_CR1_DCLKINV_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t DMA_MEM_ADDR;
+
+    __IO uint32_t BLK;                      //Block Size and Count
+
+    __IO uint32_t ARG;                      //Argument
+
+    __IO uint32_t CMD;                      //Command
+
+    __IO uint32_t RESP[4];                  //Response
+
+    __IO uint32_t DATA;
+
+    __IO uint32_t STAT;
+
+    __IO uint32_t CR1;
+
+    __IO uint32_t CR2;
+
+    __IO uint32_t IF;
+
+    __IO uint32_t IM;                       //Interrupt Mask (Interrupt Flag Enable)
+
+    __IO uint32_t IE;                       //Interrupt Enalbe
+
+    __IO uint32_t CMD12ERR;
+} SDIO_TypeDef;
+
+
+#define SDIO_BLK_SIZE_Pos           0       //0x200 512字节   0x400 1024字节   0x800 2048字节
+#define SDIO_BLK_SIZE_Msk           (0xFFF << SDIO_BLK_SIZE_Pos)
+#define SDIO_BLK_COUNT_Pos          16      //0 Stop Transfer    1 1块    2 2块    ... ...
+#define SDIO_BLK_COUNT_Msk          (0xFFF << SDIO_BLK_COUNT_Pos)
+
+#define SDIO_CMD_DMAEN_Pos          0
+#define SDIO_CMD_DMAEN_Msk          (0x01 << SDIO_CMD_DMAEN_Pos)
+#define SDIO_CMD_BLKCNTEN_Pos       1
+#define SDIO_CMD_BLKCNTEN_Msk       (0x01 << SDIO_CMD_BLKCNTEN_Pos)
+#define SDIO_CMD_AUTOCMD12_Pos      2
+#define SDIO_CMD_AUTOCMD12_Msk      (0x01 << SDIO_CMD_AUTOCMD12_Pos)
+#define SDIO_CMD_DIRREAD_Pos        4       //0 Write, Host to Card    1 Read, Card to Host
+#define SDIO_CMD_DIRREAD_Msk        (0x01 << SDIO_CMD_DIRREAD_Pos)
+#define SDIO_CMD_MULTBLK_Pos        5       //0 Single Block    1  Multiple Block
+#define SDIO_CMD_MULTBLK_Msk        (0x01 << SDIO_CMD_MULTBLK_Pos)
+#define SDIO_CMD_RESPTYPE_Pos       16       //响应类型，0 无响应    1 136位响应    2 48位响应    3 48位响应，Busy after response
+#define SDIO_CMD_RESPTYPE_Msk       (0x03 << SDIO_CMD_RESPTYPE_Pos)
+#define SDIO_CMD_CRCCHECK_Pos       19       //Command CRC Check Enable
+#define SDIO_CMD_CRCCHECK_Msk       (0x01 << SDIO_CMD_CRCCHECK_Pos)
+#define SDIO_CMD_IDXCHECK_Pos       20       //Command Index Check Enable
+#define SDIO_CMD_IDXCHECK_Msk       (0x01 << SDIO_CMD_IDXCHECK_Pos)
+#define SDIO_CMD_HAVEDATA_Pos       21       //0 No Data Present    1 Data Present
+#define SDIO_CMD_HAVEDATA_Msk       (0x01 << SDIO_CMD_HAVEDATA_Pos)
+#define SDIO_CMD_CMDTYPE_Pos        22       //0 NORMAL   1 SUSPEND    2 RESUME    3 ABORT
+#define SDIO_CMD_CMDTYPE_Msk        (0x03 << SDIO_CMD_CMDTYPE_Pos)
+#define SDIO_CMD_CMDINDX_Pos        24       //Command Index，CMD0-63、ACMD0-63
+#define SDIO_CMD_CMDINDX_Msk        (0x3F << SDIO_CMD_CMDINDX_Pos)
+
+#define SDIO_CR1_4BIT_Pos           1       //1 4 bit mode    0 1 bit mode
+#define SDIO_CR1_4BIT_Msk           (0x01 << SDIO_CR1_4BIT_Pos)
+#define SDIO_CR1_8BIT_Pos           5       //1 8 bit mode is selected    0 8 bit mode is not selected
+#define SDIO_CR1_8BIT_Msk           (0x01 << SDIO_CR1_8BIT_Pos)
+#define SDIO_CR1_CDBIT_Pos          6       //0 No Card    1 Card Inserted
+#define SDIO_CR1_CDBIT_Msk          (0x01 << SDIO_CR1_CDBIT_Pos)
+#define SDIO_CR1_CDSRC_Pos          7       //Card Detect Source, 1 CR1.CDBIT位    0 SD_Detect引脚
+#define SDIO_CR1_CDSRC_Msk          (0x01 << SDIO_CR1_CDSRC_Pos)
+#define SDIO_CR1_PWRON_Pos          8       //1 Power on    0 Power off
+#define SDIO_CR1_PWRON_Msk          (0x01 << SDIO_CR1_PWRON_Pos)
+#define SDIO_CR1_VOLT_Pos           9       //7 3.3V    6 3.0V    5 1.8V
+#define SDIO_CR1_VOLT_Msk           (0x07 << SDIO_CR1_VOLT_Pos)
+
+#define SDIO_CR2_CLKEN_Pos          0       //Internal Clock Enable
+#define SDIO_CR2_CLKEN_Msk          (0x01 << SDIO_CR2_CLKEN_Pos)
+#define SDIO_CR2_CLKRDY_Pos         1       //Internal Clock Stable/Ready
+#define SDIO_CR2_CLKRDY_Msk         (0x01 << SDIO_CR2_CLKRDY_Pos)
+#define SDIO_CR2_SDCLKEN_Pos        2       //SDCLK Enable
+#define SDIO_CR2_SDCLKEN_Msk        (0x01 << SDIO_CR2_SDCLKEN_Pos)
+#define SDIO_CR2_SDCLKDIV_Pos       8       //SDCLK Frequency Div, 0x00 不分频    0x01 2分频    0x02 4分频    0x04 8分频    0x08    16分频    ...    0x80 256分频
+#define SDIO_CR2_SDCLKDIV_Msk       (0xFF << SDIO_CR2_SDCLKDIV_Pos)
+#define SDIO_CR2_TIMEOUT_Pos        16      //0 TMCLK*2^13   1 TMCLK*2^14   ...   14 TMCLK*2^27
+#define SDIO_CR2_TIMEOUT_Msk        (0x0F << SDIO_CR2_TIMEOUT_Pos)
+#define SDIO_CR2_RSTALL_Pos         24      //Software Reset for All
+#define SDIO_CR2_RSTALL_Msk         (0x01 << SDIO_CR2_RSTALL_Pos)
+#define SDIO_CR2_RSTCMD_Pos         25      //Software Reset for CMD Line
+#define SDIO_CR2_RSTCMD_Msk         (0x01 << SDIO_CR2_RSTCMD_Pos)
+#define SDIO_CR2_RSTDAT_Pos         26      //Software Reset for DAT Line
+#define SDIO_CR2_RSTDAT_Msk         (0x01 << SDIO_CR2_RSTDAT_Pos)
+
+#define SDIO_IF_CMDDONE_Pos         0
+#define SDIO_IF_CMDDONE_Msk         (0x01 << SDIO_IF_CMDDONE_Pos)
+#define SDIO_IF_TRXDONE_Pos         1
+#define SDIO_IF_TRXDONE_Msk         (0x01 << SDIO_IF_TRXDONE_Pos)
+#define SDIO_IF_BLKGAP_Pos          2
+#define SDIO_IF_BLKGAP_Msk          (0x01 << SDIO_IF_BLKGAP_Pos)
+#define SDIO_IF_DMADONE_Pos         3
+#define SDIO_IF_DMADONE_Msk         (0x01 << SDIO_IF_DMADONE_Pos)
+#define SDIO_IF_BUFWRRDY_Pos        4
+#define SDIO_IF_BUFWRRDY_Msk        (0x01 << SDIO_IF_BUFWRRDY_Pos)
+#define SDIO_IF_BUFRDRDY_Pos        5
+#define SDIO_IF_BUFRDRDY_Msk        (0x01 << SDIO_IF_BUFRDRDY_Pos)
+#define SDIO_IF_CARDINSR_Pos        6
+#define SDIO_IF_CARDINSR_Msk        (0x01 << SDIO_IF_CARDINSR_Pos)
+#define SDIO_IF_CARDRMOV_Pos        7
+#define SDIO_IF_CARDRMOV_Msk        (0x01 << SDIO_IF_CARDRMOV_Pos)
+#define SDIO_IF_CARD_Pos            8
+#define SDIO_IF_CARD_Msk            (0x01 << SDIO_IF_CARD_Pos)
+#define SDIO_IF_ERROR_Pos           15
+#define SDIO_IF_ERROR_Msk           (0x01 << SDIO_IF_ERROR_Pos)
+#define SDIO_IF_CMDTIMEOUT_Pos      16
+#define SDIO_IF_CMDTIMEOUT_Msk      (0x01 << SDIO_IF_CMDTIMEOUT_Pos)
+#define SDIO_IF_CMDCRCERR_Pos       17
+#define SDIO_IF_CMDCRCERR_Msk       (0x01 << SDIO_IF_CMDCRCERR_Pos)
+#define SDIO_IF_CMDENDERR_Pos       18
+#define SDIO_IF_CMDENDERR_Msk       (0x01 << SDIO_IF_CMDENDCERR_Pos)
+#define SDIO_IF_CMDIDXERR_Pos       19
+#define SDIO_IF_CMDIDXERR_Msk       (0x01 << SDIO_IF_CMDIDXCERR_Pos)
+#define SDIO_IF_DATTIMEOUT_Pos      20
+#define SDIO_IF_DATTIMEOUT_Msk      (0x01 << SDIO_IF_DATTIMEOUT_Pos)
+#define SDIO_IF_DATCRCERR_Pos       21
+#define SDIO_IF_DATCRCERR_Msk       (0x01 << SDIO_IF_DATCRCERR_Pos)
+#define SDIO_IF_DATENDERR_Pos       22
+#define SDIO_IF_DATENDERR_Msk       (0x01 << SDIO_IF_DATENDCERR_Pos)
+#define SDIO_IF_CURLIMERR_Pos       23
+#define SDIO_IF_CURLIMERR_Msk       (0x01 << SDIO_IF_CURLIMERR_Pos)
+#define SDIO_IF_CMD12ERR_Pos        24
+#define SDIO_IF_CMD12ERR_Msk        (0x01 << SDIO_IF_CMD12ERR_Pos)
+#define SDIO_IF_DMAERR_Pos          25
+#define SDIO_IF_DMAERR_Msk          (0x01 << SDIO_IF_DMAERR_Pos)
+#define SDIO_IF_RESPERR_Pos         28
+#define SDIO_IF_RESPERR_Msk         (0x01 << SDIO_IF_RESPERR_Pos)
+
+#define SDIO_IE_CMDDONE_Pos         0       //Command Complete Status Enable
+#define SDIO_IE_CMDDONE_Msk         (0x01 << SDIO_IE_CMDDONE_Pos)
+#define SDIO_IE_TRXDONE_Pos         1       //Transfer Complete Status Enable
+#define SDIO_IE_TRXDONE_Msk         (0x01 << SDIO_IE_TRXDONE_Pos)
+#define SDIO_IE_BLKGAP_Pos          2       //Block Gap Event Status Enable
+#define SDIO_IE_BLKGAP_Msk          (0x01 << SDIO_IE_BLKGAP_Pos)
+#define SDIO_IE_DMADONE_Pos         3       //DMA Interrupt Status Enable
+#define SDIO_IE_DMADONE_Msk         (0x01 << SDIO_IE_DMADONE_Pos)
+#define SDIO_IE_BUFWRRDY_Pos        4       //Buffer Write Ready Status Enable
+#define SDIO_IE_BUFWRRDY_Msk        (0x01 << SDIO_IE_BUFWRRDY_Pos)
+#define SDIO_IE_BUFRDRDY_Pos        5       //Buffer Read Ready Status Enable
+#define SDIO_IE_BUFRDRDY_Msk        (0x01 << SDIO_IE_BUFRDRDY_Pos)
+#define SDIO_IE_CARDINSR_Pos        6       //Card Insertion Status Enable
+#define SDIO_IE_CARDINSR_Msk        (0x01 << SDIO_IE_CARDINSR_Pos)
+#define SDIO_IE_CARDRMOV_Pos        7       //Card Removal Status Enable
+#define SDIO_IE_CARDRMOV_Msk        (0x01 << SDIO_IE_CARDRMOV_Pos)
+#define SDIO_IE_CARD_Pos            8
+#define SDIO_IE_CARD_Msk            (0x01 << SDIO_IE_CARD_Pos)
+#define SDIO_IE_CMDTIMEOUT_Pos      16      //Command Timeout Error Status Enable
+#define SDIO_IE_CMDTIMEOUT_Msk      (0x01 << SDIO_IE_CMDTIMEOUT_Pos)
+#define SDIO_IE_CMDCRCERR_Pos       17      //Command CRC Error Status Enable
+#define SDIO_IE_CMDCRCERR_Msk       (0x01 << SDIO_IE_CMDCRCERR_Pos)
+#define SDIO_IE_CMDENDERR_Pos       18      //Command End Bit Error Status Enable
+#define SDIO_IE_CMDENDERR_Msk       (0x01 << SDIO_IE_CMDENDCERR_Pos)
+#define SDIO_IE_CMDIDXERR_Pos       19      //Command Index Error Status Enable
+#define SDIO_IE_CMDIDXERR_Msk       (0x01 << SDIO_IE_CMDIDXCERR_Pos)
+#define SDIO_IE_DATTIMEOUT_Pos      20      //Data Timeout Error Status Enable
+#define SDIO_IE_DATTIMEOUT_Msk      (0x01 << SDIO_IE_DATTIMEOUT_Pos)
+#define SDIO_IE_DATCRCERR_Pos       21      //Data CRC Error Status Enable
+#define SDIO_IE_DATCRCERR_Msk       (0x01 << SDIO_IE_DATCRCERR_Pos)
+#define SDIO_IE_DATENDERR_Pos       22      //Data End Bit Error Status Enable
+#define SDIO_IE_DATENDERR_Msk       (0x01 << SDIO_IE_DATENDCERR_Pos)
+#define SDIO_IE_CURLIMERR_Pos       23      //Current Limit Error Status Enable
+#define SDIO_IE_CURLIMERR_Msk       (0x01 << SDIO_IE_CURLIMERR_Pos)
+#define SDIO_IE_CMD12ERR_Pos        24      //Auto CMD12 Error Status Enable
+#define SDIO_IE_CMD12ERR_Msk        (0x01 << SDIO_IE_CMD12ERR_Pos)
+#define SDIO_IE_DMAERR_Pos          25      //ADMA Error Status Enable
+#define SDIO_IE_DMAERR_Msk          (0x01 << SDIO_IE_DMAERR_Pos)
+#define SDIO_IE_RESPERR_Pos         28      //Target Response Error Status Enable
+#define SDIO_IE_RESPERR_Msk         (0x01 << SDIO_IE_RESPERR_Pos)
+
+#define SDIO_IM_CMDDONE_Pos         0
+#define SDIO_IM_CMDDONE_Msk         (0x01 << SDIO_IM_CMDDONE_Pos)
+#define SDIO_IM_TRXDONE_Pos         1
+#define SDIO_IM_TRXDONE_Msk         (0x01 << SDIO_IM_TRXDONE_Pos)
+#define SDIO_IM_BLKGAP_Pos          2
+#define SDIO_IM_BLKGAP_Msk          (0x01 << SDIO_IM_BLKGAP_Pos)
+#define SDIO_IM_DMADONE_Pos         3
+#define SDIO_IM_DMADONE_Msk         (0x01 << SDIO_IM_DMADONE_Pos)
+#define SDIO_IM_BUFWRRDY_Pos        4
+#define SDIO_IM_BUFWRRDY_Msk        (0x01 << SDIO_IM_BUFWRRDY_Pos)
+#define SDIO_IM_BUFRDRDY_Pos        5
+#define SDIO_IM_BUFRDRDY_Msk        (0x01 << SDIO_IM_BUFRDRDY_Pos)
+#define SDIO_IM_CARDINSR_Pos        6
+#define SDIO_IM_CARDINSR_Msk        (0x01 << SDIO_IM_CARDINSR_Pos)
+#define SDIO_IM_CARDRMOV_Pos        7
+#define SDIO_IM_CARDRMOV_Msk        (0x01 << SDIO_IM_CARDRMOV_Pos)
+#define SDIO_IM_CARD_Pos            8
+#define SDIO_IM_CARD_Msk            (0x01 << SDIO_IM_CARD_Pos)
+#define SDIO_IM_CMDTIMEOUT_Pos      16
+#define SDIO_IM_CMDTIMEOUT_Msk      (0x01 << SDIO_IM_CMDTIMEOUT_Pos)
+#define SDIO_IM_CMDCRCERR_Pos       17
+#define SDIO_IM_CMDCRCERR_Msk       (0x01 << SDIO_IM_CMDCRCERR_Pos)
+#define SDIO_IM_CMDENDERR_Pos       18
+#define SDIO_IM_CMDENDERR_Msk       (0x01 << SDIO_IM_CMDENDCERR_Pos)
+#define SDIO_IM_CMDIDXERR_Pos       19
+#define SDIO_IM_CMDIDXERR_Msk       (0x01 << SDIO_IM_CMDIDXCERR_Pos)
+#define SDIO_IM_DATTIMEOUT_Pos      20
+#define SDIO_IM_DATTIMEOUT_Msk      (0x01 << SDIO_IM_DATTIMEOUT_Pos)
+#define SDIO_IM_DATCRCERR_Pos       21
+#define SDIO_IM_DATCRCERR_Msk       (0x01 << SDIO_IM_DATCRCERR_Pos)
+#define SDIO_IM_DATENDERR_Pos       22
+#define SDIO_IM_DATENDERR_Msk       (0x01 << SDIO_IM_DATENDCERR_Pos)
+#define SDIO_IM_CURLIMERR_Pos       23
+#define SDIO_IM_CURLIMERR_Msk       (0x01 << SDIO_IM_CURLIMERR_Pos)
+#define SDIO_IM_CMD12ERR_Pos        24
+#define SDIO_IM_CMD12ERR_Msk        (0x01 << SDIO_IM_CMD12ERR_Pos)
+#define SDIO_IM_DMAERR_Pos          25
+#define SDIO_IM_DMAERR_Msk          (0x01 << SDIO_IM_DMAERR_Pos)
+#define SDIO_IM_RESPERR_Pos         28
+#define SDIO_IM_RESPERR_Msk         (0x01 << SDIO_IM_RESPERR_Pos)
+
+#define SDIO_CMD12ERR_NE_Pos        0       //Auto CMD12 not Executed
+#define SDIO_CMD12ERR_NE_Msk        (0x01 << SDIO_CMD12ERR_NE_Pos)
+#define SDIO_CMD12ERR_TO_Pos        1       //Auto CMD12 Timeout Error
+#define SDIO_CMD12ERR_TO_Msk        (0x01 << SDIO_CMD12ERR_TO_Pos)
+#define SDIO_CMD12ERR_CRC_Pos       2       //Auto CMD12 CRC Error
+#define SDIO_CMD12ERR_CRC_Msk       (0x01 << SDIO_CMD12ERR_CRC_Pos)
+#define SDIO_CMD12ERR_END_Pos       3       //Auto CMD12 End Bit Error
+#define SDIO_CMD12ERR_END_Msk       (0x01 << SDIO_CMD12ERR_END_Pos)
+#define SDIO_CMD12ERR_INDEX_Pos     4       //Auto CMD12 Index Error
+#define SDIO_CMD12ERR_INDEX_Msk     (0x01 << SDIO_CMD12ERR_INDEX_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t DATA;
+    __IO uint32_t ADDR;
+    __IO uint32_t FLASH_ERASE;
+    __IO uint32_t CACHE;
+    __IO uint32_t CFG0;
+    __IO uint32_t CFG1;
+    __IO uint32_t CFG2;
+    __IO uint32_t CFG3;
+    __IO uint32_t STAT;
+} FLASH_Typedef;
+
+
+#define FLASH_ERASE_REQ_Pos         31
+#define FLASH_ERASE_REQ_Msk         (0x01u<< FLASH_ERASE_REQ_Pos)
+
+#define FLASH_CACHE_PROG_Pos        2
+#define FLASH_CACHE_PROG_Msk        (0x01 << FLASH_CACHE_PROG_Pos)
+#define FLASH_CACHE_CLEAR_Pos       3
+#define FLASH_CACHE_CLEAR_Msk       (0x01 << FLASH_CACHE_CLEAR_Pos)
+
+#define FLASH_STAT_ERASE_GOING_Pos  0
+#define FLASH_STAT_ERASE_GOING_Msk  (0X01 << FLASH_STAT_ERASE_GOING_Pos)
+#define FLASH_STAT_PROG_GOING_Pos   1
+#define FLASH_STAT_PROG_GOING_Msk   (0x01 << FLASH_STAT_PROG_GOING_Pos)
+#define FALSH_STAT_FIFO_EMPTY_Pos   3
+#define FLASH_STAT_FIFO_EMPTY_Msk   (0x01 << FALSH_STAT_FIFO_EMPTY_Pos)
+#define FALSH_STAT_FIFO_FULL_Pos    4
+#define FLASH_STAT_FIFO_FULL_Msk    (0x01 << FALSH_STAT_FIFO_FULL_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t CR;
+} SRAMC_TypeDef;
+
+
+#define SRAMC_CR_RWTIME_Pos         0       //读写操作持续多少个时钟周期。0表示1个时钟周期。最小设置为4
+#define SRAMC_CR_RWTIME_Msk         (0x0F << SRAMC_CR_RWTIME_Pos)
+#define SRAMC_CR_BYTEIF_Pos         4       //外部SRAM数据宽度，0 16位    1 8位
+#define SRAMC_CR_BYTEIF_Msk         (0x01 << SRAMC_CR_BYTEIF_Pos)
+#define SRAMC_CR_HBLBDIS_Pos        5       //1 ADDR[23:22]为地址线   0 ADDR[23]为高字节使能，ADDR[22]为低字节使能
+#define SRAMC_CR_HBLBDIS_Msk        (0x01 << SRAMC_CR_HBLBDIS_Pos)
+
+
+
+typedef struct {
+    __IO uint32_t CR0;
+
+    __IO uint32_t CR1;
+
+    __IO uint32_t REFRESH;
+
+    __IO uint32_t NOPNUM;                   //[15:0] 初始化完成后，在正常操作之前，发送多少个NOP命令
+
+    __IO uint32_t LATCH;
+
+    __IO uint32_t REFDONE;                  //[0] Frefresh Done，上电初始化完成
+} SDRAMC_TypeDef;
+
+
+#define SDRAMC_CR0_BURSTLEN_Pos     0       //必须取2，表示Burst Length为4
+#define SDRAMC_CR0_BURSTLEN_Msk     (0x07 << SDRAMC_CR0_BURSTLEN_Pos)
+#define SDRAMC_CR0_CASDELAY_Pos     4       //CAS Latency， 2 2    3 3
+#define SDRAMC_CR0_CASDELAY_Msk     (0x07 << SDRAMC_CR0_CASDELAY_Pos)
+
+#define SDRAMC_CR1_TRP_Pos          0
+#define SDRAMC_CR1_TRP_Msk          (0x07 << SDRAMC_CR1_TRP_Pos)
+#define SDRAMC_CR1_TRCD_Pos         3
+#define SDRAMC_CR1_TRCD_Msk         (0x07 << SDRAMC_CR1_TRCD_Pos)
+#define SDRAMC_CR1_TRC_Pos          6
+#define SDRAMC_CR1_TRC_Msk          (0x0F << SDRAMC_CR1_TRC_Pos)
+#define SDRAMC_CR1_TRAS_Pos         10
+#define SDRAMC_CR1_TRAS_Msk         (0x07 << SDRAMC_CR1_TRAS_Pos)
+#define SDRAMC_CR1_TRRD_Pos         13
+#define SDRAMC_CR1_TRRD_Msk         (0x03 << SDRAMC_CR1_TRRD_Pos)
+#define SDRAMC_CR1_TMRD_Pos         15
+#define SDRAMC_CR1_TMRD_Msk         (0x07 << SDRAMC_CR1_TMRD_Pos)
+#define SDRAMC_CR1_32BIT_Pos        18      //SDRAMC的接口数据位宽，1 32bit    0 16bit
+#define SDRAMC_CR1_32BIT_Msk        (0x01 << SDRAMC_CR1_32BIT_Pos)
+#define SDRAMC_CR1_BANK_Pos         19      //SDRAM每个颗粒有几个bank，0 2 banks    1 4 banks
+#define SDRAMC_CR1_BANK_Msk         (0x01 << SDRAMC_CR1_BANK_Pos)
+#define SDRAMC_CR1_CELL32BIT_Pos    20      //SDRAM颗粒的位宽，1 32bit    0 16bit
+#define SDRAMC_CR1_CELL32BIT_Msk    (0x01 << SDRAMC_CR1_CELL32BIT_Pos)
+#define SDRAMC_CR1_CELLSIZE_Pos     21      //SDRAM颗粒的容量，0 64Mb    1 128Mb    2 256Mb    3 16Mb
+#define SDRAMC_CR1_CELLSIZE_Msk     (0x03 << SDRAMC_CR1_CELLSIZE_Pos)
+
+#define SDRAMC_REFRESH_RATE_Pos     0
+#define SDRAMC_REFRESH_RATE_Msk     (0xFFF << SDRAMC_REFRESH_RATE_Pos)
+#define SDRAMC_REFRESH_EN_Pos       12
+#define SDRAMC_REFRESH_EN_Msk       (0x01 << SDRAMC_REFRESH_EN_Pos)
+
+#define SDRAMC_LATCH_INEDGE_Pos     0       //哪个沿来锁存从SDRAM中读回的数据，0 上升沿    1 下降沿
+#define SDRAMC_LATCH_INEDGE_Msk     (0x01 << SDRAMC_LATCH_INEDGE_Pos)
+#define SDRAMC_LATCH_OUTEDGE_Pos    1       //哪个沿去锁存送给SDRAM的数据，1 上升沿    0 下降沿
+#define SDRAMC_LATCH_OUTEDGE_Msk    (0x01 << SDRAMC_LATCH_OUTEDGE_Pos)
+#define SDRAMC_LATCH_WAITST_Pos     2
+#define SDRAMC_LATCH_WAITST_Msk     (0x01 << SDRAMC_LATCH_WAITST_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t IE;
+
+    __IO uint32_t IF;                       //写1清零
+
+    __IO uint32_t IM;
+
+    __IO uint32_t CR;
+
+    __IO uint32_t ADDR;
+
+    __IO uint32_t CMD;
+} NORFLC_TypeDef;
+
+
+#define NORFLC_IE_FINISH_Pos        0
+#define NORFLC_IE_FINISH_Msk        (0x01 << NORFLC_IE_FINISH_Pos)
+#define NORFLC_IE_TIMEOUT_Pos       1
+#define NORFLC_IE_TIMEOUT_Msk       (0x01 << NORFLC_IE_TIMEOUT_Pos)
+
+#define NORFLC_IF_FINISH_Pos        0
+#define NORFLC_IF_FINISH_Msk        (0x01 << NORFLC_IF_FINISH_Pos)
+#define NORFLC_IF_TIMEOUT_Pos       1
+#define NORFLC_IF_TIMEOUT_Msk       (0x01 << NORFLC_IF_TIMEOUT_Pos)
+
+#define NORFLC_IM_FINISH_Pos        0
+#define NORFLC_IM_FINISH_Msk        (0x01 << NORFLC_IM_FINISH_Pos)
+#define NORFLC_IM_TIMEOUT_Pos       1
+#define NORFLC_IM_TIMEOUT_Msk       (0x01 << NORFLC_IM_TIMEOUT_Pos)
+
+#define NORFLC_CR_RDTIME_Pos        0       //Oen下降沿后多少个时钟周期后采样读回的数据。0表示1个时钟周期
+#define NORFLC_CR_RDTIME_Msk        (0x1F << NORFLC_CR_RDTIME_Pos)
+#define NORFLC_CR_WRTIME_Pos        5       //输出Wen的低电平宽度。0表示1个时钟周期
+#define NORFLC_CR_WRTIME_Msk        (0x07 << NORFLC_CR_WRTIME_Pos)
+#define NORFLC_CR_BYTEIF_Pos        8       //外部NOR FLASH数据宽度，1 8位    0 16位
+#define NORFLC_CR_BYTEIF_Msk        (0x01 << NORFLC_CR_BYTEIF_Pos)
+
+#define NORFLC_CMD_DATA_Pos         0       //在PROGRAM命令中，DATA是要写入NOR FLASH的数据；在READ命令中，DATA是从NOR FLASH读回的数据
+#define NORFLC_CMD_DATA_Msk         (0xFFFF << NORFLC_CMD_DATA_Pos)
+#define NORFLC_CMD_CMD_Pos          16       //需要执行的命令，0 READ   1 RESET   2 AUTOMATIC SELECT   3 PROGRAM   4 CHIP ERASE   5 SECTOR ERASE
+#define NORFLC_CMD_CMD_Msk          (0x07 << NORFLC_CMD_CMD_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t CR;
+
+    __O  uint32_t DATAIN;
+
+    __IO uint32_t INIVAL;
+
+    __I  uint32_t RESULT;
+} CRC_TypeDef;
+
+
+#define CRC_CR_EN_Pos               0
+#define CRC_CR_EN_Msk               (0x01 << CRC_CR_EN_Pos)
+#define CRC_CR_OREV_Pos             1       //输出结果是否翻转
+#define CRC_CR_OREV_Msk             (0x01 << CRC_CR_OREV_Pos)
+#define CRC_CR_ONOT_Pos             2       //输出结果是否取反
+#define CRC_CR_ONOT_Msk             (0x01 << CRC_CR_ONOT_Pos)
+#define CRC_CR_CRC16_Pos            3       //1 CRC16    0 CRC32
+#define CRC_CR_CRC16_Msk            (0x01 << CRC_CR_CRC16_Pos)
+#define CRC_CR_IBITS_Pos            4       //输入数据有效位数 0 32位    1 16位    2 8位
+#define CRC_CR_IBITS_Msk            (0x03 << CRC_CR_IBITS_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t MINSEC;                   //分秒计数
+
+    __IO uint32_t DATHUR;                   //日时计数
+
+    __IO uint32_t MONDAY;                   //月周计数
+
+    __IO uint32_t YEAR;                     //[11:0] 年计数，支持1901-2199
+
+    __IO uint32_t MINSECAL;                 //分秒闹铃设置
+
+    __IO uint32_t DAYHURAL;                 //周时闹铃设置
+
+    __IO uint32_t LOAD;                     //将设置寄存器中的值同步到RTC中，同步完成自动清零
+
+    __IO uint32_t IE;
+
+    __IO uint32_t IF;                       //写1清零
+
+    __IO uint32_t EN;                       //[0] 1 RTC使能
+
+    __IO uint32_t CFGABLE;                  //[0] 1 RTC可配置
+
+    __IO uint32_t TRIM;                     //时钟调整
+
+    __IO uint32_t TRIMM;                    //时钟微调整
+} RTC_TypeDef;
+
+
+#define RTC_LOAD_TIME_Pos           0
+#define RTC_LOAD_TIME_Msk           (0x01 << RTC_LOAD_TIME_Pos)
+#define RTC_LOAD_ALARM_Pos          1
+#define RTC_LOAD_ALARM_Msk          (0x01 << RTC_LOAD_ALARM_Pos)
+
+#define RTC_MINSEC_SEC_Pos          0       //秒计数，取值0--59
+#define RTC_MINSEC_SEC_Msk          (0x3F << RTC_MINSEC_SEC_Pos)
+#define RTC_MINSEC_MIN_Pos          6       //分钟计数，取值0--59
+#define RTC_MINSEC_MIN_Msk          (0x3F << RTC_MINSEC_MIN_Pos)
+
+#define RTC_DATHUR_HOUR_Pos         0       //小时计数，取值0--23
+#define RTC_DATHUR_HOUR_Msk         (0x1F << RTC_DATHUR_HOUR_Pos)
+#define RTC_DATHUR_DATE_Pos         5       //date of month，取值1--31
+#define RTC_DATHUR_DATE_Msk         (0x1F << RTC_DATHUR_DATE_Pos)
+
+#define RTC_MONDAY_DAY_Pos          0       //day of week，取值0--6
+#define RTC_MONDAY_DAY_Msk          (0x07 << RTC_MONDAY_DAY_Pos)
+#define RTC_MONDAY_MON_Pos          3       //月份计数，取值1--12
+#define RTC_MONDAY_MON_Msk          (0x0F << RTC_MONDAY_MON_Pos)
+
+#define RTC_MINSECAL_SEC_Pos        0       //闹钟秒设置
+#define RTC_MINSECAL_SEC_Msk        (0x3F << RTC_MINSECAL_SEC_Pos)
+#define RTC_MINSECAL_MIN_Pos        6       //闹钟分钟设置
+#define RTC_MINSECAL_MIN_Msk        (0x3F << RTC_MINSECAL_MIN_Pos)
+
+#define RTC_DAYHURAL_HOUR_Pos       0       //闹钟小时设置
+#define RTC_DAYHURAL_HOUR_Msk       (0x1F << RTC_DAYHURAL_HOUR_Pos)
+#define RTC_DAYHURAL_SUN_Pos        5       //周日闹钟有效
+#define RTC_DAYHURAL_SUN_Msk        (0x01 << RTC_DAYHURAL_SUN_Pos)
+#define RTC_DAYHURAL_MON_Pos        6       //周一闹钟有效
+#define RTC_DAYHURAL_MON_Msk        (0x01 << RTC_DAYHURAL_MON_Pos)
+#define RTC_DAYHURAL_TUE_Pos        7       //周二闹钟有效
+#define RTC_DAYHURAL_TUE_Msk        (0x01 << RTC_DAYHURAL_TUE_Pos)
+#define RTC_DAYHURAL_WED_Pos        8       //周三闹钟有效
+#define RTC_DAYHURAL_WED_Msk        (0x01 << RTC_DAYHURAL_WED_Pos)
+#define RTC_DAYHURAL_THU_Pos        9       //周四闹钟有效
+#define RTC_DAYHURAL_THU_Msk        (0x01 << RTC_DAYHURAL_THU_Pos)
+#define RTC_DAYHURAL_FRI_Pos        10      //周五闹钟有效
+#define RTC_DAYHURAL_FRI_Msk        (0x01 << RTC_DAYHURAL_FRI_Pos)
+#define RTC_DAYHURAL_SAT_Pos        11      //周六闹钟有效
+#define RTC_DAYHURAL_SAT_Msk        (0x01 << RTC_DAYHURAL_SAT_Pos)
+
+#define RTC_IE_SEC_Pos              0       //秒中断使能
+#define RTC_IE_SEC_Msk              (0x01 << RTC_IE_SEC_Pos)
+#define RTC_IE_MIN_Pos              1
+#define RTC_IE_MIN_Msk              (0x01 << RTC_IE_MIN_Pos)
+#define RTC_IE_HOUR_Pos             2
+#define RTC_IE_HOUR_Msk             (0x01 << RTC_IE_HOUR_Pos)
+#define RTC_IE_DATE_Pos             3
+#define RTC_IE_DATE_Msk             (0x01 << RTC_IE_DATE_Pos)
+#define RTC_IE_ALARM_Pos            4
+#define RTC_IE_ALARM_Msk            (0x01 << RTC_IE_ALARM_Pos)
+
+#define RTC_IF_SEC_Pos              0       //写1清零
+#define RTC_IF_SEC_Msk              (0x01 << RTC_IF_SEC_Pos)
+#define RTC_IF_MIN_Pos              1
+#define RTC_IF_MIN_Msk              (0x01 << RTC_IF_MIN_Pos)
+#define RTC_IF_HOUR_Pos             2
+#define RTC_IF_HOUR_Msk             (0x01 << RTC_IF_HOUR_Pos)
+#define RTC_IF_DATE_Pos             3
+#define RTC_IF_DATE_Msk             (0x01 << RTC_IF_DATE_Pos)
+#define RTC_IF_ALARM_Pos            4
+#define RTC_IF_ALARM_Msk            (0x01 << RTC_IF_ALARM_Pos)
+
+#define RTC_TRIM_ADJ_Pos            0       //用于调整BASECNT的计数周期，默认为32768，如果DEC为1，则计数周期调整为32768-ADJ，否则调整为32768+ADJ
+#define RTC_TRIM_ADJ_Msk            (0xFF << RTC_TRIM_ADJ_Pos)
+#define RTC_TRIM_DEC_Pos            8
+#define RTC_TRIM_DEC_Msk            (0x01 << RTC_TRIM_DEC_Pos)
+
+#define RTC_TRIMM_CYCLE_Pos         0       //用于计数周期微调，如果INC为1，则第n个计数周期调整为(32768±ADJ)+1,否则调整为(32768±ADJ)-1
+                                            //cycles=0时，不进行微调整；cycles=1，则n为2；cycles=7，则n为8；以此类推
+#define RTC_TRIMM_CYCLE_Msk         (0x07 << RTC_TRIMM_CYCLE_Pos)
+#define RTC_TRIMM_INC_Pos           3
+#define RTC_TRIMM_INC_Msk           (0x01 << RTC_TRIMM_INC_Pos)
+
+
+
+
+typedef struct {
+    __IO uint32_t LOAD;                     //喂狗使计数器装载LOAD值
+
+    __I  uint32_t VALUE;
+
+    __IO uint32_t CR;
+
+    __IO uint32_t IF;                       //计数到0时硬件置位，软件写1清除标志
+
+    __IO uint32_t FEED;                     //写0x55喂狗
+} WDT_TypeDef;
+
+
+#define WDT_CR_EN_Pos               0
+#define WDT_CR_EN_Msk               (0x01 << WDT_CR_EN_Pos)
+#define WDT_CR_RSTEN_Pos            1
+#define WDT_CR_RSTEN_Msk            (0x01 << WDT_CR_RSTEN_Pos)
+
+
+/******************************************************************************/
+/*                       Peripheral memory map                            */
+/******************************************************************************/
+#define RAM_BASE            0x20000000
+#define AHB_BASE            0x40000000
+#define APB_BASE            0x40010000
+
+#define NORFLC_BASE         0x60000000
+#define NORFLM_BASE         0x61000000
+
+#define SRAMC_BASE          0x68000000
+#define SRAMM_BASE          0x69000000
+
+#define SDRAMC_BASE         0x78000000
+#define SDRAMM_BASE         0x70000000
+
+/* AHB Peripheral memory map */
+#define SYS_BASE            (AHB_BASE + 0x00000)
+
+#define DMA_BASE            (AHB_BASE + 0x01000)
+
+#define LCD_BASE            (AHB_BASE + 0x02000)
+
+#define CRC_BASE            (AHB_BASE + 0x03000)
+
+#define SDIO_BASE           (AHB_BASE + 0x04000)
+
+/* APB Peripheral memory map */
+#define PORT_BASE           (APB_BASE + 0x00000)
+
+#define GPIOA_BASE          (APB_BASE + 0x01000)
+#define GPIOB_BASE          (APB_BASE + 0x02000)
+#define GPIOC_BASE          (APB_BASE + 0x03000)
+#define GPIOD_BASE          (APB_BASE + 0x04000)
+#define GPIOM_BASE          (APB_BASE + 0x05000)
+#define GPION_BASE          (APB_BASE + 0x06000)
+#define GPIOP_BASE          (APB_BASE + 0x08000)
+
+#define TIMR0_BASE          (APB_BASE + 0x07000)
+#define TIMR1_BASE          (APB_BASE + 0x0700C)
+#define TIMR2_BASE          (APB_BASE + 0x07018)
+#define TIMR3_BASE          (APB_BASE + 0x07024)
+#define TIMR4_BASE          (APB_BASE + 0x07030)
+#define TIMR5_BASE          (APB_BASE + 0x0703C)
+#define TIMRG_BASE          (APB_BASE + 0x07060)
+
+#define WDT_BASE            (APB_BASE + 0x09000)
+
+#define PWM0_BASE           (APB_BASE + 0x0A000)
+#define PWM1_BASE           (APB_BASE + 0x0A020)
+#define PWM2_BASE           (APB_BASE + 0x0A040)
+#define PWM3_BASE           (APB_BASE + 0x0A060)
+#define PWM4_BASE           (APB_BASE + 0x0A080)
+#define PWM5_BASE           (APB_BASE + 0x0A0A0)
+#define PWMG_BASE           (APB_BASE + 0x0A180)
+
+#define RTC_BASE            (APB_BASE + 0x0B000)
+
+#define ADC0_BASE           (APB_BASE + 0x0C000)
+#define ADC1_BASE           (APB_BASE + 0x0D000)
+
+#define FLASH_BASE          (APB_BASE + 0x0F000)
+
+#define UART0_BASE          (APB_BASE + 0x10000)
+#define UART1_BASE          (APB_BASE + 0x11000)
+#define UART2_BASE          (APB_BASE + 0x12000)
+#define UART3_BASE          (APB_BASE + 0x13000)
+
+#define I2C0_BASE           (APB_BASE + 0x18000)
+#define I2C1_BASE           (APB_BASE + 0x19000)
+
+#define SPI0_BASE           (APB_BASE + 0x1C000)
+#define SPI1_BASE           (APB_BASE + 0x1D000)
+
+#define CAN_BASE            (APB_BASE + 0x20000)
+
+
+/******************************************************************************/
+/*                       Peripheral declaration                          */
+/******************************************************************************/
+#define SYS                 ((SYS_TypeDef  *) SYS_BASE)
+
+#define PORT                ((PORT_TypeDef *) PORT_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOM               ((GPIO_TypeDef *) GPIOM_BASE)
+#define GPION               ((GPIO_TypeDef *) GPION_BASE)
+#define GPIOP               ((GPIO_TypeDef *) GPIOP_BASE)
+
+#define TIMR0               ((TIMR_TypeDef *) TIMR0_BASE)
+#define TIMR1               ((TIMR_TypeDef *) TIMR1_BASE)
+#define TIMR2               ((TIMR_TypeDef *) TIMR2_BASE)
+#define TIMR3               ((TIMR_TypeDef *) TIMR3_BASE)
+#define TIMR4               ((TIMR_TypeDef *) TIMR4_BASE)
+#define TIMR5               ((TIMR_TypeDef *) TIMR5_BASE)
+#define TIMRG               ((TIMRG_TypeDef*) TIMRG_BASE)
+
+#define UART0               ((UART_TypeDef *) UART0_BASE)
+#define UART1               ((UART_TypeDef *) UART1_BASE)
+#define UART2               ((UART_TypeDef *) UART2_BASE)
+#define UART3               ((UART_TypeDef *) UART3_BASE)
+
+#define SPI0                ((SPI_TypeDef  *) SPI0_BASE)
+#define SPI1                ((SPI_TypeDef  *) SPI1_BASE)
+
+#define I2C0                ((I2C_TypeDef  *) I2C0_BASE)
+#define I2C1                ((I2C_TypeDef  *) I2C1_BASE)
+
+#define ADC0                ((ADC_TypeDef  *) ADC0_BASE)
+#define ADC1                ((ADC_TypeDef  *) ADC1_BASE)
+
+#define PWM0                ((PWM_TypeDef  *) PWM0_BASE)
+#define PWM1                ((PWM_TypeDef  *) PWM1_BASE)
+#define PWM2                ((PWM_TypeDef  *) PWM2_BASE)
+#define PWM3                ((PWM_TypeDef  *) PWM3_BASE)
+#define PWM4                ((PWM_TypeDef  *) PWM4_BASE)
+#define PWM5                ((PWM_TypeDef  *) PWM5_BASE)
+#define PWMG                ((PWMG_TypeDef *) PWMG_BASE)
+
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
+
+#define DMA                 ((DMA_TypeDef  *) DMA_BASE)
+
+#define CAN                 ((CAN_TypeDef  *) CAN_BASE)
+
+#define LCD                 ((LCD_TypeDef  *) LCD_BASE)
+
+#define CRC                 ((CRC_TypeDef  *) CRC_BASE)
+
+#define RTC                 ((RTC_TypeDef  *) RTC_BASE)
+
+#define WDT                 ((WDT_TypeDef  *) WDT_BASE)
+
+#define FLASH               ((FLASH_Typedef*) FLASH_BASE)
+
+#define SRAMC               ((SRAMC_TypeDef*) SRAMC_BASE)
+
+#define NORFLC              ((NORFLC_TypeDef*) NORFLC_BASE)
+
+#define SDRAMC              ((SDRAMC_TypeDef*) SDRAMC_BASE)
+
+
+
+typedef void (* Func_void_void) (void);
+
+
+#include "SWM320_port.h"
+#include "SWM320_gpio.h"
+#include "SWM320_exti.h"
+#include "SWM320_timr.h"
+#include "SWM320_uart.h"
+#include "SWM320_spi.h"
+#include "SWM320_i2c.h"
+#include "SWM320_pwm.h"
+#include "SWM320_adc.h"
+#include "SWM320_dma.h"
+#include "SWM320_lcd.h"
+#include "SWM320_can.h"
+#include "SWM320_sdio.h"
+#include "SWM320_flash.h"
+#include "SWM320_norflash.h"
+#include "SWM320_sdram.h"
+#include "SWM320_sram.h"
+#include "SWM320_crc.h"
+#include "SWM320_rtc.h"
+#include "SWM320_wdt.h"
+
+
+#endif //__SWM320_H__