Merge pull request #3435 from sheltonyu/develop

Upload at32 bsp first version.

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_acc.h

@@ -0,0 +1,95 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_acc.h
+ * Description  : at32f4xx ACC header file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+ /* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32f4xx_ACC_H
+#define __AT32f4xx_ACC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ACC
+  * @{
+  */
+
+  /** @defgroup ACC_Exported_Constants
+  * @{
+  */
+#define ACC_CAL_Enable                        ((uint16_t)0x0001)
+
+#define ACC_CAL_ON                            ((uint16_t)0x0001)
+#define ACC_TRIM_ON                           ((uint16_t)0x0003)
+
+#define ACC_CAL_HSICAL                        ((uint16_t)0x0000)
+#define ACC_CAL_HSITRIM                       ((uint16_t)0x0002)
+  
+#define ACC_FLAG_RSLOST                       ((uint16_t)0x0002)
+#define ACC_FLAG_CALRDY                       ((uint16_t)0x0001)
+
+#define ACC_IT_CALRDYIEN                      ((uint16_t)0x0020)
+#define ACC_IT_EIEN                           ((uint16_t)0x0010)
+/**
+  * @}
+  */
+  
+/** @defgroup ACC_Exported_Functions
+  * @{
+  */  
+
+void ACC_EnterCALMode(uint16_t ACC_ON, FunctionalState NewState);
+void ACC_ExitCALMode(void);
+void ACC_SetStep(uint8_t StepValue);
+void ACC_CAL_Choose(uint16_t ACC_Calibration_Choose);
+void ACC_ITConfig(uint16_t ACC_IT, FunctionalState NewState);
+
+uint8_t ACC_GetHSITRIM(void);
+uint8_t ACC_GetHSICAL(void);
+
+void ACC_WriteC1(uint16_t ACC_C1_Value);
+void ACC_WriteC2(uint16_t ACC_C2_Value);
+void ACC_WriteC3(uint16_t ACC_C3_Value);
+
+uint16_t ACC_ReadC1(void);
+uint16_t ACC_ReadC2(void);
+uint16_t ACC_ReadC3(void);
+
+FlagStatus ACC_GetFlagStatus(uint16_t ACC_FLAG);
+void ACC_ClearFlag(uint16_t ACC_FLAG);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_ACC_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/**
+  * @}
+  */    
+
+
+
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_adc.h

@@ -0,0 +1,526 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_adc.h
+ * Description  : at32f4xx ADC header file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_ADC_H
+#define __AT32F4xx_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  ADC Init structure definition
+  */
+
+typedef struct
+{
+    uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in independent or
+                                               dual mode.
+                                               This parameter can be a value of @ref ADC_mode */
+
+    FunctionalState ADC_ScanMode;           /*!< Specifies whether the conversion is performed in
+                                                   Scan (multichannels) or Single (one channel) mode.
+                                                   This parameter can be set to ENABLE or DISABLE */
+
+    FunctionalState ADC_ContinuousMode;     /*!< Specifies whether the conversion is performed in
+                                                   Continuous or Single mode.
+                                                   This parameter can be set to ENABLE or DISABLE. */
+
+    uint32_t ADC_ExternalTrig;              /*!< Defines the external trigger used to start the analog
+                                                   to digital conversion of regular channels. This parameter
+                                                   can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+    uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data alignment is left or right.
+                                               This parameter can be a value of @ref ADC_data_align */
+
+    uint8_t ADC_NumOfChannel;               /*!< Specifies the number of ADC channels that will be converted
+                                               using the sequencer for regular channel group.
+                                               This parameter must range from 1 to 16. */
+} ADC_InitType;
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Constants
+  * @{
+  */
+
+
+#if defined (AT32F403xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+#define IS_ADC_ALL_PERIPH(PERIPH)           (((PERIPH) == ADC1) || \
+                                             ((PERIPH) == ADC2) || \
+                                             ((PERIPH) == ADC3))
+#elif defined (AT32F413xx)
+#define IS_ADC_ALL_PERIPH(PERIPH)           (((PERIPH) == ADC1) || \
+                                             ((PERIPH) == ADC2))
+#elif defined (AT32F415xx)
+#define IS_ADC_ALL_PERIPH(PERIPH)           (((PERIPH) == ADC1))
+#endif
+
+
+#if defined (AT32F403xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+#define IS_ADC_DMA_PERIPH(PERIPH)           (((PERIPH) == ADC1) || \
+                                             ((PERIPH) == ADC3))
+#elif defined (AT32F413xx) || defined (AT32F415xx)
+#define IS_ADC_DMA_PERIPH(PERIPH)           (((PERIPH) == ADC1))
+#endif
+
+
+/** @defgroup ADC_mode
+  * @{
+  */
+
+#define ADC_Mode_Independent                ((uint32_t)0x00000000)
+#define ADC_Mode_RegInjecSimult             ((uint32_t)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig        ((uint32_t)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl     ((uint32_t)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl     ((uint32_t)0x00040000)
+#define ADC_Mode_InjecSimult                ((uint32_t)0x00050000)
+#define ADC_Mode_RegSimult                  ((uint32_t)0x00060000)
+#define ADC_Mode_FastInterl                 ((uint32_t)0x00070000)
+#define ADC_Mode_SlowInterl                 ((uint32_t)0x00080000)
+#define ADC_Mode_AlterTrig                  ((uint32_t)0x00090000)
+
+#define IS_ADC_MODE(MODE)                   (((MODE) == ADC_Mode_Independent) || \
+                                             ((MODE) == ADC_Mode_RegInjecSimult) || \
+                                             ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
+                                             ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
+                                             ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
+                                             ((MODE) == ADC_Mode_InjecSimult) || \
+                                             ((MODE) == ADC_Mode_RegSimult) || \
+                                             ((MODE) == ADC_Mode_FastInterl) || \
+                                             ((MODE) == ADC_Mode_SlowInterl) || \
+                                             ((MODE) == ADC_Mode_AlterTrig))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
+  * @{
+  */
+
+#define ADC_ExternalTrig_TMR1_CC1_ADC12             ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrig_TMR1_CC2_ADC12             ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrig_TMR2_CC2_ADC12             ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrig_TMR3_TRGO_ADC12            ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrig_TMR4_CC4_ADC12             ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrig_Ext_INT11_TMR8_TRGO_ADC12  ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrig_TMR8_CC1_ADC12             ((uint32_t)0x020C0000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrig_TMR8_CC2_ADC12             ((uint32_t)0x020E0000) /*!< For ADC1 and ADC2 */
+                                                    
+#define ADC_ExternalTrig_TMR1_CC3                   ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrig_None                       ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrig_TMR15_CC1                  ((uint32_t)0x02000000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrig_TMR15_CC2                  ((uint32_t)0x02020000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrig_TMR15_CC3                  ((uint32_t)0x02040000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrig_TMR15_CC4                  ((uint32_t)0x02060000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrig_TMR15_TRGO                 ((uint32_t)0x02080000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrig_TMR1_TRGO                  ((uint32_t)0x020A0000) /*!< For ADC1, ADC2 and ADC3 */
+                                                    
+#define ADC_ExternalTrig_TMR3_CC1_ADC3              ((uint32_t)0x00000000) /*!< For ADC3 only */
+#define ADC_ExternalTrig_TMR2_CC3_ADC3              ((uint32_t)0x00020000) /*!< For ADC3 only */
+#define ADC_ExternalTrig_TMR8_CC1_ADC3              ((uint32_t)0x00060000) /*!< For ADC3 only */
+#define ADC_ExternalTrig_TMR8_TRGO_ADC3             ((uint32_t)0x00080000) /*!< For ADC3 only */
+#define ADC_ExternalTrig_TMR5_CC1_ADC3              ((uint32_t)0x000A0000) /*!< For ADC3 only */
+#define ADC_ExternalTrig_TMR5_CC3_ADC3              ((uint32_t)0x000C0000) /*!< For ADC3 only */
+#define ADC_ExternalTrig_TMR1_CC1_ADC3              ((uint32_t)0x020C0000) /*!< For ADC3 only */
+#define ADC_ExternalTrig_TMR8_CC3_ADC3              ((uint32_t)0x020E0000) /*!< For ADC3 only */
+
+#define IS_ADC_EXT_TRIG(REGTRIG)                    (((REGTRIG) == ADC_ExternalTrig_TMR1_CC1_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR1_CC2_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR2_CC2_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR3_TRGO_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR4_CC4_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_Ext_INT11_TMR8_TRGO_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR8_CC1_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR8_CC2_ADC12) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR1_CC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_None) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR15_CC1) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR15_CC2) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR15_CC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR15_CC4) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR15_TRGO) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR1_TRGO) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR3_CC1_ADC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR2_CC3_ADC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR8_CC1_ADC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR8_TRGO_ADC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR5_CC1_ADC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR5_CC3_ADC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR1_CC1_ADC3) || \
+                                                     ((REGTRIG) == ADC_ExternalTrig_TMR8_CC3_ADC3))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_data_align
+  * @{
+  */
+
+#define ADC_DataAlign_Right                         ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                          ((uint32_t)0x00000800)
+#define IS_ADC_DATA_ALIGN(ALIGN)                    (((ALIGN) == ADC_DataAlign_Right) || \
+                                                     ((ALIGN) == ADC_DataAlign_Left))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_channels
+  * @{
+  */
+
+#define ADC_Channel_0                               ((uint8_t)0x00)
+#define ADC_Channel_1                               ((uint8_t)0x01)
+#define ADC_Channel_2                               ((uint8_t)0x02)
+#define ADC_Channel_3                               ((uint8_t)0x03)
+#define ADC_Channel_4                               ((uint8_t)0x04)
+#define ADC_Channel_5                               ((uint8_t)0x05)
+#define ADC_Channel_6                               ((uint8_t)0x06)
+#define ADC_Channel_7                               ((uint8_t)0x07)
+#define ADC_Channel_8                               ((uint8_t)0x08)
+#define ADC_Channel_9                               ((uint8_t)0x09)
+#define ADC_Channel_10                              ((uint8_t)0x0A)
+#define ADC_Channel_11                              ((uint8_t)0x0B)
+#define ADC_Channel_12                              ((uint8_t)0x0C)
+#define ADC_Channel_13                              ((uint8_t)0x0D)
+#define ADC_Channel_14                              ((uint8_t)0x0E)
+#define ADC_Channel_15                              ((uint8_t)0x0F)
+#define ADC_Channel_16                              ((uint8_t)0x10)
+#define ADC_Channel_17                              ((uint8_t)0x11)
+                                                    
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
+                                                    
+#define IS_ADC_CHANNEL(CHANNEL)                     (((CHANNEL) == ADC_Channel_0)  || ((CHANNEL) == ADC_Channel_1) || \
+                                                     ((CHANNEL) == ADC_Channel_2)  || ((CHANNEL) == ADC_Channel_3) || \
+                                                     ((CHANNEL) == ADC_Channel_4)  || ((CHANNEL) == ADC_Channel_5) || \
+                                                     ((CHANNEL) == ADC_Channel_6)  || ((CHANNEL) == ADC_Channel_7) || \
+                                                     ((CHANNEL) == ADC_Channel_8)  || ((CHANNEL) == ADC_Channel_9) || \
+                                                     ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
+                                                     ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
+                                                     ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
+                                                     ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_sampling_time
+  * @{
+  */
+
+#define ADC_SampleTime_1_5                          ((uint8_t)0x00)
+#define ADC_SampleTime_7_5                          ((uint8_t)0x01)
+#define ADC_SampleTime_13_5                         ((uint8_t)0x02)
+#define ADC_SampleTime_28_5                         ((uint8_t)0x03)
+#define ADC_SampleTime_41_5                         ((uint8_t)0x04)
+#define ADC_SampleTime_55_5                         ((uint8_t)0x05)
+#define ADC_SampleTime_71_5                         ((uint8_t)0x06)
+#define ADC_SampleTime_239_5                        ((uint8_t)0x07)
+#define IS_ADC_SAMPLE_TIME(TIME)                    (((TIME) == ADC_SampleTime_1_5) || \
+                                                     ((TIME) == ADC_SampleTime_7_5) || \
+                                                     ((TIME) == ADC_SampleTime_13_5) || \
+                                                     ((TIME) == ADC_SampleTime_28_5) || \
+                                                     ((TIME) == ADC_SampleTime_41_5) || \
+                                                     ((TIME) == ADC_SampleTime_55_5) || \
+                                                     ((TIME) == ADC_SampleTime_71_5) || \
+                                                     ((TIME) == ADC_SampleTime_239_5))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
+  * @{
+  */
+
+#define ADC_ExternalTrigInjec_TMR2_TRGO_ADC12             ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjec_TMR2_CC1_ADC12              ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjec_TMR3_CC4_ADC12              ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjec_TMR4_TRGO_ADC12             ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjec_Ext_INT15_TMR8_CC4_ADC12    ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjec_TMR8_CC1_ADC12              ((uint32_t)0x01006000) /*!< For ADC1 and ADC2 */
+                                                    
+#define ADC_ExternalTrigInjec_TMR1_TRGO                   ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjec_TMR1_CC4                    ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjec_None                        ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjec_TMR15_CC1                   ((uint32_t)0x01000000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjec_TMR15_CC2                   ((uint32_t)0x01001000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjec_TMR15_CC3                   ((uint32_t)0x01002000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjec_TMR15_CC4                   ((uint32_t)0x01003000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjec_TMR15_TRGO                  ((uint32_t)0x01004000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjec_TMR1_CC1                    ((uint32_t)0x01005000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjec_TMR8_TRGO                   ((uint32_t)0x01007000) /*!< For ADC1, ADC2 and ADC3 */
+                                                    
+#define ADC_ExternalTrigInjec_TMR4_CC3_ADC3               ((uint32_t)0x00002000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjec_TMR8_CC2_ADC3               ((uint32_t)0x00003000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjec_TMR8_CC4_ADC3               ((uint32_t)0x00004000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjec_TMR5_TRGO_ADC3              ((uint32_t)0x00005000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjec_TMR5_CC4_ADC3               ((uint32_t)0x00006000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjec_TMR1_CC2_ADC3               ((uint32_t)0x01006000) /*!< For ADC3 only */
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG)              (((INJTRIG) == ADC_ExternalTrigInjec_TMR2_TRGO_ADC12) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR2_CC1_ADC12) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR3_CC4_ADC12) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR4_TRGO_ADC12) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_Ext_INT15_TMR8_CC4_ADC12) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR8_CC1_ADC12) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR1_TRGO) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR1_CC4) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_None) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR15_CC1) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR15_CC2) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR15_CC3) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR15_CC4) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR15_TRGO) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR1_CC1) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR8_TRGO) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR4_CC3_ADC3) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR8_CC2_ADC3) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR8_CC4_ADC3) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR5_TRGO_ADC3) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR5_CC4_ADC3) || \
+                                                     ((INJTRIG) == ADC_ExternalTrigInjec_TMR1_CC2_ADC3))
+                                        
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_channel_selection
+  * @{
+  */
+
+#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
+#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
+#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) == ADC_InjectedChannel_1) || \
+                                                     ((CHANNEL) == ADC_InjectedChannel_2) || \
+                                                     ((CHANNEL) == ADC_InjectedChannel_3) || \
+                                                     ((CHANNEL) == ADC_InjectedChannel_4))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_selection
+  * @{
+  */
+
+#define ADC_AnalogWDG_SingleRegEnable               ((uint32_t)0x00800200)
+#define ADC_AnalogWDG_SingleInjecEnable             ((uint32_t)0x00400200)
+#define ADC_AnalogWDG_SingleRegOrInjecEnable        ((uint32_t)0x00C00200)
+#define ADC_AnalogWDG_AllRegEnable                  ((uint32_t)0x00800000)
+#define ADC_AnalogWDG_AllInjecEnable                ((uint32_t)0x00400000)
+#define ADC_AnalogWDG_AllRegAllInjecEnable          ((uint32_t)0x00C00000)
+#define ADC_AnalogWDG_None                          ((uint32_t)0x00000000)
+
+#define IS_ADC_ANALOG_WDG(WDG)                      (((WDG) == ADC_AnalogWDG_SingleRegEnable) || \
+                                                     ((WDG) == ADC_AnalogWDG_SingleInjecEnable) || \
+                                                     ((WDG) == ADC_AnalogWDG_SingleRegOrInjecEnable) || \
+                                                     ((WDG) == ADC_AnalogWDG_AllRegEnable) || \
+                                                     ((WDG) == ADC_AnalogWDG_AllInjecEnable) || \
+                                                     ((WDG) == ADC_AnalogWDG_AllRegAllInjecEnable) || \
+                                                     ((WDG) == ADC_AnalogWDG_None))
+/**                                                 
+  * @}
+  */
+
+/** @defgroup ADC_interrupts_definition
+  * @{
+  */
+
+#define ADC_INT_EC                                  ((uint16_t)0x0220)
+#define ADC_INT_AWD                                 ((uint16_t)0x0140)
+#define ADC_INT_JEC                                 ((uint16_t)0x0480)
+
+#define IS_ADC_INT(INT)                             ((((INT) & (uint16_t)0xF81F) == 0x00) && ((INT) != 0x00))
+
+#define IS_ADC_GET_INT(INT)                         (((INT) == ADC_INT_EC) || ((INT) == ADC_INT_AWD) || \
+                                                     ((INT) == ADC_INT_JEC))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_flags_definition
+  * @{
+  */
+
+#define ADC_FLAG_AWD                                ((uint8_t)0x01)
+#define ADC_FLAG_EC                                 ((uint8_t)0x02)
+#define ADC_FLAG_JEC                                ((uint8_t)0x04)
+#define ADC_FLAG_JSTR                               ((uint8_t)0x08)
+#define ADC_FLAG_RSTR                               ((uint8_t)0x10)
+#define IS_ADC_CLEAR_FLAG(FLAG)                     ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
+#define IS_ADC_GET_FLAG(FLAG)                       (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EC) || \
+                                                     ((FLAG) == ADC_FLAG_JEC) || ((FLAG)== ADC_FLAG_JSTR) || \
+                                                     ((FLAG) == ADC_FLAG_RSTR))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_thresholds
+  * @{
+  */
+
+#define IS_ADC_THRESHOLD(THRESHOLD)                 ((THRESHOLD) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_offset
+  * @{
+  */
+
+#define IS_ADC_OFFSET(OFFSET)                       ((OFFSET) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_length
+  * @{
+  */
+
+#define IS_ADC_INJECTED_LENGTH(LENGTH)              (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_rank
+  * @{
+  */
+
+#define IS_ADC_INJECTED_RANK(RANK)                  (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup ADC_regular_length
+  * @{
+  */
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH)               (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_rank
+  * @{
+  */
+
+#define IS_ADC_REGULAR_RANK(RANK)                   (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_discontinuous_mode_number
+  * @{
+  */
+
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER)          (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions
+  * @{
+  */
+
+void ADC_Reset(ADC_Type* ADCx);
+void ADC_Init(ADC_Type* ADCx, ADC_InitType* ADC_InitStruct);
+void ADC_StructInit(ADC_InitType* ADC_InitStruct);
+void ADC_Ctrl(ADC_Type* ADCx, FunctionalState NewState);
+void ADC_DMACtrl(ADC_Type* ADCx, FunctionalState NewState);
+void ADC_INTConfig(ADC_Type* ADCx, uint16_t ADC_INT, FunctionalState NewState);
+void ADC_RstCalibration(ADC_Type* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_Type* ADCx);
+void ADC_StartCalibration(ADC_Type* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_Type* ADCx);
+void ADC_SoftwareStartConvCtrl(ADC_Type* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Type* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_Type* ADCx, uint8_t Number);
+void ADC_DiscModeCtrl(ADC_Type* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_Type* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ExternalTrigConvCtrl(ADC_Type* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_Type* ADCx);
+uint32_t ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCtrl(ADC_Type* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCtrl(ADC_Type* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_Type* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCtrl(ADC_Type* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCtrl(ADC_Type* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCtrlStatus(ADC_Type* ADCx);
+void ADC_InjectedChannelConfig(ADC_Type* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_Type* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_Type* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionValue(ADC_Type* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_AnalogWDGCtrl(ADC_Type* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWDGThresholdsConfig(ADC_Type* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWDGSingleChannelConfig(ADC_Type* ADCx, uint8_t ADC_Channel);
+void ADC_TempSensorVrefintCtrl(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_Type* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_Type* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetINTStatus(ADC_Type* ADCx, uint16_t ADC_INT);
+void ADC_ClearINTPendingBit(ADC_Type* ADCx, uint16_t ADC_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4xx_ADC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_bkp.h

@@ -0,0 +1,198 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_bkp.h
+ * Description  : at32f4xx BKP header file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_BKP_H
+#define __AT32F4xx_BKP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup BKP
+  * @{
+  */
+
+/** @defgroup BKP_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Tamper_Pin_active_level
+  * @{
+  */
+
+#define BKP_TamperPinLv_H                   ((uint16_t)0x0000)
+#define BKP_TamperPinLv_L                   ((uint16_t)0x0001)
+
+#define IS_BKP_TAMPER_PIN_LV(LV)            (((LV) == BKP_TamperPinLv_H) || \
+                                             ((LV) == BKP_TamperPinLv_L))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
+  * @{
+  */
+
+#define BKP_RTCOutput_None                  ((uint16_t)0x0000)
+#define BKP_RTCOutput_CalClk                ((uint16_t)0x0080)
+#define BKP_RTCOutput_Alarm_Pulse           ((uint16_t)0x0100)
+#define BKP_RTCOutput_Second_Pulse          ((uint16_t)0x0300)
+#if defined (AT32F403Axx) || defined (AT32F407xx) 
+#define BKP_RTCOutput_Alarm_Toggle          ((uint16_t)0x0900)
+#define BKP_RTCOutput_Second_Toggle         ((uint16_t)0x0B00)
+#endif
+
+#if defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_BKP_RTC_OUTPUT_SEL(SEL)          (((SEL) == BKP_RTCOutput_None) || \
+                                             ((SEL) == BKP_RTCOutput_CalClk) || \
+                                             ((SEL) == BKP_RTCOutput_Alarm_Pulse) || \
+                                             ((SEL) == BKP_RTCOutput_Second_Pulse) || \
+                                             ((SEL) == BKP_RTCOutput_Alarm_Toggle) || \
+                                             ((SEL) == BKP_RTCOutput_Second_Toggle))
+#elif defined (AT32F403xx) || defined (AT32F413xx)
+#define IS_BKP_RTC_OUTPUT_SEL(SEL)          (((SEL) == BKP_RTCOutput_None) || \
+                                             ((SEL) == BKP_RTCOutput_CalClk) || \
+                                             ((SEL) == BKP_RTCOutput_Alarm_Pulse) || \
+                                             ((SEL) == BKP_RTCOutput_Second_Pulse))
+#endif																		 
+/**
+  * @}
+  */
+
+/** @defgroup Data_Backup_Register
+  * @{
+  */
+
+#define BKP_DT1                             ((uint16_t)0x0004)
+#define BKP_DT2                             ((uint16_t)0x0008)
+#define BKP_DT3                             ((uint16_t)0x000C)
+#define BKP_DT4                             ((uint16_t)0x0010)
+#define BKP_DT5                             ((uint16_t)0x0014)
+#define BKP_DT6                             ((uint16_t)0x0018)
+#define BKP_DT7                             ((uint16_t)0x001C)
+#define BKP_DT8                             ((uint16_t)0x0020)
+#define BKP_DT9                             ((uint16_t)0x0024)
+#define BKP_DT10                            ((uint16_t)0x0028)
+#define BKP_DT11                            ((uint16_t)0x0040)
+#define BKP_DT12                            ((uint16_t)0x0044)
+#define BKP_DT13                            ((uint16_t)0x0048)
+#define BKP_DT14                            ((uint16_t)0x004C)
+#define BKP_DT15                            ((uint16_t)0x0050)
+#define BKP_DT16                            ((uint16_t)0x0054)
+#define BKP_DT17                            ((uint16_t)0x0058)
+#define BKP_DT18                            ((uint16_t)0x005C)
+#define BKP_DT19                            ((uint16_t)0x0060)
+#define BKP_DT20                            ((uint16_t)0x0064)
+#define BKP_DT21                            ((uint16_t)0x0068)
+#define BKP_DT22                            ((uint16_t)0x006C)
+#define BKP_DT23                            ((uint16_t)0x0070)
+#define BKP_DT24                            ((uint16_t)0x0074)
+#define BKP_DT25                            ((uint16_t)0x0078)
+#define BKP_DT26                            ((uint16_t)0x007C)
+#define BKP_DT27                            ((uint16_t)0x0080)
+#define BKP_DT28                            ((uint16_t)0x0084)
+#define BKP_DT29                            ((uint16_t)0x0088)
+#define BKP_DT30                            ((uint16_t)0x008C)
+#define BKP_DT31                            ((uint16_t)0x0090)
+#define BKP_DT32                            ((uint16_t)0x0094)
+#define BKP_DT33                            ((uint16_t)0x0098)
+#define BKP_DT34                            ((uint16_t)0x009C)
+#define BKP_DT35                            ((uint16_t)0x00A0)
+#define BKP_DT36                            ((uint16_t)0x00A4)
+#define BKP_DT37                            ((uint16_t)0x00A8)
+#define BKP_DT38                            ((uint16_t)0x00AC)
+#define BKP_DT39                            ((uint16_t)0x00B0)
+#define BKP_DT40                            ((uint16_t)0x00B4)
+#define BKP_DT41                            ((uint16_t)0x00B8)
+#define BKP_DT42                            ((uint16_t)0x00BC)
+
+#define IS_BKP_DT(DT)                       (((DT) == BKP_DT1)  || ((DT) == BKP_DT2)  || ((DT) == BKP_DT3)  || \
+                                             ((DT) == BKP_DT4)  || ((DT) == BKP_DT5)  || ((DT) == BKP_DT6)  || \
+                                             ((DT) == BKP_DT7)  || ((DT) == BKP_DT8)  || ((DT) == BKP_DT9)  || \
+                                             ((DT) == BKP_DT10) || ((DT) == BKP_DT11) || ((DT) == BKP_DT12) || \
+                                             ((DT) == BKP_DT13) || ((DT) == BKP_DT14) || ((DT) == BKP_DT15) || \
+                                             ((DT) == BKP_DT16) || ((DT) == BKP_DT17) || ((DT) == BKP_DT18) || \
+                                             ((DT) == BKP_DT19) || ((DT) == BKP_DT20) || ((DT) == BKP_DT21) || \
+                                             ((DT) == BKP_DT22) || ((DT) == BKP_DT23) || ((DT) == BKP_DT24) || \
+                                             ((DT) == BKP_DT25) || ((DT) == BKP_DT26) || ((DT) == BKP_DT27) || \
+                                             ((DT) == BKP_DT28) || ((DT) == BKP_DT29) || ((DT) == BKP_DT30) || \
+                                             ((DT) == BKP_DT31) || ((DT) == BKP_DT32) || ((DT) == BKP_DT33) || \
+                                             ((DT) == BKP_DT34) || ((DT) == BKP_DT35) || ((DT) == BKP_DT36) || \
+                                             ((DT) == BKP_DT37) || ((DT) == BKP_DT38) || ((DT) == BKP_DT39) || \
+                                             ((DT) == BKP_DT40) || ((DT) == BKP_DT41) || ((DT) == BKP_DT42))
+
+#define IS_BKP_CAL_VAL(VAL)                 ((VAL) <= 0x7F)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Functions
+  * @{
+  */
+
+void BKP_Reset(void);
+void BKP_TamperPinLvConfig(uint16_t BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_IntConfig(FunctionalState NewState);
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
+void BKP_SetRTCCalValue(uint8_t CalibrationValue);
+void BKP_WriteBackupReg(uint16_t BKP_DR, uint16_t Data);
+uint16_t BKP_ReadBackupReg(uint16_t BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetIntStatus(void);
+void BKP_ClearIntPendingBit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_BKP_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_can.h

@@ -0,0 +1,689 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_can.h
+ * Description  : at32f4xx CAN header file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_CAN_H
+#define __AT32F4xx_CAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CAN
+  * @{
+  */
+
+/** @defgroup CAN_Exported_Types
+  * @{
+  */
+
+#if defined (AT32F403xx) || defined (AT32F415xx)
+#define IS_CAN_ALL_PERIPH(PERIPH)           ((PERIPH) == CAN1)
+#elif defined (AT32F413xx) || defined (AT32F403Axx) || \
+      defined (AT32F407xx)
+#if !defined (AT32FEBKCx_MD)
+#define IS_CAN_ALL_PERIPH(PERIPH)           (((PERIPH) == CAN1) || ((PERIPH) == CAN2))
+#else
+#define IS_CAN_ALL_PERIPH(PERIPH)           (((PERIPH) == CAN1))
+#endif
+#endif
+
+/**
+  * @brief  CAN init structure definition
+  */
+
+typedef struct
+{
+    uint16_t CAN_Prescaler;                 /*!< Specifies the length of a time quantum.
+                                               It ranges from 1 to 1024. */
+                                            
+    uint8_t CAN_Mode;                       /*!< Specifies the CAN operating mode.
+                                               This parameter can be a value of
+                                              @ref CAN_operating_mode */
+                                            
+    uint8_t CAN_SJW;                        /*!< Specifies the maximum number of time quanta
+                                               the CAN hardware is allowed to lengthen or
+                                               shorten a bit to perform resynchronization.
+                                               This parameter can be a value of
+                                               @ref CAN_synchronisation_jump_width */
+                                            
+    uint8_t CAN_BS1;                        /*!< Specifies the number of time quanta in Bit
+                                               Segment 1. This parameter can be a value of
+                                               @ref CAN_time_quantum_in_bit_segment_1 */
+                                            
+    uint8_t CAN_BS2;                        /*!< Specifies the number of time quanta in Bit
+                                               Segment 2.
+                                               This parameter can be a value of
+                                               @ref CAN_time_quantum_in_bit_segment_2 */
+                                            
+    FunctionalState CAN_TTC;                /*!< Enable or disable the time triggered
+                                               communication mode. This parameter can be set
+                                               either to ENABLE or DISABLE. */
+                                            
+    FunctionalState CAN_ABO;                /*!< Enable or disable the automatic bus-off
+                                                management. This parameter can be set either
+                                                to ENABLE or DISABLE. */
+                                            
+    FunctionalState CAN_AWU;                /*!< Enable or disable the automatic wake-up mode.
+                                                This parameter can be set either to ENABLE or
+                                                DISABLE. */
+                                            
+    FunctionalState CAN_NART;                /*!< Enable or disable the no-automatic
+                                                retransmission mode. This parameter can be
+                                                set either to ENABLE or DISABLE. */
+                                            
+    FunctionalState CAN_RFL;                /*!< Enable or disable the Receive FIFO Locked mode.
+                                                This parameter can be set either to ENABLE
+                                                or DISABLE. */
+                                            
+    FunctionalState CAN_TFP;                /*!< Enable or disable the transmit FIFO priority.
+                                                This parameter can be set either to ENABLE
+                                                or DISABLE. */
+} CAN_InitType;
+
+/**
+  * @brief  CAN filter init structure definition
+  */
+
+typedef struct
+{
+    uint16_t CAN_FilterIdHigh;              /*!< Specifies the filter identification number (MSBs for a 32-bit
+                                                   configuration, first one for a 16-bit configuration).
+                                                   This parameter can be a value between 0x0000 and 0xFFFF */
+                                            
+    uint16_t CAN_FilterIdLow;               /*!< Specifies the filter identification number (LSBs for a 32-bit
+                                                   configuration, second one for a 16-bit configuration).
+                                                   This parameter can be a value between 0x0000 and 0xFFFF */
+                                            
+    uint16_t CAN_FilterMskIdHigh;           /*!< Specifies the filter mask number or identification number,
+                                                    according to the mode (MSBs for a 32-bit configuration,
+                                                    first one for a 16-bit configuration).
+                                                    This parameter can be a value between 0x0000 and 0xFFFF */
+                                            
+    uint16_t CAN_FilterMskIdLow;            /*!< Specifies the filter mask number or identification number,
+                                                    according to the mode (LSBs for a 32-bit configuration,
+                                                    second one for a 16-bit configuration).
+                                                    This parameter can be a value between 0x0000 and 0xFFFF */
+
+    uint16_t CAN_FilterFIFOAssignment;      /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+                                                   This parameter can be a value of @ref CAN_filter_FIFO */
+                                            
+    uint8_t CAN_FilterNumber;               /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+                                            
+    uint8_t CAN_FilterMode;                 /*!< Specifies the filter mode to be initialized.
+                                                   This parameter can be a value of @ref CAN_filter_mode */
+                                            
+    uint8_t CAN_FilterScale;                /*!< Specifies the filter scale.
+                                                   This parameter can be a value of @ref CAN_filter_scale */
+
+    FunctionalState CAN_FilterActivation;   /*!< Enable or disable the filter.
+                                                This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitType;
+
+/**
+  * @brief  CAN Tx message structure definition
+  */
+
+typedef struct
+{
+    uint32_t StdId;                         /*!< Specifies the standard identifier.
+                                               This parameter can be a value between 0 to 0x7FF. */
+                                            
+    uint32_t ExtId;                         /*!< Specifies the extended identifier.
+                                               This parameter can be a value between 0 to 0x1FFFFFFF. */
+                                            
+    uint8_t IDT;                            /*!< Specifies the type of identifier for the message that
+                                               will be transmitted. This parameter can be a value
+                                               of @ref CAN_identifier_type */
+                                            
+    uint8_t RTR;                            /*!< Specifies the type of frame for the message that will
+                                               be transmitted. This parameter can be a value of
+                                               @ref CAN_remote_transmission_request */
+                                            
+    uint8_t DLC;                            /*!< Specifies the length of the frame that will be
+                                               transmitted. This parameter can be a value between
+                                               0 to 8 */
+                                            
+    uint8_t Data[8];                        /*!< Contains the data to be transmitted. It ranges from 0
+                                               to 0xFF. */
+} CanTxMsg;
+
+/**
+  * @brief  CAN Rx message structure definition
+  */
+
+typedef struct
+{
+    uint32_t StdId;                         /*!< Specifies the standard identifier.
+                                               This parameter can be a value between 0 to 0x7FF. */
+                                            
+    uint32_t ExtId;                         /*!< Specifies the extended identifier.
+                                               This parameter can be a value between 0 to 0x1FFFFFFF. */
+                                            
+    uint8_t IDT;                            /*!< Specifies the type of identifier for the message that
+                                               will be received. This parameter can be a value of
+                                               @ref CAN_identifier_type */
+                                            
+    uint8_t RTR;                            /*!< Specifies the type of frame for the received message.
+                                               This parameter can be a value of
+                                               @ref CAN_remote_transmission_request */
+                                            
+    uint8_t DLC;                            /*!< Specifies the length of the frame that will be received.
+                                               This parameter can be a value between 0 to 8 */
+                                            
+    uint8_t Data[8];                        /*!< Contains the data to be received. It ranges from 0 to
+                                               0xFF. */
+                                            
+    uint8_t FID;                            /*!< Specifies the index of the filter the message stored in
+                                               the mailbox passes through. This parameter can be a
+                                               value between 0 to 0xFF */
+} CanRxMsg;
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Constants
+  * @{
+  */
+
+/** @defgroup CAN_sleep_constants
+  * @{
+  */
+
+#define CAN_InitStatus_Failed               ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitStatus_Success              ((uint8_t)0x01) /*!< CAN initialization OK */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Mode
+  * @{
+  */
+
+#define CAN_Mode_Normal                     ((uint8_t)0x00)  /*!< normal mode */
+#define CAN_Mode_LoopBack                   ((uint8_t)0x01)  /*!< loopback mode */
+#define CAN_Mode_Silent                     ((uint8_t)0x02)  /*!< silent mode */
+#define CAN_Mode_Silent_LoopBack            ((uint8_t)0x03)  /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE)                   (((MODE) == CAN_Mode_Normal) || \
+                                             ((MODE) == CAN_Mode_LoopBack)|| \
+                                             ((MODE) == CAN_Mode_Silent) || \
+                                             ((MODE) == CAN_Mode_Silent_LoopBack))
+/**
+  * @}
+  */
+
+
+/**
+  * @defgroup CAN_Operating_Mode
+  * @{
+  */
+#define CAN_OperatingMode_Initialization    ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Normal            ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Sleep             ((uint8_t)0x02) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE)         (((MODE) == CAN_OperatingMode_Initialization) ||\
+                                             ((MODE) == CAN_OperatingMode_Normal)|| \
+                                             ((MODE) == CAN_OperatingMode_Sleep))
+/**
+  * @}
+  */
+
+/**
+  * @defgroup CAN_Mode_Status
+  * @{
+  */
+
+#define CAN_ModeStatus_Failed               ((uint8_t)0x00)                /*!< CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success              ((uint8_t)!CAN_ModeStatus_Failed)   /*!< CAN entering the specific mode Succeed */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_synchronisation_jump_width
+  * @{
+  */
+
+#define CAN_SJW_1tq                         ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_SJW_2tq                         ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_SJW_3tq                         ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_SJW_4tq                         ((uint8_t)0x03)  /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW)                     (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+                                             ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1
+  * @{
+  */
+
+#define CAN_BS1_1tq                         ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS1_2tq                         ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS1_3tq                         ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS1_4tq                         ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS1_5tq                         ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS1_6tq                         ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS1_7tq                         ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS1_8tq                         ((uint8_t)0x07)  /*!< 8 time quantum */
+#define CAN_BS1_9tq                         ((uint8_t)0x08)  /*!< 9 time quantum */
+#define CAN_BS1_10tq                        ((uint8_t)0x09)  /*!< 10 time quantum */
+#define CAN_BS1_11tq                        ((uint8_t)0x0A)  /*!< 11 time quantum */
+#define CAN_BS1_12tq                        ((uint8_t)0x0B)  /*!< 12 time quantum */
+#define CAN_BS1_13tq                        ((uint8_t)0x0C)  /*!< 13 time quantum */
+#define CAN_BS1_14tq                        ((uint8_t)0x0D)  /*!< 14 time quantum */
+#define CAN_BS1_15tq                        ((uint8_t)0x0E)  /*!< 15 time quantum */
+#define CAN_BS1_16tq                        ((uint8_t)0x0F)  /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1)                     ((BS1) <= CAN_BS1_16tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2
+  * @{
+  */
+
+#define CAN_BS2_1tq                         ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS2_2tq                         ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS2_3tq                         ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS2_4tq                         ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS2_5tq                         ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS2_6tq                         ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS2_7tq                         ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS2_8tq                         ((uint8_t)0x07)  /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2)                     ((BS2) <= CAN_BS2_8tq)
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_clock_prescaler
+  * @{
+  */
+
+#define IS_CAN_PRESCALER(PRESCALER)         (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_number
+  * @{
+  */
+#define IS_CAN_FILTER_NUMBER(NUMBER)        ((NUMBER) <= 13)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_mode
+  * @{
+  */
+
+#define CAN_FilterMode_IdMask               ((uint8_t)0x00)  /*!< identifier/mask mode */
+#define CAN_FilterMode_IdList               ((uint8_t)0x01)  /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE)            (((MODE) == CAN_FilterMode_IdMask) || \
+                                             ((MODE) == CAN_FilterMode_IdList))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_scale
+  * @{
+  */
+
+#define CAN_FilterScale_16bit               ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FilterScale_32bit               ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE)          (((SCALE) == CAN_FilterScale_16bit) || \
+                                             ((SCALE) == CAN_FilterScale_32bit))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_FIFO
+  * @{
+  */
+
+#define CAN_Filter_FIFO0                    ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1                    ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(FIFO)            (((FIFO) == CAN_FilterFIFO0) || \
+                                             ((FIFO) == CAN_FilterFIFO1))
+/**
+  * @}
+  */
+
+/** @defgroup Start_bank_filter_for_slave_CAN
+  * @{
+  */
+#define IS_CAN_BANKNUMBER(BANKNUMBER)       (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Tx
+  * @{
+  */
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX)     ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID)                         ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID)                         ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC)                             ((DLC) <= ((uint8_t)0x08))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_identifier_type
+  * @{
+  */
+
+#define CAN_Id_Standard                     ((uint32_t)0x00000000)  /*!< Standard Id */
+#define CAN_Id_Extended                     ((uint32_t)0x00000004)  /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE)               (((IDTYPE) == CAN_Id_Standard) || \
+                                             ((IDTYPE) == CAN_Id_Extended))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_remote_transmission_request
+  * @{
+  */
+
+#define CAN_RTR_Data                        ((uint32_t)0x00000000)  /*!< Data frame */
+#define CAN_RTR_Remote                      ((uint32_t)0x00000002)  /*!< Remote frame */
+#define IS_CAN_RTR(RTR)                     (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_transmit_constants
+  * @{
+  */
+
+#define CAN_TxStatus_Failed                 ((uint8_t)0x00)/*!< CAN transmission failed */
+#define CAN_TxStatus_Ok                     ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxStatus_Pending                ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxStatus_NoMailBox              ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_receive_FIFO_number_constants
+  * @{
+  */
+
+#define CAN_FIFO0                           ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1                           ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO)                   (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_sleep_constants
+  * @{
+  */
+
+#define CAN_Sleep_Failed                    ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok                        ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_wake_up_constants
+  * @{
+  */
+
+#define CAN_WakeUp_Failed                   ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok                       ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/**
+  * @}
+  */
+
+/**
+  * @defgroup   CAN_Error_Code_constants
+  * @{
+  */
+
+#define CAN_ErrorCode_NoErr                 ((uint8_t)0x00) /*!< No Error */
+#define	CAN_ErrorCode_StuffErr              ((uint8_t)0x10) /*!< Stuff Error */
+#define	CAN_ErrorCode_FormErr               ((uint8_t)0x20) /*!< Form Error */
+#define	CAN_ErrorCode_ACKErr                ((uint8_t)0x30) /*!< Acknowledgment Error */
+#define	CAN_ErrorCode_BitRecessiveErr       ((uint8_t)0x40) /*!< Bit Recessive Error */
+#define	CAN_ErrorCode_BitDominantErr        ((uint8_t)0x50) /*!< Bit Dominant Error */
+#define	CAN_ErrorCode_CRCErr                ((uint8_t)0x60) /*!< CRC Error  */
+#define	CAN_ErrorCode_SoftwareSetErr        ((uint8_t)0x70) /*!< Software Set Error */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_flags
+  * @{
+  */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+   and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function.  */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0                      ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1                      ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2                      ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_RFP0                       ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
+#define CAN_FLAG_RFFU0                      ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag            */
+#define CAN_FLAG_RFOV0                      ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag         */
+#define CAN_FLAG_RFP1                       ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
+#define CAN_FLAG_RFFU1                      ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag            */
+#define CAN_FLAG_RFOV1                      ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag         */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WK                         ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SAK                        ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+         In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_ERG                        ((uint32_t)0x10F00001) /*!< Error Warning Flag   */
+#define CAN_FLAG_ERP                        ((uint32_t)0x10F00002) /*!< Error Passive Flag   */
+#define CAN_FLAG_BU                         ((uint32_t)0x10F00004) /*!< Bus-Off Flag         */
+#define CAN_FLAG_ERC                        ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG)               (((FLAG) == CAN_FLAG_ERC)   || ((FLAG) == CAN_FLAG_BU)   || \
+                                             ((FLAG) == CAN_FLAG_ERP)   || ((FLAG) == CAN_FLAG_ERG)   || \
+                                             ((FLAG) == CAN_FLAG_WK)    || ((FLAG) == CAN_FLAG_RFOV0)  || \
+                                             ((FLAG) == CAN_FLAG_RFFU0) || ((FLAG) == CAN_FLAG_RFP0)  || \
+                                             ((FLAG) == CAN_FLAG_RFOV1) || ((FLAG) == CAN_FLAG_RFFU1)   || \
+                                             ((FLAG) == CAN_FLAG_RFP1)  || ((FLAG) == CAN_FLAG_RQCP2) || \
+                                             ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
+                                             ((FLAG) == CAN_FLAG_SAK ))
+
+#define IS_CAN_CLEAR_FLAG(FLAG)             (((FLAG) == CAN_FLAG_ERC)   || ((FLAG) == CAN_FLAG_RQCP2) || \
+                                             ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
+                                             ((FLAG) == CAN_FLAG_RFFU0) || ((FLAG) == CAN_FLAG_RFOV0) ||\
+                                             ((FLAG) == CAN_FLAG_RFFU1) || ((FLAG) == CAN_FLAG_RFOV1) || \
+                                             ((FLAG) == CAN_FLAG_WK)    || ((FLAG) == CAN_FLAG_SAK))
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_interrupts
+  * @{
+  */
+
+
+
+#define CAN_INT_TSME                        ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_INT_RFP0                        ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
+#define CAN_INT_RFFU0                       ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
+#define CAN_INT_RFOV0                       ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
+#define CAN_INT_RFP1                        ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
+#define CAN_INT_RFFU1                       ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
+#define CAN_INT_RFOV1                       ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_INT_WK                          ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_INT_SAK                         ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_INT_ERG                         ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_INT_ERP                         ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_INT_BU                          ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_INT_LEC                         ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_INT_ERR                         ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_INT_RQCP0                       CAN_INT_TSME
+#define CAN_INT_RQCP1                       CAN_INT_TSME
+#define CAN_INT_RQCP2                       CAN_INT_TSME
+
+
+#define IS_CAN_INT(INT)                     (((INT) == CAN_INT_TSME)  || ((INT) == CAN_INT_RFP0)  ||\
+                                             ((INT) == CAN_INT_RFFU0) || ((INT) == CAN_INT_RFOV0)  ||\
+                                             ((INT) == CAN_INT_RFP1)  || ((INT) == CAN_INT_RFFU1)   ||\
+                                             ((INT) == CAN_INT_RFOV1) || ((INT) == CAN_INT_ERG)   ||\
+                                             ((INT) == CAN_INT_ERP)   || ((INT) == CAN_INT_BU)   ||\
+                                             ((INT) == CAN_INT_LEC)   || ((INT) == CAN_INT_ERR)   ||\
+                                             ((INT) == CAN_INT_WK)    || ((INT) == CAN_INT_SAK))
+
+#define IS_CAN_CLEAR_INT(INT)               (((INT) == CAN_INT_TSME)  || ((INT) == CAN_INT_RFFU0)    ||\
+                                             ((INT) == CAN_INT_RFOV0) || ((INT) == CAN_INT_RFFU1)    ||\
+                                             ((INT) == CAN_INT_RFOV1) || ((INT) == CAN_INT_ERG)    ||\
+                                             ((INT) == CAN_INT_ERP)   || ((INT) == CAN_INT_BU)    ||\
+                                             ((INT) == CAN_INT_LEC)   || ((INT) == CAN_INT_ERR)    ||\
+                                             ((INT) == CAN_INT_WK)    || ((INT) == CAN_INT_SAK))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Legacy
+  * @{
+  */
+#define CANINITFAILED                       CAN_InitStatus_Failed
+#define CANINITOK                           CAN_InitStatus_Success
+#define CAN_FilterFIFO0                     CAN_Filter_FIFO0
+#define CAN_FilterFIFO1                     CAN_Filter_FIFO1
+#define CAN_ID_STD                          CAN_Id_Standard
+#define CAN_ID_EXT                          CAN_Id_Extended
+#define CAN_RTR_DATA                        CAN_RTR_Data
+#define CAN_RTR_REMOTE                      CAN_RTR_Remote
+#define CANTXFAILE                          CAN_TxStatus_Failed
+#define CANTXOK                             CAN_TxStatus_Ok
+#define CANTXPENDING                        CAN_TxStatus_Pending
+#define CAN_NO_MB                           CAN_TxStatus_NoMailBox
+#define CANSLEEPFAILED                      CAN_Sleep_Failed
+#define CANSLEEPOK                          CAN_Sleep_Ok
+#define CANWAKEUPFAILED                     CAN_WakeUp_Failed
+#define CANWAKEUPOK                         CAN_WakeUp_Ok
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Functions
+  * @{
+  */
+/*  Function used to set the CAN configuration to the default reset state *****/
+void CAN_Reset(CAN_Type* CANx);
+
+/* Initialization and Configuration functions *********************************/
+uint8_t CAN_Init(CAN_Type* CANx, CAN_InitType* CAN_InitStruct);
+void CAN_FilterInit(CAN_Type* CANx, CAN_FilterInitType* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitType* CAN_InitStruct);
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
+void CAN_DBGFreeze(CAN_Type* CANx, FunctionalState NewState);
+void CAN_TTComModeCtrl(CAN_Type* CANx, FunctionalState NewState);
+
+/* Transmit functions *********************************************************/
+uint8_t CAN_Transmit(CAN_Type* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_Type* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_Type* CANx, uint8_t Mailbox);
+
+/* Receive functions **********************************************************/
+void CAN_Receive(CAN_Type* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_FIFORelease(CAN_Type* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_Type* CANx, uint8_t FIFONumber);
+
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeRequest(CAN_Type* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_Sleep(CAN_Type* CANx);
+uint8_t CAN_WakeUp(CAN_Type* CANx);
+
+/* Error management functions *************************************************/
+uint8_t CAN_GetLastErrorCode(CAN_Type* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_Type* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_Type* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_INTConfig(CAN_Type* CANx, uint32_t CAN_INT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_Type* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_Type* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetINTStatus(CAN_Type* CANx, uint32_t CAN_INT);
+void CAN_ClearINTPendingBit(CAN_Type* CANx, uint32_t CAN_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_CAN_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_comp.h

@@ -0,0 +1,271 @@
+/**
+  ******************************************************************************
+  * @file    at32f4xx_comp.h
+  * @author  Artery
+  * @version V1.0.1
+  * @date    20-April-2012
+  * @brief   This file contains all the functions prototypes for the COMP firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 Artery</center></h2>
+  *
+  * Licensed under Artery Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4XX_COMP_H
+#define __AT32F4XX_COMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup AT32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup COMP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  COMP Init structure definition  
+  */
+  
+typedef struct
+{
+
+  uint32_t COMP_INMInput;     /*!< Selects the inverting input of the comparator.
+                                          This parameter can be a value of @ref COMP_INMInput */
+
+  uint32_t COMP_Output;             /*!< Selects the output redirection of the comparator.
+                                          This parameter can be a value of @ref COMP_Output */
+
+  uint32_t COMP_OutPolarity;           /*!< Selects the output polarity of the comparator.
+                                          This parameter can be a value of @ref COMP_OutputPolarity */
+
+  uint32_t COMP_Hysteresis;         /*!< Selects the hysteresis voltage of the comparator.
+                                          This parameter can be a value of @ref COMP_Hysteresis */
+
+  uint32_t COMP_Mode;               /*!< Selects the operating mode of the comparator
+                                         and allows to adjust the speed/consumption.
+                                          This parameter can be a value of @ref COMP_Mode */
+
+}COMP_InitType;
+
+/* Exported constants --------------------------------------------------------*/
+   
+/** @defgroup COMP_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup COMP_Selection
+  * @{
+  */
+
+#define COMP1_Selection                    ((uint32_t)0x00000000) /*!< COMP1 Selection */
+#define COMP2_Selection                    ((uint32_t)0x00000010) /*!< COMP2 Selection */
+
+#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP1_Selection) || \
+                                    ((PERIPH) == COMP2_Selection))
+ 
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_NonInvertingInput
+  * @{
+  */
+
+#define COMP_INPInput_00               ((uint32_t)0x00000000) /*!< PA5/PA7 connected to comparator1/2 non-inverting input */
+#define COMP_INPInput_01               ((uint32_t)0x00000001) /*!< PA1/PA3 connected to comparator1/2 non-inverting input */
+#define COMP_INPInput_10               ((uint32_t)0x00000002) /*!< PA0/PA2 connected to comparator1/2 non-inverting input */
+
+#define IS_COMP_NONINVERTING_INPUT(INPUT) (((INPUT) == COMP_INPInput_00) || \
+                                          ((INPUT) == COMP_INPInput_01) || \
+                                          ((INPUT) == COMP_INPInput_10))
+
+/** @defgroup COMP_InvertingInput
+  * @{
+  */
+
+#define COMP_INMInput_1_4VREFINT          ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
+#define COMP_INMInput_1_2VREFINT          ((uint32_t)0x00000010) /*!< 1/2 VREFINT connected to comparator inverting input */
+#define COMP_INMInput_3_4VREFINT          ((uint32_t)0x00000020) /*!< 3/4 VREFINT connected to comparator inverting input */
+#define COMP_INMInput_VREFINT             ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
+#define COMP_INMInput_IN1                 ((uint32_t)0x00000040) /*!< I/O (PA4 for COMP1 and PA3 for COMP2) connected to comparator inverting input */
+#define COMP_INMInput_IN2                 ((uint32_t)0x00000050) /*!< I/O (PA5 for COMP1 and PA7 for COMP2) connected to comparator inverting input */
+#define COMP_INMInput_IN3                 ((uint32_t)0x00000060) /*!< I/O (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */
+
+#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_INMInput_1_4VREFINT) || \
+                                        ((INPUT) == COMP_INMInput_1_2VREFINT) || \
+                                        ((INPUT) == COMP_INMInput_3_4VREFINT) || \
+                                        ((INPUT) == COMP_INMInput_VREFINT)    || \
+                                        ((INPUT) == COMP_INMInput_IN1)       || \
+                                        ((INPUT) == COMP_INMInput_1_4VREFINT) || \
+                                        ((INPUT) == COMP_INMInput_IN3))
+/**
+  * @}
+  */ 
+  
+/** @defgroup COMP_Output
+  * @{
+  */
+
+#define COMP_Output_None                  ((uint32_t)0x00000000)   /*!< COMP output isn't connected to other peripherals */
+#define COMP_Output_TMR1BKIN              ((uint32_t)0x00000100)   /*!< COMP output connected to TIM1 Break Input (BKIN) */
+#define COMP_Output_TMR1IC1               ((uint32_t)0x00000200)   /*!< COMP output connected to TIM1 Input Capture 1 */
+#define COMP_Output_TMR1OCREFCLR          ((uint32_t)0x00000300)   /*!< COMP output connected to TIM1 OCREF Clear */
+#define COMP_Output_TMR2IC4               ((uint32_t)0x00000400)   /*!< COMP output connected to TIM2 Input Capture 4 */
+#define COMP_Output_TMR2OCREFCLR          ((uint32_t)0x00000500)   /*!< COMP output connected to TIM2 OCREF Clear */
+#define COMP_Output_TMR3IC1               ((uint32_t)0x00000600)   /*!< COMP output connected to TIM3 Input Capture 1 */
+#define COMP_Output_TMR3OCREFCLR          ((uint32_t)0x00000700)   /*!< COMP output connected to TIM3 OCREF Clear */
+
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None)         || \
+                                ((OUTPUT) == COMP_Output_TMR1BKIN)     || \
+                                ((OUTPUT) == COMP_Output_TMR1IC1)      || \
+                                ((OUTPUT) == COMP_Output_TMR1OCREFCLR) || \
+                                ((OUTPUT) == COMP_Output_TMR2IC4)      || \
+                                ((OUTPUT) == COMP_Output_TMR2OCREFCLR) || \
+                                ((OUTPUT) == COMP_Output_TMR3IC1)      || \
+                                ((OUTPUT) == COMP_Output_TMR3OCREFCLR))
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_OutputPolarity
+  * @{
+  */
+#define COMP_OutPolarity_NonInverted          ((uint32_t)0x00000000)  /*!< COMP output on GPIO isn't inverted */
+#define COMP_OutPolarity_Inverted             COMP_CTRLSTS_COMP1POL       /*!< COMP output on GPIO is inverted */
+
+#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutPolarity_NonInverted)  || \
+                                 ((POL) == COMP_OutPolarity_Inverted))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_Hysteresis
+  * @{
+  */
+/* Please refer to the electrical characteristics in the device datasheet for
+   the hysteresis level */
+#define COMP_Hysteresis_No                         ((uint32_t)0x00000000)   /*!< No hysteresis */
+#define COMP_Hysteresis_Low                        COMP_CTRLSTS_COMP1HYST_0 /*!< Hysteresis level low */
+#define COMP_Hysteresis_Medium                     COMP_CTRLSTS_COMP1HYST_1 /*!< Hysteresis level medium */
+#define COMP_Hysteresis_High                       COMP_CTRLSTS_COMP1HYST   /*!< Hysteresis level high */
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS)    (((HYSTERESIS) == COMP_Hysteresis_No) || \
+                                           ((HYSTERESIS) == COMP_Hysteresis_Low) || \
+                                           ((HYSTERESIS) == COMP_Hysteresis_Medium) || \
+                                           ((HYSTERESIS) == COMP_Hysteresis_High))
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Mode
+  * @{
+  */
+/* Please refer to the electrical characteristics in the device datasheet for
+   the power consumption values */
+#define COMP_Mode_Fast                     ((uint32_t)0x00000000)  /*!< High Speed */
+#define COMP_Mode_Slow                     COMP_CTRLSTS_COMP1MDE_0 /*!< Low power mode */
+
+#define IS_COMP_MODE(MODE)    (((MODE) == COMP_Mode_Slow)      || \
+                               ((MODE) == COMP_Mode_Fast))
+/**
+  * @}
+  */
+
+/** @defgroup COMP_OutputLevel
+  * @{
+  */ 
+/* When output polarity is not inverted, comparator output is high when
+   the non-inverting input is at a higher voltage than the inverting input */
+#define COMP_OutputState_High                   COMP_CTRLSTS_COMP1OUT
+/* When output polarity is not inverted, comparator output is low when
+   the non-inverting input is at a lower voltage than the inverting input*/
+#define COMP_OutputState_Low                    ((uint32_t)0x00000000)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_High_Pulse_Filter
+  * @{
+  */        
+  
+#define IS_COMP_HighPulseCnt(HighPulse)          ((HighPulse) <= 0x3F)
+/**
+  * @}
+  */
+  
+/** @defgroup COMP_Low_Pulse_Filter
+  * @{
+  */        
+  
+#define IS_COMP_LowPulseCnt(LowPulse)            ((LowPulse) <= 0x3F)
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the COMP configuration to the default reset state ****/
+void COMP_Reset(void);
+
+/* Initialization and Configuration functions *********************************/
+void COMP_Init(uint32_t COMP_Selection, COMP_InitType* COMP_InitStruct);
+void COMP_SelectINPInput(uint32_t COMP_Selection, uint32_t COMP_INPInput);
+void COMP_StructInit(COMP_InitType* COMP_InitStruct);
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
+void COMP_SwitchCmd(FunctionalState NewState);
+uint32_t COMP_GetOutputState(uint32_t COMP_Selection);
+
+/* Window mode control function ***********************************************/
+void COMP_WindowCmd(FunctionalState NewState);
+
+/* COMP configuration locking function ****************************************/
+void COMP_LockConfig(uint32_t COMP_Selection);
+
+/* COMP configuration glitch filter ****************************************/
+void COMP_FilterConfig(uint16_t COMP_HighPulseCnt, uint16_t COMP_LowPulseCnt, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4xx_COMP_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT Artery *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_crc.h

@@ -0,0 +1,82 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_crc.h
+ * Description  : at32f4xx CRC header file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_CRC_H
+#define __AT32F4xx_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/** @defgroup CRC_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Functions
+  * @{
+  */
+
+void CRC_ResetDT(void);
+uint32_t CRC_CalculateCRC(uint32_t Data);
+uint32_t CRC_CalculateBlkCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void CRC_SetIDTReg(uint8_t IDValue);
+uint8_t CRC_GetIDTReg(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_CRC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_dac.h

@@ -0,0 +1,269 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_dac.h
+ * Description  : at32f4xx DAC header file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_DAC_H
+#define __AT32F4xx_DAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/** @defgroup DAC_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  DAC Init structure definition
+  */
+
+typedef struct
+{
+    uint32_t DAC_Trigger;                           /*!< Specifies the external trigger for the selected DAC channel.
+                                                       This parameter can be a value of @ref DAC_trigger_selection */
+                                                    
+    uint32_t DAC_WaveGeneration;                    /*!< Specifies whether DAC channel noise waves or triangle waves
+                                                       are generated, or whether no wave is generated.
+                                                       This parameter can be a value of @ref DAC_wave_generation */
+                                                    
+    uint32_t DAC_LFSRUnmask_TriangleAmplitude;      /*!< Specifies the LFSR mask for noise wave generation or
+                                                       the maximum amplitude triangle generation for the DAC channel.
+                                                       This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+                                                    
+    uint32_t DAC_OutputBuffer;                      /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                                       This parameter can be a value of @ref DAC_output_buffer */
+} DAC_InitType;
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DAC_trigger_selection
+  * @{
+  */
+
+#define DAC_Trigger_None                    ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_Trigger_TMR6_TRGO               ((uint32_t)0x00000004) /*!< TMR6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_TMR8_TRGO               ((uint32_t)0x0000000C) /*!< TMR8 TRGO selected as external conversion trigger for DAC channel
+                                                                      only in High-density devices*/
+#define DAC_Trigger_TMR7_TRGO               ((uint32_t)0x00000014) /*!< TMR7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_TMR5_TRGO               ((uint32_t)0x0000001C) /*!< TMR5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_TMR2_TRGO               ((uint32_t)0x00000024) /*!< TMR2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_TMR4_TRGO               ((uint32_t)0x0000002C) /*!< TMR4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Ext_INT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software                ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER)             (((TRIGGER) == DAC_Trigger_None) || \
+                                             ((TRIGGER) == DAC_Trigger_TMR6_TRGO) || \
+                                             ((TRIGGER) == DAC_Trigger_TMR8_TRGO) || \
+                                             ((TRIGGER) == DAC_Trigger_TMR7_TRGO) || \
+                                             ((TRIGGER) == DAC_Trigger_TMR5_TRGO) || \
+                                             ((TRIGGER) == DAC_Trigger_TMR2_TRGO) || \
+                                             ((TRIGGER) == DAC_Trigger_TMR4_TRGO) || \
+                                             ((TRIGGER) == DAC_Trigger_Ext_INT9) || \
+                                             ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation
+  * @{
+  */
+
+#define DAC_WaveGeneration_None             ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise            ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle         ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE)          (((WAVE) == DAC_WaveGeneration_None) || \
+                                             ((WAVE) == DAC_WaveGeneration_Noise) || \
+                                             ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+  * @{
+  */
+
+#define DAC_LFSRUnmsk_Bit0                  ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmsk_Bits1_0               ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits2_0               ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits3_0               ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits4_0               ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits5_0               ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits6_0               ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits7_0               ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits8_0               ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits9_0               ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits10_0              ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmsk_Bits11_0              ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmp_1                   ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmp_3                   ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmp_7                   ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmp_15                  ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmp_31                  ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmp_63                  ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmp_127                 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmp_255                 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmp_511                 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmp_1023                ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmp_2047                ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmp_4095                ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)    (((VALUE) == DAC_LFSRUnmsk_Bit0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits1_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits2_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits3_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits4_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits5_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits6_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits7_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits8_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits9_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits10_0) || \
+                                                         ((VALUE) == DAC_LFSRUnmsk_Bits11_0) || \
+                                                         ((VALUE) == DAC_TriangleAmp_1) || \
+                                                         ((VALUE) == DAC_TriangleAmp_3) || \
+                                                         ((VALUE) == DAC_TriangleAmp_7) || \
+                                                         ((VALUE) == DAC_TriangleAmp_15) || \
+                                                         ((VALUE) == DAC_TriangleAmp_31) || \
+                                                         ((VALUE) == DAC_TriangleAmp_63) || \
+                                                         ((VALUE) == DAC_TriangleAmp_127) || \
+                                                         ((VALUE) == DAC_TriangleAmp_255) || \
+                                                         ((VALUE) == DAC_TriangleAmp_511) || \
+                                                         ((VALUE) == DAC_TriangleAmp_1023) || \
+                                                         ((VALUE) == DAC_TriangleAmp_2047) || \
+                                                         ((VALUE) == DAC_TriangleAmp_4095))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_output_buffer
+  * @{
+  */
+
+#define DAC_OutputBuffer_Enable             ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable            ((uint32_t)0x00000002)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE)   (((STATE) == DAC_OutputBuffer_Enable) || \
+                                             ((STATE) == DAC_OutputBuffer_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Channel_selection
+  * @{
+  */
+
+#define DAC_Channel_1                       ((uint32_t)0x00000000)
+#define DAC_Channel_2                       ((uint32_t)0x00000010)
+#define IS_DAC_CHANNEL(CHANNEL)             (((CHANNEL) == DAC_Channel_1) || \
+                                             ((CHANNEL) == DAC_Channel_2))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignment
+  * @{
+  */
+
+#define DAC_Align_12b_Right                 ((uint32_t)0x00000000)
+#define DAC_Align_12b_Left                  ((uint32_t)0x00000004)
+#define DAC_Align_8b_Right                  ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN)                 (((ALIGN) == DAC_Align_12b_Right) || \
+                                             ((ALIGN) == DAC_Align_12b_Left) || \
+                                             ((ALIGN) == DAC_Align_8b_Right))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation
+  * @{
+  */
+
+#define DAC_Wave_Noise                      ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle                   ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE)                   (((WAVE) == DAC_Wave_Noise) || \
+                                             ((WAVE) == DAC_Wave_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data
+  * @{
+  */
+
+#define IS_DAC_DATA(DATA)                   ((DATA) <= 0xFFF0)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Functions
+  * @{
+  */
+
+void DAC_Reset(void);
+void DAC_Init(uint32_t DAC_Channel, DAC_InitType* DAC_InitStruct);
+void DAC_StructInit(DAC_InitType* DAC_InitStruct);
+void DAC_Ctrl(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DMACtrl(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCtrl(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCtrl(FunctionalState NewState);
+void DAC_WaveGenerationCtrl(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4xx_DAC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_dbgmcu.h

@@ -0,0 +1,105 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_dbgmcu.h
+ * Description  : at32f4xx MCUDBG header file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_MCUDBG_H
+#define __AT32F4xx_MCUDBG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DBGMCU
+  * @{
+  */
+
+/** @defgroup DBGMCU_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Exported_Constants
+  * @{
+  */
+
+#define MCUDBG_SLEEP                        ((uint32_t)0x00000001)
+#define MCUDBG_STOP                         ((uint32_t)0x00000002)
+#define MCUDBG_STANDBY                      ((uint32_t)0x00000004)
+#define MCUDBG_IWDG_STOP                    ((uint32_t)0x00000100)
+#define MCUDBG_WWDG_STOP                    ((uint32_t)0x00000200)
+#define MCUDBG_TMR1_STOP                    ((uint32_t)0x00000400)
+#define MCUDBG_TMR2_STOP                    ((uint32_t)0x00000800)
+#define MCUDBG_TMR3_STOP                    ((uint32_t)0x00001000)
+#define MCUDBG_TMR4_STOP                    ((uint32_t)0x00002000)
+#define MCUDBG_CAN1_STOP                    ((uint32_t)0x00004000)
+#define MCUDBG_I2C1_SMBUS_TIMEOUT           ((uint32_t)0x00008000)
+#define MCUDBG_I2C2_SMBUS_TIMEOUT           ((uint32_t)0x00010000)
+#define MCUDBG_TMR8_STOP                    ((uint32_t)0x00020000)
+#define MCUDBG_TMR5_STOP                    ((uint32_t)0x00040000)
+#define MCUDBG_TMR6_STOP                    ((uint32_t)0x00080000)
+#define MCUDBG_TMR7_STOP                    ((uint32_t)0x00100000)
+#define MCUDBG_TMR15_STOP                   ((uint32_t)0x00400000)
+#define MCUDBG_TMR12_STOP                   ((uint32_t)0x02000000)
+#define MCUDBG_TMR13_STOP                   ((uint32_t)0x04000000)
+#define MCUDBG_TMR14_STOP                   ((uint32_t)0x08000000)
+#define MCUDBG_TMR9_STOP                    ((uint32_t)0x10000000)
+#define MCUDBG_TMR10_STOP                   ((uint32_t)0x20000000)
+#define MCUDBG_TMR11_STOP                   ((uint32_t)0x40000000)
+#define MCUDBG_I2C3_SMBUS_TIMEOUT           ((uint32_t)0x80000000)
+
+#define IS_MCUDBG_PERIPH(PERIPH)            ((((PERIPH) & 0x008000F8) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Exported_Functions
+  * @{
+  */
+
+uint32_t MCUDBG_GetRevID(void);
+uint32_t MCUDBG_GetDevID(void);
+void MCUDBG_PeriphDebugModeConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_MCUDBG_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_dma.h

@@ -0,0 +1,574 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_dma.h
+ * Description  : at32f4xx DMA header file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_DMA_H
+#define __AT32F4xx_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/** @defgroup DMA_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  DMA Init structure definition
+  */
+
+typedef struct
+{
+    uint32_t DMA_PeripheralBaseAddr;        /*!< Specifies the peripheral base address for DMAy Channelx. */
+                                            
+    uint32_t DMA_MemoryBaseAddr;            /*!< Specifies the memory base address for DMAy Channelx. */
+                                            
+    uint32_t DMA_Direction;                 /*!< Specifies if the peripheral is the source or destination.
+                                               This parameter can be a value of @ref DMA_data_transfer_direction */
+                                            
+    uint32_t DMA_BufferSize;                /*!< Specifies the buffer size, in data unit, of the specified Channel.
+                                               The data unit is equal to the configuration set in DMA_PeripheralDataWidth
+                                               or DMA_MemoryDataWidth members depending in the transfer direction. */
+                                            
+    uint32_t DMA_PeripheralInc;             /*!< Specifies whether the Peripheral address register is incremented or not.
+                                               This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+                                            
+    uint32_t DMA_MemoryInc;                 /*!< Specifies whether the memory address register is incremented or not.
+                                               This parameter can be a value of @ref DMA_memory_incremented_mode */
+                                            
+    uint32_t DMA_PeripheralDataWidth;       /*!< Specifies the Peripheral data width.
+                                               This parameter can be a value of @ref DMA_peripheral_data_size */
+                                            
+    uint32_t DMA_MemoryDataWidth;           /*!< Specifies the Memory data width.
+                                               This parameter can be a value of @ref DMA_memory_data_size */
+                                            
+    uint32_t DMA_Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
+                                               This parameter can be a value of @ref DMA_circular_normal_mode.
+                                               @note: The circular buffer mode cannot be used if the memory-to-memory
+                                                     data transfer is configured on the selected Channel */
+                                            
+    uint32_t DMA_Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
+                                               This parameter can be a value of @ref DMA_priority_level */
+                                            
+    uint32_t DMA_MTOM;                      /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+                                               This parameter can be a value of @ref DMA_memory_to_memory */
+} DMA_InitType;
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Constants
+  * @{
+  */
+
+#define IS_DMA_ALL_PERIPH(PERIPH)           (((PERIPH) == DMA1_Channel1) || \
+                                             ((PERIPH) == DMA1_Channel2) || \
+                                             ((PERIPH) == DMA1_Channel3) || \
+                                             ((PERIPH) == DMA1_Channel4) || \
+                                             ((PERIPH) == DMA1_Channel5) || \
+                                             ((PERIPH) == DMA1_Channel6) || \
+                                             ((PERIPH) == DMA1_Channel7) || \
+                                             ((PERIPH) == DMA2_Channel1) || \
+                                             ((PERIPH) == DMA2_Channel2) || \
+                                             ((PERIPH) == DMA2_Channel3) || \
+                                             ((PERIPH) == DMA2_Channel4) || \
+                                             ((PERIPH) == DMA2_Channel5))
+
+
+/** @defgroup DMA_flexible_channel
+  * @{
+  */
+#define Flex_Channel1          ((uint8_t)0x01)
+#define Flex_Channel2          ((uint8_t)0x02)
+#define Flex_Channel3          ((uint8_t)0x03)
+#define Flex_Channel4          ((uint8_t)0x04)
+#define Flex_Channel5          ((uint8_t)0x05)
+#define Flex_Channel6          ((uint8_t)0x06)
+#define Flex_Channel7          ((uint8_t)0x07)
+
+#define IS_DMA_ALL_CHANNELS(CHANNELS)     (((CHANNELS) == Flex_Channel1) || \
+                                           ((CHANNELS) == Flex_Channel2) || \
+                                           ((CHANNELS) == Flex_Channel3) || \
+                                           ((CHANNELS) == Flex_Channel4) || \
+                                           ((CHANNELS) == Flex_Channel5) || \
+                                           ((CHANNELS) == Flex_Channel6) || \
+                                           ((CHANNELS) == Flex_Channel7))
+
+/** @defgroup DMA_hardware_id
+  * @{
+  */
+#define DMA_FLEXIBLE_ADC1           ((uint8_t)0x01)
+#define DMA_FLEXIBLE_ADC3           ((uint8_t)0x03)
+#define DMA_FLEXIBLE_DAC1           ((uint8_t)0x05)
+#define DMA_FLEXIBLE_DAC2           ((uint8_t)0x06)
+#define DMA_FLEXIBLE_SPI1_RX        ((uint8_t)0x09)
+#define DMA_FLEXIBLE_SPI1_TX        ((uint8_t)0x0A)
+#define DMA_FLEXIBLE_SPI2_RX        ((uint8_t)0x0B)
+#define DMA_FLEXIBLE_SPI2_TX        ((uint8_t)0x0C)
+#define DMA_FLEXIBLE_SPI3_RX        ((uint8_t)0x0D)
+#define DMA_FLEXIBLE_SPI3_TX        ((uint8_t)0x0E)
+#define DMA_FLEXIBLE_SPI4_RX        ((uint8_t)0x0F)
+#define DMA_FLEXIBLE_SPI4_TX        ((uint8_t)0x10)
+#define DMA_FLEXIBLE_I2S2EXT_RX     ((uint8_t)0x11)
+#define DMA_FLEXIBLE_I2S2EXT_TX     ((uint8_t)0x12)
+#define DMA_FLEXIBLE_I2S3EXT_RX     ((uint8_t)0x13)
+#define DMA_FLEXIBLE_I2S3EXT_TX     ((uint8_t)0x14)
+#define DMA_FLEXIBLE_UART1_RX       ((uint8_t)0x19)
+#define DMA_FLEXIBLE_UART1_TX       ((uint8_t)0x1A)
+#define DMA_FLEXIBLE_UART2_RX       ((uint8_t)0x1B)
+#define DMA_FLEXIBLE_UART2_TX       ((uint8_t)0x1C)
+#define DMA_FLEXIBLE_UART3_RX       ((uint8_t)0x1D)
+#define DMA_FLEXIBLE_UART3_TX       ((uint8_t)0x1E)
+#define DMA_FLEXIBLE_UART4_RX       ((uint8_t)0x1F)
+#define DMA_FLEXIBLE_UART4_TX       ((uint8_t)0x20)
+#define DMA_FLEXIBLE_UART5_RX       ((uint8_t)0x21)
+#define DMA_FLEXIBLE_UART5_TX       ((uint8_t)0x22)
+#define DMA_FLEXIBLE_UART6_RX       ((uint8_t)0x23)
+#define DMA_FLEXIBLE_UART6_TX       ((uint8_t)0x24)
+#define DMA_FLEXIBLE_UART7_RX       ((uint8_t)0x25)
+#define DMA_FLEXIBLE_UART7_TX       ((uint8_t)0x26)
+#define DMA_FLEXIBLE_UART8_RX       ((uint8_t)0x27)
+#define DMA_FLEXIBLE_UART8_TX       ((uint8_t)0x28)
+#define DMA_FLEXIBLE_I2C1_RX        ((uint8_t)0x29)
+#define DMA_FLEXIBLE_I2C1_TX        ((uint8_t)0x2A)
+#define DMA_FLEXIBLE_I2C2_RX        ((uint8_t)0x2B)
+#define DMA_FLEXIBLE_I2C2_TX        ((uint8_t)0x2C)
+#define DMA_FLEXIBLE_I2C3_RX        ((uint8_t)0x2D)
+#define DMA_FLEXIBLE_I2C3_TX        ((uint8_t)0x2E)
+#define DMA_FLEXIBLE_SDIO1          ((uint8_t)0x31)
+#define DMA_FLEXIBLE_SDIO2          ((uint8_t)0x32)
+#define DMA_FLEXIBLE_TIM1_TRIG      ((uint8_t)0x35)
+#define DMA_FLEXIBLE_TIM1_COM       ((uint8_t)0x36)
+#define DMA_FLEXIBLE_TIM1_UP        ((uint8_t)0x37)
+#define DMA_FLEXIBLE_TIM1_CH1       ((uint8_t)0x38)
+#define DMA_FLEXIBLE_TIM1_CH2       ((uint8_t)0x39)
+#define DMA_FLEXIBLE_TIM1_CH3       ((uint8_t)0x3A)
+#define DMA_FLEXIBLE_TIM1_CH4       ((uint8_t)0x3B)
+#define DMA_FLEXIBLE_TIM2_TRIG      ((uint8_t)0x3D)
+#define DMA_FLEXIBLE_TIM2_UP        ((uint8_t)0x3F)
+#define DMA_FLEXIBLE_TIM2_CH1       ((uint8_t)0x40)
+#define DMA_FLEXIBLE_TIM2_CH2       ((uint8_t)0x41)
+#define DMA_FLEXIBLE_TIM2_CH3       ((uint8_t)0x42)
+#define DMA_FLEXIBLE_TIM2_CH4       ((uint8_t)0x43)
+#define DMA_FLEXIBLE_TIM3_TRIG      ((uint8_t)0x45)
+#define DMA_FLEXIBLE_TIM3_UP        ((uint8_t)0x47)
+#define DMA_FLEXIBLE_TIM3_CH1       ((uint8_t)0x48)
+#define DMA_FLEXIBLE_TIM3_CH2       ((uint8_t)0x49)
+#define DMA_FLEXIBLE_TIM3_CH3       ((uint8_t)0x4A)
+#define DMA_FLEXIBLE_TIM3_CH4       ((uint8_t)0x4B)
+#define DMA_FLEXIBLE_TIM4_TRIG      ((uint8_t)0x4D)
+#define DMA_FLEXIBLE_TIM4_UP        ((uint8_t)0x4F)
+#define DMA_FLEXIBLE_TIM4_CH1       ((uint8_t)0x50)
+#define DMA_FLEXIBLE_TIM4_CH2       ((uint8_t)0x51)
+#define DMA_FLEXIBLE_TIM4_CH3       ((uint8_t)0x52)
+#define DMA_FLEXIBLE_TIM4_CH4       ((uint8_t)0x53)
+#define DMA_FLEXIBLE_TIM5_TRIG      ((uint8_t)0x55)
+#define DMA_FLEXIBLE_TIM5_UP        ((uint8_t)0x57)
+#define DMA_FLEXIBLE_TIM5_CH1       ((uint8_t)0x58)
+#define DMA_FLEXIBLE_TIM5_CH2       ((uint8_t)0x59)
+#define DMA_FLEXIBLE_TIM5_CH3       ((uint8_t)0x5A)
+#define DMA_FLEXIBLE_TIM5_CH4       ((uint8_t)0x5B)
+#define DMA_FLEXIBLE_TIM6_UP        ((uint8_t)0x5F)
+#define DMA_FLEXIBLE_TIM7_UP        ((uint8_t)0x67)
+#define DMA_FLEXIBLE_TIM8_TRIG      ((uint8_t)0x6D)
+#define DMA_FLEXIBLE_TIM8_COM       ((uint8_t)0x6E)
+#define DMA_FLEXIBLE_TIM8_UP        ((uint8_t)0x6F)
+#define DMA_FLEXIBLE_TIM8_CH1       ((uint8_t)0x70)
+#define DMA_FLEXIBLE_TIM8_CH2       ((uint8_t)0x71)
+#define DMA_FLEXIBLE_TIM8_CH3       ((uint8_t)0x72)
+#define DMA_FLEXIBLE_TIM8_CH4       ((uint8_t)0x73)
+
+#define IS_DMA_ALL_HARDWARE_ID(HARDWARE_ID)     (((HARDWARE_ID) == DMA_FLEXIBLE_ADC1)     || ((HARDWARE_ID) == DMA_FLEXIBLE_ADC3)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_SPI1_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_SPI1_TX)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_SPI2_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_SPI2_TX)  || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_SPI3_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_SPI3_TX)  || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_SPI4_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_SPI4_TX)  || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_I2S2EXT_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_I2S2EXT_TX)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_I2S3EXT_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_I2S3EXT_TX)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_UART1_RX) || ((HARDWARE_ID) == DMA_FLEXIBLE_UART1_TX) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_UART2_RX) || ((HARDWARE_ID) == DMA_FLEXIBLE_UART2_TX) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_UART3_RX) || ((HARDWARE_ID) == DMA_FLEXIBLE_UART3_TX) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_UART4_RX) || ((HARDWARE_ID) == DMA_FLEXIBLE_UART4_TX) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_UART5_RX) || ((HARDWARE_ID) == DMA_FLEXIBLE_UART5_TX) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_UART6_RX) || ((HARDWARE_ID) == DMA_FLEXIBLE_UART6_TX) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_UART7_RX) || ((HARDWARE_ID) == DMA_FLEXIBLE_UART7_TX) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_UART8_RX) || ((HARDWARE_ID) == DMA_FLEXIBLE_UART8_TX) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_I2C1_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_I2C1_TX)  || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_I2C2_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_I2C2_TX)  || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_I2C3_RX)  || ((HARDWARE_ID) == DMA_FLEXIBLE_I2C3_TX)  || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_SDIO1)    || ((HARDWARE_ID) == DMA_FLEXIBLE_SDIO2)    || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM1_TRIG)|| ((HARDWARE_ID) == DMA_FLEXIBLE_TIM1_COM) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM1_UP)  || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM1_CH1) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM1_CH2) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM1_CH3) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM1_CH4) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM2_TRIG)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM2_UP)  || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM2_CH1) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM2_CH2) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM2_CH3) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM2_CH4) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM3_TRIG)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM3_UP)  || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM3_CH1) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM3_CH2) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM3_CH3) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM3_CH4) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM4_TRIG)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM4_UP)  || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM4_CH1) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM4_CH2) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM4_CH3) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM4_CH4) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM5_TRIG)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM5_UP)  || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM5_CH1) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM5_CH2) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM5_CH3) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM5_CH4) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM6_UP)  || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM7_UP)  || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM8_TRIG)|| \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM8_COM) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM8_UP)  || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM8_CH1) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM8_CH2) || \
+                                                 ((HARDWARE_ID) == DMA_FLEXIBLE_TIM8_CH3) || ((HARDWARE_ID) == DMA_FLEXIBLE_TIM8_CH4))
+
+#define DMA_FLEX_FUNCTION_EN                ((uint32_t)0X1000000)
+
+/** @defgroup DMA_data_transfer_direction
+  * @{
+  */
+
+#define DMA_DIR_PERIPHERALDST               ((uint32_t)0x00000010)
+#define DMA_DIR_PERIPHERALSRC               ((uint32_t)0x00000000)
+#define IS_DMA_DIR(DIR)                     (((DIR) == DMA_DIR_PERIPHERALDST) || \
+                                             ((DIR) == DMA_DIR_PERIPHERALSRC))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_peripheral_incremented_mode
+  * @{
+  */
+
+#define DMA_PERIPHERALINC_ENABLE            ((uint32_t)0x00000040)
+#define DMA_PERIPHERALINC_DISABLE           ((uint32_t)0x00000000)
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE)  (((STATE) == DMA_PERIPHERALINC_ENABLE) || \
+                                             ((STATE) == DMA_PERIPHERALINC_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_incremented_mode
+  * @{
+  */
+
+#define DMA_MEMORYINC_ENABLE                ((uint32_t)0x00000080)
+#define DMA_MEMORYINC_DISABLE               ((uint32_t)0x00000000)
+#define IS_DMA_MEMORY_INC_STATE(STATE)      (((STATE) == DMA_MEMORYINC_ENABLE) || \
+                                             ((STATE) == DMA_MEMORYINC_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_peripheral_data_size
+  * @{
+  */
+
+#define DMA_PERIPHERALDATAWIDTH_BYTE        ((uint32_t)0x00000000)
+#define DMA_PERIPHERALDATAWIDTH_HALFWORD    ((uint32_t)0x00000100)
+#define DMA_PERIPHERALDATAWIDTH_WORD        ((uint32_t)0x00000200)
+#define IS_DMA_PERIPHERAL_DATA_WIDTH(WIDTH) (((WIDTH) == DMA_PERIPHERALDATAWIDTH_BYTE) || \
+                                             ((WIDTH) == DMA_PERIPHERALDATAWIDTH_HALFWORD) || \
+                                             ((WIDTH) == DMA_PERIPHERALDATAWIDTH_WORD))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_data_size
+  * @{
+  */
+
+#define DMA_MEMORYDATAWIDTH_BYTE            ((uint32_t)0x00000000)
+#define DMA_MEMORYDATAWIDTH_HALFWORD        ((uint32_t)0x00000400)
+#define DMA_MEMORYDATAWIDTH_WORD            ((uint32_t)0x00000800)
+#define IS_DMA_MEMORY_DATA_WIDTH(WIDTH)     (((WIDTH) == DMA_MEMORYDATAWIDTH_BYTE) || \
+                                             ((WIDTH) == DMA_MEMORYDATAWIDTH_HALFWORD) || \
+                                             ((WIDTH) == DMA_MEMORYDATAWIDTH_WORD))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_circular_normal_mode
+  * @{
+  */
+
+#define DMA_MODE_CIRCULAR                   ((uint32_t)0x00000020)
+#define DMA_MODE_NORMAL                     ((uint32_t)0x00000000)
+#define IS_DMA_MODE(MODE)                   (((MODE) == DMA_MODE_CIRCULAR) || ((MODE) == DMA_MODE_NORMAL))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_priority_level
+  * @{
+  */
+
+#define DMA_PRIORITY_VERYHIGH               ((uint32_t)0x00003000)
+#define DMA_PRIORITY_HIGH                   ((uint32_t)0x00002000)
+#define DMA_PRIORITY_MEDIUM                 ((uint32_t)0x00001000)
+#define DMA_PRIORITY_LOW                    ((uint32_t)0x00000000)
+#define IS_DMA_PRIORITY(PRIORITY)           (((PRIORITY) == DMA_PRIORITY_VERYHIGH) || \
+                                             ((PRIORITY) == DMA_PRIORITY_HIGH) || \
+                                             ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                             ((PRIORITY) == DMA_PRIORITY_LOW))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_to_memory
+  * @{
+  */
+
+#define DMA_MEMTOMEM_ENABLE                 ((uint32_t)0x00004000)
+#define DMA_MEMTOMEM_DISABLE                ((uint32_t)0x00000000)
+#define IS_DMA_MTOM_STATE(STATE)            (((STATE) == DMA_MEMTOMEM_ENABLE) || ((STATE) == DMA_MEMTOMEM_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_interrupts_definition
+  * @{
+  */
+
+#define DMA_INT_TC                          ((uint32_t)0x00000002)
+#define DMA_INT_HT                          ((uint32_t)0x00000004)
+#define DMA_INT_ERR                         ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_INT(INT)              ((((INT) & 0xFFFFFFF1) == 0x00) && ((INT) != 0x00))
+
+#define DMA1_INT_GL1                        ((uint32_t)0x00000001)
+#define DMA1_INT_TC1                        ((uint32_t)0x00000002)
+#define DMA1_INT_HT1                        ((uint32_t)0x00000004)
+#define DMA1_INT_ERR1                       ((uint32_t)0x00000008)
+#define DMA1_INT_GL2                        ((uint32_t)0x00000010)
+#define DMA1_INT_TC2                        ((uint32_t)0x00000020)
+#define DMA1_INT_HT2                        ((uint32_t)0x00000040)
+#define DMA1_INT_ERR2                       ((uint32_t)0x00000080)
+#define DMA1_INT_GL3                        ((uint32_t)0x00000100)
+#define DMA1_INT_TC3                        ((uint32_t)0x00000200)
+#define DMA1_INT_HT3                        ((uint32_t)0x00000400)
+#define DMA1_INT_ERR3                       ((uint32_t)0x00000800)
+#define DMA1_INT_GL4                        ((uint32_t)0x00001000)
+#define DMA1_INT_TC4                        ((uint32_t)0x00002000)
+#define DMA1_INT_HT4                        ((uint32_t)0x00004000)
+#define DMA1_INT_ERR4                       ((uint32_t)0x00008000)
+#define DMA1_INT_GL5                        ((uint32_t)0x00010000)
+#define DMA1_INT_TC5                        ((uint32_t)0x00020000)
+#define DMA1_INT_HT5                        ((uint32_t)0x00040000)
+#define DMA1_INT_ERR5                       ((uint32_t)0x00080000)
+#define DMA1_INT_GL6                        ((uint32_t)0x00100000)
+#define DMA1_INT_TC6                        ((uint32_t)0x00200000)
+#define DMA1_INT_HT6                        ((uint32_t)0x00400000)
+#define DMA1_INT_ERR6                       ((uint32_t)0x00800000)
+#define DMA1_INT_GL7                        ((uint32_t)0x01000000)
+#define DMA1_INT_TC7                        ((uint32_t)0x02000000)
+#define DMA1_INT_HT7                        ((uint32_t)0x04000000)
+#define DMA1_INT_ERR7                       ((uint32_t)0x08000000)
+
+#define DMA2_INT_GL1                        ((uint32_t)0x10000001)
+#define DMA2_INT_TC1                        ((uint32_t)0x10000002)
+#define DMA2_INT_HT1                        ((uint32_t)0x10000004)
+#define DMA2_INT_ERR1                       ((uint32_t)0x10000008)
+#define DMA2_INT_GL2                        ((uint32_t)0x10000010)
+#define DMA2_INT_TC2                        ((uint32_t)0x10000020)
+#define DMA2_INT_HT2                        ((uint32_t)0x10000040)
+#define DMA2_INT_ERR2                       ((uint32_t)0x10000080)
+#define DMA2_INT_GL3                        ((uint32_t)0x10000100)
+#define DMA2_INT_TC3                        ((uint32_t)0x10000200)
+#define DMA2_INT_HT3                        ((uint32_t)0x10000400)
+#define DMA2_INT_ERR3                       ((uint32_t)0x10000800)
+#define DMA2_INT_GL4                        ((uint32_t)0x10001000)
+#define DMA2_INT_TC4                        ((uint32_t)0x10002000)
+#define DMA2_INT_HT4                        ((uint32_t)0x10004000)
+#define DMA2_INT_ERR4                       ((uint32_t)0x10008000)
+#define DMA2_INT_GL5                        ((uint32_t)0x10010000)
+#define DMA2_INT_TC5                        ((uint32_t)0x10020000)
+#define DMA2_INT_HT5                        ((uint32_t)0x10040000)
+#define DMA2_INT_ERR5                        ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_INT(INT)               (((((INT) & 0xF0000000) == 0x00) || (((INT) & 0xEFF00000) == 0x00)) && ((INT) != 0x00))
+
+#define IS_DMA_GET_INT(INT)                 (((INT) == DMA1_INT_GL1) || ((INT) == DMA1_INT_TC1) || \
+                                             ((INT) == DMA1_INT_HT1) || ((INT) == DMA1_INT_ERR1) || \
+                                             ((INT) == DMA1_INT_GL2) || ((INT) == DMA1_INT_TC2) || \
+                                             ((INT) == DMA1_INT_HT2) || ((INT) == DMA1_INT_ERR2) || \
+                                             ((INT) == DMA1_INT_GL3) || ((INT) == DMA1_INT_TC3) || \
+                                             ((INT) == DMA1_INT_HT3) || ((INT) == DMA1_INT_ERR3) || \
+                                             ((INT) == DMA1_INT_GL4) || ((INT) == DMA1_INT_TC4) || \
+                                             ((INT) == DMA1_INT_HT4) || ((INT) == DMA1_INT_ERR4) || \
+                                             ((INT) == DMA1_INT_GL5) || ((INT) == DMA1_INT_TC5) || \
+                                             ((INT) == DMA1_INT_HT5) || ((INT) == DMA1_INT_ERR5) || \
+                                             ((INT) == DMA1_INT_GL6) || ((INT) == DMA1_INT_TC6) || \
+                                             ((INT) == DMA1_INT_HT6) || ((INT) == DMA1_INT_ERR6) || \
+                                             ((INT) == DMA1_INT_GL7) || ((INT) == DMA1_INT_TC7) || \
+                                             ((INT) == DMA1_INT_HT7) || ((INT) == DMA1_INT_ERR7) || \
+                                             ((INT) == DMA2_INT_GL1) || ((INT) == DMA2_INT_TC1) || \
+                                             ((INT) == DMA2_INT_HT1) || ((INT) == DMA2_INT_ERR1) || \
+                                             ((INT) == DMA2_INT_GL2) || ((INT) == DMA2_INT_TC2) || \
+                                             ((INT) == DMA2_INT_HT2) || ((INT) == DMA2_INT_ERR2) || \
+                                             ((INT) == DMA2_INT_GL3) || ((INT) == DMA2_INT_TC3) || \
+                                             ((INT) == DMA2_INT_HT3) || ((INT) == DMA2_INT_ERR3) || \
+                                             ((INT) == DMA2_INT_GL4) || ((INT) == DMA2_INT_TC4) || \
+                                             ((INT) == DMA2_INT_HT4) || ((INT) == DMA2_INT_ERR4) || \
+                                             ((INT) == DMA2_INT_GL5) || ((INT) == DMA2_INT_TC5) || \
+                                             ((INT) == DMA2_INT_HT5) || ((INT) == DMA2_INT_ERR5))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flags_definition
+  * @{
+  */
+#define DMA1_FLAG_GL1                       ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1                       ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1                       ((uint32_t)0x00000004)
+#define DMA1_FLAG_ERR1                      ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2                       ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2                       ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2                       ((uint32_t)0x00000040)
+#define DMA1_FLAG_ERR2                      ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3                       ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3                       ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3                       ((uint32_t)0x00000400)
+#define DMA1_FLAG_ERR3                      ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4                       ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4                       ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4                       ((uint32_t)0x00004000)
+#define DMA1_FLAG_ERR4                      ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5                       ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5                       ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5                       ((uint32_t)0x00040000)
+#define DMA1_FLAG_ERR5                      ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6                       ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6                       ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6                       ((uint32_t)0x00400000)
+#define DMA1_FLAG_ERR6                      ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7                       ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7                       ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7                       ((uint32_t)0x04000000)
+#define DMA1_FLAG_ERR7                      ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1                       ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1                       ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1                       ((uint32_t)0x10000004)
+#define DMA2_FLAG_ERR1                      ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2                       ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2                       ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2                       ((uint32_t)0x10000040)
+#define DMA2_FLAG_ERR2                      ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3                       ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3                       ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3                       ((uint32_t)0x10000400)
+#define DMA2_FLAG_ERR3                      ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4                       ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4                       ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4                       ((uint32_t)0x10004000)
+#define DMA2_FLAG_ERR4                      ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5                       ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5                       ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5                       ((uint32_t)0x10040000)
+#define DMA2_FLAG_ERR5                      ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG)             (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG)               (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+                                             ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_ERR1) || \
+                                             ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+                                             ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_ERR2) || \
+                                             ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+                                             ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_ERR3) || \
+                                             ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+                                             ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_ERR4) || \
+                                             ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+                                             ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_ERR5) || \
+                                             ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+                                             ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_ERR6) || \
+                                             ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+                                             ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_ERR7) || \
+                                             ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
+                                             ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_ERR1) || \
+                                             ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
+                                             ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_ERR2) || \
+                                             ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
+                                             ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_ERR3) || \
+                                             ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
+                                             ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_ERR4) || \
+                                             ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
+                                             ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_ERR5))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Buffer_Size
+  * @{
+  */
+
+#define IS_DMA_BUFFER_SIZE(SIZE)            (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions
+  * @{
+  */
+
+void DMA_Reset(DMA_Channel_Type* DMAy_Channelx);
+void DMA_Init(DMA_Channel_Type* DMAy_Channelx, DMA_InitType* DMA_InitStruct);
+void DMA_DefaultInitParaConfig(DMA_InitType* DMA_InitStruct);
+void DMA_ChannelEnable(DMA_Channel_Type* DMAy_Channelx, FunctionalState NewState);
+void DMA_INTConfig(DMA_Channel_Type* DMAy_Channelx, uint32_t DMA_INT, FunctionalState NewState);
+void DMA_SetCurrDataCounter(DMA_Channel_Type* DMAy_Channelx, uint16_t DataNumber);
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_Type* DMAy_Channelx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMAy_INT);
+void DMA_ClearITPendingBit(uint32_t DMAy_INT);
+void DMA_Flexible_Config(DMA_Type *DMAx,uint8_t Flex_Channelx,uint8_t Hardware_ID);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4xx_DMA_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_ertc.h

@@ -0,0 +1,864 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_ertc.h
+ * Description  : at32f4xx ERTC header file
+ * Date         : 2018-03-15
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_ERTC_H
+#define __AT32F4xx_ERTC_H
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ERTC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  ERTC Init structures definition  
+  */ 
+typedef struct
+{
+  uint32_t ERTC_HourFormat;   /*!< Specifies the ERTC Hour Format.
+                             This parameter can be a value of @ref RTC_Hour_Formats */
+  
+  uint32_t ERTC_AsynchPrediv; /*!< Specifies the ERTC Asynchronous Predivider value.
+                             This parameter must be set to a value lower than 0x7F */
+  
+  uint32_t ERTC_SynchPrediv;  /*!< Specifies the ERTC Synchronous Predivider value.
+                             This parameter must be set to a value lower than 0x7FFF */
+}ERTC_InitType;
+
+/** 
+  * @brief  ERTC Time structure definition  
+  */
+typedef struct
+{
+  uint8_t ERTC_Hours;    /*!< Specifies the ERTC Time Hour.
+                        This parameter must be set to a value in the 0-12 range
+                        if the ERTC_HourFormat_12 is selected or 0-23 range if
+                        the ERTC_HourFormat_24 is selected. */
+
+  uint8_t ERTC_Minutes;  /*!< Specifies the ERTC Time Minutes.
+                        This parameter must be set to a value in the 0-59 range. */
+  
+  uint8_t ERTC_Seconds;  /*!< Specifies the ERTC Time Seconds.
+                        This parameter must be set to a value in the 0-59 range. */
+
+  uint8_t ERTC_AMPM;      /*!< Specifies the ERTC AM/PM Time.
+                        This parameter can be a value of @ref RTC_AM_PM_Definitions */
+}ERTC_TimeType; 
+
+/** 
+  * @brief  ERTC Date structure definition  
+  */
+typedef struct
+{
+  uint8_t ERTC_WeekDay; /*!< Specifies the ERTC Date WeekDay.
+                        This parameter can be a value of @ref RTC_WeekDay_Definitions */
+  
+  uint8_t ERTC_Month;   /*!< Specifies the ERTC Date Month (in BCD format).
+                        This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+  uint8_t ERTC_Date;     /*!< Specifies the ERTC Date.
+                        This parameter must be set to a value in the 1-31 range. */
+  
+  uint8_t ERTC_Year;     /*!< Specifies the ERTC Date Year.
+                        This parameter must be set to a value in the 0-99 range. */
+}ERTC_DateType;
+
+/** 
+  * @brief  ERTC Alarm structure definition  
+  */
+typedef struct
+{
+  ERTC_TimeType ERTC_AlarmTime;     /*!< Specifies the ERTC Alarm Time members. */
+
+  uint32_t ERTC_AlarmMask;            /*!< Specifies the ERTC Alarm Masks.
+                                     This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+  uint32_t ERTC_AlarmDateWeekSel;  /*!< Specifies the ERTC Alarm is on Date or WeekDay.
+                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+  
+  uint8_t ERTC_AlarmDateWeek;      /*!< Specifies the ERTC Alarm Date/WeekDay.
+                                     If the Alarm Date is selected, this parameter
+                                     must be set to a value in the 1-31 range.
+                                     If the Alarm WeekDay is selected, this 
+                                     parameter can be a value of @ref RTC_WeekDay_Definitions */
+}ERTC_AlarmType;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RTC_Exported_Constants
+  * @{
+  */ 
+
+
+/** @defgroup RTC_Hour_Formats 
+  * @{
+  */ 
+#define ERTC_HourFormat_24              ((uint32_t)0x00000000)
+#define ERTC_HourFormat_12              ((uint32_t)0x00000040)
+#define IS_ERTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == ERTC_HourFormat_12) || \
+                                         ((FORMAT) == ERTC_HourFormat_24))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Asynchronous_Predivider 
+  * @{
+  */ 
+#define IS_ERTC_ASYNCH_PRDIV(PRDIV)   ((PRDIV) <= 0x7F)
+ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Synchronous_Predivider 
+  * @{
+  */ 
+#define IS_ERTC_SYNCH_PRDIV(PRDIV)    ((PRDIV) <= 0x7FFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Time_Definitions 
+  * @{
+  */ 
+#define IS_ERTC_HOUR12(HOUR)            (((HOUR) > 0) && ((HOUR) <= 12))
+#define IS_ERTC_HOUR24(HOUR)            ((HOUR) <= 23)
+#define IS_ERTC_MINUTES(MINUTES)        ((MINUTES) <= 59)
+#define IS_ERTC_SECONDS(SECONDS)        ((SECONDS) <= 59)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_AM_PM_Definitions 
+  * @{
+  */ 
+#define ERTC_H12_AM                     ((uint8_t)0x00)
+#define ERTC_H12_PM                     ((uint8_t)0x40)
+#define IS_ERTC_H12(AMPM) (((AMPM) == ERTC_H12_AM) || ((AMPM) == ERTC_H12_PM))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Year_Date_Definitions 
+  * @{
+  */ 
+#define IS_ERTC_YEAR(YEAR)              ((YEAR) <= 99)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Month_Date_Definitions 
+  * @{
+  */ 
+
+/* Coded in BCD format */
+#define ERTC_Month_JAN                  ((uint8_t)0x01)
+#define ERTC_Month_FEB                  ((uint8_t)0x02)
+#define ERTC_Month_MAR                  ((uint8_t)0x03)
+#define ERTC_Month_APR                  ((uint8_t)0x04)
+#define ERTC_Month_MAY                  ((uint8_t)0x05)
+#define ERTC_Month_JUN                  ((uint8_t)0x06)
+#define ERTC_Month_JUL                  ((uint8_t)0x07)
+#define ERTC_Month_AUG                  ((uint8_t)0x08)
+#define ERTC_Month_SEP                  ((uint8_t)0x09)
+#define ERTC_Month_OCT                  ((uint8_t)0x10)
+#define ERTC_Month_NOV                  ((uint8_t)0x11)
+#define ERTC_Month_DEC                  ((uint8_t)0x12)
+#define IS_ERTC_MONTH(MONTH)            (((MONTH) >= 1) && ((MONTH) <= 12))
+#define IS_ERTC_DATE(DATE)              (((DATE) >= 1) && ((DATE) <= 31))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_WeekDay_Definitions 
+  * @{
+  */ 
+  
+#define ERTC_Week_MON                   ((uint8_t)0x01)
+#define ERTC_Week_TUES                  ((uint8_t)0x02)
+#define ERTC_Week_WED                   ((uint8_t)0x03)
+#define ERTC_Week_THUR                  ((uint8_t)0x04)
+#define ERTC_Week_FRI                   ((uint8_t)0x05)
+#define ERTC_Week_SAT                   ((uint8_t)0x06)
+#define ERTC_Week_SUN                   ((uint8_t)0x07)
+#define IS_ERTC_WEEK(WEEK)      (((WEEK) == ERTC_Week_MON) || \
+                                 ((WEEK) == ERTC_Week_TUES) || \
+                                 ((WEEK) == ERTC_Week_WED) || \
+                                 ((WEEK) == ERTC_Week_THUR) || \
+                                 ((WEEK) == ERTC_Week_FRI) || \
+                                 ((WEEK) == ERTC_Week_SAT) || \
+                                 ((WEEK) == ERTC_Week_SUN))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Alarm_Definitions
+  * @{
+  */ 
+#define IS_ERTC_ALARM_DATE_WEEK_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+#define IS_ERTC_ALARM_DATE_WEEK_WEEK(WEEK) (((WEEK) == ERTC_Week_MON) || \
+                                                    ((WEEK) == ERTC_Week_TUES) || \
+                                                    ((WEEK) == ERTC_Week_WED) || \
+                                                    ((WEEK) == ERTC_Week_THUR) || \
+                                                    ((WEEK) == ERTC_Week_FRI) || \
+                                                    ((WEEK) == ERTC_Week_SAT) || \
+                                                    ((WEEK) == ERTC_Week_SUN))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions 
+  * @{
+  */ 
+#define ERTC_AlarmDateWeekSel_Date       ((uint32_t)0x00000000)
+#define ERTC_AlarmDateWeekSel_Week       ((uint32_t)0x40000000)
+
+#define IS_ERTC_ALARM_DATE_WEEK_SEL(SEL) (((SEL) == ERTC_AlarmDateWeekSel_Date) || \
+                                            ((SEL) == ERTC_AlarmDateWeekSel_Week))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_AlarmMask_Definitions 
+  * @{
+  */ 
+#define ERTC_AlarmMask_None                ((uint32_t)0x00000000)
+#define ERTC_AlarmMask_DateWeek            ((uint32_t)0x80000000)
+#define ERTC_AlarmMask_Hours               ((uint32_t)0x00800000)
+#define ERTC_AlarmMask_Minutes             ((uint32_t)0x00008000)
+#define ERTC_AlarmMask_Seconds             ((uint32_t)0x00000080)
+#define ERTC_AlarmMask_All                 ((uint32_t)0x80808080)
+#define IS_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarms_Definitions 
+  * @{
+  */ 
+#define ERTC_AlA                       ((uint32_t)0x00000100)
+#define ERTC_AlB                       ((uint32_t)0x00000200)
+#define IS_ERTC_ALARM(ALARM)     (((ALARM) == ERTC_AlA) || ((ALARM) == ERTC_AlB))
+#define IS_ERTC_CMD_ALARM(ALARM) (((ALARM) & (ERTC_AlA | ERTC_AlB)) != (uint32_t)RESET)
+
+/**
+  * @}
+  */ 
+
+  /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+  * @{
+  */ 
+#define ERTC_AlarmSubSecondMask_All          ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. 
+                                                                       There is no comparison on sub seconds 
+                                                                       for Alarm */
+#define ERTC_AlarmSubSecondMask_SBS14_1      ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm 
+                                                                       comparison. Only SS[0] is compared. */
+#define ERTC_AlarmSubSecondMask_SBS14_2      ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm 
+                                                                       comparison. Only SS[1:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_3      ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm 
+                                                                       comparison. Only SS[2:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_4      ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm 
+                                                                       comparison. Only SS[3:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_5      ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm 
+                                                                       comparison. Only SS[4:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_6      ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm 
+                                                                       comparison. Only SS[5:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_7      ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm 
+                                                                       comparison. Only SS[6:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_8      ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm 
+                                                                       comparison. Only SS[7:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_9      ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm 
+                                                                       comparison. Only SS[8:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_10     ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm 
+                                                                       comparison. Only SS[9:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_11     ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm 
+                                                                       comparison. Only SS[10:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_12     ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm 
+                                                                       comparison.Only SS[11:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14_13     ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm 
+                                                                       comparison. Only SS[12:0] are compared */
+#define ERTC_AlarmSubSecondMask_SBS14        ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm 
+                                                                       comparison.Only SS[13:0] are compared */
+#define ERTC_AlarmSubSecondMask_None         ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match 
+                                                                       to activate alarm. */
+#define IS_ERTC_ALARM_SUB_SECOND_MASK(MASK)  (((MASK) == ERTC_AlarmSubSecondMask_All) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_1) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_2) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_3) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_4) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_5) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_6) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_7) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_8) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_9) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_10) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_11) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_12) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14_13) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_SBS14) || \
+                                              ((MASK) == ERTC_AlarmSubSecondMask_None))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Value
+  * @{
+  */ 
+
+#define IS_ERTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Wakeup_Timer_Definitions 
+  * @{
+  */ 
+#define ERTC_WakeUpClockSelect_RTCCLK_Div16        ((uint32_t)0x00000000)
+#define ERTC_WakeUpClockSelect_RTCCLK_Div8         ((uint32_t)0x00000001)
+#define ERTC_WakeUpClockSelect_RTCCLK_Div4         ((uint32_t)0x00000002)
+#define ERTC_WakeUpClockSelect_RTCCLK_Div2         ((uint32_t)0x00000003)
+#define ERTC_WakeUpClockSelect_CK_SPRE_16bits      ((uint32_t)0x00000004)
+#define ERTC_WakeUpClockSelect_CK_SPRE_17bits      ((uint32_t)0x00000006)
+#define IS_ERTC_WAKEUP_CLOCK_SELECT(CLOCK) (((CLOCK) == ERTC_WakeUpClockSelect_RTCCLK_Div16) || \
+                                    ((CLOCK) == ERTC_WakeUpClockSelect_RTCCLK_Div8) || \
+                                    ((CLOCK) == ERTC_WakeUpClockSelect_RTCCLK_Div4) || \
+                                    ((CLOCK) == ERTC_WakeUpClockSelect_RTCCLK_Div2) || \
+                                    ((CLOCK) == ERTC_WakeUpClockSelect_CK_SPRE_16bits) || \
+                                    ((CLOCK) == ERTC_WakeUpClockSelect_CK_SPRE_17bits))
+#define IS_ERTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Time_Stamp_Edges_definitions 
+  * @{
+  */ 
+#define ERTC_TimeStampEdge_Rising          ((uint32_t)0x00000000)
+#define ERTC_TimeStampEdge_Falling         ((uint32_t)0x00000008)
+#define IS_ERTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == ERTC_TimeStampEdge_Rising) || \
+                                     ((EDGE) == ERTC_TimeStampEdge_Falling))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_selection_Definitions 
+  * @{
+  */ 
+#define ERTC_Output_Disable             ((uint32_t)0x00000000)
+#define ERTC_Output_AlarmA              ((uint32_t)0x00200000)
+#define ERTC_Output_AlarmB              ((uint32_t)0x00400000)
+#define ERTC_Output_WakeUp              ((uint32_t)0x00600000)
+ 
+#define IS_ERTC_OUTPUT(OUTPUT) (((OUTPUT) == ERTC_Output_Disable) || \
+                               ((OUTPUT) == ERTC_Output_AlarmA) || \
+                               ((OUTPUT) == ERTC_Output_AlarmB) || \
+                               ((OUTPUT) == ERTC_Output_WakeUp))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_Polarity_Definitions 
+  * @{
+  */ 
+#define ERTC_OutputPolarity_High           ((uint32_t)0x00000000)
+#define ERTC_OutputPolarity_Low            ((uint32_t)0x00100000)
+#define IS_ERTC_OUTPUT_OPOL(OPOL) (((OPOL) == ERTC_OutputPolarity_High) || \
+                                ((OPOL) == ERTC_OutputPolarity_Low))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Digital_Calibration_Definitions 
+  * @{
+  */ 
+#define ERTC_DataCalSign_Positive            ((uint32_t)0x00000000) 
+#define ERTC_DataCalSign_Negative            ((uint32_t)0x00000080)
+#define IS_ERTC_DATACAL_SIGN(SIGN) (((SIGN) == ERTC_DataCalSign_Positive) || \
+                                 ((SIGN) == ERTC_DataCalSign_Negative))
+#define IS_ERTC_DATACAL_VALUE(VALUE) ((VALUE) < 0x20)
+
+/**
+  * @}
+  */ 
+
+ /** @defgroup RTC_Calib_Output_selection_Definitions 
+  * @{
+  */ 
+#define ERTC_CalOutput_512Hz            ((uint32_t)0x00000000) 
+#define ERTC_CalOutput_1Hz              ((uint32_t)0x00080000)
+#define IS_ERTC_CAL_OUTPUT(OUTPUT)  (((OUTPUT) == ERTC_CalOutput_512Hz) || \
+                                      ((OUTPUT) == ERTC_CalOutput_1Hz))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_period_Definitions 
+  * @{
+  */ 
+#define ERTC_SmoothCalPeriod_32sec   ((uint32_t)0x00000000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
+                                                             period is 32s,  else 2exp20 RTCCLK seconds */
+#define ERTC_SmoothCalPeriod_16sec   ((uint32_t)0x00002000) /*!<  if RTCCLK = 32768 Hz, Smooth calibration 
+                                                             period is 16s, else 2exp19 RTCCLK seconds */
+#define ERTC_SmoothCalPeriod_8sec    ((uint32_t)0x00004000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
+                                                             period is 8s, else 2exp18 RTCCLK seconds */
+#define IS_ERTC_SMOOTH_CAL_PERIOD(PERIOD) (((PERIOD) == ERTC_SmoothCalPeriod_32sec) || \
+                                             ((PERIOD) == ERTC_SmoothCalPeriod_16sec) || \
+                                             ((PERIOD) == ERTC_SmoothCalPeriod_8sec))
+                                          
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions 
+  * @{
+  */ 
+#define ERTC_SmoothCalAddPulses_Set    ((uint32_t)0x00008000) /*!<  The number of RTCCLK pulses added  
+                                                                during a X -second window = Y - CALM[8:0]. 
+                                                                 with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define ERTC_SmoothCalAddPulses_Reset  ((uint32_t)0x00000000) /*!<  The number of RTCCLK pulses subbstited
+                                                                 during a 32-second window =   CALM[8:0]. */
+#define IS_ERTC_SMOOTH_CAL_ADD(ADD) (((ADD) == ERTC_SmoothCalAddPulses_Set) || \
+                                         ((ADD) == ERTC_SmoothCalAddPulses_Reset))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions 
+  * @{
+  */ 
+#define  IS_ERTC_SMOOTH_CAL_VALUE(VALUE) ((VALUE) <= 0x000001FF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_DayLightSaving_Definitions 
+  * @{
+  */ 
+#define ERTC_DayLightSaving_SUB1H   ((uint32_t)0x00020000)
+#define ERTC_DayLightSaving_ADD1H   ((uint32_t)0x00010000)
+#define IS_ERTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == ERTC_DayLightSaving_SUB1H) || \
+                                      ((SAVE) == ERTC_DayLightSaving_ADD1H))
+
+#define ERTC_StoreOperation_Reset        ((uint32_t)0x00000000)
+#define ERTC_StoreOperation_Set          ((uint32_t)0x00040000)
+#define IS_ERTC_STORE_OPERATION(OPERATION) (((OPERATION) == ERTC_StoreOperation_Reset) || \
+                                           ((OPERATION) == ERTC_StoreOperation_Set))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Trigger_Definitions 
+  * @{
+  */ 
+#define ERTC_TamperTrig_RisingEdge            ((uint32_t)0x00000000)
+#define ERTC_TamperTrig_FallingEdge           ((uint32_t)0x00000001)
+#define ERTC_TamperTrig_LowLevel              ((uint32_t)0x00000000)
+#define ERTC_TamperTrig_HighLevel             ((uint32_t)0x00000001)
+#define IS_ERTC_TAMPER_TRIG(TRIG) (((TRIG) == ERTC_TamperTrig_RisingEdge) || \
+                                        ((TRIG) == ERTC_TamperTrig_FallingEdge) || \
+                                        ((TRIG) == ERTC_TamperTrig_LowLevel) || \
+                                        ((TRIG) == ERTC_TamperTrig_HighLevel)) 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Filter_Definitions 
+  * @{
+  */ 
+#define ERTC_TamperFilter_Disable   ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define ERTC_TamperFilter_2Sample   ((uint32_t)0x00000800) /*!< Tamper is activated after 2 
+                                                          consecutive samples at the active level */
+#define ERTC_TamperFilter_4Sample   ((uint32_t)0x00001000) /*!< Tamper is activated after 4 
+                                                          consecutive samples at the active level */
+#define ERTC_TamperFilter_8Sample   ((uint32_t)0x00001800) /*!< Tamper is activated after 8 
+                                                          consecutive samples at the active level. */
+#define IS_ERTC_TAMPER_FILTER(FILTER) (((FILTER) == ERTC_TamperFilter_Disable) || \
+                                      ((FILTER) == ERTC_TamperFilter_2Sample) || \
+                                      ((FILTER) == ERTC_TamperFilter_4Sample) || \
+                                      ((FILTER) == ERTC_TamperFilter_8Sample))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions 
+  * @{
+  */ 
+#define ERTC_TamperSamplingFreq_CLK_Div32768  ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 32768 */
+#define ERTC_TamperSamplingFreq_CLK_Div16384  ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
+                                                                            with a frequency =  RTCCLK / 16384 */
+#define ERTC_TamperSamplingFreq_CLK_Div8192   ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 8192  */
+#define ERTC_TamperSamplingFreq_CLK_Div4096   ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 4096  */
+#define ERTC_TamperSamplingFreq_CLK_Div2048   ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 2048  */
+#define ERTC_TamperSamplingFreq_CLK_Div1024   ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 1024  */
+#define ERTC_TamperSamplingFreq_CLK_Div512    ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 512   */
+#define ERTC_TamperSamplingFreq_CLK_Div256    ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 256   */
+#define IS_ERTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==ERTC_TamperSamplingFreq_CLK_Div32768) || \
+                                           ((FREQ) ==ERTC_TamperSamplingFreq_CLK_Div16384) || \
+                                           ((FREQ) ==ERTC_TamperSamplingFreq_CLK_Div8192) || \
+                                           ((FREQ) ==ERTC_TamperSamplingFreq_CLK_Div4096) || \
+                                           ((FREQ) ==ERTC_TamperSamplingFreq_CLK_Div2048) || \
+                                           ((FREQ) ==ERTC_TamperSamplingFreq_CLK_Div1024) || \
+                                           ((FREQ) ==ERTC_TamperSamplingFreq_CLK_Div512) || \
+                                           ((FREQ) ==ERTC_TamperSamplingFreq_CLK_Div256))
+
+/**
+  * @}
+  */
+
+  /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions 
+  * @{
+  */ 
+#define ERTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 1 RTCCLK cycle */
+#define ERTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 2 RTCCLK cycles */
+#define ERTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 4 RTCCLK cycles */
+#define ERTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 8 RTCCLK cycles */
+
+#define IS_ERTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == ERTC_TamperPrechargeDuration_1RTCCLK) || \
+                                                    ((DURATION) == ERTC_TamperPrechargeDuration_2RTCCLK) || \
+                                                    ((DURATION) == ERTC_TamperPrechargeDuration_4RTCCLK) || \
+                                                    ((DURATION) == ERTC_TamperPrechargeDuration_8RTCCLK))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Pins_Definitions 
+  * @{
+  */ 
+#define ERTC_TAMP_1 ERTC_TPAF_TM1E
+#define ERTC_TAMP_2 ERTC_TPAF_TM2E
+#define IS_ERTC_TAMP(TAMP) (((TAMP) == ERTC_TAMP_1) || ((TAMP) == ERTC_TAMP_2))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Pin_Selection 
+  * @{
+  */ 
+#define ERTC_TAMPPIN_Default       ((uint32_t)0x00000000)
+#define ERTC_TAMPPIN_Pos1          ((uint32_t)0x00010000)
+#define IS_ERTC_TAMP_PIN(PIN)      (((PIN) == ERTC_TAMPPIN_Default) || \
+                                    ((PIN) == ERTC_TAMPPIN_Pos1))
+/* Legacy Defines */
+#define ERTC_TAMPPIN_PC13           ERTC_TAMPPIN_Default
+#define ERTC_TAMPPIN_PI8            ERTC_TAMPPIN_Pos1
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_TimeStamp_Pin_Selection 
+  * @{
+  */ 
+#define ERTC_TimeStampPin_PC13              ((uint32_t)0x00000000)
+#define ERTC_TimeStampPin_PI8               ((uint32_t)0x00020000)
+#define IS_ERTC_TIMESTAMP_PIN(PIN) (((PIN) == ERTC_TimeStampPin_PC13) || \
+                                   ((PIN) == ERTC_TimeStampPin_PI8))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_Type_ALARM_OUT 
+  * @{
+  */ 
+#define ERTC_OutputType_OpenDrain           ((uint32_t)0x00000000)
+#define ERTC_OutputType_PushPull            ((uint32_t)0x00040000)
+#define IS_ERTC_OUTPUT_TYPE(TYPE) (((TYPE) == ERTC_OutputType_OpenDrain) || \
+                                  ((TYPE) == ERTC_OutputType_PushPull))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Add_1_Second_Parameter_Definitions
+  * @{
+  */ 
+#define ERTC_ShiftAdd1S_Reset      ((uint32_t)0x00000000)
+#define ERTC_ShiftAdd1S_Set        ((uint32_t)0x80000000)
+#define IS_ERTC_SHIFT_ADD1S(SEL) (((SEL) == ERTC_ShiftAdd1S_Reset) || \
+                                 ((SEL) == ERTC_ShiftAdd1S_Set))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Substract_Fraction_Of_Second_Value
+  * @{
+  */ 
+#define IS_ERTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Backup_Registers_Definitions 
+  * @{
+  */
+
+#define ERTC_BKP_DT0                       ((uint32_t)0x00000000)
+#define ERTC_BKP_DT1                       ((uint32_t)0x00000001)
+#define ERTC_BKP_DT2                       ((uint32_t)0x00000002)
+#define ERTC_BKP_DT3                       ((uint32_t)0x00000003)
+#define ERTC_BKP_DT4                       ((uint32_t)0x00000004)
+#define ERTC_BKP_DT5                       ((uint32_t)0x00000005)
+#define ERTC_BKP_DT6                       ((uint32_t)0x00000006)
+#define ERTC_BKP_DT7                       ((uint32_t)0x00000007)
+#define ERTC_BKP_DT8                       ((uint32_t)0x00000008)
+#define ERTC_BKP_DT9                       ((uint32_t)0x00000009)
+#define ERTC_BKP_DT10                      ((uint32_t)0x0000000A)
+#define ERTC_BKP_DT11                      ((uint32_t)0x0000000B)
+#define ERTC_BKP_DT12                      ((uint32_t)0x0000000C)
+#define ERTC_BKP_DT13                      ((uint32_t)0x0000000D)
+#define ERTC_BKP_DT14                      ((uint32_t)0x0000000E)
+#define ERTC_BKP_DT15                      ((uint32_t)0x0000000F)
+#define ERTC_BKP_DT16                      ((uint32_t)0x00000010)
+#define ERTC_BKP_DT17                      ((uint32_t)0x00000011)
+#define ERTC_BKP_DT18                      ((uint32_t)0x00000012)
+#define ERTC_BKP_DT19                      ((uint32_t)0x00000013)
+#define IS_ERTC_BKP(BKP)                  (((BKP) == ERTC_BKP_DT0) || \
+                                           ((BKP) == ERTC_BKP_DT1) || \
+                                           ((BKP) == ERTC_BKP_DT2) || \
+                                           ((BKP) == ERTC_BKP_DT3) || \
+                                           ((BKP) == ERTC_BKP_DT4) || \
+                                           ((BKP) == ERTC_BKP_DT5) || \
+                                           ((BKP) == ERTC_BKP_DT6) || \
+                                           ((BKP) == ERTC_BKP_DT7) || \
+                                           ((BKP) == ERTC_BKP_DT8) || \
+                                           ((BKP) == ERTC_BKP_DT9) || \
+                                           ((BKP) == ERTC_BKP_DT10) || \
+                                           ((BKP) == ERTC_BKP_DT11) || \
+                                           ((BKP) == ERTC_BKP_DT12) || \
+                                           ((BKP) == ERTC_BKP_DT13) || \
+                                           ((BKP) == ERTC_BKP_DT14) || \
+                                           ((BKP) == ERTC_BKP_DT15) || \
+                                           ((BKP) == ERTC_BKP_DT16) || \
+                                           ((BKP) == ERTC_BKP_DT17) || \
+                                           ((BKP) == ERTC_BKP_DT18) || \
+                                           ((BKP) == ERTC_BKP_DT19))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Input_parameter_format_definitions 
+  * @{
+  */ 
+#define ERTC_Format_BIN                    ((uint32_t)0x000000000)
+#define ERTC_Format_BCD                    ((uint32_t)0x000000001)
+#define IS_ERTC_FORMAT(FORMAT) (((FORMAT) == ERTC_Format_BIN) || ((FORMAT) == ERTC_Format_BCD))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Flags_Definitions 
+  * @{
+  */ 
+#define ERTC_FLAG_RECALPDF                 ((uint32_t)0x00010000)
+#define ERTC_FLAG_TP1F                     ((uint32_t)0x00002000)
+#define ERTC_FLAG_TP2F                     ((uint32_t)0x00004000) 
+#define ERTC_FLAG_TSOF                     ((uint32_t)0x00001000)
+#define ERTC_FLAG_TSF                      ((uint32_t)0x00000800)
+#define ERTC_FLAG_WATF                     ((uint32_t)0x00000400)
+#define ERTC_FLAG_ALBF                     ((uint32_t)0x00000200)
+#define ERTC_FLAG_ALAF                     ((uint32_t)0x00000100)
+#define ERTC_FLAG_INITF                    ((uint32_t)0x00000040)
+#define ERTC_FLAG_RSF                      ((uint32_t)0x00000020)
+#define ERTC_FLAG_INITS                    ((uint32_t)0x00000010)
+#define ERTC_FLAG_SFP                      ((uint32_t)0x00000008)
+#define ERTC_FLAG_WATWF                    ((uint32_t)0x00000004)
+#define ERTC_FLAG_ALBWF                    ((uint32_t)0x00000002)
+#define ERTC_FLAG_ALAWF                    ((uint32_t)0x00000001)
+#define IS_ERTC_GET_FLAG(FLAG) (((FLAG) == ERTC_FLAG_TSOF) || ((FLAG) == ERTC_FLAG_TSF) || \
+                                ((FLAG) == ERTC_FLAG_WATF) || ((FLAG) == ERTC_FLAG_ALBF) || \
+                                ((FLAG) == ERTC_FLAG_ALAF) || ((FLAG) == ERTC_FLAG_INITF) || \
+                                ((FLAG) == ERTC_FLAG_RSF) || ((FLAG) == ERTC_FLAG_WATWF) || \
+                                ((FLAG) == ERTC_FLAG_ALBWF) || ((FLAG) == ERTC_FLAG_ALAWF) || \
+                                ((FLAG) == ERTC_FLAG_TP1F) || ((FLAG) == ERTC_FLAG_RECALPDF) || \
+                                ((FLAG) == ERTC_FLAG_TP2F) ||((FLAG) == ERTC_FLAG_SFP))
+#define IS_ERTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Interrupts_Definitions 
+  * @{
+  */ 
+#define ERTC_INT_TS                         ((uint32_t)0x00008000)
+#define ERTC_INT_WAT                        ((uint32_t)0x00004000)
+#define ERTC_INT_ALB                        ((uint32_t)0x00002000)
+#define ERTC_INT_ALA                        ((uint32_t)0x00001000)
+#define ERTC_INT_TAMP                       ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+#define ERTC_INT_TAMP1                      ((uint32_t)0x00020000)
+#define ERTC_INT_TAMP2                      ((uint32_t)0x00040000)
+
+#define IS_ERTC_CONFIG_INT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
+#define IS_ERTC_GET_INT(IT) (((IT) == ERTC_INT_TS) || ((IT) == ERTC_INT_WAT) || \
+                           ((IT) == ERTC_INT_ALB) || ((IT) == ERTC_INT_ALA) || \
+                           ((IT) == ERTC_INT_TAMP1) || ((IT) == ERTC_INT_TAMP2))
+#define IS_ERTC_CLEAR_INT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF90FFF) == (uint32_t)RESET))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Legacy 
+  * @{
+  */ 
+#define ERTC_DigitalCalConfig  ERTC_CoarseCalConfig
+#define ERTC_DigitalCalCmd     ERTC_CoarseCalCmd
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the ERTC configuration to the default reset state *****/
+ErrorStatus ERTC_Reset(void);
+
+/* Initialization and Configuration functions *********************************/
+ErrorStatus ERTC_Init(ERTC_InitType* ERTC_InitStruct);
+void ERTC_StructInit(ERTC_InitType* ERTC_InitStruct);
+void ERTC_WriteProtectionCmd(FunctionalState NewState);
+ErrorStatus ERTC_EnterInitMode(void);
+void ERTC_ExitInitMode(void);
+ErrorStatus ERTC_WaitForSynchro(void);
+ErrorStatus ERTC_RefClockCmd(FunctionalState NewState);
+void ERTC_BypassShadowCmd(FunctionalState NewState);
+
+/* Time and Date configuration functions **************************************/
+ErrorStatus ERTC_SetTimeValue(uint32_t ERTC_Format, ERTC_TimeType* ERTC_TimeStruct);
+void ERTC_TimeStructInit(ERTC_TimeType* ERTC_TimeStruct);
+void ERTC_GetTimeValue(uint32_t ERTC_Format, ERTC_TimeType* ERTC_TimeStruct);
+uint32_t ERTC_GetSubSecondValue(void);
+ErrorStatus ERTC_SetDateValue(uint32_t ERTC_Format, ERTC_DateType* ERTC_DateStruct);
+void ERTC_DateStructInit(ERTC_DateType* ERTC_DateStruct);
+void ERTC_GetDateValue(uint32_t ERTC_Format, ERTC_DateType* ERTC_DateStruct);
+
+/* Alarms (Alarm A and Alarm B) configuration functions  **********************/
+void ERTC_SetAlarmValue(uint32_t ERTC_Format, uint32_t ERTC_Alarm, ERTC_AlarmType* ERTC_AlarmStruct);
+void ERTC_AlarmStructInit(ERTC_AlarmType* ERTC_AlarmStruct);
+void ERTC_GetAlarmValue(uint32_t ERTC_Format, uint32_t ERTC_Alarm, ERTC_AlarmType* ERTC_AlarmStruct);
+ErrorStatus ERTC_AlarmCmd(uint32_t ERTC_Alarm, FunctionalState NewState);
+void ERTC_AlarmSubSecondConfig(uint32_t ERTC_Alarm, uint32_t ERTC_AlarmSubSecondValue, uint32_t ERTC_AlarmSubSecondMask);
+uint32_t ERTC_GetAlarmSubSecond(uint32_t ERTC_Alarm);
+
+/* WakeUp Timer configuration functions ***************************************/
+void ERTC_WakeUpClockConfig(uint32_t ERTC_WakeUpClock);
+void ERTC_SetWakeUpCounter(uint32_t ERTC_WakeUpCounter);
+uint32_t ERTC_GetWakeUpCounter(void);
+ErrorStatus ERTC_WakeUpCmd(FunctionalState NewState);
+
+/* Daylight Saving configuration functions ************************************/
+void ERTC_DayLightSavingConfig(uint32_t ERTC_DayLightSaving, uint32_t ERTC_StoreOperation);
+uint32_t ERTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/
+void ERTC_OutputConfig(uint32_t ERTC_Output, uint32_t ERTC_OutputPolarity);
+
+/* Digital Calibration configuration functions *********************************/
+ErrorStatus ERTC_CoarseCalConfig(uint32_t ERTC_CalSign, uint32_t Value);
+ErrorStatus ERTC_CoarseCalCmd(FunctionalState NewState);
+void ERTC_CalOutputCmd(FunctionalState NewState);
+void ERTC_CalOutputConfig(uint32_t ERTC_CalOutput);
+ErrorStatus ERTC_SmoothCalConfig(uint32_t ERTC_SmoothCalPeriod, 
+                                  uint32_t ERTC_SmoothCalPlusPulses,
+                                  uint32_t ERTC_SmouthCalMinusPulsesValue);
+
+/* TimeStamp configuration functions ******************************************/
+void ERTC_TimeStampCmd(uint32_t ERTC_TimeStampEdge, FunctionalState NewState);
+void ERTC_GetTimeStamp(uint32_t ERTC_Format, ERTC_TimeType* ERTC_StampTimeStruct,
+                                      ERTC_DateType* ERTC_StampDateStruct);
+uint32_t ERTC_GetTimeStampSubSecond(void);
+
+/* Tampers configuration functions ********************************************/
+void ERTC_TamperTriggerConfig(uint32_t ERTC_Tamper, uint32_t ERTC_TamperTrigger);
+void ERTC_TamperCmd(uint32_t ERTC_Tamper, FunctionalState NewState);
+void ERTC_TamperFilterConfig(uint32_t ERTC_TamperFilter);
+void ERTC_TamperSamplingFreqConfig(uint32_t ERTC_TamperSamplingFreq);
+void ERTC_TamperPinsPrechargeDuration(uint32_t ERTC_TamperPrechargeDuration);
+void ERTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
+void ERTC_TamperPullUpCmd(FunctionalState NewState);
+
+/* Backup Data Registers configuration functions ******************************/
+void ERTC_WriteBackupRegister(uint32_t ERTC_BKP_DT, uint32_t Data);
+uint32_t ERTC_ReadBackupRegister(uint32_t ERTC_BKP_DT);
+
+/* ERTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
+   functions ******************************************************************/
+void ERTC_TamperPinSelection(uint32_t ERTC_TamperPin);
+void ERTC_TimeStampPinSelection(uint32_t ERTC_TimeStampPin);
+void ERTC_OutputTypeConfig(uint32_t ERTC_OutputType);
+
+/* RTC_Shift_control_synchonisation_functions *********************************/
+ErrorStatus ERTC_SynchroShiftConfig(uint32_t ERTC_ShiftAdd1S, uint32_t ERTC_ShiftSubFS);
+
+/* Interrupts and flags management functions **********************************/
+void ERTC_INTConfig(uint32_t ERTC_INT, FunctionalState NewState);
+FlagStatus ERTC_GetFlagStatus(uint32_t ERTC_FLAG);
+void ERTC_ClearFlag(uint32_t ERTC_FLAG);
+ITStatus ERTC_GetINTStatus(uint32_t ERTC_INT);
+void ERTC_ClearINTPendingBINT(uint32_t ERTC_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4xx_RCC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_eth.h

@@ -0,0 +1,1735 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_eth.h
+ * Description  : at32f4xx ETH header file
+ * Date         : 2019-12-16
+ * Version      : V1.0.0
+ **************************************************************************
+ */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_ETH_H
+#define __AT32F4xx_ETH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup ETH_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  ETH MAC Init structure definition
+  * @note   The user should not configure all the ETH_InitType structure's fields. 
+  *   By calling the ETH_StructInit function the structure’s fields are set to their default values.
+  *   Only the parameters that will be set to a non-default value should be configured.  
+  */ 
+typedef struct {
+/** 
+  * @brief / * MAC  
+  */ 
+  uint32_t             ETH_AutoNegotiation;           /*!< Selects or not the AutoNegotiation mode for the external PHY
+                                                           The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
+                                                           and the mode (half/full-duplex).
+                                                           This parameter can be a value of @ref ETH_AutoNegotiation */
+
+  uint32_t             ETH_Watchdog;                  /*!< Selects or not the Watchdog timer
+                                                           When enabled, the MAC allows no more then 2048 bytes to be received.
+                                                           When disabled, the MAC can receive up to 16384 bytes.
+                                                           This parameter can be a value of @ref ETH_watchdog */  
+
+  uint32_t             ETH_Jabber;                    /*!< Selects or not Jabber timer
+                                                           When enabled, the MAC allows no more then 2048 bytes to be sent.
+                                                           When disabled, the MAC can send up to 16384 bytes.
+                                                           This parameter can be a value of @ref ETH_Jabber */
+
+  uint32_t             ETH_InterFrameGap;             /*!< Selects the minimum IFG between frames during transmission
+                                                           This parameter can be a value of @ref ETH_Inter_Frame_Gap */   
+
+  uint32_t             ETH_CarrierSense;              /*!< Selects or not the Carrier Sense
+                                                           This parameter can be a value of @ref ETH_Carrier_Sense */
+
+  uint32_t             ETH_Speed;                     /*!< Sets the Ethernet speed: 10/100 Mbps
+                                                           This parameter can be a value of @ref ETH_Speed */
+
+  uint32_t             ETH_ReceiveOwn;                /*!< Selects or not the ReceiveOwn
+                                                           ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
+                                                           in Half-Duplex mode
+                                                           This parameter can be a value of @ref ETH_Receive_Own */  
+
+  uint32_t             ETH_LoopbackMode;              /*!< Selects or not the internal MAC MII Loopback mode
+                                                           This parameter can be a value of @ref ETH_Loop_Back_Mode */  
+
+  uint32_t             ETH_Mode;                      /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+                                                           This parameter can be a value of @ref ETH_Duplex_Mode */  
+
+  uint32_t             ETH_ChecksumOffload;           /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
+                                                           This parameter can be a value of @ref ETH_Checksum_Offload */    
+
+  uint32_t             ETH_RetryTransmission;         /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
+                                                           when a colision occurs (Half-Duplex mode)
+                                                           This parameter can be a value of @ref ETH_Retry_Transmission */
+
+  uint32_t             ETH_AutomaticPadCRCStrip;      /*!< Selects or not the Automatic MAC Pad/CRC Stripping
+                                                           This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ 
+
+  uint32_t             ETH_BackOffLimit;              /*!< Selects the BackOff limit value
+                                                           This parameter can be a value of @ref ETH_Back_Off_Limit */
+
+  uint32_t             ETH_DeferralCheck;             /*!< Selects or not the deferral check function (Half-Duplex mode)
+                                                           This parameter can be a value of @ref ETH_Deferral_Check */                                                                                                        
+
+  uint32_t             ETH_ReceiveAll;                /*!< Selects or not all frames reception by the MAC (No fitering)
+                                                           This parameter can be a value of @ref ETH_Receive_All */   
+
+  uint32_t             ETH_SourceAddrFilter;          /*!< Selects the Source Address Filter mode                                                           
+                                                           This parameter can be a value of @ref ETH_Source_Addr_Filter */                  
+
+  uint32_t             ETH_PassControlFrames;         /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)                                                          
+                                                           This parameter can be a value of @ref ETH_Pass_Control_Frames */ 
+
+  uint32_t             ETH_BroadcastFramesReception;  /*!< Selects or not the reception of Broadcast Frames
+                                                           This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
+
+  uint32_t             ETH_DestinationAddrFilter;     /*!< Sets the destination filter mode for both unicast and multicast frames
+                                                           This parameter can be a value of @ref ETH_Destination_Addr_Filter */ 
+
+  uint32_t             ETH_PromiscuousMode;           /*!< Selects or not the Promiscuous Mode
+                                                           This parameter can be a value of @ref ETH_Promiscuous_Mode */
+
+  uint32_t             ETH_MulticastFramesFilter;     /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
+                                                           This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ 
+
+  uint32_t             ETH_UnicastFramesFilter;       /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
+                                                           This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ 
+
+  uint32_t             ETH_HashTableHigh;             /*!< This field holds the higher 32 bits of Hash table.  */    
+
+  uint32_t             ETH_HashTableLow;              /*!< This field holds the lower 32 bits of Hash table.  */    
+
+  uint32_t             ETH_PauseTime;                 /*!< This field holds the value to be used in the Pause Time field in the
+                                                           transmit control frame */
+
+  uint32_t             ETH_ZeroQuantaPause;           /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames
+                                                           This parameter can be a value of @ref ETH_Zero_Quanta_Pause */  
+
+  uint32_t             ETH_PauseLowThreshold;         /*!< This field configures the threshold of the PAUSE to be checked for
+                                                           automatic retransmission of PAUSE Frame
+                                                           This parameter can be a value of @ref ETH_Pause_Low_Threshold */
+                                                           
+  uint32_t             ETH_UnicastPauseFrameDetect;   /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
+                                                           unicast address and unique multicast address)
+                                                           This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */  
+
+  uint32_t             ETH_ReceiveFlowControl;        /*!< Enables or disables the MAC to decode the received Pause frame and
+                                                           disable its transmitter for a specified time (Pause Time)
+                                                           This parameter can be a value of @ref ETH_Receive_Flow_Control */
+
+  uint32_t             ETH_TransmitFlowControl;       /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
+                                                           or the MAC back-pressure operation (Half-Duplex mode)
+                                                           This parameter can be a value of @ref ETH_Transmit_Flow_Control */     
+
+  uint32_t             ETH_VLANTagComparison;         /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
+                                                           comparison and filtering
+                                                           This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ 
+
+  uint32_t             ETH_VLANTagIdentifier;         /*!< Holds the VLAN tag identifier for receive frames */
+
+/** 
+  * @brief / * DMA  
+  */ 
+
+  uint32_t             ETH_DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames
+                                                             This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ 
+
+  uint32_t             ETH_ReceiveStoreForward;         /*!< Enables or disables the Receive store and forward mode
+                                                             This parameter can be a value of @ref ETH_Receive_Store_Forward */ 
+
+  uint32_t             ETH_FlushReceivedFrame;          /*!< Enables or disables the flushing of received frames
+                                                             This parameter can be a value of @ref ETH_Flush_Received_Frame */ 
+
+  uint32_t             ETH_TransmitStoreForward;        /*!< Enables or disables Transmit store and forward mode
+                                                             This parameter can be a value of @ref ETH_Transmit_Store_Forward */ 
+
+  uint32_t             ETH_TransmitThresholdControl;    /*!< Selects or not the Transmit Threshold Control
+                                                             This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
+
+  uint32_t             ETH_ForwardErrorFrames;          /*!< Selects or not the forward to the DMA of erroneous frames
+                                                             This parameter can be a value of @ref ETH_Forward_Error_Frames */
+
+  uint32_t             ETH_ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+                                                             and length less than 64 bytes) including pad-bytes and CRC)
+                                                             This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
+
+  uint32_t             ETH_ReceiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO
+                                                             This parameter can be a value of @ref ETH_Receive_Threshold_Control */
+
+  uint32_t             ETH_SecondFrameOperate;          /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
+                                                             frame of Transmit data even before obtaining the status for the first frame.
+                                                             This parameter can be a value of @ref ETH_Second_Frame_Operate */
+
+  uint32_t             ETH_AddressAlignedBeats;         /*!< Enables or disables the Address Aligned Beats
+                                                             This parameter can be a value of @ref ETH_Address_Aligned_Beats */
+
+  uint32_t             ETH_FixedBurst;                  /*!< Enables or disables the AHB Master interface fixed burst transfers
+                                                             This parameter can be a value of @ref ETH_Fixed_Burst */
+                       
+  uint32_t             ETH_RxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction
+                                                             This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 
+
+  uint32_t             ETH_TxDMABurstLength;            /*!< Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction
+                                                             This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */                                                   
+
+  uint32_t             ETH_DescriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */                                                             
+
+  uint32_t             ETH_DMAArbitration;              /*!< Selects the DMA Tx/Rx arbitration
+                                                             This parameter can be a value of @ref ETH_DMA_Arbitration */  
+}ETH_InitType;
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                           DMA descriptors types
+  */ 
+/**--------------------------------------------------------------------------**/
+
+/** 
+  * @brief  ETH DMA Desciptors data structure definition
+  */ 
+typedef struct  {
+  uint32_t   Status;                /*!< Status */
+  uint32_t   ControlBufferSize;     /*!< Control and Buffer1, Buffer2 lengths */
+  uint32_t   Buffer1Addr;           /*!< Buffer1 address pointer */
+  uint32_t   Buffer2NextDescAddr;   /*!< Buffer2 or next descriptor address pointer */
+} ETH_DMADESCTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Exported_Constants
+  * @{
+  */ 
+
+/**
+ * @brief Uncomment the line below if you want to use user defined Delay function
+ *        (for precise timing), otherwise default _eth_delay_ function defined within
+ *        this driver is used (less precise timing).  
+ */
+/* #define USE_Delay */
+
+#ifdef USE_Delay
+#include "main.h" 
+  #define _eth_delay_    Delay     /*!< User can provide more timing precise _eth_delay_ function */
+#else
+  #define _eth_delay_    ETH_Delay /*!< Default _eth_delay_ function with less precise timing */
+#endif  
+  
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                          ETH Frames defines
+  */ 
+/**--------------------------------------------------------------------------**/
+
+/** @defgroup ENET_Buffers_setting 
+  * @{
+  */ 
+#define ETH_MAX_PACKET_SIZE    1520    /*!< ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER               14    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/ept_type */
+#define ETH_CRC                   4    /*!< Ethernet CRC */
+#define ETH_EXTRA                 2    /*!< Extra bytes in some cases */   
+#define VLAN_TAG                  4    /*!< optional 802.1q VLAN Tag */
+#define MIN_ETH_PAYLOAD          46    /*!< Minimum Ethernet payload size */
+#define MAX_ETH_PAYLOAD        1500    /*!< Maximum Ethernet payload size */
+#define JUMBO_FRAME_PAYLOAD    9000    /*!< Jumbo frame payload size */      
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                 Ethernet DMA descriptors registers bits definition
+  */ 
+/**--------------------------------------------------------------------------**/
+
+/**
+@code 
+   DMA Tx Desciptor
+  -----------------------------------------------------------------------------------------------
+  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
+  -----------------------------------------------------------------------------------------------
+  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
+  -----------------------------------------------------------------------------------------------
+  TDES2 |                         Buffer1 Address [31:0]                                         |
+  -----------------------------------------------------------------------------------------------
+  TDES3 |                   Buffer2 Address [31:0] / Next Desciptor Address [31:0]               |
+  -----------------------------------------------------------------------------------------------
+@endcode
+*/
+
+/** 
+  * @brief  Bit definition of TDES0 register: DMA Tx descriptor status register
+  */ 
+#define ETH_DMATxDesc_OWN                     ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATxDesc_IC                      ((uint32_t)0x40000000)  /*!< Interrupt on Completion */
+#define ETH_DMATxDesc_LS                      ((uint32_t)0x20000000)  /*!< Last Segment */
+#define ETH_DMATxDesc_FS                      ((uint32_t)0x10000000)  /*!< First Segment */
+#define ETH_DMATxDesc_DC                      ((uint32_t)0x08000000)  /*!< Disable CRC */
+#define ETH_DMATxDesc_DP                      ((uint32_t)0x04000000)  /*!< Disable Padding */
+#define ETH_DMATxDesc_TTSE                    ((uint32_t)0x02000000)  /*!< Transmit Time Stamp Enable */
+#define ETH_DMATxDesc_CIC                     ((uint32_t)0x00C00000)  /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATxDesc_CIC_ByPass              ((uint32_t)0x00000000)  /*!< Do Nothing: Checksum Engine is bypassed */ 
+#define ETH_DMATxDesc_CIC_IPV4Header          ((uint32_t)0x00400000)  /*!< IPV4 header Checksum Insertion */ 
+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment  ((uint32_t)0x00800000)  /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 
+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full     ((uint32_t)0x00C00000)  /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 
+#define ETH_DMATxDesc_TER                     ((uint32_t)0x00200000)  /*!< Transmit End of Ring */
+#define ETH_DMATxDesc_TCH                     ((uint32_t)0x00100000)  /*!< Second Address Chained */
+#define ETH_DMATxDesc_TTSS                    ((uint32_t)0x00020000)  /*!< Tx Time Stamp Status */
+#define ETH_DMATxDesc_IHE                     ((uint32_t)0x00010000)  /*!< IP Header Error */
+#define ETH_DMATxDesc_ES                      ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATxDesc_JT                      ((uint32_t)0x00004000)  /*!< Jabber Timeout */
+#define ETH_DMATxDesc_FF                      ((uint32_t)0x00002000)  /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATxDesc_PCE                     ((uint32_t)0x00001000)  /*!< Payload Checksum Error */
+#define ETH_DMATxDesc_LCA                     ((uint32_t)0x00000800)  /*!< Loss of Carrier: carrier lost during tramsmission */
+#define ETH_DMATxDesc_NC                      ((uint32_t)0x00000400)  /*!< No Carrier: no carrier signal from the tranceiver */
+#define ETH_DMATxDesc_LCO                     ((uint32_t)0x00000200)  /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATxDesc_EC                      ((uint32_t)0x00000100)  /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATxDesc_VF                      ((uint32_t)0x00000080)  /*!< VLAN Frame */
+#define ETH_DMATxDesc_CC                      ((uint32_t)0x00000078)  /*!< Collision Count */
+#define ETH_DMATxDesc_ED                      ((uint32_t)0x00000004)  /*!< Excessive Deferral */
+#define ETH_DMATxDesc_UF                      ((uint32_t)0x00000002)  /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATxDesc_DB                      ((uint32_t)0x00000001)  /*!< Deferred Bit */
+
+/** 
+  * @brief  Bit definition of TDES1 register
+  */ 
+#define ETH_DMATxDesc_TBS2  ((uint32_t)0x1FFF0000)  /*!< Transmit Buffer2 Size */
+#define ETH_DMATxDesc_TBS1  ((uint32_t)0x00001FFF)  /*!< Transmit Buffer1 Size */
+
+/** 
+  * @brief  Bit definition of TDES2 register
+  */ 
+#define ETH_DMATxDesc_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */
+
+/** 
+  * @brief  Bit definition of TDES3 register
+  */ 
+#define ETH_DMATxDesc_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_Rx_descriptor 
+  * @{
+  */
+
+/**
+@code 
+  DMA Rx Desciptor
+  --------------------------------------------------------------------------------------------------------------------
+  RDES0 | OWN(31) |                                             Status [30:0]                                          |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES2 |                                       Buffer1 Address [31:0]                                                 |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES3 |                          Buffer2 Address [31:0] / Next Desciptor Address [31:0]                              |
+  ---------------------------------------------------------------------------------------------------------------------
+@endcode
+*/
+
+/** 
+  * @brief  Bit definition of RDES0 register: DMA Rx descriptor status register
+  */ 
+#define ETH_DMARxDesc_OWN         ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine  */
+#define ETH_DMARxDesc_AFM         ((uint32_t)0x40000000)  /*!< DA Filter Fail for the rx frame  */
+#define ETH_DMARxDesc_FL          ((uint32_t)0x3FFF0000)  /*!< Receive descriptor frame length  */
+#define ETH_DMARxDesc_ES          ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARxDesc_DE          ((uint32_t)0x00004000)  /*!< Desciptor error: no more descriptors for receive frame  */
+#define ETH_DMARxDesc_SAF         ((uint32_t)0x00002000)  /*!< SA Filter Fail for the received frame */
+#define ETH_DMARxDesc_LE          ((uint32_t)0x00001000)  /*!< Frame size not matching with length field */
+#define ETH_DMARxDesc_OE          ((uint32_t)0x00000800)  /*!< Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARxDesc_VLAN        ((uint32_t)0x00000400)  /*!< VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARxDesc_FS          ((uint32_t)0x00000200)  /*!< First descriptor of the frame  */
+#define ETH_DMARxDesc_LS          ((uint32_t)0x00000100)  /*!< Last descriptor of the frame  */ 
+#define ETH_DMARxDesc_IPV4HCE     ((uint32_t)0x00000080)  /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */    
+#define ETH_DMARxDesc_LC          ((uint32_t)0x00000040)  /*!< Late collision occurred during reception   */
+#define ETH_DMARxDesc_FT          ((uint32_t)0x00000020)  /*!< Frame ept_type - Ethernet, otherwise 802.3    */
+#define ETH_DMARxDesc_RWT         ((uint32_t)0x00000010)  /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */
+#define ETH_DMARxDesc_RE          ((uint32_t)0x00000008)  /*!< Receive error: error reported by MII interface  */
+#define ETH_DMARxDesc_DBE         ((uint32_t)0x00000004)  /*!< Dribble bit error: frame contains non int multiple of 8 bits  */
+#define ETH_DMARxDesc_CE          ((uint32_t)0x00000002)  /*!< CRC error */
+#define ETH_DMARxDesc_MAMPCE      ((uint32_t)0x00000001)  /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+
+/** 
+  * @brief  Bit definition of RDES1 register
+  */ 
+#define ETH_DMARxDesc_DIC   ((uint32_t)0x80000000)  /*!< Disable Interrupt on Completion */
+#define ETH_DMARxDesc_RBS2  ((uint32_t)0x1FFF0000)  /*!< Receive Buffer2 Size */
+#define ETH_DMARxDesc_RER   ((uint32_t)0x00008000)  /*!< Receive End of Ring */
+#define ETH_DMARxDesc_RCH   ((uint32_t)0x00004000)  /*!< Second Address Chained */
+#define ETH_DMARxDesc_RBS1  ((uint32_t)0x00001FFF)  /*!< Receive Buffer1 Size */
+
+/** 
+  * @brief  Bit definition of RDES2 register  
+  */ 
+#define ETH_DMARxDesc_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */
+
+/** 
+  * @brief  Bit definition of RDES3 register  
+  */ 
+#define ETH_DMARxDesc_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                     Desciption of common PHY registers
+  */ 
+/**--------------------------------------------------------------------------**/
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_Read_write_Timeouts 
+  * @{
+  */ 
+#define PHY_READ_TO                     ((uint32_t)0x00FFFFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x00FFFFFF)
+
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_Reset_Delay 
+  * @{
+  */ 
+#define PHY_ResetDelay                  ((uint32_t)0x000FFFFF) 
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_Config_Delay 
+  * @{
+  */ 
+#define PHY_ConfigDelay                 ((uint32_t)0x00FFFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_Register_address 
+  * @{
+  */ 
+#define PHY_BCR                          0          /*!< Tranceiver Basic Control Register */
+#define PHY_BSR                          1          /*!< Tranceiver Basic Status Register */
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_basic_Control_register 
+  * @{
+  */ 
+#define PHY_Reset                       ((u16)0x8000)      /*!< PHY Reset */
+#define PHY_Loopback                    ((u16)0x4000)      /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((u16)0x2100)      /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((u16)0x2000)      /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((u16)0x0100)      /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M              ((u16)0x0000)      /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AutoNegotiation             ((u16)0x1000)      /*!< Enable auto-negotiation function */
+#define PHY_Restart_AutoNegotiation     ((u16)0x0200)      /*!< Restart auto-negotiation function */
+#define PHY_Powerdown                   ((u16)0x0800)      /*!< Select the power down mode */
+#define PHY_Isolate                     ((u16)0x0400)      /*!< Isolate PHY from MII */
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_basic_status_register 
+  * @{
+  */ 
+#define PHY_AutoNego_Complete           ((u16)0x0020)      /*!< Auto-Negotioation process completed */
+#define PHY_Linked_Status               ((u16)0x0004)      /*!< Valid link established */
+#define PHY_Jabber_detection            ((u16)0x0002)      /*!< Jabber condition detected */
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_status_register 
+  * @{
+  */ 
+/* The PHY status register value change from a PHY to another so the user have 
+   to update this value depending on the used external PHY */
+/** 
+  * @brief  For DM6162  
+  */ 
+#define PHY_SR                           17         /*!< Tranceiver Status Register */
+/** 
+  * @brief  For DP83848  
+  */ 
+//#define PHY_SR                           0x10     /*!< Tranceiver Status Register */
+
+/* The Speed and Duplex mask values change from a PHY to another so the user have to update
+   this value depending on the used external PHY */
+/** 
+  * @brief  For dm9162  
+  */ 
+#define PHY_Speed_Status            ((u16)0x2000)       /*!< Configured information of Speed: 10Mbps */
+#define PHY_Duplex_Status           ((u16)0x0100)       /*!< Configured information of Duplex: Full-duplex */
+#define PHY_FullDuplex_Speed_100_Status   ((u16)0x8000)
+#define PHY_HalfDuplex_Speed_100_Status   ((u16)0x4000)
+#define PHY_FullDuplex_Speed_10_Status   ((u16)0x2000)
+#define PHY_HalfDuplex_Speed_10_Status   ((u16)0x1000)
+
+
+/** 
+  * @brief  For DP83848  
+  */ 
+//#define PHY_Speed_Status            ((u16)0x0002)    /*!< Configured information of Speed: 10Mbps */
+//#define PHY_Duplex_Status           ((u16)0x0100)    /*!< Configured information of Duplex: Full-duplex */
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
+#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \
+                             ((REG) == PHY_BSR) || \
+                             ((REG) == PHY_SR))
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                                  MAC defines
+  */ 
+/**--------------------------------------------------------------------------**/
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ETH_AutoNegotiation 
+  * @{
+  */ 
+#define ETH_AutoNegotiation_Enable     ((uint32_t)0x00000001)
+#define ETH_AutoNegotiation_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \
+                                     ((CMD) == ETH_AutoNegotiation_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_watchdog 
+  * @{
+  */ 
+#define ETH_Watchdog_Enable       ((uint32_t)0x00000000)
+#define ETH_Watchdog_Disable      ((uint32_t)0x00800000)
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \
+                              ((CMD) == ETH_Watchdog_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Jabber 
+  * @{
+  */ 
+#define ETH_Jabber_Enable    ((uint32_t)0x00000000)
+#define ETH_Jabber_Disable   ((uint32_t)0x00400000)
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \
+                            ((CMD) == ETH_Jabber_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Inter_Frame_Gap 
+  * @{
+  */ 
+#define ETH_InterFrameGap_96Bit   ((uint32_t)0x00000000)  /*!< minimum IFG between frames during transmission is 96Bit */
+#define ETH_InterFrameGap_88Bit   ((uint32_t)0x00020000)  /*!< minimum IFG between frames during transmission is 88Bit */
+#define ETH_InterFrameGap_80Bit   ((uint32_t)0x00040000)  /*!< minimum IFG between frames during transmission is 80Bit */
+#define ETH_InterFrameGap_72Bit   ((uint32_t)0x00060000)  /*!< minimum IFG between frames during transmission is 72Bit */
+#define ETH_InterFrameGap_64Bit   ((uint32_t)0x00080000)  /*!< minimum IFG between frames during transmission is 64Bit */
+#define ETH_InterFrameGap_56Bit   ((uint32_t)0x000A0000)  /*!< minimum IFG between frames during transmission is 56Bit */
+#define ETH_InterFrameGap_48Bit   ((uint32_t)0x000C0000)  /*!< minimum IFG between frames during transmission is 48Bit */
+#define ETH_InterFrameGap_40Bit   ((uint32_t)0x000E0000)  /*!< minimum IFG between frames during transmission is 40Bit */
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_88Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_80Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_72Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_64Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_56Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_48Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_40Bit))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Carrier_Sense 
+  * @{
+  */ 
+#define ETH_CarrierSense_Enable   ((uint32_t)0x00000000)
+#define ETH_CarrierSense_Disable  ((uint32_t)0x00010000)
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \
+                                   ((CMD) == ETH_CarrierSense_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Speed 
+  * @{
+  */ 
+#define ETH_Speed_10M        ((uint32_t)0x00000000)
+#define ETH_Speed_100M       ((uint32_t)0x00004000)
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \
+                             ((SPEED) == ETH_Speed_100M))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Own 
+  * @{
+  */ 
+#define ETH_ReceiveOwn_Enable     ((uint32_t)0x00000000)
+#define ETH_ReceiveOwn_Disable    ((uint32_t)0x00002000)
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \
+                                 ((CMD) == ETH_ReceiveOwn_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Loop_Back_Mode 
+  * @{
+  */ 
+#define ETH_LoopbackMode_Enable        ((uint32_t)0x00001000)
+#define ETH_LoopbackMode_Disable       ((uint32_t)0x00000000)
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \
+                                   ((CMD) == ETH_LoopbackMode_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Duplex_Mode 
+  * @{
+  */ 
+#define ETH_Mode_FullDuplex       ((uint32_t)0x00000800)
+#define ETH_Mode_HalfDuplex       ((uint32_t)0x00000000)
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \
+                                  ((MODE) == ETH_Mode_HalfDuplex))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Checksum_Offload 
+  * @{
+  */ 
+#define ETH_ChecksumOffload_Enable     ((uint32_t)0x00000400)
+#define ETH_ChecksumOffload_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \
+                                      ((CMD) == ETH_ChecksumOffload_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Retry_Transmission 
+  * @{
+  */ 
+#define ETH_RetryTransmission_Enable   ((uint32_t)0x00000000)
+#define ETH_RetryTransmission_Disable  ((uint32_t)0x00000200)
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \
+                                        ((CMD) == ETH_RetryTransmission_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Automatic_Pad_CRC_Strip 
+  * @{
+  */ 
+#define ETH_AutomaticPadCRCStrip_Enable     ((uint32_t)0x00000080)
+#define ETH_AutomaticPadCRCStrip_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \
+                                            ((CMD) == ETH_AutomaticPadCRCStrip_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Back_Off_Limit 
+  * @{
+  */ 
+#define ETH_BackOffLimit_10  ((uint32_t)0x00000000)
+#define ETH_BackOffLimit_8   ((uint32_t)0x00000020)
+#define ETH_BackOffLimit_4   ((uint32_t)0x00000040)
+#define ETH_BackOffLimit_1   ((uint32_t)0x00000060)
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \
+                                     ((LIMIT) == ETH_BackOffLimit_8) || \
+                                     ((LIMIT) == ETH_BackOffLimit_4) || \
+                                     ((LIMIT) == ETH_BackOffLimit_1))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Deferral_Check 
+  * @{
+  */
+#define ETH_DeferralCheck_Enable       ((uint32_t)0x00000010)
+#define ETH_DeferralCheck_Disable      ((uint32_t)0x00000000)
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \
+                                    ((CMD) == ETH_DeferralCheck_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_All 
+  * @{
+  */ 
+#define ETH_ReceiveAll_Enable     ((uint32_t)0x80000000)
+#define ETH_ReceiveAll_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \
+                                 ((CMD) == ETH_ReceiveAll_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Source_Addr_Filter 
+  * @{
+  */ 
+#define ETH_SourceAddrFilter_Normal_Enable       ((uint32_t)0x00000200)
+#define ETH_SourceAddrFilter_Inverse_Enable      ((uint32_t)0x00000300)
+#define ETH_SourceAddrFilter_Disable             ((uint32_t)0x00000000)
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \
+                                        ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \
+                                        ((CMD) == ETH_SourceAddrFilter_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Pass_Control_Frames 
+  * @{
+  */ 
+#define ETH_PassControlFrames_BlockAll                ((uint32_t)0x00000040)  /*!< MAC filters all control frames from reaching the application */
+#define ETH_PassControlFrames_ForwardAll              ((uint32_t)0x00000080)  /*!< MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /*!< MAC forwards control frames that pass the Address Filter. */ 
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \
+                                     ((PASS) == ETH_PassControlFrames_ForwardAll) || \
+                                     ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Broadcast_Frames_Reception 
+  * @{
+  */ 
+#define ETH_BroadcastFramesReception_Enable      ((uint32_t)0x00000000)
+#define ETH_BroadcastFramesReception_Disable     ((uint32_t)0x00000020)
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \
+                                                ((CMD) == ETH_BroadcastFramesReception_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Destination_Addr_Filter 
+  * @{
+  */ 
+#define ETH_DestinationAddrFilter_Normal    ((uint32_t)0x00000000)
+#define ETH_DestinationAddrFilter_Inverse   ((uint32_t)0x00000008)
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \
+                                                ((FILTER) == ETH_DestinationAddrFilter_Inverse))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Promiscuous_Mode 
+  * @{
+  */ 
+#define ETH_PromiscuousMode_Enable     ((uint32_t)0x00000001)
+#define ETH_PromiscuousMode_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \
+                                      ((CMD) == ETH_PromiscuousMode_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Multicast_Frames_Filter 
+  * @{
+  */ 
+#define ETH_MulticastFramesFilter_PerfectHashTable    ((uint32_t)0x00000404)
+#define ETH_MulticastFramesFilter_HashTable           ((uint32_t)0x00000004)
+#define ETH_MulticastFramesFilter_Perfect             ((uint32_t)0x00000000)
+#define ETH_MulticastFramesFilter_None                ((uint32_t)0x00000010)
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \
+                                                ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \
+                                                ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \
+                                                ((FILTER) == ETH_MulticastFramesFilter_None))
+                                                     
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Unicast_Frames_Filter 
+  * @{
+  */ 
+#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402)
+#define ETH_UnicastFramesFilter_HashTable        ((uint32_t)0x00000002)
+#define ETH_UnicastFramesFilter_Perfect          ((uint32_t)0x00000000)
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \
+                                              ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \
+                                              ((FILTER) == ETH_UnicastFramesFilter_Perfect))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Pause_Time 
+  * @{
+  */ 
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Zero_Quanta_Pause 
+  * @{
+  */ 
+#define ETH_ZeroQuantaPause_Enable     ((uint32_t)0x00000000)
+#define ETH_ZeroQuantaPause_Disable    ((uint32_t)0x00000080)
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD)   (((CMD) == ETH_ZeroQuantaPause_Enable) || \
+                                        ((CMD) == ETH_ZeroQuantaPause_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Pause_Low_Threshold 
+  * @{
+  */ 
+#define ETH_PauseLowThreshold_Minus4        ((uint32_t)0x00000000)  /*!< Pause time minus 4 slot times */
+#define ETH_PauseLowThreshold_Minus28       ((uint32_t)0x00000010)  /*!< Pause time minus 28 slot times */
+#define ETH_PauseLowThreshold_Minus144      ((uint32_t)0x00000020)  /*!< Pause time minus 144 slot times */
+#define ETH_PauseLowThreshold_Minus256      ((uint32_t)0x00000030)  /*!< Pause time minus 256 slot times */
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \
+                                               ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \
+                                               ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \
+                                               ((THRESHOLD) == ETH_PauseLowThreshold_Minus256))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Unicast_Pause_Frame_Detect 
+  * @{
+  */ 
+#define ETH_UnicastPauseFrameDetect_Enable  ((uint32_t)0x00000008)
+#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000)
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \
+                                                ((CMD) == ETH_UnicastPauseFrameDetect_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Flow_Control 
+  * @{
+  */ 
+#define ETH_ReceiveFlowControl_Enable       ((uint32_t)0x00000004)
+#define ETH_ReceiveFlowControl_Disable      ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \
+                                         ((CMD) == ETH_ReceiveFlowControl_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Transmit_Flow_Control 
+  * @{
+  */ 
+#define ETH_TransmitFlowControl_Enable      ((uint32_t)0x00000002)
+#define ETH_TransmitFlowControl_Disable     ((uint32_t)0x00000000)
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \
+                                          ((CMD) == ETH_TransmitFlowControl_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_VLAN_Tag_Comparison 
+  * @{
+  */ 
+#define ETH_VLANTagComparison_12Bit    ((uint32_t)0x00010000)
+#define ETH_VLANTagComparison_16Bit    ((uint32_t)0x00000000)
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \
+                                                ((COMPARISON) == ETH_VLANTagComparison_16Bit))
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_Flags 
+  * @{
+  */ 
+#define ETH_MAC_FLAG_TST     ((uint32_t)0x00000200)  /*!< Time stamp trigger flag (on MAC) */
+#define ETH_MAC_FLAG_MMCT    ((uint32_t)0x00000040)  /*!< MMC transmit flag  */
+#define ETH_MAC_FLAG_MMCR    ((uint32_t)0x00000020)  /*!< MMC receive flag */
+#define ETH_MAC_FLAG_MMC     ((uint32_t)0x00000010)  /*!< MMC flag (on MAC) */
+#define ETH_MAC_FLAG_PMT     ((uint32_t)0x00000008)  /*!< PMT flag (on MAC) */
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
+                                   ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
+                                   ((FLAG) == ETH_MAC_FLAG_PMT))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_Interrupts 
+  * @{
+  */ 
+#define ETH_MAC_INT_TST       ((uint32_t)0x00000200)  /*!< Time stamp trigger interrupt (on MAC) */
+#define ETH_MAC_INT_MMCT      ((uint32_t)0x00000040)  /*!< MMC transmit interrupt */
+#define ETH_MAC_INT_MMCR      ((uint32_t)0x00000020)  /*!< MMC receive interrupt */
+#define ETH_MAC_INT_MMC       ((uint32_t)0x00000010)  /*!< MMC interrupt (on MAC) */
+#define ETH_MAC_INT_PMT       ((uint32_t)0x00000008)  /*!< PMT interrupt (on MAC) */
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_INT_TST) || ((IT) == ETH_MAC_INT_MMCT) || \
+                               ((IT) == ETH_MAC_INT_MMCR) || ((IT) == ETH_MAC_INT_MMC) || \
+                               ((IT) == ETH_MAC_INT_PMT))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_addresses 
+  * @{
+  */ 
+#define ETH_MAC_Address0     ((uint32_t)0x00000000)
+#define ETH_MAC_Address1     ((uint32_t)0x00000008)
+#define ETH_MAC_Address2     ((uint32_t)0x00000010)
+#define ETH_MAC_Address3     ((uint32_t)0x00000018)
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \
+                                         ((ADDRESS) == ETH_MAC_Address1) || \
+                                         ((ADDRESS) == ETH_MAC_Address2) || \
+                                         ((ADDRESS) == ETH_MAC_Address3))
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \
+                                        ((ADDRESS) == ETH_MAC_Address2) || \
+                                        ((ADDRESS) == ETH_MAC_Address3))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames 
+  * @{
+  */ 
+#define ETH_MAC_AddressFilter_SA       ((uint32_t)0x00000000)
+#define ETH_MAC_AddressFilter_DA       ((uint32_t)0x00000008)
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \
+                                           ((FILTER) == ETH_MAC_AddressFilter_DA))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes 
+  * @{
+  */ 
+#define ETH_MAC_AddressMask_Byte6      ((uint32_t)0x20000000)  /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MAC_AddressMask_Byte5      ((uint32_t)0x10000000)  /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MAC_AddressMask_Byte4      ((uint32_t)0x08000000)  /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MAC_AddressMask_Byte3      ((uint32_t)0x04000000)  /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MAC_AddressMask_Byte2      ((uint32_t)0x02000000)  /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MAC_AddressMask_Byte1      ((uint32_t)0x01000000)  /*!< Mask MAC Address low reg bits [70] */
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte5) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte4) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte3) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte2) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte1))
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                      Ethernet DMA Desciptors defines
+  */ 
+/**--------------------------------------------------------------------------**/
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Tx_descriptor_flags
+  * @{
+  */ 
+#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \
+                                         ((FLAG) == ETH_DMATxDesc_IC) || \
+                                         ((FLAG) == ETH_DMATxDesc_LS) || \
+                                         ((FLAG) == ETH_DMATxDesc_FS) || \
+                                         ((FLAG) == ETH_DMATxDesc_DC) || \
+                                         ((FLAG) == ETH_DMATxDesc_DP) || \
+                                         ((FLAG) == ETH_DMATxDesc_TTSE) || \
+                                         ((FLAG) == ETH_DMATxDesc_TER) || \
+                                         ((FLAG) == ETH_DMATxDesc_TCH) || \
+                                         ((FLAG) == ETH_DMATxDesc_TTSS) || \
+                                         ((FLAG) == ETH_DMATxDesc_IHE) || \
+                                         ((FLAG) == ETH_DMATxDesc_ES) || \
+                                         ((FLAG) == ETH_DMATxDesc_JT) || \
+                                         ((FLAG) == ETH_DMATxDesc_FF) || \
+                                         ((FLAG) == ETH_DMATxDesc_PCE) || \
+                                         ((FLAG) == ETH_DMATxDesc_LCA) || \
+                                         ((FLAG) == ETH_DMATxDesc_NC) || \
+                                         ((FLAG) == ETH_DMATxDesc_LCO) || \
+                                         ((FLAG) == ETH_DMATxDesc_EC) || \
+                                         ((FLAG) == ETH_DMATxDesc_VF) || \
+                                         ((FLAG) == ETH_DMATxDesc_CC) || \
+                                         ((FLAG) == ETH_DMATxDesc_ED) || \
+                                         ((FLAG) == ETH_DMATxDesc_UF) || \
+                                         ((FLAG) == ETH_DMATxDesc_DB))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Tx_descriptor_segment 
+  * @{
+  */ 
+#define ETH_DMATxDesc_LastSegment      ((uint32_t)0x40000000)  /*!< Last Segment */
+#define ETH_DMATxDesc_FirstSegment     ((uint32_t)0x20000000)  /*!< First Segment */
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \
+                                            ((SEGMENT) == ETH_DMATxDesc_FirstSegment))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
+  * @{
+  */ 
+#define ETH_DMATxDesc_ChecksumByPass             ((uint32_t)0x00000000)   /*!< Checksum engine bypass */
+#define ETH_DMATxDesc_ChecksumIPV4Header         ((uint32_t)0x00400000)   /*!< IPv4 header checksum insertion  */
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment  ((uint32_t)0x00800000)   /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull     ((uint32_t)0x00C00000)   /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \
+                                              ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \
+                                              ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \
+                                              ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull))
+/** 
+  * @brief  ETH DMA Tx Desciptor buffer size
+  */ 
+#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Rx_descriptor_flags
+  * @{
+  */ 
+#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \
+                                         ((FLAG) == ETH_DMARxDesc_AFM) || \
+                                         ((FLAG) == ETH_DMARxDesc_ES) || \
+                                         ((FLAG) == ETH_DMARxDesc_DE) || \
+                                         ((FLAG) == ETH_DMARxDesc_SAF) || \
+                                         ((FLAG) == ETH_DMARxDesc_LE) || \
+                                         ((FLAG) == ETH_DMARxDesc_OE) || \
+                                         ((FLAG) == ETH_DMARxDesc_VLAN) || \
+                                         ((FLAG) == ETH_DMARxDesc_FS) || \
+                                         ((FLAG) == ETH_DMARxDesc_LS) || \
+                                         ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \
+                                         ((FLAG) == ETH_DMARxDesc_LC) || \
+                                         ((FLAG) == ETH_DMARxDesc_FT) || \
+                                         ((FLAG) == ETH_DMARxDesc_RWT) || \
+                                         ((FLAG) == ETH_DMARxDesc_RE) || \
+                                         ((FLAG) == ETH_DMARxDesc_DBE) || \
+                                         ((FLAG) == ETH_DMARxDesc_CE) || \
+                                         ((FLAG) == ETH_DMARxDesc_MAMPCE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Rx_descriptor_buffers_ 
+  * @{
+  */ 
+#define ETH_DMARxDesc_Buffer1     ((uint32_t)0x00000000)  /*!< DMA Rx Desc Buffer1 */
+#define ETH_DMARxDesc_Buffer2     ((uint32_t)0x00000001)  /*!< DMA Rx Desc Buffer2 */
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \
+                                          ((BUFFER) == ETH_DMARxDesc_Buffer2))
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                           Ethernet DMA defines
+  */ 
+/**--------------------------------------------------------------------------**/
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame 
+  * @{
+  */ 
+#define ETH_DropTCPIPChecksumErrorFrame_Enable   ((uint32_t)0x00000000)
+#define ETH_DropTCPIPChecksumErrorFrame_Disable  ((uint32_t)0x04000000)
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \
+                                               ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Store_Forward 
+  * @{
+  */ 
+#define ETH_ReceiveStoreForward_Enable      ((uint32_t)0x02000000)
+#define ETH_ReceiveStoreForward_Disable     ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \
+                                           ((CMD) == ETH_ReceiveStoreForward_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Flush_Received_Frame 
+  * @{
+  */ 
+#define ETH_FlushReceivedFrame_Enable       ((uint32_t)0x00000000)
+#define ETH_FlushReceivedFrame_Disable      ((uint32_t)0x01000000)
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \
+                                         ((CMD) == ETH_FlushReceivedFrame_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Transmit_Store_Forward 
+  * @{
+  */ 
+#define ETH_TransmitStoreForward_Enable     ((uint32_t)0x00200000)
+#define ETH_TransmitStoreForward_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \
+                                            ((CMD) == ETH_TransmitStoreForward_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Transmit_Threshold_Control 
+  * @{
+  */ 
+#define ETH_TransmitThresholdControl_64Bytes     ((uint32_t)0x00000000)  /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_TransmitThresholdControl_128Bytes    ((uint32_t)0x00004000)  /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_TransmitThresholdControl_192Bytes    ((uint32_t)0x00008000)  /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_TransmitThresholdControl_256Bytes    ((uint32_t)0x0000C000)  /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_TransmitThresholdControl_40Bytes     ((uint32_t)0x00010000)  /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_TransmitThresholdControl_32Bytes     ((uint32_t)0x00014000)  /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_TransmitThresholdControl_24Bytes     ((uint32_t)0x00018000)  /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_TransmitThresholdControl_16Bytes     ((uint32_t)0x0001C000)  /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Forward_Error_Frames 
+  * @{
+  */ 
+#define ETH_ForwardErrorFrames_Enable       ((uint32_t)0x00000080)
+#define ETH_ForwardErrorFrames_Disable      ((uint32_t)0x00000000)
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \
+                                          ((CMD) == ETH_ForwardErrorFrames_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Forward_Undersized_Good_Frames 
+  * @{
+  */ 
+#define ETH_ForwardUndersizedGoodFrames_Enable   ((uint32_t)0x00000040)
+#define ETH_ForwardUndersizedGoodFrames_Disable  ((uint32_t)0x00000000)     
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \
+                                                    ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Threshold_Control 
+  * @{
+  */ 
+#define ETH_ReceiveThresholdControl_64Bytes      ((uint32_t)0x00000000)  /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_ReceiveThresholdControl_32Bytes      ((uint32_t)0x00000008)  /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_ReceiveThresholdControl_96Bytes      ((uint32_t)0x00000010)  /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_ReceiveThresholdControl_128Bytes     ((uint32_t)0x00000018)  /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \
+                                                     ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \
+                                                     ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \
+                                                     ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Second_Frame_Operate 
+  * @{
+  */ 
+#define ETH_SecondFrameOperate_Enable       ((uint32_t)0x00000004)
+#define ETH_SecondFrameOperate_Disable      ((uint32_t)0x00000000)  
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \
+                                          ((CMD) == ETH_SecondFrameOperate_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Address_Aligned_Beats 
+  * @{
+  */ 
+#define ETH_AddressAlignedBeats_Enable      ((uint32_t)0x02000000)
+#define ETH_AddressAlignedBeats_Disable     ((uint32_t)0x00000000) 
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \
+                                           ((CMD) == ETH_AddressAlignedBeats_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Fixed_Burst 
+  * @{
+  */ 
+#define ETH_FixedBurst_Enable     ((uint32_t)0x00010000)
+#define ETH_FixedBurst_Disable    ((uint32_t)0x00000000) 
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \
+                                 ((CMD) == ETH_FixedBurst_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_DMA_Burst_Length 
+  * @{
+  */ 
+#define ETH_RxDMABurstLength_1Beat          ((uint32_t)0x00020000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_RxDMABurstLength_2Beat          ((uint32_t)0x00040000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_RxDMABurstLength_4Beat          ((uint32_t)0x00080000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RxDMABurstLength_8Beat          ((uint32_t)0x00100000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RxDMABurstLength_16Beat         ((uint32_t)0x00200000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RxDMABurstLength_32Beat         ((uint32_t)0x00400000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+#define ETH_RxDMABurstLength_4xPBL_4Beat    ((uint32_t)0x01020000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RxDMABurstLength_4xPBL_8Beat    ((uint32_t)0x01040000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RxDMABurstLength_4xPBL_16Beat   ((uint32_t)0x01080000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RxDMABurstLength_4xPBL_32Beat   ((uint32_t)0x01100000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RxDMABurstLength_4xPBL_64Beat   ((uint32_t)0x01200000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_RxDMABurstLength_4xPBL_128Beat  ((uint32_t)0x01400000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat))
+ 
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_DMA_Burst_Length 
+  * @{
+  */ 
+#define ETH_TxDMABurstLength_1Beat          ((uint32_t)0x00000100)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_TxDMABurstLength_2Beat          ((uint32_t)0x00000200)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_TxDMABurstLength_4Beat          ((uint32_t)0x00000400)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TxDMABurstLength_8Beat          ((uint32_t)0x00000800)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TxDMABurstLength_16Beat         ((uint32_t)0x00001000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TxDMABurstLength_32Beat         ((uint32_t)0x00002000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+#define ETH_TxDMABurstLength_4xPBL_4Beat    ((uint32_t)0x01000100)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TxDMABurstLength_4xPBL_8Beat    ((uint32_t)0x01000200)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TxDMABurstLength_4xPBL_16Beat   ((uint32_t)0x01000400)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TxDMABurstLength_4xPBL_32Beat   ((uint32_t)0x01000800)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TxDMABurstLength_4xPBL_64Beat   ((uint32_t)0x01001000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_TxDMABurstLength_4xPBL_128Beat  ((uint32_t)0x01002000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat))
+/** 
+  * @brief  ETH DMA Desciptor SkipLength  
+  */ 
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Arbitration 
+  * @{
+  */ 
+#define ETH_DMAArbitration_RoundRobin_RxTx_1_1   ((uint32_t)0x00000000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_2_1   ((uint32_t)0x00004000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_3_1   ((uint32_t)0x00008000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_4_1   ((uint32_t)0x0000C000)
+#define ETH_DMAArbitration_RxPriorTx             ((uint32_t)0x00000002)
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \
+                                                       ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \
+                                                       ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \
+                                                       ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \
+                                                       ((RATIO) == ETH_DMAArbitration_RxPriorTx))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Flags 
+  * @{
+  */ 
+#define ETH_DMA_FLAG_TST               ((uint32_t)0x20000000)  /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_FLAG_PMT               ((uint32_t)0x10000000)  /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_FLAG_MMC               ((uint32_t)0x08000000)  /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000)  /*!< Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMA_FLAG_ReadWriteError    ((uint32_t)0x01000000)  /*!< Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMA_FLAG_AccessError       ((uint32_t)0x02000000)  /*!< Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMA_FLAG_NIS               ((uint32_t)0x00010000)  /*!< Normal interrupt summary flag */
+#define ETH_DMA_FLAG_AIS               ((uint32_t)0x00008000)  /*!< Abnormal interrupt summary flag */
+#define ETH_DMA_FLAG_ER                ((uint32_t)0x00004000)  /*!< Early receive flag */
+#define ETH_DMA_FLAG_FBE               ((uint32_t)0x00002000)  /*!< Fatal bus error flag */
+#define ETH_DMA_FLAG_ET                ((uint32_t)0x00000400)  /*!< Early transmit flag */
+#define ETH_DMA_FLAG_RWT               ((uint32_t)0x00000200)  /*!< Receive watchdog timeout flag */
+#define ETH_DMA_FLAG_RPS               ((uint32_t)0x00000100)  /*!< Receive process stopped flag */
+#define ETH_DMA_FLAG_RBU               ((uint32_t)0x00000080)  /*!< Receive buffer unavailable flag */
+#define ETH_DMA_FLAG_R                 ((uint32_t)0x00000040)  /*!< Receive flag */
+#define ETH_DMA_FLAG_TU                ((uint32_t)0x00000020)  /*!< Underflow flag */
+#define ETH_DMA_FLAG_RO                ((uint32_t)0x00000010)  /*!< Overflow flag */
+#define ETH_DMA_FLAG_TJT               ((uint32_t)0x00000008)  /*!< Transmit jabber timeout flag */
+#define ETH_DMA_FLAG_TBU               ((uint32_t)0x00000004)  /*!< Transmit buffer unavailable flag */
+#define ETH_DMA_FLAG_TPS               ((uint32_t)0x00000002)  /*!< Transmit process stopped flag */
+#define ETH_DMA_FLAG_T                 ((uint32_t)0x00000001)  /*!< Transmit flag */
+
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) 
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
+                                   ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \
+                                   ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \
+                                   ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
+                                   ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
+                                   ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
+                                   ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
+                                   ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
+                                   ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
+                                   ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
+                                   ((FLAG) == ETH_DMA_FLAG_T))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Interrupts 
+  * @{
+  */ 
+#define ETH_DMA_INT_TST       ((uint32_t)0x20000000)  /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_INT_PMT       ((uint32_t)0x10000000)  /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_INT_MMC       ((uint32_t)0x08000000)  /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_INT_NIS       ((uint32_t)0x00010000)  /*!< Normal interrupt summary */
+#define ETH_DMA_INT_AIS       ((uint32_t)0x00008000)  /*!< Abnormal interrupt summary */
+#define ETH_DMA_INT_ER        ((uint32_t)0x00004000)  /*!< Early receive interrupt */
+#define ETH_DMA_INT_FBE       ((uint32_t)0x00002000)  /*!< Fatal bus error interrupt */
+#define ETH_DMA_INT_ET        ((uint32_t)0x00000400)  /*!< Early transmit interrupt */
+#define ETH_DMA_INT_RWT       ((uint32_t)0x00000200)  /*!< Receive watchdog timeout interrupt */
+#define ETH_DMA_INT_RPS       ((uint32_t)0x00000100)  /*!< Receive process stopped interrupt */
+#define ETH_DMA_INT_RBU       ((uint32_t)0x00000080)  /*!< Receive buffer unavailable interrupt */
+#define ETH_DMA_INT_R         ((uint32_t)0x00000040)  /*!< Receive interrupt */
+#define ETH_DMA_INT_TU        ((uint32_t)0x00000020)  /*!< Underflow interrupt */
+#define ETH_DMA_INT_RO        ((uint32_t)0x00000010)  /*!< Overflow interrupt */
+#define ETH_DMA_INT_TJT       ((uint32_t)0x00000008)  /*!< Transmit jabber timeout interrupt */
+#define ETH_DMA_INT_TBU       ((uint32_t)0x00000004)  /*!< Transmit buffer unavailable interrupt */
+#define ETH_DMA_INT_TPS       ((uint32_t)0x00000002)  /*!< Transmit process stopped interrupt */
+#define ETH_DMA_INT_T         ((uint32_t)0x00000001)  /*!< Transmit interrupt */
+
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_INT_TST) || ((IT) == ETH_DMA_INT_PMT) || \
+                               ((IT) == ETH_DMA_INT_MMC) || ((IT) == ETH_DMA_INT_NIS) || \
+                               ((IT) == ETH_DMA_INT_AIS) || ((IT) == ETH_DMA_INT_ER) || \
+                               ((IT) == ETH_DMA_INT_FBE) || ((IT) == ETH_DMA_INT_ET) || \
+                               ((IT) == ETH_DMA_INT_RWT) || ((IT) == ETH_DMA_INT_RPS) || \
+                               ((IT) == ETH_DMA_INT_RBU) || ((IT) == ETH_DMA_INT_R) || \
+                               ((IT) == ETH_DMA_INT_TU) || ((IT) == ETH_DMA_INT_RO) || \
+                               ((IT) == ETH_DMA_INT_TJT) || ((IT) == ETH_DMA_INT_TBU) || \
+                               ((IT) == ETH_DMA_INT_TPS) || ((IT) == ETH_DMA_INT_T))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_transmit_process_state_ 
+  * @{
+  */ 
+#define ETH_DMA_TransmitProcess_Stopped     ((uint32_t)0x00000000)  /*!< Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMA_TransmitProcess_Fetching    ((uint32_t)0x00100000)  /*!< Running - fetching the Tx descriptor */
+#define ETH_DMA_TransmitProcess_Waiting     ((uint32_t)0x00200000)  /*!< Running - waiting for status */
+#define ETH_DMA_TransmitProcess_Reading     ((uint32_t)0x00300000)  /*!< Running - reading the data from host memory */
+#define ETH_DMA_TransmitProcess_Suspended   ((uint32_t)0x00600000)  /*!< Suspended - Tx Desciptor unavailabe */
+#define ETH_DMA_TransmitProcess_Closing     ((uint32_t)0x00700000)  /*!< Running - closing Rx descriptor */
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ETH_DMA_receive_process_state_ 
+  * @{
+  */ 
+#define ETH_DMA_ReceiveProcess_Stopped      ((uint32_t)0x00000000)  /*!< Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMA_ReceiveProcess_Fetching     ((uint32_t)0x00020000)  /*!< Running - fetching the Rx descriptor */
+#define ETH_DMA_ReceiveProcess_Waiting      ((uint32_t)0x00060000)  /*!< Running - waiting for packet */
+#define ETH_DMA_ReceiveProcess_Suspended    ((uint32_t)0x00080000)  /*!< Suspended - Rx Desciptor unavailable */
+#define ETH_DMA_ReceiveProcess_Closing      ((uint32_t)0x000A0000)  /*!< Running - closing descriptor */
+#define ETH_DMA_ReceiveProcess_Queuing      ((uint32_t)0x000E0000)  /*!< Running - queuing the recieve frame into host memory */
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_overflow_ 
+  * @{
+  */ 
+#define ETH_DMA_Overflow_RxFIFOCounter      ((uint32_t)0x10000000)  /*!< Overflow bit for FIFO overflow counter */
+#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000)  /*!< Overflow bit for missed frame counter */
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \
+                                           ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter))
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                           Ethernet PMT defines
+  */ 
+/**--------------------------------------------------------------------------**/
+/**
+  * @}
+  */
+
+/** @defgroup ETH_PMT_Flags 
+  * @{
+  */ 
+#define ETH_PMT_FLAG_WUFFRPR      ((uint32_t)0x80000000)  /*!< Wake-Up Frame Filter Register Poniter Reset */
+#define ETH_PMT_FLAG_WUFR         ((uint32_t)0x00000040)  /*!< Wake-Up Frame Received */
+#define ETH_PMT_FLAG_MPR          ((uint32_t)0x00000020)  /*!< Magic Packet Received */
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
+                                   ((FLAG) == ETH_PMT_FLAG_MPR))
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                           Ethernet MMC defines
+  */ 
+/**--------------------------------------------------------------------------**/
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MMC_Tx_Interrupts 
+  * @{
+  */ 
+#define ETH_MMC_INT_TGF       ((uint32_t)0x00200000)  /*!< When Tx good frame counter reaches half the maximum value */
+#define ETH_MMC_INT_TGFMSC    ((uint32_t)0x00008000)  /*!< When Tx good multi col counter reaches half the maximum value */
+#define ETH_MMC_INT_TGFSC     ((uint32_t)0x00004000)  /*!< When Tx good single col counter reaches half the maximum value */
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MMC_Rx_Interrupts 
+  * @{
+  */
+#define ETH_MMC_INT_RGUF      ((uint32_t)0x10020000)  /*!< When Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMC_INT_RFAE      ((uint32_t)0x10000040)  /*!< When Rx alignment error counter reaches half the maximum value */
+#define ETH_MMC_INT_RFCE      ((uint32_t)0x10000020)  /*!< When Rx crc error counter reaches half the maximum value */
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
+                           ((IT) != 0x00))
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_INT_TGF) || ((IT) == ETH_MMC_INT_TGFMSC) || \
+                               ((IT) == ETH_MMC_INT_TGFSC) || ((IT) == ETH_MMC_INT_RGUF) || \
+                               ((IT) == ETH_MMC_INT_RFAE) || ((IT) == ETH_MMC_INT_RFCE))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MMC_Registers 
+  * @{
+  */ 
+#define ETH_MMCCR            ((uint32_t)0x00000100)  /*!< MMC CR register */
+#define ETH_MMCRIR           ((uint32_t)0x00000104)  /*!< MMC RIR register */
+#define ETH_MMCTIR           ((uint32_t)0x00000108)  /*!< MMC TIR register */
+#define ETH_MMCRIMR          ((uint32_t)0x0000010C)  /*!< MMC RIMR register */
+#define ETH_MMCTIMR          ((uint32_t)0x00000110)  /*!< MMC TIMR register */ 
+#define ETH_MMCTGFSCCR       ((uint32_t)0x0000014C)  /*!< MMC TGFSCCR register */
+#define ETH_MMCTGFMSCCR      ((uint32_t)0x00000150)  /*!< MMC TGFMSCCR register */ 
+#define ETH_MMCTGFCR         ((uint32_t)0x00000168)  /*!< MMC TGFCR register */
+#define ETH_MMCRFCECR        ((uint32_t)0x00000194)  /*!< MMC RFCECR register */
+#define ETH_MMCRFAECR        ((uint32_t)0x00000198)  /*!< MMC RFAECR register */
+#define ETH_MMCRGUFCR        ((uint32_t)0x000001C4)  /*!< MMC RGUFCR register */
+
+/** 
+  * @brief  ETH MMC registers  
+  */ 
+#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR)  || ((REG) == ETH_MMCRIR) || \
+                                  ((REG) == ETH_MMCTIR)  || ((REG) == ETH_MMCRIMR) || \
+                                  ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
+                                  ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
+                                  ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
+                                  ((REG) == ETH_MMCRGUFCR)) 
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                           Ethernet PTP defines
+  */ 
+/**--------------------------------------------------------------------------**/
+/**
+  * @}
+  */
+
+/** @defgroup ETH_PTP_time_update_method 
+  * @{
+  */ 
+#define ETH_PTP_FineUpdate        ((uint32_t)0x00000001)  /*!< Fine Update method */
+#define ETH_PTP_CoarseUpdate      ((uint32_t)0x00000000)  /*!< Coarse Update method */
+#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \
+                                   ((UPDATE) == ETH_PTP_CoarseUpdate))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ETH_PTP_Flags 
+  * @{
+  */ 
+#define ETH_PTP_FLAG_TSARU        ((uint32_t)0x00000020)  /*!< Addend Register Update */
+#define ETH_PTP_FLAG_TSITE        ((uint32_t)0x00000010)  /*!< Time Stamp Interrupt Trigger */
+#define ETH_PTP_FLAG_TSSTU        ((uint32_t)0x00000008)  /*!< Time Stamp Update */
+#define ETH_PTP_FLAG_TSSTI        ((uint32_t)0x00000004)  /*!< Time Stamp Initialize */
+#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \
+                                   ((FLAG) == ETH_PTP_FLAG_TSITE) || \
+                                   ((FLAG) == ETH_PTP_FLAG_TSSTU) || \
+                                   ((FLAG) == ETH_PTP_FLAG_TSSTI))
+/** 
+  * @brief  ETH PTP subsecond increment  
+  */ 
+#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF)
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ETH_PTP_time_sign 
+  * @{
+  */ 
+#define ETH_PTP_PositiveTime      ((uint32_t)0x00000000)  /*!< Positive time value */
+#define ETH_PTP_NegativeTime      ((uint32_t)0x80000000)  /*!< Negative time value */
+#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \
+                                    ((SIGN) == ETH_PTP_NegativeTime))
+
+/** 
+  * @brief  ETH PTP time stamp low update  
+  */ 
+#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF)
+
+/** 
+  * @brief  ETH PTP registers  
+  */ 
+#define ETH_PTPTSCR     ((uint32_t)0x00000700)  /*!< PTP TSCR register */
+#define ETH_PTPSSIR     ((uint32_t)0x00000704)  /*!< PTP SSIR register */
+#define ETH_PTPTSHR     ((uint32_t)0x00000708)  /*!< PTP TSHR register */
+#define ETH_PTPTSLR     ((uint32_t)0x0000070C)  /*!< PTP TSLR register */
+#define ETH_PTPTSHUR    ((uint32_t)0x00000710)  /*!< PTP TSHUR register */
+#define ETH_PTPTSLUR    ((uint32_t)0x00000714)  /*!< PTP TSLUR register */
+#define ETH_PTPTSAR     ((uint32_t)0x00000718)  /*!< PTP TSAR register */
+#define ETH_PTPTTHR     ((uint32_t)0x0000071C)  /*!< PTP TTHR register */
+#define ETH_PTPTTLR     ((uint32_t)0x00000720)  /* PTP TTLR register */
+#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \
+                                  ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \
+                                  ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \
+                                  ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \
+                                  ((REG) == ETH_PTPTTLR)) 
+
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Exported_Functions
+  * @{
+  */ 
+void ETH_DeInit(void);
+uint32_t ETH_Init(ETH_InitType* ETH_InitStruct, u16 PHYAddress);
+void ETH_StructInit(ETH_InitType* ETH_InitStruct);
+void ETH_SoftwareReset(void);
+FlagStatus ETH_GetSoftwareResetStatus(void);
+void  ETH_Start(void);
+uint32_t ETH_HandleTxPkt(u8 *ppkt, u16 FrameLength);
+uint32_t ETH_HandleRxPkt(u8 *ppkt);
+uint32_t ETH_GetRxPktSize(void);
+void ETH_DropRxPkt(void);
+
+/** 
+  * @brief  PHY  
+  */ 
+u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg);
+uint32_t ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue);
+uint32_t ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState);
+
+/** 
+  * @brief  MAC  
+  */ 
+void ETH_MACTransmissionCmd(FunctionalState NewState);
+void ETH_MACReceptionCmd(FunctionalState NewState);
+FlagStatus ETH_GetFlowControlBusyStatus(void);
+void ETH_InitiatePauseControlFrame(void);  
+void ETH_BackPressureActivationCmd(FunctionalState NewState); 
+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG);  
+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT);
+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState);
+void ETH_MACAddressConfig(uint32_t MacAddr, u8 *Addr);
+void ETH_GetMACAddress(uint32_t MacAddr, u8 *Addr);
+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState);
+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter);
+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte);
+
+/** 
+  * @brief  DMA Tx/Rx descriptors  
+  */ 
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, uint32_t TxBuffCount);
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, uint32_t TxBuffCount);
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag);
+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment);
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum);
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2);
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, uint32_t RxBuffCount);
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, uint32_t RxBuffCount);
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag);
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);
+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer);
+
+/** 
+  * @brief  DMA
+  */ 
+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG);
+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG);
+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT);
+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT);
+uint32_t ETH_GetTransmitProcessState(void);
+uint32_t ETH_GetReceiveProcessState(void);
+void ETH_FlushTransmitFIFO(void);
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
+void ETH_DMATransmissionCmd(FunctionalState NewState);
+void ETH_DMAReceptionCmd(FunctionalState NewState);
+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState);
+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow);
+uint32_t ETH_GetRxOverflowMissedFrameCounter(void);
+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void);
+uint32_t ETH_GetCurrentTxDescStartAddress(void);
+uint32_t ETH_GetCurrentRxDescStartAddress(void);
+uint32_t ETH_GetCurrentTxBufferAddress(void);
+uint32_t ETH_GetCurrentRxBufferAddress(void);
+void ETH_ResumeDMATransmission(void);
+void ETH_ResumeDMAReception(void);
+
+/** 
+  * @brief  PMT  
+  */ 
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer);
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);
+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG);
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState);
+void ETH_PowerDownCmd(FunctionalState NewState);
+
+/** 
+  * @brief  MMC  
+  */ 
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState);
+void ETH_MMCResetOnReadCmd(FunctionalState NewState);
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState);
+void ETH_MMCCountersReset(void);
+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState);
+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT);
+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg);
+
+/** 
+  * @brief  PTP  
+  */ 
+uint32_t ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, uint32_t *PTPTxTab);
+uint32_t ETH_HandlePTPRxPkt(u8 *ppkt, uint32_t *PTPRxTab);
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, uint32_t TxBuffCount);
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, uint32_t RxBuffCount);
+void ETH_EnablePTPTimeStampAddend(void);
+void ETH_EnablePTPTimeStampInterruptTrigger(void);
+void ETH_EnablePTPTimeStampUpdate(void);
+void ETH_InitializePTPTimeStamp(void);
+void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod);
+void ETH_PTPTimeStampCmd(FunctionalState NewState);
+FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG);
+void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue);
+void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue);
+void ETH_SetPTPTimeStampAddend(uint32_t Value);
+void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue);
+uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_ETH_H */
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2009 Artery Technology *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_exti.h

@@ -0,0 +1,191 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_exti.h
+ * Description  : at32f4xx EXTI header file
+ * Date         : 2019-06-04
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_EXTI_H
+#define __AT32F4xx_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+
+/** @defgroup EXTI_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  EXTI mode enumeration
+  */
+
+typedef enum
+{
+    EXTI_Mode_Interrupt = 0x00,
+    EXTI_Mode_Event = 0x04
+} EXTIMode_Type;
+
+#define IS_EXTI_MODE(MODE)                  (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+  * @brief  EXTI Trigger enumeration
+  */
+
+typedef enum
+{
+    EXTI_Trigger_Rising = 0x08,
+    EXTI_Trigger_Falling = 0x0C,
+    EXTI_Trigger_Rising_Falling = 0x10
+} EXTITrigger_Type;
+
+#define IS_EXTI_TRIGGER(TRIGGER)            (((TRIGGER) == EXTI_Trigger_Rising) || \
+                                             ((TRIGGER) == EXTI_Trigger_Falling) || \
+                                             ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+  * @brief  EXTI Init Structure definition
+  */
+
+typedef struct
+{
+    uint32_t EXTI_Line;                     /*!< Specifies the EXTI lines to be enabled or disabled.
+                                                  This parameter can be any combination of @ref EXTI_Lines */
+                                            
+    EXTIMode_Type EXTI_Mode;                /*!< Specifies the mode for the EXTI lines.
+                                                  This parameter can be a value of @ref EXTIMode_Type */
+                                            
+    EXTITrigger_Type EXTI_Trigger;          /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                                  This parameter can be a value of @ref EXTIMode_Type */
+
+    FunctionalState EXTI_LineEnable;        /*!< Specifies the new state of the selected EXTI lines.
+                                                  This parameter can be set either to ENABLE or DISABLE */
+} EXTI_InitType;
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Lines
+  * @{
+  */
+
+#define EXTI_Line0                          ((uint32_t)0x000001)  /*!< External interrupt line 0 */
+#define EXTI_Line1                          ((uint32_t)0x000002)  /*!< External interrupt line 1 */
+#define EXTI_Line2                          ((uint32_t)0x000004)  /*!< External interrupt line 2 */
+#define EXTI_Line3                          ((uint32_t)0x000008)  /*!< External interrupt line 3 */
+#define EXTI_Line4                          ((uint32_t)0x000010)  /*!< External interrupt line 4 */
+#define EXTI_Line5                          ((uint32_t)0x000020)  /*!< External interrupt line 5 */
+#define EXTI_Line6                          ((uint32_t)0x000040)  /*!< External interrupt line 6 */
+#define EXTI_Line7                          ((uint32_t)0x000080)  /*!< External interrupt line 7 */
+#define EXTI_Line8                          ((uint32_t)0x000100)  /*!< External interrupt line 8 */
+#define EXTI_Line9                          ((uint32_t)0x000200)  /*!< External interrupt line 9 */
+#define EXTI_Line10                         ((uint32_t)0x000400)  /*!< External interrupt line 10 */
+#define EXTI_Line11                         ((uint32_t)0x000800)  /*!< External interrupt line 11 */
+#define EXTI_Line12                         ((uint32_t)0x001000)  /*!< External interrupt line 12 */
+#define EXTI_Line13                         ((uint32_t)0x002000)  /*!< External interrupt line 13 */
+#define EXTI_Line14                         ((uint32_t)0x004000)  /*!< External interrupt line 14 */
+#define EXTI_Line15                         ((uint32_t)0x008000)  /*!< External interrupt line 15 */
+#define EXTI_Line16                         ((uint32_t)0x010000)  /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17                         ((uint32_t)0x020000)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18                         ((uint32_t)0x040000)  /*!< External interrupt line 18 Connected to the USB Device FS
+                                                                      Wakeup from suspend event */
+#define EXTI_Line19                         ((uint32_t)0x080000)  /*!< External interrupt line 19 Connected to the COMP1*/
+#ifdef AT32F415xx
+  #define EXTI_Line20                         ((uint32_t)0x100000)  /*!< External interrupt line 20 Connected to the COMP2*/
+  #define EXTI_Line21                         ((uint32_t)0x200000)  /*!< External interrupt line 20 Connected to the RTC Temper_Pin and Temper_Stamp*/
+  #define EXTI_Line22                         ((uint32_t)0x400000)  /*!< External interrupt line 20 Connected to the RTC Wakeup*/
+
+  #define IS_EXTI_LINE(LINE)                  ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
+  #define IS_GET_EXTI_LINE(LINE)              (((LINE) == EXTI_Line0)  || ((LINE) == EXTI_Line1) || \
+                                             ((LINE) == EXTI_Line2)  || ((LINE) == EXTI_Line3) || \
+                                             ((LINE) == EXTI_Line4)  || ((LINE) == EXTI_Line5) || \
+                                             ((LINE) == EXTI_Line6)  || ((LINE) == EXTI_Line7) || \
+                                             ((LINE) == EXTI_Line8)  || ((LINE) == EXTI_Line9) || \
+                                             ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+                                             ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+                                             ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+                                             ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+                                             ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
+                                             ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
+                                             ((LINE) == EXTI_Line22))
+#else
+  #define IS_EXTI_LINE(LINE)                  ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
+  #define IS_GET_EXTI_LINE(LINE)              (((LINE) == EXTI_Line0)  || ((LINE) == EXTI_Line1) || \
+                                             ((LINE) == EXTI_Line2)  || ((LINE) == EXTI_Line3) || \
+                                             ((LINE) == EXTI_Line4)  || ((LINE) == EXTI_Line5) || \
+                                             ((LINE) == EXTI_Line6)  || ((LINE) == EXTI_Line7) || \
+                                             ((LINE) == EXTI_Line8)  || ((LINE) == EXTI_Line9) || \
+                                             ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+                                             ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+                                             ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+                                             ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+                                             ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
+#endif
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions
+  * @{
+  */
+
+void EXTI_Reset(void);
+void EXTI_Init(EXTI_InitType* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitType* EXTI_InitStruct);
+void EXTI_GenerateSWInt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetIntStatus(uint32_t EXTI_Line);
+void EXTI_ClearIntPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_EXTI_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_flash.h

@@ -0,0 +1,428 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_flash.h
+ * Description  : at32f4xx FMC header file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_FLASH_H
+#define __AT32F4xx_FLASH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/** @defgroup FLASH_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Status
+  */
+
+typedef enum
+{
+    FLASH_BSY = 1,
+    FLASH_PGRM_FLR,
+    FLASH_WRPRT_FLR,
+    FLASH_PRC_DONE,
+    FLASH_TIMEOUT
+} FLASH_Status;
+
+/**
+  * @brief  BANK3 SEL
+  */
+
+typedef enum
+{
+    E_BANK3_SEL_ESMT_SP=0,
+    E_BANK3_SEL_GENERAL_CFGQE,
+    E_BANK3_SEL_GENERAL,
+}T_BANK3_SEL;
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Option_Bytes_Write_Protection
+  * @{
+  */
+
+/* Values to be used with AT32F4xx Medium-density devices */
+#define FLASH_WRPRT_PAGE_0to3               ((uint32_t)0x00000001) /*!< AT32F4xx Medium-density devices: Write protection of page 0 to 3 */
+#define FLASH_WRPRT_PAGE_4to7               ((uint32_t)0x00000002) /*!< AT32F4xx Medium-density devices: Write protection of page 4 to 7 */
+#define FLASH_WRPRT_PAGE_8to11              ((uint32_t)0x00000004) /*!< AT32F4xx Medium-density devices: Write protection of page 8 to 11 */
+#define FLASH_WRPRT_PAGE_12to15             ((uint32_t)0x00000008) /*!< AT32F4xx Medium-density devices: Write protection of page 12 to 15 */
+#define FLASH_WRPRT_PAGE_16to19             ((uint32_t)0x00000010) /*!< AT32F4xx Medium-density devices: Write protection of page 16 to 19 */
+#define FLASH_WRPRT_PAGE_20to23             ((uint32_t)0x00000020) /*!< AT32F4xx Medium-density devices: Write protection of page 20 to 23 */
+#define FLASH_WRPRT_PAGE_24to27             ((uint32_t)0x00000040) /*!< AT32F4xx Medium-density devices: Write protection of page 24 to 27 */
+#define FLASH_WRPRT_PAGE_28to31             ((uint32_t)0x00000080) /*!< AT32F4xx Medium-density devices: Write protection of page 28 to 31 */
+#define FLASH_WRPRT_PAGE_32to35             ((uint32_t)0x00000100) /*!< AT32F4xx Medium-density devices: Write protection of page 32 to 35 */
+#define FLASH_WRPRT_PAGE_36to39             ((uint32_t)0x00000200) /*!< AT32F4xx Medium-density devices: Write protection of page 36 to 39 */
+#define FLASH_WRPRT_PAGE_40to43             ((uint32_t)0x00000400) /*!< AT32F4xx Medium-density devices: Write protection of page 40 to 43 */
+#define FLASH_WRPRT_PAGE_44to47             ((uint32_t)0x00000800) /*!< AT32F4xx Medium-density devices: Write protection of page 44 to 47 */
+#define FLASH_WRPRT_PAGE_48to51             ((uint32_t)0x00001000) /*!< AT32F4xx Medium-density devices: Write protection of page 48 to 51 */
+#define FLASH_WRPRT_PAGE_52to55             ((uint32_t)0x00002000) /*!< AT32F4xx Medium-density devices: Write protection of page 52 to 55 */
+#define FLASH_WRPRT_PAGE_56to59             ((uint32_t)0x00004000) /*!< AT32F4xx Medium-density devices: Write protection of page 56 to 59 */
+#define FLASH_WRPRT_PAGE_60to63             ((uint32_t)0x00008000) /*!< AT32F4xx Medium-density devices: Write protection of page 60 to 63 */
+#define FLASH_WRPRT_PAGE_64to67             ((uint32_t)0x00010000) /*!< AT32F4xx Medium-density devices: Write protection of page 64 to 67 */
+#define FLASH_WRPRT_PAGE_68to71             ((uint32_t)0x00020000) /*!< AT32F4xx Medium-density devices: Write protection of page 68 to 71 */
+#define FLASH_WRPRT_PAGE_72to75             ((uint32_t)0x00040000) /*!< AT32F4xx Medium-density devices: Write protection of page 72 to 75 */
+#define FLASH_WRPRT_PAGE_76to79             ((uint32_t)0x00080000) /*!< AT32F4xx Medium-density devices: Write protection of page 76 to 79 */
+#define FLASH_WRPRT_PAGE_80to83             ((uint32_t)0x00100000) /*!< AT32F4xx Medium-density devices: Write protection of page 80 to 83 */
+#define FLASH_WRPRT_PAGE_84to87             ((uint32_t)0x00200000) /*!< AT32F4xx Medium-density devices: Write protection of page 84 to 87 */
+#define FLASH_WRPRT_PAGE_88to91             ((uint32_t)0x00400000) /*!< AT32F4xx Medium-density devices: Write protection of page 88 to 91 */
+#define FLASH_WRPRT_PAGE_92to95             ((uint32_t)0x00800000) /*!< AT32F4xx Medium-density devices: Write protection of page 92 to 95 */
+#define FLASH_WRPRT_PAGE_96to99             ((uint32_t)0x01000000) /*!< AT32F4xx Medium-density devices: Write protection of page 96 to 99 */
+#define FLASH_WRPRT_PAGE_100to103           ((uint32_t)0x02000000) /*!< AT32F4xx Medium-density devices: Write protection of page 100 to 103 */
+#define FLASH_WRPRT_PAGE_104to107           ((uint32_t)0x04000000) /*!< AT32F4xx Medium-density devices: Write protection of page 104 to 107 */
+#define FLASH_WRPRT_PAGE_108to111           ((uint32_t)0x08000000) /*!< AT32F4xx Medium-density devices: Write protection of page 108 to 111 */
+#define FLASH_WRPRT_PAGE_112to115           ((uint32_t)0x10000000) /*!< AT32F4xx Medium-density devices: Write protection of page 112 to 115 */
+#define FLASH_WRPRT_PAGE_116to119           ((uint32_t)0x20000000) /*!< AT32F4xx Medium-density devices: Write protection of page 115 to 119 */
+#define FLASH_WRPRT_PAGE_120to123           ((uint32_t)0x40000000) /*!< AT32F4xx Medium-density devices: Write protection of page 120 to 123 */
+#define FLASH_WRPRT_PAGE_124to127           ((uint32_t)0x80000000) /*!< AT32F4xx Medium-density devices: Write protection of page 124 to 127 */
+
+/* Values to be used with AT32F4xx High-density, XL-density and AT32F415xx devices */
+#define FLASH_WRPRT_PAGE_0to1               ((uint32_t)0x00000001) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 0 to 1 */
+#define FLASH_WRPRT_PAGE_2to3               ((uint32_t)0x00000002) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 2 to 3 */
+#define FLASH_WRPRT_PAGE_4to5               ((uint32_t)0x00000004) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 4 to 5 */
+#define FLASH_WRPRT_PAGE_6to7               ((uint32_t)0x00000008) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 6 to 7 */
+#define FLASH_WRPRT_PAGE_8to9               ((uint32_t)0x00000010) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 8 to 9 */
+#define FLASH_WRPRT_PAGE_10to11             ((uint32_t)0x00000020) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 10 to 11 */
+#define FLASH_WRPRT_PAGE_12to13             ((uint32_t)0x00000040) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 12 to 13 */
+#define FLASH_WRPRT_PAGE_14to15             ((uint32_t)0x00000080) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 14 to 15 */
+#define FLASH_WRPRT_PAGE_16to17             ((uint32_t)0x00000100) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 16 to 17 */
+#define FLASH_WRPRT_PAGE_18to19             ((uint32_t)0x00000200) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 18 to 19 */
+#define FLASH_WRPRT_PAGE_20to21             ((uint32_t)0x00000400) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 20 to 21 */
+#define FLASH_WRPRT_PAGE_22to23             ((uint32_t)0x00000800) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 22 to 23 */
+#define FLASH_WRPRT_PAGE_24to25             ((uint32_t)0x00001000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 24 to 25 */
+#define FLASH_WRPRT_PAGE_26to27             ((uint32_t)0x00002000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 26 to 27 */
+#define FLASH_WRPRT_PAGE_28to29             ((uint32_t)0x00004000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 28 to 29 */
+#define FLASH_WRPRT_PAGE_30to31             ((uint32_t)0x00008000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 30 to 31 */
+#define FLASH_WRPRT_PAGE_32to33             ((uint32_t)0x00010000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 32 to 33 */
+#define FLASH_WRPRT_PAGE_34to35             ((uint32_t)0x00020000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 34 to 35 */
+#define FLASH_WRPRT_PAGE_36to37             ((uint32_t)0x00040000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 36 to 37 */
+#define FLASH_WRPRT_PAGE_38to39             ((uint32_t)0x00080000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 38 to 39 */
+#define FLASH_WRPRT_PAGE_40to41             ((uint32_t)0x00100000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 40 to 41 */
+#define FLASH_WRPRT_PAGE_42to43             ((uint32_t)0x00200000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 42 to 43 */
+#define FLASH_WRPRT_PAGE_44to45             ((uint32_t)0x00400000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 44 to 45 */
+#define FLASH_WRPRT_PAGE_46to47             ((uint32_t)0x00800000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 46 to 47 */
+#define FLASH_WRPRT_PAGE_48to49             ((uint32_t)0x01000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 48 to 49 */
+#define FLASH_WRPRT_PAGE_50to51             ((uint32_t)0x02000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 50 to 51 */
+#define FLASH_WRPRT_PAGE_52to53             ((uint32_t)0x04000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 52 to 53 */
+#define FLASH_WRPRT_PAGE_54to55             ((uint32_t)0x08000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 54 to 55 */
+#define FLASH_WRPRT_PAGE_56to57             ((uint32_t)0x10000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 56 to 57 */
+#define FLASH_WRPRT_PAGE_58to59             ((uint32_t)0x20000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 58 to 59 */
+#define FLASH_WRPRT_PAGE_60to61             ((uint32_t)0x40000000) /*!< AT32F4xx High-density, XL-density and AT32F415xx devices:
+                                                                         Write protection of page 60 to 61 */
+																		 
+#define FLASH_WRPRT_PAGE_62to63             ((uint32_t)0x80000000) /*!< AT32F415xx Medium-density devices: Write protection of page 62 to 63 */                                                                         
+#define FLASH_WRPRT_PAGE_62to127            ((uint32_t)0x80000000) /*!< AT32F4xx High-density, AT32F415xx Medium-density, High-density devices:
+                                                                         Write protection of page 62 to 127 */
+#define FLASH_WRPRT_PAGE_62to255            ((uint32_t)0x80000000) /*!< AT32F4xx High-density devices: Write protection of page 62 to 255 */                                                                         
+#define FLASH_WRPRT_PAGE_62to511            ((uint32_t)0x80000000) /*!< AT32F4xx XL-density devices: Write protection of page 62 to 511 */
+                                            
+#define FLASH_WRPRT_AllPAGES                ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+                                            
+#define IS_FLASH_WRPRT_PAGES(PAGES)         (((PAGES) != 0x00000000))
+                                            
+#define IS_FLASH_ADDR(ADDR)                 (((ADDR) >= 0x08000000) && ((ADDR) <= FLASH_BANK3_ADDR_MAX))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_IWatchdog
+  * @{
+  */
+
+#define UOB_SW_IWDG                         ((uint16_t)0x0001)  /*!< Software IWDG selected */
+#define UOB_HW_IWDG                         ((uint16_t)0x0000)  /*!< Hardware IWDG selected */
+#define IS_UOB_IWDG_CFG(CFG)                (((CFG) == UOB_SW_IWDG) || ((CFG) == UOB_HW_IWDG))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_nRST_STOP
+  * @{
+  */
+
+#define UOB_NO_RST_STP                      ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
+#define UOB_RST_STP                         ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
+#define IS_UOB_STOP_CFG(CFG)                (((CFG) == UOB_NO_RST_STP) || ((CFG) == UOB_RST_STP))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_nRST_STDBY
+  * @{
+  */
+
+#define UOB_NO_RST_STDBY                    ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
+#define UOB_RST_STDBY                       ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
+#define IS_UOB_STDBY_CFG(CFG)               (((CFG) == UOB_NO_RST_STDBY) || ((CFG) == UOB_RST_STDBY))
+
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+/**
+  * @}
+  */
+/** @defgroup FLASH_Boot
+  * @{
+  */
+#define FLASH_BOOT_FROM_BANK1               ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
+                                                               and this parameter is selected the device will boot from Bank1(Default) */
+#define FLASH_BOOT_FROM_BANK2               ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
+                                                               and this parameter is selected the device will boot from Bank 2 or Bank 1,
+                                                               depending on the activation of the bank */
+#define IS_FLASH_BOOT_CFG(CFG)              (((CFG) == FLASH_BOOT_FROM_BANK1) || ((CFG) == FLASH_BOOT_FROM_BANK2))
+#endif
+/**
+  * @}
+  */
+/** @defgroup FLASH_Interrupts
+  * @{
+  */
+#define FLASH_INT_FLR                       ((uint32_t)0x00000400)  /*!< FPEC error interrupt source */
+#define FLASH_INT_PRCDN                     ((uint32_t)0x00001000)  /*!< End of FLASH Operation Interrupt source */
+#define FLASH_INT_BANK1_FLR                 FLASH_INT_FLR           /*!< FPEC BANK1 error interrupt source */
+#define FLASH_INT_BANK1_PRCDN               FLASH_INT_PRCDN         /*!< End of FLASH BANK1 Operation Interrupt source */
+#define FLASH_INT_BANK3                     ((uint32_t)0x40000000)
+#define FLASH_INT_BANK3_MASK                (~FLASH_INT_BANK3)
+#define FLASH_INT_BANK3_FLR                 ((uint32_t)0x40000400)  /*!< FPEC BANK1 error interrupt source */
+#define FLASH_INT_BANK3_PRCDN               ((uint32_t)0x40001000)  /*!< End of FLASH BANK1 Operation Interrupt source */
+
+
+
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+#define FLASH_INT_BANK2                     ((uint32_t)0x80000000)
+#define FLASH_INT_BANK2_MASK                (~FLASH_INT_BANK2)
+#define FLASH_INT_BANK2_FLR                 ((uint32_t)0x80000400)  /*!< FPEC BANK2 error interrupt source */
+#define FLASH_INT_BANK2_PRCDN               ((uint32_t)0x80001000)  /*!< End of FLASH BANK2 Operation Interrupt source */
+#define IS_FLASH_INT(INT)                   ((((INT) & (uint32_t)0x3FFFEBFF) == 0x00000000) && (((INT) != 0x00000000)))
+#else
+#define IS_FLASH_INT(INT) ((((INT) & (uint32_t)0xBFFFEBFF) == 0x00000000) && (((INT) != 0x00000000)))
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flags
+  * @{
+  */
+
+#define FLASH_FLAG_BSY                      ((uint32_t)0x00000001)  /*!< FLASH Busy flag */
+#define FLASH_FLAG_PRCDN                    ((uint32_t)0x00000020)  /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_PRGMFLR                  ((uint32_t)0x00000004)  /*!< FLASH Program error flag */
+#define FLASH_FLAG_WRPRTFLR                 ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_UOBFLR                   ((uint32_t)0x00000001)  /*!< FLASH Option Byte error flag */
+
+#define FLASH_FLAG_BNK1_BSY                 FLASH_FLAG_BSY          /*!< FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BNK1_PRCDN               FLASH_FLAG_PRCDN        /*!< FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BNK1_PRGMFLR             FLASH_FLAG_PRGMFLR      /*!< FLASH BANK1 Program error flag */
+#define FLASH_FLAG_BNK1_WRPRTFLR            FLASH_FLAG_WRPRTFLR     /*!< FLASH BANK1 Write protected error flag */
+
+#define FLASH_FLAG_BANK3                    ((uint32_t)0x40000000)
+#define FLASH_FLAG_BNK3_BSY                 ((uint32_t)0x40000001)  /*!< FLASH BANK3 Busy flag*/
+#define FLASH_FLAG_BNK3_PRCDN               ((uint32_t)0x40000020)  /*!< FLASH BANK3 End of Operation flag */
+#define FLASH_FLAG_BNK3_PRGMFLR             ((uint32_t)0x40000004)  /*!< FLASH BANK3 Program error flag */
+#define FLASH_FLAG_BNK3_WRPRTFLR            ((uint32_t)0x40000010)  /*!< FLASH BANK3 Write protected error flag */
+
+
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+#define FLASH_FLAG_BANK2                    ((uint32_t)0x80000000)
+#define FLASH_FLAG_BNK2_BSY                 ((uint32_t)0x80000001)  /*!< FLASH BANK2 Busy flag */
+#define FLASH_FLAG_BNK2_PRCDN               ((uint32_t)0x80000020)  /*!< FLASH BANK2 End of Operation flag */
+#define FLASH_FLAG_BNK2_PRGMFLR             ((uint32_t)0x80000004)  /*!< FLASH BANK2 Program error flag */
+#define FLASH_FLAG_BNK2_WRPRTFLR            ((uint32_t)0x80000010)  /*!< FLASH BANK2 Write protected error flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG)           ((((FLAG) & (uint32_t)0x3FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG)             (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PRCDN) || \
+                                             ((FLAG) == FLASH_FLAG_PRGMFLR) || ((FLAG) == FLASH_FLAG_WRPRTFLR) || \
+                                             ((FLAG) == FLASH_FLAG_UOBFLR)|| \
+                                             ((FLAG) == FLASH_FLAG_BNK1_BSY) || ((FLAG) == FLASH_FLAG_BNK1_PRCDN) || \
+                                             ((FLAG) == FLASH_FLAG_BNK1_PRGMFLR) || ((FLAG) == FLASH_FLAG_BNK1_WRPRTFLR) || \
+                                             ((FLAG) == FLASH_FLAG_BNK2_BSY) || ((FLAG) == FLASH_FLAG_BNK2_PRCDN) || \
+                                             ((FLAG) == FLASH_FLAG_BNK2_PRGMFLR) || ((FLAG) == FLASH_FLAG_BNK2_WRPRTFLR) || \
+                                             ((FLAG) == FLASH_FLAG_BNK3_BSY) || ((FLAG) == FLASH_FLAG_BNK3_PRCDN) || \
+                                             ((FLAG) == FLASH_FLAG_BNK3_PRGMFLR) || ((FLAG) == FLASH_FLAG_BNK3_WRPRTFLR))
+#else
+#define IS_FLASH_CLEAR_FLAG(FLAG)           ((((FLAG) & (uint32_t)0xBFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG)             (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PRCDN) || \
+                                             ((FLAG) == FLASH_FLAG_PRGMFLR) || ((FLAG) == FLASH_FLAG_WRPRTFLR) || \
+                                             ((FLAG) == FLASH_FLAG_BNK1_BSY) || ((FLAG) == FLASH_FLAG_BNK1_PRCDN) || \
+                                             ((FLAG) == FLASH_FLAG_BNK1_PRGMFLR) || ((FLAG) == FLASH_FLAG_BNK1_WRPRTFLR) || \
+                                             ((FLAG) == FLASH_FLAG_UOBFLR) || \
+                                             ((FLAG) == FLASH_FLAG_BNK3_BSY) || ((FLAG) == FLASH_FLAG_BNK3_PRCDN) || \
+                                             ((FLAG) == FLASH_FLAG_BNK3_PRGMFLR) || ((FLAG) == FLASH_FLAG_BNK3_WRPRTFLR))
+#endif
+
+#define FLASH_BANK3_ADDR_MAX                  ((uint32_t)0x1FFEFFFF)
+#define IS_IN_FLASH_BANK3_RANGE(ADDR)         (((ADDR) >=EXT_FLASH_BASE) && ((ADDR) <= FLASH_BANK3_ADDR_MAX))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions
+  * @{
+  */
+
+/*------------ Functions used for all at32f4xx devices -----*/
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseUserOptionBytes(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_ProgramUserOptionByteData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_EnableWriteProtect(uint32_t FLASH_Pages);
+FLASH_Status FLASH_ReadProtectConfig(FunctionalState NewState);
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t UOB_IWDG, uint16_t UOB_STOP, uint16_t UOB_STDBY);
+uint32_t FLASH_GetUserOptionByte(void);
+uint32_t FLASH_GetWriteProtectStatus(void);
+FlagStatus FLASH_GetReadProtectStatus(void);
+FlagStatus FLASH_GetPrefetchBufferStatus(void);
+void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForProcess(uint32_t Timeout);
+
+#if defined (AT32F415xx)
+/*------------ Functions used only for at32f415 devices -----*/
+FLASH_Status FLASH_SYS_AP(void);
+FLASH_Status FLASH_SlibSysEnable(uint32_t Psw,uint8_t data_start_page);
+FlagStatus FLASH_GetOptionByteProtectStatus(void);
+FLASH_Status FLASH_RDPandOptionByteProtectEnable(void);
+void FLASH_OptionByteProtectDisable(void);
+#endif /* AT32F415xx */
+
+/*------------ New function used for all at32f4xx devices -----*/
+void FLASH_UnlockBank1(void);
+void FLASH_LockBank1(void);
+FLASH_Status FLASH_EraseBank1AllPages(void);
+FLASH_Status FLASH_GetBank1Status(void);
+FLASH_Status FLASH_WaitForBank1Process(uint32_t Timeout);
+
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+/*---- New Functions used only with at32f403_XL density devices -----*/
+void FLASH_UnlockBank2(void);
+void FLASH_LockBank2(void);
+FLASH_Status FLASH_EraseBank2AllPages(void);
+FLASH_Status FLASH_GetBank2Status(void);
+FLASH_Status FLASH_WaitForBank2Process(uint32_t Timeout);
+FLASH_Status FLASH_BootOptConfig(uint16_t FLASH_BOOT);
+#endif
+
+#if !defined (AT32F415xx)
+/*---- New Functions for extrenal flash -----*/
+void FLASH_UnlockBank3(void);
+void FLASH_LockBank3(void);
+FLASH_Status FLASH_EraseBank3AllPages(void);
+FLASH_Status FLASH_GetBank3Status(void);
+FLASH_Status FLASH_WaitForBank3Process(uint32_t Timeout);
+void FLASH_Bank3EncEndAddrConfig(uint32_t EndAddress);
+#endif
+
+/*---- New Functions for SLIB -----*/
+FLASH_Status FLASH_SlibMainEnable(uint32_t Psw, uint16_t StartPage, uint16_t DataPage, uint16_t EndPage);
+uint32_t FLASH_SlibDisable(uint32_t dwPsw);
+#if !defined (AT32F415xx)
+uint32_t FLASH_GetSlibCurCnt(void);
+#endif
+uint8_t FLASH_GetSlibState(void);
+uint16_t FLASH_GetSlibStartPage(void);
+uint16_t FLASH_GetSlibDataStartPage(void);
+uint16_t FLASH_GetSlibEndPage(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_FLASH_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_gpio.h

@@ -0,0 +1,677 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_gpio.h
+ * Description  : at32f4xx GPIO header file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_GPIO_H
+#define __AT32F4xx_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Types
+  * @{
+  */
+
+#if defined (AT32F413xx) || defined (AT32F415xx)
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                    ((PERIPH) == GPIOB) || \
+                                    ((PERIPH) == GPIOC) || \
+                                    ((PERIPH) == GPIOD) || \
+                                    ((PERIPH) == GPIOF))
+#elif defined AT32F403xx
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                    ((PERIPH) == GPIOB) || \
+                                    ((PERIPH) == GPIOC) || \
+                                    ((PERIPH) == GPIOD) || \
+                                    ((PERIPH) == GPIOE) || \
+                                    ((PERIPH) == GPIOF) || \
+                                    ((PERIPH) == GPIOG))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                    ((PERIPH) == GPIOB) || \
+                                    ((PERIPH) == GPIOC) || \
+                                    ((PERIPH) == GPIOD) || \
+                                    ((PERIPH) == GPIOE))
+#endif
+
+                                     
+/** 
+  * @brief  Output Maximum frequency selection  
+  */
+
+typedef enum
+{ 
+  GPIO_MaxSpeed_10MHz = 1,
+  GPIO_MaxSpeed_2MHz,
+  GPIO_MaxSpeed_50MHz = 2
+}GPIOMaxSpeed_Type;
+#define IS_GPIO_MAXSPEED(MAXSPEED) (((MAXSPEED) == GPIO_MaxSpeed_10MHz) ||\
+                                    ((MAXSPEED) == GPIO_MaxSpeed_2MHz)  || \
+                                    ((MAXSPEED) == GPIO_MaxSpeed_50MHz))
+
+/** 
+  * @brief  Configuration Mode enumeration  
+  */
+
+typedef enum
+{ GPIO_Mode_IN_ANALOG = 0x0,
+  GPIO_Mode_IN_FLOATING = 0x04,
+  GPIO_Mode_IN_PD = 0x28,
+  GPIO_Mode_IN_PU = 0x48,
+  GPIO_Mode_OUT_OD = 0x14,
+  GPIO_Mode_OUT_PP = 0x10,
+  GPIO_Mode_AF_OD = 0x1C,
+  GPIO_Mode_AF_PP = 0x18
+}GPIOMode_Type;
+
+#define IS_GPIO_MDE(MDE) (((MDE) == GPIO_Mode_IN_ANALOG) || ((MDE) == GPIO_Mode_IN_FLOATING) || \
+                          ((MDE) == GPIO_Mode_IN_PD)     || ((MDE) == GPIO_Mode_IN_PU)       || \
+                          ((MDE) == GPIO_Mode_OUT_OD)    || ((MDE) == GPIO_Mode_OUT_PP)      || \
+                          ((MDE) == GPIO_Mode_AF_OD)     || ((MDE) == GPIO_Mode_AF_PP))
+
+/** 
+  * @brief  GPIO Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t GPIO_Pins;               /*!< Specifies the GPIO pins to be configured.
+                                      This parameter can be any value of @ref GPIO_pins_define */
+
+  GPIOMaxSpeed_Type GPIO_MaxSpeed;  /*!< Specifies the speed for the selected pins.
+                                      This parameter can be a value of @ref GPIOMaxSpeed_Type */
+
+  GPIOMode_Type GPIO_Mode;          /*!< Specifies the operating mode for the selected pins.
+                                      This parameter can be a value of @ref GPIOMode_Type */
+}GPIO_InitType;
+
+
+/** 
+  * @brief  Bit_SET and Bit_RESET enumeration  
+  */
+
+typedef enum
+{ Bit_RESET = 0,
+  Bit_SET
+}BitState;
+
+#define IS_GPIO_BIT_STATE(STATE) (((STATE) == Bit_RESET) || ((STATE) == Bit_SET))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Constants
+  * @{
+  */
+
+/** @defgroup GPIO_pins_define 
+  * @{
+  */
+
+#define GPIO_Pins_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */
+#define GPIO_Pins_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */
+#define GPIO_Pins_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */
+#define GPIO_Pins_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */
+#define GPIO_Pins_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */
+#define GPIO_Pins_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */
+#define GPIO_Pins_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */
+#define GPIO_Pins_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */
+#define GPIO_Pins_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */
+#define GPIO_Pins_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */
+#define GPIO_Pins_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */
+#define GPIO_Pins_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */
+#define GPIO_Pins_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */
+#define GPIO_Pins_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */
+#define GPIO_Pins_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */
+#define GPIO_Pins_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */
+#define GPIO_Pins_All               ((uint16_t)0xFFFF)  /*!< All pins selected */
+
+#define IS_GPIO_PINS(PINS) ((((PINS) & (uint16_t)0x00) == 0x00) && ((PINS) != (uint16_t)0x00))
+
+#define IS_GET_GPIO_PINS(PINS)      (((PINS) == GPIO_Pins_0)  || \
+                                     ((PINS) == GPIO_Pins_1)  || \
+                                     ((PINS) == GPIO_Pins_2)  || \
+                                     ((PINS) == GPIO_Pins_3)  || \
+                                     ((PINS) == GPIO_Pins_4)  || \
+                                     ((PINS) == GPIO_Pins_5)  || \
+                                     ((PINS) == GPIO_Pins_6)  || \
+                                     ((PINS) == GPIO_Pins_7)  || \
+                                     ((PINS) == GPIO_Pins_8)  || \
+                                     ((PINS) == GPIO_Pins_9)  || \
+                                     ((PINS) == GPIO_Pins_10) || \
+                                     ((PINS) == GPIO_Pins_11) || \
+                                     ((PINS) == GPIO_Pins_12) || \
+                                     ((PINS) == GPIO_Pins_13) || \
+                                     ((PINS) == GPIO_Pins_14) || \
+                                     ((PINS) == GPIO_Pins_15))
+
+/**
+  * @}
+  */
+
+#if defined (AT32F403xx) || defined (AT32F413xx)|| defined (AT32F415xx) || defined (AT32F403Axx) || defined (AT32F407xx)
+/** @defgroup GPIO_Remap_define 
+  * @{
+  */
+  
+/** @defgroup AFIO_MAP_define
+  * @{
+  */
+#define GPIO_Remap01_SPI1           ((uint32_t)0x00000001)  /*!< SPI1 Alternate Function mapping 01 */
+#define GPIO_Remap_I2C1             ((uint32_t)0x00000002)  /*!< I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1           ((uint32_t)0x00000004)  /*!< USART1 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3    ((uint32_t)0x00000010)  /*!< USART3 Partial Alternate Function mapping */
+#define GPIO_PartialRemap_TMR1      ((uint32_t)0x00000040)  /*!< TMR1 Partial Alternate Function mapping */
+#define GPIO_PartialRemap1_TMR2     ((uint32_t)0x00000100)  /*!< TMR2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TMR2     ((uint32_t)0x00000200)  /*!< TMR2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TMR2         ((uint32_t)0x00000300)  /*!< TMR2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TMR3      ((uint32_t)0x00000800)  /*!< TMR3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TMR3         ((uint32_t)0x00000C00)  /*!< TMR3 Full Alternate Function mapping */
+#define GPIO_Remap1_CAN1            ((uint32_t)0x00004000)  /*!< CAN1 Alternate Function mapping */
+#define GPIO_Remap_PD01             ((uint32_t)0x00008000)  /*!< PD01 Alternate Function mapping */
+#define GPIO_Remap_TMR5CH4_LSI      ((uint32_t)0x00010000)  /*!< LSI connected to TMR5 Channel4 input capture for calibration */
+#define GPIO_Remap_ADC1_EXTRGINJ    ((uint32_t)0x00020000)  /*!< ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_EXTRGREG    ((uint32_t)0x00040000)  /*!< ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_SWJ_NoJNTRST     ((uint32_t)0x01000000)  /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable  ((uint32_t)0x02000000)  /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_AllDisable   ((uint32_t)0x04000000)  /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
+#ifdef AT32F403xx
+#define GPIO_Remap10_SPI1           ((uint32_t)0x80000000)  /*!< SPI1 Alternate Function mapping 10*/
+#define GPIO_Remap_USART2           ((uint32_t)0x00000008)  /*!< USART2 Alternate Function mapping */
+#define GPIO_FullRemap_USART3       ((uint32_t)0x00000030)  /*!< USART3 Full Alternate Function mapping */
+#define GPIO_FullRemap_TMR1         ((uint32_t)0x000000C0)  /*!< TMR1 Full Alternate Function mapping */
+#define GPIO_Remap_TMR4             ((uint32_t)0x00001000)  /*!< TMR4 Alternate Function mapping */
+#define GPIO_Remap2_CAN1            ((uint32_t)0x00006000)  /*!< CAN1 Alternate Function mapping */
+#define GPIO_Remap_ADC2_EXTRGINJ    ((uint32_t)0x00080000)  /*!< ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_EXTRGREG    ((uint32_t)0x00100000)  /*!< ADC2 External Trigger Regular Conversion remapping */
+#elif defined (AT32F413xx)
+#define GPIO_Remap_ADC2_EXTRGINJ    ((uint32_t)0x00080000)  /*!< ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_EXTRGREG    ((uint32_t)0x00100000)  /*!< ADC2 External Trigger Regular Conversion remapping */
+#elif defined (AT32F415xx)
+#define GPIO_PartialRemap2_USART3   ((uint32_t)0x00000020)  /*!< EXT_FLASH Alternate Function mapping*/
+#define GPIO_PartialRemap2_TMR1     ((uint32_t)0x00000080)  /*!< TMR1 Partial2 Alternate Function mapping */
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define GPIO_Remap_USART2           ((uint32_t)0x00000008)  /*!< USART2 Alternate Function mapping */
+#define GPIO_FullRemap_USART3       ((uint32_t)0x00000030)  /*!< USART3 Full Alternate Function mapping */
+#define GPIO_FullRemap_TMR1         ((uint32_t)0x000000C0)  /*!< TMR1 Full Alternate Function mapping */
+#define GPIO_Remap_TMR4             ((uint32_t)0x00001000)  /*!< TMR4 Alternate Function mapping */
+#define GPIO_Remap2_CAN1            ((uint32_t)0x00006000)  /*!< CAN1 Alternate Function mapping */
+#define GPIO_Remap_ADC2_EXTRGINJ    ((uint32_t)0x00080000)  /*!< ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_EXTRGREG    ((uint32_t)0x00100000)  /*!< ADC2 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ETH              ((uint32_t)0x00200000)  /*!< ETH Alternate Function mapping*/
+#define GPIO_Remap_CAN2             ((uint32_t)0x00400000)  /*!< CAN2 Alternate Function mapping*/
+#define GPIO_Remap_MII_RMII         ((uint32_t)0x00800000)  /*!< MII or RMII Alternate Function mapping */
+#define GPIO_Remap_SPI3             ((uint32_t)0x10000000)  /*!< SPI3 Alternate Function mapping*/
+#define GPIO_Remap_TMR2ITR1         ((uint32_t)0x20000000)  /*!< TMR2 internal trigger 1 Alternate remapping    */
+#define GPIO_Remap_PTP_PPS          ((uint32_t)0x40000000)  /*!< Ethernet PTP PPS Alternate Function remapping  */
+#endif
+/**
+  * @}
+  */
+  
+/** @defgroup AFIO_MAP2_define
+  * @{
+  */
+#ifdef AT32F403xx
+#define GPIO_Remap_TMR15            ((uint32_t)0x40000001)  /*!< TMR15 Alternate Function mapping  */
+#define GPIO_Remap_TMR9             ((uint32_t)0x40000020)  /*!< TMR9 Alternate Function mapping  */
+#define GPIO_Remap_TMR10            ((uint32_t)0x40000040)  /*!< TMR10 Alternate Function mapping  */
+#define GPIO_Remap_TMR11            ((uint32_t)0x40000080)  /*!< TMR11 Alternate Function mapping  */
+#define GPIO_Remap_TMR13            ((uint32_t)0x40000100)  /*!< TMR13 Alternate Function mapping  */
+#define GPIO_Remap_TMR14            ((uint32_t)0x40000200)  /*!< TMR14 Alternate Function mapping  */
+#define GPIO_Remap_XMC_NADV         ((uint32_t)0x40000400)  /*!< XMC_NADV Alternate Function mapping  */
+#define GPIO_Remap_SPI4             ((uint32_t)0x40020000)  /*!< SPI4 Alternate Function mapping*/
+#define GPIO_Remap_I2C3             ((uint32_t)0x40040000)  /*!< I2C3 Alternate Function mapping*/
+#define GPIO_Remap01_SDIO2          ((uint32_t)0x40080000)  /*!< SDIO2 Alternate Function mapping 01:CK/CMD Remaped None,D0~D3 Remaped to PA4~PA7*/
+#define GPIO_Remap10_SDIO2          ((uint32_t)0x40100000)  /*!< SDIO2 Alternate Function mapping 10:CK/CMD Remaped to PA2/PA3,D0~D3 Remaped None*/
+#define GPIO_Remap11_SDIO2          ((uint32_t)0x40180000)  /*!< SDIO2 Alternate Function mapping 11:CK/CMD Remaped to PA2/PA3,D0~D3 Remaped to PA4~PA7*/
+#define GPIO_Remap_EXT_FLASH        ((uint32_t)0x40200000)  /*!< EXT_FLASH Alternate Function mapping*/
+#elif defined (AT32F413xx)
+#define GPIO_Remap_EXT_FLASH        ((uint32_t)0x40200000)  /*!< EXT_FLASH Alternate Function mapping*/
+#elif defined (AT32F415xx)
+#define GPIO_Remap01_COMP           ((uint32_t)0x44000000)  /*!< COMP1/2 Alternate Function mapping 01: COMP1/2_OUT connect to PA6/7*/
+#define GPIO_Remap10_COMP           ((uint32_t)0x48000000)  /*!< COMP1/2 Alternate Function mapping 10: COMP1/2_OUT connect to PA11/12*/
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define GPIO_Remap_TMR9             ((uint32_t)0x40000020)  /*!< TMR9 Alternate Function mapping  */
+#define GPIO_Remap_XMC_NADV         ((uint32_t)0x40000400)  /*!< XMC_NADV Alternate Function mapping  */
+#define GPIO_Remap_SPI4             ((uint32_t)0x40020000)  /*!< SPI4 Alternate Function mapping*/
+#define GPIO_Remap_I2C3             ((uint32_t)0x40040000)  /*!< I2C3 Alternate Function mapping*/
+#define GPIO_Remap01_SDIO2          ((uint32_t)0x40080000)  /*!< SDIO2 Alternate Function mapping 01:CK/CMD Remaped None,D0~D3 Remaped to PA4~PA7*/
+#define GPIO_Remap10_SDIO2          ((uint32_t)0x40100000)  /*!< SDIO2 Alternate Function mapping 10:CK/CMD Remaped to PA2/PA3,D0~D3 Remaped None*/
+#define GPIO_Remap11_SDIO2          ((uint32_t)0x40180000)  /*!< SDIO2 Alternate Function mapping 11:CK/CMD Remaped to PA2/PA3,D0~D3 Remaped to PA4~PA7*/
+#define GPIO_Remap_EXT_FLASH        ((uint32_t)0x40200000)  /*!< EXT_FLASH Alternate Function mapping*/
+#endif
+/**
+  * @}
+  */
+  
+#ifdef AT32F403xx
+#define IS_GPIO_REMAP(REMAP)        (((REMAP) == GPIO_Remap01_SPI1)         || ((REMAP) == GPIO_Remap_I2C1)           || \
+                                     ((REMAP) == GPIO_Remap_USART1)         || ((REMAP) == GPIO_Remap_USART2)         || \
+                                     ((REMAP) == GPIO_PartialRemap_USART3)  || ((REMAP) == GPIO_FullRemap_USART3)     || \
+                                     ((REMAP) == GPIO_PartialRemap_TMR1)    || ((REMAP) == GPIO_FullRemap_TMR1)       || \
+                                     ((REMAP) == GPIO_PartialRemap1_TMR2)   || ((REMAP) == GPIO_PartialRemap2_TMR2)   || \
+                                     ((REMAP) == GPIO_FullRemap_TMR2)       || ((REMAP) == GPIO_PartialRemap_TMR3)    || \
+                                     ((REMAP) == GPIO_FullRemap_TMR3)       || ((REMAP) == GPIO_Remap_TMR4)           || \
+                                     ((REMAP) == GPIO_Remap1_CAN1)          || ((REMAP) == GPIO_Remap2_CAN1)          || \
+                                     ((REMAP) == GPIO_Remap_PD01)           || ((REMAP) == GPIO_Remap_TMR5CH4_LSI)    || \
+                                     ((REMAP) == GPIO_Remap_ADC1_EXTRGINJ)  || ((REMAP) == GPIO_Remap_ADC1_EXTRGREG)  || \
+                                     ((REMAP) == GPIO_Remap_ADC2_EXTRGINJ)  || ((REMAP) == GPIO_Remap_ADC2_EXTRGREG)  || \
+                                     ((REMAP) == GPIO_Remap_SWJ_NoJNTRST)   || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \
+                                     ((REMAP) == GPIO_Remap_SWJ_AllDisable) || ((REMAP) == GPIO_Remap10_SPI1)         || \
+                                     ((REMAP) == GPIO_Remap_TMR15)          || ((REMAP) == GPIO_Remap_TMR9)           || \
+                                     ((REMAP) == GPIO_Remap_TMR10)          || ((REMAP) == GPIO_Remap_TMR11)          || \
+                                     ((REMAP) == GPIO_Remap_TMR13)          || ((REMAP) == GPIO_Remap_TMR14)          || \
+                                     ((REMAP) == GPIO_Remap_XMC_NADV)       || ((REMAP) == GPIO_Remap_SPI4)           || \
+                                     ((REMAP) == GPIO_Remap_I2C3)           || ((REMAP) == GPIO_Remap01_SDIO2)        || \
+                                     ((REMAP) == GPIO_Remap10_SDIO2)        || ((REMAP) == GPIO_Remap11_SDIO2)        || \
+                                     ((REMAP) == GPIO_Remap_EXT_FLASH))
+#elif defined (AT32F413xx)
+#define IS_GPIO_REMAP(REMAP)        (((REMAP) == GPIO_Remap01_SPI1)         || ((REMAP) == GPIO_Remap_I2C1)           || \
+                                     ((REMAP) == GPIO_Remap_USART1)         || ((REMAP) == GPIO_PartialRemap_USART3)  || \
+                                     ((REMAP) == GPIO_PartialRemap_TMR1)    || ((REMAP) == GPIO_PartialRemap1_TMR2)   || \
+                                     ((REMAP) == GPIO_PartialRemap2_TMR2)   || ((REMAP) == GPIO_FullRemap_TMR2)       || \
+                                     ((REMAP) == GPIO_PartialRemap_TMR3)    || ((REMAP) == GPIO_FullRemap_TMR3)       || \
+                                     ((REMAP) == GPIO_Remap1_CAN1)          || ((REMAP) == GPIO_Remap_EXT_FLASH)      || \
+                                     ((REMAP) == GPIO_Remap_PD01)           || ((REMAP) == GPIO_Remap_TMR5CH4_LSI)    || \
+                                     ((REMAP) == GPIO_Remap_ADC1_EXTRGINJ)  || ((REMAP) == GPIO_Remap_ADC1_EXTRGREG)  || \
+                                     ((REMAP) == GPIO_Remap_ADC2_EXTRGINJ)  || ((REMAP) == GPIO_Remap_ADC2_EXTRGREG)  || \
+                                     ((REMAP) == GPIO_Remap_SWJ_NoJNTRST)   || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \
+                                     ((REMAP) == GPIO_Remap_SWJ_AllDisable))
+#elif defined (AT32F415xx)
+#define IS_GPIO_REMAP(REMAP)        (((REMAP) == GPIO_Remap01_SPI1)         || ((REMAP) == GPIO_Remap_I2C1)           || \
+                                     ((REMAP) == GPIO_Remap_USART1)         || ((REMAP) == GPIO_PartialRemap_USART3)  || \
+                                     ((REMAP) == GPIO_PartialRemap_TMR1)    || ((REMAP) == GPIO_PartialRemap1_TMR2)   || \
+                                     ((REMAP) == GPIO_PartialRemap2_TMR2)   || ((REMAP) == GPIO_FullRemap_TMR2)       || \
+                                     ((REMAP) == GPIO_PartialRemap_TMR3)    || ((REMAP) == GPIO_FullRemap_TMR3)       || \
+                                     ((REMAP) == GPIO_Remap1_CAN1)          || ((REMAP) == GPIO_Remap_PD01)           || \
+                                     ((REMAP) == GPIO_Remap_TMR5CH4_LSI)    || ((REMAP) == GPIO_Remap_ADC1_EXTRGINJ)  || \
+                                     ((REMAP) == GPIO_Remap_ADC1_EXTRGREG)  || ((REMAP) == GPIO_Remap_SWJ_NoJNTRST)   || \
+                                     ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| ((REMAP) == GPIO_Remap_SWJ_AllDisable) || \
+                                     ((REMAP) == GPIO_Remap01_COMP)         || ((REMAP) == GPIO_Remap10_COMP)         || \
+                                     ((REMAP) == GPIO_PartialRemap2_USART3) || ((REMAP) == GPIO_PartialRemap2_TMR1))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_GPIO_REMAP(REMAP)        (((REMAP) == GPIO_Remap01_SPI1)         || ((REMAP) == GPIO_Remap_I2C1)           || \
+                                     ((REMAP) == GPIO_Remap_USART1)         || ((REMAP) == GPIO_Remap_USART2)         || \
+                                     ((REMAP) == GPIO_PartialRemap_USART3)  || ((REMAP) == GPIO_FullRemap_USART3)     || \
+                                     ((REMAP) == GPIO_PartialRemap_TMR1)    || ((REMAP) == GPIO_FullRemap_TMR1)       || \
+                                     ((REMAP) == GPIO_PartialRemap1_TMR2)   || ((REMAP) == GPIO_PartialRemap2_TMR2)   || \
+                                     ((REMAP) == GPIO_FullRemap_TMR2)       || ((REMAP) == GPIO_PartialRemap_TMR3)    || \
+                                     ((REMAP) == GPIO_FullRemap_TMR3)       || ((REMAP) == GPIO_Remap_TMR4)           || \
+                                     ((REMAP) == GPIO_Remap1_CAN1)          || ((REMAP) == GPIO_Remap2_CAN1)          || \
+                                     ((REMAP) == GPIO_Remap_PD01)           || ((REMAP) == GPIO_Remap_TMR5CH4_LSI)    || \
+                                     ((REMAP) == GPIO_Remap_ADC1_EXTRGINJ)  || ((REMAP) == GPIO_Remap_ADC1_EXTRGREG)  || \
+                                     ((REMAP) == GPIO_Remap_ADC2_EXTRGINJ)  || ((REMAP) == GPIO_Remap_ADC2_EXTRGREG)  || \
+                                     ((REMAP) == GPIO_Remap_SWJ_NoJNTRST)   || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \
+                                     ((REMAP) == GPIO_Remap_SWJ_AllDisable) || ((REMAP) == GPIO_Remap_EXT_FLASH)      || \
+                                     ((REMAP) == GPIO_Remap_PTP_PPS)        || ((REMAP) == GPIO_Remap_TMR2ITR1)       || \
+                                     ((REMAP) == GPIO_Remap_SPI3)           || ((REMAP) == GPIO_Remap_MII_RMII)       || \
+                                     ((REMAP) == GPIO_Remap_CAN2)           || ((REMAP) == GPIO_Remap_ETH)            || \
+                                     ((REMAP) == GPIO_Remap_TMR9)           || ((REMAP) == GPIO_Remap_XMC_NADV)       || \
+                                     ((REMAP) == GPIO_Remap_SPI4)           || ((REMAP) == GPIO_Remap_I2C3)           || \
+                                     ((REMAP) == GPIO_Remap01_SDIO2)        || ((REMAP) == GPIO_Remap10_SDIO2)        || \
+                                     ((REMAP) == GPIO_Remap11_SDIO2))
+                                     
+#endif
+                              
+/**
+  * @}
+  */ 
+#endif
+
+#if !defined(AT32F403xx)
+
+#define AFIO_MAP3     0x00
+#define AFIO_MAP4     0x01
+#define AFIO_MAP5     0x02
+#define AFIO_MAP6     0x03
+#define AFIO_MAP7     0x04
+#if defined (AT32F415xx) || defined (AT32F403Axx) || defined (AT32F407xx)
+#define AFIO_MAP8     0x05
+#endif
+
+#define BITS0         0x00
+#define BITS1         0x01
+#define BITS2         0x02
+#define BITS3         0x03
+#define BITS4         0x04
+#define BITS5         0x05
+#define BITS6         0x06
+#define BITS7         0x07
+
+#define OFFSET_MASK0  0xFFFFFFF0
+#define OFFSET_MASK1  0xFFFFFF0F
+#define OFFSET_MASK2  0xFFFFF0FF
+#define OFFSET_MASK3  0xFFFF0FFF
+#define OFFSET_MASK4  0xFFF0FFFF
+#define OFFSET_MASK5  0xFF0FFFFF
+#define OFFSET_MASK6  0xF0FFFFFF
+#define OFFSET_MASK7  0x0FFFFFFF
+
+/** @defgroup AFIO_MAP3_4_5_6_7_8_define 
+  * @{ 
+  */
+#define AFIO_MAP3_TMR9_0010         ((uint32_t)0x80000002)  /*!< TMR9 Alternate Function mapping  */
+#define AFIO_MAP3_TMR10_0010        ((uint32_t)0x80000012)  /*!< TMR10 Alternate Function mapping  */
+#define AFIO_MAP3_TMR11_0010        ((uint32_t)0x80000022)  /*!< TMR11 Alternate Function mapping  */
+
+#define AFIO_MAP4_TMR1_0001         ((uint32_t)0x80000081)  /*!< TMR1 Alternate Function mapping */
+#define AFIO_MAP4_TMR3_0010         ((uint32_t)0x800000A2)  /*!< TMR3 Alternate Function mapping 0010*/
+#define AFIO_MAP4_TMR3_0011         ((uint32_t)0x800000A3)  /*!< TMR3 Alternate Function mapping 0011*/
+#define AFIO_MAP4_TMR5_1000         ((uint32_t)0x800000C8)  /*!< TMR5 Alternate Function mapping 1000: CH4 */
+
+#define AFIO_MAP5_USART5_0001       ((uint32_t)0x80000101)  /*!< USART5 Alternate Function mapping 0001*/
+#define AFIO_MAP5_I2C1_0001         ((uint32_t)0x80000111)  /*!< I2C1 Alternate Function mapping 0001*/
+#define AFIO_MAP5_I2C1_0011         ((uint32_t)0x80000113)  /*!< I2C1 Alternate Function mapping 0011*/
+#define AFIO_MAP5_I2C2_0001         ((uint32_t)0x80000121)  /*!< I2C2 Alternate Function mapping 0001*/
+#define AFIO_MAP5_I2C2_0010         ((uint32_t)0x80000122)  /*!< I2C2 Alternate Function mapping 0010*/
+#define AFIO_MAP5_I2C2_0011         ((uint32_t)0x80000123)  /*!< I2C2 Alternate Function mapping 0011*/
+#define AFIO_MAP5_I2C3_0001         ((uint32_t)0x80000131)  /*!< I2C3 Alternate Function mapping 0001*/
+#define AFIO_MAP5_SPI1_0001         ((uint32_t)0x80000141)  /*!< SPI1 Alternate Function mapping 0001*/
+#define AFIO_MAP5_SPI1_0010         ((uint32_t)0x80000142)  /*!< SPI1 Alternate Function mapping 0010*/
+#define AFIO_MAP5_SPI1_0011         ((uint32_t)0x80000143)  /*!< SPI1 Alternate Function mapping 0011*/
+#define AFIO_MAP5_SPI2_0001         ((uint32_t)0x80000151)  /*!< SPI2 Alternate Function mapping 0001*/
+#define AFIO_MAP5_SPI2_0010         ((uint32_t)0x80000152)  /*!< SPI2 Alternate Function mapping 0010*/
+#define AFIO_MAP5_SPI3_0001         ((uint32_t)0x80000161)  /*!< SPI3 Alternate Function mapping 0001*/
+#define AFIO_MAP5_SPI3_0010         ((uint32_t)0x80000162)  /*!< SPI3 Alternate Function mapping 0010*/
+#define AFIO_MAP5_SPI3_0011         ((uint32_t)0x80000163)  /*!< SPI3 Alternate Function mapping 0011*/
+#define AFIO_MAP5_SPI4_0001         ((uint32_t)0x80000171)  /*!< SPI4 Alternate Function mapping 0001*/
+#define AFIO_MAP5_SPI4_0010         ((uint32_t)0x80000172)  /*!< SPI4 Alternate Function mapping 0010*/
+#define AFIO_MAP5_SPI4_0011         ((uint32_t)0x80000173)  /*!< SPI4 Alternate Function mapping 0011*/
+
+#define AFIO_MAP6_CAN1_0010         ((uint32_t)0x80000182)  /*!< CAN1 Alternate Function mapping 0010*/
+#define AFIO_MAP6_CAN1_0011         ((uint32_t)0x80000183)  /*!< CAN1 Alternate Function mapping 0011*/
+#define AFIO_MAP6_CAN2_0001         ((uint32_t)0x80000191)  /*!< CAN2 Alternate Function mapping */
+#define AFIO_MAP6_SDIO_0100         ((uint32_t)0x800001A4)  /*!< SDIO Alternate Function mapping 100 */
+#define AFIO_MAP6_SDIO_0101         ((uint32_t)0x800001A5)  /*!< SDIO Alternate Function mapping 101 */
+#define AFIO_MAP6_SDIO_0110         ((uint32_t)0x800001A6)  /*!< SDIO Alternate Function mapping 110 */
+#define AFIO_MAP6_SDIO_0111         ((uint32_t)0x800001A7)  /*!< SDIO Alternate Function mapping 111 */
+#define AFIO_MAP6_SDIO2_0001        ((uint32_t)0x800001B1)  /*!< SDIO2 Alternate Function mapping 0001 */
+#define AFIO_MAP6_SDIO2_0010        ((uint32_t)0x800001B2)  /*!< SDIO2 Alternate Function mapping 0010 */
+#define AFIO_MAP6_SDIO2_0011        ((uint32_t)0x800001B3)  /*!< SDIO2 Alternate Function mapping 0011 */
+#define AFIO_MAP6_USART1_0001       ((uint32_t)0x800001C1)  /*!< USART1 Alternate Function mapping */
+#define AFIO_MAP6_USART2_0001       ((uint32_t)0x800001D1)  /*!< USART2 Alternate Function mapping */
+#define AFIO_MAP6_USART3_0001       ((uint32_t)0x800001E1)  /*!< USART3 Alternate Function mapping 0001*/
+#define AFIO_MAP6_USART3_0011       ((uint32_t)0x800001E3)  /*!< USART3 Alternate Function mapping 0011*/
+#define AFIO_MAP6_UART4_0001        ((uint32_t)0x800001F1)  /*!< UART4 Alternate Function mapping */
+
+#define AFIO_MAP7_SPIF_1000         ((uint32_t)0x80000208)  /*!< EXT_FLASH Alternate Function mapping */ 
+#define AFIO_MAP7_SPIF_1001         ((uint32_t)0x80000209)  /*!< EXT_FLASH Alternate Function enable */ 
+#define AFIO_MAP7_ADC1_0001         ((uint32_t)0x80000211)  /*!< ADC1 External Trigger Injected Conversion remapping */
+#define AFIO_MAP7_ADC1_0010         ((uint32_t)0x80000212)  /*!< ADC1 External Trigger Regular Conversion remapping */
+#define AFIO_MAP7_ADC1_0011         ((uint32_t)0x80000213)  /*!< ADC1 External Trigger Regular & Injected Conversion remapping */
+#define AFIO_MAP7_ADC2_0001         ((uint32_t)0x80000221)  /*!< ADC2 External Trigger Injected Conversion remapping */
+#define AFIO_MAP7_ADC2_0010         ((uint32_t)0x80000222)  /*!< ADC2 External Trigger Regular Conversion remapping */
+#define AFIO_MAP7_ADC2_0011         ((uint32_t)0x80000223)  /*!< ADC2 External Trigger Regular & Injected Conversion remapping */
+#define AFIO_MAP7_SWJTAG_0001       ((uint32_t)0x80000241)  /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define AFIO_MAP7_SWJTAG_0010       ((uint32_t)0x80000242)  /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAP7_SWJTAG_0100       ((uint32_t)0x80000244)  /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
+#define AFIO_MAP7_PD01_0001         ((uint32_t)0x80000251)  /*!< PD01 Alternate Function mapping */  
+#define AFIO_MAP7_XMC_0001          ((uint32_t)0x80000261)  /*!< XMC Alternate Function mapping 0001 */
+#define AFIO_MAP7_XMC_0010          ((uint32_t)0x80000262)  /*!< XMC Alternate Function mapping 0010 */
+#define AFIO_MAP7_XMC_1000          ((uint32_t)0x80000268)  /*!< XMC Alternate Function mapping 1000 */
+#define AFIO_MAP7_XMC_1001          ((uint32_t)0x80000269)  /*!< XMC Alternate Function mapping 1001 */
+#define AFIO_MAP7_XMC_1010          ((uint32_t)0x8000026A)  /*!< XMC Alternate Function mapping 1011 */
+
+#define AFIO_MAP8_ETH_0001          ((uint32_t)0x800002C1)  /*!< ETH Alternate Function mapping 0001*/
+#define AFIO_MAP8_ETH_0100          ((uint32_t)0x800002C4)  /*!< ETH Alternate Function mapping 0100*/
+#define AFIO_MAP8_ETH_0101          ((uint32_t)0x800002C5)  /*!< ETH Alternate Function mapping 0101*/
+#define AFIO_MAP8_ETH_1000          ((uint32_t)0x800002C8)  /*!< ETH Alternate Function mapping 1000*/
+#define AFIO_MAP8_ETH_1001          ((uint32_t)0x800002C9)  /*!< ETH Alternate Function mapping 1001*/
+#define AFIO_MAP8_ETH_1100          ((uint32_t)0x800002CC)  /*!< ETH Alternate Function mapping 1100*/
+#define AFIO_MAP8_ETH_1101          ((uint32_t)0x800002CD)  /*!< ETH Alternate Function mapping 1101*/
+#define AFIO_MAP8_USART6_0001       ((uint32_t)0x800002D1)  /*!< USART6 Alternate Function mapping */
+#define AFIO_MAP8_UART7_0001        ((uint32_t)0x800002E1)  /*!< UART7 Alternate Function mapping */
+#define AFIO_MAP8_UART8_0001        ((uint32_t)0x800002F1)  /*!< UART8 Alternate Function mapping */
+
+#ifdef AT32F413xx
+#define AFIO_MAP4_TMR2_0001         ((uint32_t)0x80000091)  /*!< TMR2 Alternate Function mapping 1001*/
+#define AFIO_MAP4_TMR2_0010         ((uint32_t)0x80000092)  /*!< TMR2 Alternate Function mapping 1010*/
+#define AFIO_MAP4_TMR2_0011         ((uint32_t)0x80000093)  /*!< TMR2 Alternate Function mapping 1011*/
+#define AFIO_MAP4_TMR2_1001         ((uint32_t)0x80000099)  /*!< TMR2 Alternate Function mapping 1001*/
+#define AFIO_MAP4_TMR2_1010         ((uint32_t)0x8000009A)  /*!< TMR2 Alternate Function mapping 1010*/
+#define AFIO_MAP4_TMR2_1011         ((uint32_t)0x8000009B)  /*!< TMR2 Alternate Function mapping 1011*/
+#define AFIO_MAP4_TMR5_0001         ((uint32_t)0x800000C1)  /*!< TMR5 Alternate Function mapping 0001: CH1/CH2*/
+#define AFIO_MAP4_TMR5_1001         ((uint32_t)0x800000C9)  /*!< TMR5 Alternate Function mapping 1001: CH1/CH2+CH4 */
+#endif
+
+#ifdef AT32F415xx
+#define AFIO_MAP4_TMR1_0010         ((uint32_t)0x80000082)  /*!< TMR1 Alternate Function mapping 0010*/
+#define AFIO_MAP4_TMR2_0001         ((uint32_t)0x80000091)  /*!< TMR2 Alternate Function mapping 0001*/
+#define AFIO_MAP4_TMR2_0010         ((uint32_t)0x80000092)  /*!< TMR2 Alternate Function mapping 0010*/
+#define AFIO_MAP4_TMR2_0011         ((uint32_t)0x80000093)  /*!< TMR2 Alternate Function mapping 0011*/
+#define AFIO_MAP4_TMR5_0001         ((uint32_t)0x800000C1)  /*!< TMR5 Alternate Function mapping 0001: CH1/CH2*/
+#define AFIO_MAP4_TMR5_1001         ((uint32_t)0x800000C9)  /*!< TMR5 Alternate Function mapping 1001: CH1/CH2+CH4 */
+
+#define AFIO_MAP8_TMR1_BK1_00       ((uint32_t)0x80000280)  /*!< TMR1 BK1 input selection 00/01*/
+#define AFIO_MAP8_TMR1_BK1_10       ((uint32_t)0x80000282)  /*!< TMR1 BK1 input selection 10   */
+#define AFIO_MAP8_TMR1_BK1_11       ((uint32_t)0x80000283)  /*!< TMR1 BK1 input selection 11   */
+#define AFIO_MAP8_TMR1_CH1_00       ((uint32_t)0x80000290)  /*!< TMR1 CH1 input selection 00/01*/
+#define AFIO_MAP8_TMR1_CH1_10       ((uint32_t)0x80000298)  /*!< TMR1 CH1 input selection 10   */
+#define AFIO_MAP8_TMR1_CH1_11       ((uint32_t)0x8000029C)  /*!< TMR1 CH1 input selection 11   */
+#define AFIO_MAP8_TMR2_CH4_00       ((uint32_t)0x800002A0)  /*!< TMR2 CH4 input selection 00/01*/
+#define AFIO_MAP8_TMR2_CH4_10       ((uint32_t)0x800002A2)  /*!< TMR2 CH4 input selection 10   */
+#define AFIO_MAP8_TMR2_CH4_11       ((uint32_t)0x800002A3)  /*!< TMR2 CH4 input selection 11   */
+#define AFIO_MAP8_TMR3_CH1_00       ((uint32_t)0x800002B0)  /*!< TMR3 CH1 input selection 00/01*/
+#define AFIO_MAP8_TMR3_CH1_10       ((uint32_t)0x800002B8)  /*!< TMR3 CH1 input selection 10   */
+#define AFIO_MAP8_TMR3_CH1_11       ((uint32_t)0x800002BC)  /*!< TMR3 CH1 input selection 11   */
+#endif
+
+#if defined (AT32F403Axx) || defined (AT32F407xx)
+#define AFIO_MAP4_TMR1_0011         ((uint32_t)0x80000083)  /*!< TMR1 Alternate Function mapping 0011*/
+#define AFIO_MAP4_TMR2_0001         ((uint32_t)0x80000091)  /*!< TMR2 Alternate Function mapping 1001*/
+#define AFIO_MAP4_TMR2_0010         ((uint32_t)0x80000092)  /*!< TMR2 Alternate Function mapping 1010*/
+#define AFIO_MAP4_TMR2_0011         ((uint32_t)0x80000093)  /*!< TMR2 Alternate Function mapping 1011*/
+#define AFIO_MAP4_TIM2ITR1_1000     ((uint32_t)0x80000098)  /*!< TMR2 Alternate Function mapping 1101*/
+#define AFIO_MAP4_TIM2ITR1_1100     ((uint32_t)0x8000009C)  /*!< TMR2 Alternate Function mapping 1110*/
+#define AFIO_MAP4_TMR4_0001         ((uint32_t)0x800000B1)  /*!< TMR5 Alternate Function mapping 0001: CH1/CH2*/
+#endif
+
+#define IS_GREMAP(REMAP)            ((REMAP) > 0x80000000)
+
+#define IS_GPIO_GREMAP(REMAP)        (((REMAP) == AFIO_MAP3_TMR9_0010)    || ((REMAP) == AFIO_MAP3_TMR10_0010)    || \
+                                     ((REMAP) == AFIO_MAP3_TMR11_0010)    || ((REMAP) == AFIO_MAP4_TMR1_0001)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR2_0001)     || ((REMAP) == AFIO_MAP6_CAN1_0010)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR2_0010)     || ((REMAP) == AFIO_MAP6_CAN2_0001)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR2_0011)     || ((REMAP) == AFIO_MAP6_SDIO_0100)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR3_0010)     || ((REMAP) == AFIO_MAP6_SDIO_0101)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR3_0011)     || ((REMAP) == AFIO_MAP6_SDIO_0110)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR5_0001)     || ((REMAP) == AFIO_MAP6_SDIO_0111)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR5_1000)     || ((REMAP) == AFIO_MAP6_USART1_0001)   || \
+                                     ((REMAP) == AFIO_MAP4_TMR5_1001)     || ((REMAP) == AFIO_MAP6_USART3_0001)   || \
+                                     ((REMAP) == AFIO_MAP5_I2C1_0001)     || ((REMAP) == AFIO_MAP6_UART4_0001)    || \
+                                     ((REMAP) == AFIO_MAP5_I2C1_0011)     || ((REMAP) == AFIO_MAP7_SPIF_1000)     || \
+                                     ((REMAP) == AFIO_MAP5_I2C2_0001)     || ((REMAP) == AFIO_MAP7_SPIF_1001)     || \
+                                     ((REMAP) == AFIO_MAP5_I2C2_0010)     || ((REMAP) == AFIO_MAP7_ADC1_0001)     || \
+                                     ((REMAP) == AFIO_MAP5_I2C2_0011)     || ((REMAP) == AFIO_MAP7_ADC1_0010)     || \
+                                     ((REMAP) == AFIO_MAP5_SPI1_0001)     || ((REMAP) == AFIO_MAP7_ADC2_0001)     || \
+                                     ((REMAP) == AFIO_MAP5_SPI2_0001)     || ((REMAP) == AFIO_MAP7_ADC2_0010)     || \
+                                     ((REMAP) == AFIO_MAP7_SWJTAG_0010)   || ((REMAP) == AFIO_MAP7_SWJTAG_0001)   || \
+                                     ((REMAP) == AFIO_MAP7_SWJTAG_0100)   || ((REMAP) == AFIO_MAP7_PD01_0001)     || \
+                                     ((REMAP) == AFIO_MAP8_TMR1_BK1_00)   || ((REMAP) == AFIO_MAP8_TMR1_BK1_10)   || \
+                                     ((REMAP) == AFIO_MAP8_TMR1_BK1_11)   || ((REMAP) == AFIO_MAP8_TMR1_CH1_00)   || \
+                                     ((REMAP) == AFIO_MAP8_TMR1_CH1_10)   || ((REMAP) == AFIO_MAP8_TMR1_CH1_11)   || \
+                                     ((REMAP) == AFIO_MAP8_TMR2_CH4_00)   || ((REMAP) == AFIO_MAP8_TMR2_CH4_10)   || \
+                                     ((REMAP) == AFIO_MAP8_TMR2_CH4_11)   || ((REMAP) == AFIO_MAP8_TMR3_CH1_00)   || \
+                                     ((REMAP) == AFIO_MAP8_TMR3_CH1_10)   || ((REMAP) == AFIO_MAP8_TMR3_CH1_11)   || \
+                                     ((REMAP) == AFIO_MAP4_TMR1_0011)     || ((REMAP) == AFIO_MAP4_TMR4_0001)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR2_1001)     || ((REMAP) == AFIO_MAP4_TMR2_1010)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR2_1011)     || ((REMAP) == AFIO_MAP4_TMR2_1101)     || \
+                                     ((REMAP) == AFIO_MAP4_TMR2_1110)     || ((REMAP) == AFIO_MAP4_TMR2_1111)     || \
+                                     ((REMAP) == AFIO_MAP5_USART5_0001)   || ((REMAP) == AFIO_MAP5_I2C3_0001)     || \
+                                     ((REMAP) == AFIO_MAP5_SPI1_0010)     || ((REMAP) == AFIO_MAP5_SPI1_0011)     || \
+                                     ((REMAP) == AFIO_MAP5_SPI2_0010)     || ((REMAP) == AFIO_MAP5_SPI3_0001)     || \
+                                     ((REMAP) == AFIO_MAP5_SPI3_0010)     || ((REMAP) == AFIO_MAP5_SPI3_0011)     || \
+                                     ((REMAP) == AFIO_MAP5_SPI4_0001)     || ((REMAP) == AFIO_MAP5_SPI4_0010)     || \
+                                     ((REMAP) == AFIO_MAP5_SPI4_0011)     || ((REMAP) == AFIO_MAP6_CAN1_0011)     || \
+                                     ((REMAP) == AFIO_MAP6_SDIO2_0001)    || ((REMAP) == AFIO_MAP6_SDIO2_0010)    || \
+                                     ((REMAP) == AFIO_MAP6_SDIO2_0011)    || ((REMAP) == AFIO_MAP6_USART2_0001)   || \
+                                     ((REMAP) == AFIO_MAP6_USART3_0011)   || ((REMAP) == AFIO_MAP7_ADC1_0011)     || \
+                                     ((REMAP) == AFIO_MAP7_ADC2_0011)     || ((REMAP) == AFIO_MAP7_XMC_0001)      || \
+                                     ((REMAP) == AFIO_MAP7_XMC_0010)      || ((REMAP) == AFIO_MAP7_XMC_1001)      || \
+                                     ((REMAP) == AFIO_MAP7_XMC_1010)      || ((REMAP) == AFIO_MAP8_ETH_0001)      || \
+                                     ((REMAP) == AFIO_MAP8_ETH_0100)      || ((REMAP) == AFIO_MAP8_ETH_0101)      || \
+                                     ((REMAP) == AFIO_MAP8_ETH_1000)      || ((REMAP) == AFIO_MAP8_ETH_1001)      || \
+                                     ((REMAP) == AFIO_MAP8_ETH_1100)      || ((REMAP) == AFIO_MAP8_ETH_1101)      || \
+                                     ((REMAP) == AFIO_MAP8_USART6_0001)   || ((REMAP) == AFIO_MAP8_UART7_0001)    || \
+                                     ((REMAP) == AFIO_MAP8_UART8_0001)    || ((REMAP) == AFIO_MAP4_TIM2ITR1_1000) || \
+                                     ((REMAP) == AFIO_MAP4_TIM2ITR1_1100) || ((REMAP) == AFIO_MAP7_XMC_1000))
+                                     
+/**
+  * @}
+  */ 
+#endif
+
+/** @defgroup GPIO_Port_Sources 
+  * @{
+  */
+
+#define GPIO_PortSourceGPIOA       ((uint8_t)0x00)
+#define GPIO_PortSourceGPIOB       ((uint8_t)0x01)
+#define GPIO_PortSourceGPIOC       ((uint8_t)0x02)
+#define GPIO_PortSourceGPIOD       ((uint8_t)0x03)
+#define GPIO_PortSourceGPIOE       ((uint8_t)0x04)
+#define GPIO_PortSourceGPIOF       ((uint8_t)0x05)
+#define GPIO_PortSourceGPIOG       ((uint8_t)0x06)
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOE))
+
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE)     (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOG))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Pin_sources 
+  * @{
+  */
+
+#define GPIO_PinsSource0            ((uint8_t)0x00)
+#define GPIO_PinsSource1            ((uint8_t)0x01)
+#define GPIO_PinsSource2            ((uint8_t)0x02)
+#define GPIO_PinsSource3            ((uint8_t)0x03)
+#define GPIO_PinsSource4            ((uint8_t)0x04)
+#define GPIO_PinsSource5            ((uint8_t)0x05)
+#define GPIO_PinsSource6            ((uint8_t)0x06)
+#define GPIO_PinsSource7            ((uint8_t)0x07)
+#define GPIO_PinsSource8            ((uint8_t)0x08)
+#define GPIO_PinsSource9            ((uint8_t)0x09)
+#define GPIO_PinsSource10           ((uint8_t)0x0A)
+#define GPIO_PinsSource11           ((uint8_t)0x0B)
+#define GPIO_PinsSource12           ((uint8_t)0x0C)
+#define GPIO_PinsSource13           ((uint8_t)0x0D)
+#define GPIO_PinsSource14           ((uint8_t)0x0E)
+#define GPIO_PinsSource15           ((uint8_t)0x0F)
+
+#define IS_GPIO_PINS_SOURCE(PINSSOURCE) (((PINSSOURCE) == GPIO_PinsSource0)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource1)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource2)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource3)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource4)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource5)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource6)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource7)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource8)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource9)  || \
+                                         ((PINSSOURCE) == GPIO_PinsSource10) || \
+                                         ((PINSSOURCE) == GPIO_PinsSource11) || \
+                                         ((PINSSOURCE) == GPIO_PinsSource12) || \
+                                         ((PINSSOURCE) == GPIO_PinsSource13) || \
+                                         ((PINSSOURCE) == GPIO_PinsSource14) || \
+                                         ((PINSSOURCE) == GPIO_PinsSource15))
+
+/**
+  * @}
+  */
+                                             
+/** @defgroup Ethernet_Media_Interface 
+  * @{
+  */ 
+#define GPIO_ETH_MediaInterface_MII    ((uint32_t)0x00000000) 
+#define GPIO_ETH_MediaInterface_RMII   ((uint32_t)0x00000001)                                       
+
+#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
+                                                ((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
+                                                
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions
+  * @{
+  */
+
+void GPIO_Reset(GPIO_Type* GPIOx);
+void GPIO_AFIOReset(void);
+void GPIO_Init(GPIO_Type* GPIOx, GPIO_InitType* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitType* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_Type* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_Type* GPIOx);
+void GPIO_SetBits(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin, BitState BitVal);
+void GPIO_Write(GPIO_Type* GPIOx, uint16_t PortVal);
+void GPIO_PinsLockConfig(GPIO_Type* GPIOx, uint16_t GPIO_Pin);
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_EventOutputCmd(FunctionalState NewState);
+void GPIO_PinsRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_GPIO_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_i2c.h

@@ -0,0 +1,682 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_i2c.h
+ * Description  : at32f4xx I2C header file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_I2C_H
+#define __AT32F4xx_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  I2C Init structure definition
+  */
+
+typedef struct
+{
+    uint32_t I2C_BitRate;           /*!< Specifies the clock frequency.
+                                         This parameter must be set to a value lower than 400kHz */
+
+    uint16_t I2C_Mode;              /*!< Specifies the I2C mode.
+                                         This parameter can be a value of @ref I2C_mode */
+
+    uint16_t I2C_FmDutyCycle;       /*!< Specifies the I2C fast mode duty cycle.
+                                         This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+    uint16_t I2C_OwnAddr1;          /*!< Specifies the first device own address.
+                                         This parameter can be a 7-bit or 10-bit address. */
+
+    uint16_t I2C_Ack;               /*!< Enables or disables the acknowledgement.
+                                         This parameter can be a value of @ref I2C_acknowledgement */
+
+    uint16_t I2C_AddrMode;          /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+                                         This parameter can be a value of @ref I2C_acknowledged_address */
+} I2C_InitType;
+
+/**
+  * @}
+  */
+
+
+/** @defgroup I2C_Exported_Constants
+  * @{
+  */
+
+#if defined (AT32F413xx) || defined (AT32F415xx)
+#define IS_I2C_ALL_PERIPH(PERIPH)       (((PERIPH) == I2C1) || \
+                                         ((PERIPH) == I2C2))
+#elif defined (AT32F403xx) || defined (AT32F403Axx) || \
+      defined (AT32F407xx)
+#define IS_I2C_ALL_PERIPH(PERIPH)       (((PERIPH) == I2C1) || \
+                                         ((PERIPH) == I2C2) || \
+                                         ((PERIPH) == I2C3))
+#endif
+
+/** @defgroup I2C_mode
+  * @{
+  */
+
+#define I2C_Mode_I2CDevice              ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)
+#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
+#define IS_I2C_MODE(MODE)               (((MODE) == I2C_Mode_I2CDevice) || \
+                                         ((MODE) == I2C_Mode_SMBusDevice) || \
+                                         ((MODE) == I2C_Mode_SMBusHost))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode
+  * @{
+  */
+
+#define I2C_FmDutyCycle_16_9            ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_FmDutyCycle_2_1             ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_FM_DUTY_CYCLE(CYCLE)     (((CYCLE) == I2C_FmDutyCycle_16_9) || \
+                                         ((CYCLE) == I2C_FmDutyCycle_2_1))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledgement
+  * @{
+  */
+
+#define I2C_Ack_Enable                  ((uint16_t)0x0400)
+#define I2C_Ack_Disable                 ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE)         (((STATE) == I2C_Ack_Enable) || \
+                                         ((STATE) == I2C_Ack_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_transfer_direction
+  * @{
+  */
+
+#define  I2C_Direction_Transmit         ((uint8_t)0x00)
+#define  I2C_Direction_Receive          ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION)     (((DIRECTION) == I2C_Direction_Transmit) || \
+                                         ((DIRECTION) == I2C_Direction_Receive))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledged_address
+  * @{
+  */
+
+#define I2C_AddrMode_7bit               ((uint16_t)0x4000)
+#define I2C_AddrMode_10bit              ((uint16_t)0xC000)
+#define IS_I2C_ADDR_MODE(MODE)          (((MODE) == I2C_AddrMode_7bit) || \
+                                         ((MODE) == I2C_AddrMode_10bit))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_registers
+  * @{
+  */
+
+#define I2C_Register_CTRL1              ((uint8_t)0x00)
+#define I2C_Register_CTRL2              ((uint8_t)0x04)
+#define I2C_Register_OADDR1             ((uint8_t)0x08)
+#define I2C_Register_OADDR2             ((uint8_t)0x0C)
+#define I2C_Register_DT                 ((uint8_t)0x10)
+#define I2C_Register_STS1               ((uint8_t)0x14)
+#define I2C_Register_STS2               ((uint8_t)0x18)
+#define I2C_Register_CLKCTRL            ((uint8_t)0x1C)
+#define I2C_Register_TMRISE             ((uint8_t)0x20)
+#define IS_I2C_REGISTER(REGISTER)       (((REGISTER) == I2C_Register_CTRL1)  || \
+                                         ((REGISTER) == I2C_Register_CTRL2)  || \
+                                         ((REGISTER) == I2C_Register_OADDR1) || \
+                                         ((REGISTER) == I2C_Register_OADDR2) || \
+                                         ((REGISTER) == I2C_Register_DT)     || \
+                                         ((REGISTER) == I2C_Register_STS1)   || \
+                                         ((REGISTER) == I2C_Register_STS2)   || \
+                                         ((REGISTER) == I2C_Register_CLKCTRL)|| \
+                                         ((REGISTER) == I2C_Register_TMRISE))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_SMBus_alert_pin_level
+  * @{
+  */
+
+#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
+#define IS_I2C_SMBUS_ALERT(ALERT)       (((ALERT) == I2C_SMBusAlert_Low) || \
+                                         ((ALERT) == I2C_SMBusAlert_High))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_PEC_position
+  * @{
+  */
+
+#define I2C_PECPosition_Next            ((uint16_t)0x0800)
+#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POSITION(POSITION)   (((POSITION) == I2C_PECPosition_Next) || \
+                                         ((POSITION) == I2C_PECPosition_Current))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_NCAK_position
+  * @{
+  */
+
+#define I2C_NACKPosition_Next           ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POSITION(POSITION)  (((POSITION) == I2C_NACKPosition_Next) || \
+                                         ((POSITION) == I2C_NACKPosition_Current))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_interrupts_definition
+  * @{
+  */
+
+#define I2C_INT_BUF                     ((uint16_t)0x0400)
+#define I2C_INT_EVT                     ((uint16_t)0x0200)
+#define I2C_INT_ERR                     ((uint16_t)0x0100)
+#define IS_I2C_CONFIG_INT(INT)          ((((INT) & (uint16_t)0xF8FF) == 0x00) && ((INT) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_interrupts_definition
+  * @{
+  */
+
+#define I2C_INT_SMBALERTF               ((uint32_t)0x01008000)
+#define I2C_INT_TIMOUT                  ((uint32_t)0x01004000)
+#define I2C_INT_PECERR                  ((uint32_t)0x01001000)
+#define I2C_INT_OVRUN                   ((uint32_t)0x01000800)
+#define I2C_INT_ACKFAIL                 ((uint32_t)0x01000400)
+#define I2C_INT_ARLOST                  ((uint32_t)0x01000200)
+#define I2C_INT_BUSERR                  ((uint32_t)0x01000100)
+#define I2C_INT_TDE                     ((uint32_t)0x06000080)
+#define I2C_INT_RDNE                    ((uint32_t)0x06000040)
+#define I2C_INT_STOPF                   ((uint32_t)0x02000010)
+#define I2C_INT_ADDR10F                 ((uint32_t)0x02000008)
+#define I2C_INT_BTFF                    ((uint32_t)0x02000004)
+#define I2C_INT_ADDRF                   ((uint32_t)0x02000002)
+#define I2C_INT_STARTF                  ((uint32_t)0x02000001)
+
+#define IS_I2C_CLEAR_INT(INT)           ((((INT) & (uint16_t)0x20FF) == 0x00) && ((INT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_INT(INT)             (((INT) == I2C_INT_SMBALERTF) || ((INT) == I2C_INT_TIMOUT) || \
+                                         ((INT) == I2C_INT_PECERR)    || ((INT) == I2C_INT_OVRUN)  || \
+                                         ((INT) == I2C_INT_ACKFAIL)   || ((INT) == I2C_INT_ARLOST) || \
+                                         ((INT) == I2C_INT_BUSERR)    || ((INT) == I2C_INT_TDE)    || \
+                                         ((INT) == I2C_INT_RDNE)      || ((INT) == I2C_INT_STOPF)  || \
+                                         ((INT) == I2C_INT_ADDR10F)   || ((INT) == I2C_INT_BTFF)   || \
+                                         ((INT) == I2C_INT_ADDRF)     || ((INT) == I2C_INT_STARTF))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_flags_definition
+  * @{
+  */
+
+/**
+  * @brief  SR2 register flags
+  */
+
+#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOSTADDRF           ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFTADDRF           ((uint32_t)0x00200000)
+#define I2C_FLAG_GCADDRF                ((uint32_t)0x00100000)
+#define I2C_FLAG_TRF                    ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSYF                  ((uint32_t)0x00020000)
+#define I2C_FLAG_MSF                    ((uint32_t)0x00010000)
+
+/**
+  * @brief  SR1 register flags
+  */
+
+#define I2C_FLAG_SMBALERTF              ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMOUT                 ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
+#define I2C_FLAG_OVRUN                  ((uint32_t)0x10000800)
+#define I2C_FLAG_ACKFAIL                ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLOST                 ((uint32_t)0x10000200)
+#define I2C_FLAG_BUSERR                 ((uint32_t)0x10000100)
+#define I2C_FLAG_TDE                    ((uint32_t)0x10000080)
+#define I2C_FLAG_RDNE                   ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
+#define I2C_FLAG_ADDR10F                ((uint32_t)0x10000008)
+#define I2C_FLAG_BTFF                   ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDRF                  ((uint32_t)0x10000002)
+#define I2C_FLAG_STARTF                 ((uint32_t)0x10000001)
+
+#define IS_I2C_CLEAR_FLAG(FLAG)         ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG)           (((FLAG) == I2C_FLAG_DUALF)        || ((FLAG) == I2C_FLAG_SMBHOSTADDRF) || \
+                                         ((FLAG) == I2C_FLAG_SMBDEFTADDRF) || ((FLAG) == I2C_FLAG_GCADDRF)      || \
+                                         ((FLAG) == I2C_FLAG_TRF)          || ((FLAG) == I2C_FLAG_BUSYF)        || \
+                                         ((FLAG) == I2C_FLAG_MSF)          || ((FLAG) == I2C_FLAG_SMBALERTF)    || \
+                                         ((FLAG) == I2C_FLAG_TIMOUT)       || ((FLAG) == I2C_FLAG_PECERR)       || \
+                                         ((FLAG) == I2C_FLAG_OVRUN)        || ((FLAG) == I2C_FLAG_ACKFAIL)      || \
+                                         ((FLAG) == I2C_FLAG_ARLOST)       || ((FLAG) == I2C_FLAG_BUSERR)       || \
+                                         ((FLAG) == I2C_FLAG_TDE)          || ((FLAG) == I2C_FLAG_RDNE)         || \
+                                         ((FLAG) == I2C_FLAG_STOPF)        || ((FLAG) == I2C_FLAG_ADDR10F)      || \
+                                         ((FLAG) == I2C_FLAG_BTFF)         || ((FLAG) == I2C_FLAG_ADDRF)        || \
+                                         ((FLAG) == I2C_FLAG_STARTF))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Events
+  * @{
+  */
+
+/*========================================
+
+                     I2C Master Events (Events grouped in order of communication)
+                                                        ==========================================*/
+/**
+  * @brief  Communication start
+  *
+  * After sending the START condition (I2C_GenerateSTART() function) the master
+  * has to wait for this event. It means that the Start condition has been correctly
+  * released on the I2C bus (the bus is free, no other devices is communicating).
+  *
+  */
+/* --EV5 */
+#define  I2C_EVENT_MASTER_START_GENERATED               ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
+
+/**
+  * @brief  Address Acknowledge
+  *
+  * After checking on EV5 (start condition correctly released on the bus), the
+  * master sends the address of the slave(s) with which it will communicate
+  * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
+  * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
+  * his address. If an acknowledge is sent on the bus, one of the following events will
+  * be set:
+  *
+  *  1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_ADDRESS_WITH_RECEIVER
+  *     event is set.
+  *
+  *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_ADDRESS | I2C_EVENT_MASTER_TRANSMITTER
+  *     is set
+  *
+  *  3) In case of 10-Bit addressing mode, the master (just after generating the START
+  *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
+  *  function). Then master should wait on EV9. It means that the 10-bit addressing
+  *  header has been correctly sent on the bus. Then master should send the second part of
+  *  the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
+  *  should wait for event EV6.
+  *
+  */
+
+/* --EV6 */
+#define  I2C_EVENT_MASTER_ADDRESS                       ((uint32_t)0x00070002)  /* BUSY, MSL, ADDR and TRF flags */
+#define  I2C_EVENT_MASTER_TRANSMITTER                   ((uint32_t)0x00000080)  /* TDE flags */
+#define  I2C_EVENT_MASTER_ADDRESS_WITH_RECEIVER         ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
+/* --EV9 */
+#define  I2C_EVENT_MASTER_ADDRESS10_GENERATED           ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
+
+/**
+  * @brief Communication events
+  *
+  * If a communication is established (START condition generated and slave address
+  * acknowledged) then the master has to check on one of the following events for
+  * communication procedures:
+  *
+  * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
+  *    the data received from the slave (I2C_ReceiveData() function).
+  *
+  * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
+  *    function) then to wait on event EV8 or EV8_2.
+  *    These two events are similar:
+  *     - EV8 means that the data has been written in the data register and is
+  *       being shifted out.
+  *     - EV8_2 means that the data has been physically shifted out and output
+  *       on the bus.
+  *     In most cases, using EV8 is sufficient for the application.
+  *     Using EV8_2 leads to a slower communication but ensure more reliable test.
+  *     EV8_2 is also more suitable than EV8 for testing on the last data transmission
+  *     (before Stop condition generation).
+  *
+  *  @note In case the  user software does not guarantee that this event EV7 is
+  *  managed before the current byte end of transfer, then user may check on EV7
+  *  and BTF flag at the same time (ie. (I2C_EVENT_MASTER_DATA_RECEIVED | I2C_FLAG_BTFF)).
+  *  In this case the communication may be slower.
+  *
+  */
+
+/* Master RECEIVER mode -----------------------------*/
+/* --EV7 */
+#define  I2C_EVENT_MASTER_DATA_RECEIVED                 ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
+
+/* Master TRANSMITTER mode --------------------------*/
+/* --EV8 */
+#define I2C_EVENT_MASTER_DATA_TRANSMITTING              ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+/* --EV8_2 */
+#define  I2C_EVENT_MASTER_DATA_TRANSMITTED              ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
+
+
+/*========================================
+
+                     I2C Slave Events (Events grouped in order of communication)
+                                                        ==========================================*/
+
+/**
+  * @brief  Communication start events
+  *
+  * Wait on one of these events at the start of the communication. It means that
+  * the I2C peripheral detected a Start condition on the bus (generated by master
+  * device) followed by the peripheral address. The peripheral generates an ACK
+  * condition on the bus (if the acknowledge feature is enabled through function
+  * I2C_AcknowledgeConfig()) and the events listed above are set :
+  *
+  * 1) In normal case (only one address managed by the slave), when the address
+  *   sent by the master matches the own address of the peripheral (configured by
+  *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
+  *   (where XXX could be TRANSMITTER or RECEIVER).
+  *
+  * 2) In case the address sent by the master matches the second address of the
+  *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled
+  *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
+  *   (where XXX could be TRANSMITTER or RECEIVER) are set.
+  *
+  * 3) In case the address sent by the master is General Call (address 0x00) and
+  *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
+  *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
+  *
+  */
+
+/* --EV1  (all the events below are variants of EV1) */
+/* 1) Case of One Single Address managed by the slave */
+#define  I2C_EVENT_SLAVE_ADDRESS_RECEIVER_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define  I2C_EVENT_SLAVE_ADDRESS_TRANSMITTER_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+
+/* 2) Case of Dual address managed by the slave */
+#define  I2C_EVENT_SLAVE_SECONDADDRESS_RECEIVER_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
+#define  I2C_EVENT_SLAVE_SECONDADDRESS_TRANSMITTER_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
+
+/* 3) Case of General Call enabled for the slave */
+#define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
+
+/**
+  * @brief  Communication events
+  *
+  * Wait on one of these events when EV1 has already been checked and:
+  *
+  * - Slave RECEIVER mode:
+  *     - EV2: When the application is expecting a data byte to be received.
+  *     - EV4: When the application is expecting the end of the communication: master
+  *       sends a stop condition and data transmission is stopped.
+  *
+  * - Slave Transmitter mode:
+  *    - EV3: When a byte has been transmitted by the slave and the application is expecting
+  *      the end of the byte transmission. The two events I2C_EVENT_SLAVE_DATA_TRANSMITTED and
+  *      I2C_EVENT_SLAVE_DATA_TRANSMITTING are similar. The second one can optionally be
+  *      used when the user software doesn't guarantee the EV3 is managed before the
+  *      current byte end of transfer.
+  *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission
+  *      shall end (before sending the STOP condition). In this case slave has to stop sending
+  *      data bytes and expect a Stop condition on the bus.
+  *
+  *  @note In case the  user software does not guarantee that the event EV2 is
+  *  managed before the current byte end of transfer, then user may check on EV2
+  *  and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_DATA_RECEIVED | I2C_FLAG_BTFF)).
+  * In this case the communication may be slower.
+  *
+  */
+
+/* Slave RECEIVER mode --------------------------*/
+/* --EV2 */
+#define  I2C_EVENT_SLAVE_DATA_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
+/* --EV4  */
+#define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
+
+/* Slave TRANSMITTER mode -----------------------*/
+/* --EV3 */
+#define  I2C_EVENT_SLAVE_DATA_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
+#define  I2C_EVENT_SLAVE_DATA_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
+/* --EV3_2 */
+#define  I2C_EVENT_SLAVE_ACK_FAILURE_DETECTED              ((uint32_t)0x00000400)  /* AF flag */
+
+/*===========================      End of Events Description           ==========================================*/
+
+#define IS_I2C_EVENT(EVENT)     (((EVENT) == I2C_EVENT_SLAVE_ADDRESS_TRANSMITTER_MATCHED)           || \
+                                 ((EVENT) == I2C_EVENT_SLAVE_ADDRESS_RECEIVER_MATCHED)              || \
+                                 ((EVENT) == I2C_EVENT_SLAVE_SECONDADDRESS_TRANSMITTER_MATCHED)     || \
+                                 ((EVENT) == I2C_EVENT_SLAVE_SECONDADDRESS_RECEIVER_MATCHED)        || \
+                                 ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED)            || \
+                                 ((EVENT) == I2C_EVENT_SLAVE_DATA_RECEIVED)                         || \
+                                 ((EVENT) == (I2C_EVENT_SLAVE_DATA_RECEIVED | I2C_FLAG_DUALF))      || \
+                                 ((EVENT) == (I2C_EVENT_SLAVE_DATA_RECEIVED | I2C_FLAG_GCADDRF))    || \
+                                 ((EVENT) == I2C_EVENT_SLAVE_DATA_TRANSMITTED)                      || \
+                                 ((EVENT) == (I2C_EVENT_SLAVE_DATA_TRANSMITTED | I2C_FLAG_DUALF))   || \
+                                 ((EVENT) == (I2C_EVENT_SLAVE_DATA_TRANSMITTED | I2C_FLAG_GCADDRF)) || \
+                                 ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED)                         || \
+                                 ((EVENT) == I2C_EVENT_MASTER_START_GENERATED)                      || \
+                                 ((EVENT) == I2C_EVENT_MASTER_ADDRESS)                              || \
+                                 ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER)                          || \
+                                 ((EVENT) == I2C_EVENT_MASTER_ADDRESS_WITH_RECEIVER)                || \
+                                 ((EVENT) == I2C_EVENT_MASTER_DATA_RECEIVED)                        || \
+                                 ((EVENT) == I2C_EVENT_MASTER_DATA_TRANSMITTED)                     || \
+                                 ((EVENT) == I2C_EVENT_MASTER_DATA_TRANSMITTING)                    || \
+                                 ((EVENT) == I2C_EVENT_MASTER_ADDRESS10_GENERATED)                  || \
+                                 ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE_DETECTED))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_own_address1
+  * @{
+  */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)       ((ADDRESS1) <= 0x3FF)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_clock_speed
+  * @{
+  */
+
+#define IS_I2C_BIT_RATE(RATE)               (((RATE) >= 0x1) && ((RATE) <= 400000))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions
+  * @{
+  */
+
+void I2C_DeInit(I2C_Type* I2Cx);
+void I2C_Init(I2C_Type* I2Cx, I2C_InitType* I2C_InitStruct);
+void I2C_StructInit(I2C_InitType* I2C_InitStruct);
+void I2C_Cmd(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_DMACmd(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_Type* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_INTConfig(I2C_Type* I2Cx, uint16_t I2C_INT, FunctionalState NewState);
+void I2C_SendData(I2C_Type* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_Type* I2Cx);
+void I2C_Send7bitAddress(I2C_Type* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_ReadRegister(I2C_Type* I2Cx, uint8_t I2C_Register);
+void I2C_SoftwareResetCmd(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_NACKPositionConfig(I2C_Type* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_SMBusAlertConfig(I2C_Type* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_TransmitPEC(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_PECPositionConfig(I2C_Type* I2Cx, uint16_t I2C_PECPosition);
+void I2C_CalculatePEC(I2C_Type* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_Type* I2Cx);
+void I2C_ARPCmd(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_Type* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_Type* I2Cx, uint16_t I2C_DutyCycle);
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ *                         I2C State Monitoring Functions
+ *
+ ****************************************************************************************
+ * This I2C driver provides three different ways for I2C state monitoring
+ *  depending on the application requirements and constraints:
+ *
+ *
+ * 1) Basic state monitoring:
+ *    Using I2C_CheckEvent() function:
+ *    It compares the status registers (SR1 and SR2) content to a given event
+ *    (can be the combination of one or more flags).
+ *    It returns SUCCESS if the current status includes the given flags
+ *    and returns ERROR if one or more flags are missing in the current status.
+ *    - When to use:
+ *      - This function is suitable for most applications as well as for startup
+ *      activity since the events are fully described in the product reference manual
+ *      (RM0008).
+ *      - It is also suitable for users who need to define their own events.
+ *    - Limitations:
+ *      - If an error occurs (ie. error flags are set besides to the monitored flags),
+ *        the I2C_CheckEvent() function may return SUCCESS despite the communication
+ *        hold or corrupted real state.
+ *        In this case, it is advised to use error interrupts to monitor the error
+ *        events and handle them in the interrupt IRQ handler.
+ *
+ *        @note
+ *        For error management, it is advised to use the following functions:
+ *          - I2C_INTConfig() to configure and enable the error interrupts (I2C_INT_ERR).
+ *          - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ *            Where x is the peripheral instance (I2C1, I2C2 ...)
+ *          - I2C_GetFlagStatus() or I2C_GetINTStatus() to be called into I2Cx_ER_IRQHandler()
+ *            in order to determine which error occurred.
+ *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
+ *            and/or I2C_GenerateStop() in order to clear the error flag and source,
+ *            and return to correct communication status.
+ *
+ *
+ *  2) Advanced state monitoring:
+ *     Using the function I2C_GetLastEvent() which returns the image of both status
+ *     registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ *     by 16 bits and concatenated to Status Register 1).
+ *     - When to use:
+ *       - This function is suitable for the same applications above but it allows to
+ *         overcome the limitations of I2C_GetFlagStatus() function (see below).
+ *         The returned value could be compared to events already defined in the
+ *         library (at32f4xx_i2c.h) or to custom values defined by user.
+ *       - This function is suitable when multiple flags are monitored at the same time.
+ *       - At the opposite of I2C_CheckEvent() function, this function allows user to
+ *         choose when an event is accepted (when all events flags are set and no
+ *         other flags are set or just when the needed flags are set like
+ *         I2C_CheckEvent() function).
+ *     - Limitations:
+ *       - User may need to define his own events.
+ *       - Same remark concerning the error management is applicable for this
+ *         function if user decides to check only regular communication flags (and
+ *         ignores error flags).
+ *
+ *
+ *  3) Flag-based state monitoring:
+ *     Using the function I2C_GetFlagStatus() which simply returns the status of
+ *     one single flag (ie. I2C_FLAG_RDNE ...).
+ *     - When to use:
+ *        - This function could be used for specific applications or in debug phase.
+ *        - It is suitable when only one flag checking is needed (most I2C events
+ *          are monitored through multiple flags).
+ *     - Limitations:
+ *        - When calling this function, the Status register is accessed. Some flags are
+ *          cleared when the status register is accessed. So checking the status
+ *          of one Flag, may clear other ones.
+ *        - Function may need to be called twice or more in order to monitor one
+ *          single event.
+ *
+ */
+
+/**
+ *
+ *  1) Basic state monitoring
+ *******************************************************************************
+ */
+ErrorStatus I2C_CheckEvent(I2C_Type* I2Cx, uint32_t I2C_EVENT);
+/**
+ *
+ *  2) Advanced state monitoring
+ *******************************************************************************
+ */
+uint32_t I2C_GetLastEvent(I2C_Type* I2Cx);
+/**
+ *
+ *  3) Flag-based state monitoring
+ *******************************************************************************
+ */
+FlagStatus I2C_GetFlagStatus(I2C_Type* I2Cx, uint32_t I2C_FLAG);
+/**
+ *
+ *******************************************************************************
+ */
+
+void I2C_ClearFlag(I2C_Type* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetINTStatus(I2C_Type* I2Cx, uint32_t I2C_INT);
+void I2C_ClearITPendingBit(I2C_Type* I2Cx, uint32_t I2C_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4xx_I2C_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_iwdg.h

@@ -0,0 +1,128 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_iwdg.h
+ * Description  : at32f4xx IWDG header file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_IWDG_H
+#define __AT32F4xx_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup IWDG
+  * @{
+  */
+
+/** @defgroup IWDG_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Constants
+  * @{
+  */
+
+/** @defgroup IWDG_WriteAccess
+  * @{
+  */
+
+#define IWDG_KeyRegWrite_Enable             ((uint16_t)0x5555)
+#define IWDG_KeyRegWrite_Disable            ((uint16_t)0x0000)
+#define IS_IWDG_KEY_REG_WRITE(WRITE)        (((WRITE) == IWDG_KeyRegWrite_Enable) || \
+                                             ((WRITE) == IWDG_KeyRegWrite_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_prescaler
+  * @{
+  */
+
+#define IWDG_Psc_4                          ((uint8_t)0x00)
+#define IWDG_Psc_8                          ((uint8_t)0x01)
+#define IWDG_Psc_16                         ((uint8_t)0x02)
+#define IWDG_Psc_32                         ((uint8_t)0x03)
+#define IWDG_Psc_64                         ((uint8_t)0x04)
+#define IWDG_Psc_128                        ((uint8_t)0x05)
+#define IWDG_Psc_256                        ((uint8_t)0x06)
+#define IS_IWDG_PSC(PSC)                    (((PSC) == IWDG_Psc_4)  || \
+                                             ((PSC) == IWDG_Psc_8)  || \
+                                             ((PSC) == IWDG_Psc_16) || \
+                                             ((PSC) == IWDG_Psc_32) || \
+                                             ((PSC) == IWDG_Psc_64) || \
+                                             ((PSC) == IWDG_Psc_128)|| \
+                                             ((PSC) == IWDG_Psc_256))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Flag
+  * @{
+  */
+
+#define IWDG_FLAG_PSCF                      ((uint16_t)0x0001)
+#define IWDG_FLAG_RLDF                      ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG)                  (((FLAG) == IWDG_FLAG_PSCF) || ((FLAG) == IWDG_FLAG_RLDF))
+#define IS_IWDG_RLD(RLD)                      ((RLD) <= 0xFFF)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Functions
+  * @{
+  */
+
+void IWDG_KeyRegWrite(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_IWDG_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_pwr.h

@@ -0,0 +1,156 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_pwr.h
+ * Description  : at32f4xx PWR header file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_PWR_H
+#define __AT32F4xx_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */
+
+/** @defgroup PWR_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Constants
+  * @{
+  */
+
+/** @defgroup PVD_detection_level
+  * @{
+  */
+
+#define PWR_PVDS_2V2                        ((uint32_t)0x00000000)
+#define PWR_PVDS_2V3                        ((uint32_t)0x00000020)
+#define PWR_PVDS_2V4                        ((uint32_t)0x00000040)
+#define PWR_PVDS_2V5                        ((uint32_t)0x00000060)
+#define PWR_PVDS_2V6                        ((uint32_t)0x00000080)
+#define PWR_PVDS_2V7                        ((uint32_t)0x000000A0)
+#define PWR_PVDS_2V8                        ((uint32_t)0x000000C0)
+#define PWR_PVDS_2V9                        ((uint32_t)0x000000E0)
+#define IS_PWR_PVD_LEVEL(LEVEL)             (((LEVEL) == PWR_PVDS_2V2) || ((LEVEL) == PWR_PVDS_2V3)|| \
+                                             ((LEVEL) == PWR_PVDS_2V4) || ((LEVEL) == PWR_PVDS_2V5)|| \
+                                             ((LEVEL) == PWR_PVDS_2V6) || ((LEVEL) == PWR_PVDS_2V7)|| \
+                                             ((LEVEL) == PWR_PVDS_2V8) || ((LEVEL) == PWR_PVDS_2V9))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SLEEP_mode_entry 
+  * @{
+  */
+
+#define PWR_SLEEPEntry_WFI              ((uint8_t)0x01)
+#define PWR_SLEEPEntry_WFE              ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
+
+/** @defgroup Regulator_state_is_STOP_mode
+  * @{
+  */
+#define PWR_Regulator_ON                    ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower              ((uint32_t)0x00000001)
+#define IS_PWR_REGULATOR(REGULATOR)         (((REGULATOR) == PWR_Regulator_ON) || \
+                                             ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+  * @}
+  */
+
+/** @defgroup STOP_mode_entry
+  * @{
+  */
+
+#define PWR_STOPEntry_WFI                   ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE                   ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY)            (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag
+  * @{
+  */
+
+#define PWR_FLAG_WUF                        ((uint32_t)0x00000001)
+#define PWR_FLAG_SBF                        ((uint32_t)0x00000002)
+#define PWR_FLAG_PVDO                       ((uint32_t)0x00000004)
+#define IS_PWR_GET_FLAG(FLAG)               (((FLAG) == PWR_FLAG_WUF) || ((FLAG) == PWR_FLAG_SBF) || \
+                                             ((FLAG) == PWR_FLAG_PVDO))
+
+#define IS_PWR_CLEAR_FLAG(FLAG)             (((FLAG) == PWR_FLAG_WUF) || ((FLAG) == PWR_FLAG_SBF))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions
+  * @{
+  */
+
+void PWR_Reset(void);
+void PWR_BackupAccessCtrl(FunctionalState NewState);
+void PWR_PVDCtrl(FunctionalState NewState);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinCtrl(FunctionalState NewState);
+void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
+#if defined (AT32F403xx) || defined (AT32F413xx)
+    void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry);
+#else
+    void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+#endif
+void PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_PWR_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_rcc.h

@@ -0,0 +1,784 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_rcc.h
+ * Description  : at32f4xx RCC header file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_RCC_H
+#define __AT32F4xx_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/** @defgroup RCC_Exported_Types
+  * @{
+  */
+
+typedef struct
+{
+    uint32_t SYSCLK_Freq;     /*!< returns SYSCLK clock frequency expressed in Hz */
+    uint32_t AHBCLK_Freq;     /*!< returns HCLK clock frequency expressed in Hz */
+    uint32_t APB1CLK_Freq;    /*!< returns PCLK1 clock frequency expressed in Hz */
+    uint32_t APB2CLK_Freq;    /*!< returns PCLK2 clock frequency expressed in Hz */
+    uint32_t ADCCLK_Freq;     /*!< returns ADCCLK clock frequency expressed in Hz */
+} RCC_ClockType;
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup HSE_configuration
+  * @{
+  */
+
+#define RCC_HSE_DISABLE                 ((uint32_t)0x00000000)
+#define RCC_HSE_ENABLE                  ((uint32_t)0x00010000)
+#define RCC_HSE_BYPASS                  ((uint32_t)0x00040000)
+#define IS_RCC_HSE(HSE)                 (((HSE) == RCC_HSE_DISABLE) || \
+                                         ((HSE) == RCC_HSE_ENABLE)  || \
+                                         ((HSE) == RCC_HSE_BYPASS))
+
+/**
+  * @}
+  */
+
+/** @defgroup PLL_entry_clock_source
+  * @{
+  */
+
+#define RCC_PLLRefClk_HSI_Div2          ((uint32_t)0x00000000)
+
+#define RCC_PLLRefClk_HSE_Div1          ((uint32_t)0x00010000)
+#define RCC_PLLRefClk_HSE_Div2          ((uint32_t)0x00030000)
+#define IS_RCC_PLL_CFG(CFG)             (((CFG) == RCC_PLLRefClk_HSI_Div2) || \
+                                         ((CFG) == RCC_PLLRefClk_HSE_Div1) || \
+                                         ((CFG) == RCC_PLLRefClk_HSE_Div2))
+
+
+/**
+  * @}
+  */
+#define RCC_PLL_RANGE                   72000000
+/** @defgroup PLL_clock_range_setting
+  * @{
+  */
+#define RCC_Range_LessEqual_72Mhz       ((uint32_t)0x00000000)
+#define RCC_Range_GreatThan_72Mhz       ((uint32_t)0x80000000)
+#define IS_RCC_PLL_RANGE(CFG)           (((CFG) == RCC_Range_LessEqual_72Mhz) || \
+                                         ((CFG) == RCC_Range_GreatThan_72Mhz))
+/**
+  * @}
+  */
+/** @defgroup PLL_multiplication_factor
+  * @{
+  */
+#define RCC_PLLMult_2                   RCC_CFG_PLLMULT2
+#define RCC_PLLMult_3                   RCC_CFG_PLLMULT3
+#define RCC_PLLMult_4                   RCC_CFG_PLLMULT4
+#define RCC_PLLMult_5                   RCC_CFG_PLLMULT5
+#define RCC_PLLMult_6                   RCC_CFG_PLLMULT6
+#define RCC_PLLMult_7                   RCC_CFG_PLLMULT7
+#define RCC_PLLMult_8                   RCC_CFG_PLLMULT8
+#define RCC_PLLMult_9                   RCC_CFG_PLLMULT9
+#define RCC_PLLMult_10                  RCC_CFG_PLLMULT10
+#define RCC_PLLMult_11                  RCC_CFG_PLLMULT11
+#define RCC_PLLMult_12                  RCC_CFG_PLLMULT12
+#define RCC_PLLMult_13                  RCC_CFG_PLLMULT13
+#define RCC_PLLMult_14                  RCC_CFG_PLLMULT14
+#define RCC_PLLMult_15                  RCC_CFG_PLLMULT15
+#define RCC_PLLMult_16                  RCC_CFG_PLLMULT16
+#define RCC_PLLMult_17                  RCC_CFG_PLLMULT17 
+#define RCC_PLLMult_18                  RCC_CFG_PLLMULT18 
+#define RCC_PLLMult_19                  RCC_CFG_PLLMULT19 
+#define RCC_PLLMult_20                  RCC_CFG_PLLMULT20 
+#define RCC_PLLMult_21                  RCC_CFG_PLLMULT21 
+#define RCC_PLLMult_22                  RCC_CFG_PLLMULT22 
+#define RCC_PLLMult_23                  RCC_CFG_PLLMULT23 
+#define RCC_PLLMult_24                  RCC_CFG_PLLMULT24 
+#define RCC_PLLMult_25                  RCC_CFG_PLLMULT25 
+#define RCC_PLLMult_26                  RCC_CFG_PLLMULT26 
+#define RCC_PLLMult_27                  RCC_CFG_PLLMULT27 
+#define RCC_PLLMult_28                  RCC_CFG_PLLMULT28 
+#define RCC_PLLMult_29                  RCC_CFG_PLLMULT29 
+#define RCC_PLLMult_30                  RCC_CFG_PLLMULT30 
+#define RCC_PLLMult_31                  RCC_CFG_PLLMULT31 
+#define RCC_PLLMult_32                  RCC_CFG_PLLMULT32 
+#define RCC_PLLMult_33                  RCC_CFG_PLLMULT33 
+#define RCC_PLLMult_34                  RCC_CFG_PLLMULT34 
+#define RCC_PLLMult_35                  RCC_CFG_PLLMULT35 
+#define RCC_PLLMult_36                  RCC_CFG_PLLMULT36 
+#define RCC_PLLMult_37                  RCC_CFG_PLLMULT37 
+#define RCC_PLLMult_38                  RCC_CFG_PLLMULT38 
+#define RCC_PLLMult_39                  RCC_CFG_PLLMULT39 
+#define RCC_PLLMult_40                  RCC_CFG_PLLMULT40 
+#define RCC_PLLMult_41                  RCC_CFG_PLLMULT41 
+#define RCC_PLLMult_42                  RCC_CFG_PLLMULT42 
+#define RCC_PLLMult_43                  RCC_CFG_PLLMULT43 
+#define RCC_PLLMult_44                  RCC_CFG_PLLMULT44 
+#define RCC_PLLMult_45                  RCC_CFG_PLLMULT45 
+#define RCC_PLLMult_46                  RCC_CFG_PLLMULT46 
+#define RCC_PLLMult_47                  RCC_CFG_PLLMULT47 
+#define RCC_PLLMult_48                  RCC_CFG_PLLMULT48 
+#define RCC_PLLMult_49                  RCC_CFG_PLLMULT49 
+#define RCC_PLLMult_50                  RCC_CFG_PLLMULT50 
+#define RCC_PLLMult_51                  RCC_CFG_PLLMULT51 
+#define RCC_PLLMult_52                  RCC_CFG_PLLMULT52 
+#define RCC_PLLMult_53                  RCC_CFG_PLLMULT53 
+#define RCC_PLLMult_54                  RCC_CFG_PLLMULT54 
+#define RCC_PLLMult_55                  RCC_CFG_PLLMULT55 
+#define RCC_PLLMult_56                  RCC_CFG_PLLMULT56 
+#define RCC_PLLMult_57                  RCC_CFG_PLLMULT57 
+#define RCC_PLLMult_58                  RCC_CFG_PLLMULT58 
+#define RCC_PLLMult_59                  RCC_CFG_PLLMULT59 
+#define RCC_PLLMult_60                  RCC_CFG_PLLMULT60 
+#define RCC_PLLMult_61                  RCC_CFG_PLLMULT61 
+#define RCC_PLLMult_62                  RCC_CFG_PLLMULT62 
+#define RCC_PLLMult_63                  RCC_CFG_PLLMULT63 
+#define RCC_PLLMult_64                  RCC_CFG_PLLMULT64 
+#define IS_RCC_PLL_MULT(MULT)           (((MULT) & (~RCC_CFG_PLLMULT)) == 0x00000000)
+
+#define RCC_GET_PLLMULT(MULT)           ((((MULT & RCC_CFG_PLLMULT_LB_MASK) >> RCC_CFG_PLLMULT_LB_POS) | \
+                                            ((MULT & RCC_CFG_PLLMULT_HB_MASK) >> (RCC_CFG_PLLMULT_HB_POS - RCC_CFG_PLLMULT_HB_OFFSET))) +\
+                                          ((((MULT & RCC_CFG_PLLMULT_HB_MASK)==0) && \
+                                            ((MULT & RCC_CFG_PLLMULT_LB_MASK)!=RCC_CFG_PLLMULT_LB_MASK) )? 2 : 1 ))
+											
+/**
+  * @}
+  */
+/** @defgroup System_clock_source
+  * @{
+  */
+
+#define RCC_SYSCLKSelction_HSI          ((uint32_t)0x00000000)
+#define RCC_SYSCLKSelction_HSE          ((uint32_t)0x00000001)
+#define RCC_SYSCLKSelction_PLL          ((uint32_t)0x00000002)
+#define IS_RCC_SYSCLK_CFG(CFG)          (((CFG) == RCC_SYSCLKSelction_HSI) || \
+                                         ((CFG) == RCC_SYSCLKSelction_HSE) || \
+                                         ((CFG) == RCC_SYSCLKSelction_PLL))
+/**
+  * @}
+  */
+
+/** @defgroup AHB_clock_source
+  * @{
+  */
+
+#define RCC_SYSCLK_Div1                 ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2                 ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4                 ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8                 ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16                ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64                ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128               ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256               ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512               ((uint32_t)0x000000F0)
+#define IS_RCC_AHBCLK(CLK)              (((CLK) == RCC_SYSCLK_Div1)   || ((CLK) == RCC_SYSCLK_Div2)   || \
+                                         ((CLK) == RCC_SYSCLK_Div4)   || ((CLK) == RCC_SYSCLK_Div8)   || \
+                                         ((CLK) == RCC_SYSCLK_Div16)  || ((CLK) == RCC_SYSCLK_Div64)  || \
+                                         ((CLK) == RCC_SYSCLK_Div128) || ((CLK) == RCC_SYSCLK_Div256) || \
+                                         ((CLK) == RCC_SYSCLK_Div512))
+/**
+  * @}
+  */
+
+/** @defgroup APB1_APB2_clock_source
+  * @{
+  */
+
+#define RCC_AHBCLK_Div1                 ((uint32_t)0x00000000)
+#define RCC_AHBCLK_Div2                 ((uint32_t)0x00000400)
+#define RCC_AHBCLK_Div4                 ((uint32_t)0x00000500)
+#define RCC_AHBCLK_Div8                 ((uint32_t)0x00000600)
+#define RCC_AHBCLK_Div16                ((uint32_t)0x00000700)
+#define IS_RCC_APBCLK(CLK)              (((CLK) == RCC_AHBCLK_Div1) || ((CLK) == RCC_AHBCLK_Div2) || \
+                                         ((CLK) == RCC_AHBCLK_Div4) || ((CLK) == RCC_AHBCLK_Div8) || \
+                                         ((CLK) == RCC_AHBCLK_Div16))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Interrupt_source
+  * @{
+  */
+
+#define RCC_INT_LSISTBL                 ((uint8_t)0x01)
+#define RCC_INT_LSESTBL                 ((uint8_t)0x02)
+#define RCC_INT_HSISTBL                 ((uint8_t)0x04)
+#define RCC_INT_HSESTBL                 ((uint8_t)0x08)
+#define RCC_INT_PLLSTBL                 ((uint8_t)0x10)
+#define RCC_INT_HSECFD                  ((uint8_t)0x80)
+
+#define IS_RCC_INT_EN(INT)              ((((INT) & (uint8_t)0xE0) == 0x00) && ((INT) != 0x00))
+#define IS_RCC_INT_STS(INT)             (((INT) == RCC_INT_LSISTBL) || ((INT) == RCC_INT_LSESTBL) || \
+                                         ((INT) == RCC_INT_HSISTBL) || ((INT) == RCC_INT_HSESTBL) || \
+                                         ((INT) == RCC_INT_PLLSTBL) || ((INT) == RCC_INT_HSECFD))
+#define IS_RCC_INT_CLR(INT)             ((((INT) & (uint8_t)0x60) == 0x00) && ((INT) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup USB_Device_clock_source
+  * @{
+  */
+#define RCC_USBCLKSelection_PLL_Div1_5   ((uint32_t)0x00000000)
+#define RCC_USBCLKSelection_PLL_Div1     ((uint32_t)0x00400000)
+#define RCC_USBCLKSelection_PLL_Div2_5   ((uint32_t)0x00800000)
+#define RCC_USBCLKSelection_PLL_Div2     ((uint32_t)0x00C00000)
+#define RCC_USBCLKSelection_PLL_Div3_5   ((uint32_t)0x08000000)
+#define RCC_USBCLKSelection_PLL_Div3     ((uint32_t)0x08400000)
+#define RCC_USBCLKSelection_PLL_Div4     ((uint32_t)0x08800000)
+
+#define IS_RCC_USBCLK_CFG(CFG)      (((CFG) == RCC_USBCLKSelection_PLL_Div1_5) || \
+                                     ((CFG) == RCC_USBCLKSelection_PLL_Div1)   || \
+                                     ((CFG) == RCC_USBCLKSelection_PLL_Div2_5) || \
+                                     ((CFG) == RCC_USBCLKSelection_PLL_Div2)   || \
+																		 ((CFG) == RCC_USBCLKSelection_PLL_Div3_5) || \
+																		 ((CFG) == RCC_USBCLKSelection_PLL_Div3)   || \
+																		 ((CFG) == RCC_USBCLKSelection_PLL_Div4))						
+/**
+  * @}
+  */
+
+/** @defgroup ADC_clock_source
+  * @{
+  */
+
+#define RCC_APB2CLK_Div2            ((uint32_t)0x00000000)
+#define RCC_APB2CLK_Div4            ((uint32_t)0x00004000)
+#define RCC_APB2CLK_Div6            ((uint32_t)0x00008000)
+#define RCC_APB2CLK_Div8            ((uint32_t)0x0000C000)
+#define RCC_APB2CLK_Div12           ((uint32_t)0x10004000)
+#define RCC_APB2CLK_Div16           ((uint32_t)0x1000C000)
+#define IS_RCC_ADCCLK(CLK)          (((CLK) == RCC_APB2CLK_Div2) || ((CLK) == RCC_APB2CLK_Div4) || \
+                                     ((CLK) == RCC_APB2CLK_Div6) || ((CLK) == RCC_APB2CLK_Div8) || \
+                                     ((CLK) == RCC_APB2CLK_Div12)|| ((CLK) == RCC_APB2CLK_Div16))
+/**
+  * @}
+  */
+
+/** @defgroup LSE_configuration
+  * @{
+  */
+
+#define RCC_LSE_DISABLE             ((uint8_t)0x00)
+#define RCC_LSE_ENABLE              ((uint8_t)0x01)
+#define RCC_LSE_BYPASS              ((uint8_t)0x04)
+#define IS_RCC_LSE(LSE)             (((LSE) == RCC_LSE_DISABLE) || ((LSE) == RCC_LSE_ENABLE) || \
+                                     ((LSE) == RCC_LSE_BYPASS))
+/**
+  * @}
+  */
+
+
+#if defined (AT32F415xx)
+/** @defgroup ERTC_clock_source
+  * @{
+  */
+#define RCC_ERTCCLKSelection_LSE             ((uint32_t)0x00000100)
+#define RCC_ERTCCLKSelection_LSI             ((uint32_t)0x00000200)
+#define RCC_ERTCCLKSelection_HSE_Div128      ((uint32_t)0x00000300)
+#define IS_RCC_ERTCCLK_SEL(SEL)              (((SEL) == RCC_ERTCCLKSelection_LSE) || \
+                                              ((SEL)  == RCC_ERTCCLKSelection_LSI) || \
+                                              ((SEL)  == RCC_ERTCCLKSelection_HSE_Div128))
+#else
+/** @defgroup RTC_clock_source
+  * @{
+  */
+#define RCC_RTCCLKSelection_LSE             ((uint32_t)0x00000100)
+#define RCC_RTCCLKSelection_LSI             ((uint32_t)0x00000200)
+#define RCC_RTCCLKSelection_HSE_Div128      ((uint32_t)0x00000300)
+#define IS_RCC_RTCCLK_SEL(SEL)              (((SEL) == RCC_RTCCLKSelection_LSE) || \
+                                              ((SEL) == RCC_RTCCLKSelection_LSI) || \
+                                              ((SEL) == RCC_RTCCLKSelection_HSE_Div128))
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup AHB_peripheral
+  * @{
+  */
+
+#define RCC_AHBPERIPH_DMA1          ((uint32_t)0x00000001)
+#define RCC_AHBPERIPH_DMA2          ((uint32_t)0x00000002)
+#define RCC_AHBPERIPH_SRAM          ((uint32_t)0x00000004)
+#define RCC_AHBPERIPH_FLASH         ((uint32_t)0x00000010)
+#define RCC_AHBPERIPH_CRC           ((uint32_t)0x00000040)
+#define RCC_AHBPERIPH_SDIO1         ((uint32_t)0x00000400)
+
+#if defined (AT32F403xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+#define RCC_AHBPERIPH_XMC           ((uint32_t)0x00000100)
+#define RCC_AHBPERIPH_SDIO2         ((uint32_t)0x00000800)
+#endif
+
+#if defined (AT32F403Axx) || defined (AT32F407xx)
+#define RCC_AHBPERIPH_ETHMAC        ((uint32_t)0x00004000)
+#define RCC_AHBPERIPH_ETHMACTX      ((uint32_t)0x00008000)
+#define RCC_AHBPERIPH_ETHMACRX      ((uint32_t)0x00010000)
+#define RCC_AHBPERIPH_ETHMACPTP     ((uint32_t)0x10000000)
+#endif
+
+#if defined (AT32F415xx)
+#define RCC_AHBPERIPH_USB           ((uint32_t)0x00001000)
+#endif
+
+#if defined (AT32F403xx)
+#define IS_RCC_AHB_PERIPH(PERIPH)   ((((PERIPH) & 0xFFFFF2A8) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F413xx)
+#define IS_RCC_AHB_PERIPH(PERIPH)   ((((PERIPH) & 0xFFFFFBA8) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F415xx)
+#define IS_RCC_AHB_PERIPH(PERIPH)   ((((PERIPH) & 0xFFFFEBA8) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_RCC_AHB_PERIPH(PERIPH)   ((((PERIPH) & 0xEFFE32A8) == 0x00) && ((PERIPH) != 0x00))
+#endif
+
+
+/**
+  * @}
+  */
+
+/** @defgroup APB2_peripheral
+  * @{
+  */
+
+#define RCC_APB2PERIPH_AFIO         ((uint32_t)0x00000001)
+#define RCC_APB2PERIPH_GPIOA        ((uint32_t)0x00000004)
+#define RCC_APB2PERIPH_GPIOB        ((uint32_t)0x00000008)
+#define RCC_APB2PERIPH_GPIOC        ((uint32_t)0x00000010)
+#define RCC_APB2PERIPH_GPIOD        ((uint32_t)0x00000020)
+#if !defined (AT32F403Axx) || !defined (AT32F407xx)
+#define RCC_APB2PERIPH_GPIOF        ((uint32_t)0x00000080)
+#endif
+#define RCC_APB2PERIPH_ADC1         ((uint32_t)0x00000200)
+#define RCC_APB2PERIPH_ADC2         ((uint32_t)0x00000400)
+#define RCC_APB2PERIPH_TMR1         ((uint32_t)0x00000800)
+#define RCC_APB2PERIPH_SPI1         ((uint32_t)0x00001000)
+#define RCC_APB2PERIPH_USART1       ((uint32_t)0x00004000)
+#define RCC_APB2PERIPH_TMR9         ((uint32_t)0x00080000)
+#define RCC_APB2PERIPH_TMR10        ((uint32_t)0x00100000)
+#define RCC_APB2PERIPH_TMR11        ((uint32_t)0x00200000)
+
+#if defined (AT32F403xx)
+#define RCC_APB2PERIPH_GPIOE        ((uint32_t)0x00000040)
+#define RCC_APB2PERIPH_GPIOG        ((uint32_t)0x00000100)
+#define RCC_APB2PERIPH_ADC3         ((uint32_t)0x00008000)
+#define RCC_APB2PERIPH_TMR15        ((uint32_t)0x00010000)
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define RCC_APB2PERIPH_GPIOE        ((uint32_t)0x00000040)
+#define RCC_APB2PERIPH_ADC3         ((uint32_t)0x00008000)
+#define RCC_APB2PERIPH_I2C3         ((uint32_t)0x00800000)
+#define RCC_APB2PERIPH_USART6       ((uint32_t)0x01000000)
+#define RCC_APB2PERIPH_UART7        ((uint32_t)0x02000000)
+#define RCC_APB2PERIPH_UART8        ((uint32_t)0x04000000)
+#endif
+
+#if !defined (AT32F415xx)
+#define RCC_APB2PERIPH_TMR8         ((uint32_t)0x00002000)
+#endif
+
+#if !defined (AT32F403xx)
+#define RCC_APB2PERIPH_ACC          ((uint32_t)0x00400000)
+#endif
+
+#if defined (AT32F415xx)
+#define RCC_APB2PERIPH_EFCB         ((uint32_t)0x00800000)
+#endif
+
+#if defined (AT32F403xx)
+#define IS_RCC_APB2_PERIPH(PERIPH)  ((((PERIPH) & 0xFFC60002) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F413xx)
+#define IS_RCC_APB2_PERIPH(PERIPH)  ((((PERIPH) & 0xFF878142) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F415xx)
+#define IS_RCC_APB2_PERIPH(PERIPH)  ((((PERIPH) & 0xFF078142) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_RCC_APB2_PERIPH(PERIPH)  ((((PERIPH) & 0xF8070182) == 0x00) && ((PERIPH) != 0x00))
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup APB1_peripheral
+  * @{
+  */
+
+#define RCC_APB1PERIPH_TMR2         ((uint32_t)0x00000001)
+#define RCC_APB1PERIPH_TMR3         ((uint32_t)0x00000002)
+#define RCC_APB1PERIPH_TMR4         ((uint32_t)0x00000004)
+#define RCC_APB1PERIPH_TMR5         ((uint32_t)0x00000008)
+#define RCC_APB1PERIPH_WWDG         ((uint32_t)0x00000800)
+#define RCC_APB1PERIPH_SPI2         ((uint32_t)0x00004000)
+#define RCC_APB1PERIPH_USART2       ((uint32_t)0x00020000)
+#define RCC_APB1PERIPH_USART3       ((uint32_t)0x00040000)
+#define RCC_APB1PERIPH_UART4        ((uint32_t)0x00080000)
+#define RCC_APB1PERIPH_UART5        ((uint32_t)0x00100000)
+#define RCC_APB1PERIPH_I2C1         ((uint32_t)0x00200000)
+#define RCC_APB1PERIPH_I2C2         ((uint32_t)0x00400000)
+#define RCC_APB1PERIPH_CAN1         ((uint32_t)0x02000000)
+#define RCC_APB1PERIPH_PWR          ((uint32_t)0x10000000)
+
+#if defined (AT32F403xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+#define RCC_APB1PERIPH_TMR6         ((uint32_t)0x00000010)
+#define RCC_APB1PERIPH_TMR7         ((uint32_t)0x00000020)
+#define RCC_APB1PERIPH_TMR12        ((uint32_t)0x00000040)
+#define RCC_APB1PERIPH_TMR13        ((uint32_t)0x00000080)
+#define RCC_APB1PERIPH_TMR14        ((uint32_t)0x00000100)
+#define RCC_APB1PERIPH_SPI3         ((uint32_t)0x00008000)
+#define RCC_APB1PERIPH_SPI4         ((uint32_t)0x00010000)
+#define RCC_APB1PERIPH_I2C3         ((uint32_t)0x04000000)
+#define RCC_APB1PERIPH_DAC          ((uint32_t)0x20000000)
+#endif
+
+#if defined (AT32F413xx)
+#define RCC_APB1PERIPH_CAN2         ((uint32_t)0x80000000)
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define RCC_APB1PERIPH_CAN2         ((uint32_t)0x04000000)
+#endif
+
+#if !defined (AT32F415xx)
+#define RCC_APB1PERIPH_USB          ((uint32_t)0x00800000)
+#define RCC_APB1PERIPH_BKP          ((uint32_t)0x08000000)
+#else
+#define RCC_APB1PERIPH_COMP         ((uint32_t)0x00000200)
+#endif
+
+#if defined (AT32F403xx)
+#define IS_RCC_APB1_PERIPH(PERIPH)  ((((PERIPH) & 0xC1003600) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F413xx)
+#define IS_RCC_APB1_PERIPH(PERIPH)  ((((PERIPH) & 0x6501B7F0) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F415xx)
+#define IS_RCC_APB1_PERIPH(PERIPH)  ((((PERIPH) & 0xED81B3F0) == 0x00) && ((PERIPH) != 0x00))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_RCC_APB1_PERIPH(PERIPH)  ((((PERIPH) & 0xC1003600) == 0x00) && ((PERIPH) != 0x00))
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup Clock_source_to_output_on_CLKOUT_pin
+  * @{
+  */
+#define RCC_CLKOUT_NOCLK            ((uint32_t)0x00000000)
+#define RCC_CLKOUT_SYSCLK           ((uint32_t)0x04000000)
+#define RCC_CLKOUT_HSI              ((uint32_t)0x05000000)
+#define RCC_CLKOUT_HSE              ((uint32_t)0x06000000)
+#define RCC_CLKOUT_PLL_Div2         ((uint32_t)0x07000000)
+#define RCC_CLKOUT_PLL_Div4         ((uint32_t)0x14000000)
+#define RCC_CLKOUT_USB              ((uint32_t)0x15000000)
+#define RCC_CLKOUT_ADC              ((uint32_t)0x16000000)
+#if !defined (AT32F403xx)
+#define RCC_CLKOUT_LSI              ((uint32_t)0x02000000)
+#define RCC_CLKOUT_LSE              ((uint32_t)0x03000000)
+#endif
+#if !defined (AT32F403xx)
+#define IS_RCC_CLKOUT(CLK)          (((CLK) == RCC_CLKOUT_NOCLK)    || ((CLK) == RCC_CLKOUT_HSI)      || \
+                                     ((CLK) == RCC_CLKOUT_SYSCLK)   || ((CLK) == RCC_CLKOUT_HSE)      || \
+                                     ((CLK) == RCC_CLKOUT_PLL_Div2) || ((CLK) == RCC_CLKOUT_PLL_Div4) || \
+                                     ((CLK) == RCC_CLKOUT_USB)      || ((CLK) == RCC_CLKOUT_ADC)      || \
+                                     ((CLK) == RCC_CLKOUT_LSI)      || ((CLK) == RCC_CLKOUT_LSE))
+#else
+#define IS_RCC_CLKOUT(CLK)          (((CLK) == RCC_CLKOUT_NOCLK)    || ((CLK) == RCC_CLKOUT_HSI)      || \
+                                     ((CLK) == RCC_CLKOUT_SYSCLK)   || ((CLK) == RCC_CLKOUT_HSE)      || \
+                                     ((CLK) == RCC_CLKOUT_PLL_Div2) || ((CLK) == RCC_CLKOUT_PLL_Div4) || \
+                                     ((CLK) == RCC_CLKOUT_USB)      || ((CLK) == RCC_CLKOUT_ADC))
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HSE_Divider
+  * @{
+  */
+#define RCC_HSE_DIV_MASK            RCC_MISC2_HSE_DIV_CTRL
+#define RCC_HSE_DIV_2               RCC_MISC2_HSE_DIV_CTRL_2
+#define RCC_HSE_DIV_3               RCC_MISC2_HSE_DIV_CTRL_3
+#define RCC_HSE_DIV_4               RCC_MISC2_HSE_DIV_CTRL_4
+#define RCC_HSE_DIV_5               RCC_MISC2_HSE_DIV_CTRL_5
+
+#define IS_RCC_HSEDIV(CLK)          (((CLK) == RCC_HSE_DIV_2) || ((CLK) == RCC_HSE_DIV_3) || \
+                                     ((CLK) == RCC_HSE_DIV_4) || ((CLK) == RCC_HSE_DIV_5))
+/**
+  * @}
+  */
+
+/** @defgroup Clock_source_to_output_MCOPRE
+  * @{
+  */
+#define  RCC_MCOPRE_MASK            RCC_MISC_MCOPRE_MASK
+#define  RCC_MCOPRE_1               RCC_MISC_MCOPRE_1
+#define  RCC_MCOPRE_2               RCC_MISC_MCOPRE_2
+#define  RCC_MCOPRE_4               RCC_MISC_MCOPRE_4
+#define  RCC_MCOPRE_8               RCC_MISC_MCOPRE_8
+#define  RCC_MCOPRE_16              RCC_MISC_MCOPRE_16
+#define  RCC_MCOPRE_64              RCC_MISC_MCOPRE_64
+#define  RCC_MCOPRE_128             RCC_MISC_MCOPRE_128
+#define  RCC_MCOPRE_256             RCC_MISC_MCOPRE_256
+#define  RCC_MCOPRE_512             RCC_MISC_MCOPRE_512
+
+#if !defined (AT32F403xx)
+#define IS_RCC_MCO(MCOPRE)          (((MCOPRE) == RCC_MCOPRE_1)    || ((MCOPRE) == RCC_MCOPRE_2)      || \
+                                     ((MCOPRE) == RCC_MCOPRE_4)    || ((MCOPRE) == RCC_MCOPRE_8)      || \
+                                     ((MCOPRE) == RCC_MCOPRE_16)   || ((MCOPRE) == RCC_MCOPRE_64)     || \
+                                     ((MCOPRE) == RCC_MCOPRE_128)  || ((MCOPRE) == RCC_MCOPRE_256)    || \
+                                     ((MCOPRE) == RCC_MCOPRE_512))
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flag
+  * @{
+  */
+
+#define RCC_FLAG_HSISTBL            ((uint8_t)0x21)
+#define RCC_FLAG_HSESTBL            ((uint8_t)0x31)
+#define RCC_FLAG_PLLSTBL            ((uint8_t)0x39)
+#define RCC_FLAG_LSESTBL            ((uint8_t)0x41)
+#define RCC_FLAG_LSISTBL            ((uint8_t)0x61)
+#define RCC_FLAG_PINRST             ((uint8_t)0x7A)
+#define RCC_FLAG_PORST              ((uint8_t)0x7B)
+#define RCC_FLAG_SWRST              ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST            ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST            ((uint8_t)0x7E)
+#define RCC_FLAG_LPRST              ((uint8_t)0x7F)
+
+#define IS_RCC_FLAG(FLAG)           (((FLAG) == RCC_FLAG_HSISTBL) || ((FLAG) == RCC_FLAG_HSESTBL) || \
+                                     ((FLAG) == RCC_FLAG_PLLSTBL) || ((FLAG) == RCC_FLAG_LSESTBL) || \
+                                     ((FLAG) == RCC_FLAG_LSISTBL) || ((FLAG) == RCC_FLAG_PINRST)  || \
+                                     ((FLAG) == RCC_FLAG_PORST)   || ((FLAG) == RCC_FLAG_SWRST)   || \
+                                     ((FLAG) == RCC_FLAG_IWDGRST) || ((FLAG) == RCC_FLAG_WWDGRST) || \
+                                     ((FLAG) == RCC_FLAG_LPRST))
+#if defined (AT32F403xx)
+#define IS_RCC_TWEAK_VALUE(VALUE)    ((VALUE) <= 0x1F)
+#else
+#define IS_RCC_TWEAK_VALUE(VALUE)    ((VALUE) <= 0x3F)
+#endif
+#define IS_RCC_CALIB_VALUE(VALUE)    ((VALUE) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#if defined (AT32F415xx)
+/** @defgroup RCC_PLL_Register_For_F415
+  * @{
+  */
+#define PLL_FR_POS                   0
+#define PLL_FR_MASK                  ((uint32_t)0x00000007)
+#define PLL_FR_1                     ((uint32_t)0x00000000)
+#define PLL_FR_2                     ((uint32_t)0x00000001)
+#define PLL_FR_4                     ((uint32_t)0x00000002)
+#define PLL_FR_8                     ((uint32_t)0x00000003)
+#define PLL_FR_16                    ((uint32_t)0x00000004)
+#define PLL_FR_32                    ((uint32_t)0x00000005)
+
+#define PLL_MS_POS                   4
+#define PLL_MS_MASK                  ((uint32_t)0x000000F0)
+
+#define PLL_NS_POS                   8
+#define PLL_NS_MASK                  ((uint32_t)0x0000FF00)
+
+#define PLL_FREF_POS                 24
+#define PLL_FREF_MASK                ((uint32_t)0x07000000)
+#define PLL_FREF_4M                  ((uint32_t)0x00000000)
+#define PLL_FREF_6M                  ((uint32_t)0x01000000)
+#define PLL_FREF_8M                  ((uint32_t)0x02000000)
+#define PLL_FREF_12M                 ((uint32_t)0x03000000)
+#define PLL_FREF_16M                 ((uint32_t)0x04000000)
+#define PLL_FREF_25M                 ((uint32_t)0x05000000)
+
+#define PLL_CFGGEN_POS               31
+#define PLL_CFGEN_ENABLE             ((uint32_t)0x80000000)
+#define PLL_CFGEN_MASK               ((uint32_t)0x80000000)
+
+#define IS_RCC_FR(PLL_FR)            (((PLL_FR) == PLL_FR_1)    || ((PLL_FR) == PLL_FR_2)      || \
+                                      ((PLL_FR) == PLL_FR_4)    || ((PLL_FR) == PLL_FR_8)      || \
+                                      ((PLL_FR) == PLL_FR_16)   || ((PLL_FR) == PLL_FR_32))
+
+#define IS_RCC_FREF(PLL_FREF)        (((PLL_FREF) == PLL_FREF_4M)  || ((PLL_FREF) == PLL_FREF_6M)    || \
+                                      ((PLL_FREF) == PLL_FREF_8M)  || ((PLL_FREF) == PLL_FREF_12M)   || \
+                                      ((PLL_FREF) == PLL_FREF_16M) || ((PLL_FREF) == PLL_FREF_25M))
+
+#define IS_RCC_MS_VALUE(VALUE)       (((VALUE) >= 0x1) && ((VALUE) <= 0xF))
+#define IS_RCC_NS_VALUE(VALUE)       (((VALUE) >= 0x1F) && ((VALUE) <= 0x1F4))
+#define IS_RCC_RESULT_VALUE(VALUE)   (((VALUE) >= 0x1F4) && ((VALUE) <= 0x3E8))
+
+#define RCC_FREF_VALUE(VALUE, RET)   do                         \
+                                     {                          \
+                                       switch (VALUE)           \
+                                       {                        \
+                                         case PLL_FREF_4M:      \
+                                         RET = 4;               \
+                                         break;                 \
+                                         case PLL_FREF_6M:      \
+                                         RET = 6;               \
+                                         break;                 \
+                                         case PLL_FREF_8M:      \
+                                         RET = 8;               \
+                                         break;                 \
+                                         case PLL_FREF_12M:     \
+                                         RET = 12;              \
+                                         break;                 \
+                                         case PLL_FREF_16M:     \
+                                         RET = 16;              \
+                                         break;                 \
+                                         case PLL_FREF_25M:     \
+                                         RET = 25;              \
+                                         break;                 \
+                                         default:               \
+                                         RET = 0;               \
+                                         break;                 \
+                                       }                        \
+                                     }while(0)
+
+#define RCC_FR_VALUE(VALUE, RET)     do                         \
+                                     {                          \
+                                       switch (VALUE)           \
+                                       {                        \
+                                         case PLL_FR_1:         \
+                                         RET = 1;               \
+                                         break;                 \
+                                         case PLL_FR_2:         \
+                                         RET = 2;               \
+                                         break;                 \
+                                         case PLL_FR_4:         \
+                                         RET = 4;               \
+                                         break;                 \
+                                         case PLL_FR_8:         \
+                                         RET = 8;               \
+                                         break;                 \
+                                         case PLL_FR_16:        \
+                                         RET = 16;              \
+                                         break;                 \
+                                         case PLL_FR_32:        \
+                                         RET = 32;              \
+                                         break;                 \
+                                         default:               \
+                                         RET = 1;               \
+                                         break;                 \
+                                       }                        \
+                                     }while(0)
+/**
+  * @}
+  */
+#endif
+
+/**
+  * @}
+  */
+  
+/** @defgroup RCC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Exported_Functions
+  * @{
+  */
+
+void RCC_Reset(void);
+void RCC_HSEConfig(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStable(void);
+void RCC_SetHSITweakValue(uint8_t HSITweakValue);
+void RCC_SetHSICalibValue(uint8_t HSICalibValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLRefClk, uint32_t RCC_PLLMult, uint32_t RCC_PLLRange);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSelect);
+uint8_t RCC_GetSYSCLKSelction(void);
+void RCC_AHBCLKConfig(uint32_t RCC_SYSCLK_Div);
+void RCC_APB1CLKConfig(uint32_t RCC_HCLK_Div);
+void RCC_APB2CLKConfig(uint32_t RCC_HCLK_Div);
+void RCC_INTConfig(uint8_t RCC_INT, FunctionalState NewState);
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2_Div);
+void RCC_LSEConfig(uint8_t RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+#if defined (AT32F415xx)
+void RCC_ERTCCLKConfig(uint32_t RCC_ERTCCLKSelect);
+void RCC_ERTCCLKCmd(FunctionalState NewState);
+#else
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSelect);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+#endif
+void RCC_GetClocksFreq(RCC_ClockType* RCC_Clocks);
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+#if defined (AT32F403Axx) || defined (AT32F407xx)
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+#endif
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_HSEClockFailureDetectorCmd(FunctionalState NewState);
+#if defined (AT32F403xx)
+void RCC_CLKOUTConfig(uint32_t RCC_CLKOUT);
+#else
+void RCC_CLKOUTConfig(uint32_t RCC_CLKOUT, uint32_t RCC_CLKOUTPRE);
+#endif
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_Flag);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetINTStatus(uint8_t RCC_INT);
+void RCC_ClearINTPendingBit(uint8_t RCC_INT);
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSelect);
+void RCC_StepModeCmd(FunctionalState NewState);
+void RCC_USBINTRemap(FunctionalState NewState);
+void RCC_HSI2USB48M(FunctionalState NewState);
+void RCC_MCO2TMR10(FunctionalState NewState);
+#if defined (AT32F415xx)
+void RCC_PLLconfig2(uint32_t PLL_FREF, uint32_t PLL_NS, uint32_t PLL_MS, \
+                    uint32_t PLL_FR);
+#endif
+#if defined (AT32F403Axx) || defined (AT32F407xx)
+void RCC_HSEDivConfig(uint32_t HSEDiv);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_RCC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_rtc.h

@@ -0,0 +1,123 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_rtc.h
+ * Description  : at32f4xx RTC header file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_RTC_H
+#define __AT32F4xx_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RTC
+  * @{
+  */
+
+/** @defgroup RTC_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup RTC_interrupts_define
+  * @{
+  */
+
+#define RTC_INT_OV                          ((uint16_t)0x0004)  /*!< Overflow interrupt */
+#define RTC_INT_ALA                         ((uint16_t)0x0002)  /*!< Alarm interrupt */
+#define RTC_INT_PACE                        ((uint16_t)0x0001)  /*!< Second interrupt */
+#define IS_RTC_INT(INT)                     ((((INT) & (uint16_t)0xFFF8) == 0x00) && ((INT) != 0x00))
+#define IS_RTC_GET_INT(INT)                 (((INT) == RTC_INT_OV) || ((INT) == RTC_INT_ALA) || \
+                                             ((INT) == RTC_INT_PACE))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_interrupts_flags
+  * @{
+  */
+
+#define RTC_FLAG_RTF                        ((uint16_t)0x0020)  /*!< RTC Operation OFF flag */
+#define RTC_FLAG_RSYNF                      ((uint16_t)0x0008)  /*!< Registers Synchronized flag */
+#define RTC_FLAG_OV                         ((uint16_t)0x0004)  /*!< Overflow flag */
+#define RTC_FLAG_ALA                        ((uint16_t)0x0002)  /*!< Alarm flag */
+#define RTC_FLAG_PACE                       ((uint16_t)0x0001)  /*!< Second flag */
+#define IS_RTC_CLEAR_FLAG(FLAG)             ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
+#define IS_RTC_GET_FLAG(FLAG)               (((FLAG) == RTC_FLAG_RTF) || ((FLAG) == RTC_FLAG_RSYNF) || \
+                                             ((FLAG) == RTC_FLAG_OV)  || ((FLAG) == RTC_FLAG_ALA)   || \
+                                             ((FLAG) == RTC_FLAG_PACE))
+#define IS_RTC_DIV(DIV)                      ((DIV) <= 0xFFFFF)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Functions
+  * @{
+  */
+
+void RTC_INTConfig(uint16_t RTC_INT, FunctionalState NewState);
+void RTC_EnterConfigMode(void);
+void RTC_ExitConfigMode(void);
+uint32_t  RTC_GetCounter(void);
+void RTC_SetCounter(uint32_t CounterValue);
+void RTC_SetDIV(uint32_t PrescalerValue);
+void RTC_SetAlarmValue(uint32_t AlarmValue);
+uint32_t  RTC_GetDivider(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchro(void);
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
+void RTC_ClearFlag(uint16_t RTC_FLAG);
+ITStatus RTC_GetINTStatus(uint16_t RTC_INT);
+void RTC_ClearINTPendingBit(uint16_t RTC_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_RTC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_sdio.h

@@ -0,0 +1,526 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_sdio.h
+ * Description  : at32f4xx SDIO header file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_SDIO_H
+#define __AT32F4xx_SDIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SDIO
+  * @{
+  */
+
+/** @defgroup SDIO_Exported_Types
+  * @{
+  */
+
+typedef struct
+{
+    uint32_t SDIO_ClkEdge;                  /*!< Specifies the clock transition on which the bit capture is made.
+                                                 This parameter can be a value of @ref SDIO_Clock_Edge */
+                                            
+    uint32_t SDIO_ClkBypass;                /*!< Specifies whether the SDIO Clock divider bypass is
+                                                 enabled or disabled.
+                                                 This parameter can be a value of @ref SDIO_Clock_Bypass */
+                                            
+    uint32_t SDIO_ClkPowerSave;             /*!< Specifies whether SDIO Clock output is enabled or
+                                                 disabled when the bus is idle.
+                                                 This parameter can be a value of @ref SDIO_Clock_Power_Save */
+                                            
+    uint32_t SDIO_BusWidth;                 /*!< Specifies the SDIO bus width.
+                                                 This parameter can be a value of @ref SDIO_Bus_Wide */
+                                            
+    uint32_t SDIO_FlowCtrl;                 /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
+                                                 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+                                            
+    uint16_t SDIO_ClkPsc;                    /*!< Specifies the clock frequency of the SDIO controller.
+                                                 This parameter can be a value between 0x00 and 0x3FF. */
+
+} SDIO_InitType;
+
+typedef struct
+{
+    uint32_t SDIO_Argu;                     /*!< Specifies the SDIO command argument which is sent
+                                                 to a card as part of a command message. If a command
+                                                 contains an argument, it must be loaded into this register
+                                                 before writing the command to the command register */
+                                            
+    uint32_t SDIO_CmdIdx;                   /*!< Specifies the SDIO command index. It must be lower than 0x40. */
+                                            
+    uint32_t SDIO_Resp;                     /*!< Specifies the SDIO response type.
+                                                 This parameter can be a value of @ref SDIO_Response_Type */
+                                            
+    uint32_t SDIO_Wait;                     /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+                                                 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+                                            
+    uint32_t SDIO_CPSM;                     /*!< Specifies whether SDIO Command path state machine (CPSM)
+                                                 is enabled or disabled.
+                                                 This parameter can be a value of @ref SDIO_CPSM_State */
+} SDIO_CmdInitType;
+
+typedef struct
+{
+    uint32_t SDIO_DataTimeOut;              /*!< Specifies the data timeout period in card bus clock periods. */
+                                            
+    uint32_t SDIO_DataLen;                  /*!< Specifies the number of data bytes to be transferred. */
+                                            
+    uint32_t SDIO_DataBlkSize;              /*!< Specifies the data block size for block transfer.
+                                               This parameter can be a value of @ref SDIO_Data_Block_Size */
+                                            
+    uint32_t SDIO_TransferDir;              /*!< Specifies the data transfer direction, whether the transfer
+                                               is a read or write.
+                                               This parameter can be a value of @ref SDIO_Transfer_Direction */
+                                            
+    uint32_t SDIO_TransferMode;             /*!< Specifies whether data transfer is in stream or block mode.
+                                               This parameter can be a value of @ref SDIO_Transfer_Type */
+                                            
+    uint32_t SDIO_DPSM;                     /*!< Specifies whether SDIO Data path state machine (DPSM)
+                                               is enabled or disabled.
+                                               This parameter can be a value of @ref SDIO_DPSM_State */
+} SDIO_DataInitType;
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constants
+  * @{
+  */
+
+#if defined (AT32F413xx) || defined (AT32F415xx)
+#define IS_SDIO_ALL_PERIPH(PERIPH)          ((PERIPH) == SDIO)
+#elif defined (AT32F403xx) || defined (AT32F403Axx) || \
+      defined (AT32F407xx)
+#define IS_SDIO_ALL_PERIPH(PERIPH)          (((PERIPH) == SDIO1) || \
+                                             ((PERIPH) == SDIO2))
+#endif
+/** @defgroup SDIO_Clock_Edge
+  * @{
+  */
+
+#define SDIO_ClkEdge_Rising                 ((uint32_t)0x00000000)
+#define SDIO_ClkEdge_Falling                ((uint32_t)0x00002000)
+#define IS_SDIO_CLK_EDGE(EDGE)              (((EDGE) == SDIO_ClkEdge_Rising) || \
+                                             ((EDGE) == SDIO_ClkEdge_Falling))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Clock_Bypass
+  * @{
+  */
+
+#define SDIO_ClkBypass_Disable              ((uint32_t)0x00000000)
+#define SDIO_ClkBypass_Enable               ((uint32_t)0x00000400)
+#define IS_SDIO_CLK_BYPASS(BYPASS)          (((BYPASS) == SDIO_ClkBypass_Disable) || \
+                                             ((BYPASS) == SDIO_ClkBypass_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Clock_Power_Save
+  * @{
+  */
+
+#define SDIO_ClkPowerSave_Disable           ((uint32_t)0x00000000)
+#define SDIO_ClkPowerSave_Enable            ((uint32_t)0x00000200)
+#define IS_SDIO_CLK_POWER_SAVE(SAVE)        (((SAVE) == SDIO_ClkPowerSave_Disable) || \
+                                             ((SAVE) == SDIO_ClkPowerSave_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Bus_Wide
+  * @{
+  */
+
+#define SDIO_BusWidth_1b                    ((uint32_t)0x00000000)
+#define SDIO_BusWidth_4b                    ((uint32_t)0x00000800)
+#define SDIO_BusWidth_8b                    ((uint32_t)0x00001000)
+#define IS_SDIO_BUS_WIDTH(WIDTH)            (((WIDTH) == SDIO_BusWidth_1b) || ((WIDTH) == SDIO_BusWidth_4b) || \
+                                             ((WIDTH) == SDIO_BusWidth_8b))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Hardware_Flow_Control
+  * @{
+  */
+
+#define SDIO_FlowCtrl_Disable               ((uint32_t)0x00000000)
+#define SDIO_FlowCtrl_Enable                ((uint32_t)0x00004000)
+#define IS_SDIO_FLOW_CTRL(CTRL)             (((CTRL) == SDIO_FlowCtrl_Disable) || \
+                                             ((CTRL) == SDIO_FlowCtrl_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Power_State
+  * @{
+  */
+
+#define SDIO_PowerSave_OFF                  ((uint32_t)0x00000000)
+#define SDIO_PowerSave_ON                   ((uint32_t)0x00000003)
+#define IS_SDIO_POWER_SAVE(SAVE)            (((SAVE) == SDIO_PowerSave_OFF) || ((SAVE) == SDIO_PowerSave_ON))
+/**
+  * @}
+  */
+
+
+/** @defgroup SDIO_Interrupt_sources
+  * @{
+  */
+
+#define SDIO_INT_CMDFAIL                    ((uint32_t)0x00000001)
+#define SDIO_INT_DTFAIL                     ((uint32_t)0x00000002)
+#define SDIO_INT_CMDTIMEOUT                 ((uint32_t)0x00000004)
+#define SDIO_INT_DTTIMEOUT                  ((uint32_t)0x00000008)
+#define SDIO_INT_TXERRU                     ((uint32_t)0x00000010)
+#define SDIO_INT_RXERRO                     ((uint32_t)0x00000020)
+#define SDIO_INT_CMDRSPCMPL                 ((uint32_t)0x00000040)
+#define SDIO_INT_CMDCMPL                    ((uint32_t)0x00000080)
+#define SDIO_INT_DTCMPL                     ((uint32_t)0x00000100)
+#define SDIO_INT_SBITERR                    ((uint32_t)0x00000200)
+#define SDIO_INT_DTBLKCMPL                  ((uint32_t)0x00000400)
+#define SDIO_INT_DOCMD                      ((uint32_t)0x00000800)
+#define SDIO_INT_DOTX                       ((uint32_t)0x00001000)
+#define SDIO_INT_DORX                       ((uint32_t)0x00002000)
+#define SDIO_INT_TXBUF_H                    ((uint32_t)0x00004000)
+#define SDIO_INT_RXBUF_H                    ((uint32_t)0x00008000)
+#define SDIO_INT_TXBUF_F                    ((uint32_t)0x00010000)
+#define SDIO_INT_RXBUF_F                    ((uint32_t)0x00020000)
+#define SDIO_INT_TXBUF_E                    ((uint32_t)0x00040000)
+#define SDIO_INT_RXBUF_E                    ((uint32_t)0x00080000)
+#define SDIO_INT_TXBUF                      ((uint32_t)0x00100000)
+#define SDIO_INT_RXBUF                      ((uint32_t)0x00200000)
+#define SDIO_INT_SDIOIF                     ((uint32_t)0x00400000)
+#define SDIO_INT_ATACMPL                    ((uint32_t)0x00800000)
+#define IS_SDIO_INT(INT)                    ((((INT) & (uint32_t)0xFF000000) == 0x00) && ((INT) != (uint32_t)0x00))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Command_Index
+  * @{
+  */
+
+#define IS_SDIO_CMD_IDX(IDX)                ((IDX) < 0x40)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Response_Type
+  * @{
+  */
+
+#define SDIO_Rsp_No                         ((uint32_t)0x00000000)
+#define SDIO_Rsp_Short                      ((uint32_t)0x00000040)
+#define SDIO_Rsp_Long                       ((uint32_t)0x000000C0)
+#define IS_SDIO_RSP_TYPE(TYPE)              (((TYPE) == SDIO_Rsp_No) || \
+                                             ((TYPE) == SDIO_Rsp_Short) || \
+                                             ((TYPE) == SDIO_Rsp_Long))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Wait_Interrupt_State
+  * @{
+  */
+
+#define SDIO_Wait_No                        ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
+#define SDIO_Wait_INT                       ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
+#define SDIO_Wait_Pend                      ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
+#define IS_SDIO_WAIT(WAIT)                  (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_INT) || \
+                                             ((WAIT) == SDIO_Wait_Pend))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_CPSM_State
+  * @{
+  */
+
+#define SDIO_CPSM_Disable                   ((uint32_t)0x00000000)
+#define SDIO_CPSM_Enable                    ((uint32_t)0x00000400)
+#define IS_SDIO_CPSM(CPSM)                  (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Response_Registers
+  * @{
+  */
+
+#define SDIO_RSP1                           ((uint32_t)0x00000000)
+#define SDIO_RSP2                           ((uint32_t)0x00000004)
+#define SDIO_RSP3                           ((uint32_t)0x00000008)
+#define SDIO_RSP4                           ((uint32_t)0x0000000C)
+#define IS_SDIO_RSP(RSP)                    (((RSP) == SDIO_RSP1) || ((RSP) == SDIO_RSP2) || \
+                                             ((RSP) == SDIO_RSP3) || ((RSP) == SDIO_RSP4))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Length
+  * @{
+  */
+
+#define IS_SDIO_DATA_LEN(LEN)               ((LEN) <= 0x01FFFFFF)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Block_Size
+  * @{
+  */
+
+#define SDIO_DataBlkSize_1b                 ((uint32_t)0x00000000)
+#define SDIO_DataBlkSize_2b                 ((uint32_t)0x00000010)
+#define SDIO_DataBlkSize_4b                 ((uint32_t)0x00000020)
+#define SDIO_DataBlkSize_8b                 ((uint32_t)0x00000030)
+#define SDIO_DataBlkSize_16b                ((uint32_t)0x00000040)
+#define SDIO_DataBlkSize_32b                ((uint32_t)0x00000050)
+#define SDIO_DataBlkSize_64b                ((uint32_t)0x00000060)
+#define SDIO_DataBlkSize_128b               ((uint32_t)0x00000070)
+#define SDIO_DataBlkSize_256b               ((uint32_t)0x00000080)
+#define SDIO_DataBlkSize_512b               ((uint32_t)0x00000090)
+#define SDIO_DataBlkSize_1024b              ((uint32_t)0x000000A0)
+#define SDIO_DataBlkSize_2048b              ((uint32_t)0x000000B0)
+#define SDIO_DataBlkSize_4096b              ((uint32_t)0x000000C0)
+#define SDIO_DataBlkSize_8192b              ((uint32_t)0x000000D0)
+#define SDIO_DataBlkSize_16384b             ((uint32_t)0x000000E0)
+#define IS_SDIO_BLK_SIZE(SIZE)              (((SIZE) == SDIO_DataBlkSize_1b)    || \
+                                             ((SIZE) == SDIO_DataBlkSize_2b)    || \
+                                             ((SIZE) == SDIO_DataBlkSize_4b)    || \
+                                             ((SIZE) == SDIO_DataBlkSize_8b)    || \
+                                             ((SIZE) == SDIO_DataBlkSize_16b)   || \
+                                             ((SIZE) == SDIO_DataBlkSize_32b)   || \
+                                             ((SIZE) == SDIO_DataBlkSize_64b)   || \
+                                             ((SIZE) == SDIO_DataBlkSize_128b)  || \
+                                             ((SIZE) == SDIO_DataBlkSize_256b)  || \
+                                             ((SIZE) == SDIO_DataBlkSize_512b)  || \
+                                             ((SIZE) == SDIO_DataBlkSize_1024b) || \
+                                             ((SIZE) == SDIO_DataBlkSize_2048b) || \
+                                             ((SIZE) == SDIO_DataBlkSize_4096b) || \
+                                             ((SIZE) == SDIO_DataBlkSize_8192b) || \
+                                             ((SIZE) == SDIO_DataBlkSize_16384b))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Direction
+  * @{
+  */
+
+#define SDIO_TransferDir_ToCard             ((uint32_t)0x00000000)
+#define SDIO_TransferDir_ToSDIO             ((uint32_t)0x00000002)
+#define IS_SDIO_TRANSFER_DIR(DIR)           (((DIR) == SDIO_TransferDir_ToCard) || \
+                                             ((DIR) == SDIO_TransferDir_ToSDIO))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Type
+  * @{
+  */
+
+#define SDIO_TransferMode_Block             ((uint32_t)0x00000000)
+#define SDIO_TransferMode_Stream            ((uint32_t)0x00000004)
+#define IS_SDIO_TRANSFER_MODE(MODE)         (((MODE) == SDIO_TransferMode_Stream) || \
+                                             ((MODE) == SDIO_TransferMode_Block))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_DPSM_State
+  * @{
+  */
+
+#define SDIO_DPSM_Disable                   ((uint32_t)0x00000000)
+#define SDIO_DPSM_Enable                    ((uint32_t)0x00000001)
+#define IS_SDIO_DPSM(DPSM)                  (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Flags
+  * @{
+  */
+
+#define SDIO_FLG_CMDFAIL                    ((uint32_t)0x00000001)
+#define SDIO_FLG_DTFAIL                     ((uint32_t)0x00000002)
+#define SDIO_FLG_CMDTIMEOUT                 ((uint32_t)0x00000004)
+#define SDIO_FLG_DTTIMEOUT                  ((uint32_t)0x00000008)
+#define SDIO_FLG_TXERRU                     ((uint32_t)0x00000010)
+#define SDIO_FLG_RXERRO                     ((uint32_t)0x00000020)
+#define SDIO_FLG_CMDRSPCMPL                 ((uint32_t)0x00000040)
+#define SDIO_FLG_CMDCMPL                    ((uint32_t)0x00000080)
+#define SDIO_FLG_DTCMPL                     ((uint32_t)0x00000100)
+#define SDIO_FLG_SBITERR                    ((uint32_t)0x00000200)
+#define SDIO_FLG_DTBLKCMPL                  ((uint32_t)0x00000400)
+#define SDIO_FLG_DOCMD                      ((uint32_t)0x00000800)
+#define SDIO_FLG_DOTX                       ((uint32_t)0x00001000)
+#define SDIO_FLG_DORX                       ((uint32_t)0x00002000)
+#define SDIO_FLG_TXBUF_H                    ((uint32_t)0x00004000)
+#define SDIO_FLG_RXBUF_H                    ((uint32_t)0x00008000)
+#define SDIO_FLG_TXBUF_F                    ((uint32_t)0x00010000)
+#define SDIO_FLG_RXBUF_F                    ((uint32_t)0x00020000)
+#define SDIO_FLG_TXBUF_E                    ((uint32_t)0x00040000)
+#define SDIO_FLG_RXBUF_E                    ((uint32_t)0x00080000)
+#define SDIO_FLG_TXBUF                      ((uint32_t)0x00100000)
+#define SDIO_FLG_RXBUF                      ((uint32_t)0x00200000)
+#define SDIO_FLG_SDIOIF                     ((uint32_t)0x00400000)
+#define SDIO_FLG_ATACMPL                    ((uint32_t)0x00800000)
+#define IS_SDIO_FLG(FLG)                    (((FLG)  == SDIO_FLG_CMDFAIL)    || \
+                                             ((FLG)  == SDIO_FLG_DTFAIL)     || \
+                                             ((FLG)  == SDIO_FLG_CMDTIMEOUT) || \
+                                             ((FLG)  == SDIO_FLG_DTTIMEOUT)  || \
+                                             ((FLG)  == SDIO_FLG_TXERRU)     || \
+                                             ((FLG)  == SDIO_FLG_RXERRO)     || \
+                                             ((FLG)  == SDIO_FLG_CMDRSPCMPL) || \
+                                             ((FLG)  == SDIO_FLG_CMDCMPL)    || \
+                                             ((FLG)  == SDIO_FLG_DTCMPL)     || \
+                                             ((FLG)  == SDIO_FLG_SBITERR)    || \
+                                             ((FLG)  == SDIO_FLG_DTBLKCMPL)  || \
+                                             ((FLG)  == SDIO_FLG_DOCMD)      || \
+                                             ((FLG)  == SDIO_FLG_DOTX)       || \
+                                             ((FLG)  == SDIO_FLG_DORX)       || \
+                                             ((FLG)  == SDIO_FLG_TXBUF_H)    || \
+                                             ((FLG)  == SDIO_FLG_RXBUF_H)    || \
+                                             ((FLG)  == SDIO_FLG_TXBUF_F)    || \
+                                             ((FLG)  == SDIO_FLG_RXBUF_F)    || \
+                                             ((FLG)  == SDIO_FLG_TXBUF_E)    || \
+                                             ((FLG)  == SDIO_FLG_RXBUF_E)    || \
+                                             ((FLG)  == SDIO_FLG_TXBUF)      || \
+                                             ((FLG)  == SDIO_FLG_RXBUF)      || \
+                                             ((FLG)  == SDIO_FLG_SDIOIF)     || \
+                                             ((FLG)  == SDIO_FLG_ATACMPL))
+
+#define IS_SDIO_CLEAR_FLG(FLG)              ((((FLG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLG) != (uint32_t)0x00))
+
+#define IS_SDIO_GET_INT(INT)                (((INT)  == SDIO_INT_CMDFAIL)    || \
+                                             ((INT)  == SDIO_INT_DTFAIL)     || \
+                                             ((INT)  == SDIO_INT_CMDTIMEOUT) || \
+                                             ((INT)  == SDIO_INT_DTTIMEOUT)  || \
+                                             ((INT)  == SDIO_INT_TXERRU)     || \
+                                             ((INT)  == SDIO_INT_RXERRO)     || \
+                                             ((INT)  == SDIO_INT_CMDRSPCMPL) || \
+                                             ((INT)  == SDIO_INT_CMDCMPL)    || \
+                                             ((INT)  == SDIO_INT_DTCMPL)     || \
+                                             ((INT)  == SDIO_INT_SBITERR)    || \
+                                             ((INT)  == SDIO_INT_DTBLKCMPL)  || \
+                                             ((INT)  == SDIO_INT_DOCMD)      || \
+                                             ((INT)  == SDIO_INT_DOTX)       || \
+                                             ((INT)  == SDIO_INT_DORX)       || \
+                                             ((INT)  == SDIO_INT_TXBUF_H)    || \
+                                             ((INT)  == SDIO_INT_RXBUF_H)    || \
+                                             ((INT)  == SDIO_INT_TXBUF_F)    || \
+                                             ((INT)  == SDIO_INT_RXBUF_F)    || \
+                                             ((INT)  == SDIO_INT_TXBUF_E)    || \
+                                             ((INT)  == SDIO_INT_RXBUF_E)    || \
+                                             ((INT)  == SDIO_INT_TXBUF)      || \
+                                             ((INT)  == SDIO_INT_RXBUF)      || \
+                                             ((INT)  == SDIO_INT_SDIOIF)     || \
+                                             ((INT)  == SDIO_INT_ATACMPL))
+
+#define IS_SDIO_CLEAR_INT(INT)              ((((INT) & (uint32_t)0xFF3FF800) == 0x00) && ((INT) != (uint32_t)0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Read_Wait_Mode
+  * @{
+  */
+
+#define SDIO_ReadWaitMode_CLK               ((uint32_t)0x00000001)
+#define SDIO_ReadWaitMode_DATA2             ((uint32_t)0x00000000)
+#define IS_SDIO_READWAIT_MODE(MODE)         (((MODE) == SDIO_ReadWaitMode_CLK) || \
+                                             ((MODE) == SDIO_ReadWaitMode_DATA2))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Functions
+  * @{
+  */
+
+void SDIO_Reset(SDIO_Type * SDIOx);
+void SDIO_Init(SDIO_Type * SDIOx, SDIO_InitType* SDIO_InitStruct);
+void SDIO_StructInit(SDIO_InitType* SDIO_InitStruct);
+void SDIO_ClockCmd(SDIO_Type * SDIOx, FunctionalState NewState);
+void SDIO_SetPowerSaveState(SDIO_Type * SDIOx, uint32_t SDIO_PowerState);
+uint32_t SDIO_GetPowerSaveState(SDIO_Type * SDIOx);
+void SDIO_INTConfig(SDIO_Type * SDIOx, uint32_t SDIO_INT, FunctionalState NewState);
+void SDIO_DMACmd(SDIO_Type * SDIOx, FunctionalState NewState);
+void SDIO_SendCommand(SDIO_Type * SDIOx, SDIO_CmdInitType *SDIO_CmdInitStruct);
+void SDIO_CmdStructInit(SDIO_CmdInitType* SDIO_CmdInitStruct);
+uint8_t SDIO_GetCommandResponse(SDIO_Type * SDIOx);
+uint32_t SDIO_GetResponse(SDIO_Type * SDIOx, uint32_t SDIO_RESP);
+void SDIO_DataConfig(SDIO_Type * SDIOx, SDIO_DataInitType* SDIO_DataInitStruct);
+void SDIO_DataStructInit(SDIO_DataInitType* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCounter(SDIO_Type * SDIOx);
+uint32_t SDIO_ReadData(SDIO_Type * SDIOx);
+void SDIO_WriteData(SDIO_Type * SDIOx, uint32_t Data);
+uint32_t SDIO_GetBUFCount(SDIO_Type * SDIOx);
+void SDIO_StartSDIOReadWait(SDIO_Type * SDIOx, FunctionalState NewState);
+void SDIO_StopSDIOReadWait(SDIO_Type * SDIOx, FunctionalState NewState);
+void SDIO_SetSDIOReadWaitMode(SDIO_Type * SDIOx, uint32_t SDIO_ReadWaitMode);
+void SDIO_SetSDIOOperation(SDIO_Type * SDIOx, FunctionalState NewState);
+void SDIO_SendSDIOSuspendCmd(SDIO_Type * SDIOx, FunctionalState NewState);
+void SDIO_CommandCompletionCmd(SDIO_Type * SDIOx, FunctionalState NewState);
+void SDIO_ATAINTCmd(SDIO_Type * SDIOx, FunctionalState NewState);
+void SDIO_SendATACmd(SDIO_Type * SDIOx, FunctionalState NewState);
+FlagStatus SDIO_GetFlagStatus(SDIO_Type * SDIOx, uint32_t SDIO_FLAG);
+void SDIO_ClearFlag(SDIO_Type * SDIOx, uint32_t SDIO_FLAG);
+ITStatus SDIO_GetINTStatus(SDIO_Type * SDIOx, uint32_t SDIO_INT);
+void SDIO_ClearINTPendingBit(SDIO_Type * SDIOx, uint32_t SDIO_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_SDIO_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_spi.h

@@ -0,0 +1,513 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_spi.h
+ * Description  : at32f4xx SPI header file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_SPI_H
+#define __AT32F4xx_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */
+
+/** @defgroup SPI_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  SPI Init structure definition
+  */
+
+typedef struct
+{
+    uint16_t SPI_TransMode;                 /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                               This parameter can be a value of @ref SPI_data_direction */
+                                            
+    uint16_t SPI_Mode;                      /*!< Specifies the SPI operating mode.
+                                               This parameter can be a value of @ref SPI_mode */
+                                            
+    uint16_t SPI_FrameSize;                 /*!< Specifies the SPI data size.
+                                               This parameter can be a value of @ref SPI_data_size */
+                                            
+    uint16_t SPI_CPOL;                      /*!< Specifies the serial clock steady state.
+                                               This parameter can be a value of @ref SPI_Clock_Polarity */
+                                            
+    uint16_t SPI_CPHA;                      /*!< Specifies the clock active edge for the bit capture.
+                                               This parameter can be a value of @ref SPI_Clock_Phase */
+                                            
+    uint16_t SPI_NSSSEL;                    /*!< Specifies whether the NSSSEL signal is managed by
+                                               hardware (NSSSEL pin) or by software using the SSI bit.
+                                               This parameter can be a value of @ref SPI_Slave_Select_management */
+                                            
+    uint16_t SPI_MCLKP;                     /*!< Specifies the Baud Rate prescaler value which will be
+                                                used to configure the transmit and receive SCK clock.
+                                                This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+                                                @note The communication clock is derived from the master
+                                                      clock. The slave clock does not need to be set. */
+                                            
+    uint16_t SPI_FirstBit;                  /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                                This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+                                    
+    uint16_t SPI_CPOLY;                     /*!<  Specifies the polynomial used for the CRC calculation. */
+} SPI_InitType;                     
+                                    
+/**                                 
+  * @brief  I2S Init structure defi nition
+  */                                
+                                    
+typedef struct                      
+{                                   
+                                    
+    uint16_t I2S_Mode;                      /*!<  Specifies the I2S operating mode.
+                                               This parameter can be a value of @ref I2S_Mode */
+                                    
+    uint16_t I2s_AudioProtocol;             /*!< Specifies the standard used for the I2S communication.
+                                                This parameter can be a value of @ref I2s_AudioProtocol */
+                                    
+    uint16_t I2S_FrameFormat;               /*! < Specifies the data format for the I2S communication.
+                                              This parameter can be a value of @ref I2S_Data_Format */
+
+    uint16_t I2S_MCLKOE;                    /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                                   This parameter can be a value of @ref I2S_MCLK_Output */
+
+    uint32_t I2S_AudioFreq;                 /*!< Specifies the frequency selected for the I2S communication.
+                                               This parameter can be a value of @ref I2S_Audio_Frequency */
+                                            
+    uint16_t I2S_CPOL;                      /*!< Specifies the idle state of the I2S clock.
+                                               This parameter can be a value of @ref I2S_Clock_Polarity */
+} I2S_InitType;
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Constants
+  * @{
+  */
+
+#if defined (AT32F413xx) || defined (AT32F415xx)
+#define IS_SPI_ALL_PERIPH(PERIPH)           (((PERIPH) == SPI1) || \
+                                             ((PERIPH) == SPI2))
+#elif defined (AT32F403xx)
+#define IS_SPI_ALL_PERIPH(PERIPH)           (((PERIPH) == SPI1) || \
+                                             ((PERIPH) == SPI2) || \
+                                             ((PERIPH) == SPI3) || \
+                                             ((PERIPH) == SPI4))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_SPI_ALL_PERIPH(PERIPH)           (((PERIPH) == SPI1)    || \
+                                             ((PERIPH) == SPI2)    || \
+                                             ((PERIPH) == SPI3)    || \
+                                             ((PERIPH) == SPI4)    || \
+                                             ((PERIPH) == I2S2EXT) || \
+                                             ((PERIPH) == I2S3EXT))
+#endif
+
+#if defined (AT32F413xx) || defined (AT32F415xx)
+#define IS_SPI_I2S_PERIPH(PERIPH)           (((PERIPH) == SPI1) || \
+                                             ((PERIPH) == SPI2))
+#elif defined (AT32F403xx)
+#define IS_SPI_I2S_PERIPH(PERIPH)           (((PERIPH) == SPI1) || \
+                                             ((PERIPH) == SPI2) || \
+                                             ((PERIPH) == SPI3) || \
+                                             ((PERIPH) == SPI4))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_SPI_I2S_PERIPH(PERIPH)           (((PERIPH) == SPI1)    || \
+                                             ((PERIPH) == SPI2)    || \
+                                             ((PERIPH) == SPI3)    || \
+                                             ((PERIPH) == SPI4)    || \
+                                             ((PERIPH) == I2S2EXT) || \
+                                             ((PERIPH) == I2S3EXT))
+#endif
+
+/** @defgroup SPI_data_direction
+  * @{
+  */
+
+#define SPI_TRANSMODE_FULLDUPLEX            ((uint16_t)0x0000)
+#define SPI_TRANSMODE_RXONLY                ((uint16_t)0x0400)
+#define SPI_TRANSMODE_RX_HALFDUPLEX         ((uint16_t)0x8000)
+#define SPI_TRANSMODE_TX_HALFDUPLEX         ((uint16_t)0xC000)
+#define IS_SPI_TRANS_MODE(MODE)             (((MODE) == SPI_TRANSMODE_FULLDUPLEX) || \
+                                             ((MODE) == SPI_TRANSMODE_RXONLY) || \
+                                             ((MODE) == SPI_TRANSMODE_RX_HALFDUPLEX) || \
+                                             ((MODE) == SPI_TRANSMODE_TX_HALFDUPLEX))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_mode
+  * @{
+  */
+
+#define SPI_MODE_MASTER                     ((uint16_t)0x0104)
+#define SPI_MODE_SLAVE                      ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE)                   (((MODE) == SPI_MODE_MASTER) || \
+                                             ((MODE) == SPI_MODE_SLAVE))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_data_size
+  * @{
+  */
+
+#define SPI_FRAMESIZE_16BIT                 ((uint16_t)0x0800)
+#define SPI_FRAMESIZE_8BIT                  ((uint16_t)0x0000)
+#define IS_SPI_FRAMESIZE(FRAMESIZE)         (((FRAMESIZE) == SPI_FRAMESIZE_16BIT) || \
+                                             ((FRAMESIZE) == SPI_FRAMESIZE_8BIT))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Polarity
+  * @{
+  */
+
+#define SPI_CPOL_LOW                        ((uint16_t)0x0000)
+#define SPI_CPOL_HIGH                       ((uint16_t)0x0002)
+#define IS_SPI_CPOL(CPOL)                   (((CPOL) == SPI_CPOL_LOW) || \
+                                             ((CPOL) == SPI_CPOL_HIGH))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase
+  * @{
+  */
+
+#define SPI_CPHA_1EDGE                      ((uint16_t)0x0000)
+#define SPI_CPHA_2EDGE                      ((uint16_t)0x0001)
+#define IS_SPI_CPHA(CPHA)                   (((CPHA) == SPI_CPHA_1EDGE) || \
+                                             ((CPHA) == SPI_CPHA_2EDGE))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_management
+  * @{
+  */
+
+#define SPI_NSSSEL_SOFT                     ((uint16_t)0x0200)
+#define SPI_NSSSEL_HARD                     ((uint16_t)0x0000)
+#define IS_SPI_NSSSEL(NSSSEL)               (((NSSSEL) == SPI_NSSSEL_SOFT) || \
+                                             ((NSSSEL) == SPI_NSSSEL_HARD))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_BaudRate_Prescaler
+  * @{
+  */
+
+
+#define SPI_MCLKP_OVER_256                  ((uint16_t)0x8000)
+                                            
+#define SPI_MCLKP_2                         ((uint16_t)0x0000)
+#define SPI_MCLKP_4                         ((uint16_t)0x0008)
+#define SPI_MCLKP_8                         ((uint16_t)0x0010)
+#define SPI_MCLKP_16                        ((uint16_t)0x0018)
+#define SPI_MCLKP_32                        ((uint16_t)0x0020)
+#define SPI_MCLKP_64                        ((uint16_t)0x0028)
+#define SPI_MCLKP_128                       ((uint16_t)0x0030)
+#define SPI_MCLKP_256                       ((uint16_t)0x0038)
+#define SPI_MCLKP_512                       ((uint16_t)0x8000)
+#define SPI_MCLKP_1024                      ((uint16_t)0x8008)
+#define IS_SPI_MCLKP(MCLKP)                 (((MCLKP) == SPI_MCLKP_2) || \
+                                             ((MCLKP) == SPI_MCLKP_4) || \
+                                             ((MCLKP) == SPI_MCLKP_8) || \
+                                             ((MCLKP) == SPI_MCLKP_16) || \
+                                             ((MCLKP) == SPI_MCLKP_32) || \
+                                             ((MCLKP) == SPI_MCLKP_64) || \
+                                             ((MCLKP) == SPI_MCLKP_128) || \
+                                             ((MCLKP) == SPI_MCLKP_256) || \
+                                             ((MCLKP) == SPI_MCLKP_512) || \
+                                             ((MCLKP) == SPI_MCLKP_1024))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_MSB_LSB_transmission
+  * @{
+  */
+
+#define SPI_FIRSTBIT_MSB                    ((uint16_t)0x0000)
+#define SPI_FIRSTBIT_LSB                    ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT)               (((BIT) == SPI_FIRSTBIT_MSB) || \
+                                             ((BIT) == SPI_FIRSTBIT_LSB))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Mode
+  * @{
+  */
+
+#define I2S_MODE_SLAVETX                    ((uint16_t)0x0000)
+#define I2S_MODE_SLAVERX                    ((uint16_t)0x0100)
+#define I2S_MODE_MASTERTX                   ((uint16_t)0x0200)
+#define I2S_MODE_MASTERRX                   ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE)                   (((MODE) == I2S_MODE_SLAVETX) || \
+                                             ((MODE) == I2S_MODE_SLAVERX) || \
+                                             ((MODE) == I2S_MODE_MASTERTX) || \
+                                             ((MODE) == I2S_MODE_MASTERRX) )
+/**
+  * @}
+  */
+
+/** @defgroup I2S_AUDIOPROTOCOL
+  * @{
+  */
+
+#define I2S_AUDIOPROTOCOL_PHILLIPS                  ((uint16_t)0x0000)
+#define I2S_AUDIOPROTOCOL_MSB                       ((uint16_t)0x0010)
+#define I2S_AUDIOPROTOCOL_LSB                       ((uint16_t)0x0020)
+#define I2S_AUDIOPROTOCOL_PCMSHORT                  ((uint16_t)0x0030)
+#define I2S_AUDIOPROTOCOL_PCMLONG                   ((uint16_t)0x00B0)
+#define IS_I2S_AUDIOPROTOCOL(AUDIOPROTOCOL)         (((AUDIOPROTOCOL) == I2S_AUDIOPROTOCOL_PHILLIPS) || \
+                                                     ((AUDIOPROTOCOL) == I2S_AUDIOPROTOCOL_MSB) || \
+                                                     ((AUDIOPROTOCOL) == I2S_AUDIOPROTOCOL_LSB) || \
+                                                     ((AUDIOPROTOCOL) == I2S_AUDIOPROTOCOL_PCMSHORT) || \
+                                                     ((AUDIOPROTOCOL) == I2S_AUDIOPROTOCOL_PCMLONG))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Data_Format
+  * @{
+  */
+
+#define I2S_FRAMEFORMAT_DL16BIT_CHL16BIT    ((uint16_t)0x0000)
+#define I2S_FRAMEFORMAT_DL16BIT_CHL32BIT    ((uint16_t)0x0001)
+#define I2S_FRAMEFORMAT_DL24BIT_CHL32BIT    ((uint16_t)0x0003)
+#define I2S_FRAMEFORMAT_DL32BIT_CHL32BIT    ((uint16_t)0x0005)
+#define IS_I2S_FRAMEFORMAT(FRAMEFORMAT)     (((FRAMEFORMAT) == I2S_FRAMEFORMAT_DL16BIT_CHL16BIT) || \
+                                             ((FRAMEFORMAT) == I2S_FRAMEFORMAT_DL16BIT_CHL32BIT) || \
+                                             ((FRAMEFORMAT) == I2S_FRAMEFORMAT_DL24BIT_CHL32BIT) || \
+                                             ((FRAMEFORMAT) == I2S_FRAMEFORMAT_DL32BIT_CHL32BIT))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_MCLK_Output
+  * @{
+  */
+
+#define I2S_MCLKOE_ENABLE                   ((uint16_t)0x0200)
+#define I2S_MCLKOE_DISABLE                  ((uint16_t)0x0000)
+#define IS_I2S_MCLKOE(MCLKOE)               (((MCLKOE) == I2S_MCLKOE_ENABLE) || \
+                                             ((MCLKOE) == I2S_MCLKOE_DISABLE))
+/**
+  * @}
+  */
+  
+#define I2S_DIV_VALUE_MAX                   ((uint16_t)0x03FF)
+#define I2S_DIV_EXT_VALUE_MASK              ((uint16_t)0x0300)
+#define I2S_DIV_EXT_VALUE_LSHIFT_OFFSET     ((uint16_t)2)
+
+/** @defgroup I2S_Audio_Frequency
+  * @{
+  */
+
+#define I2S_AUDIOFREQ_192K                  ((uint32_t)192000)
+#define I2S_AUDIOFREQ_96K                   ((uint32_t)96000)
+#define I2S_AUDIOFREQ_48K                   ((uint32_t)48000)
+#define I2S_AUDIOFREQ_44K                   ((uint32_t)44100)
+#define I2S_AUDIOFREQ_32K                   ((uint32_t)32000)
+#define I2S_AUDIOFREQ_22K                   ((uint32_t)22050)
+#define I2S_AUDIOFREQ_16K                   ((uint32_t)16000)
+#define I2S_AUDIOFREQ_11K                   ((uint32_t)11025)
+#define I2S_AUDIOFREQ_8K                    ((uint32_t)8000)
+#define I2S_AUDIOFREQ_DEFAULT               ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ)             ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
+                                             ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
+                                             ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Clock_Polarity
+  * @{
+  */
+
+#define I2S_CPOL_LOW                        ((uint16_t)0x0000)
+#define I2S_CPOL_HIGH                       ((uint16_t)0x0008)
+#define IS_I2S_CPOL(CPOL)                   (((CPOL) == I2S_CPOL_LOW) || \
+                                             ((CPOL) == I2S_CPOL_HIGH))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests
+  * @{
+  */
+
+#define SPI_I2S_DMA_TX                      ((uint16_t)0x0002)
+#define SPI_I2S_DMA_RX                      ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMA(DMA)                 ((((DMA) & (uint16_t)0xFFFC) == 0x00) && ((DMA) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_NSS_internal_software_management
+  * @{
+  */
+
+#define SPI_ISS_SET                         ((uint16_t)0x0100)
+#define SPI_ISS_RESET                       ((uint16_t)0xFEFF)
+#define IS_SPI_ISS(ISS)                     (((ISS) == SPI_ISS_SET) || \
+                                             ((ISS) == SPI_ISS_RESET))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Transmit_Receive
+  * @{
+  */
+
+#define SPI_CRC_TX                          ((uint8_t)0x00)
+#define SPI_CRC_RX                          ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC)                     (((CRC) == SPI_CRC_TX) || ((CRC) == SPI_CRC_RX))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_direction_transmit_receive
+  * @{
+  */
+
+#define SPI_HALFDUPLEX_RX                   ((uint16_t)0xBFFF)
+#define SPI_HALFDUPLEX_TX                   ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION)         (((DIRECTION) == SPI_HALFDUPLEX_RX) || \
+                                             ((DIRECTION) == SPI_HALFDUPLEX_TX))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_interrupts_definition
+  * @{
+  */
+
+#define SPI_I2S_INT_TE                      ((uint8_t)0x71)
+#define SPI_I2S_INT_RNE                     ((uint8_t)0x60)
+#define SPI_I2S_INT_ERR                     ((uint8_t)0x50)
+#define IS_SPI_I2S_CONFIG_INT(INT)          (((INT) == SPI_I2S_INT_TE) || \
+                                             ((INT) == SPI_I2S_INT_RNE) || \
+                                             ((INT) == SPI_I2S_INT_ERR))
+#define SPI_I2S_INT_OVR                     ((uint8_t)0x56)
+#define SPI_INT_MODF                        ((uint8_t)0x55)
+#define SPI_INT_CERR                        ((uint8_t)0x54)
+#define I2S_INT_UDR                         ((uint8_t)0x53)
+#define IS_SPI_I2S_CLEAR_INT(INT)           (((INT) == SPI_INT_CERR))
+#define IS_SPI_I2S_GET_INT(INT)             (((INT) == SPI_I2S_INT_RNE) || ((INT) == SPI_I2S_INT_TE) || \
+                                             ((INT) == I2S_INT_UDR)     || ((INT) == SPI_INT_CERR) || \
+                                             ((INT) == SPI_INT_MODF)    || ((INT) == SPI_I2S_INT_OVR))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_flags_definition
+  * @{
+  */
+
+#define SPI_I2S_FLAG_RNE                    ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TE                     ((uint16_t)0x0002)
+#define I2S_FLAG_CS                         ((uint16_t)0x0004)
+#define I2S_FLAG_UDR                        ((uint16_t)0x0008)
+#define SPI_FLAG_CERR                       ((uint16_t)0x0010)
+#define SPI_FLAG_MODF                       ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR                    ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BUSY                   ((uint16_t)0x0080)
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG)         (((FLAG) == SPI_FLAG_CERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG)           (((FLAG) == SPI_I2S_FLAG_BUSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+                                             ((FLAG) == SPI_FLAG_MODF)     || ((FLAG) == SPI_FLAG_CERR) || \
+                                             ((FLAG) == I2S_FLAG_UDR)      || ((FLAG) == I2S_FLAG_CS) || \
+                                             ((FLAG) == SPI_I2S_FLAG_TE)   || ((FLAG) == SPI_I2S_FLAG_RNE))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_polynomial
+  * @{
+  */
+
+#define IS_SPI_CPOLY(CPOLY)                 ((CPOLY) >= 0x1)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Functions
+  * @{
+  */
+
+void SPI_I2S_Reset(SPI_Type* SPIx);
+void SPI_Init(SPI_Type* SPIx, SPI_InitType* SPI_InitStruct);
+void I2S_Init(SPI_Type* SPIx, I2S_InitType* I2S_InitStruct);
+void SPI_DefaultInitParaConfig(SPI_InitType* SPI_InitStruct);
+void I2S_DefaultInit(I2S_InitType* I2S_InitStruct);
+void SPI_Enable(SPI_Type* SPIx, FunctionalState NewState);
+void I2S_Enable(SPI_Type* SPIx, FunctionalState NewState);
+void SPI_I2S_INTConfig(SPI_Type* SPIx, uint8_t SPI_I2S_INT, FunctionalState NewState);
+void SPI_I2S_DMAEnable(SPI_Type* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_I2S_TxData(SPI_Type* SPIx, uint16_t Data);
+uint16_t SPI_I2S_RxData(SPI_Type* SPIx);
+void SPI_NSSInternalSoftwareConfig(SPI_Type* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_NSSHardwareOutputEnable(SPI_Type* SPIx, FunctionalState NewState);
+void SPI_FrameSizeConfig(SPI_Type* SPIx, uint16_t SPI_DataSize);
+void SPI_TxCRC(SPI_Type* SPIx);
+void SPI_CRCEN(SPI_Type* SPIx, FunctionalState NewState);
+uint16_t SPI_GetCRC(SPI_Type* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_Type* SPIx);
+void SPI_HalfDuplexTransModeConfig(SPI_Type* SPIx, uint16_t SPI_Direction);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_Type* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_Type* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_Type* SPIx, uint8_t SPI_I2S_INT);
+void SPI_I2S_ClearINTPendingBit(SPI_Type* SPIx, uint8_t SPI_I2S_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4xx_SPI_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_tim.h

@@ -0,0 +1,1402 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_tim.h
+ * Description  : at32f4xx TIMER header file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_TIM_H
+#define __AT32F4xx_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup TMR
+  * @{
+  */ 
+
+/** @defgroup TMR_Exported_Types
+  * @{
+  */ 
+
+/** 
+  * @brief  TMR Time Base Init structure definition
+  * @note   This structure is used with all TMRx except for TMR6 and TMR7.    
+  */
+
+typedef struct
+{
+  uint16_t TMR_DIV;         			/*!< Specifies the prescaler value used to divide the TMR clock.
+                                       This parameter can be a number between 0x0000 and 0xFFFF */
+
+  uint32_t TMR_CounterMode;       /*!< Specifies the counter mode.
+                                       This parameter can be a value of @ref TMR_Counter_Mode */
+
+  uint32_t TMR_Period;            /*!< Specifies the period value to be loaded into the active
+                                       Auto-Reload Register at the next update event. 
+																			 This parameter must be a number between 0x0000 and 0xFFFF. */ 
+
+  uint16_t TMR_ClockDivision;     /*!< Specifies the clock division.
+                                      This parameter can be a value of @ref TMR_Clock_Division_CKD */
+
+  uint8_t TMR_RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                       reaches zero, an update event is generated and counting restarts
+                                       from the RCR value (N).
+                                       This means in PWM mode that (N+1) corresponds to:
+                                          - the number of PWM periods in edge-aligned mode
+                                          - the number of half PWM period in center-aligned mode
+                                       This parameter must be a number between 0x00 and 0xFF. 
+                                       @note This parameter is valid only for TMR1 and TMR8. */
+} TMR_TimerBaseInitType;       
+
+/** 
+  * @brief  TMR Output Compare Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t TMR_OCMode;        /*!< Specifies the TMR mode.
+                                   This parameter can be a value of @ref TMR_Output_Compare_and_PWM_modes */
+
+  uint16_t TMR_OutputState;   /*!< Specifies the TMR Output Compare state.
+                                   This parameter can be a value of @ref TMR_Output_Compare_state */
+
+  uint16_t TMR_OutputNState;  /*!< Specifies the TMR complementary Output Compare state.
+                                   This parameter can be a value of @ref TMR_Output_Compare_N_state
+                                   @note This parameter is valid only for TMR1 and TMR8. */
+
+  uint32_t TMR_Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
+                                   This parameter can be a number between 0x0000 and 0xFFFF */
+ 
+
+  uint16_t TMR_OCPolarity;    /*!< Specifies the output polarity.
+                                   This parameter can be a value of @ref TMR_Output_Compare_Polarity */
+
+  uint16_t TMR_OCNPolarity;   /*!< Specifies the complementary output polarity.
+                                   This parameter can be a value of @ref TMR_Output_Compare_N_Polarity
+                                   @note This parameter is valid only for TMR1 and TMR8. */
+
+  uint16_t TMR_OCIdleState;   /*!< Specifies the TMR Output Compare pin state during Idle state.
+                                   This parameter can be a value of @ref TMR_Output_Compare_Idle_State
+                                   @note This parameter is valid only for TMR1 and TMR8. */
+
+  uint16_t TMR_OCNIdleState;  /*!< Specifies the TMR Output Compare pin state during Idle state.
+                                   This parameter can be a value of @ref TMR_Output_Compare_N_Idle_State
+                                   @note This parameter is valid only for TMR1 and TMR8. */
+} TMR_OCInitType;
+
+/** 
+  * @brief  TMR Input Capture Init structure definition  
+  */
+
+typedef struct
+{
+
+  uint16_t TMR_Channel;       /*!< Specifies the TMR channel.
+                                  This parameter can be a value of @ref TMR_Channel */
+
+  uint16_t TMR_ICPolarity;    /*!< Specifies the active edge of the input signal.
+                                  This parameter can be a value of @ref TMR_Input_Capture_Polarity */
+
+  uint16_t TMR_ICSelection;   /*!< Specifies the input.
+                                  This parameter can be a value of @ref TMR_Input_Capture_Selection */
+
+  uint16_t TMR_ICDIV;         /*!< Specifies the Input Capture Prescaler.
+                                  This parameter can be a value of @ref TMR_Input_Capture_Prescaler */
+
+  uint16_t TMR_ICFilter;      /*!< Specifies the input capture filter.
+                                  This parameter can be a number between 0x0 and 0xF */
+} TMR_ICInitType;
+
+/** 
+  * @brief  BDTR structure definition 
+  * @note   This structure is used only with TMR1 and TMR8.    
+  */
+
+typedef struct
+{
+
+  uint16_t TMR_OSIMRState;        /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
+
+  uint16_t TMR_OSIMIState;        /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
+
+  uint16_t TMR_LOCKgrade;         /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref Lock_level */ 
+
+  uint16_t TMR_DeadTime;          /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between 0x00 and 0xFF  */
+
+  uint16_t TMR_Break;             /*!< Specifies whether the TMR Break input is enabled or not. 
+                                      This parameter can be a value of @ref Break_Input_enable_disable */
+
+  uint16_t TMR_BreakPolarity;     /*!< Specifies the TMR Break Input pin polarity.
+                                      This parameter can be a value of @ref Break_Polarity */
+
+  uint16_t TMR_AutomaticOutput;   /*!< Specifies whether the TMR Automatic Output feature is enabled or not. 
+                                      This parameter can be a value of @ref TMR_AOE_Bit_Set_Reset */
+} TMR_BRKDTInitType;
+
+/** @defgroup TMR_Exported_constants 
+  * @{
+  */
+
+#if defined (AT32F403xx)
+#define IS_TMR_ALL_PERIPH(PERIPH)    (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR6) || \
+                                      ((PERIPH) == TMR7) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR9) || \
+                                      ((PERIPH) == TMR10)|| \
+                                      ((PERIPH) == TMR11)|| \
+                                      ((PERIPH) == TMR12)|| \
+                                      ((PERIPH) == TMR13)|| \
+                                      ((PERIPH) == TMR14)|| \
+                                      ((PERIPH) == TMR15))
+#elif defined (AT32F413xx)
+#define IS_TMR_ALL_PERIPH(PERIPH)    (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR9) || \
+                                      ((PERIPH) == TMR10)|| \
+                                      ((PERIPH) == TMR11))
+#elif defined (AT32F415xx)
+#define IS_TMR_ALL_PERIPH(PERIPH)    (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR9) || \
+                                      ((PERIPH) == TMR10)|| \
+                                      ((PERIPH) == TMR11))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_TMR_ALL_PERIPH(PERIPH)    (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR6) || \
+                                      ((PERIPH) == TMR7) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR9) || \
+                                      ((PERIPH) == TMR10)|| \
+                                      ((PERIPH) == TMR11)|| \
+                                      ((PERIPH) == TMR12)|| \
+                                      ((PERIPH) == TMR13)|| \
+                                      ((PERIPH) == TMR14))
+#endif
+
+
+
+/* LIST1: TMR 1, 8 and 15 */
+#if defined (AT32F403xx)
+#define IS_TMR_LIST1_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR15))
+#elif defined (AT32F413xx)
+#define IS_TMR_LIST1_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR8))
+#elif defined (AT32F415xx)
+#define IS_TMR_LIST1_PERIPH(PERIPH)  (((PERIPH) == TMR1))
+
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_TMR_LIST1_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR8))
+#endif
+
+/* LIST2: TMR 1, 8, 15 */
+#if defined (AT32F403xx)
+#define IS_TMR_LIST2_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR15))
+#elif defined (AT32F413xx)
+#define IS_TMR_LIST2_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR8))
+#elif defined (AT32F415xx)
+#define IS_TMR_LIST2_PERIPH(PERIPH)  (((PERIPH) == TMR1))
+
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_TMR_LIST2_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR8))
+#endif
+
+
+/* LIST3: TMR 1, 2, 3, 4, 5 ,8 and 15 */
+#if defined (AT32F403xx)
+#define IS_TMR_LIST3_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR15)) 
+#elif defined (AT32F413xx)
+#define IS_TMR_LIST3_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8)) 
+#elif defined (AT32F415xx)
+#define IS_TMR_LIST3_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_TMR_LIST3_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8))
+#endif
+									                                 
+/* LIST4: TMR 1, 2, 3, 4, 5, 8, 15 */
+#if defined (AT32F403xx)
+#define IS_TMR_LIST4_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR15))
+#elif defined (AT32F413xx)
+#define IS_TMR_LIST4_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8))
+#elif defined (AT32F415xx)
+#define IS_TMR_LIST4_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_TMR_LIST4_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8))
+#endif
+
+/* LIST5: TMR 1, 2, 3, 4, 5, 8 and 15 */ 
+
+#if defined (AT32F403xx)
+#define IS_TMR_LIST5_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR15))
+#elif defined (AT32F413xx)
+#define IS_TMR_LIST5_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8))
+#elif defined (AT32F415xx)
+#define IS_TMR_LIST5_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_TMR_LIST5_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8))
+#endif
+
+/* LIST6: TMR 1, 2, 3, 4, 5, 8, 9, 12 and 15 */
+#if defined (AT32F403xx)
+#define IS_TMR_LIST6_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR9) || \
+                                      ((PERIPH) == TMR12)|| \
+                                      ((PERIPH) == TMR15))
+#elif defined (AT32F413xx)
+#define IS_TMR_LIST6_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR9))
+#elif defined (AT32F415xx)
+#define IS_TMR_LIST6_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR9))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_TMR_LIST6_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR9) || \
+                                      ((PERIPH) == TMR12))
+#endif
+
+/* LIST7: TMR 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */
+#if defined (AT32F403xx)
+#define IS_TMR_LIST7_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR6) || \
+                                      ((PERIPH) == TMR7) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR9) || \
+                                      ((PERIPH) == TMR12)|| \
+                                      ((PERIPH) == TMR15))
+#elif defined (AT32F413xx)
+#define IS_TMR_LIST7_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR9))
+#elif defined (AT32F415xx)
+#define IS_TMR_LIST7_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR9))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_TMR_LIST7_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR6) || \
+                                      ((PERIPH) == TMR7) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR9) || \
+                                      ((PERIPH) == TMR12))
+#endif
+
+/* LIST8: TMR 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15 */  
+#if defined (AT32F403xx)
+#define IS_TMR_LIST8_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR9) || \
+                                      ((PERIPH) == TMR10)|| \
+                                      ((PERIPH) == TMR11)|| \
+                                      ((PERIPH) == TMR12)|| \
+                                      ((PERIPH) == TMR13)|| \
+                                      ((PERIPH) == TMR14)|| \
+                                      ((PERIPH) == TMR15))
+#elif defined (AT32F413xx)
+#define IS_TMR_LIST8_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR9) || \
+                                      ((PERIPH) == TMR10)|| \
+                                      ((PERIPH) == TMR11))
+#elif defined (AT32F415xx)
+#define IS_TMR_LIST8_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR9) || \
+                                      ((PERIPH) == TMR10)|| \
+                                      ((PERIPH) == TMR11))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_TMR_LIST8_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR9) || \
+                                      ((PERIPH) == TMR10)|| \
+                                      ((PERIPH) == TMR11)|| \
+                                      ((PERIPH) == TMR12)|| \
+                                      ((PERIPH) == TMR13)|| \
+                                      ((PERIPH) == TMR14))
+#endif
+
+/* LIST9: TMR 1, 2, 3, 4, 5, 6, 7, 8, 15 */
+#if defined (AT32F403xx)
+#define IS_TMR_LIST9_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR6) || \
+                                      ((PERIPH) == TMR7) || \
+                                      ((PERIPH) == TMR8) || \
+                                      ((PERIPH) == TMR15))
+#elif defined (AT32F413xx)
+#define IS_TMR_LIST9_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR8))
+#elif defined (AT32F415xx)
+#define IS_TMR_LIST9_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5))
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+#define IS_TMR_LIST9_PERIPH(PERIPH)  (((PERIPH) == TMR1) || \
+                                      ((PERIPH) == TMR2) || \
+                                      ((PERIPH) == TMR3) || \
+                                      ((PERIPH) == TMR4) || \
+                                      ((PERIPH) == TMR5) || \
+                                      ((PERIPH) == TMR6) || \
+                                      ((PERIPH) == TMR7) || \
+                                      ((PERIPH) == TMR8))
+#endif
+
+/*LIST10:TIM 2, 5*/																	 
+#define IS_TMR_PLUSMODE_PERIPH(PERIPH) (((PERIPH)==TMR2) ||\
+																			 ((PERIPH)==TMR5))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Output_Compare_and_PWM_modes 
+  * @{
+  */
+
+#define TMR_OCMode_Timing                  ((uint16_t)0x0000)
+#define TMR_OCMode_Active                  ((uint16_t)0x0010)
+#define TMR_OCMode_Inactive                ((uint16_t)0x0020)
+#define TMR_OCMode_Toggle                  ((uint16_t)0x0030)
+#define TMR_OCMode_PWM1                    ((uint16_t)0x0060)
+#define TMR_OCMode_PWM2                    ((uint16_t)0x0070)
+#define IS_TMR_OC_MODE(MODE)               (((MODE) == TMR_OCMode_Timing) || \
+                                            ((MODE) == TMR_OCMode_Active) || \
+                                            ((MODE) == TMR_OCMode_Inactive) || \
+                                            ((MODE) == TMR_OCMode_Toggle)|| \
+                                            ((MODE) == TMR_OCMode_PWM1) || \
+                                            ((MODE) == TMR_OCMode_PWM2))
+#define IS_TMR_OCM(MODE)                   (((MODE) == TMR_OCMode_Timing) || \
+                                            ((MODE) == TMR_OCMode_Active) || \
+                                            ((MODE) == TMR_OCMode_Inactive) || \
+                                            ((MODE) == TMR_OCMode_Toggle)|| \
+                                            ((MODE) == TMR_OCMode_PWM1) || \
+                                            ((MODE) == TMR_OCMode_PWM2) ||	\
+                                            ((MODE) == TMR_ForcedAction_Active) || \
+                                            ((MODE) == TMR_ForcedAction_InActive))
+/**
+  * @}
+  */
+
+/** @defgroup TMR_One_Pulse_Mode 
+  * @{
+  */
+
+#define TMR_OPMode_Once                  ((uint16_t)0x0008)
+#define TMR_OPMode_Repetitive            ((uint16_t)0x0000)
+#define IS_TMR_OPM_MODE(MODE)            (((MODE) == TMR_OPMode_Once) || \
+                                          ((MODE) == TMR_OPMode_Repetitive))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Channel 
+  * @{
+  */
+
+#define TMR_Channel_1                      ((uint16_t)0x0000)
+#define TMR_Channel_2                      ((uint16_t)0x0004)
+#define TMR_Channel_3                      ((uint16_t)0x0008)
+#define TMR_Channel_4                      ((uint16_t)0x000C)
+#define IS_TMR_CHANNEL(CHANNEL)            (((CHANNEL) == TMR_Channel_1) || \
+                                            ((CHANNEL) == TMR_Channel_2) || \
+                                            ((CHANNEL) == TMR_Channel_3) || \
+                                            ((CHANNEL) == TMR_Channel_4))
+#define IS_TMR_PWMI_CHANNEL(CHANNEL)       (((CHANNEL) == TMR_Channel_1) || \
+                                            ((CHANNEL) == TMR_Channel_2))
+#define IS_TMR_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TMR_Channel_1) || \
+                                               ((CHANNEL) == TMR_Channel_2) || \
+                                               ((CHANNEL) == TMR_Channel_3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Clock_Division_CKD 
+  * @{
+  */
+
+#define TMR_CKD_DIV1                       ((uint16_t)0x0000)
+#define TMR_CKD_DIV2                       ((uint16_t)0x0100)
+#define TMR_CKD_DIV4                       ((uint16_t)0x0200)
+#define IS_TMR_CKD_DIV(DIV)                (((DIV) == TMR_CKD_DIV1) || \
+                                            ((DIV) == TMR_CKD_DIV2) || \
+                                            ((DIV) == TMR_CKD_DIV4))
+/**
+  * @}
+  */
+
+
+/** @defgroup TMR_Counter_Mode 
+  * @{
+  */
+
+#define TMR_CounterDIR_Up                 ((uint16_t)0x0000)
+#define TMR_CounterDIR_Down               ((uint16_t)0x0010)
+#define TMR_CounterDIR_CenterAligned1     ((uint16_t)0x0020)
+#define TMR_CounterDIR_CenterAligned2     ((uint16_t)0x0040)
+#define TMR_CounterDIR_CenterAligned3     ((uint16_t)0x0060)
+#define IS_TMR_COUNTER_DIR(DIR)           (((DIR) == TMR_CounterDIR_Up) ||  \
+                                           ((DIR) == TMR_CounterDIR_Down) || \
+                                           ((DIR) == TMR_CounterDIR_CenterAligned1) || \
+                                           ((DIR) == TMR_CounterDIR_CenterAligned2) || \
+                                           ((DIR) == TMR_CounterDIR_CenterAligned3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Output_Compare_Polarity 
+  * @{
+  */
+
+#define TMR_OCPolarity_High                ((uint16_t)0x0000)
+#define TMR_OCPolarity_Low                 ((uint16_t)0x0002)
+#define IS_TMR_OC_POLARITY(POLARITY)       (((POLARITY) == TMR_OCPolarity_High) || \
+                                            ((POLARITY) == TMR_OCPolarity_Low))
+/**
+  * @}
+  */
+
+/** @defgroup TMR_Output_Compare_N_Polarity 
+  * @{
+  */
+  
+#define TMR_OCNPolarity_High               ((uint16_t)0x0000)
+#define TMR_OCNPolarity_Low                ((uint16_t)0x0008)
+#define IS_TMR_OCN_POLARITY(POLARITY)      (((POLARITY) == TMR_OCNPolarity_High) || \
+                                            ((POLARITY) == TMR_OCNPolarity_Low))
+/**
+  * @}
+  */
+
+/** @defgroup TMR_Output_Compare_state 
+  * @{
+  */
+
+#define TMR_OutputState_Disable            ((uint16_t)0x0000)
+#define TMR_OutputState_Enable             ((uint16_t)0x0001)
+#define IS_TMR_OUTPUT_STATE(STATE)         (((STATE) == TMR_OutputState_Disable) || \
+                                            ((STATE) == TMR_OutputState_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Output_Compare_N_state 
+  * @{
+  */
+
+#define TMR_OutputNState_Disable           ((uint16_t)0x0000)
+#define TMR_OutputNState_Enable            ((uint16_t)0x0004)
+#define IS_TMR_OUTPUTN_STATE(STATE)        (((STATE) == TMR_OutputNState_Disable) || \
+                                            ((STATE) == TMR_OutputNState_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Capture_Compare_state 
+  * @{
+  */
+
+#define TMR_CCx_Enable                     ((uint16_t)0x0001)
+#define TMR_CCx_Disable                    ((uint16_t)0x0000)
+#define IS_TMR_CCX(CCX)                    (((CCX) == TMR_CCx_Enable) || \
+                                            ((CCX) == TMR_CCx_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Capture_Compare_N_state 
+  * @{
+  */
+
+#define TMR_CCxN_Enable                    ((uint16_t)0x0004)
+#define TMR_CCxN_Disable                   ((uint16_t)0x0000)
+#define IS_TMR_CCXN(CCXN)                  (((CCXN) == TMR_CCxN_Enable) || \
+                                            ((CCXN) == TMR_CCxN_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup Break_Input_enable_disable 
+  * @{
+  */
+
+#define TMR_Break_Enable                  ((uint16_t)0x1000)
+#define TMR_Break_Disable                 ((uint16_t)0x0000)
+#define IS_TMR_BREAK_STATE(STATE)         (((STATE) == TMR_Break_Enable) || \
+                                           ((STATE) == TMR_Break_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup Break_Polarity 
+  * @{
+  */
+
+#define TMR_BreakPolarity_Low             ((uint16_t)0x0000)
+#define TMR_BreakPolarity_High            ((uint16_t)0x2000)
+#define IS_TMR_BREAK_POLARITY(POLARITY)   (((POLARITY) == TMR_BreakPolarity_Low) || \
+                                           ((POLARITY) == TMR_BreakPolarity_High))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_AOE_Bit_Set_Reset 
+  * @{
+  */
+
+#define TMR_AutomaticOutput_Enable            ((uint16_t)0x4000)
+#define TMR_AutomaticOutput_Disable           ((uint16_t)0x0000)
+#define IS_TMR_AUTOMATIC_OUTPUT_STATE(STATE)  (((STATE) == TMR_AutomaticOutput_Enable) || \
+                                               ((STATE) == TMR_AutomaticOutput_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup Lock_level 
+  * @{
+  */
+
+#define TMR_LOCKgrade_OFF                  ((uint16_t)0x0000)
+#define TMR_LOCKgrade_1                    ((uint16_t)0x0100)
+#define TMR_LOCKgrade_2                    ((uint16_t)0x0200)
+#define TMR_LOCKgrade_3                    ((uint16_t)0x0300)
+#define IS_TMR_LOCK_grade(grade)           (((grade) == TMR_LOCKgrade_OFF) || \
+                                            ((grade) == TMR_LOCKgrade_1) || \
+                                            ((grade) == TMR_LOCKgrade_2) || \
+                                            ((grade) == TMR_LOCKgrade_3))
+/**
+  * @}
+  */ 
+
+/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state 
+  * @{
+  */
+
+#define TMR_OSIMIState_Enable              ((uint16_t)0x0400)
+#define TMR_OSIMIState_Disable             ((uint16_t)0x0000)
+#define IS_TMR_OSIMI_STATE(STATE)          (((STATE) == TMR_OSIMIState_Enable) || \
+                                            ((STATE) == TMR_OSIMIState_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state 
+  * @{
+  */
+
+#define TMR_OSIMRState_Enable              ((uint16_t)0x0800)
+#define TMR_OSIMRState_Disable             ((uint16_t)0x0000)
+#define IS_TMR_OSIMR_STATE(STATE)          (((STATE) == TMR_OSIMRState_Enable) || \
+                                            ((STATE) == TMR_OSIMRState_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Output_Compare_Idle_State 
+  * @{
+  */
+
+#define TMR_OCIdleState_Set                ((uint16_t)0x0100)
+#define TMR_OCIdleState_Reset              ((uint16_t)0x0000)
+#define IS_TMR_OCIDLE_STATE(STATE)         (((STATE) == TMR_OCIdleState_Set) || \
+                                            ((STATE) == TMR_OCIdleState_Reset))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Output_Compare_N_Idle_State 
+  * @{
+  */
+
+#define TMR_OCNIdleState_Set               ((uint16_t)0x0200)
+#define TMR_OCNIdleState_Reset             ((uint16_t)0x0000)
+#define IS_TMR_OCNIDLE_STATE(STATE)        (((STATE) == TMR_OCNIdleState_Set) || \
+                                            ((STATE) == TMR_OCNIdleState_Reset))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Input_Capture_Polarity 
+  * @{
+  */
+
+#define  TMR_ICPolarity_Rising             ((uint16_t)0x0000)
+#define  TMR_ICPolarity_Falling            ((uint16_t)0x0002)
+#define  TMR_ICPolarity_BothEdge           ((uint16_t)0x000A)
+#define IS_TMR_IC_POLARITY(POLARITY)       (((POLARITY) == TMR_ICPolarity_Rising) || \
+                                            ((POLARITY) == TMR_ICPolarity_Falling))
+#define IS_TMR_IC_POLARITY_LITE(POLARITY)  (((POLARITY) == TMR_ICPolarity_Rising) || \
+                                            ((POLARITY) == TMR_ICPolarity_Falling)|| \
+                                            ((POLARITY) == TMR_ICPolarity_BothEdge))                                      
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Input_Capture_Selection 
+  * @{
+  */
+
+#define TMR_ICSelection_DirectTI           ((uint16_t)0x0001) /*!< TMR Input 1, 2, 3 or 4 is selected to be 
+                                                                   connected to IC1, IC2, IC3 or IC4, respectively */
+#define TMR_ICSelection_IndirectTI         ((uint16_t)0x0002) /*!< TMR Input 1, 2, 3 or 4 is selected to be
+                                                                   connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TMR_ICSelection_TRC                ((uint16_t)0x0003) /*!< TMR Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IS_TMR_IC_SELECTION(SELECTION)     (((SELECTION) == TMR_ICSelection_DirectTI) || \
+                                            ((SELECTION) == TMR_ICSelection_IndirectTI) || \
+                                            ((SELECTION) == TMR_ICSelection_TRC))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Input_Capture_Prescaler 
+  * @{
+  */
+
+#define TMR_ICDIV_DIV1                     ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
+#define TMR_ICDIV_DIV2                     ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TMR_ICDIV_DIV4                     ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TMR_ICDIV_DIV8                     ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IS_TMR_IC_DIV(DIV)                 (((DIV) == TMR_ICDIV_DIV1) || \
+                                            ((DIV) == TMR_ICDIV_DIV2) || \
+                                            ((DIV) == TMR_ICDIV_DIV4) || \
+                                            ((DIV) == TMR_ICDIV_DIV8))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_interrupt_sources 
+  * @{
+  */
+
+#define TMR_INT_Overflow                    ((uint16_t)0x0001)
+#define TMR_INT_CC1                         ((uint16_t)0x0002)
+#define TMR_INT_CC2                         ((uint16_t)0x0004)
+#define TMR_INT_CC3                         ((uint16_t)0x0008)
+#define TMR_INT_CC4                         ((uint16_t)0x0010)
+#define TMR_INT_HALL                        ((uint16_t)0x0020)
+#define TMR_INT_Trigger                     ((uint16_t)0x0040)
+#define TMR_INT_Break                       ((uint16_t)0x0080)
+#define IS_TMR_INT(INT) ((((INT) & (uint16_t)0xFF00) == 0x0000) && ((INT) != 0x0000))
+
+#define IS_TMR_GET_INT(INT)                 (((INT) == TMR_INT_Overflow) || \
+                                             ((INT) == TMR_INT_CC1) || \
+                                             ((INT) == TMR_INT_CC2) || \
+                                             ((INT) == TMR_INT_CC3) || \
+                                             ((INT) == TMR_INT_CC4) || \
+                                             ((INT) == TMR_INT_HALL) || \
+                                             ((INT) == TMR_INT_Trigger) || \
+                                             ((INT) == TMR_INT_Break))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_DMA_Base_address 
+  * @{
+  */
+
+#define TMR_DMABase_CTRL1                   ((uint16_t)0x0000)
+#define TMR_DMABase_CTRL2                   ((uint16_t)0x0001)
+#define TMR_DMABase_SMC                     ((uint16_t)0x0002)
+#define TMR_DMABase_DIE                     ((uint16_t)0x0003)
+#define TMR_DMABase_STS                     ((uint16_t)0x0004)
+#define TMR_DMABase_EVEG                    ((uint16_t)0x0005)
+#define TMR_DMABase_CCM1                    ((uint16_t)0x0006)
+#define TMR_DMABase_CCM2                    ((uint16_t)0x0007)
+#define TMR_DMABase_CCE                     ((uint16_t)0x0008)
+#define TMR_DMABase_CNT                     ((uint16_t)0x0009)
+#define TMR_DMABase_DIV                     ((uint16_t)0x000A)
+#define TMR_DMABase_AR                      ((uint16_t)0x000B)
+#define TMR_DMABase_RC                      ((uint16_t)0x000C)
+#define TMR_DMABase_CC1                     ((uint16_t)0x000D)
+#define TMR_DMABase_CC2                     ((uint16_t)0x000E)
+#define TMR_DMABase_CC3                     ((uint16_t)0x000F)
+#define TMR_DMABase_CC4                     ((uint16_t)0x0010)
+#define TMR_DMABase_BRKDT                   ((uint16_t)0x0011)
+#define TMR_DMABase_DMAC                    ((uint16_t)0x0012)
+#define IS_TMR_DMA_BASE(BASE)               (((BASE) == TMR_DMABase_CTRL1) || \
+                                             ((BASE) == TMR_DMABase_CTRL2) || \
+                                             ((BASE) == TMR_DMABase_SMC) || \
+                                             ((BASE) == TMR_DMABase_DIE) || \
+                                             ((BASE) == TMR_DMABase_STS) || \
+                                             ((BASE) == TMR_DMABase_EVEG) || \
+                                             ((BASE) == TMR_DMABase_CCM1) || \
+                                             ((BASE) == TMR_DMABase_CCM2) || \
+                                             ((BASE) == TMR_DMABase_CCE) || \
+                                             ((BASE) == TMR_DMABase_CNT) || \
+                                             ((BASE) == TMR_DMABase_DIV) || \
+                                             ((BASE) == TMR_DMABase_AR) || \
+                                             ((BASE) == TMR_DMABase_RC) || \
+                                             ((BASE) == TMR_DMABase_CC1) || \
+                                             ((BASE) == TMR_DMABase_CC2) || \
+                                             ((BASE) == TMR_DMABase_CC3) || \
+                                             ((BASE) == TMR_DMABase_CC4) || \
+                                             ((BASE) == TMR_DMABase_BRKDT) || \
+                                             ((BASE) == TMR_DMABase_DMAC))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_DMA_Burst_Length 
+  * @{
+  */
+
+#define TMR_DMABurstLength_1Transfer           ((uint16_t)0x0000)
+#define TMR_DMABurstLength_2Transfers          ((uint16_t)0x0100)
+#define TMR_DMABurstLength_3Transfers          ((uint16_t)0x0200)
+#define TMR_DMABurstLength_4Transfers          ((uint16_t)0x0300)
+#define TMR_DMABurstLength_5Transfers          ((uint16_t)0x0400)
+#define TMR_DMABurstLength_6Transfers          ((uint16_t)0x0500)
+#define TMR_DMABurstLength_7Transfers          ((uint16_t)0x0600)
+#define TMR_DMABurstLength_8Transfers          ((uint16_t)0x0700)
+#define TMR_DMABurstLength_9Transfers          ((uint16_t)0x0800)
+#define TMR_DMABurstLength_10Transfers         ((uint16_t)0x0900)
+#define TMR_DMABurstLength_11Transfers         ((uint16_t)0x0A00)
+#define TMR_DMABurstLength_12Transfers         ((uint16_t)0x0B00)
+#define TMR_DMABurstLength_13Transfers         ((uint16_t)0x0C00)
+#define TMR_DMABurstLength_14Transfers         ((uint16_t)0x0D00)
+#define TMR_DMABurstLength_15Transfers         ((uint16_t)0x0E00)
+#define TMR_DMABurstLength_16Transfers         ((uint16_t)0x0F00)
+#define TMR_DMABurstLength_17Transfers         ((uint16_t)0x1000)
+#define TMR_DMABurstLength_18Transfers         ((uint16_t)0x1100)
+#define IS_TMR_DMA_LENGTH(LENGTH)              (((LENGTH) == TMR_DMABurstLength_1Transfer) || \
+                                                ((LENGTH) == TMR_DMABurstLength_2Transfers) || \
+                                                ((LENGTH) == TMR_DMABurstLength_3Transfers) || \
+                                                ((LENGTH) == TMR_DMABurstLength_4Transfers) || \
+                                                ((LENGTH) == TMR_DMABurstLength_5Transfers) || \
+                                                ((LENGTH) == TMR_DMABurstLength_6Transfers) || \
+                                                ((LENGTH) == TMR_DMABurstLength_7Transfers) || \
+                                                ((LENGTH) == TMR_DMABurstLength_8Transfers) || \
+                                                ((LENGTH) == TMR_DMABurstLength_9Transfers) || \
+                                                ((LENGTH) == TMR_DMABurstLength_10Transfers) || \
+                                                ((LENGTH) == TMR_DMABurstLength_11Transfers) || \
+                                                ((LENGTH) == TMR_DMABurstLength_12Transfers) || \
+                                                ((LENGTH) == TMR_DMABurstLength_13Transfers) || \
+                                                ((LENGTH) == TMR_DMABurstLength_14Transfers) || \
+                                                ((LENGTH) == TMR_DMABurstLength_15Transfers) || \
+                                                ((LENGTH) == TMR_DMABurstLength_16Transfers) || \
+                                                ((LENGTH) == TMR_DMABurstLength_17Transfers) || \
+                                                ((LENGTH) == TMR_DMABurstLength_18Transfers))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_DMA_sources 
+  * @{
+  */
+
+#define TMR_DMA_Update                      ((uint16_t)0x0100)
+#define TMR_DMA_CC1                         ((uint16_t)0x0200)
+#define TMR_DMA_CC2                         ((uint16_t)0x0400)
+#define TMR_DMA_CC3                         ((uint16_t)0x0800)
+#define TMR_DMA_CC4                         ((uint16_t)0x1000)
+#define TMR_DMA_HALL                        ((uint16_t)0x2000)
+#define TMR_DMA_Trigger                     ((uint16_t)0x4000)
+#define IS_TMR_DMA_SOURCE(SOURCE)           ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_External_Trigger_Prescaler 
+  * @{
+  */
+
+#define TMR_ExtTRGDIV_OFF                  ((uint16_t)0x0000)
+#define TMR_ExtTRGDIV_DIV2                 ((uint16_t)0x1000)
+#define TMR_ExtTRGDIV_DIV4                 ((uint16_t)0x2000)
+#define TMR_ExtTRGDIV_DIV8                 ((uint16_t)0x3000)
+#define IS_TMR_EXT_DIV(DIV)                (((DIV) == TMR_ExtTRGDIV_OFF) || \
+                                            ((DIV) == TMR_ExtTRGDIV_DIV2) || \
+                                            ((DIV) == TMR_ExtTRGDIV_DIV4) || \
+                                            ((DIV) == TMR_ExtTRGDIV_DIV8))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Internal_Trigger_Selection 
+  * @{
+  */
+
+#define TMR_TRGSEL_ITR0                        ((uint16_t)0x0000)
+#define TMR_TRGSEL_ITR1                        ((uint16_t)0x0010)
+#define TMR_TRGSEL_ITR2                        ((uint16_t)0x0020)
+#define TMR_TRGSEL_ITR3                        ((uint16_t)0x0030)
+#define TMR_TRGSEL_TI1F_ED                     ((uint16_t)0x0040)
+#define TMR_TRGSEL_TI1FP1                      ((uint16_t)0x0050)
+#define TMR_TRGSEL_TI2FP2                      ((uint16_t)0x0060)
+#define TMR_TRGSEL_ETRF                        ((uint16_t)0x0070)
+#define IS_TMR_TRIGGER_SELECTION(SELECTION)    (((SELECTION) == TMR_TRGSEL_ITR0) || \
+                                                ((SELECTION) == TMR_TRGSEL_ITR1) || \
+                                                ((SELECTION) == TMR_TRGSEL_ITR2) || \
+                                                ((SELECTION) == TMR_TRGSEL_ITR3) || \
+                                                ((SELECTION) == TMR_TRGSEL_TI1F_ED) || \
+                                                ((SELECTION) == TMR_TRGSEL_TI1FP1) || \
+                                                ((SELECTION) == TMR_TRGSEL_TI2FP2) || \
+                                                ((SELECTION) == TMR_TRGSEL_ETRF))
+#define IS_TMR_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TMR_TRGSEL_ITR0) || \
+                                                      ((SELECTION) == TMR_TRGSEL_ITR1) || \
+                                                      ((SELECTION) == TMR_TRGSEL_ITR2) || \
+                                                      ((SELECTION) == TMR_TRGSEL_ITR3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_TIx_External_Clock_Source 
+  * @{
+  */
+
+#define TMR_TIxExternalCLK1Source_TI1         ((uint16_t)0x0050)
+#define TMR_TIxExternalCLK1Source_TI2         ((uint16_t)0x0060)
+#define TMR_TIxExternalCLK1Source_TI1ED       ((uint16_t)0x0040)
+#define IS_TMR_TIXCLK_SOURCE(SOURCE)          (((SOURCE) == TMR_TIxExternalCLK1Source_TI1) || \
+                                               ((SOURCE) == TMR_TIxExternalCLK1Source_TI2) || \
+                                               ((SOURCE) == TMR_TIxExternalCLK1Source_TI1ED))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_External_Trigger_Polarity 
+  * @{
+  */ 
+#define TMR_ExtTRGPolarity_Inverted         ((uint16_t)0x8000)
+#define TMR_ExtTRGPolarity_NonInverted      ((uint16_t)0x0000)
+#define IS_TMR_EXT_POLARITY(POLARITY)       (((POLARITY) == TMR_ExtTRGPolarity_Inverted) || \
+                                             ((POLARITY) == TMR_ExtTRGPolarity_NonInverted))
+/**
+  * @}
+  */
+
+/** @defgroup TMR_Prescaler_Reload_Mode 
+  * @{
+  */
+
+#define TMR_DIVReloadMode_Update           ((uint16_t)0x0000)
+#define TMR_DIVReloadMode_Immediate        ((uint16_t)0x0001)
+#define IS_TMR_DIV_RELOAD(RELOAD)          (((RELOAD) == TMR_DIVReloadMode_Update) || \
+                                            ((RELOAD) == TMR_DIVReloadMode_Immediate))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Forced_Action 
+  * @{
+  */
+
+#define TMR_ForcedAction_Active            ((uint16_t)0x0050)
+#define TMR_ForcedAction_InActive          ((uint16_t)0x0040)
+#define IS_TMR_FORCED_ACTION(ACTION)       (((ACTION) == TMR_ForcedAction_Active) || \
+                                            ((ACTION) == TMR_ForcedAction_InActive))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Encoder_Mode 
+  * @{
+  */
+
+#define TMR_EncoderMode_TI1                ((uint16_t)0x0001)
+#define TMR_EncoderMode_TI2                ((uint16_t)0x0002)
+#define TMR_EncoderMode_TI12               ((uint16_t)0x0003)
+#define IS_TMR_ENCODER_MODE(MODE)          (((MODE) == TMR_EncoderMode_TI1) || \
+                                            ((MODE) == TMR_EncoderMode_TI2) || \
+                                            ((MODE) == TMR_EncoderMode_TI12))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup TMR_Event_Source 
+  * @{
+  */
+
+#define TMR_EventSource_Update             ((uint16_t)0x0001)
+#define TMR_EventSource_CC1                ((uint16_t)0x0002)
+#define TMR_EventSource_CC2                ((uint16_t)0x0004)
+#define TMR_EventSource_CC3                ((uint16_t)0x0008)
+#define TMR_EventSource_CC4                ((uint16_t)0x0010)
+#define TMR_EventSource_HALL               ((uint16_t)0x0020)
+#define TMR_EventSource_Trigger            ((uint16_t)0x0040)
+#define TMR_EventSource_Break              ((uint16_t)0x0080)
+#define IS_TMR_EVENT_SOURCE(SOURCE)        ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Update_Source 
+  * @{
+  */
+
+#define TMR_UpdateSource_Global            ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
+                                                                   or the setting of UG bit, or an update generation
+                                                                   through the slave mode controller. */
+#define TMR_UpdateSource_Regular           ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IS_TMR_UPDATE_SOURCE(SOURCE)       (((SOURCE) == TMR_UpdateSource_Global) || \
+                                            ((SOURCE) == TMR_UpdateSource_Regular))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Plus_Mode__State 
+  * @{
+  */	
+	
+#define TMR_Plus_Mode_Enable              ((uint16_t)0x0400)	
+#define TMR_Plus_Mode_Disable             ((uint16_t)0x0000)	
+#define IS_TMR_PLUS_MODE_STATE(STATE) (((STATE) == TMR_Plus_Mode_Enable) || \
+                                       ((STATE) == TMR_Plus_Mode_Disable))	
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Output_Compare_Preload_State 
+  * @{
+  */
+
+#define TMR_OCPreload_Enable               ((uint16_t)0x0008)
+#define TMR_OCPreload_Disable              ((uint16_t)0x0000)
+#define IS_TMR_OCPRELOAD_STATE(STATE)      (((STATE) == TMR_OCPreload_Enable) || \
+                                            ((STATE) == TMR_OCPreload_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Output_Compare_Fast_State 
+  * @{
+  */
+
+#define TMR_OCFast_Enable                  ((uint16_t)0x0004)
+#define TMR_OCFast_Disable                 ((uint16_t)0x0000)
+#define IS_TMR_OCFAST_STATE(STATE)         (((STATE) == TMR_OCFast_Enable) || \
+                                            ((STATE) == TMR_OCFast_Disable))
+                                     
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Output_Compare_Clear_State 
+  * @{
+  */
+
+#define TMR_OCClear_Enable                 ((uint16_t)0x0080)
+#define TMR_OCClear_Disable                ((uint16_t)0x0000)
+#define IS_TMR_OCCLEAR_STATE(STATE)        (((STATE) == TMR_OCClear_Enable) || \
+                                            ((STATE) == TMR_OCClear_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Trigger_Output_Source 
+  * @{
+  */
+
+#define TMR_TRGOSource_Reset               ((uint16_t)0x0000)
+#define TMR_TRGOSource_Enable              ((uint16_t)0x0010)
+#define TMR_TRGOSource_Update              ((uint16_t)0x0020)
+#define TMR_TRGOSource_OC1                 ((uint16_t)0x0030)
+#define TMR_TRGOSource_OC1Ref              ((uint16_t)0x0040)
+#define TMR_TRGOSource_OC2Ref              ((uint16_t)0x0050)
+#define TMR_TRGOSource_OC3Ref              ((uint16_t)0x0060)
+#define TMR_TRGOSource_OC4Ref              ((uint16_t)0x0070)
+#define IS_TMR_TRGO_SOURCE(SOURCE)         (((SOURCE) == TMR_TRGOSource_Reset) || \
+                                            ((SOURCE) == TMR_TRGOSource_Enable) || \
+                                            ((SOURCE) == TMR_TRGOSource_Update) || \
+                                            ((SOURCE) == TMR_TRGOSource_OC1) || \
+                                            ((SOURCE) == TMR_TRGOSource_OC1Ref) || \
+                                            ((SOURCE) == TMR_TRGOSource_OC2Ref) || \
+                                            ((SOURCE) == TMR_TRGOSource_OC3Ref) || \
+                                            ((SOURCE) == TMR_TRGOSource_OC4Ref))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Slave_Mode 
+  * @{
+  */
+
+#define TMR_SlaveMode_Reset                ((uint16_t)0x0004)
+#define TMR_SlaveMode_Gate                 ((uint16_t)0x0005)
+#define TMR_SlaveMode_Trigger              ((uint16_t)0x0006)
+#define TMR_SlaveMode_External1            ((uint16_t)0x0007)
+#define IS_TMR_SLAVE_MODE(MODE)            (((MODE) == TMR_SlaveMode_Reset) || \
+                                            ((MODE) == TMR_SlaveMode_Gate) || \
+                                            ((MODE) == TMR_SlaveMode_Trigger) || \
+                                            ((MODE) == TMR_SlaveMode_External1))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Master_Slave_Mode 
+  * @{
+  */
+
+#define TMR_MasterSlaveMode_Enable         ((uint16_t)0x0080)
+#define TMR_MasterSlaveMode_Disable        ((uint16_t)0x0000)
+#define IS_TMR_MSMODE_STATE(STATE)         (((STATE) == TMR_MasterSlaveMode_Enable) || \
+                                            ((STATE) == TMR_MasterSlaveMode_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Flags 
+  * @{
+  */
+
+#define TMR_FLAG_Update                    ((uint16_t)0x0001)
+#define TMR_FLAG_CC1                       ((uint16_t)0x0002)
+#define TMR_FLAG_CC2                       ((uint16_t)0x0004)
+#define TMR_FLAG_CC3                       ((uint16_t)0x0008)
+#define TMR_FLAG_CC4                       ((uint16_t)0x0010)
+#define TMR_FLAG_HALL                      ((uint16_t)0x0020)
+#define TMR_FLAG_Trigger                   ((uint16_t)0x0040)
+#define TMR_FLAG_Break                     ((uint16_t)0x0080)
+#define TMR_FLAG_C1OF                      ((uint16_t)0x0200)
+#define TMR_FLAG_C2OF                      ((uint16_t)0x0400)
+#define TMR_FLAG_C3OF                      ((uint16_t)0x0800)
+#define TMR_FLAG_C4OF                      ((uint16_t)0x1000)
+#define IS_TMR_GET_FLAG(FLAG)              (((FLAG) == TMR_FLAG_Update) || \
+                                            ((FLAG) == TMR_FLAG_CC1) || \
+                                            ((FLAG) == TMR_FLAG_CC2) || \
+                                            ((FLAG) == TMR_FLAG_CC3) || \
+                                            ((FLAG) == TMR_FLAG_CC4) || \
+                                            ((FLAG) == TMR_FLAG_HALL) || \
+                                            ((FLAG) == TMR_FLAG_Trigger) || \
+                                            ((FLAG) == TMR_FLAG_Break) || \
+                                            ((FLAG) == TMR_FLAG_C1OF) || \
+                                            ((FLAG) == TMR_FLAG_C2OF) || \
+                                            ((FLAG) == TMR_FLAG_C3OF) || \
+                                            ((FLAG) == TMR_FLAG_C4OF))
+                               
+                               
+#define IS_TMR_CLEAR_FLAG(TMR_FLAG)        ((((TMR_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TMR_FLAG) != 0x0000))
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Input_Capture_Filer_Value 
+  * @{
+  */
+
+#define IS_TMR_IC_FILTER(ICFILTER)         ((ICFILTER) <= 0xF) 
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_External_Trigger_Filter 
+  * @{
+  */
+
+#define IS_TMR_EXT_FILTER(EXTFILTER)      ((EXTFILTER) <= 0xF)
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Legacy 
+  * @{
+  */
+
+#define TMR_DMABurstLength_1Byte           TMR_DMABurstLength_1Transfer
+#define TMR_DMABurstLength_2Bytes          TMR_DMABurstLength_2Transfers
+#define TMR_DMABurstLength_3Bytes          TMR_DMABurstLength_3Transfers
+#define TMR_DMABurstLength_4Bytes          TMR_DMABurstLength_4Transfers
+#define TMR_DMABurstLength_5Bytes          TMR_DMABurstLength_5Transfers
+#define TMR_DMABurstLength_6Bytes          TMR_DMABurstLength_6Transfers
+#define TMR_DMABurstLength_7Bytes          TMR_DMABurstLength_7Transfers
+#define TMR_DMABurstLength_8Bytes          TMR_DMABurstLength_8Transfers
+#define TMR_DMABurstLength_9Bytes          TMR_DMABurstLength_9Transfers
+#define TMR_DMABurstLength_10Bytes         TMR_DMABurstLength_10Transfers
+#define TMR_DMABurstLength_11Bytes         TMR_DMABurstLength_11Transfers
+#define TMR_DMABurstLength_12Bytes         TMR_DMABurstLength_12Transfers
+#define TMR_DMABurstLength_13Bytes         TMR_DMABurstLength_13Transfers
+#define TMR_DMABurstLength_14Bytes         TMR_DMABurstLength_14Transfers
+#define TMR_DMABurstLength_15Bytes         TMR_DMABurstLength_15Transfers
+#define TMR_DMABurstLength_16Bytes         TMR_DMABurstLength_16Transfers
+#define TMR_DMABurstLength_17Bytes         TMR_DMABurstLength_17Transfers
+#define TMR_DMABurstLength_18Bytes         TMR_DMABurstLength_18Transfers
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TMR_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TMR_Exported_Functions
+  * @{
+  */
+
+void TMR_Reset(TMR_Type* TMRx);
+void TMR_TimeBaseInit(TMR_Type* TMRx, TMR_TimerBaseInitType* TMR_TimeBaseInitStruct);
+void TMR_OC1Init(TMR_Type* TMRx, TMR_OCInitType* TMR_OCInitStruct);
+void TMR_OC2Init(TMR_Type* TMRx, TMR_OCInitType* TMR_OCInitStruct);
+void TMR_OC3Init(TMR_Type* TMRx, TMR_OCInitType* TMR_OCInitStruct);
+void TMR_OC4Init(TMR_Type* TMRx, TMR_OCInitType* TMR_OCInitStruct);
+void TMR_ICInit(TMR_Type* TMRx, TMR_ICInitType* TMR_ICInitStruct);
+void TMR_PWMIConfig(TMR_Type* TMRx, TMR_ICInitType* TMR_ICInitStruct);
+void TMR_BRKDTConfig(TMR_Type* TMRx, TMR_BRKDTInitType *TMR_BDTRInitStruct);
+void TMR_TimeBaseStructInit(TMR_TimerBaseInitType* TMR_TimeBaseInitStruct);
+void TMR_OCStructInit(TMR_OCInitType* TMR_OCInitStruct);
+void TMR_ICStructInit(TMR_ICInitType* TMR_ICInitStruct);
+void TMR_BRKDTStructInit(TMR_BRKDTInitType* TMR_BDTRInitStruct);
+void TMR_Cmd(TMR_Type* TMRx, FunctionalState NewState);
+void TMR_CtrlPWMOutputs(TMR_Type* TMRx, FunctionalState NewState);
+void TMR_INTConfig(TMR_Type* TMRx, uint16_t TMR_INT, FunctionalState NewState);
+void TMR_GenerateEvent(TMR_Type* TMRx, uint16_t TMR_EventSource);
+void TMR_DMAConfig(TMR_Type* TMRx, uint16_t TMR_DMABase, uint16_t TMR_DMABurstLength);
+void TMR_DMACmd(TMR_Type* TMRx, uint16_t TMR_DMASource, FunctionalState NewState);
+void TMR_InternalClockConfig(TMR_Type* TMRx);
+void TMR_ITRxExternalClockConfig(TMR_Type* TMRx, uint16_t TMR_InputTriggerSource);
+void TMR_TIxExternalClockConfig(TMR_Type* TMRx, uint16_t TMR_TIxExternalCLKSource,
+                                uint16_t TMR_ICPolarity, uint16_t ICFilter);
+void TMR_ETRClockMode1Config(TMR_Type* TMRx, uint16_t TMR_ExtTRGPrescaler, uint16_t TMR_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter);
+void TMR_ETRClockMode2Config(TMR_Type* TMRx, uint16_t TMR_ExtTRGPrescaler, 
+                             uint16_t TMR_ExtTRGPolarity, uint16_t ExtTRGFilter);
+void TMR_ETRConfig(TMR_Type* TMRx, uint16_t TMR_ExtTRGPrescaler, uint16_t TMR_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter);
+void TMR_DIVConfig(TMR_Type* TMRx, uint16_t Prescaler, uint16_t TMR_PSCReloadMode);
+void TMR_CounterModeConfig(TMR_Type* TMRx, uint16_t TMR_CounterMode);
+void TMR_SelectInputTrigger(TMR_Type* TMRx, uint16_t TMR_InputTriggerSource);
+void TMR_EncoderInterfaceConfig(TMR_Type* TMRx, uint16_t TMR_EncoderMode,
+                                uint16_t TMR_IC1Polarity, uint16_t TMR_IC2Polarity);
+void TMR_ForcedOC1Config(TMR_Type* TMRx, uint16_t TMR_ForcedAction);
+void TMR_ForcedOC2Config(TMR_Type* TMRx, uint16_t TMR_ForcedAction);
+void TMR_ForcedOC3Config(TMR_Type* TMRx, uint16_t TMR_ForcedAction);
+void TMR_ForcedOC4Config(TMR_Type* TMRx, uint16_t TMR_ForcedAction);
+void TMR_ARPreloadConfig(TMR_Type* TMRx, FunctionalState NewState);
+void TMR_SelectHALL(TMR_Type* TMRx, FunctionalState NewState);
+void TMR_SelectCCDMA(TMR_Type* TMRx, FunctionalState NewState);
+void TMR_CCPreloadControl(TMR_Type* TMRx, FunctionalState NewState);
+void TMR_OC1PreloadConfig(TMR_Type* TMRx, uint16_t TMR_OCPreload);
+void TMR_OC2PreloadConfig(TMR_Type* TMRx, uint16_t TMR_OCPreload);
+void TMR_OC3PreloadConfig(TMR_Type* TMRx, uint16_t TMR_OCPreload);
+void TMR_OC4PreloadConfig(TMR_Type* TMRx, uint16_t TMR_OCPreload);
+void TMR_OC1FastConfig(TMR_Type* TMRx, uint16_t TMR_OCFast);
+void TMR_OC2FastConfig(TMR_Type* TMRx, uint16_t TMR_OCFast);
+void TMR_OC3FastConfig(TMR_Type* TMRx, uint16_t TMR_OCFast);
+void TMR_OC4FastConfig(TMR_Type* TMRx, uint16_t TMR_OCFast);
+void TMR_ClearOC1Ref(TMR_Type* TMRx, uint16_t TMR_OCClear);
+void TMR_ClearOC2Ref(TMR_Type* TMRx, uint16_t TMR_OCClear);
+void TMR_ClearOC3Ref(TMR_Type* TMRx, uint16_t TMR_OCClear);
+void TMR_ClearOC4Ref(TMR_Type* TMRx, uint16_t TMR_OCClear);
+void TMR_OC1PolarityConfig(TMR_Type* TMRx, uint16_t TMR_OCPolarity);
+void TMR_OC1NPolarityConfig(TMR_Type* TMRx, uint16_t TMR_OCNPolarity);
+void TMR_OC2PolarityConfig(TMR_Type* TMRx, uint16_t TMR_OCPolarity);
+void TMR_OC2NPolarityConfig(TMR_Type* TMRx, uint16_t TMR_OCNPolarity);
+void TMR_OC3PolarityConfig(TMR_Type* TMRx, uint16_t TMR_OCPolarity);
+void TMR_OC3NPolarityConfig(TMR_Type* TMRx, uint16_t TMR_OCNPolarity);
+void TMR_OC4PolarityConfig(TMR_Type* TMRx, uint16_t TMR_OCPolarity);
+void TMR_CCxCmd(TMR_Type* TMRx, uint16_t TMR_Channel, uint16_t TMR_CCx);
+void TMR_CCxNCmd(TMR_Type* TMRx, uint16_t TMR_Channel, uint16_t TMR_CCxN);
+void TMR_SelectOCxM(TMR_Type* TMRx, uint16_t TMR_Channel, uint16_t TMR_OCMode);
+void TMR_UpdateDisableConfig(TMR_Type* TMRx, FunctionalState NewState);
+void TMR_UpdateRequestConfig(TMR_Type* TMRx, uint16_t TMR_UpdateSource);
+void TMR_SelectHallSensor(TMR_Type* TMRx, FunctionalState NewState);
+void TMR_SelectOnePulseMode(TMR_Type* TMRx, uint16_t TMR_OPMode);
+void TMR_SelectPlusMode(TMR_Type* TIMx, uint16_t  TIMX_PLUS_MODE_STATE);
+void TMR_SelectOutputTrigger(TMR_Type* TMRx, uint16_t TMR_TRGOSource);
+void TMR_SelectSlaveMode(TMR_Type* TMRx, uint16_t TMR_SlaveMode);
+void TMR_SelectMasterSlaveMode(TMR_Type* TMRx, uint16_t TMR_MasterSlaveMode);
+void TMR_SetCounter(TMR_Type* TMRx, uint32_t Counter);
+void TMR_SetAutoreload(TMR_Type* TMRx, uint32_t Autoreload);
+void TMR_SetCompare1(TMR_Type* TMRx, uint32_t Compare1);
+void TMR_SetCompare2(TMR_Type* TMRx, uint32_t Compare2);
+void TMR_SetCompare3(TMR_Type* TMRx, uint32_t Compare3);
+void TMR_SetCompare4(TMR_Type* TMRx, uint32_t Compare4);
+void TMR_SetIC1DIV(TMR_Type* TMRx, uint16_t TMR_ICPSC);
+void TMR_SetIC2DIV(TMR_Type* TMRx, uint16_t TMR_ICPSC);
+void TMR_SetIC3DIV(TMR_Type* TMRx, uint16_t TMR_ICPSC);
+void TMR_SetIC4DIV(TMR_Type* TMRx, uint16_t TMR_ICPSC);
+void TMR_SetClockDivision(TMR_Type* TMRx, uint16_t TMR_CKD);
+uint32_t TMR_GetCapture1(TMR_Type* TMRx);
+uint32_t TMR_GetCapture2(TMR_Type* TMRx);
+uint32_t TMR_GetCapture3(TMR_Type* TMRx);
+uint32_t TMR_GetCapture4(TMR_Type* TMRx);
+uint32_t TMR_GetCounter(TMR_Type* TMRx);
+uint16_t TMR_GetDIV(TMR_Type* TMRx);
+FlagStatus TMR_GetFlagStatus(TMR_Type* TMRx, uint16_t TMR_FLAG);
+void TMR_ClearFlag(TMR_Type* TMRx, uint16_t TMR_FLAG);
+ITStatus TMR_GetINTStatus(TMR_Type* TMRx, uint16_t TMR_INT);
+void TMR_ClearITPendingBit(TMR_Type* TMRx, uint16_t TMR_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4xx_TIM_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_usart.h

@@ -0,0 +1,400 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_usart.h
+ * Description  : at32f4xx USART header file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_USART_H
+#define __AT32F4xx_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup USART
+  * @{
+  */
+
+/** @defgroup USART_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  USART Init Structure definition
+  */
+
+typedef struct
+{
+    uint32_t USART_BaudRate;                /*!< This member configures the USART communication baud rate.
+                                                 The baud rate is computed using the following formula:
+                                                  - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+                                                  - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+    uint16_t USART_WordLength;               /*!< Specifies the number of data bits transmitted or received in a frame.
+                                                  This parameter can be a value of @ref USART_Word_Length */
+
+    uint16_t USART_StopBits;                /*!< Specifies the number of stop bits transmitted.
+                                                 This parameter can be a value of @ref USART_Stop_Bits */
+                                             
+    uint16_t USART_Parity;                  /*!< Specifies the parity mode.
+                                                 This parameter can be a value of @ref USART_Parity
+                                                 @note When parity is enabled, the computed parity is inserted
+                                                       at the MSB position of the transmitted data (9th bit when
+                                                       the word length is set to 9 data bits; 8th bit when the
+                                                       word length is set to 8 data bits). */
+                                            
+    uint16_t USART_Mode;                    /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                                 This parameter can be a value of @ref USART_Mode */
+                                            
+    uint16_t USART_HardwareFlowControl;     /*!< Specifies wether the hardware flow control mode is enabled
+                                                 or disabled.
+                                                 This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitType;
+
+/**
+  * @brief  USART Clock Init Structure definition
+  */
+
+typedef struct
+{
+
+    uint16_t USART_Clock;                   /*!< Specifies whether the USART clock is enabled or disabled.
+                                                This parameter can be a value of @ref USART_Clock */
+                                            
+    uint16_t USART_CPOL;                    /*!< Specifies the steady state value of the serial clock.
+                                                This parameter can be a value of @ref USART_Clock_Polarity */
+                                            
+    uint16_t USART_CPHA;                    /*!< Specifies the clock transition on which the bit capture is made.
+                                                This parameter can be a value of @ref USART_Clock_Phase */
+                                            
+    uint16_t USART_LastBit;                 /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                                data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                                This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitType;
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Exported_Constants
+  * @{
+  */
+
+#define IS_USART_ALL_PERIPH(PERIPH)         (((PERIPH) == USART1) || \
+                                             ((PERIPH) == USART2) || \
+                                             ((PERIPH) == USART3) || \
+                                             ((PERIPH) == UART4) || \
+                                             ((PERIPH) == UART5))
+
+#define IS_USART_123_PERIPH(PERIPH)         (((PERIPH) == USART1) || \
+                                             ((PERIPH) == USART2) || \
+                                             ((PERIPH) == USART3))
+                                            
+#define IS_USART_1234_PERIPH(PERIPH)        (((PERIPH) == USART1) || \
+                                             ((PERIPH) == USART2) || \
+                                             ((PERIPH) == USART3) || \
+                                             ((PERIPH) == UART4))
+/** @defgroup USART_Word_Length
+  * @{
+  */
+
+#define USART_WordLength_8b                 ((uint16_t)0x0000)
+#define USART_WordLength_9b                 ((uint16_t)0x1000)
+
+#define IS_USART_WORD_LENGTH(LENGTH)        (((LENGTH) == USART_WordLength_8b) || \
+                                             ((LENGTH) == USART_WordLength_9b))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Stop_Bits
+  * @{
+  */
+                                            
+#define USART_StopBits_1                    ((uint16_t)0x0000)
+#define USART_StopBits_0_5                  ((uint16_t)0x1000)
+#define USART_StopBits_2                    ((uint16_t)0x2000)
+#define USART_StopBits_1_5                  ((uint16_t)0x3000)
+#define IS_USART_STOPBITS(STOPBITS)         (((STOPBITS) == USART_StopBits_1) || \
+                                             ((STOPBITS) == USART_StopBits_0_5) || \
+                                             ((STOPBITS) == USART_StopBits_2) || \
+                                             ((STOPBITS) == USART_StopBits_1_5))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Parity
+  * @{
+  */
+
+#define USART_Parity_No                     ((uint16_t)0x0000)
+#define USART_Parity_Even                   ((uint16_t)0x0400)
+#define USART_Parity_Odd                    ((uint16_t)0x0600)
+#define IS_USART_PARITY(PARITY)             (((PARITY) == USART_Parity_No) || \
+                                             ((PARITY) == USART_Parity_Even) || \
+                                             ((PARITY) == USART_Parity_Odd))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Mode
+  * @{
+  */
+
+#define USART_Mode_Rx                       ((uint16_t)0x0004)
+#define USART_Mode_Tx                       ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE)                 ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Hardware_Flow_Control
+  * @{
+  */
+#define USART_HardwareFlowControl_None      ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS       ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS       ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS   ((uint16_t)0x0300)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                                            (((CONTROL) == USART_HardwareFlowControl_None) || \
+                                             ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+                                             ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+                                             ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock
+  * @{
+  */
+#define USART_Clock_Disable                 ((uint16_t)0x0000)
+#define USART_Clock_Enable                  ((uint16_t)0x0800)
+#define IS_USART_CLOCK(CLOCK)               (((CLOCK) == USART_Clock_Disable) || \
+                                             ((CLOCK) == USART_Clock_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock_Polarity
+  * @{
+  */
+
+#define USART_CPOL_Low                      ((uint16_t)0x0000)
+#define USART_CPOL_High                     ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL)                 (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock_Phase
+  * @{
+  */
+
+#define USART_CPHA_1Edge                    ((uint16_t)0x0000)
+#define USART_CPHA_2Edge                    ((uint16_t)0x0200)
+#define IS_USART_CPHA(CPHA)                 (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Last_Bit
+  * @{
+  */
+
+#define USART_LastBit_Disable               ((uint16_t)0x0000)
+#define USART_LastBit_Enable                ((uint16_t)0x0100)
+#define IS_USART_LASTBIT(LASTBIT)           (((LASTBIT) == USART_LastBit_Disable) || \
+                                             ((LASTBIT) == USART_LastBit_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Interrupt_definition
+  * @{
+  */
+
+#define USART_INT_PERR                      ((uint16_t)0x0028)
+#define USART_INT_TDE                       ((uint16_t)0x0727)
+#define USART_INT_TRAC                      ((uint16_t)0x0626)
+#define USART_INT_RDNE                      ((uint16_t)0x0525)
+#define USART_INT_IDLEF                     ((uint16_t)0x0424)
+#define USART_INT_LBDF                      ((uint16_t)0x0846)
+#define USART_INT_CTSF                      ((uint16_t)0x096A)
+#define USART_INT_ERR                       ((uint16_t)0x0060)
+#define USART_INT_ORERR                     ((uint16_t)0x0360)
+#define USART_INT_NERR                      ((uint16_t)0x0260)
+#define USART_INT_FERR                      ((uint16_t)0x0160)
+#define IS_USART_CONFIG_INT(INT)            (((INT) == USART_INT_PERR)  || ((INT) == USART_INT_TDE) || \
+                                             ((INT) == USART_INT_TRAC)  || ((INT) == USART_INT_RDNE) || \
+                                             ((INT) == USART_INT_IDLEF) || ((INT) == USART_INT_LBDF) || \
+                                             ((INT) == USART_INT_CTSF)  || ((INT) == USART_INT_ERR))
+#define IS_USART_GET_INT(INT)               (((INT) == USART_INT_PERR)  || ((INT) == USART_INT_TDE) || \
+                                             ((INT) == USART_INT_TRAC)  || ((INT) == USART_INT_RDNE) || \
+                                             ((INT) == USART_INT_IDLEF) || ((INT) == USART_INT_LBDF) || \
+                                             ((INT) == USART_INT_CTSF)  || ((INT) == USART_INT_ORERR) || \
+                                             ((INT) == USART_INT_NERR)  || ((INT) == USART_INT_FERR))
+#define IS_USART_CLEAR_INT(INT)             (((INT) == USART_INT_TRAC)  || ((INT) == USART_INT_RDNE) || \
+                                             ((INT) == USART_INT_LBDF)  || ((INT) == USART_INT_CTSF))
+/**
+  * @}
+  */
+
+/** @defgroup USART_DMA_Requests
+  * @{
+  */
+
+#define USART_DMAReq_Tx                     ((uint16_t)0x0080)
+#define USART_DMAReq_Rx                     ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ)             ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_WakeUp_methods
+  * @{
+  */
+
+#define USART_WakeUp_IdleLine               ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark            ((uint16_t)0x0800)
+#define IS_USART_WAKEUP(WAKEUP)             (((WAKEUP) == USART_WakeUp_IdleLine) || \
+                                             ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+  * @}
+  */
+
+/** @defgroup USART_LIN_Break_Detection_Length
+  * @{
+  */
+
+#define USART_LINBreakDetectLength_10b      ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b      ((uint16_t)0x0020)
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+                                            (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+                                             ((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+  * @}
+  */
+
+/** @defgroup USART_IrDA_Low_Power
+  * @{
+  */
+
+#define USART_IrDAMode_LowPower             ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal               ((uint16_t)0x0000)
+#define IS_USART_IRDA_MODE(MODE)            (((MODE) == USART_IrDAMode_LowPower) || \
+                                             ((MODE) == USART_IrDAMode_Normal))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Flags
+  * @{
+  */
+
+#define USART_FLAG_CTSF                     ((uint16_t)0x0200)
+#define USART_FLAG_LBDF                     ((uint16_t)0x0100)
+#define USART_FLAG_TDE                      ((uint16_t)0x0080)
+#define USART_FLAG_TRAC                     ((uint16_t)0x0040)
+#define USART_FLAG_RDNE                     ((uint16_t)0x0020)
+#define USART_FLAG_IDLEF                    ((uint16_t)0x0010)
+#define USART_FLAG_ORERR                    ((uint16_t)0x0008)
+#define USART_FLAG_NERR                     ((uint16_t)0x0004)
+#define USART_FLAG_FERR                     ((uint16_t)0x0002)
+#define USART_FLAG_PERR                     ((uint16_t)0x0001)
+#define IS_USART_FLAG(FLAG)                 (((FLAG) == USART_FLAG_PERR) || ((FLAG) == USART_FLAG_TDE) || \
+                                             ((FLAG) == USART_FLAG_TRAC) || ((FLAG) == USART_FLAG_RDNE) || \
+                                             ((FLAG) == USART_FLAG_IDLEF)|| ((FLAG) == USART_FLAG_LBDF) || \
+                                             ((FLAG) == USART_FLAG_CTSF) || ((FLAG) == USART_FLAG_ORERR) || \
+                                             ((FLAG) == USART_FLAG_NERR) || ((FLAG) == USART_FLAG_FERR))
+
+#define IS_USART_CLEAR_FLAG(FLAG)           ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG)    ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
+                                                     ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
+                                                     || ((USART_FLAG) != USART_FLAG_CTSF))
+#define IS_USART_BAUDRATE(BAUDRATE)         (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
+#define IS_USART_ADDRESS(ADDRESS)           ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA)                 ((DATA) <= 0x1FF)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Exported_Functions
+  * @{
+  */
+
+void USART_Reset(USART_Type* USARTx);
+void USART_Init(USART_Type* USARTx, USART_InitType* USART_InitStruct);
+void USART_StructInit(USART_InitType* USART_InitStruct);
+void USART_ClockInit(USART_Type* USARTx, USART_ClockInitType* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct);
+void USART_Cmd(USART_Type* USARTx, FunctionalState NewState);
+void USART_INTConfig(USART_Type* USARTx, uint16_t USART_INT, FunctionalState NewState);
+void USART_DMACmd(USART_Type* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+void USART_SetAddress(USART_Type* USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_Type* USARTx, uint16_t USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_Type* USARTx, FunctionalState NewState);
+void USART_LINBreakDetectLengthConfig(USART_Type* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_Type* USARTx, FunctionalState NewState);
+void USART_SendData(USART_Type* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_Type* USARTx);
+void USART_SendBreak(USART_Type* USARTx);
+void USART_SetGuardTime(USART_Type* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_Type* USARTx, uint8_t USART_Prescaler);
+void USART_SmartCardCmd(USART_Type* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_Type* USARTx, FunctionalState NewState);
+void USART_HalfDuplexCmd(USART_Type* USARTx, FunctionalState NewState);
+void USART_OverSampling8Cmd(USART_Type* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_Type* USARTx, FunctionalState NewState);
+void USART_IrDAConfig(USART_Type* USARTx, uint16_t USART_IrDAMode);
+void USART_IrDACmd(USART_Type* USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_Type* USARTx, uint16_t USART_FLAG);
+void USART_ClearFlag(USART_Type* USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_Type* USARTx, uint16_t USART_INT);
+void USART_ClearITPendingBit(USART_Type* USARTx, uint16_t USART_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_USART_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_wwdg.h

@@ -0,0 +1,103 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_wwdg.h
+ * Description  : at32f4xx WWDG header file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_WWDG_H
+#define __AT32F4xx_WWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup WWDG
+  * @{
+  */
+
+/** @defgroup WWDG_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Exported_Constants
+  * @{
+  */
+
+/** @defgroup WWDG_Prescaler
+  * @{
+  */
+
+#define WWDG_Psc_1                          ((uint32_t)0x00000000)
+#define WWDG_Psc_2                          ((uint32_t)0x00000080)
+#define WWDG_Psc_4                          ((uint32_t)0x00000100)
+#define WWDG_Psc_8                          ((uint32_t)0x00000180)
+#define IS_WWDG_PSC(PSC)                    (((PSC) == WWDG_Psc_1) || \
+                                             ((PSC) == WWDG_Psc_2) || \
+                                             ((PSC) == WWDG_Psc_4) || \
+                                             ((PSC) == WWDG_Psc_8))
+#define IS_WWDG_WCNTR(WCNTR)                ((WCNTR) <= 0x7F)
+#define IS_WWDG_CNTR(CNTR)                  (((CNTR) >= 0x40) && ((CNTR) <= 0x7F))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Exported_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Exported_Functions
+  * @{
+  */
+
+void WWDG_Reset(void);
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowCounter(uint8_t WindowValue);
+void WWDG_EnableINT(void);
+void WWDG_SetCounter(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_WWDG_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_xmc.h

@@ -0,0 +1,739 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_xmc.h
+ * Description  : at32f4xx XMC header file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_XMC_H
+#define __AT32F4xx_XMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup XMC
+  * @{
+  */
+
+/** @defgroup XMC_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  Timing parameters For NOR/SRAM Banks
+  */
+
+typedef struct
+{
+    uint32_t XMC_AdrOpTime;                 /*!< Defines the number of HCLK cycles to configure
+                                                       the duration of the address setup time.
+                                                       This parameter can be a value between 0 and 0xF.
+                                                       @note: It is not used with synchronous NOR Flash memories. */
+
+    uint32_t XMC_AdrHoldTime;               /*!< Defines the number of HCLK cycles to configure
+                                                    the duration of the address hold time.
+                                                    This parameter can be a value between 0 and 0xF.
+                                                    @note: It is not used with synchronous NOR Flash memories.*/
+
+    uint32_t XMC_DataOpTime;                /*!< Defines the number of HCLK cycles to configure
+                                                   the duration of the data setup time.
+                                                   This parameter can be a value between 0 and 0xFF.
+                                                   @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
+
+    uint32_t XMC_IntervalBetweenOP;         /*!< Defines the number of HCLK cycles to configure
+                                                    the duration of the bus turnaround.
+                                                    This parameter can be a value between 0 and 0xF.
+                                                    @note: It is only used for multiplexed NOR Flash memories. */
+
+    uint32_t XMC_CLKPsc;                    /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+                                                     This parameter can be a value between 1 and 0xF.
+                                                     @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
+
+    uint32_t XMC_DataStableTime;            /*!< Defines the number of memory clock cycles to issue
+                                             to the memory before getting the first data.
+                                             The value of this parameter depends on the memory type as shown below:
+                                              - It must be set to 0 in case of a CRAM
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
+                                              - It may assume a value between 0 and 0xF in NOR Flash memories
+                                                with synchronous burst mode enable */
+
+    uint32_t XMC_Mode;                      /*!< Specifies the asynchronous access mode.
+                                                      This parameter can be a value of @ref XMC_Access_Mode */
+} XMC_NORSRAMTimingInitType;
+
+/**
+  * @brief  XMC NOR/SRAM Init structure definition
+  */
+
+typedef struct
+{
+    uint32_t XMC_Bank;                      /*!< Specifies the NOR/SRAM memory bank that will be used.
+                                                 This parameter can be a value of @ref XMC_NORSRAM_Bank */
+
+    uint32_t XMC_DataAdrMux;                /*!< Specifies whether the address and data values are
+                                                 multiplexed on the databus or not.
+                                                 This parameter can be a value of @ref XMC_Data_Address_Bus_Multiplexing */
+
+    uint32_t XMC_Dev;                       /*!< Specifies the type of external memory attached to
+                                                 the corresponding memory bank.
+                                                 This parameter can be a value of @ref XMC_Memory_Type */
+
+    uint32_t XMC_BusType;                   /*!< Specifies the external memory device width.
+                                                        This parameter can be a value of @ref XMC_Data_Width */
+
+    uint32_t XMC_EnableBurstMode;           /*!< Enables or disables the burst access mode for Flash memory,
+                                                 valid only with synchronous burst Flash memories.
+                                                 This parameter can be a value of @ref XMC_Burst_Access_Mode */
+
+    uint32_t XMC_EnableAsynWait;            /*!< Enables or disables wait signal during asynchronous transfers,
+                                                 valid only with asynchronous Flash memories.
+                                                 This parameter can be a value of @ref XMC_EnableAsynWait */
+
+    uint32_t XMC_WaitSignalLv;              /*!< Specifies the wait signal polarity, valid only when accessing
+                                                 the Flash memory in burst mode.
+                                                 This parameter can be a value of @ref XMC_Wait_Signal_Polarity */
+
+    uint32_t XMC_EnableBurstModeSplit;      /*!< Enables or disables the Wrapped burst access mode for Flash
+                                                 memory, valid only when accessing Flash memories in burst mode.
+                                                 This parameter can be a value of @ref XMC_Wrap_Mode */
+
+    uint32_t XMC_WaitSignalConfig;          /*!< Specifies if the wait signal is asserted by the memory one
+                                                 clock cycle before the wait state or during the wait state,
+                                                 valid only when accessing memories in burst mode.
+                                                 This parameter can be a value of @ref XMC_Wait_Timing */
+
+    uint32_t XMC_EnableWrite;               /*!< Enables or disables the write operation in the selected bank by the XMC.
+                                                 This parameter can be a value of @ref XMC_Write_Operation */
+
+    uint32_t XMC_EnableWaitSignal;          /*!< Enables or disables the wait-state insertion via wait
+                                                 signal, valid for Flash memory access in burst mode.
+                                                 This parameter can be a value of @ref XMC_Wait_Signal */
+
+    uint32_t XMC_EnableWriteTiming;         /*!< Enables or disables the extended mode.
+                                                 This parameter can be a value of @ref XMC_Extended_Mode */
+
+    uint32_t XMC_WriteBurstSyn;             /*!< Enables or disables the write burst operation.
+                                                 This parameter can be a value of @ref XMC_Write_Burst */
+
+    XMC_NORSRAMTimingInitType* XMC_RWTimingStruct;  /*!< Timing Parameters for write and read access if the  ExtendedMode is not used*/
+
+    XMC_NORSRAMTimingInitType* XMC_WTimingStruct;   /*!< Timing Parameters for write access if the  ExtendedMode is used*/
+} XMC_NORSRAMInitType;
+
+/**
+  * @brief  Timing parameters For XMC NAND and PCCARD Banks
+  */
+
+typedef struct
+{
+    uint32_t XMC_SetupTime;                 /*!< Defines the number of HCLK cycles to setup address before
+                                                 the command assertion for NAND-Flash read or write access
+                                                 to common/Attribute or I/O memory space (depending on
+                                                 the memory space timing to be configured).
+                                                 This parameter can be a value between 0 and 0xFF.*/
+
+    uint32_t XMC_OpTime;                    /*!< Defines the minimum number of HCLK cycles to assert the
+                                                 command for NAND-Flash read or write access to
+                                                 common/Attribute or I/O memory space (depending on the
+                                                 memory space timing to be configured).
+                                                 This parameter can be a number between 0x00 and 0xFF */
+
+    uint32_t XMC_HoldTime;                  /*!< Defines the number of HCLK clock cycles to hold address
+                                                 (and data for write access) after the command deassertion
+                                                 for NAND-Flash read or write access to common/Attribute
+                                                 or I/O memory space (depending on the memory space timing
+                                                 to be configured).
+                                                 This parameter can be a number between 0x00 and 0xFF */
+
+    uint32_t XMC_WriteSetupTime;            /*!< Defines the number of HCLK clock cycles during which the
+                                                 databus is kept in HiZ after the start of a NAND-Flash
+                                                 write access to common/Attribute or I/O memory space (depending
+                                                 on the memory space timing to be configured).
+                                                 This parameter can be a number between 0x00 and 0xFF */
+} XMC_NAND_PCCARDTimingInitType;
+
+/**
+  * @brief  XMC NAND Init structure definition
+  */
+
+typedef struct
+{
+    uint32_t XMC_Bank;                      /*!< Specifies the NAND memory bank that will be used.
+                                                 This parameter can be a value of @ref XMC_NAND_Bank */
+
+    uint32_t XMC_EnableWait;                /*!< Enables or disables the Wait feature for the NAND Memory Bank.
+                                                 This parameter can be any value of @ref XMC_Wait_feature */
+
+    uint32_t XMC_BusType;                   /*!< Specifies the external memory device width.
+                                                 This parameter can be any value of @ref XMC_Data_Width */
+
+    uint32_t XMC_EnableECC;                 /*!< Enables or disables the ECC computation.
+                                                 This parameter can be any value of @ref XMC_EnableECC */
+
+    uint32_t XMC_ECCPageSize;               /*!< Defines the page size for the extended ECC.
+                                                 This parameter can be any value of @ref XMC_ECC_Page_Size */
+
+    uint32_t XMC_DelayTimeCR;               /*!< Defines the number of HCLK cycles to configure the
+                                                 delay between CLE low and RE low.
+                                                 This parameter can be a value between 0 and 0xFF. */
+
+    uint32_t XMC_DelayTimeAR;               /*!< Defines the number of HCLK cycles to configure the
+                                                 delay between ALE low and RE low.
+                                                 This parameter can be a number between 0x0 and 0xFF */
+
+    XMC_NAND_PCCARDTimingInitType*  XMC_CommonSpaceTimingStruct;    /*!< XMC Common Space Timing */
+
+    XMC_NAND_PCCARDTimingInitType*  XMC_AttributeSpaceTimingStruct; /*!< XMC Attribute Space Timing */
+} XMC_NANDInitType;
+
+/**
+  * @brief  XMC PCCARD Init structure definition
+  */
+
+typedef struct
+{
+    uint32_t XMC_EnableWait;                /*!< Enables or disables the Wait feature for the Memory Bank.
+                                                 This parameter can be any value of @ref XMC_Wait_feature */
+
+    uint32_t XMC_DelayTimeCR;               /*!< Defines the number of HCLK cycles to configure the
+                                                 delay between CLE low and RE low.
+                                                 This parameter can be a value between 0 and 0xFF. */
+
+    uint32_t XMC_DelayTimeAR;               /*!< Defines the number of HCLK cycles to configure the
+                                                 delay between ALE low and RE low.
+                                                 This parameter can be a number between 0x0 and 0xFF */
+
+
+    XMC_NAND_PCCARDTimingInitType*  XMC_CommonSpaceTimingStruct; /*!< XMC Common Space Timing */
+
+    XMC_NAND_PCCARDTimingInitType*  XMC_AttributeSpaceTimingStruct;  /*!< XMC Attribute Space Timing */
+
+    XMC_NAND_PCCARDTimingInitType*  XMC_IOSpaceTimingStruct; /*!< XMC IO Space Timing */
+} XMC_PCCARDInitType;
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup XMC_NORSRAM_Bank
+  * @{
+  */
+#define XMC_Bank1_NORSRAM1                  ((uint32_t)0x00000000)
+#define XMC_Bank1_NORSRAM2                  ((uint32_t)0x00000002)
+#define XMC_Bank1_NORSRAM3                  ((uint32_t)0x00000004)
+#define XMC_Bank1_NORSRAM4                  ((uint32_t)0x00000006)
+/**
+  * @}
+  */
+
+/** @defgroup XMC_SubBank
+  * @{
+  */
+#define XMC_SubBank1_NORSRAM1                  ((uint32_t)0x00000000)
+#define XMC_SubBank1_NORSRAM2                  ((uint32_t)0x00000001)
+#define XMC_SubBank1_NORSRAM3                  ((uint32_t)0x00000002)
+#define XMC_SubBank1_NORSRAM4                  ((uint32_t)0x00000003)
+/**
+  * @}
+  */
+
+
+/** @defgroup XMC_NAND_Bank
+  * @{
+  */
+#define XMC_Bank2_NAND                      ((uint32_t)0x00000010)
+#define XMC_Bank3_NAND                      ((uint32_t)0x00000100)
+/**
+  * @}
+  */
+
+/** @defgroup XMC_PCCARD_Bank
+  * @{
+  */
+#define XMC_Bank4_PCCARD                    ((uint32_t)0x00001000)
+/**
+  * @}
+  */
+
+#define IS_XMC_Sub_NORSRAM_REGION(REGION)       (((REGION) == XMC_SubBank1_NORSRAM1) || \
+                                             ((REGION) == XMC_SubBank1_NORSRAM2) || \
+                                             ((REGION) == XMC_SubBank1_NORSRAM3) || \
+                                             ((REGION) == XMC_SubBank1_NORSRAM4))
+
+#define IS_XMC_NORSRAM_REGION(REGION)       (((REGION) == XMC_Bank1_NORSRAM1) || \
+                                             ((REGION) == XMC_Bank1_NORSRAM2) || \
+                                             ((REGION) == XMC_Bank1_NORSRAM3) || \
+                                             ((REGION) == XMC_Bank1_NORSRAM4))
+
+#define IS_XMC_NAND_BANK(BANK)              (((BANK) == XMC_Bank2_NAND) || \
+                                             ((BANK) == XMC_Bank3_NAND))
+
+#define IS_XMC_GETFLAG_BANK(BANK)           (((BANK) == XMC_Bank2_NAND) || \
+                                             ((BANK) == XMC_Bank3_NAND) || \
+                                             ((BANK) == XMC_Bank4_PCCARD))
+
+#define IS_XMC_INT_BANK(BANK)               (((BANK) == XMC_Bank2_NAND) || \
+                                             ((BANK) == XMC_Bank3_NAND) || \
+                                             ((BANK) == XMC_Bank4_PCCARD))
+
+/** @defgroup NOR_SRAM_Controller
+  * @{
+  */
+
+/** @defgroup XMC_Data_Address_Bus_Multiplexing
+  * @{
+  */
+
+#define XMC_DataAdrMux_Disable              ((uint32_t)0x00000000)
+#define XMC_DataAdrMux_Enable               ((uint32_t)0x00000002)
+#define IS_XMC_MUX(MUX)                     (((MUX) == XMC_DataAdrMux_Disable) || \
+                                             ((MUX) == XMC_DataAdrMux_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Memory_Type
+  * @{
+  */
+
+#define XMC_Dev_SRAM                        ((uint32_t)0x00000000)
+#define XMC_Dev_PSRAM                       ((uint32_t)0x00000004)
+#define XMC_Dev_NOR                         ((uint32_t)0x00000008)
+#define IS_XMC_DEVICE(DEVICE)               (((DEVICE) == XMC_Dev_SRAM) || \
+                                             ((DEVICE) == XMC_Dev_PSRAM)|| \
+                                             ((DEVICE) == XMC_Dev_NOR))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Data_Width
+  * @{
+  */
+
+#define XMC_BusType_8b                      ((uint32_t)0x00000000)
+#define XMC_BusType_16b                     ((uint32_t)0x00000010)
+#define IS_XMC_BUS_TYPE(TYPE)               (((TYPE) == XMC_BusType_8b) || \
+                                             ((TYPE) == XMC_BusType_16b))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Burst_Access_Mode
+  * @{
+  */
+
+#define XMC_BurstMode_Disable               ((uint32_t)0x00000000)
+#define XMC_BurstMode_Enable                ((uint32_t)0x00000100)
+#define IS_XMC_BURSTMODE(STATE)             (((STATE) == XMC_BurstMode_Disable) || \
+                                             ((STATE) == XMC_BurstMode_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup XMC_AsynchronousWait
+  * @{
+  */
+#define XMC_AsynWait_Disable                ((uint32_t)0x00000000)
+#define XMC_AsynWait_Enable                 ((uint32_t)0x00008000)
+#define IS_XMC_ASYNWAIT(STATE)              (((STATE) == XMC_AsynWait_Disable) || \
+                                             ((STATE) == XMC_AsynWait_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Wait_Signal_Polarity
+  * @{
+  */
+
+#define XMC_WaitSignalLv_Low                ((uint32_t)0x00000000)
+#define XMC_WaitSignalLv_High               ((uint32_t)0x00000200)
+#define IS_XMC_WAIT_SIGNAL_LEVEL(LEVEL)     (((LEVEL) == XMC_WaitSignalLv_Low) || \
+                                             ((LEVEL) == XMC_WaitSignalLv_High))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Wrap_Mode
+  * @{
+  */
+
+#define XMC_BurstModeSplit_Disable          ((uint32_t)0x00000000)
+#define XMC_BurstModeSplit_Enable           ((uint32_t)0x00000400)
+#define IS_XMC_BURSTMODE_SPLIT(MODE)        (((MODE) == XMC_BurstModeSplit_Disable) || \
+                                             ((MODE) == XMC_BurstModeSplit_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Wait_Timing
+  * @{
+  */
+
+#define XMC_WaitSignalConfig_BeforeWaitState        ((uint32_t)0x00000000)
+#define XMC_WaitSignalConfig_DuringWaitState        ((uint32_t)0x00000800)
+#define IS_XMC_WAIT_SIGNAL_CONFIG(CONFIG)           (((CONFIG) == XMC_WaitSignalConfig_BeforeWaitState) || \
+                                                     ((CONFIG) == XMC_WaitSignalConfig_DuringWaitState))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Write_Operation
+  * @{
+  */
+
+#define XMC_WriteOperation_Disable          ((uint32_t)0x00000000)
+#define XMC_WriteOperation_Enable           ((uint32_t)0x00001000)
+#define IS_XMC_WRITE_OPERATION(OPERATION)   (((OPERATION) == XMC_WriteOperation_Disable) || \
+                                             ((OPERATION) == XMC_WriteOperation_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Wait_Signal
+  * @{
+  */
+
+#define XMC_WaitSignal_Disable              ((uint32_t)0x00000000)
+#define XMC_WaitSignal_Enable               ((uint32_t)0x00002000)
+#define IS_XMC_WAIT_SIGNAL(SIGNAL)          (((SIGNAL) == XMC_WaitSignal_Disable) || \
+                                             ((SIGNAL) == XMC_WaitSignal_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Extended_Mode
+  * @{
+  */
+
+#define XMC_WriteTiming_Disable             ((uint32_t)0x00000000)
+#define XMC_WriteTiming_Enable              ((uint32_t)0x00004000)
+
+#define IS_XMC_WRITE_TIMING(STATE)          (((STATE) == XMC_WriteTiming_Disable) || \
+                                             ((STATE) == XMC_WriteTiming_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Write_Burst
+  * @{
+  */
+
+#define XMC_WriteBurstSyn_Disable           ((uint32_t)0x00000000)
+#define XMC_WriteBurstSyn_Enable            ((uint32_t)0x00080000)
+#define IS_XMC_WRITE_BURST_SYN(SYN)         (((SYN) == XMC_WriteBurstSyn_Disable) || \
+                                             ((SYN) == XMC_WriteBurstSyn_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Address_Setup_Time
+  * @{
+  */
+
+#define IS_XMC_ADDRESS_OP_TIME(TIME)        ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Address_Hold_Time
+  * @{
+  */
+
+#define IS_XMC_ADDRESS_HOLD_TIME(TIME)      ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Data_Setup_Time
+  * @{
+  */
+
+#define IS_XMC_DATA_OP_TIME(TIME)           (((TIME) > 0) && ((TIME) <= 0xFF))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Bus_Turn_around_Duration
+  * @{
+  */
+
+#define IS_XMC_INTERVAL_BETWEEN_OP_TIME(TIME)       ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_CLK_Division
+  * @{
+  */
+
+#define IS_XMC_CLK_DIV(DIV)                 ((DIV) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Data_Latency
+  * @{
+  */
+
+#define IS_XMC_DATA_STABLE_TIME(TIME)       ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Access_Mode
+  * @{
+  */
+
+#define XMC_Mode_A                          ((uint32_t)0x00000000)
+#define XMC_Mode_B                          ((uint32_t)0x10000000)
+#define XMC_Mode_C                          ((uint32_t)0x20000000)
+#define XMC_Mode_D                          ((uint32_t)0x30000000)
+#define IS_XMC_MODE(MODE)                   (((MODE) == XMC_Mode_A) || \
+                                             ((MODE) == XMC_Mode_B) || \
+                                             ((MODE) == XMC_Mode_C) || \
+                                             ((MODE) == XMC_Mode_D))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup NAND_PCCARD_Controller
+  * @{
+  */
+
+/** @defgroup XMC_Wait_feature
+  * @{
+  */
+
+#define XMC_WaitOperation_Disable           ((uint32_t)0x00000000)
+#define XMC_WaitOperation_Enable            ((uint32_t)0x00000002)
+#define IS_XMC_WAIT_OPERATION(OPERATION)    (((OPERATION) == XMC_WaitOperation_Disable) || \
+                                             ((OPERATION) == XMC_WaitOperation_Enable))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup XMC_EnableECC
+  * @{
+  */
+
+#define XMC_ECCOperation_Disable            ((uint32_t)0x00000000)
+#define XMC_ECCOperation_Enable             ((uint32_t)0x00000040)
+#define IS_XMC_ECC_OPERATION(OPERATION)     (((OPERATION) == XMC_ECCOperation_Disable) || \
+                                             ((OPERATION) == XMC_ECCOperation_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_ECC_Page_Size
+  * @{
+  */
+
+#define XMC_ECCPageSize_256Bytes            ((uint32_t)0x00000000)
+#define XMC_ECCPageSize_512Bytes            ((uint32_t)0x00020000)
+#define XMC_ECCPageSize_1024Bytes           ((uint32_t)0x00040000)
+#define XMC_ECCPageSize_2048Bytes           ((uint32_t)0x00060000)
+#define XMC_ECCPageSize_4096Bytes           ((uint32_t)0x00080000)
+#define XMC_ECCPageSize_8192Bytes           ((uint32_t)0x000A0000)
+#define IS_XMC_ECCPAGE_SIZE(SIZE)           (((SIZE) == XMC_ECCPageSize_256Bytes) || \
+                                             ((SIZE) == XMC_ECCPageSize_512Bytes) || \
+                                             ((SIZE) == XMC_ECCPageSize_1024Bytes) || \
+                                             ((SIZE) == XMC_ECCPageSize_2048Bytes) || \
+                                             ((SIZE) == XMC_ECCPageSize_4096Bytes) || \
+                                             ((SIZE) == XMC_ECCPageSize_8192Bytes))
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_TCLR_Setup_Time
+  * @{
+  */
+
+#define IS_XMC_DELAY_CR_TIME(TIME)          ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_TAR_Setup_Time
+  * @{
+  */
+
+#define IS_XMC_DELAY_AR_TIME(TIME)          ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Setup_Time
+  * @{
+  */
+
+#define IS_XMC_SETUP_TIME(TIME)             ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Wait_Setup_Time
+  * @{
+  */
+
+#define IS_XMC_OP_TIME(TIME)                ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Hold_Setup_Time
+  * @{
+  */
+
+#define IS_XMC_HOLD_TIME(TIME)              ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_HiZ_Setup_Time
+  * @{
+  */
+
+#define IS_XMC_WRITE_SETUP_TIME(TIME)       ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Interrupt_sources
+  * @{
+  */
+
+#define XMC_INT_RisingEdge                  ((uint32_t)0x00000008)
+#define XMC_INT_Level                       ((uint32_t)0x00000010)
+#define XMC_INT_FallingEdge                 ((uint32_t)0x00000020)
+#define IS_XMC_INT(INT)                     ((((INT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((INT) != 0x00000000))
+#define IS_XMC_GET_INT(INT)                 (((INT) == XMC_INT_RisingEdge) || \
+                                             ((INT) == XMC_INT_Level) || \
+                                             ((INT) == XMC_INT_FallingEdge))
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Flags
+  * @{
+  */
+
+#define XMC_FLAG_RisingEdge                 ((uint32_t)0x00000001)
+#define XMC_FLAG_Level                      ((uint32_t)0x00000002)
+#define XMC_FLAG_FallingEdge                ((uint32_t)0x00000004)
+#define XMC_FLAG_FEMPT                      ((uint32_t)0x00000040)
+#define IS_XMC_GET_FLAG(FLAG)               (((FLAG) == XMC_FLAG_RisingEdge) || \
+                                             ((FLAG) == XMC_FLAG_Level) || \
+                                             ((FLAG) == XMC_FLAG_FallingEdge) || \
+                                             ((FLAG) == XMC_FLAG_FEMPT))
+
+#define IS_XMC_CLEAR_FLAG(FLAG)             ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Exported_Functions
+  * @{
+  */
+  
+void XMC_ExtTimingConfig(uint32_t XMC_SubBank, uint8_t W2W_Timing, uint8_t R2R_Timing);
+void XMC_NORSRAMReset(uint32_t XMC_Bank);
+void XMC_NANDReset(uint32_t XMC_Bank);
+void XMC_PCCARDReset(void);
+void XMC_NORSRAMInit(XMC_NORSRAMInitType* XMC_NORSRAMInitStruct);
+void XMC_NANDInit(XMC_NANDInitType* XMC_NANDInitStruct);
+void XMC_PCCARDInit(XMC_PCCARDInitType* XMC_PCCARDInitStruct);
+void XMC_NORSRAMStructInit(XMC_NORSRAMInitType* XMC_NORSRAMInitStruct);
+void XMC_NANDStructInit(XMC_NANDInitType* XMC_NANDInitStruct);
+void XMC_PCCARDStructInit(XMC_PCCARDInitType* XMC_PCCARDInitStruct);
+void XMC_NORSRAMCmd(uint32_t XMC_Bank, FunctionalState NewState);
+void XMC_NANDCmd(uint32_t XMC_Bank, FunctionalState NewState);
+void XMC_PCCARDCmd(FunctionalState NewState);
+void XMC_NANDECCCmd(uint32_t XMC_Bank, FunctionalState NewState);
+uint32_t XMC_GetECC(uint32_t XMC_Bank);
+void XMC_INTConfig(uint32_t XMC_Bank, uint32_t XMC_INT, FunctionalState NewState);
+FlagStatus XMC_GetFlagStatus(uint32_t XMC_Bank, uint32_t XMC_FLAG);
+void XMC_ClearFlag(uint32_t XMC_Bank, uint32_t XMC_FLAG);
+ITStatus XMC_GetINTStatus(uint32_t XMC_Bank, uint32_t XMC_INT);
+void XMC_ClearINTPendingBit(uint32_t XMC_Bank, uint32_t XMC_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__AT32F4xx_XMC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/misc.h

@@ -0,0 +1,219 @@
+/*
+ **************************************************************************
+ * Copyright (C) 2016 by ARTERY Technology Co., Ltd. All Rights Reserved.
+ **************************************************************************
+ * THIS SOURCE FILE IS DISTRIBUTED IN THE HOPE THAT CAN REDUCE EFFORTS AND
+ * TIME, BUT WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ **************************************************************************
+ * File Name    : misc.h
+ * Description  : at32f4xx MISC header file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H
+#define __MISC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup MISC
+  * @{
+  */
+
+/** @defgroup MISC_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  NVIC Init Structure definition
+  */
+
+typedef struct
+{
+    uint8_t NVIC_IRQChannel;                        /*!< Specifies the IRQ channel to be enabled or disabled.
+                                                       This parameter can be a value of @ref IRQn_Type
+                                                       (For the complete AT32 Devices IRQ Channels list, please
+                                                        refer to at32f4xx.h file) */
+
+    uint8_t NVIC_IRQChannelPreemptionPriority;      /*!< Specifies the pre-emption priority for the IRQ channel
+                                                       specified in NVIC_IRQChannel. This parameter can be a value
+                                                       between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+    uint8_t NVIC_IRQChannelSubPriority;             /*!< Specifies the subpriority level for the IRQ channel specified
+                                                       in NVIC_IRQChannel. This parameter can be a value
+                                                       between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+    FunctionalState NVIC_IRQChannelCmd;             /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                                       will be enabled or disabled.
+                                                       This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitType;
+
+/**
+  * @}
+  */
+
+/** @defgroup NVIC_Priority_Table
+  * @{
+  */
+
+/**
+@code
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+  ============================================================================================================================
+    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
+  ============================================================================================================================
+   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
+                         |                                   |                             |   4 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
+                         |                                   |                             |   3 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
+                         |                                   |                             |   2 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
+                         |                                   |                             |   1 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
+                         |                                   |                             |   0 bits for subpriority
+  ============================================================================================================================
+@endcode
+*/
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Vector_Table_Base
+  * @{
+  */
+
+#define NVIC_VectTab_RAM                    ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH                  ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB)            (((VECTTAB) == NVIC_VectTab_RAM) || \
+                                             ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+  * @}
+  */
+
+/** @defgroup System_Low_Power
+  * @{
+  */
+
+#define NVIC_LP_SEVONPEND                   ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP                   ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT                 ((uint8_t)0x02)
+#define IS_NVIC_LP(LP)                      (((LP) == NVIC_LP_SEVONPEND) || \
+                                             ((LP) == NVIC_LP_SLEEPDEEP) || \
+                                             ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+  * @}
+  */
+
+/** @defgroup Preemption_Priority_Group
+  * @{
+  */
+
+#define NVIC_PriorityGroup_0                ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+                                                                   4 bits for subpriority */
+#define NVIC_PriorityGroup_1                ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+                                                                   3 bits for subpriority */
+#define NVIC_PriorityGroup_2                ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+                                                                   2 bits for subpriority */
+#define NVIC_PriorityGroup_3                ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+                                                                   1 bits for subpriority */
+#define NVIC_PriorityGroup_4                ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+                                                                   0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP)       (((GROUP) == NVIC_PriorityGroup_0) || \
+                                             ((GROUP) == NVIC_PriorityGroup_1) || \
+                                             ((GROUP) == NVIC_PriorityGroup_2) || \
+                                             ((GROUP) == NVIC_PriorityGroup_3) || \
+                                             ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)       ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)              ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET)                      ((OFFSET) < 0x000FFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup SysTick_clock_source
+  * @{
+  */
+
+#define SysTick_CLKSource_HCLK_Div8         ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK              ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE)       (((SOURCE) == SysTick_CLKSource_HCLK) || \
+                                             ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Functions
+  * @{
+  */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitType* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_acc.c

@@ -0,0 +1,238 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_acc.c
+ * Description  : at32f4xx ACC source file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_acc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup ACC
+  * @brief ACC driver modules
+  * @{
+  */
+#if defined (AT32F413xx) || defined (AT32F415xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+
+/** @defgroup ACC_Private_Functions
+  * @{
+  */
+  
+/**
+  * @brief  Stores Calibration Step data in ACC's CTRL1 register.
+  * @param  StepValue:  value to be stored in the ACC's CTRL1 register 					
+  * @retval None
+  */
+void ACC_SetStep(uint8_t StepValue)
+{
+  ACC->CTRL1 |= StepValue<<8;
+}
+
+/**
+  * @brief  Enables the specified ACC Calibration.
+  * @param  ACC_CAL: specifies the ACC CAL sources.
+  *   This parameter can be one of the following values:
+  *     @arg ACC_CAL_HSICAL:  Calibration HSICAL
+  *     @arg ACC_CAL_HSITRIM:  Calibration HSITRIM
+  * @retval None
+  */
+void ACC_CAL_Choose(uint16_t ACC_CAL)
+{
+  ACC->CTRL1 &= ~0x2;
+  
+  ACC->CTRL1 |= ACC_CAL;
+  
+}
+
+/**
+  * @brief  Enables or disables the specified ACC interrupts.
+  * @param  ACC_IT: specifies the ACC interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg ACC_IT_CALRDYIEN:  CALRDY interrupt enable
+  *     @arg ACC_IT_EIEN:  RSLOST error interrupt enable
+  * @param  NewState: new state of the specified ACC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ACC_ITConfig(uint16_t ACC_IT, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    ACC->CTRL1  |= ACC_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    ACC->CTRL1 &= (uint16_t)~ACC_IT;
+  }
+}
+
+/**
+  * @brief  Enters the ACC Calibration mode.
+  * @param  ACC_IT: specifies the ACC interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg ACC_CAL_ON:  CALRDY interrupt enable
+  *     @arg ACC_TRIM_ON:  RSLOST error interrupt enable
+  * @param  NewState: new state of the specified ACC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ACC_EnterCALMode(uint16_t ACC_ON, FunctionalState NewState)
+{
+  ACC->CTRL1 |= ACC_ON;
+}
+/**
+  * @brief  Exits from the ACC Calibration mode.
+  * @param  None
+  * @retval None
+  */
+void ACC_ExitCALMode(void)
+{
+  ACC->CTRL1 &= ~ACC_CAL_Enable;
+}
+
+/**
+  * @brief  Checks whether the specified ACC flag is set or not.
+  * @param  ACC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ACC_FLAG_RSLOST:  Reference Signal Lost
+  *     @arg ACC_FLAG_CALRDY:  Internal high-speed clock calibration ready
+  * @retval The new state of ACC_FLAG (SET or RESET).
+  */
+FlagStatus ACC_GetFlagStatus(uint16_t ACC_FLAG)
+{
+  FlagStatus bitstatus = RESET;  
+  
+  if ((ACC->STS & ACC_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Wtire the value to  ACC C1 register.
+  * @param  ACC_C1_Value
+  * @retval none.
+  */
+void ACC_WriteC1(uint16_t ACC_C1_Value)
+{
+  ACC->C1 = ACC_C1_Value;
+}
+
+/**
+  * @brief  Wtire the value to  ACC C2 register.
+  * @param  ACC_C2_Value
+  * @retval none.
+  */
+void ACC_WriteC2(uint16_t ACC_C2_Value)
+{
+  ACC->C2 = ACC_C2_Value;
+}
+/**
+  * @brief  Wtire the value to  ACC C3 register.
+  * @param  ACC_C3_Value
+  * @retval none.
+  */
+void ACC_WriteC3(uint16_t ACC_C3_Value)
+{
+  ACC->C3 = ACC_C3_Value;
+}
+
+/**
+  * @brief  Returns the current ACC HSITRIM value.
+  * @param  None
+  * @retval 8-bit HSITRIM value.
+  */
+uint8_t ACC_GetHSITRIM(void)
+{
+  return ((uint8_t)((ACC->CTRL2)>>8));
+}
+
+
+/**
+  * @brief  Returns the current ACC HSICAL value.
+  * @param  None
+  * @retval 8-bit HSITRIM value.
+  */
+uint8_t ACC_GetHSICAL(void)
+{
+  return ((uint8_t)(ACC->CTRL2));
+}
+
+/**
+  * @brief  Returns the current ACC C1 value.
+  * @param  None
+  * @retval 16-bit C1 value.
+  */
+uint16_t ACC_ReadC1(void)
+{
+  return ((uint16_t)(ACC->C1));
+}
+
+/**
+  * @brief  Returns the current ACC C2 value.
+  * @param  None
+  * @retval 16-bit C2 value.
+  */
+uint16_t ACC_ReadC2(void)
+{
+  return ((uint16_t)(ACC->C2));
+}
+/**
+  * @brief  Returns the current ACC C3 value.
+  * @param  None
+  * @retval 16-bit C3 value.
+  */
+uint16_t ACC_ReadC3(void)
+{
+  return ((uint16_t)(ACC->C3));
+}
+
+/**
+  * @brief  Checks whether the specified ACC flag is set or not.
+  * @param  ACC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ACC_FLAG_RSLOST:  Reference Signal Lost
+  *     @arg ACC_FLAG_CALRDY:  Internal high-speed clock calibration ready
+  * @retval None.
+  */
+void ACC_ClearFlag(uint16_t ACC_FLAG)            
+{
+  if(ACC_FLAG == ACC_FLAG_CALRDY)
+  {
+    ACC->STS &= ~1;
+  }
+  
+  if(ACC_FLAG == ACC_FLAG_RSLOST)
+  {
+    ACC->STS &= ~2;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* AT32F413xx || AT32F415xx || AT32F403Axx || AT32F407xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_adc.c

@@ -0,0 +1,1331 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_adc.c
+ * Description  : at32f4xx ADC source file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_adc.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup ADC
+  * @brief ADC driver modules
+  * @{
+  */
+
+/** @defgroup ADC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Defines
+  * @{
+  */
+
+/* ADC DISCNUM mask */
+#define CTRL1_DISCNUM_Reset         ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISCEN mask */
+#define CTRL1_RDISCEN_Set           ((uint32_t)0x00000800)
+#define CTRL1_RDISCEN_Rst           ((uint32_t)0xFFFFF7FF)
+
+/* ADC JAUTO mask */
+#define CTRL1_JAUT_Set              ((uint32_t)0x00000400)
+#define CTRL1_JAUT_Rst              ((uint32_t)0xFFFFFBFF)
+
+/* ADC JDISCEN mask */
+#define CTRL1_JDISCEN_Set           ((uint32_t)0x00001000)
+#define CTRL1_JDISCEN_Rst           ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDCH mask */
+#define CTRL1_AWDCH_Rst             ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CTRL1_AWDMode_Rst           ((uint32_t)0xFF3FFDFF)
+
+/* CTRL1 register Mask */
+#define CTRL1_CLEAR_MASK            ((uint32_t)0xFFF0FEFF)
+
+/* ADC ADON mask */
+#define CTRL2_ADON_Set              ((uint32_t)0x00000001)
+#define CTRL2_ADON_Rst              ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CTRL2_DMA_Set               ((uint32_t)0x00000100)
+#define CTRL2_DMA_Rst               ((uint32_t)0xFFFFFEFF)
+
+/* ADC RSTCAL mask */
+#define CTRL2_RSTCAL_Set            ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CTRL2_CAL_Set               ((uint32_t)0x00000004)
+
+/* ADC SWSTART mask */
+#define CTRL2_SWSTR_Set             ((uint32_t)0x00400000)
+
+/* ADC EXTTRIG mask */
+#define CTRL2_EXTTRIG_Set           ((uint32_t)0x00100000)
+#define CTRL2_EXTTRIG_Rst           ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CTRL2_EXTTRIG_SWSTR_Set     ((uint32_t)0x00500000)
+#define CTRL2_EXTTRIG_SWSTR_Rst     ((uint32_t)0xFFAFFFFF)
+
+/* ADC JEXTSEL mask */
+#define CTRL2_JEXTSEL_Rst           ((uint32_t)0xFEFF8FFF)
+
+/* ADC JEXTTRIG mask */
+#define CTRL2_JEXTTRIG_Set          ((uint32_t)0x00008000)
+#define CTRL2_JEXTTRIG_Rst          ((uint32_t)0xFFFF7FFF)
+
+/* ADC JSWSTART mask */
+#define CTRL2_JSWSTR_Set            ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CTRL2_JEXTTRIG_JSWSTR_Set   ((uint32_t)0x00208000)
+#define CTRL2_JEXTTRIG_JSWSTR_Rst   ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CTRL2_TSVREFE_Set           ((uint32_t)0x00800000)
+#define CTRL2_TSVREFE_Rst           ((uint32_t)0xFF7FFFFF)
+
+/* CTRL2 register Mask */
+#define CTRL2_CLEAR_Msk             ((uint32_t)0xFDF1F7FD)
+
+/* ADC SQx mask */
+#define RSQ3_SQ_Set                 ((uint32_t)0x0000001F)
+#define RSQ2_SQ_Set                 ((uint32_t)0x0000001F)
+#define RSQ1_SQ_Set                 ((uint32_t)0x0000001F)
+
+/* SQR1 register Mask */
+#define RSQ1_CLEAR_Msk              ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define JSQR_JSQ_Set                ((uint32_t)0x0000001F)
+
+/* ADC JL mask */
+#define JSQR_JLEN_Set               ((uint32_t)0x00300000)
+#define JSQR_JLEN_Rst               ((uint32_t)0xFFCFFFFF)
+
+/* ADC SMPx mask */
+#define SMPT1_SMP_Set               ((uint32_t)0x00000007)
+#define SMPT2_SMP_Set               ((uint32_t)0x00000007)
+
+/* ADC JDRx registers offset */
+#define JDOR_Offset                 ((uint8_t)0x28)
+
+/* ADC1 DR register base address */
+#define DOR_ADDRESS                 ((uint32_t)0x4001244C)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the ADCx peripheral registers to their default reset values.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_Reset(ADC_Type* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  if (ADCx == ADC1)
+  {
+    /* Enable ADC1 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_ADC1, ENABLE);
+    /* Release ADC1 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_ADC1, DISABLE);
+  }
+  else if (ADCx == ADC2)
+  {
+    /* Enable ADC2 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_ADC2, ENABLE);
+    /* Release ADC2 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_ADC2, DISABLE);
+  }
+#ifdef AT32F403xx
+  else if (ADCx == ADC3)
+  {
+    /* Enable ADC3 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_ADC3, ENABLE);
+    /* Release ADC3 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_ADC3, DISABLE);
+  }
+#endif
+}
+
+/**
+  * @brief  Initializes the ADCx peripheral according to the specified parameters
+  *         in the ADC_InitStruct.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_InitStruct: pointer to an ADC_InitType structure that contains
+  *         the configuration information for the specified ADC peripheral.
+  * @retval None
+  */
+void ADC_Init(ADC_Type* ADCx, ADC_InitType* ADC_InitStruct)
+{
+  uint32_t tmpreg1 = 0;
+  uint8_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanMode));
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousMode));
+  assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrig));
+  assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
+  assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NumOfChannel));
+
+  /*---------------------------- ADCx CTRL1 Configuration -----------------*/
+  /* Get the ADCx CTRL1 value */
+  tmpreg1 = ADCx->CTRL1;
+  /* Clear DUALMOD and SCAN bits */
+  tmpreg1 &= CTRL1_CLEAR_MASK;
+  /* Configure ADCx: Dual mode and scan conversion mode */
+  /* Set DUALMOD bits according to ADC_Mode value */
+  /* Set SCAN bit according to ADC_ScanConvMode value */
+  tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanMode << 8));
+  /* Write to ADCx CTRL1 */
+  ADCx->CTRL1 = tmpreg1;
+
+  /*---------------------------- ADCx CTRL2 Configuration -----------------*/
+  /* Get the ADCx CTRL2 value */
+  tmpreg1 = ADCx->CTRL2;
+  /* Clear CONT, ALIGN and EXTSEL bits */
+  tmpreg1 &= CTRL2_CLEAR_Msk;
+  /* Configure ADCx: external trigger event and continuous conversion mode */
+  /* Set ALIGN bit according to ADC_DataAlign value */
+  /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
+  /* Set CONT bit according to ADC_ContinuousConvMode value */
+  tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrig |
+                        ((uint32_t)ADC_InitStruct->ADC_ContinuousMode << 1));
+  /* Write to ADCx CTRL2 */
+  ADCx->CTRL2 = tmpreg1;
+
+  /*---------------------------- ADCx SQR1 Configuration -----------------*/
+  /* Get the ADCx SQR1 value */
+  tmpreg1 = ADCx->RSQ1;
+  /* Clear L bits */
+  tmpreg1 &= RSQ1_CLEAR_Msk;
+  /* Configure ADCx: regular channel sequence length */
+  /* Set L bits according to ADC_NbrOfChannel value */
+  tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NumOfChannel - (uint8_t)1);
+  tmpreg1 |= (uint32_t)tmpreg2 << 20;
+  /* Write to ADCx SQR1 */
+  ADCx->RSQ1 = tmpreg1;
+}
+
+/**
+  * @brief  Fills each ADC_InitStruct member with its default value.
+  * @param  ADC_InitStruct : pointer to an ADC_InitType structure which will be initialized.
+  * @retval None
+  */
+void ADC_StructInit(ADC_InitType* ADC_InitStruct)
+{
+  /* Reset ADC init structure parameters values */
+  /* Initialize the ADC_Mode member */
+  ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
+  /* initialize the ADC_ScanConvMode member */
+  ADC_InitStruct->ADC_ScanMode = DISABLE;
+  /* Initialize the ADC_ContinuousConvMode member */
+  ADC_InitStruct->ADC_ContinuousMode = DISABLE;
+  /* Initialize the ADC_ExternalTrigConv member */
+  ADC_InitStruct->ADC_ExternalTrig = ADC_ExternalTrig_TMR1_CC1_ADC12;
+  /* Initialize the ADC_DataAlign member */
+  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+  /* Initialize the ADC_NbrOfChannel member */
+  ADC_InitStruct->ADC_NumOfChannel = 1;
+}
+
+/**
+  * @brief  Enables or disables the specified ADC peripheral.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the ADCx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_Ctrl(ADC_Type* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the ADON bit to wake up the ADC from power down mode */
+    ADCx->CTRL2 |= CTRL2_ADON_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC peripheral */
+    ADCx->CTRL2 &= CTRL2_ADON_Rst;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified ADC DMA request.
+  * @param  ADCx: where x can be 1 or 3 to select the ADC peripheral.
+  *   Note: ADC2 hasn't a DMA capability.
+  * @param  NewState: new state of the selected ADC DMA transfer.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DMACtrl(ADC_Type* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_DMA_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC DMA request */
+    ADCx->CTRL2 |= CTRL2_DMA_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC DMA request */
+    ADCx->CTRL2 &= CTRL2_DMA_Rst;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified ADC interrupts.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_INT: specifies the ADC interrupt sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg ADC_INT_EC: End of conversion interrupt mask
+  *     @arg ADC_INT_AWD: Analog watchdog interrupt mask
+  *     @arg ADC_INT_JEC: End of injected conversion interrupt mask
+  * @param  NewState: new state of the specified ADC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_INTConfig(ADC_Type* ADCx, uint16_t ADC_INT, FunctionalState NewState)
+{
+  uint8_t itmask = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_ADC_INT(ADC_INT));
+  /* Get the ADC INT index */
+  itmask = (uint8_t)ADC_INT;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC interrupts */
+    ADCx->CTRL1 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected ADC interrupts */
+    ADCx->CTRL1 &= (~(uint32_t)itmask);
+  }
+}
+
+/**
+  * @brief  Resets the selected ADC calibration registers.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_RstCalibration(ADC_Type* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Resets the selected ADC calibration registers */
+  ADCx->CTRL2 |= CTRL2_RSTCAL_Set;
+}
+
+/**
+  * @brief  Gets the selected ADC reset calibration registers status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC reset calibration registers (SET or RESET).
+  */
+FlagStatus ADC_GetResetCalibrationStatus(ADC_Type* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  /* Check the status of RSTCAL bit */
+  if ((ADCx->CTRL2 & CTRL2_RSTCAL_Set) != (uint32_t)RESET)
+  {
+    /* RSTCAL bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* RSTCAL bit is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the RSTCAL bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Starts the selected ADC calibration process.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_StartCalibration(ADC_Type* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Enable the selected ADC calibration process */
+  ADCx->CTRL2 |= CTRL2_CAL_Set;
+}
+
+/**
+  * @brief  Gets the selected ADC calibration status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC calibration (SET or RESET).
+  */
+FlagStatus ADC_GetCalibrationStatus(ADC_Type* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  /* Check the status of CAL bit */
+  if ((ADCx->CTRL2 & CTRL2_CAL_Set) != (uint32_t)RESET)
+  {
+    /* CAL bit is set: calibration on going */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CAL bit is reset: end of calibration */
+    bitstatus = RESET;
+  }
+
+  /* Return the CAL bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Enables or disables the selected ADC software start conversion .
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC software start conversion.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_SoftwareStartConvCtrl(ADC_Type* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC conversion on external event and start the selected
+       ADC conversion */
+    ADCx->CTRL2 |= CTRL2_EXTTRIG_SWSTR_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC conversion on external event and stop the selected
+       ADC conversion */
+    ADCx->CTRL2 &= CTRL2_EXTTRIG_SWSTR_Rst;
+  }
+}
+
+/**
+  * @brief  Gets the selected ADC Software start conversion Status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC software start conversion (SET or RESET).
+  */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Type* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  /* Check the status of SWSTART bit */
+  if ((ADCx->CTRL2 & CTRL2_SWSTR_Set) != (uint32_t)RESET)
+  {
+    /* SWSTART bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SWSTART bit is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the SWSTART bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Configures the discontinuous mode for the selected ADC regular
+  *         group channel.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  Number: specifies the discontinuous mode regular channel
+  *         count value. This number must be between 1 and 8.
+  * @retval None
+  */
+void ADC_DiscModeChannelCountConfig(ADC_Type* ADCx, uint8_t Number)
+{
+  uint32_t tmpreg1 = 0;
+  uint32_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
+  /* Get the old register value */
+  tmpreg1 = ADCx->CTRL1;
+  /* Clear the old discontinuous mode channel count */
+  tmpreg1 &= CTRL1_DISCNUM_Reset;
+  /* Set the discontinuous mode channel count */
+  tmpreg2 = Number - 1;
+  tmpreg1 |= tmpreg2 << 13;
+  /* Store the new register value */
+  ADCx->CTRL1 = tmpreg1;
+}
+
+/**
+  * @brief  Enables or disables the discontinuous mode on regular group
+  *         channel for the specified ADC
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC discontinuous mode
+  *         on regular group channel.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DiscModeCtrl(ADC_Type* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC regular discontinuous mode */
+    ADCx->CTRL1 |= CTRL1_RDISCEN_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC regular discontinuous mode */
+    ADCx->CTRL1 &= CTRL1_RDISCEN_Rst;
+  }
+}
+
+/**
+  * @brief  Configures for the selected ADC regular channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_Channel_0: ADC Channel0 selected
+  *     @arg ADC_Channel_1: ADC Channel1 selected
+  *     @arg ADC_Channel_2: ADC Channel2 selected
+  *     @arg ADC_Channel_3: ADC Channel3 selected
+  *     @arg ADC_Channel_4: ADC Channel4 selected
+  *     @arg ADC_Channel_5: ADC Channel5 selected
+  *     @arg ADC_Channel_6: ADC Channel6 selected
+  *     @arg ADC_Channel_7: ADC Channel7 selected
+  *     @arg ADC_Channel_8: ADC Channel8 selected
+  *     @arg ADC_Channel_9: ADC Channel9 selected
+  *     @arg ADC_Channel_10: ADC Channel10 selected
+  *     @arg ADC_Channel_11: ADC Channel11 selected
+  *     @arg ADC_Channel_12: ADC Channel12 selected
+  *     @arg ADC_Channel_13: ADC Channel13 selected
+  *     @arg ADC_Channel_14: ADC Channel14 selected
+  *     @arg ADC_Channel_15: ADC Channel15 selected
+  *     @arg ADC_Channel_16: ADC Channel16 selected
+  *     @arg ADC_Channel_17: ADC Channel17 selected
+  * @param  Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.
+  * @param  ADC_SampleTime: The sample time value to be set for the selected channel.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_SampleTime_1_5: Sample time equal to 1.5 cycles
+  *     @arg ADC_SampleTime_7_5: Sample time equal to 7.5 cycles
+  *     @arg ADC_SampleTime_13_5: Sample time equal to 13.5 cycles
+  *     @arg ADC_SampleTime_28_5: Sample time equal to 28.5 cycles
+  *     @arg ADC_SampleTime_41_5: Sample time equal to 41.5 cycles
+  *     @arg ADC_SampleTime_55_5: Sample time equal to 55.5 cycles
+  *     @arg ADC_SampleTime_71_5: Sample time equal to 71.5 cycles
+  *     @arg ADC_SampleTime_239_5: Sample time equal to 239.5 cycles
+  * @retval None
+  */
+void ADC_RegularChannelConfig(ADC_Type* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  assert_param(IS_ADC_REGULAR_RANK(Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+
+  /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+  if (ADC_Channel > ADC_Channel_9)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPT1;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPT1_SMP_Set << (3 * (ADC_Channel - 10));
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPT1 = tmpreg1;
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPT2;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPT2_SMP_Set << (3 * ADC_Channel);
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPT2 = tmpreg1;
+  }
+
+  /* For Rank 1 to 6 */
+  if (Rank < 7)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->RSQ3;
+    /* Calculate the mask to clear */
+    tmpreg2 = RSQ3_SQ_Set << (5 * (Rank - 1));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->RSQ3 = tmpreg1;
+  }
+  /* For Rank 7 to 12 */
+  else if (Rank < 13)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->RSQ2;
+    /* Calculate the mask to clear */
+    tmpreg2 = RSQ2_SQ_Set << (5 * (Rank - 7));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->RSQ2 = tmpreg1;
+  }
+  /* For Rank 13 to 16 */
+  else
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->RSQ1;
+    /* Calculate the mask to clear */
+    tmpreg2 = RSQ1_SQ_Set << (5 * (Rank - 13));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->RSQ1 = tmpreg1;
+  }
+}
+
+/**
+  * @brief  Enables or disables the ADCx conversion through external trigger.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC external trigger start of conversion.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ExternalTrigConvCtrl(ADC_Type* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC conversion on external event */
+    ADCx->CTRL2 |= CTRL2_EXTTRIG_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC conversion on external event */
+    ADCx->CTRL2 &= CTRL2_EXTTRIG_Rst;
+  }
+}
+
+/**
+  * @brief  Returns the last ADCx conversion result data for regular channel.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetConversionValue(ADC_Type* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Return the selected ADC conversion value */
+  return (uint16_t) ADCx->RDOR;
+}
+
+/**
+  * @brief  Returns the last ADC1 and ADC2 conversion result data in dual mode.
+  * @retval The Data conversion value.
+  */
+uint32_t ADC_GetDualModeConversionValue(void)
+{
+  /* Return the dual mode conversion value */
+  return (*(__IO uint32_t *) DOR_ADDRESS);
+}
+
+/**
+  * @brief  Enables or disables the selected ADC automatic injected group
+  *         conversion after regular one.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC auto injected conversion
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_AutoInjectedConvCtrl(ADC_Type* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC automatic injected group conversion */
+    ADCx->CTRL1 |= CTRL1_JAUT_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC automatic injected group conversion */
+    ADCx->CTRL1 &= CTRL1_JAUT_Rst;
+  }
+}
+
+/**
+  * @brief  Enables or disables the discontinuous mode for injected group
+  *         channel for the specified ADC
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC discontinuous mode
+  *         on injected group channel.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_InjectedDiscModeCtrl(ADC_Type* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC injected discontinuous mode */
+    ADCx->CTRL1 |= CTRL1_JDISCEN_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC injected discontinuous mode */
+    ADCx->CTRL1 &= CTRL1_JDISCEN_Rst;
+  }
+}
+
+/**
+  * @brief  Configures the ADCx external trigger for injected channels conversion.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_ExternalTrigInjec_TMR2_TRGO_ADC12: Timer2 TRGO event selected (for ADC1, ADC2)
+  *     @arg ADC_ExternalTrigInjec_TMR2_CC1_ADC12: Timer2 capture compare1 selected (for ADC1, ADC2)
+  *     @arg ADC_ExternalTrigInjec_TMR3_CC4_ADC12: Timer3 capture compare4 selected (for ADC1, ADC2)
+  *     @arg ADC_ExternalTrigInjec_TMR4_TRGO_ADC12: Timer4 TRGO event selected (for ADC1, ADC2)
+  *     @arg ADC_ExternalTrigInjec_Ext_INT15_TMR8_CC4_ADC12: External interrupt line 15 or Timer8 capture compare4 event selected (for ADC1 and ADC2)
+  *     @arg ADC_ExternalTrigInjec_TMR8_CC1_ADC12: Timer8 capture compare1 selected (for ADC1, ADC2)
+
+  *     @arg ADC_ExternalTrigInjec_TMR1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
+  *     @arg ADC_ExternalTrigInjec_TMR1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
+  *     @arg ADC_ExternalTrigInjec_TMR15_CC1: Timer15 capture compare1 selected (for ADC1, ADC2 and ADC3)
+  *     @arg ADC_ExternalTrigInjec_TMR15_CC2: Timer15 capture compare2 selected (for ADC1, ADC2 and ADC3)
+  *     @arg ADC_ExternalTrigInjec_TMR15_CC3: Timer15 capture compare3 selected (for ADC1, ADC2 and ADC3)
+  *     @arg ADC_ExternalTrigInjec_TMR15_CC4: Timer15 capture compare4 selected (for ADC1, ADC2 and ADC3)
+  *     @arg ADC_ExternalTrigInjec_TMR15_TRGO: Timer15 TRGO event selected (for ADC1, ADC2 and ADC3)
+  *     @arg ADC_ExternalTrigInjec_TMR1_CC1: Timer1 capture compare1 selected (for ADC1, ADC2 and ADC3)
+  *     @arg ADC_ExternalTrigInjec_TMR8_TRGO: Timer8 TRGO event selected (for ADC1, ADC2 and ADC3)
+  *     @arg ADC_ExternalTrigInjec_None: Injected conversion started by software and not by external trigger (for ADC1, ADC2 and ADC3)
+  
+  *     @arg ADC_ExternalTrigInjec_TMR4_CC3_ADC3: Timer4 capture compare3 selected (for ADC3 only)
+  *     @arg ADC_ExternalTrigInjec_TMR8_CC2_ADC3: Timer8 capture compare2 selected (for ADC3 only)
+  *     @arg ADC_ExternalTrigInjec_TMR8_CC4_ADC3: Timer8 capture compare4 selected (for ADC3 only)
+  *     @arg ADC_ExternalTrigInjec_TMR5_TRGO_ADC3: Timer5 TRGO event selected (for ADC3 only)
+  *     @arg ADC_ExternalTrigInjec_TMR5_CC4_ADC3: Timer5 capture compare4 selected (for ADC3 only)
+  *     @arg ADC_ExternalTrigInjec_TMR1_CC2_ADC3: Timer1 capture compare2 selected (for ADC3 only)  
+  * @retval None
+  */
+void ADC_ExternalTrigInjectedConvConfig(ADC_Type* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
+  /* Get the old register value */
+  tmpreg = ADCx->CTRL2;
+  /* Clear the old external event selection for injected group */
+  tmpreg &= CTRL2_JEXTSEL_Rst;
+  /* Set the external event selection for injected group */
+  tmpreg |= ADC_ExternalTrigInjecConv;
+  /* Store the new register value */
+  ADCx->CTRL2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the ADCx injected channels conversion through
+  *         external trigger
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC external trigger start of
+  *         injected conversion.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ExternalTrigInjectedConvCtrl(ADC_Type* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC external event selection for injected group */
+    ADCx->CTRL2 |= CTRL2_JEXTTRIG_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC external event selection for injected group */
+    ADCx->CTRL2 &= CTRL2_JEXTTRIG_Rst;
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected ADC start of the injected
+  *         channels conversion.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC software start injected conversion.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_SoftwareStartInjectedConvCtrl(ADC_Type* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC conversion for injected group on external event and start the selected
+       ADC injected conversion */
+    ADCx->CTRL2 |= CTRL2_JEXTTRIG_JSWSTR_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC conversion on external event for injected group and stop the selected
+       ADC injected conversion */
+    ADCx->CTRL2 &= CTRL2_JEXTTRIG_JSWSTR_Rst;
+  }
+}
+
+/**
+  * @brief  Gets the selected ADC Software start injected conversion Status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC software start injected conversion (SET or RESET).
+  */
+FlagStatus ADC_GetSoftwareStartInjectedConvCtrlStatus(ADC_Type* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  /* Check the status of JSWSTART bit */
+  if ((ADCx->CTRL2 & CTRL2_JSWSTR_Set) != (uint32_t)RESET)
+  {
+    /* JSWSTART bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* JSWSTART bit is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the JSWSTART bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Configures for the selected ADC injected channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_Channel_0: ADC Channel0 selected
+  *     @arg ADC_Channel_1: ADC Channel1 selected
+  *     @arg ADC_Channel_2: ADC Channel2 selected
+  *     @arg ADC_Channel_3: ADC Channel3 selected
+  *     @arg ADC_Channel_4: ADC Channel4 selected
+  *     @arg ADC_Channel_5: ADC Channel5 selected
+  *     @arg ADC_Channel_6: ADC Channel6 selected
+  *     @arg ADC_Channel_7: ADC Channel7 selected
+  *     @arg ADC_Channel_8: ADC Channel8 selected
+  *     @arg ADC_Channel_9: ADC Channel9 selected
+  *     @arg ADC_Channel_10: ADC Channel10 selected
+  *     @arg ADC_Channel_11: ADC Channel11 selected
+  *     @arg ADC_Channel_12: ADC Channel12 selected
+  *     @arg ADC_Channel_13: ADC Channel13 selected
+  *     @arg ADC_Channel_14: ADC Channel14 selected
+  *     @arg ADC_Channel_15: ADC Channel15 selected
+  *     @arg ADC_Channel_16: ADC Channel16 selected
+  *     @arg ADC_Channel_17: ADC Channel17 selected
+  * @param  Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4.
+  * @param  ADC_SampleTime: The sample time value to be set for the selected channel.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_SampleTime_1_5: Sample time equal to 1.5 cycles
+  *     @arg ADC_SampleTime_7_5: Sample time equal to 7.5 cycles
+  *     @arg ADC_SampleTime_13_5: Sample time equal to 13.5 cycles
+  *     @arg ADC_SampleTime_28_5: Sample time equal to 28.5 cycles
+  *     @arg ADC_SampleTime_41_5: Sample time equal to 41.5 cycles
+  *     @arg ADC_SampleTime_55_5: Sample time equal to 55.5 cycles
+  *     @arg ADC_SampleTime_71_5: Sample time equal to 71.5 cycles
+  *     @arg ADC_SampleTime_239_5: Sample time equal to 239.5 cycles
+  * @retval None
+  */
+void ADC_InjectedChannelConfig(ADC_Type* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  assert_param(IS_ADC_INJECTED_RANK(Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+
+  /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+  if (ADC_Channel > ADC_Channel_9)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPT1;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPT1_SMP_Set << (3 * (ADC_Channel - 10));
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPT1 = tmpreg1;
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPT2;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPT2_SMP_Set << (3 * ADC_Channel);
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPT2 = tmpreg1;
+  }
+
+  /* Rank configuration */
+  /* Get the old register value */
+  tmpreg1 = ADCx->JSQ;
+  /* Get JL value: Number = JL+1 */
+  tmpreg3 =  (tmpreg1 & JSQR_JLEN_Set) >> 20;
+  /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
+  tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+  /* Clear the old JSQx bits for the selected rank */
+  tmpreg1 &= ~tmpreg2;
+  /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
+  tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+  /* Set the JSQx bits for the selected rank */
+  tmpreg1 |= tmpreg2;
+  /* Store the new register value */
+  ADCx->JSQ = tmpreg1;
+}
+
+/**
+  * @brief  Configures the sequencer length for injected channels
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  Length: The sequencer length.
+  *   This parameter must be a number between 1 to 4.
+  * @retval None
+  */
+void ADC_InjectedSequencerLengthConfig(ADC_Type* ADCx, uint8_t Length)
+{
+  uint32_t tmpreg1 = 0;
+  uint32_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_LENGTH(Length));
+
+  /* Get the old register value */
+  tmpreg1 = ADCx->JSQ;
+  /* Clear the old injected sequnence lenght JL bits */
+  tmpreg1 &= JSQR_JLEN_Rst;
+  /* Set the injected sequnence lenght JL bits */
+  tmpreg2 = Length - 1;
+  tmpreg1 |= tmpreg2 << 20;
+  /* Store the new register value */
+  ADCx->JSQ = tmpreg1;
+}
+
+/**
+  * @brief  Set the injected channels conversion value offset
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_InjectedChannel: the ADC injected channel to set its offset.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_InjectedChannel_1: Injected Channel1 selected
+  *     @arg ADC_InjectedChannel_2: Injected Channel2 selected
+  *     @arg ADC_InjectedChannel_3: Injected Channel3 selected
+  *     @arg ADC_InjectedChannel_4: Injected Channel4 selected
+  * @param  Offset: the offset value for the selected ADC injected channel
+  *   This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_SetInjectedOffset(ADC_Type* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+  assert_param(IS_ADC_OFFSET(Offset));
+
+  tmp = (uint32_t)ADCx;
+  tmp += ADC_InjectedChannel;
+
+  /* Set the selected injected channel data offset */
+  *(__IO uint32_t *) tmp = (uint32_t)Offset;
+}
+
+/**
+  * @brief  Returns the ADC injected channel conversion result
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_InjectedChannel: the converted ADC injected channel.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_InjectedChannel_1: Injected Channel1 selected
+  *     @arg ADC_InjectedChannel_2: Injected Channel2 selected
+  *     @arg ADC_InjectedChannel_3: Injected Channel3 selected
+  *     @arg ADC_InjectedChannel_4: Injected Channel4 selected
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetInjectedConversionValue(ADC_Type* ADCx, uint8_t ADC_InjectedChannel)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+
+  tmp = (uint32_t)ADCx;
+  tmp += ADC_InjectedChannel + JDOR_Offset;
+
+  /* Returns the selected injected channel conversion data value */
+  return (uint16_t) (*(__IO uint32_t*)  tmp);
+}
+
+/**
+  * @brief  Enables or disables the analog watchdog on single/all regular
+  *         or injected channels
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_AnalogWatchdog: the ADC analog watchdog configuration.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_AnalogWDG_SingleRegEnable: Analog watchdog on a single regular channel
+  *     @arg ADC_AnalogWDG_SingleInjecEnable: Analog watchdog on a single injected channel
+  *     @arg ADC_AnalogWDG_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
+  *     @arg ADC_AnalogWDG_AllRegEnable: Analog watchdog on  all regular channel
+  *     @arg ADC_AnalogWDG_AllInjecEnable: Analog watchdog on  all injected channel
+  *     @arg ADC_AnalogWDG_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
+  *     @arg ADC_AnalogWDG_None: No channel guarded by the analog watchdog
+  * @retval None
+  */
+void ADC_AnalogWDGCtrl(ADC_Type* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_ANALOG_WDG(ADC_AnalogWatchdog));
+  /* Get the old register value */
+  tmpreg = ADCx->CTRL1;
+  /* Clear AWDEN, AWDENJ and AWDSGL bits */
+  tmpreg &= CTRL1_AWDMode_Rst;
+  /* Set the analog watchdog enable mode */
+  tmpreg |= ADC_AnalogWatchdog;
+  /* Store the new register value */
+  ADCx->CTRL1 = tmpreg;
+}
+
+/**
+  * @brief  Configures the high and low thresholds of the analog watchdog.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  HighThreshold: the ADC analog watchdog High threshold value.
+  *   This parameter must be a 12bit value.
+  * @param  LowThreshold: the ADC analog watchdog Low threshold value.
+  *   This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_AnalogWDGThresholdsConfig(ADC_Type* ADCx, uint16_t HighThreshold,
+                                   uint16_t LowThreshold)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_THRESHOLD(HighThreshold));
+  assert_param(IS_ADC_THRESHOLD(LowThreshold));
+  /* Set the ADCx high threshold */
+  ADCx->WHTR = HighThreshold;
+  /* Set the ADCx low threshold */
+  ADCx->WLTR = LowThreshold;
+}
+
+/**
+  * @brief  Configures the analog watchdog guarded single channel
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure for the analog watchdog.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_Channel_0: ADC Channel0 selected
+  *     @arg ADC_Channel_1: ADC Channel1 selected
+  *     @arg ADC_Channel_2: ADC Channel2 selected
+  *     @arg ADC_Channel_3: ADC Channel3 selected
+  *     @arg ADC_Channel_4: ADC Channel4 selected
+  *     @arg ADC_Channel_5: ADC Channel5 selected
+  *     @arg ADC_Channel_6: ADC Channel6 selected
+  *     @arg ADC_Channel_7: ADC Channel7 selected
+  *     @arg ADC_Channel_8: ADC Channel8 selected
+  *     @arg ADC_Channel_9: ADC Channel9 selected
+  *     @arg ADC_Channel_10: ADC Channel10 selected
+  *     @arg ADC_Channel_11: ADC Channel11 selected
+  *     @arg ADC_Channel_12: ADC Channel12 selected
+  *     @arg ADC_Channel_13: ADC Channel13 selected
+  *     @arg ADC_Channel_14: ADC Channel14 selected
+  *     @arg ADC_Channel_15: ADC Channel15 selected
+  *     @arg ADC_Channel_16: ADC Channel16 selected
+  *     @arg ADC_Channel_17: ADC Channel17 selected
+  * @retval None
+  */
+void ADC_AnalogWDGSingleChannelConfig(ADC_Type* ADCx, uint8_t ADC_Channel)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  /* Get the old register value */
+  tmpreg = ADCx->CTRL1;
+  /* Clear the Analog watchdog channel select bits */
+  tmpreg &= CTRL1_AWDCH_Rst;
+  /* Set the Analog watchdog channel */
+  tmpreg |= ADC_Channel;
+  /* Store the new register value */
+  ADCx->CTRL1 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the temperature sensor and Vrefint channel.
+  * @param  NewState: new state of the temperature sensor.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_TempSensorVrefintCtrl(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the temperature sensor and Vrefint channel*/
+    ADC1->CTRL2 |= CTRL2_TSVREFE_Set;
+  }
+  else
+  {
+    /* Disable the temperature sensor and Vrefint channel*/
+    ADC1->CTRL2 &= CTRL2_TSVREFE_Rst;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ADC flag is set or not.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_FLAG_AWD: Analog watchdog flag
+  *     @arg ADC_FLAG_EC: End of conversion flag
+  *     @arg ADC_FLAG_JEC: End of injected group conversion flag
+  *     @arg ADC_FLAG_JSTR: Start of injected group conversion flag
+  *     @arg ADC_FLAG_RSTR: Start of regular group conversion flag
+  * @retval The new state of ADC_FLAG (SET or RESET).
+  */
+FlagStatus ADC_GetFlagStatus(ADC_Type* ADCx, uint8_t ADC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+
+  /* Check the status of the specified ADC flag */
+  if ((ADCx->STS & ADC_FLAG) != (uint8_t)RESET)
+  {
+    /* ADC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_FLAG is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the ADC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's pending flags.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg ADC_FLAG_AWD: Analog watchdog flag
+  *     @arg ADC_FLAG_EC: End of conversion flag
+  *     @arg ADC_FLAG_JEC: End of injected group conversion flag
+  *     @arg ADC_FLAG_JSTR: Start of injected group conversion flag
+  *     @arg ADC_FLAG_RSTR: Start of regular group conversion flag
+  * @retval None
+  */
+void ADC_ClearFlag(ADC_Type* ADCx, uint8_t ADC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+  /* Clear the selected ADC flags */
+  ADCx->STS = ~(uint32_t)ADC_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified ADC interrupt has occurred or not.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_INT: specifies the ADC interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_INT_EC: End of conversion interrupt mask
+  *     @arg ADC_INT_AWD: Analog watchdog interrupt mask
+  *     @arg ADC_INT_JEC: End of injected conversion interrupt mask
+  * @retval The new state of ADC_INT (SET or RESET).
+  */
+ITStatus ADC_GetINTStatus(ADC_Type* ADCx, uint16_t ADC_INT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t itmask = 0, enablestatus = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_GET_INT(ADC_INT));
+  /* Get the ADC INT index */
+  itmask = ADC_INT >> 8;
+  /* Get the ADC_INT enable bit status */
+  enablestatus = (ADCx->CTRL1 & (uint8_t)ADC_INT) ;
+
+  /* Check the status of the specified ADC interrupt */
+  if (((ADCx->STS & itmask) != (uint32_t)RESET) && enablestatus)
+  {
+    /* ADC_INT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_INT is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the ADC_INT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's interrupt pending bits.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_INT: specifies the ADC interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg ADC_INT_EC: End of conversion interrupt mask
+  *     @arg ADC_INT_AWD: Analog watchdog interrupt mask
+  *     @arg ADC_INT_JEC: End of injected conversion interrupt mask
+  * @retval None
+  */
+void ADC_ClearINTPendingBit(ADC_Type* ADCx, uint16_t ADC_INT)
+{
+  uint8_t itmask = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INT(ADC_INT));
+  /* Get the ADC INT index */
+  itmask = (uint8_t)(ADC_INT >> 8);
+  /* Clear the selected ADC interrupt pending bits */
+  ADCx->STS = ~(uint32_t)itmask;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_bkp.c

@@ -0,0 +1,302 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_bkp.c
+ * Description  : at32f4xx BKP source file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_bkp.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup BKP
+  * @brief BKP driver modules
+  * @{
+  */
+
+#if defined (AT32F403xx) || defined (AT32F413xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+
+/** @defgroup BKP_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Private_Defines
+  * @{
+  */
+
+/* ------------ BKP registers bit address in the alias region --------------- */
+#define BKP_OFFSET                  (BKP_BASE - PERIPH_BASE)
+
+/* --- CTRL Register ----*/
+
+/* Alias word address of TPAL bit */
+#define CTRL_OFFSET                 (BKP_OFFSET + 0x30)
+#define TPALV_BitPos                0x01
+#define CTRL_TPALV_BBMAP            (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (TPALV_BitPos * 4))
+
+/* Alias word address of TPE bit */
+#define TPEN_BitPos                 0x00
+#define CTRL_TPEN_BBMAP             (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (TPEN_BitPos * 4))
+
+/* --- CTRLSTS Register ---*/
+
+/* Alias word address of TPIE bit */
+#define CTRLSTS_OFFSET              (BKP_OFFSET + 0x34)
+#define TPIEN_BitPos                0x02
+#define CTRLSTS_TPIEN_BBMAP         (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TPIEN_BitPos * 4))
+
+/* Alias word address of TIF bit */
+#define TPIF_BitPos                 0x09
+#define CTRLSTS_TPIF_BBMAP          (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TPIF_BitPos * 4))
+
+/* Alias word address of TEF bit */
+#define TPEF_BitPos                 0x08
+#define CTRLSTS_TPEF_BBMAP          (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TPEF_BitPos * 4))
+
+/* ---------------------- BKP registers bit mask ------------------------ */
+
+/* RTCCR register bit mask */
+#define RTCCAL_CAL_MASK             ((uint16_t)0xFF80)
+#define RTCCAL_MASK                 ((uint16_t)0xFC7F)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup BKP_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the BKP peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void BKP_Reset(void)
+{
+  RCC_BackupResetCmd(ENABLE);
+  RCC_BackupResetCmd(DISABLE);
+}
+
+/**
+  * @brief  Configures the Tamper Pin active level.
+  * @param  BKP_TamperPinLevel: specifies the Tamper Pin active level.
+  *   This parameter can be one of the following values:
+  *     @arg BKP_TamperPinLv_H: Tamper pin active on high level
+  *     @arg BKP_TamperPinLv_L: Tamper pin active on low level
+  * @retval None
+  */
+void BKP_TamperPinLvConfig(uint16_t BKP_TamperPinLevel)
+{
+  /* Check the parameters */
+  assert_param(IS_BKP_TAMPER_PIN_LV(BKP_TamperPinLevel));
+  *(__IO uint32_t *) CTRL_TPALV_BBMAP = BKP_TamperPinLevel;
+}
+
+/**
+  * @brief  Enables or disables the Tamper Pin activation.
+  * @param  NewState: new state of the Tamper Pin activation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void BKP_TamperPinCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CTRL_TPEN_BBMAP = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the Tamper Pin Interrupt.
+  * @param  NewState: new state of the Tamper Pin Interrupt.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void BKP_IntConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CTRLSTS_TPIEN_BBMAP = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Select the RTC output source to output on the Tamper pin.
+  * @param  BKP_RTCOutputSource: specifies the RTC output source.
+  *   This parameter can be one of the following values:
+  *     @arg BKP_RTCOutput_None: no RTC output on the Tamper pin.
+  *     @arg BKP_RTCOutput_CalClk: output the RTC clock with frequency
+  *                                          divided by 64 on the Tamper pin.
+  *     @arg BKP_RTCOutput_Alarm: output the RTC Alarm pulse signal on
+  *                                     the Tamper pin.
+  *     @arg BKP_RTCOutput_Second: output the RTC Second pulse signal on
+  *                                      the Tamper pin.
+  * @retval None
+  */
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
+{
+  uint16_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_BKP_RTC_OUTPUT_SEL(BKP_RTCOutputSource));
+  tmpreg = BKP->RTCCAL;
+  /* Clear CCO, ASOE and ASOS bits */
+  tmpreg &= RTCCAL_MASK;
+
+  /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
+  tmpreg |= BKP_RTCOutputSource;
+  /* Store the new value */
+  BKP->RTCCAL = tmpreg;
+}
+
+/**
+  * @brief  Sets RTC Clock Calibration value.
+  * @param  CalibrationValue: specifies the RTC Clock Calibration value.
+  *   This parameter must be a number between 0 and 0x7F.
+  * @retval None
+  */
+void BKP_SetRTCCalValue(uint8_t CalibrationValue)
+{
+  uint16_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_BKP_CAL_VAL(CalibrationValue));
+  tmpreg = BKP->RTCCAL;
+  /* Clear CAL[6:0] bits */
+  tmpreg &= RTCCAL_CAL_MASK;
+  /* Set CAL[6:0] bits according to CalibrationValue value */
+  tmpreg |= CalibrationValue;
+  /* Store the new value */
+  BKP->RTCCAL = tmpreg;
+}
+
+/**
+  * @brief  Writes user data to the specified Data Backup Register.
+  * @param  BKP_DR: specifies the Data Backup Register.
+  *   This parameter can be BKP_DRx where x:[1, 42]
+  * @param  Data: data to write
+  * @retval None
+  */
+void BKP_WriteBackupReg(uint16_t BKP_DR, uint16_t Data)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_BKP_DT(BKP_DR));
+
+  tmp = (uint32_t)BKP_BASE;
+  tmp += BKP_DR;
+
+  *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+  * @brief  Reads data from the specified Data Backup Register.
+  * @param  BKP_DR: specifies the Data Backup Register.
+  *   This parameter can be BKP_DRx where x:[1, 42]
+  * @retval The content of the specified Data Backup Register
+  */
+uint16_t BKP_ReadBackupReg(uint16_t BKP_DR)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_BKP_DT(BKP_DR));
+
+  tmp = (uint32_t)BKP_BASE;
+  tmp += BKP_DR;
+
+  return (*(__IO uint16_t *) tmp);
+}
+
+/**
+  * @brief  Checks whether the Tamper Pin Event flag is set or not.
+  * @param  None
+  * @retval The new state of the Tamper Pin Event flag (SET or RESET).
+  */
+FlagStatus BKP_GetFlagStatus(void)
+{
+  return (FlagStatus)(*(__IO uint32_t *) CTRLSTS_TPEF_BBMAP);
+}
+
+/**
+  * @brief  Clears Tamper Pin Event pending flag.
+  * @param  None
+  * @retval None
+  */
+void BKP_ClearFlag(void)
+{
+  /* Set CTE bit to clear Tamper Pin Event flag */
+  BKP->CTRLSTS |= BKP_CTRLSTS_CTPEF;
+}
+
+/**
+  * @brief  Checks whether the Tamper Pin Interrupt has occurred or not.
+  * @param  None
+  * @retval The new state of the Tamper Pin Interrupt (SET or RESET).
+  */
+ITStatus BKP_GetIntStatus(void)
+{
+  return (ITStatus)(*(__IO uint32_t *) CTRLSTS_TPIF_BBMAP);
+}
+
+/**
+  * @brief  Clears Tamper Pin Interrupt pending bit.
+  * @param  None
+  * @retval None
+  */
+void BKP_ClearIntPendingBit(void)
+{
+  /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
+  BKP->CTRLSTS |= BKP_CTRLSTS_CTPIF;
+}
+
+/**
+  * @}
+  */
+
+#endif /* AT32F403xx || AT32F413xx || AT32F403Axx || AT32F407xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_can.c

@@ -0,0 +1,1480 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_can.c
+ * Description  : at32f4xx CAN source file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_can.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CAN
+  * @brief CAN driver modules
+  * @{
+  */
+
+/** @defgroup CAN_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Private_Defines
+  * @{
+  */
+
+/* CAN Master Control Register bits */
+
+#define MCR_DBF                     ((uint32_t)0x00010000) /* software master reset */
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ                 ((uint32_t)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define FM_FINIT                    ((uint32_t)0x00000001) /* Filter init mode */
+
+/* Time out for INAK bit */
+#define IAK_TIMEOUT                 ((uint32_t)0x0000FFFF)
+/* Time out for SLAK bit */
+#define SAK_TIMEOUT                 ((uint32_t)0x0000FFFF)
+
+
+
+/* Flags in TSR register */
+#define CAN_FLAGS_TTST              ((uint32_t)0x08000000)
+/* Flags in RF1R register */
+#define CAN_FLAGS_RF1               ((uint32_t)0x04000000)
+/* Flags in RF0R register */
+#define CAN_FLAGS_RF0               ((uint32_t)0x02000000)
+/* Flags in MSR register */
+#define CAN_FLAGS_MSTS              ((uint32_t)0x01000000)
+/* Flags in ESR register */
+#define CAN_FLAGS_ESTS              ((uint32_t)0x00F00000)
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0             ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1             ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2             ((uint8_t)0x02)
+
+
+
+#define CAN_MODE_MSK                ((uint32_t) 0x00000003)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Private_FunctionPrototypes
+  * @{
+  */
+
+static ITStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t It_Bit);
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the CAN peripheral registers to their default reset values.
+  * @param  CANx: where x can be only 1 to select the CAN peripheral.
+  * @retval None.
+  */
+void CAN_Reset(CAN_Type* CANx)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+  if (CANx == CAN1)
+  {
+    /* Enable CAN1 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_CAN1, ENABLE);
+    /* Release CAN1 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_CAN1, DISABLE);
+  }
+#ifdef AT32F413xx
+#ifndef AT32FEBKCx_MD
+  if (CANx == CAN2)
+  {
+    /* Enable CAN1 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_CAN2, ENABLE);
+    /* Release CAN1 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_CAN2, DISABLE);
+  }
+#endif
+#endif
+}
+
+/**
+  * @brief  Initializes the CAN peripheral according to the specified
+  *         parameters in the CAN_InitStruct.
+  * @param  CANx:           where x can be only 1 to to select the CAN
+  *                         peripheral.
+  * @param  CAN_InitStruct: pointer to a CAN_InitType structure that
+  *                         contains the configuration information for the
+  *                         CAN peripheral.
+  * @retval Constant indicates initialization succeed which will be
+  *         CAN_InitStatus_Failed or CAN_InitStatus_Success.
+  */
+uint8_t CAN_Init(CAN_Type* CANx, CAN_InitType* CAN_InitStruct)
+{
+  uint8_t InitStatus = CAN_InitStatus_Failed;
+  uint32_t wait_ack = 0x00000000;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTC));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABO));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWU));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFL));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TFP));
+  assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
+  assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
+  assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
+  assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
+  assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
+
+  /* Exit from sleep mode */
+  CANx->MCTRL &= (~(uint32_t)CAN_MCTRL_SLP);
+
+  /* Request initialisation */
+  CANx->MCTRL |= CAN_MCTRL_INRQ ;
+
+  /* Wait the acknowledge */
+  while (((CANx->MSTS & CAN_MSTS_IAK) != CAN_MSTS_IAK) && (wait_ack != IAK_TIMEOUT))
+  {
+    wait_ack++;
+  }
+
+  /* Check acknowledge */
+  if ((CANx->MSTS & CAN_MSTS_IAK) != CAN_MSTS_IAK)
+  {
+    InitStatus = CAN_InitStatus_Failed;
+  }
+  else
+  {
+    /* Set the time triggered communication mode */
+    if (CAN_InitStruct->CAN_TTC == ENABLE)
+    {
+      CANx->MCTRL |= CAN_MCTRL_TTC;
+    }
+    else
+    {
+      CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TTC;
+    }
+
+    /* Set the automatic bus-off management */
+    if (CAN_InitStruct->CAN_ABO == ENABLE)
+    {
+      CANx->MCTRL |= CAN_MCTRL_ABO;
+    }
+    else
+    {
+      CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_ABO;
+    }
+
+    /* Set the automatic wake-up mode */
+    if (CAN_InitStruct->CAN_AWU == ENABLE)
+    {
+      CANx->MCTRL |= CAN_MCTRL_AWU;
+    }
+    else
+    {
+      CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_AWU;
+    }
+
+    /* Set the no automatic retransmission */
+    if (CAN_InitStruct->CAN_NART == ENABLE)
+    {
+      CANx->MCTRL |= CAN_MCTRL_NART;
+    }
+    else
+    {
+      CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_NART;
+    }
+
+    /* Set the receive FIFO locked mode */
+    if (CAN_InitStruct->CAN_RFL == ENABLE)
+    {
+      CANx->MCTRL |= CAN_MCTRL_RFL;
+    }
+    else
+    {
+      CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_RFL;
+    }
+
+    /* Set the transmit FIFO priority */
+    if (CAN_InitStruct->CAN_TFP == ENABLE)
+    {
+      CANx->MCTRL |= CAN_MCTRL_TFP;
+    }
+    else
+    {
+      CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TFP;
+    }
+
+    /* Set the bit timing register */
+    CANx->BTMG = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
+                 ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
+                 ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
+                 ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
+                 ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
+
+    /* Request leave initialisation */
+    CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_INRQ;
+
+    /* Wait the acknowledge */
+    wait_ack = 0;
+
+    while (((CANx->MSTS & CAN_MSTS_IAK) == CAN_MSTS_IAK) && (wait_ack != IAK_TIMEOUT))
+    {
+      wait_ack++;
+    }
+
+    /* ...and check acknowledged */
+    if ((CANx->MSTS & CAN_MSTS_IAK) == CAN_MSTS_IAK)
+    {
+      InitStatus = CAN_InitStatus_Failed;
+    }
+    else
+    {
+      InitStatus = CAN_InitStatus_Success ;
+    }
+  }
+
+  /* At this step, return the status of initialization */
+  return InitStatus;
+}
+
+/**
+  * @brief  Initializes the CAN peripheral according to the specified
+  *         parameters in the CAN_FilterInitStruct.
+  * @param  CANx:           where x can be only 1 to to select the CAN
+  *                         peripheral.
+  * @param  CAN_FilterInitStruct: pointer to a CAN_FilterInitType
+  *                               structure that contains the configuration
+  *                               information.
+  * @retval None.
+  */
+void CAN_FilterInit(CAN_Type* CANx, CAN_FilterInitType* CAN_FilterInitStruct)
+{
+  uint32_t filter_number_bit_pos = 0;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
+  assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
+  assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
+  assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
+
+  filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
+
+  /* Initialisation mode for the filter */
+  CANx->FM |= FM_FINIT;
+
+  /* Filter Deactivation */
+  CANx->FA1 &= ~(uint32_t)filter_number_bit_pos;
+
+  /* Filter Scale */
+  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
+  {
+    /* 16-bit scale for the filter */
+    CANx->FS1 &= ~(uint32_t)filter_number_bit_pos;
+
+    /* First 16-bit identifier and First 16-bit mask */
+    /* Or First 16-bit identifier and Second 16-bit identifier */
+    CANx->FilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FBR1 =
+      ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMskIdLow) << 16) |
+      (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+
+    /* Second 16-bit identifier and Second 16-bit mask */
+    /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+    CANx->FilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FBR2 =
+      ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMskIdHigh) << 16) |
+      (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
+  }
+
+  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
+  {
+    /* 32-bit scale for the filter */
+    CANx->FS1 |= filter_number_bit_pos;
+    /* 32-bit identifier or First 32-bit identifier */
+    CANx->FilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FBR1 =
+      ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
+      (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+    /* 32-bit mask or Second 32-bit identifier */
+    CANx->FilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FBR2 =
+      ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMskIdHigh) << 16) |
+      (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMskIdLow);
+  }
+
+  /* Filter Mode */
+  if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
+  {
+    /*Id/Mask mode for the filter*/
+    CANx->FM1 &= ~(uint32_t)filter_number_bit_pos;
+  }
+  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+  {
+    /*Identifier list mode for the filter*/
+    CANx->FM1 |= (uint32_t)filter_number_bit_pos;
+  }
+
+  /* Filter FIFO assignment */
+  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
+  {
+    /* FIFO 0 assignation for the filter */
+    CANx->FFA1 &= ~(uint32_t)filter_number_bit_pos;
+  }
+
+  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
+  {
+    /* FIFO 1 assignation for the filter */
+    CANx->FFA1 |= (uint32_t)filter_number_bit_pos;
+  }
+
+  /* Filter activation */
+  if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
+  {
+    CANx->FA1 |= filter_number_bit_pos;
+  }
+
+  /* Leave the initialisation mode for the filter */
+  CANx->FM &= ~FM_FINIT;
+}
+
+/**
+  * @brief  Fills each CAN_InitStruct member with its default value.
+  * @param  CAN_InitStruct: pointer to a CAN_InitType structure which
+  *                         will be initialized.
+  * @retval None.
+  */
+void CAN_StructInit(CAN_InitType* CAN_InitStruct)
+{
+  /* Reset CAN init structure parameters values */
+
+  /* Initialize the time triggered communication mode */
+  CAN_InitStruct->CAN_TTC = DISABLE;
+
+  /* Initialize the automatic bus-off management */
+  CAN_InitStruct->CAN_ABO = DISABLE;
+
+  /* Initialize the automatic wake-up mode */
+  CAN_InitStruct->CAN_AWU = DISABLE;
+
+  /* Initialize the no automatic retransmission */
+  CAN_InitStruct->CAN_NART = DISABLE;
+
+  /* Initialize the receive FIFO locked mode */
+  CAN_InitStruct->CAN_RFL = DISABLE;
+
+  /* Initialize the transmit FIFO priority */
+  CAN_InitStruct->CAN_TFP = DISABLE;
+
+  /* Initialize the CAN_Mode member */
+  CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
+
+  /* Initialize the CAN_SJW member */
+  CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
+
+  /* Initialize the CAN_BS1 member */
+  CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
+
+  /* Initialize the CAN_BS2 member */
+  CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
+
+  /* Initialize the CAN_Prescaler member */
+  CAN_InitStruct->CAN_Prescaler = 1;
+}
+
+/**
+  * @brief  Select the start bank filter for slave CAN.
+  * @note   None.
+  * @param  CAN_BankNumber: Select the start slave bank filter from 1..27.
+  * @retval None.
+  */
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
+
+  /* Enter Initialisation mode for the filter */
+  CAN1->FM |= FM_FINIT;
+
+  /* Select the start slave bank */
+  CAN1->FM &= (uint32_t)0xFFFFC0F1 ;
+  CAN1->FM |= (uint32_t)(CAN_BankNumber) << 8;
+
+  /* Leave Initialisation mode for the filter */
+  CAN1->FM &= ~FM_FINIT;
+}
+
+/**
+  * @brief  Enables or disables the DBG Freeze for CAN.
+  * @param  CANx:     where x can be only 1 to to select the CAN peripheral.
+  * @param  NewState: new state of the CAN peripheral. This parameter can
+  *                   be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void CAN_DBGFreeze(CAN_Type* CANx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable Debug Freeze  */
+    CANx->MCTRL |= MCR_DBF;
+  }
+  else
+  {
+    /* Disable Debug Freeze */
+    CANx->MCTRL &= ~MCR_DBF;
+  }
+}
+
+
+/**
+  * @brief  Enables or disabes the CAN Time TriggerOperation communication mode.
+  * @param  CANx:      where x can be only 1 to to select the CAN peripheral.
+  * @param  NewState : Mode new state , can be one of @ref FunctionalState.
+  * @note   when enabled, Time stamp (TIME[15:0]) value is sent in the last
+  *         two data bytes of the 8-byte message: TIME[7:0] in data byte 6
+  *         and TIME[15:8] in data byte 7
+  * @note   DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
+  *         sent over the CAN bus.
+  * @retval None
+  */
+void CAN_TTComModeCtrl(CAN_Type* CANx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the TTCM mode */
+    CANx->MCTRL |= CAN_MCTRL_TTC;
+
+    /* Set TGT bits */
+    CANx->TxMailBox[0].TDT |= ((uint32_t)CAN_TDT0_TMEN);
+    CANx->TxMailBox[1].TDT |= ((uint32_t)CAN_TDT1_TMEN);
+    CANx->TxMailBox[2].TDT |= ((uint32_t)CAN_TDT2_TMEN);
+  }
+  else
+  {
+    /* Disable the TTCM mode */
+    CANx->MCTRL &= (uint32_t)(~(uint32_t)CAN_MCTRL_TTC);
+
+    /* Reset TGT bits */
+    CANx->TxMailBox[0].TDT &= ((uint32_t)~CAN_TDT0_TMEN);
+    CANx->TxMailBox[1].TDT &= ((uint32_t)~CAN_TDT1_TMEN);
+    CANx->TxMailBox[2].TDT &= ((uint32_t)~CAN_TDT2_TMEN);
+  }
+}
+/**
+  * @brief  Initiates the transmission of a message.
+  * @param  CANx:      where x can be only 1 to to select the CAN peripheral.
+  * @param  TxMessage: pointer to a structure which contains CAN Id, CAN
+  *                    DLC and CAN data.
+  * @retval The number of the mailbox that is used for transmission
+  *                    or CAN_TxStatus_NoMailBox if there is no empty mailbox.
+  */
+uint8_t CAN_Transmit(CAN_Type* CANx, CanTxMsg* TxMessage)
+{
+  uint8_t transmit_mailbox = 0;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_IDTYPE(TxMessage->IDT));
+  assert_param(IS_CAN_RTR(TxMessage->RTR));
+  assert_param(IS_CAN_DLC(TxMessage->DLC));
+
+  /* Select one empty transmit mailbox */
+  if ((CANx->TSTS & CAN_TSTS_TSME0) == CAN_TSTS_TSME0)
+  {
+    transmit_mailbox = 0;
+  }
+  else if ((CANx->TSTS & CAN_TSTS_TSME1) == CAN_TSTS_TSME1)
+  {
+    transmit_mailbox = 1;
+  }
+  else if ((CANx->TSTS & CAN_TSTS_TSME2) == CAN_TSTS_TSME2)
+  {
+    transmit_mailbox = 2;
+  }
+  else
+  {
+    transmit_mailbox = CAN_TxStatus_NoMailBox;
+  }
+
+  if (transmit_mailbox != CAN_TxStatus_NoMailBox)
+  {
+    /* Set up the Id */
+    CANx->TxMailBox[transmit_mailbox].TMI &= TMIDxR_TXRQ;
+
+    if (TxMessage->IDT == CAN_Id_Standard)
+    {
+      assert_param(IS_CAN_STDID(TxMessage->StdId));
+      CANx->TxMailBox[transmit_mailbox].TMI |= ((TxMessage->StdId << 21) | \
+          TxMessage->RTR);
+    }
+    else
+    {
+      assert_param(IS_CAN_EXTID(TxMessage->ExtId));
+      CANx->TxMailBox[transmit_mailbox].TMI |= ((TxMessage->ExtId << 3) | \
+          TxMessage->IDT | \
+          TxMessage->RTR);
+    }
+
+    /* Set up the DLC */
+    TxMessage->DLC &= (uint8_t)0x0000000F;
+    CANx->TxMailBox[transmit_mailbox].TDT &= (uint32_t)0xFFFFFFF0;
+    CANx->TxMailBox[transmit_mailbox].TDT |= TxMessage->DLC;
+
+    /* Set up the data field */
+    CANx->TxMailBox[transmit_mailbox].TDL = (((uint32_t)TxMessage->Data[3] << 24) |
+                                            ((uint32_t)TxMessage->Data[2] << 16) |
+                                            ((uint32_t)TxMessage->Data[1] << 8) |
+                                            ((uint32_t)TxMessage->Data[0]));
+    CANx->TxMailBox[transmit_mailbox].TDH = (((uint32_t)TxMessage->Data[7] << 24) |
+                                            ((uint32_t)TxMessage->Data[6] << 16) |
+                                            ((uint32_t)TxMessage->Data[5] << 8) |
+                                            ((uint32_t)TxMessage->Data[4]));
+    /* Request transmission */
+    CANx->TxMailBox[transmit_mailbox].TMI |= TMIDxR_TXRQ;
+  }
+
+  return transmit_mailbox;
+}
+
+/**
+  * @brief  Checks the transmission of a message.
+  * @param  CANx:            where x can be only 1 to to select the
+  *                          CAN peripheral.
+  * @param  TransmitMailbox: the number of the mailbox that is used for
+  *                          transmission.
+  * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed
+  *         in an other case.
+  */
+uint8_t CAN_TransmitStatus(CAN_Type* CANx, uint8_t TransmitMailbox)
+{
+  uint32_t state = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+
+  switch (TransmitMailbox)
+  {
+  case (CAN_TXMAILBOX_0):
+    state =   CANx->TSTS &  (CAN_TSTS_RQC0 | CAN_TSTS_TOK0 | CAN_TSTS_TSME0);
+    break;
+
+  case (CAN_TXMAILBOX_1):
+    state =   CANx->TSTS &  (CAN_TSTS_RQC1 | CAN_TSTS_TOK1 | CAN_TSTS_TSME1);
+    break;
+
+  case (CAN_TXMAILBOX_2):
+    state =   CANx->TSTS &  (CAN_TSTS_RQC2 | CAN_TSTS_TOK2 | CAN_TSTS_TSME2);
+    break;
+
+  default:
+    state = CAN_TxStatus_Failed;
+    break;
+  }
+
+  switch (state)
+  {
+    /* transmit pending  */
+  case (0x0):
+    state = CAN_TxStatus_Pending;
+    break;
+
+    /* transmit failed  */
+  case (CAN_TSTS_RQC0 | CAN_TSTS_TSME0):
+    state = CAN_TxStatus_Failed;
+    break;
+
+  case (CAN_TSTS_RQC1 | CAN_TSTS_TSME1):
+    state = CAN_TxStatus_Failed;
+    break;
+
+  case (CAN_TSTS_RQC2 | CAN_TSTS_TSME2):
+    state = CAN_TxStatus_Failed;
+    break;
+
+    /* transmit succeeded  */
+  case (CAN_TSTS_RQC0 | CAN_TSTS_TOK0 | CAN_TSTS_TSME0):
+    state = CAN_TxStatus_Ok;
+    break;
+
+  case (CAN_TSTS_RQC1 | CAN_TSTS_TOK1 | CAN_TSTS_TSME1):
+    state = CAN_TxStatus_Ok;
+    break;
+
+  case (CAN_TSTS_RQC2 | CAN_TSTS_TOK2 | CAN_TSTS_TSME2):
+    state = CAN_TxStatus_Ok;
+    break;
+
+  default:
+    state = CAN_TxStatus_Failed;
+    break;
+  }
+
+  return (uint8_t) state;
+}
+
+/**
+  * @brief  Cancels a transmit request.
+  * @param  CANx:     where x can be only 1 to to select the CAN peripheral.
+  * @param  Mailbox:  Mailbox number.
+  * @retval None.
+  */
+void CAN_CancelTransmit(CAN_Type* CANx, uint8_t Mailbox)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
+
+  /* abort transmission */
+  switch (Mailbox)
+  {
+  case (CAN_TXMAILBOX_0):
+    CANx->TSTS |= CAN_TSTS_ARQ0;
+    break;
+
+  case (CAN_TXMAILBOX_1):
+    CANx->TSTS |= CAN_TSTS_ARQ1;
+    break;
+
+  case (CAN_TXMAILBOX_2):
+    CANx->TSTS |= CAN_TSTS_ARQ2;
+    break;
+
+  default:
+    break;
+  }
+}
+
+
+/**
+  * @brief  Receives a message.
+  * @param  CANx:       where x can be only 1 to to select the CAN peripheral.
+  * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @param  RxMessage:  pointer to a structure receive message which contains
+  *                     CAN Id, CAN DLC, CAN datas and FMI number.
+  * @retval None.
+  */
+void CAN_Receive(CAN_Type* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  /* Get the Id */
+  RxMessage->IDT = (uint8_t)0x04 & CANx->FIFOMailBox[FIFONumber].RFI;
+
+  if (RxMessage->IDT == CAN_Id_Standard)
+  {
+    RxMessage->StdId = (uint32_t)0x000007FF & (CANx->FIFOMailBox[FIFONumber].RFI >> 21);
+  }
+  else
+  {
+    RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->FIFOMailBox[FIFONumber].RFI >> 3);
+  }
+
+  RxMessage->RTR = (uint8_t)0x02 & CANx->FIFOMailBox[FIFONumber].RFI;
+  /* Get the DLC */
+  RxMessage->DLC = (uint8_t)0x0F & CANx->FIFOMailBox[FIFONumber].RDT;
+  /* Get the FMI */
+  RxMessage->FID = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RDT >> 8);
+  /* Get the data field */
+  RxMessage->Data[0] = (uint8_t)0xFF & CANx->FIFOMailBox[FIFONumber].RDL;
+  RxMessage->Data[1] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RDL >> 8);
+  RxMessage->Data[2] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RDL >> 16);
+  RxMessage->Data[3] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RDL >> 24);
+  RxMessage->Data[4] = (uint8_t)0xFF & CANx->FIFOMailBox[FIFONumber].RDH;
+  RxMessage->Data[5] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RDH >> 8);
+  RxMessage->Data[6] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RDH >> 16);
+  RxMessage->Data[7] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RDH >> 24);
+
+  /* Release the FIFO */
+  /* Release FIFO0 */
+  if (FIFONumber == CAN_FIFO0)
+  {
+    CANx->RF0 |= CAN_RF0_RRFM0;
+  }
+  /* Release FIFO1 */
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    CANx->RF1 |= CAN_RF1_RRFM1;
+  }
+}
+
+/**
+  * @brief  Releases the specified FIFO.
+  * @param  CANx:       where x can be only 1 to to select the CAN peripheral.
+  * @param  FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
+  * @retval None.
+  */
+void CAN_FIFORelease(CAN_Type* CANx, uint8_t FIFONumber)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_FIFO(FIFONumber));
+
+  /* Release FIFO0 */
+  if (FIFONumber == CAN_FIFO0)
+  {
+    CANx->RF0 |= CAN_RF0_RRFM0;
+  }
+  /* Release FIFO1 */
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    CANx->RF1 |= CAN_RF1_RRFM1;
+  }
+}
+
+/**
+  * @brief  Returns the number of pending messages.
+  * @param  CANx:       where x can be only 1 to to select the CAN peripheral.
+  * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @retval NbMessage : which is the number of pending message.
+  */
+uint8_t CAN_MessagePending(CAN_Type* CANx, uint8_t FIFONumber)
+{
+  uint8_t message_pending = 0;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_FIFO(FIFONumber));
+
+  if (FIFONumber == CAN_FIFO0)
+  {
+    message_pending = (uint8_t)(CANx->RF0 & (uint32_t)0x03);
+  }
+  else if (FIFONumber == CAN_FIFO1)
+  {
+    message_pending = (uint8_t)(CANx->RF1 & (uint32_t)0x03);
+  }
+  else
+  {
+    message_pending = 0;
+  }
+
+  return message_pending;
+}
+
+
+/**
+  * @brief   Select the CAN Operation mode.
+  * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one
+  *                            of @ref CAN_Operating_Mode enumeration.
+  * @retval status of the requested mode which can be
+  *         - CAN_ModeStatus_Failed    CAN failed entering the specific mode
+  *         - CAN_ModeStatus_Success   CAN Succeed entering the specific mode
+
+  */
+uint8_t CAN_OperatingModeRequest(CAN_Type* CANx, uint8_t CAN_OperatingMode)
+{
+  uint8_t status = CAN_ModeStatus_Failed;
+
+  /* Timeout for INAK or also for SLAK bits*/
+  uint32_t timeout = IAK_TIMEOUT;
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
+
+  if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
+  {
+    /* Request initialisation */
+    CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_SLP)) | CAN_MCTRL_INRQ);
+
+    /* Wait the acknowledge */
+    while (((CANx->MSTS & CAN_MODE_MSK) != CAN_MSTS_IAK) && (timeout != 0))
+    {
+      timeout--;
+    }
+
+    if ((CANx->MSTS & CAN_MODE_MSK) != CAN_MSTS_IAK)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else  if (CAN_OperatingMode == CAN_OperatingMode_Normal)
+  {
+    /* Request leave initialisation and sleep mode  and enter Normal mode */
+    CANx->MCTRL &= (uint32_t)(~(CAN_MCTRL_SLP | CAN_MCTRL_INRQ));
+
+    /* Wait the acknowledge */
+    while (((CANx->MSTS & CAN_MODE_MSK) != 0) && (timeout != 0))
+    {
+      timeout--;
+    }
+
+    if ((CANx->MSTS & CAN_MODE_MSK) != 0)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else  if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
+  {
+    /* Request Sleep mode */
+    CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_INRQ)) | CAN_MCTRL_SLP);
+
+    /* Wait the acknowledge */
+    while (((CANx->MSTS & CAN_MODE_MSK) != CAN_MSTS_SAK) && (timeout != 0))
+    {
+      timeout--;
+    }
+
+    if ((CANx->MSTS & CAN_MODE_MSK) != CAN_MSTS_SAK)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else
+  {
+    status = CAN_ModeStatus_Failed;
+  }
+
+  return  (uint8_t) status;
+}
+
+/**
+  * @brief  Enters the low power mode.
+  * @param  CANx:   where x can be only 1 to to select the CAN peripheral.
+  * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an
+  *                 other case.
+  */
+uint8_t CAN_Sleep(CAN_Type* CANx)
+{
+  uint8_t sleepstatus = CAN_Sleep_Failed;
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+  /* Request Sleep mode */
+  CANx->MCTRL = (((CANx->MCTRL) & (uint32_t)(~(uint32_t)CAN_MCTRL_INRQ)) | CAN_MCTRL_SLP);
+
+  /* Sleep mode status */
+  if ((CANx->MSTS & (CAN_MSTS_SAK | CAN_MSTS_IAK)) == CAN_MSTS_SAK)
+  {
+    /* Sleep mode not entered */
+    sleepstatus =  CAN_Sleep_Ok;
+  }
+
+  /* return sleep mode status */
+  return (uint8_t)sleepstatus;
+}
+
+/**
+  * @brief  Wakes the CAN up.
+  * @param  CANx:    where x can be only 1 to to select the CAN peripheral.
+  * @retval status:  CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an
+  *                  other case.
+  */
+uint8_t CAN_WakeUp(CAN_Type* CANx)
+{
+  uint32_t wait_slak = SAK_TIMEOUT;
+  uint8_t wakeupstatus = CAN_WakeUp_Failed;
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+  /* Wake up request */
+  CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_SLP;
+
+  /* Sleep mode status */
+  while(((CANx->MSTS & CAN_MSTS_SAK) == CAN_MSTS_SAK) && (wait_slak != 0x00))
+  {
+    wait_slak--;
+  }
+
+  if((CANx->MSTS & CAN_MSTS_SAK) != CAN_MSTS_SAK)
+  {
+    /* wake up done : Sleep mode exited */
+    wakeupstatus = CAN_WakeUp_Ok;
+  }
+
+  /* return wakeup status */
+  return (uint8_t)wakeupstatus;
+}
+
+
+/**
+  * @brief  Returns the CANx's last error code (LEC).
+  * @param  CANx:          where x can be only 1 to to select the CAN peripheral.
+  * @retval CAN_ErrorCode: specifies the Error code :
+  *                        - CAN_ErrorCode_NoErr            No Error
+  *                        - CAN_ErrorCode_StuffErr         Stuff Error
+  *                        - CAN_ErrorCode_FormErr          Form Error
+  *                        - CAN_ErrorCode_ACKErr           Acknowledgment Error
+  *                        - CAN_ErrorCode_BitRecessiveErr  Bit Recessive Error
+  *                        - CAN_ErrorCode_BitDominantErr   Bit Dominant Error
+  *                        - CAN_ErrorCode_CRCErr           CRC Error
+  *                        - CAN_ErrorCode_SoftwareSetErr   Software Set Error
+  */
+
+uint8_t CAN_GetLastErrorCode(CAN_Type* CANx)
+{
+  uint8_t errorcode = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+  /* Get the error code*/
+  errorcode = (((uint8_t)CANx->ESTS) & (uint8_t)CAN_ESTS_ERC);
+
+  /* Return the error code*/
+  return errorcode;
+}
+/**
+  * @brief  Returns the CANx Receive Error Counter (REC).
+  * @note   In case of an error during reception, this counter is incremented
+  *         by 1 or by 8 depending on the error condition as defined by the CAN
+  *         standard. After every successful reception, the counter is
+  *         decremented by 1 or reset to 120 if its value was higher than 128.
+  *         When the counter value exceeds 127, the CAN controller enters the
+  *         error passive state.
+  * @param  CANx: where x can be only 1 to to select the CAN peripheral.
+  * @retval CAN Receive Error Counter.
+  */
+uint8_t CAN_GetReceiveErrorCounter(CAN_Type* CANx)
+{
+  uint8_t counter = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+  /* Get the Receive Error Counter*/
+  counter = (uint8_t)((CANx->ESTS & CAN_ESTS_REC) >> 24);
+
+  /* Return the Receive Error Counter*/
+  return counter;
+}
+
+
+/**
+  * @brief  Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+  * @param  CANx:   where x can be only 1 to to select the CAN peripheral.
+  * @retval LSB of the 9-bit CAN Transmit Error Counter.
+  */
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_Type* CANx)
+{
+  uint8_t counter = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+  /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+  counter = (uint8_t)((CANx->ESTS & CAN_ESTS_TEC) >> 16);
+
+  /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+  return counter;
+}
+
+
+/**
+  * @brief  Enables or disables the specified CANx interrupts.
+  * @param  CANx:   where x can be only 1 to to select the CAN peripheral.
+  * @param  CAN_INT: specifies the CAN interrupt sources to be enabled or disabled.
+  *                 This parameter can be:
+  *                 - CAN_INT_TSME,
+  *                 - CAN_INT_RFP0,
+  *                 - CAN_INT_RFFU0,
+  *                 - CAN_INT_RFOV0,
+  *                 - CAN_INT_RFP1,
+  *                 - CAN_INT_RFFU1,
+  *                 - CAN_INT_RFOV1,
+  *                 - CAN_INT_ERG,
+  *                 - CAN_INT_ERP,
+  *                 - CAN_INT_LEC,
+  *                 - CAN_INT_ERR,
+  *                 - CAN_INT_WK or
+  *                 - CAN_INT_SAK.
+  * @param  NewState: new state of the CAN interrupts.
+  *                   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void CAN_INTConfig(CAN_Type* CANx, uint32_t CAN_INT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_INT(CAN_INT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected CANx interrupt */
+    CANx->INTEN |= CAN_INT;
+  }
+  else
+  {
+    /* Disable the selected CANx interrupt */
+    CANx->INTEN &= ~CAN_INT;
+  }
+}
+/**
+  * @brief  Checks whether the specified CAN flag is set or not.
+  * @param  CANx:     where x can be only 1 to to select the CAN peripheral.
+  * @param  CAN_FLAG: specifies the flag to check.
+  *                   This parameter can be one of the following flags:
+  *                  - CAN_FLAG_ERG
+  *                  - CAN_FLAG_ERP
+  *                  - CAN_FLAG_BU
+  *                  - CAN_FLAG_RQCP0
+  *                  - CAN_FLAG_RQCP1
+  *                  - CAN_FLAG_RQCP2
+  *                  - CAN_FLAG_RFP1
+  *                  - CAN_FLAG_RFFU1
+  *                  - CAN_FLAG_RFOV1
+  *                  - CAN_FLAG_RFP0
+  *                  - CAN_FLAG_RFFU0
+  *                  - CAN_FLAG_RFOV0
+  *                  - CAN_FLAG_WK
+  *                  - CAN_FLAG_SAK
+  *                  - CAN_FLAG_ERC
+  * @retval The new state of CAN_FLAG (SET or RESET).
+  */
+FlagStatus CAN_GetFlagStatus(CAN_Type* CANx, uint32_t CAN_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
+
+
+  if((CAN_FLAG & CAN_FLAGS_ESTS) != (uint32_t)RESET)
+  {
+    /* Check the status of the specified CAN flag */
+    if ((CANx->ESTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    {
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    {
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_MSTS) != (uint32_t)RESET)
+  {
+    /* Check the status of the specified CAN flag */
+    if ((CANx->MSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    {
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    {
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_TTST) != (uint32_t)RESET)
+  {
+    /* Check the status of the specified CAN flag */
+    if ((CANx->TSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    {
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    {
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_RF0) != (uint32_t)RESET)
+  {
+    /* Check the status of the specified CAN flag */
+    if ((CANx->RF0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    {
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    {
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else /* If(CAN_FLAG & CAN_FLAGS_RF1 != (uint32_t)RESET) */
+  {
+    /* Check the status of the specified CAN flag */
+    if ((uint32_t)(CANx->RF1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    {
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    {
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+
+  /* Return the CAN_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the CAN's pending flags.
+  * @param  CANx:     where x can be only 1 to to select the CAN peripheral.
+  * @param  CAN_FLAG: specifies the flag to clear.
+  *                   This parameter can be one of the following flags:
+  *                    - CAN_FLAG_RQCP0
+  *                    - CAN_FLAG_RQCP1
+  *                    - CAN_FLAG_RQCP2
+  *                    - CAN_FLAG_RFFU1
+  *                    - CAN_FLAG_RFOV1
+  *                    - CAN_FLAG_RFFU0
+  *                    - CAN_FLAG_RFOV0
+  *                    - CAN_FLAG_WK
+  *                    - CAN_FLAG_SAK
+  *                    - CAN_FLAG_ERC
+  * @retval None.
+  */
+void CAN_ClearFlag(CAN_Type* CANx, uint32_t CAN_FLAG)
+{
+  uint32_t flagtmp = 0;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
+
+  if (CAN_FLAG == CAN_FLAG_ERC) /* ESR register */
+  {
+    /* Clear the selected CAN flags */
+    CANx->ESTS = (uint32_t)RESET;
+  }
+  else /* MSR or TSR or RF0R or RF1R */
+  {
+    flagtmp = CAN_FLAG & 0x000FFFFF;
+
+    if ((CAN_FLAG & CAN_FLAGS_RF0) != (uint32_t)RESET)
+    {
+      /* Receive Flags */
+      CANx->RF0 = (uint32_t)(flagtmp);
+    }
+    else if ((CAN_FLAG & CAN_FLAGS_RF1) != (uint32_t)RESET)
+    {
+      /* Receive Flags */
+      CANx->RF1 = (uint32_t)(flagtmp);
+    }
+    else if ((CAN_FLAG & CAN_FLAGS_TTST) != (uint32_t)RESET)
+    {
+      /* Transmit Flags */
+      CANx->TSTS = (uint32_t)(flagtmp);
+    }
+    else /* If((CAN_FLAG & CAN_FLAGS_MSTS)!=(uint32_t)RESET) */
+    {
+      /* Operating mode Flags */
+      CANx->MSTS = (uint32_t)(flagtmp);
+    }
+  }
+}
+
+/**
+  * @brief  Checks whether the specified CANx interrupt has occurred or not.
+  * @param  CANx:    where x can be only 1 to to select the CAN peripheral.
+  * @param  CAN_INT:  specifies the CAN interrupt source to check.
+  *                  This parameter can be one of the following flags:
+  *                 -  CAN_INT_TSME
+  *                 -  CAN_INT_RFP0
+  *                 -  CAN_INT_RFFU0
+  *                 -  CAN_INT_RFOV0
+  *                 -  CAN_INT_RFP1
+  *                 -  CAN_INT_RFFU1
+  *                 -  CAN_INT_RFOV1
+  *                 -  CAN_INT_WK
+  *                 -  CAN_INT_SAK
+  *                 -  CAN_INT_ERG
+  *                 -  CAN_INT_ERP
+  *                 -  CAN_INT_BU
+  *                 -  CAN_INT_LEC
+  *                 -  CAN_INT_ERR
+  * @retval The current state of CAN_INT (SET or RESET).
+  */
+ITStatus CAN_GetINTStatus(CAN_Type* CANx, uint32_t CAN_INT)
+{
+  ITStatus itstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_INT(CAN_INT));
+
+  /* check the enable interrupt bit */
+  if((CANx->INTEN & CAN_INT) != RESET)
+  {
+    /* in case the Interrupt is enabled, .... */
+    switch (CAN_INT)
+    {
+    case CAN_INT_TSME:
+      /* Check CAN_TSR_RQCPx bits */
+      itstatus = CheckINTStatus(CANx->TSTS, CAN_TSTS_RQC0 | CAN_TSTS_RQC1 | CAN_TSTS_RQC2);
+      break;
+
+    case CAN_INT_RFP0:
+      /* Check CAN_RF0_RFP0 bit */
+      itstatus = CheckINTStatus(CANx->RF0, CAN_RF0_RFP0);
+      break;
+
+    case CAN_INT_RFFU0:
+      /* Check CAN_RF0_RFFU0 bit */
+      itstatus = CheckINTStatus(CANx->RF0, CAN_RF0_RFFU0);
+      break;
+
+    case CAN_INT_RFOV0:
+      /* Check CAN_RF0_RFOV0 bit */
+      itstatus = CheckINTStatus(CANx->RF0, CAN_RF0_RFOV0);
+      break;
+
+    case CAN_INT_RFP1:
+      /* Check CAN_RF1_RFP1 bit */
+      itstatus = CheckINTStatus(CANx->RF1, CAN_RF1_RFP1);
+      break;
+
+    case CAN_INT_RFFU1:
+      /* Check CAN_RF1_RFFU1 bit */
+      itstatus = CheckINTStatus(CANx->RF1, CAN_RF1_RFFU1);
+      break;
+
+    case CAN_INT_RFOV1:
+      /* Check CAN_RF1_RFOV1 bit */
+      itstatus = CheckINTStatus(CANx->RF1, CAN_RF1_RFOV1);
+      break;
+
+    case CAN_INT_WK:
+      /* Check CAN_MSTS_WKIT bit */
+      itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_WKIT);
+      break;
+
+    case CAN_INT_SAK:
+      /* Check CAN_MSTS_SAKIT bit */
+      itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_SAKIT);
+      break;
+
+    case CAN_INT_ERG:
+      /* Check CAN_ESTS_ERWF bit */
+      itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_ERWF);
+      break;
+
+    case CAN_INT_ERP:
+      /* Check CAN_ESTS_ERPF bit */
+      itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_ERPF);
+      break;
+
+    case CAN_INT_BU:
+      /* Check CAN_ESTS_BFF bit */
+      itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_BFF);
+      break;
+
+    case CAN_INT_LEC:
+      /* Check CAN_ESTS_ERC bit */
+      itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_ERC);
+      break;
+
+    case CAN_INT_ERR:
+      /* Check CAN_MSTS_ERIT bit */
+      itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_ERIT);
+      break;
+
+    default :
+      /* in case of error, return RESET */
+      itstatus = RESET;
+      break;
+    }
+  }
+  else
+  {
+    /* in case the Interrupt is not enabled, return RESET */
+    itstatus  = RESET;
+  }
+
+  /* Return the CAN_INT status */
+  return  itstatus;
+}
+
+/**
+  * @brief  Clears the CANx's interrupt pending bits.
+  * @param  CANx:    where x can be only 1 to to select the CAN peripheral.
+  * @param  CAN_INT: specifies the interrupt pending bit to clear.
+  *                  -  CAN_INT_TSME
+  *                  -  CAN_INT_RFFU0
+  *                  -  CAN_INT_RFOV0
+  *                  -  CAN_INT_RFFU1
+  *                  -  CAN_INT_RFOV1
+  *                  -  CAN_INT_WK
+  *                  -  CAN_INT_SAK
+  *                  -  CAN_INT_ERG
+  *                  -  CAN_INT_ERP
+  *                  -  CAN_INT_BU
+  *                  -  CAN_INT_LEC
+  *                  -  CAN_INT_ERR
+  * @retval None.
+  */
+void CAN_ClearINTPendingBit(CAN_Type* CANx, uint32_t CAN_INT)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_CLEAR_INT(CAN_INT));
+
+  switch (CAN_INT)
+  {
+  case CAN_INT_TSME:
+    /* Clear CAN_TSR_RQCPx (rc_w1)*/
+    CANx->TSTS = CAN_TSTS_RQC0 | CAN_TSTS_RQC1 | CAN_TSTS_RQC2;
+    break;
+
+  case CAN_INT_RFFU0:
+    /* Clear CAN_RF0_RFFU0 (rc_w1)*/
+    CANx->RF0 = CAN_RF0_RFFU0;
+    break;
+
+  case CAN_INT_RFOV0:
+    /* Clear CAN_RF0_RFOV0 (rc_w1)*/
+    CANx->RF0 = CAN_RF0_RFOV0;
+    break;
+
+  case CAN_INT_RFFU1:
+    /* Clear CAN_RF1_RFFU1 (rc_w1)*/
+    CANx->RF1 = CAN_RF1_RFFU1;
+    break;
+
+  case CAN_INT_RFOV1:
+    /* Clear CAN_RF1_RFOV1 (rc_w1)*/
+    CANx->RF1 = CAN_RF1_RFOV1;
+    break;
+
+  case CAN_INT_WK:
+    /* Clear CAN_MSTS_WKIT (rc_w1)*/
+    CANx->MSTS = CAN_MSTS_WKIT;
+    break;
+
+  case CAN_INT_SAK:
+    /* Clear CAN_MSTS_SAKIT (rc_w1)*/
+    CANx->MSTS = CAN_MSTS_SAKIT;
+    break;
+
+  case CAN_INT_ERG:
+    /* Clear CAN_MSTS_ERIT (rc_w1) */
+    CANx->MSTS = CAN_MSTS_ERIT;
+    /* Note : the corresponding Flag is cleared by hardware depending
+              of the CAN Bus status*/
+    break;
+
+  case CAN_INT_ERP:
+    /* Clear CAN_MSTS_ERIT (rc_w1) */
+    CANx->MSTS = CAN_MSTS_ERIT;
+    /* Note : the corresponding Flag is cleared by hardware depending
+              of the CAN Bus status*/
+    break;
+
+  case CAN_INT_BU:
+    /* Clear CAN_MSTS_ERIT (rc_w1) */
+    CANx->MSTS = CAN_MSTS_ERIT;
+    /* Note : the corresponding Flag is cleared by hardware depending
+              of the CAN Bus status*/
+    break;
+
+  case CAN_INT_LEC:
+    /*  Clear LEC bits */
+    CANx->ESTS = RESET;
+    /* Clear CAN_MSTS_ERIT (rc_w1) */
+    CANx->MSTS = CAN_MSTS_ERIT;
+    break;
+
+  case CAN_INT_ERR:
+    /*Clear LEC bits */
+    CANx->ESTS = RESET;
+    /* Clear CAN_MSTS_ERIT (rc_w1) */
+    CANx->MSTS = CAN_MSTS_ERIT;
+    /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending
+            of the CAN Bus status*/
+    break;
+
+  default :
+    break;
+  }
+}
+
+/**
+  * @brief  Checks whether the CAN interrupt has occurred or not.
+  * @param  CAN_Reg: specifies the CAN interrupt register to check.
+  * @param  It_Bit:  specifies the interrupt source bit to check.
+  * @retval The new state of the CAN Interrupt (SET or RESET).
+  */
+static ITStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t It_Bit)
+{
+  ITStatus pendingbitstatus = RESET;
+
+  if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
+  {
+    /* CAN_INT is set */
+    pendingbitstatus = SET;
+  }
+  else
+  {
+    /* CAN_INT is reset */
+    pendingbitstatus = RESET;
+  }
+
+  return pendingbitstatus;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_comp.c

@@ -0,0 +1,449 @@
+/**
+  ******************************************************************************
+  * @file    at32f4xx_comp.c
+  * @author  Artery
+  * @version V1.0.1
+  * @date    20-April-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the comparators (COMP1 and COMP2) peripheral: 
+  *           + Comparators configuration
+  *           + Window mode control
+  *
+  *  @verbatim
+  *
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]           
+   
+         The device integrates two analog comparators COMP1 and COMP2:
+         (+) The non inverting input is set to PA1 for COMP1 and to PA3
+             for COMP2.
+  
+         (+) The inverting input can be selected among: DAC_OUT1, 
+             1/4 VREFINT, 1/2 VERFINT, 3/4 VREFINT, VREFINT,
+             I/O (PA0 for COMP1 and PA2 for COMP2)
+  
+         (+) The COMP output is internally is available using COMP_GetOutputState()
+             and can be set on GPIO pins: PA0, PA6, PA11 for COMP1
+             and PA2, PA7, PA12 for COMP2
+  
+         (+) The COMP output can be redirected to embedded timers (TIM1, TIM2
+             and TIM3)
+  
+         (+) The two comparators COMP1 and COMP2 can be combined in window
+             mode and only COMP1 non inverting (PA1) can be used as non-
+             inverting input.
+  
+         (+) The two comparators COMP1 and COMP2 have interrupt capability 
+             with wake-up from Sleep and Stop modes (through the EXTI controller).
+             COMP1 and COMP2 outputs are internally connected to EXTI Line 21
+             and EXTI Line 22 respectively.
+                   
+
+                     ##### How to configure the comparator #####
+ ===============================================================================
+    [..] 
+           This driver provides functions to configure and program the Comparators 
+           of all AT32F4xx devices.
+             
+    [..]   To use the comparator, perform the following steps:
+  
+         (#) Enable the SYSCFG APB clock to get write access to comparator
+             register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+  
+         (#) Configure the comparator input in analog mode using GPIO_Init()
+  
+         (#) Configure the comparator output in alternate function mode
+             using GPIO_Init() and use GPIO_PinAFConfig() function to map the
+             comparator output to the GPIO pin
+  
+         (#) Configure the comparator using COMP_Init() function:
+                 (++)  Select the inverting input
+                 (++)  Select the output polarity  
+                 (++)  Select the output redirection
+                 (++)  Select the hysteresis level
+                 (++)  Select the power mode
+    
+         (#) Enable the comparator using COMP_Cmd() function
+  
+         (#) If required enable the COMP interrupt by configuring and enabling
+             EXTI line in Interrupt mode and selecting the desired sensitivity
+             level using EXTI_Init() function. After that enable the comparator
+             interrupt vector using NVIC_Init() function.
+  
+     @endverbatim
+  *    
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 Artery</center></h2>
+  *
+  * Licensed under Artery Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_comp.h"
+
+/** @addtogroup AT32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup COMP 
+  * @brief COMP driver modules
+  * @{
+  */ 
+
+#if defined (AT32F415xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* CTRLSTS1 register Mask */
+#define COMP_CTRLSTS1_CLEAR_MASK              ((uint32_t)0x00003FFE)
+#define COMP_CTRLSTS2_CLEAR_MASK              ((uint32_t)0x00000003)
+#define COMP_HIGH_PULSE_CLEAR_MASK            ((uint16_t)0x003F) 
+#define COMP_LOW_PULSE_CLEAR_MASK             ((uint16_t)0x003F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup COMP_Private_Functions
+  * @{
+  */
+   
+/**
+  * @brief  Deinitializes COMP peripheral registers to their default reset values.
+  * @note   Deinitialization can't be performed if the COMP configuration is locked.
+  *         To unlock the configuration, perform a system reset.
+  * @param  None
+  * @retval None
+  */
+void COMP_Reset(void)
+{
+  COMP->CTRLSTS1 = ((uint32_t)0x00000000);    /*!< Set COMP_CTRLSTS register to reset value */
+}
+
+/**
+  * @brief  Initializes the COMP peripheral according to the specified parameters
+  *         in COMP_InitStruct
+  * @note   If the selected comparator is locked, initialization can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @note   By default, PA1 is selected as COMP1 non inverting input.
+  *         To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init()
+  * @param  COMP_Selection: the selected comparator. 
+  *          This parameter can be one of the following values:
+  *            @arg COMP1_Selection: COMP1 selected
+  *            @arg COMP2_Selection: COMP2 selected
+  * @param  COMP_InitStruct: pointer to an COMP_InitType structure that contains 
+  *         the configuration information for the specified COMP peripheral.
+  * @retval None
+  */
+void COMP_Init(uint32_t COMP_Selection, COMP_InitType* COMP_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+  assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_INMInput));
+  assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output));
+  assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutPolarity));
+  assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis));
+  assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode));
+
+  /*!< Get the COMP_CTRLSTS register value */
+  tmpreg = COMP->CTRLSTS1;
+
+  /*!< Clear the COMP1SW1, COMPx_IN_SEL, COMPx_OUT_TIM_SEL, COMPx_POL, COMPx_HYST and COMPx_PWR_MODE bits */ 
+  tmpreg &= (uint32_t) ~(COMP_CTRLSTS1_CLEAR_MASK<<COMP_Selection);
+
+  /*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */
+  /*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
+  /*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */
+  /*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */
+  /*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */
+  /*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */   
+  tmpreg |= (uint32_t)((COMP_InitStruct->COMP_INMInput | COMP_InitStruct->COMP_Output |
+                       COMP_InitStruct->COMP_OutPolarity | COMP_InitStruct->COMP_Hysteresis |
+                       COMP_InitStruct->COMP_Mode)<<COMP_Selection);
+
+  /*!< Write to COMP_CTRLSTS1 register */
+  COMP->CTRLSTS1 = tmpreg;  
+}
+
+/**
+  * @brief  Select the non-inverting input for COMP1/COMP2.
+  * @param  COMP_Selection: the selected comparator. 
+  *          This parameter can be one of the following values:
+  *            @arg COMP1_Selection: COMP1 selected
+  *            @arg COMP2_Selection: COMP2 selected
+  * @param  COMP_INPInput: the selected COMP non-inverting input.
+  *         This parameter can be one of the following values:
+  *            @arg COMP_INPInput_00: PA5/PA7 connected to comparator1/2 non-inverting input
+  *            @arg COMP_INPInput_01: PA1/PA3 connected to comparator1/2 non-inverting input
+  *            @arg COMP_INPInput_10: PA0/PA2 connected to comparator1/2 non-inverting input
+  * @retval None
+  */
+void COMP_SelectINPInput(uint32_t COMP_Selection, uint32_t COMP_INPInput)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+  assert_param(IS_COMP_NONINVERTING_INPUT(COMP_INPInput));
+
+  /*!< Get the COMP_CTRLSTS register value */
+  tmpreg = COMP->CTRLSTS2;
+
+  /*!< Clear the COMPxINPSEL bits */ 
+  tmpreg &= (uint32_t) ~(COMP_CTRLSTS2_CLEAR_MASK<<COMP_Selection);
+
+  /*!< Set COMPxINPSEL bits according to COMP_InitStruct->COMP_NonInvertingInput value */
+  tmpreg |= (uint32_t)(COMP_INPInput<<COMP_Selection);
+
+  /*!< Write to COMP_CTRLSTS2 register */
+  COMP->CTRLSTS2 = tmpreg;  
+}
+
+/**
+  * @brief  Fills each COMP_InitStruct member with its default value.
+  * @param  COMP_InitStruct: pointer to an COMP_InitType structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void COMP_StructInit(COMP_InitType* COMP_InitStruct)
+{
+  COMP_InitStruct->COMP_INMInput = COMP_INMInput_1_4VREFINT;
+  COMP_InitStruct->COMP_Output = COMP_Output_None;
+  COMP_InitStruct->COMP_OutPolarity = COMP_OutPolarity_NonInverted;
+  COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No;
+  COMP_InitStruct->COMP_Mode = COMP_Mode_Slow;
+}
+
+/**
+  * @brief  Enable or disable the COMP peripheral.
+  * @note   If the selected comparator is locked, enable/disable can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  COMP_Selection: the selected comparator.
+  *          This parameter can be one of the following values:
+  *            @arg COMP1_Selection: COMP1 selected
+  *            @arg COMP2_Selection: COMP2 selected
+  * @param  NewState: new state of the COMP peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When enabled, the comparator compares the non inverting input with 
+  *         the inverting input and the comparison result is available on comparator output.
+  * @note   When disabled, the comparator doesn't perform comparison and the 
+  *         output level is low.
+  * @retval None
+  */
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected COMP peripheral */
+    COMP->CTRLSTS1 |= (uint32_t) (1<<COMP_Selection);
+  }
+  else
+  {
+    /* Disable the selected COMP peripheral  */
+    COMP->CTRLSTS1 &= (uint32_t)(~((uint32_t)1<<COMP_Selection));
+  }
+}
+
+/**
+  * @brief  Close or Open the SW1 switch.
+  * @note   This switch is solely intended to redirect signals onto high
+  *         impedance input, such as COMP1 non-inverting input (highly resistive switch)
+  * @param  NewState: New state of the analog switch.
+  *          This parameter can be: ENABLE or DISABLE. 
+  * @note   When enabled, the SW1 is closed; PA1 is connected to PA4
+  * @note   When disabled, the SW1 switch is open; PA1 is disconnected from PA4
+  * @retval None
+  */
+void COMP_SwitchCmd(FunctionalState NewState)
+{
+  /* Check the parameter */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Close SW1 switch */
+    COMP->CTRLSTS1 |= (uint32_t) (COMP_CTRLSTS_COMP1SW1);
+  }
+  else
+  {
+    /* Open SW1 switch */
+    COMP->CTRLSTS1 &= (uint32_t)(~COMP_CTRLSTS_COMP1SW1);
+  }
+}
+
+/**
+  * @brief  Return the output level (high or low) of the selected comparator. 
+  * @note   The output level depends on the selected polarity.
+  * @note   If the polarity is not inverted:
+  *          - Comparator output is low when the non-inverting input is at a lower
+  *            voltage than the inverting input
+  *          - Comparator output is high when the non-inverting input is at a higher
+  *            voltage than the inverting input
+  * @note   If the polarity is inverted:
+  *          - Comparator output is high when the non-inverting input is at a lower
+  *            voltage than the inverting input
+  *          - Comparator output is low when the non-inverting input is at a higher
+  *            voltage than the inverting input
+  * @param  COMP_Selection: the selected comparator. 
+  *          This parameter can be one of the following values:
+  *            @arg COMP1_Selection: COMP1 selected
+  *            @arg COMP2_Selection: COMP2 selected  
+  * @retval Returns the selected comparator output level: low or high.
+  *       
+  */
+uint32_t COMP_GetOutputState(uint32_t COMP_Selection)
+{
+  uint32_t compout = 0x0;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+  /* Check if selected comparator output is high */
+  if ((COMP->CTRLSTS1 & (COMP_CTRLSTS_COMP1OUT<<COMP_Selection)) != 0)
+  {
+    compout = COMP_OutputState_High;
+  }
+  else
+  {
+    compout = COMP_OutputState_Low;
+  }
+
+  /* Return the comparator output level */
+  return (uint32_t)(compout);
+}
+
+/**
+  * @brief  Enables or disables the window mode.
+  * @note   In window mode, COMP1 and COMP2 non inverting inputs are connected
+  *         together and only COMP1 non inverting input (PA1) can be used.
+  * @param  NewState: new state of the window mode.
+  *          This parameter can be :
+  *           @arg ENABLE: COMP1 and COMP2 non inverting inputs are connected together.
+  *           @arg DISABLE: OMP1 and COMP2 non inverting inputs are disconnected.
+  * @retval None
+  */
+void COMP_WindowCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the window mode */
+    COMP->CTRLSTS1 |= (uint32_t)COMP_CTRLSTS_WNDWEN;
+  }
+  else
+  {
+    /* Disable the window mode */
+    COMP->CTRLSTS1 &= (uint32_t)(~COMP_CTRLSTS_WNDWEN);
+  }
+}
+
+/**
+  * @brief  Lock the selected comparator (COMP1/COMP2) configuration.
+  * @note   Locking the configuration means that all control bits are read-only.
+  *         To unlock the comparator configuration, perform a system reset.
+  * @param  COMP_Selection: selects the comparator to be locked 
+  *          This parameter can be a value of the following values:
+  *            @arg COMP1_Selection: COMP1 configuration is locked.
+  *            @arg COMP2_Selection: COMP2 configuration is locked.  
+  * @retval None
+  */
+void COMP_LockConfig(uint32_t COMP_Selection)
+{
+  /* Check the parameter */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+  /* Set the lock bit corresponding to selected comparator */
+  COMP->CTRLSTS1 |= (uint32_t) (COMP_CTRLSTS_COMP1LOCK<<COMP_Selection);
+}
+
+/**
+  * @brief  Configure COMP Glitch Filter.
+  * @note   G_FILTER_EN, HIGH_PULSE and LOW_PULSE registers will
+  *         act on both COMP1 and COMP2.
+  * @param  COMP_HighPulseCnt: COMP High Pulse Count.
+  *         This parameter must be a value between 0x00 and 0x3F  
+  * @param  COMP_LowPulseCnt: COMP Low Pulse Count.
+  *         This parameter must be a value between 0x00 and 0x3F  
+  * @param  NewState: new state of the Glitch Filter.
+  *          This parameter can be :
+  *           @arg ENABLE: COMP1 and COMP2 turn on glitch filter.
+  *           @arg DISABLE: COMP1 and COMP2 turn off glitch filter.
+  * @retval None
+  */
+void COMP_FilterConfig(uint16_t COMP_HighPulseCnt, uint16_t COMP_LowPulseCnt, FunctionalState NewState)
+{
+  uint16_t tmphp = 0;
+  uint16_t tmplp = 0;
+  /* Check the parameters */
+  assert_param(IS_COMP_HighPulseCnt(COMP_HighPulseCnt));
+  assert_param(IS_COMP_LowPulseCnt(COMP_LowPulseCnt));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the glitch filter */
+    COMP->G_FILTER_EN |= (uint16_t)COMP_G_FILTER_EN_GFE;
+    
+    tmphp = COMP->HIGH_PULSE;
+    tmplp = COMP->LOW_PULSE;
+    
+    /* Reset the H_PULSE_CNT and L_PULSE_CNT Bits */
+    tmphp &= ~COMP_HIGH_PULSE_CLEAR_MASK;
+    tmplp &= ~COMP_LOW_PULSE_CLEAR_MASK;
+    
+    /* Set the H_PULSE_CNT and L_PULSE_CNT Bits */
+    tmphp |= COMP_HighPulseCnt;
+    tmplp |= COMP_LowPulseCnt;
+    
+    /* Write to COMP HIGH_PULSE and LOW_PULSE */
+    COMP->HIGH_PULSE = tmphp;
+    COMP->LOW_PULSE = tmplp;
+  }
+  else
+  {
+    /* Disable the glitch filter */
+    COMP->G_FILTER_EN &= (uint16_t)(~COMP_G_FILTER_EN_GFE);
+    
+    /* Reset the H_PULSE_CNT and L_PULSE_CNT Bits */
+    COMP->HIGH_PULSE &= ~COMP_HIGH_PULSE_CLEAR_MASK;
+    COMP->LOW_PULSE &= ~COMP_LOW_PULSE_CLEAR_MASK;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* AT32F415xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT Artery *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_crc.c

@@ -0,0 +1,150 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_crc.c
+ * Description  : at32f4xx CRC source file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_crc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRC
+  * @brief CRC driver modules
+  * @{
+  */
+
+/** @defgroup CRC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Resets the CRC Data register (DR).
+  * @param  None
+  * @retval None
+  */
+void CRC_ResetDT(void)
+{
+  /* Reset CRC generator */
+  CRC->CTRL = CRC_CTRL_RST;
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given data word(32-bit).
+  * @param  Data: data word(32-bit) to compute its CRC
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalculateCRC(uint32_t Data)
+{
+  CRC->DT = Data;
+
+  return (CRC->DT);
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
+  * @param  pBuffer: pointer to the buffer containing the data to be computed
+  * @param  BufferLength: length of the buffer to be computed
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalculateBlkCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0;
+
+  for(index = 0; index < BufferLength; index++)
+  {
+    CRC->DT = pBuffer[index];
+  }
+
+  return (CRC->DT);
+}
+
+/**
+  * @brief  Returns the current CRC value.
+  * @param  None
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_GetCRC(void)
+{
+  return (CRC->DT);
+}
+
+/**
+  * @brief  Stores a 8-bit data in the Independent Data(ID) register.
+  * @param  IDValue: 8-bit value to be stored in the ID register
+  * @retval None
+  */
+void CRC_SetIDTReg(uint8_t IDValue)
+{
+  CRC->IDT = IDValue;
+}
+
+/**
+  * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
+  * @param  None
+  * @retval 8-bit value of the ID register
+  */
+uint8_t CRC_GetIDTReg(void)
+{
+  return (CRC->IDT);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_dac.c

@@ -0,0 +1,420 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_dac.c
+ * Description  : at32f4xx DAC source file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_dac.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DAC
+  * @brief DAC driver modules
+  * @{
+  */
+#if defined (AT32F403xx) || defined (AT32F403Axx) || defined (AT32F407xx)
+
+/** @defgroup DAC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Defines
+  * @{
+  */
+
+/* CTRL register Mask */
+#define CTRL_CLEAR_MSK                  ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET                 ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_RST                 ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET                  ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET                  ((uint32_t)0x00000014)
+#define DHR12RD_OFFSET                  ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define ODT_OFFSET                      ((uint32_t)0x0000002C)
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void DAC_Reset(void)
+{
+  /* Enable DAC reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_DAC, ENABLE);
+  /* Release DAC from reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_DAC, DISABLE);
+}
+
+/**
+  * @brief  Initializes the DAC peripheral according to the specified
+  *         parameters in the DAC_InitStruct.
+  * @param  DAC_Channel: the selected DAC channel.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_InitStruct: pointer to a DAC_InitType structure that
+  *        contains the configuration information for the specified DAC channel.
+  * @retval None
+  */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitType* DAC_InitStruct)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+  assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
+  /*---------------------------- DAC CTRL Configuration --------------------------*/
+  /* Get the DAC CTRL value */
+  tmpreg1 = DAC->CTRL;
+  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+  tmpreg1 &= ~(CTRL_CLEAR_MSK << DAC_Channel);
+  /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
+     mask/amplitude for wave generation */
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
+  /* Set WAVEx bits according to DAC_WaveGeneration value */
+  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
+  /* Set BOFFx bit according to DAC_OutputBuffer value */
+  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+             DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
+  /* Calculate CTRL register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << DAC_Channel;
+  /* Write to DAC CTRL */
+  DAC->CTRL = tmpreg1;
+}
+
+/**
+  * @brief  Fills each DAC_InitStruct member with its default value.
+  * @param  DAC_InitStruct : pointer to a DAC_InitType structure which will
+  *         be initialized.
+  * @retval None
+  */
+void DAC_StructInit(DAC_InitType* DAC_InitStruct)
+{
+  /*--------------- Reset DAC init structure parameters values -----------------*/
+  /* Initialize the DAC_Trigger member */
+  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+  /* Initialize the DAC_WaveGeneration member */
+  DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmsk_Bit0;
+  /* Initialize the DAC_OutputBuffer member */
+  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/**
+  * @brief  Enables or disables the specified DAC channel.
+  * @param  DAC_Channel: the selected DAC channel.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the DAC channel.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_Ctrl(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel */
+    DAC->CTRL |= (DAC_CTRL_EN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel */
+    DAC->CTRL &= ~(DAC_CTRL_EN1 << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified DAC channel DMA request.
+  * @param  DAC_Channel: the selected DAC channel.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel DMA request.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_DMACtrl(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel DMA request */
+    DAC->CTRL |= (DAC_CTRL_DMAEN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel DMA request */
+    DAC->CTRL &= ~(DAC_CTRL_DMAEN1 << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel software trigger.
+  * @param  DAC_Channel: the selected DAC channel.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel software trigger.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_SoftwareTriggerCtrl(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for the selected DAC channel */
+    DAC->SWTRG |= (uint32_t)DAC_SWTRG_SWTRG1 << (DAC_Channel >> 4);
+  }
+  else
+  {
+    /* Disable software trigger for the selected DAC channel */
+    DAC->SWTRG &= ~((uint32_t)DAC_SWTRG_SWTRG1 << (DAC_Channel >> 4));
+  }
+}
+
+/**
+  * @brief  Enables or disables simultaneously the two DAC channels software
+  *   triggers.
+  * @param  NewState: new state of the DAC channels software triggers.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_DualSoftwareTriggerCtrl(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for both DAC channels */
+    DAC->SWTRG |= DUAL_SWTRIG_SET ;
+  }
+  else
+  {
+    /* Disable software trigger for both DAC channels */
+    DAC->SWTRG &= DUAL_SWTRIG_RST;
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param  DAC_Channel: the selected DAC channel.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_Wave: Specifies the wave type to enable or disable.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Wave_Noise: noise wave generation
+  *     @arg DAC_Wave_Triangle: triangle wave generation
+  * @param  NewState: new state of the selected DAC channel wave generation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_WaveGenerationCtrl(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_WAVE(DAC_Wave));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected wave generation for the selected DAC channel */
+    DAC->CTRL |= DAC_Wave << DAC_Channel;
+  }
+  else
+  {
+    /* Disable the selected wave generation for the selected DAC channel */
+    DAC->CTRL &= ~(DAC_Wave << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel1.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel1.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Align_8b_Right: 8bit right data alignment selected
+  *     @arg DAC_Align_12b_Left: 12bit left data alignment selected
+  *     @arg DAC_Align_12b_Right: 12bit right data alignment selected
+  * @param  Data : Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12R1_OFFSET + DAC_Align;
+
+  /* Set the DAC channel1 selected data holding register */
+  *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel2.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel2.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Align_8b_Right: 8bit right data alignment selected
+  *     @arg DAC_Align_12b_Left: 12bit left data alignment selected
+  *     @arg DAC_Align_12b_Right: 12bit right data alignment selected
+  * @param  Data : Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12R2_OFFSET + DAC_Align;
+
+  /* Set the DAC channel2 selected data holding register */
+  *(__IO uint32_t *)tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for dual channel
+  *   DAC.
+  * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Align_8b_Right: 8bit right data alignment selected
+  *     @arg DAC_Align_12b_Left: 12bit left data alignment selected
+  *     @arg DAC_Align_12b_Right: 12bit right data alignment selected
+  * @param  Data2: Data for DAC Channel2 to be loaded in the selected data
+  *   holding register.
+  * @param  Data1: Data for DAC Channel1 to be loaded in the selected data
+  *   holding register.
+  * @retval None
+  */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+  uint32_t data = 0, tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+
+  /* Calculate and set dual DAC data holding register value */
+  if (DAC_Align == DAC_Align_8b_Right)
+  {
+    data = ((uint32_t)Data2 << 8) | Data1;
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16) | Data1;
+  }
+
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12RD_OFFSET + DAC_Align;
+
+  /* Set the dual DAC selected data holding register */
+  *(__IO uint32_t *)tmp = data;
+}
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  DAC_Channel: the selected DAC channel.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @retval The selected DAC channel data output value.
+  */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+
+  tmp = (uint32_t) DAC_BASE ;
+  tmp += ODT_OFFSET + ((uint32_t)DAC_Channel >> 2);
+
+  /* Returns the DAC channel data output register value */
+  return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+/**
+  * @}
+  */
+
+#endif /* AT32F403xx || AT32F403Axx || AT32F407xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_dbgmcu.c

@@ -0,0 +1,149 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_dbgmcu.c
+ * Description  : at32f4xx MCUDBG source file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_dbgmcu.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DBGMCU
+  * @brief DBGMCU driver modules
+  * @{
+  */
+
+/** @defgroup DBGMCU_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_Defines
+  * @{
+  */
+
+#define IDCODE_DEVID_MASK           ((uint32_t)0x00000FFF)
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @param  None
+  * @retval Device revision identifier
+  */
+uint32_t MCUDBG_GetRevID(void)
+{
+  return(DBGMCU->IDCR >> 16);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @param  None
+  * @retval Device identifier
+  */
+uint32_t MCUDBG_GetDevID(void)
+{
+  return(DBGMCU->IDCR & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @brief  Configures the specified peripheral and low power mode behavior
+  *   when the MCU under Debug mode.
+  * @param  DBGMCU_Periph: specifies the peripheral and low power mode.
+  *   This parameter can be any combination of the following values:
+  *     @arg MCUDBG_SLEEP: Keep debugger connection during SLEEP mode
+  *     @arg MCUDBG_STOP: Keep debugger connection during STOP mode
+  *     @arg MCUDBG_STANDBY: Keep debugger connection during STANDBY mode
+  *     @arg MCUDBG_IWDG_STOP: Debug IWDG stopped when Core is halted
+  *     @arg MCUDBG_WWDG_STOP: Debug WWDG stopped when Core is halted
+  *     @arg MCUDBG_TMR1_STOP: TMR1 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR2_STOP: TMR2 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR3_STOP: TMR3 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR4_STOP: TMR4 counter stopped when Core is halted
+  *     @arg MCUDBG_CAN1_STOP: Debug CAN1 stopped when Core is halted
+  *     @arg MCUDBG_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
+  *     @arg MCUDBG_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
+  *     @arg MCUDBG_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted
+  *     @arg MCUDBG_TMR5_STOP: TMR5 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR6_STOP: TMR6 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR7_STOP: TMR7 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR8_STOP: TMR8 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR15_STOP: TMR15 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR9_STOP: TMR9 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR10_STOP: TMR10 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR11_STOP: TMR11 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR12_STOP: TMR12 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR13_STOP: TMR13 counter stopped when Core is halted
+  *     @arg MCUDBG_TMR14_STOP: TMR14 counter stopped when Core is halted
+  * @param  NewState: new state of the specified peripheral in Debug mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void MCUDBG_PeriphDebugModeConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_MCUDBG_PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->CTRL |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->CTRL &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_dma.c

@@ -0,0 +1,755 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_dma.c
+ * Description  : at32f4xx DMA source file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_dma.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DMA
+  * @brief DMA driver modules
+  * @{
+  */
+
+/** @defgroup DMA_Private_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Private_Defines
+  * @{
+  */
+
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_CHANNEL1_INT_MASK      ((uint32_t)(DMA_ISTS_GIF1 | DMA_ISTS_TCIF1 | DMA_ISTS_HTIF1 | DMA_ISTS_ERRIF1))
+#define DMA1_CHANNEL2_INT_MASK      ((uint32_t)(DMA_ISTS_GIF2 | DMA_ISTS_TCIF2 | DMA_ISTS_HTIF2 | DMA_ISTS_ERRIF2))
+#define DMA1_CHANNEL3_INT_MASK      ((uint32_t)(DMA_ISTS_GIF3 | DMA_ISTS_TCIF3 | DMA_ISTS_HTIF3 | DMA_ISTS_ERRIF3))
+#define DMA1_CHANNEL4_INT_MASK      ((uint32_t)(DMA_ISTS_GIF4 | DMA_ISTS_TCIF4 | DMA_ISTS_HTIF4 | DMA_ISTS_ERRIF4))
+#define DMA1_CHANNEL5_INT_MASK      ((uint32_t)(DMA_ISTS_GIF5 | DMA_ISTS_TCIF5 | DMA_ISTS_HTIF5 | DMA_ISTS_ERRIF5))
+#define DMA1_CHANNEL6_INT_MASK      ((uint32_t)(DMA_ISTS_GIF6 | DMA_ISTS_TCIF6 | DMA_ISTS_HTIF6 | DMA_ISTS_ERRIF6))
+#define DMA1_CHANNEL7_INT_MASK      ((uint32_t)(DMA_ISTS_GIF7 | DMA_ISTS_TCIF7 | DMA_ISTS_HTIF7 | DMA_ISTS_ERRIF7))
+
+/* DMA2 Channelx interrupt pending bit masks */
+#define DMA2_CHANNEL1_INT_MASK      ((uint32_t)(DMA_ISTS_GIF1 | DMA_ISTS_TCIF1 | DMA_ISTS_HTIF1 | DMA_ISTS_ERRIF1))
+#define DMA2_CHANNEL2_INT_MASK      ((uint32_t)(DMA_ISTS_GIF2 | DMA_ISTS_TCIF2 | DMA_ISTS_HTIF2 | DMA_ISTS_ERRIF2))
+#define DMA2_CHANNEL3_INT_MASK      ((uint32_t)(DMA_ISTS_GIF3 | DMA_ISTS_TCIF3 | DMA_ISTS_HTIF3 | DMA_ISTS_ERRIF3))
+#define DMA2_CHANNEL4_INT_MASK      ((uint32_t)(DMA_ISTS_GIF4 | DMA_ISTS_TCIF4 | DMA_ISTS_HTIF4 | DMA_ISTS_ERRIF4))
+#define DMA2_CHANNEL5_INT_MASK      ((uint32_t)(DMA_ISTS_GIF5 | DMA_ISTS_TCIF5 | DMA_ISTS_HTIF5 | DMA_ISTS_ERRIF5))
+
+/* DMA2 FLAG mask */
+#define FLAG_Mask                   ((uint32_t)0x10000000)
+
+/* DMA registers Masks */
+#define CHCTRL_CLEAR_MASK           ((uint32_t)0xFFFF800F)
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DMAy Channelx registers to their default reset
+  *         values.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @retval None
+  */
+void DMA_Reset(DMA_Channel_Type* DMAy_Channelx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+  /* Disable the selected DMAy Channelx */
+  DMAy_Channelx->CHCTRL &= (uint16_t)(~DMA_CHCTRL1_CHEN);
+
+  /* Reset DMAy Channelx control register */
+  DMAy_Channelx->CHCTRL  = 0;
+
+  /* Reset DMAy Channelx remaining bytes register */
+  DMAy_Channelx->TCNT = 0;
+
+  /* Reset DMAy Channelx peripheral address register */
+  DMAy_Channelx->CPBA  = 0;
+
+  /* Reset DMAy Channelx memory address register */
+  DMAy_Channelx->CMBA = 0;
+
+  if (DMAy_Channelx == DMA1_Channel1)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel1 */
+    DMA1->ICLR |= DMA1_CHANNEL1_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel2)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel2 */
+    DMA1->ICLR |= DMA1_CHANNEL2_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel3)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel3 */
+    DMA1->ICLR |= DMA1_CHANNEL3_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel4)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel4 */
+    DMA1->ICLR |= DMA1_CHANNEL4_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel5)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel5 */
+    DMA1->ICLR |= DMA1_CHANNEL5_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel6)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel6 */
+    DMA1->ICLR |= DMA1_CHANNEL6_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel7)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel7 */
+    DMA1->ICLR |= DMA1_CHANNEL7_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel1)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel1 */
+    DMA2->ICLR |= DMA2_CHANNEL1_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel2)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel2 */
+    DMA2->ICLR |= DMA2_CHANNEL2_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel3)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel3 */
+    DMA2->ICLR |= DMA2_CHANNEL3_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel4)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel4 */
+    DMA2->ICLR |= DMA2_CHANNEL4_INT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel5)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel5 */
+    DMA2->ICLR |= DMA2_CHANNEL5_INT_MASK;
+  }
+}
+
+/**
+  * @brief  Initializes the DMAy Channelx according to the specified
+  *         parameters in the DMA_InitStruct.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  DMA_InitStruct: pointer to a DMA_InitType structure that
+  *         contains the configuration information for the specified DMA Channel.
+  * @retval None
+  */
+void DMA_Init(DMA_Channel_Type* DMAy_Channelx, DMA_InitType* DMA_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_Direction));
+  assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_WIDTH(DMA_InitStruct->DMA_PeripheralDataWidth));
+  assert_param(IS_DMA_MEMORY_DATA_WIDTH(DMA_InitStruct->DMA_MemoryDataWidth));
+  assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+  assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+  assert_param(IS_DMA_MTOM_STATE(DMA_InitStruct->DMA_MTOM));
+
+  /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
+  /* Get the DMAy_Channelx CCR value */
+  tmpreg = DMAy_Channelx->CHCTRL;
+  /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+  tmpreg &= CHCTRL_CLEAR_MASK;
+  /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+  /* Set DIR bit according to DMA_DIR value */
+  /* Set CIRC bit according to DMA_Mode value */
+  /* Set PINC bit according to DMA_PeripheralInc value */
+  /* Set MINC bit according to DMA_MemoryInc value */
+  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+  /* Set MSIZE bits according to DMA_MemoryDataSize value */
+  /* Set PL bits according to DMA_Priority value */
+  /* Set the MEM2MEM bit according to DMA_M2M value */
+  tmpreg |= DMA_InitStruct->DMA_Direction | DMA_InitStruct->DMA_Mode |
+            DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+            DMA_InitStruct->DMA_PeripheralDataWidth | DMA_InitStruct->DMA_MemoryDataWidth |
+            DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_MTOM;
+
+  /* Write to DMAy Channelx CCR */
+  DMAy_Channelx->CHCTRL = tmpreg;
+
+  /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
+  /* Write to DMAy Channelx CNDTR */
+  DMAy_Channelx->TCNT = DMA_InitStruct->DMA_BufferSize;
+
+  /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
+  /* Write to DMAy Channelx CPAR */
+  DMAy_Channelx->CPBA = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+  /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
+  /* Write to DMAy Channelx CMAR */
+  DMAy_Channelx->CMBA = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/**
+  * @brief  Initializes the DMAy flexible function according to the specified
+  *         parameters.
+  * @param  Flex_Channelx: where x can be 1 to 7 for DMA1 or DMA2.
+  * @param  Hardware_ID: Every peripheral have specified Hardware_ID.
+  * @retval None
+  */
+void DMA_Flexible_Config(DMA_Type* DMAx,uint8_t Flex_Channelx,uint8_t Hardware_ID)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_CHANNELS(Flex_Channelx));	
+  assert_param(IS_DMA_ALL_HARDWARE_ID(Hardware_ID));		
+	/* Initialize the DMA flexible function */
+	DMAx->DMA_SRC_SEL1 &= (uint32_t)(~DMA_FLEX_FUNCTION_EN);
+	DMAx->DMA_SRC_SEL1 |= (uint32_t)(DMA_FLEX_FUNCTION_EN);
+	/* Set the Hardware_ID for DMA_Channel */
+	if(Flex_Channelx == Flex_Channel1)/* channel1 */
+	{ 
+		DMAx->DMA_SRC_SEL0 &= (uint32_t)(~0xFF);
+		DMAx->DMA_SRC_SEL0 |= (uint32_t)(Hardware_ID);
+	}
+	else if(Flex_Channelx == Flex_Channel2)/* channel2 */
+	{
+		DMAx->DMA_SRC_SEL0 &= (uint32_t)(~(0xFF<<8));
+		DMAx->DMA_SRC_SEL0 |= (uint32_t)((Hardware_ID<<8));
+	}
+	else if(Flex_Channelx == Flex_Channel3)/* channel3 */
+	{
+		DMAx->DMA_SRC_SEL0 &= (uint32_t)(~(0xFF<<16));
+		DMAx->DMA_SRC_SEL0 |= (uint32_t)((Hardware_ID<<16));		
+	}
+	else if(Flex_Channelx == Flex_Channel4)/* channel5 */
+	{
+		DMAx->DMA_SRC_SEL0 &= (uint32_t)(~((~0x00)<<24));
+		DMAx->DMA_SRC_SEL0 |= (uint32_t)((Hardware_ID<<24));			
+	}	
+	else if(Flex_Channelx == Flex_Channel5)/* channel5 */
+	{
+		DMAx->DMA_SRC_SEL1 &= (uint32_t)(~0xFF);
+		DMAx->DMA_SRC_SEL1 |= (uint32_t)(Hardware_ID);		
+	}	
+	else if(Flex_Channelx == Flex_Channel6)/* channel6 */
+	{
+		DMAx->DMA_SRC_SEL1 &= (uint32_t)(~(0xFF<<8));
+		DMAx->DMA_SRC_SEL1 |= (uint32_t)((Hardware_ID<<8));		
+	}	
+	else if(Flex_Channelx == Flex_Channel7)/* channel7 */
+	{
+		DMAx->DMA_SRC_SEL1 &= (uint32_t)(~(0xFF<<16));
+		DMAx->DMA_SRC_SEL1 |= (uint32_t)((Hardware_ID<<16));		
+	}
+}
+
+/**
+  * @brief  Fills each DMA_InitStruct member with its default value.
+  * @param  DMA_InitStruct : pointer to a DMA_InitType structure which will
+  *         be initialized.
+  * @retval None
+  */
+void DMA_DefaultInitParaConfig(DMA_InitType* DMA_InitStruct)
+{
+  /*-------------- Reset DMA init structure parameters values ------------------*/
+  /* Initialize the DMA_PeripheralBaseAddr member */
+  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+  /* Initialize the DMA_MemoryBaseAddr member */
+  DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+  /* Initialize the DMA_DIR member */
+  DMA_InitStruct->DMA_Direction = DMA_DIR_PERIPHERALSRC;
+  /* Initialize the DMA_BufferSize member */
+  DMA_InitStruct->DMA_BufferSize = 0;
+  /* Initialize the DMA_PeripheralInc member */
+  DMA_InitStruct->DMA_PeripheralInc = DMA_PERIPHERALINC_DISABLE;
+  /* Initialize the DMA_MemoryInc member */
+  DMA_InitStruct->DMA_MemoryInc = DMA_MEMORYINC_DISABLE;
+  /* Initialize the DMA_PeripheralDataSize member */
+  DMA_InitStruct->DMA_PeripheralDataWidth = DMA_PERIPHERALDATAWIDTH_BYTE;
+  /* Initialize the DMA_MemoryDataSize member */
+  DMA_InitStruct->DMA_MemoryDataWidth = DMA_MEMORYDATAWIDTH_BYTE;
+  /* Initialize the DMA_Mode member */
+  DMA_InitStruct->DMA_Mode = DMA_MODE_NORMAL;
+  /* Initialize the DMA_Priority member */
+  DMA_InitStruct->DMA_Priority = DMA_PRIORITY_LOW;
+  /* Initialize the DMA_M2M member */
+  DMA_InitStruct->DMA_MTOM = DMA_MEMTOMEM_DISABLE;
+}
+
+/**
+  * @brief  Enables or disables the specified DMAy Channelx.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  NewState: new state of the DMAy Channelx.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_ChannelEnable(DMA_Channel_Type* DMAy_Channelx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMAy Channelx */
+    DMAy_Channelx->CHCTRL |= DMA_CHCTRL1_CHEN;
+  }
+  else
+  {
+    /* Disable the selected DMAy Channelx */
+    DMAy_Channelx->CHCTRL &= (uint16_t)(~DMA_CHCTRL1_CHEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified DMAy Channelx interrupts.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  DMA_INT: specifies the DMA interrupts sources to be enabled
+  *   or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg DMA_INT_TC:  Transfer complete interrupt mask
+  *     @arg DMA_INT_HT:  Half transfer interrupt mask
+  *     @arg DMA_INT_ERR:  Transfer error interrupt mask
+  * @param  NewState: new state of the specified DMA interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_INTConfig(DMA_Channel_Type* DMAy_Channelx, uint32_t DMA_INT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_DMA_CONFIG_INT(DMA_INT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA interrupts */
+    DMAy_Channelx->CHCTRL |= DMA_INT;
+  }
+  else
+  {
+    /* Disable the selected DMA interrupts */
+    DMAy_Channelx->CHCTRL &= ~DMA_INT;
+  }
+}
+
+/**
+  * @brief  Sets the number of data units in the current DMAy Channelx transfer.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  DataNumber: The number of data units in the current DMAy Channelx
+  *         transfer.
+  * @note   This function can only be used when the DMAy_Channelx is disabled.
+  * @retval None.
+  */
+void DMA_SetCurrDataCounter(DMA_Channel_Type* DMAy_Channelx, uint16_t DataNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+  /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
+  /* Write to DMAy Channelx CNDTR */
+  DMAy_Channelx->TCNT = DataNumber;
+}
+
+/**
+  * @brief  Returns the number of remaining data units in the current
+  *         DMAy Channelx transfer.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @retval The number of remaining data units in the current DMAy Channelx
+  *         transfer.
+  */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_Type* DMAy_Channelx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  /* Return the number of remaining data units for DMAy Channelx */
+  return ((uint16_t)(DMAy_Channelx->TCNT));
+}
+
+/**
+  * @brief  Checks whether the specified DMAy Channelx flag is set or not.
+  * @param  DMAy_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+  *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+  *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+  *     @arg DMA1_FLAG_ERR1: DMA1 Channel1 transfer error flag.
+  *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+  *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+  *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+  *     @arg DMA1_FLAG_ERR2: DMA1 Channel2 transfer error flag.
+  *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+  *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+  *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+  *     @arg DMA1_FLAG_ERR3: DMA1 Channel3 transfer error flag.
+  *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+  *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+  *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+  *     @arg DMA1_FLAG_ERR4: DMA1 Channel4 transfer error flag.
+  *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+  *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+  *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+  *     @arg DMA1_FLAG_ERR5: DMA1 Channel5 transfer error flag.
+  *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+  *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+  *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+  *     @arg DMA1_FLAG_ERR6: DMA1 Channel6 transfer error flag.
+  *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+  *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+  *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+  *     @arg DMA1_FLAG_ERR7: DMA1 Channel7 transfer error flag.
+  *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+  *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+  *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+  *     @arg DMA2_FLAG_ERR1: DMA2 Channel1 transfer error flag.
+  *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+  *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+  *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+  *     @arg DMA2_FLAG_ERR2: DMA2 Channel2 transfer error flag.
+  *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+  *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+  *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+  *     @arg DMA2_FLAG_ERR3: DMA2 Channel3 transfer error flag.
+  *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+  *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+  *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+  *     @arg DMA2_FLAG_ERR4: DMA2 Channel4 transfer error flag.
+  *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+  *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+  *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+  *     @arg DMA2_FLAG_ERR5: DMA2 Channel5 transfer error flag.
+  * @retval The new state of DMAy_FLAG (SET or RESET).
+  */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
+
+  /* Calculate the used DMAy */
+  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Get DMA2 ISR register value */
+    tmpreg = DMA2->ISTS ;
+  }
+  else
+  {
+    /* Get DMA1 ISR register value */
+    tmpreg = DMA1->ISTS ;
+  }
+
+  /* Check the status of the specified DMAy flag */
+  if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
+  {
+    /* DMAy_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMAy_FLAG is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the DMAy_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DMAy Channelx's pending flags.
+  * @param  DMAy_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination (for the same DMA) of the following values:
+  *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+  *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+  *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+  *     @arg DMA1_FLAG_ERR1: DMA1 Channel1 transfer error flag.
+  *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+  *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+  *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+  *     @arg DMA1_FLAG_ERR2: DMA1 Channel2 transfer error flag.
+  *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+  *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+  *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+  *     @arg DMA1_FLAG_ERR3: DMA1 Channel3 transfer error flag.
+  *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+  *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+  *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+  *     @arg DMA1_FLAG_ERR4: DMA1 Channel4 transfer error flag.
+  *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+  *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+  *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+  *     @arg DMA1_FLAG_ERR5: DMA1 Channel5 transfer error flag.
+  *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+  *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+  *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+  *     @arg DMA1_FLAG_ERR6: DMA1 Channel6 transfer error flag.
+  *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+  *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+  *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+  *     @arg DMA1_FLAG_ERR7: DMA1 Channel7 transfer error flag.
+  *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+  *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+  *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+  *     @arg DMA2_FLAG_ERR1: DMA2 Channel1 transfer error flag.
+  *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+  *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+  *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+  *     @arg DMA2_FLAG_ERR2: DMA2 Channel2 transfer error flag.
+  *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+  *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+  *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+  *     @arg DMA2_FLAG_ERR3: DMA2 Channel3 transfer error flag.
+  *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+  *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+  *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+  *     @arg DMA2_FLAG_ERR4: DMA2 Channel4 transfer error flag.
+  *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+  *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+  *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+  *     @arg DMA2_FLAG_ERR5: DMA2 Channel5 transfer error flag.
+  * @retval None
+  */
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
+
+  /* Calculate the used DMAy */
+  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Clear the selected DMAy flags */
+    DMA2->ICLR = DMAy_FLAG;
+  }
+  else
+  {
+    /* Clear the selected DMAy flags */
+    DMA1->ICLR = DMAy_FLAG;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DMAy Channelx interrupt has occurred or not.
+  * @param  DMAy_INT: specifies the DMAy interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg DMA1_INT_GL1: DMA1 Channel1 global interrupt.
+  *     @arg DMA1_INT_TC1: DMA1 Channel1 transfer complete interrupt.
+  *     @arg DMA1_INT_HT1: DMA1 Channel1 half transfer interrupt.
+  *     @arg DMA1_INT_ERR1: DMA1 Channel1 transfer error interrupt.
+  *     @arg DMA1_INT_GL2: DMA1 Channel2 global interrupt.
+  *     @arg DMA1_INT_TC2: DMA1 Channel2 transfer complete interrupt.
+  *     @arg DMA1_INT_HT2: DMA1 Channel2 half transfer interrupt.
+  *     @arg DMA1_INT_ERR2: DMA1 Channel2 transfer error interrupt.
+  *     @arg DMA1_INT_GL3: DMA1 Channel3 global interrupt.
+  *     @arg DMA1_INT_TC3: DMA1 Channel3 transfer complete interrupt.
+  *     @arg DMA1_INT_HT3: DMA1 Channel3 half transfer interrupt.
+  *     @arg DMA1_INT_ERR3: DMA1 Channel3 transfer error interrupt.
+  *     @arg DMA1_INT_GL4: DMA1 Channel4 global interrupt.
+  *     @arg DMA1_INT_TC4: DMA1 Channel4 transfer complete interrupt.
+  *     @arg DMA1_INT_HT4: DMA1 Channel4 half transfer interrupt.
+  *     @arg DMA1_INT_ERR4: DMA1 Channel4 transfer error interrupt.
+  *     @arg DMA1_INT_GL5: DMA1 Channel5 global interrupt.
+  *     @arg DMA1_INT_TC5: DMA1 Channel5 transfer complete interrupt.
+  *     @arg DMA1_INT_HT5: DMA1 Channel5 half transfer interrupt.
+  *     @arg DMA1_INT_ERR5: DMA1 Channel5 transfer error interrupt.
+  *     @arg DMA1_INT_GL6: DMA1 Channel6 global interrupt.
+  *     @arg DMA1_INT_TC6: DMA1 Channel6 transfer complete interrupt.
+  *     @arg DMA1_INT_HT6: DMA1 Channel6 half transfer interrupt.
+  *     @arg DMA1_INT_ERR6: DMA1 Channel6 transfer error interrupt.
+  *     @arg DMA1_INT_GL7: DMA1 Channel7 global interrupt.
+  *     @arg DMA1_INT_TC7: DMA1 Channel7 transfer complete interrupt.
+  *     @arg DMA1_INT_HT7: DMA1 Channel7 half transfer interrupt.
+  *     @arg DMA1_INT_ERR7: DMA1 Channel7 transfer error interrupt.
+  *     @arg DMA2_INT_GL1: DMA2 Channel1 global interrupt.
+  *     @arg DMA2_INT_TC1: DMA2 Channel1 transfer complete interrupt.
+  *     @arg DMA2_INT_HT1: DMA2 Channel1 half transfer interrupt.
+  *     @arg DMA2_INT_ERR1: DMA2 Channel1 transfer error interrupt.
+  *     @arg DMA2_INT_GL2: DMA2 Channel2 global interrupt.
+  *     @arg DMA2_INT_TC2: DMA2 Channel2 transfer complete interrupt.
+  *     @arg DMA2_INT_HT2: DMA2 Channel2 half transfer interrupt.
+  *     @arg DMA2_INT_ERR2: DMA2 Channel2 transfer error interrupt.
+  *     @arg DMA2_INT_GL3: DMA2 Channel3 global interrupt.
+  *     @arg DMA2_INT_TC3: DMA2 Channel3 transfer complete interrupt.
+  *     @arg DMA2_INT_HT3: DMA2 Channel3 half transfer interrupt.
+  *     @arg DMA2_INT_ERR3: DMA2 Channel3 transfer error interrupt.
+  *     @arg DMA2_INT_GL4: DMA2 Channel4 global interrupt.
+  *     @arg DMA2_INT_TC4: DMA2 Channel4 transfer complete interrupt.
+  *     @arg DMA2_INT_HT4: DMA2 Channel4 half transfer interrupt.
+  *     @arg DMA2_INT_ERR4: DMA2 Channel4 transfer error interrupt.
+  *     @arg DMA2_INT_GL5: DMA2 Channel5 global interrupt.
+  *     @arg DMA2_INT_TC5: DMA2 Channel5 transfer complete interrupt.
+  *     @arg DMA2_INT_HT5: DMA2 Channel5 half transfer interrupt.
+  *     @arg DMA2_INT_ERR5: DMA2 Channel5 transfer error interrupt.
+  * @retval The new state of DMAy_INT (SET or RESET).
+  */
+ITStatus DMA_GetITStatus(uint32_t DMAy_INT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_GET_INT(DMAy_INT));
+
+  /* Calculate the used DMA */
+  if ((DMAy_INT & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Get DMA2 ISR register value */
+    tmpreg = DMA2->ISTS;
+  }
+  else
+  {
+    /* Get DMA1 ISR register value */
+    tmpreg = DMA1->ISTS;
+  }
+
+  /* Check the status of the specified DMAy interrupt */
+  if ((tmpreg & DMAy_INT) != (uint32_t)RESET)
+  {
+    /* DMAy_INT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMAy_INT is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the DMA_INT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DMAy Channelx's interrupt pending bits.
+  * @param  DMAy_INT: specifies the DMAy interrupt pending bit to clear.
+  *   This parameter can be any combination (for the same DMA) of the following values:
+  *     @arg DMA1_INT_GL1: DMA1 Channel1 global interrupt.
+  *     @arg DMA1_INT_TC1: DMA1 Channel1 transfer complete interrupt.
+  *     @arg DMA1_INT_HT1: DMA1 Channel1 half transfer interrupt.
+  *     @arg DMA1_INT_ERR1: DMA1 Channel1 transfer error interrupt.
+  *     @arg DMA1_INT_GL2: DMA1 Channel2 global interrupt.
+  *     @arg DMA1_INT_TC2: DMA1 Channel2 transfer complete interrupt.
+  *     @arg DMA1_INT_HT2: DMA1 Channel2 half transfer interrupt.
+  *     @arg DMA1_INT_ERR2: DMA1 Channel2 transfer error interrupt.
+  *     @arg DMA1_INT_GL3: DMA1 Channel3 global interrupt.
+  *     @arg DMA1_INT_TC3: DMA1 Channel3 transfer complete interrupt.
+  *     @arg DMA1_INT_HT3: DMA1 Channel3 half transfer interrupt.
+  *     @arg DMA1_INT_ERR3: DMA1 Channel3 transfer error interrupt.
+  *     @arg DMA1_INT_GL4: DMA1 Channel4 global interrupt.
+  *     @arg DMA1_INT_TC4: DMA1 Channel4 transfer complete interrupt.
+  *     @arg DMA1_INT_HT4: DMA1 Channel4 half transfer interrupt.
+  *     @arg DMA1_INT_ERR4: DMA1 Channel4 transfer error interrupt.
+  *     @arg DMA1_INT_GL5: DMA1 Channel5 global interrupt.
+  *     @arg DMA1_INT_TC5: DMA1 Channel5 transfer complete interrupt.
+  *     @arg DMA1_INT_HT5: DMA1 Channel5 half transfer interrupt.
+  *     @arg DMA1_INT_ERR5: DMA1 Channel5 transfer error interrupt.
+  *     @arg DMA1_INT_GL6: DMA1 Channel6 global interrupt.
+  *     @arg DMA1_INT_TC6: DMA1 Channel6 transfer complete interrupt.
+  *     @arg DMA1_INT_HT6: DMA1 Channel6 half transfer interrupt.
+  *     @arg DMA1_INT_ERR6: DMA1 Channel6 transfer error interrupt.
+  *     @arg DMA1_INT_GL7: DMA1 Channel7 global interrupt.
+  *     @arg DMA1_INT_TC7: DMA1 Channel7 transfer complete interrupt.
+  *     @arg DMA1_INT_HT7: DMA1 Channel7 half transfer interrupt.
+  *     @arg DMA1_INT_ERR7: DMA1 Channel7 transfer error interrupt.
+  *     @arg DMA2_INT_GL1: DMA2 Channel1 global interrupt.
+  *     @arg DMA2_INT_TC1: DMA2 Channel1 transfer complete interrupt.
+  *     @arg DMA2_INT_HT1: DMA2 Channel1 half transfer interrupt.
+  *     @arg DMA2_INT_ERR1: DMA2 Channel1 transfer error interrupt.
+  *     @arg DMA2_INT_GL2: DMA2 Channel2 global interrupt.
+  *     @arg DMA2_INT_TC2: DMA2 Channel2 transfer complete interrupt.
+  *     @arg DMA2_INT_HT2: DMA2 Channel2 half transfer interrupt.
+  *     @arg DMA2_INT_ERR2: DMA2 Channel2 transfer error interrupt.
+  *     @arg DMA2_INT_GL3: DMA2 Channel3 global interrupt.
+  *     @arg DMA2_INT_TC3: DMA2 Channel3 transfer complete interrupt.
+  *     @arg DMA2_INT_HT3: DMA2 Channel3 half transfer interrupt.
+  *     @arg DMA2_INT_ERR3: DMA2 Channel3 transfer error interrupt.
+  *     @arg DMA2_INT_GL4: DMA2 Channel4 global interrupt.
+  *     @arg DMA2_INT_TC4: DMA2 Channel4 transfer complete interrupt.
+  *     @arg DMA2_INT_HT4: DMA2 Channel4 half transfer interrupt.
+  *     @arg DMA2_INT_ERR4: DMA2 Channel4 transfer error interrupt.
+  *     @arg DMA2_INT_GL5: DMA2 Channel5 global interrupt.
+  *     @arg DMA2_INT_TC5: DMA2 Channel5 transfer complete interrupt.
+  *     @arg DMA2_INT_HT5: DMA2 Channel5 half transfer interrupt.
+  *     @arg DMA2_INT_ERR5: DMA2 Channel5 transfer error interrupt.
+  * @retval None
+  */
+void DMA_ClearITPendingBit(uint32_t DMAy_INT)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CLEAR_INT(DMAy_INT));
+
+  /* Calculate the used DMAy */
+  if ((DMAy_INT & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Clear the selected DMAy interrupt pending bits */
+    DMA2->ICLR = DMAy_INT;
+  }
+  else
+  {
+    /* Clear the selected DMAy interrupt pending bits */
+    DMA1->ICLR = DMAy_INT;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_ertc.c

@@ -0,0 +1,2456 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_ertc.c
+ * Description  : at32f4xx ERTC source file
+ * Date         : 2018-03-15
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_ertc.h"
+#include "at32f4xx_rcc.h"
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup ERTC 
+  * @brief ERTC driver modules
+  * @{
+  */
+
+#if defined (AT32F415xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Masks Definition */
+#define ERTC_TIME_RESERVED_MASK    ((uint32_t)0x007F7F7F)
+#define ERTC_DATE_RESERVED_MASK    ((uint32_t)0x00FFFF3F) 
+#define ERTC_INIT_MASK             ((uint32_t)0xFFFFFFFF)  
+#define ERTC_RSF_MASK              ((uint32_t)0xFFFFFF5F)
+#define ERTC_FLAGS_MASK            ((uint32_t)(ERTC_FLAG_TSOF | ERTC_FLAG_TSF | ERTC_FLAG_WATF | \
+                                            ERTC_FLAG_ALBF | ERTC_FLAG_ALAF | ERTC_FLAG_INITF | \
+                                            ERTC_FLAG_RSF | ERTC_FLAG_INITS | ERTC_FLAG_WATWF | \
+                                            ERTC_FLAG_ALBWF | ERTC_FLAG_ALAWF | ERTC_FLAG_TP1F | \
+                                            ERTC_FLAG_TP2F | ERTC_FLAG_RECALPDF | ERTC_FLAG_SFP))
+
+#define INITMODE_TMROUT           ((uint32_t) 0x00010000)
+#define SYNCHRO_TMROUT            ((uint32_t) 0x00020000)
+#define RECALPDF_TMROUT           ((uint32_t) 0x00020000)
+#define SFP_TMROUT                ((uint32_t) 0x00001000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint8_t ERTC_ByteToBcd2(uint8_t Value);
+static uint8_t ERTC_Bcd2ToByte(uint8_t Value);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RTC_Private_Functions
+  * @{
+  */ 
+
+
+/**
+  * @brief  Deinitializes the ERTC registers to their default reset values.
+  * @note   This function doesn't reset the ERTC Clock source and ERTC Backup Data
+  *         registers.       
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ERTC registers are deinitialized
+  *          - ERROR: ERTC registers are not deinitialized
+  */
+ErrorStatus ERTC_Reset(void)
+{
+  __IO uint32_t wutcounter = 0x00;
+  uint32_t wutwfstatus = 0x00;
+  ErrorStatus status = ERROR;
+  
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (ERTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }  
+  else
+  {
+    /* Reset TIME, DATE and CTRL registers */
+    ERTC->TIME = (uint32_t)0x00000000;
+    ERTC->DATE = (uint32_t)0x00002101;
+    /* Reset All CTRL bits except CTRL[2:0] */
+    ERTC->CTRL &= (uint32_t)0x00000007;
+  
+    /* Wait till ERTC WUTWF flag is set and if Time out is reached exit */
+    do
+    {
+      wutwfstatus = ERTC->ISTS & ERTC_ISTS_WATWF;
+      wutcounter++;  
+    } while((wutcounter != INITMODE_TMROUT) && (wutwfstatus == 0x00));
+    
+    if ((ERTC->ISTS & ERTC_ISTS_WATWF) == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      /* Reset all ERTC CTRL register bits */
+      ERTC->CTRL &= (uint32_t)0x00000000;
+      ERTC->WATR  = (uint32_t)0x0000FFFF;
+      ERTC->PSC   = (uint32_t)0x007F00FF;
+      ERTC->CAL   = (uint32_t)0x00000000;
+      ERTC->ALA   = (uint32_t)0x00000000;        
+      ERTC->ALB   = (uint32_t)0x00000000;
+      ERTC->SFCTR = (uint32_t)0x00000000;
+      ERTC->CCR   = (uint32_t)0x00000000;
+      ERTC->ALASBS = (uint32_t)0x00000000;
+      ERTC->ALBSBS = (uint32_t)0x00000000;
+      
+      /* Reset ISTS register and exit initialization mode */
+      ERTC->ISTS = (uint32_t)0x00000000;
+      
+      /* Reset Tamper and alternate functions configuration register */
+      ERTC->TPAF = 0x00000000;
+  
+      if(ERTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;      
+      }
+    }
+  }
+  
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF;  
+  
+  return status;
+}
+
+/**
+  * @brief  Initializes the ERTC registers according to the specified parameters 
+  *         in ERTC_InitStruct.
+  * @param  ERTC_InitStruct: pointer to a ERTC_InitType structure that contains 
+  *         the configuration information for the ERTC peripheral.
+  * @note   The ERTC Prescaler register is write protected and can be written in 
+  *         initialization mode only.  
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ERTC registers are initialized
+  *          - ERROR: ERTC registers are not initialized  
+  */
+ErrorStatus ERTC_Init(ERTC_InitType* ERTC_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_ERTC_HOUR_FORMAT(ERTC_InitStruct->ERTC_HourFormat));
+  assert_param(IS_ERTC_ASYNCH_PRDIV(ERTC_InitStruct->ERTC_AsynchPrediv));
+  assert_param(IS_ERTC_SYNCH_PRDIV(ERTC_InitStruct->ERTC_SynchPrediv));
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (ERTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Clear ERTC CTRL FMT Bit */
+    ERTC->CTRL &= ((uint32_t)~(ERTC_CTRL_HFM));
+    /* Set RTC_CR register */
+    ERTC->CTRL |=  ((uint32_t)(ERTC_InitStruct->ERTC_HourFormat));
+  
+    /* Configure the ERTC PSC */
+    ERTC->PSC = (uint32_t)(ERTC_InitStruct->ERTC_SynchPrediv);
+    ERTC->PSC |= (uint32_t)(ERTC_InitStruct->ERTC_AsynchPrediv << 16);
+
+    /* Exit Initialization mode */
+    ERTC_ExitInitMode();
+
+    status = SUCCESS;    
+  }
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF; 
+  
+  return status;
+}
+
+/**
+  * @brief  Fills each ERTC_InitStruct member with its default value.
+  * @param  ERTC_InitStruct: pointer to a ERTC_InitType structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void ERTC_StructInit(ERTC_InitType* ERTC_InitStruct)
+{
+  /* Initialize the ERTC_HourFormat member */
+  ERTC_InitStruct->ERTC_HourFormat = ERTC_HourFormat_24;
+    
+  /* Initialize the ERTC_AsynchPrediv member */
+  ERTC_InitStruct->ERTC_AsynchPrediv = (uint32_t)0x7F;
+
+  /* Initialize the ERTC_SynchPrediv member */
+  ERTC_InitStruct->ERTC_SynchPrediv = (uint32_t)0xFF; 
+}
+
+/**
+  * @brief  Enables or disables the ERTC registers write protection.
+  * @note   All the ERTC registers are write protected except for RTC_ISR[13:8], 
+  *         RTC_TAFCR and RTC_BKPxR.
+  * @note   Writing a wrong key reactivates the write protection.
+  * @note   The protection mechanism is not affected by system reset.  
+  * @param  NewState: new state of the write protection.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ERTC_WriteProtectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the write protection for ERTC registers */
+    ERTC->WPR = 0xFF;   
+  }
+  else
+  {
+    /* Disable the write protection for ERTC registers */
+    ERTC->WPR = 0xCA;
+    ERTC->WPR = 0x53;    
+  }
+}
+
+/**
+  * @brief  Enters the ERTC Initialization mode.
+  * @note   The ERTC Initialization mode is write protected, use the 
+  *         ERTC_WriteProtectionCmd(DISABLE) before calling this function.    
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ERTC is in Init mode
+  *          - ERROR: ERTC is not in Init mode  
+  */
+ErrorStatus ERTC_EnterInitMode(void)
+{
+  __IO uint32_t initcounter = 0x00;
+  ErrorStatus status = ERROR;
+  uint32_t initstatus = 0x00;
+     
+  /* Check if the Initialization mode is set */
+  if ((ERTC->ISTS & ERTC_ISTS_INITF) == (uint32_t)RESET)
+  {
+    /* Set the Initialization mode */
+    ERTC->ISTS = (uint32_t)ERTC_INIT_MASK;
+    
+    /* Wait till ERTC is in INIT state and if Time out is reached exit */
+    do
+    {
+      initstatus = ERTC->ISTS & ERTC_ISTS_INITF;
+      initcounter++;  
+    } while((initcounter != INITMODE_TMROUT) && (initstatus == 0x00));
+    
+    if ((ERTC->ISTS & ERTC_ISTS_INITF) != RESET)
+    {
+      status = SUCCESS;
+    }
+    else
+    {
+      status = ERROR;
+    }        
+  }
+  else
+  {
+    status = SUCCESS;  
+  } 
+    
+  return (status);  
+}
+
+/**
+  * @brief  Exits the ERTC Initialization mode.
+  * @note   When the initialization sequence is complete, the calendar restarts 
+  *         counting after 4 RTCCLK cycles.  
+  * @note   The ERTC Initialization mode is write protected, use the 
+  *         ERTC_WriteProtectionCmd(DISABLE) before calling this function.      
+  * @param  None
+  * @retval None
+  */
+void ERTC_ExitInitMode(void)
+{ 
+  /* Exit Initialization mode */
+  ERTC->ISTS &= (uint32_t)~ERTC_ISTS_INITM;  
+}
+
+/**
+  * @brief  Waits until the ERTC Time and Date registers (RTC_TR and RTC_DR) are 
+  *         synchronized with ERTC APB clock.
+  * @note   The ERTC Resynchronization mode is write protected, use the 
+  *         ERTC_WriteProtectionCmd(DISABLE) before calling this function. 
+  * @note   To read the calendar through the shadow registers after Calendar 
+  *         initialization, calendar update or after wakeup from low power modes 
+  *         the software must first clear the RSF flag. 
+  *         The software must then wait until it is set again before reading 
+  *         the calendar, which means that the calendar registers have been 
+  *         correctly copied into the RTC_TR and RTC_DR shadow registers.   
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ERTC registers are synchronised
+  *          - ERROR: ERTC registers are not synchronised
+  */
+ErrorStatus ERTC_WaitForSynchro(void)
+{
+  __IO uint32_t synchrocounter = 0;
+  ErrorStatus status = ERROR;
+  uint32_t synchrostatus = 0x00;
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+    
+  /* Clear RSF flag */
+  ERTC->ISTS &= (uint32_t)ERTC_RSF_MASK;
+    
+  /* Wait the registers to be synchronised */
+  do
+  {
+    synchrostatus = ERTC->ISTS & ERTC_ISTS_RSF;
+    synchrocounter++;  
+  } while((synchrocounter != SYNCHRO_TMROUT) && (synchrostatus == 0x00));
+    
+  if ((ERTC->ISTS & ERTC_ISTS_RSF) != RESET)
+  {
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }        
+
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF; 
+    
+  return (status); 
+}
+
+/**
+  * @brief  Enables or disables the ERTC reference clock detection.
+  * @param  NewState: new state of the ERTC reference clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ERTC reference clock detection is enabled
+  *          - ERROR: ERTC reference clock detection is disabled  
+  */
+ErrorStatus ERTC_RefClockCmd(FunctionalState NewState)
+{ 
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+    
+  /* Set Initialization mode */
+  if (ERTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {  
+    if (NewState != DISABLE)
+    {
+      /* Enable the ERTC reference clock detection */
+      ERTC->CTRL |= ERTC_CTRL_RFCKON;   
+    }
+    else
+    {
+      /* Disable the ERTC reference clock detection */
+      ERTC->CTRL &= ~ERTC_CTRL_RFCKON;    
+    }
+    /* Exit Initialization mode */
+    ERTC_ExitInitMode();
+    
+    status = SUCCESS;
+  }
+  
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF;  
+  
+  return status; 
+}
+
+/**
+  * @brief  Enables or Disables the Bypass Shadow feature.
+  * @note   When the Bypass Shadow is enabled the calendar value are taken 
+  *         directly from the Calendar counter.
+  * @param  NewState: new state of the Bypass Shadow feature.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+*/
+void ERTC_BypassShadowCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the BYPSHAD bit */
+    ERTC->CTRL |= (uint8_t)ERTC_CTRL_BYPSHDW;
+  }
+  else
+  {
+    /* Reset the BYPSHAD bit */
+    ERTC->CTRL &= (uint8_t)~ERTC_CTRL_BYPSHDW;
+  }
+
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group2 Time and Date configuration functions
+ *  @brief   Time and Date configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                 ##### Time and Date configuration functions #####
+ ===============================================================================  
+ 
+ [..] This section provide functions allowing to program and read the ERTC Calendar
+      (Time and Date).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set the ERTC current time.
+  * @param  ERTC_Format: specifies the format of the entered parameters.
+  *          This parameter can be  one of the following values:
+  *            @arg ERTC_Format_BIN:  Binary data format 
+  *            @arg ERTC_Format_BCD:  BCD data format
+  * @param  ERTC_TimeStruct: pointer to a ERTC_TimeType structure that contains 
+  *                        the time configuration information for the ERTC.     
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ERTC Time register is configured
+  *          - ERROR: ERTC Time register is not configured
+  */
+ErrorStatus ERTC_SetTimeValue(uint32_t ERTC_Format, ERTC_TimeType* ERTC_TimeStruct)
+{
+  uint32_t tmpreg = 0;
+  ErrorStatus status = ERROR;
+    
+  /* Check the parameters */
+  assert_param(IS_ERTC_FORMAT(ERTC_Format));
+  
+  if (ERTC_Format == ERTC_Format_BIN)
+  {
+    if ((ERTC->CTRL & ERTC_CTRL_HFM) != (uint32_t)RESET)
+    {
+      assert_param(IS_ERTC_HOUR12(ERTC_TimeStruct->ERTC_Hours));
+      assert_param(IS_ERTC_H12(ERTC_TimeStruct->ERTC_AMPM));
+    } 
+    else
+    {
+      ERTC_TimeStruct->ERTC_AMPM = 0x00;
+      assert_param(IS_ERTC_HOUR24(ERTC_TimeStruct->ERTC_Hours));
+    }
+    assert_param(IS_ERTC_MINUTES(ERTC_TimeStruct->ERTC_Minutes));
+    assert_param(IS_ERTC_SECONDS(ERTC_TimeStruct->ERTC_Seconds));
+  }
+  else
+  {
+    if ((ERTC->CTRL & ERTC_CTRL_HFM) != (uint32_t)RESET)
+    {
+      tmpreg = ERTC_Bcd2ToByte(ERTC_TimeStruct->ERTC_Hours);
+      assert_param(IS_ERTC_HOUR12(tmpreg));
+      assert_param(IS_ERTC_H12(ERTC_TimeStruct->ERTC_AMPM)); 
+    } 
+    else
+    {
+      ERTC_TimeStruct->ERTC_AMPM = 0x00;
+      assert_param(IS_ERTC_HOUR24(ERTC_Bcd2ToByte(ERTC_TimeStruct->ERTC_Hours)));
+    }
+    assert_param(IS_ERTC_MINUTES(ERTC_Bcd2ToByte(ERTC_TimeStruct->ERTC_Minutes)));
+    assert_param(IS_ERTC_SECONDS(ERTC_Bcd2ToByte(ERTC_TimeStruct->ERTC_Seconds)));
+  }
+  
+  /* Check the input parameters format */
+  if (ERTC_Format != ERTC_Format_BIN)
+  {
+    tmpreg = (((uint32_t)(ERTC_TimeStruct->ERTC_Hours) << 16) | \
+             ((uint32_t)(ERTC_TimeStruct->ERTC_Minutes) << 8) | \
+             ((uint32_t)ERTC_TimeStruct->ERTC_Seconds) | \
+             ((uint32_t)(ERTC_TimeStruct->ERTC_AMPM) << 16)); 
+  }  
+  else
+  {
+    tmpreg = (uint32_t)(((uint32_t)ERTC_ByteToBcd2(ERTC_TimeStruct->ERTC_Hours) << 16) | \
+                   ((uint32_t)ERTC_ByteToBcd2(ERTC_TimeStruct->ERTC_Minutes) << 8) | \
+                   ((uint32_t)ERTC_ByteToBcd2(ERTC_TimeStruct->ERTC_Seconds)) | \
+                   (((uint32_t)ERTC_TimeStruct->ERTC_AMPM) << 16));
+  }  
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (ERTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Set the RTC_TR register */
+    ERTC->TIME = (uint32_t)(tmpreg & ERTC_TIME_RESERVED_MASK);
+
+    /* Exit Initialization mode */
+    ERTC_ExitInitMode(); 
+
+    /* If  ERTC_CTRL_BYPSHDW bit = 0, wait for synchro else this check is not needed */
+    if ((ERTC->CTRL & ERTC_CTRL_BYPSHDW) == RESET)
+    {
+    if(ERTC_WaitForSynchro() == ERROR)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF; 
+    
+  return status;
+}
+
+/**
+  * @brief  Fills each ERTC_TimeStruct member with its default value
+  *         (Time = 00h:00min:00sec).
+  * @param  ERTC_TimeStruct: pointer to a ERTC_TimeType structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void ERTC_TimeStructInit(ERTC_TimeType* ERTC_TimeStruct)
+{
+  /* Time = 00h:00min:00sec */
+  ERTC_TimeStruct->ERTC_AMPM = ERTC_H12_AM;
+  ERTC_TimeStruct->ERTC_Hours = 0;
+  ERTC_TimeStruct->ERTC_Minutes = 0;
+  ERTC_TimeStruct->ERTC_Seconds = 0; 
+}
+
+/**
+  * @brief  Get the ERTC current Time.
+  * @param  ERTC_Format: specifies the format of the returned parameters.
+  *          This parameter can be  one of the following values:
+  *            @arg ERTC_Format_BIN:  Binary data format 
+  *            @arg ERTC_Format_BCD:  BCD data format
+  * @param  ERTC_TimeStruct: pointer to a ERTC_TimeType structure that will 
+  *                        contain the returned current time configuration.     
+  * @retval None
+  */
+void ERTC_GetTimeValue(uint32_t ERTC_Format, ERTC_TimeType* ERTC_TimeStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ERTC_FORMAT(ERTC_Format));
+
+  /* Get the RTC_TR register */
+  tmpreg = (uint32_t)(ERTC->TIME & ERTC_TIME_RESERVED_MASK); 
+  
+  /* Fill the structure fields with the read parameters */
+  ERTC_TimeStruct->ERTC_Hours = (uint8_t)((tmpreg & (ERTC_TIME_HT | ERTC_TIME_HU)) >> 16);
+  ERTC_TimeStruct->ERTC_Minutes = (uint8_t)((tmpreg & (ERTC_TIME_MT | ERTC_TIME_MU)) >>8);
+  ERTC_TimeStruct->ERTC_Seconds = (uint8_t)(tmpreg & (ERTC_TIME_ST | ERTC_TIME_SU));
+  ERTC_TimeStruct->ERTC_AMPM = (uint8_t)((tmpreg & (ERTC_TIME_AMPM)) >> 16);  
+
+  /* Check the input parameters format */
+  if (ERTC_Format == ERTC_Format_BIN)
+  {
+    /* Convert the structure parameters to Binary format */
+    ERTC_TimeStruct->ERTC_Hours = (uint8_t)ERTC_Bcd2ToByte(ERTC_TimeStruct->ERTC_Hours);
+    ERTC_TimeStruct->ERTC_Minutes = (uint8_t)ERTC_Bcd2ToByte(ERTC_TimeStruct->ERTC_Minutes);
+    ERTC_TimeStruct->ERTC_Seconds = (uint8_t)ERTC_Bcd2ToByte(ERTC_TimeStruct->ERTC_Seconds);   
+  }
+}
+
+/**
+  * @brief  Gets the ERTC current Calendar Sub seconds value.
+  * @note   This function freeze the Time and Date registers after reading the 
+  *         SBSR register.
+  * @param  None
+  * @retval ERTC current Calendar Sub seconds value.
+  */
+uint32_t ERTC_GetSubSecondValue(void)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Get sub seconds values from the correspondent registers*/
+  tmpreg = (uint32_t)(ERTC->SBSR);
+  
+  /* Read DATE register to unfroze calendar registers */
+  (void) (ERTC->DATE);
+  
+  return (tmpreg);
+}
+
+/**
+  * @brief  Set the ERTC current date.
+  * @param  ERTC_Format: specifies the format of the entered parameters.
+  *          This parameter can be  one of the following values:
+  *            @arg ERTC_Format_BIN:  Binary data format 
+  *            @arg ERTC_Format_BCD:  BCD data format
+  * @param  ERTC_DateStruct: pointer to a ERTC_DateType structure that contains 
+  *                         the date configuration information for the ERTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ERTC Date register is configured
+  *          - ERROR: ERTC Date register is not configured
+  */
+ErrorStatus ERTC_SetDateValue(uint32_t ERTC_Format, ERTC_DateType* ERTC_DateStruct)
+{
+  uint32_t tmpreg = 0;
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_ERTC_FORMAT(ERTC_Format));
+
+  if ((ERTC_Format == ERTC_Format_BIN) && ((ERTC_DateStruct->ERTC_Month & 0x10) == 0x10))
+  {
+    ERTC_DateStruct->ERTC_Month = (ERTC_DateStruct->ERTC_Month & (uint32_t)~(0x10)) + 0x0A;
+  }  
+  if (ERTC_Format == ERTC_Format_BIN)
+  {
+    assert_param(IS_ERTC_YEAR(ERTC_DateStruct->ERTC_Year));
+    assert_param(IS_ERTC_MONTH(ERTC_DateStruct->ERTC_Month));
+    assert_param(IS_ERTC_DATE(ERTC_DateStruct->ERTC_Date));
+  }
+  else
+  {
+    assert_param(IS_ERTC_YEAR(ERTC_Bcd2ToByte(ERTC_DateStruct->ERTC_Year)));
+    tmpreg = ERTC_Bcd2ToByte(ERTC_DateStruct->ERTC_Month);
+    assert_param(IS_ERTC_MONTH(tmpreg));
+    tmpreg = ERTC_Bcd2ToByte(ERTC_DateStruct->ERTC_Date);
+    assert_param(IS_ERTC_DATE(tmpreg));
+  }
+  assert_param(IS_ERTC_WEEK(ERTC_DateStruct->ERTC_WeekDay));
+
+  /* Check the input parameters format */
+  if (ERTC_Format != ERTC_Format_BIN)
+  {
+    tmpreg = ((((uint32_t)ERTC_DateStruct->ERTC_Year) << 16) | \
+              (((uint32_t)ERTC_DateStruct->ERTC_Month) << 8) | \
+              ((uint32_t)ERTC_DateStruct->ERTC_Date) | \
+              (((uint32_t)ERTC_DateStruct->ERTC_WeekDay) << 13)); 
+  }  
+  else
+  {
+    tmpreg = (((uint32_t)ERTC_ByteToBcd2(ERTC_DateStruct->ERTC_Year) << 16) | \
+              ((uint32_t)ERTC_ByteToBcd2(ERTC_DateStruct->ERTC_Month) << 8) | \
+              ((uint32_t)ERTC_ByteToBcd2(ERTC_DateStruct->ERTC_Date)) | \
+              ((uint32_t)ERTC_DateStruct->ERTC_WeekDay << 13));
+  }
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (ERTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Set the RTC_DR register */
+    ERTC->DATE = (uint32_t)(tmpreg & ERTC_DATE_RESERVED_MASK);
+
+    /* Exit Initialization mode */
+    ERTC_ExitInitMode(); 
+
+    /* If  ERTC_CTRL_BYPSHDW bit = 0, wait for synchro else this check is not needed */
+    if ((ERTC->CTRL & ERTC_CTRL_BYPSHDW) == RESET)
+    {
+    if(ERTC_WaitForSynchro() == ERROR)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF;   
+  
+  return status;
+}
+
+/**
+  * @brief  Fills each ERTC_DateStruct member with its default value
+  *         (Monday, January 01 xx00).
+  * @param  ERTC_DateStruct: pointer to a ERTC_DateType structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void ERTC_DateStructInit(ERTC_DateType* ERTC_DateStruct)
+{
+  /* Monday, January 01 xx00 */
+  ERTC_DateStruct->ERTC_WeekDay = ERTC_Week_MON;
+  ERTC_DateStruct->ERTC_Date = 1;
+  ERTC_DateStruct->ERTC_Month = ERTC_Month_JAN;
+  ERTC_DateStruct->ERTC_Year = 0;
+}
+
+/**
+  * @brief  Get the ERTC current date. 
+  * @param  ERTC_Format: specifies the format of the returned parameters.
+  *          This parameter can be one of the following values:
+  *            @arg ERTC_Format_BIN: Binary data format 
+  *            @arg ERTC_Format_BCD: BCD data format
+  * @param ERTC_DateStruct: pointer to a ERTC_DateType structure that will 
+  *                        contain the returned current date configuration.     
+  * @retval None
+  */
+void ERTC_GetDateValue(uint32_t ERTC_Format, ERTC_DateType* ERTC_DateStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ERTC_FORMAT(ERTC_Format));
+  
+  /* Get the RTC_TR register */
+  tmpreg = (uint32_t)(ERTC->DATE & ERTC_DATE_RESERVED_MASK); 
+
+  /* Fill the structure fields with the read parameters */
+  ERTC_DateStruct->ERTC_Year = (uint8_t)((tmpreg & (ERTC_DATE_YT | ERTC_DATE_YU)) >> 16);
+  ERTC_DateStruct->ERTC_Month = (uint8_t)((tmpreg & (ERTC_DATE_MT | ERTC_DATE_MU)) >> 8);
+  ERTC_DateStruct->ERTC_Date = (uint8_t)(tmpreg & (ERTC_DATE_DT | ERTC_DATE_DU));
+  ERTC_DateStruct->ERTC_WeekDay = (uint8_t)((tmpreg & (ERTC_DATE_WK)) >> 13);
+
+  /* Check the input parameters format */
+  if (ERTC_Format == ERTC_Format_BIN)
+  {
+    /* Convert the structure parameters to Binary format */
+    ERTC_DateStruct->ERTC_Year = (uint8_t)ERTC_Bcd2ToByte(ERTC_DateStruct->ERTC_Year);
+    ERTC_DateStruct->ERTC_Month = (uint8_t)ERTC_Bcd2ToByte(ERTC_DateStruct->ERTC_Month);
+    ERTC_DateStruct->ERTC_Date = (uint8_t)ERTC_Bcd2ToByte(ERTC_DateStruct->ERTC_Date);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group3 Alarms configuration functions
+ *  @brief   Alarms (Alarm A and Alarm B) configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+         ##### Alarms A and B configuration functions #####
+ ===============================================================================  
+ 
+ [..] This section provide functions allowing to program and read the ERTC Alarms.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set the specified ERTC Alarm.
+  * @note   The Alarm register can only be written when the corresponding Alarm
+  *         is disabled (Use the ERTC_AlarmCmd(DISABLE)).    
+  * @param  ERTC_Format: specifies the format of the returned parameters.
+  *          This parameter can be one of the following values:
+  *            @arg ERTC_Format_BIN: Binary data format 
+  *            @arg ERTC_Format_BCD: BCD data format
+  * @param  ERTC_Alarm: specifies the alarm to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg ERTC_AlA: to select Alarm A
+  *            @arg ERTC_AlB: to select Alarm B  
+  * @param  ERTC_AlarmStruct: pointer to a ERTC_AlarmType structure that 
+  *                          contains the alarm configuration parameters.     
+  * @retval None
+  */
+void ERTC_SetAlarmValue(uint32_t ERTC_Format, uint32_t ERTC_Alarm, ERTC_AlarmType* ERTC_AlarmStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ERTC_FORMAT(ERTC_Format));
+  assert_param(IS_ERTC_ALARM(ERTC_Alarm));
+  assert_param(IS_ALARM_MASK(ERTC_AlarmStruct->ERTC_AlarmMask));
+  assert_param(IS_ERTC_ALARM_DATE_WEEK_SEL(ERTC_AlarmStruct->ERTC_AlarmDateWeekSel));
+
+  if (ERTC_Format == ERTC_Format_BIN)
+  {
+    if ((ERTC->CTRL & ERTC_CTRL_HFM) != (uint32_t)RESET)
+    {
+      assert_param(IS_ERTC_HOUR12(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Hours));
+      assert_param(IS_ERTC_H12(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_AMPM));
+    } 
+    else
+    {
+      ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_AMPM = 0x00;
+      assert_param(IS_ERTC_HOUR24(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Hours));
+    }
+    assert_param(IS_ERTC_MINUTES(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Minutes));
+    assert_param(IS_ERTC_SECONDS(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Seconds));
+    
+    if(ERTC_AlarmStruct->ERTC_AlarmDateWeekSel == ERTC_AlarmDateWeekSel_Date)
+    {
+      assert_param(IS_ERTC_ALARM_DATE_WEEK_DATE(ERTC_AlarmStruct->ERTC_AlarmDateWeek));
+    }
+    else
+    {
+      assert_param(IS_ERTC_ALARM_DATE_WEEK_WEEK(ERTC_AlarmStruct->ERTC_AlarmDateWeek));
+    }
+  }
+  else
+  {
+    if ((ERTC->CTRL & ERTC_CTRL_HFM) != (uint32_t)RESET)
+    {
+      tmpreg = ERTC_Bcd2ToByte(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Hours);
+      assert_param(IS_ERTC_HOUR12(tmpreg));
+      assert_param(IS_ERTC_H12(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_AMPM));
+    } 
+    else
+    {
+      ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_AMPM = 0x00;
+      assert_param(IS_ERTC_HOUR24(ERTC_Bcd2ToByte(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Hours)));
+    }
+    
+    assert_param(IS_ERTC_MINUTES(ERTC_Bcd2ToByte(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Minutes)));
+    assert_param(IS_ERTC_SECONDS(ERTC_Bcd2ToByte(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Seconds)));
+    
+    if(ERTC_AlarmStruct->ERTC_AlarmDateWeekSel == ERTC_AlarmDateWeekSel_Date)
+    {
+      tmpreg = ERTC_Bcd2ToByte(ERTC_AlarmStruct->ERTC_AlarmDateWeek);
+      assert_param(IS_ERTC_ALARM_DATE_WEEK_DATE(tmpreg));    
+    }
+    else
+    {
+      tmpreg = ERTC_Bcd2ToByte(ERTC_AlarmStruct->ERTC_AlarmDateWeek);
+      assert_param(IS_ERTC_ALARM_DATE_WEEK_WEEK(tmpreg));      
+    }    
+  }
+
+  /* Check the input parameters format */
+  if (ERTC_Format != ERTC_Format_BIN)
+  {
+    tmpreg = (((uint32_t)(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Hours) << 16) | \
+              ((uint32_t)(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Minutes) << 8) | \
+              ((uint32_t)ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Seconds) | \
+              ((uint32_t)(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_AMPM) << 16) | \
+              ((uint32_t)(ERTC_AlarmStruct->ERTC_AlarmDateWeek) << 24) | \
+              ((uint32_t)ERTC_AlarmStruct->ERTC_AlarmDateWeekSel) | \
+              ((uint32_t)ERTC_AlarmStruct->ERTC_AlarmMask)); 
+  }  
+  else
+  {
+    tmpreg = (((uint32_t)ERTC_ByteToBcd2(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Hours) << 16) | \
+              ((uint32_t)ERTC_ByteToBcd2(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Minutes) << 8) | \
+              ((uint32_t)ERTC_ByteToBcd2(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Seconds)) | \
+              ((uint32_t)(ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_AMPM) << 16) | \
+              ((uint32_t)ERTC_ByteToBcd2(ERTC_AlarmStruct->ERTC_AlarmDateWeek) << 24) | \
+              ((uint32_t)ERTC_AlarmStruct->ERTC_AlarmDateWeekSel) | \
+              ((uint32_t)ERTC_AlarmStruct->ERTC_AlarmMask)); 
+  } 
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+
+  /* Configure the Alarm register */
+  if (ERTC_Alarm == ERTC_AlA)
+  {
+    ERTC->ALA = (uint32_t)tmpreg;
+  }
+  else
+  {
+    ERTC->ALB = (uint32_t)tmpreg;
+  }
+
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF;   
+}
+
+/**
+  * @brief  Fills each ERTC_AlarmStruct member with its default value
+  *         (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
+  *         all fields are masked).
+  * @param  ERTC_AlarmStruct: pointer to a @ref ERTC_AlarmType structure which
+  *         will be initialized.
+  * @retval None
+  */
+void ERTC_AlarmStructInit(ERTC_AlarmType* ERTC_AlarmStruct)
+{
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
+  ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_AMPM = ERTC_H12_AM;
+  ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Hours = 0;
+  ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Minutes = 0;
+  ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Seconds = 0;
+
+  /* Alarm Date Settings : Date = 1st day of the month */
+  ERTC_AlarmStruct->ERTC_AlarmDateWeekSel = ERTC_AlarmDateWeekSel_Date;
+  ERTC_AlarmStruct->ERTC_AlarmDateWeek = 1;
+
+  /* Alarm Masks Settings : Mask =  all fields are not masked */
+  ERTC_AlarmStruct->ERTC_AlarmMask = ERTC_AlarmMask_None;
+}
+
+/**
+  * @brief  Get the ERTC Alarm value and masks.
+  * @param  ERTC_Format: specifies the format of the output parameters.
+  *          This parameter can be one of the following values:
+  *            @arg ERTC_Format_BIN: Binary data format 
+  *            @arg ERTC_Format_BCD: BCD data format
+  * @param  ERTC_Alarm: specifies the alarm to be read.
+  *          This parameter can be one of the following values:
+  *            @arg ERTC_AlA: to select Alarm A
+  *            @arg ERTC_AlB: to select Alarm B  
+  * @param  ERTC_AlarmStruct: pointer to a ERTC_AlarmType structure that will 
+  *                          contains the output alarm configuration values.     
+  * @retval None
+  */
+void ERTC_GetAlarmValue(uint32_t ERTC_Format, uint32_t ERTC_Alarm, ERTC_AlarmType* ERTC_AlarmStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ERTC_FORMAT(ERTC_Format));
+  assert_param(IS_ERTC_ALARM(ERTC_Alarm)); 
+
+  /* Get the RTC_ALRMxR register */
+  if (ERTC_Alarm == ERTC_AlA)
+  {
+    tmpreg = (uint32_t)(ERTC->ALA);
+  }
+  else
+  {
+    tmpreg = (uint32_t)(ERTC->ALB);
+  }
+
+  /* Fill the structure with the read parameters */
+  ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Hours = (uint32_t)((tmpreg & (ERTC_ALA_HT | \
+                                                     ERTC_ALA_HU)) >> 16);
+  ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Minutes = (uint32_t)((tmpreg & (ERTC_ALA_MT | \
+                                                     ERTC_ALA_MU)) >> 8);
+  ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Seconds = (uint32_t)(tmpreg & (ERTC_ALA_ST | \
+                                                     ERTC_ALA_SU));
+  ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_AMPM = (uint32_t)((tmpreg & ERTC_ALA_AMPM) >> 16);
+  ERTC_AlarmStruct->ERTC_AlarmDateWeek = (uint32_t)((tmpreg & (ERTC_ALA_DT | ERTC_ALA_DU)) >> 24);
+  ERTC_AlarmStruct->ERTC_AlarmDateWeekSel = (uint32_t)(tmpreg & ERTC_ALA_WKSEL);
+  ERTC_AlarmStruct->ERTC_AlarmMask = (uint32_t)(tmpreg & ERTC_AlarmMask_All);
+
+  if (ERTC_Format == ERTC_Format_BIN)
+  {
+    ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Hours = ERTC_Bcd2ToByte(ERTC_AlarmStruct-> \
+                                                        ERTC_AlarmTime.ERTC_Hours);
+    ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Minutes = ERTC_Bcd2ToByte(ERTC_AlarmStruct-> \
+                                                        ERTC_AlarmTime.ERTC_Minutes);
+    ERTC_AlarmStruct->ERTC_AlarmTime.ERTC_Seconds = ERTC_Bcd2ToByte(ERTC_AlarmStruct-> \
+                                                        ERTC_AlarmTime.ERTC_Seconds);
+    ERTC_AlarmStruct->ERTC_AlarmDateWeek = ERTC_Bcd2ToByte(ERTC_AlarmStruct->ERTC_AlarmDateWeek);
+  }  
+}
+
+/**
+  * @brief  Enables or disables the specified ERTC Alarm.
+  * @param  ERTC_Alarm: specifies the alarm to be configured.
+  *          This parameter can be any combination of the following values:
+  *            @arg ERTC_AlA: to select Alarm A
+  *            @arg ERTC_AlB: to select Alarm B  
+  * @param  NewState: new state of the specified alarm.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ERTC Alarm is enabled/disabled
+  *          - ERROR: ERTC Alarm is not enabled/disabled  
+  */
+ErrorStatus ERTC_AlarmCmd(uint32_t ERTC_Alarm, FunctionalState NewState)
+{
+  __IO uint32_t alarmcounter = 0x00;
+  uint32_t alarmstatus = 0x00;
+  ErrorStatus status = ERROR;
+    
+  /* Check the parameters */
+  assert_param(IS_ERTC_CMD_ALARM(ERTC_Alarm));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+
+  /* Configure the Alarm state */
+  if (NewState != DISABLE)
+  {
+    ERTC->CTRL |= (uint32_t)ERTC_Alarm;
+
+    status = SUCCESS;    
+  }
+  else
+  { 
+    /* Disable the Alarm in RTC_CR register */
+    ERTC->CTRL &= (uint32_t)~ERTC_Alarm;
+   
+    /* Wait till ERTC ALRxWF flag is set and if Time out is reached exit */
+    do
+    {
+      alarmstatus = ERTC->ISTS & (ERTC_Alarm >> 8);
+      alarmcounter++;  
+    } while((alarmcounter != INITMODE_TMROUT) && (alarmstatus == 0x00));
+    
+    if ((ERTC->ISTS & (ERTC_Alarm >> 8)) == RESET)
+    {
+      status = ERROR;
+    } 
+    else
+    {
+      status = SUCCESS;
+    }        
+  } 
+
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF; 
+  
+  return status;
+}
+
+/**
+  * @brief  Configure the ERTC AlarmA/B Sub seconds value and mask.*
+  * @note   This function is performed only when the Alarm is disabled. 
+  * @param  ERTC_Alarm: specifies the alarm to be configured.
+  *   This parameter can be one of the following values:
+  *     @arg ERTC_AlA: to select Alarm A
+  *     @arg ERTC_AlB: to select Alarm B
+  * @param  ERTC_AlarmSubSecondValue: specifies the Sub seconds value.
+  *   This parameter can be a value from 0 to 0x00007FFF.
+  * @param  ERTC_AlarmSubSecondMask:  specifies the Sub seconds Mask.
+  *   This parameter can be any combination of the following values:
+  *     @arg ERTC_AlarmSubSecondMask_All    : All Alarm SS fields are masked.
+  *                                          There is no comparison on sub seconds for Alarm.
+  *     @arg ERTC_AlarmSubSecondMask_SBS14_1 : SS[14:1] are don't care in Alarm comparison.
+  *                                          Only SS[0] is compared
+  *     @arg ERTC_AlarmSubSecondMask_SBS14_2 : SS[14:2] are don't care in Alarm comparison.
+  *                                          Only SS[1:0] are compared
+  *     @arg ERTC_AlarmSubSecondMask_SBS14_3 : SS[14:3] are don't care in Alarm comparison.
+  *                                          Only SS[2:0] are compared
+  *     @arg ERTC_AlarmSubSecondMask_SBS14_4 : SS[14:4] are don't care in Alarm comparison.
+  *                                          Only SS[3:0] are compared
+  *     @arg ERTC_AlarmSubSecondMask_SBS14_5 : SS[14:5] are don't care in Alarm comparison.
+  *                                          Only SS[4:0] are compared
+  *     @arg ERTC_AlarmSubSecondMask_SBS14_6 : SS[14:6] are don't care in Alarm comparison.
+  *                                          Only SS[5:0] are compared
+  *     @arg ERTC_AlarmSubSecondMask_SBS14_7 : SS[14:7] are don't care in Alarm comparison.
+  *                                          Only SS[6:0] are compared
+  *     @arg ERTC_AlarmSubSecondMask_SBS14_8 : SS[14:8] are don't care in Alarm comparison.
+  *                                          Only SS[7:0] are compared
+  *     @arg ERTC_AlarmSubSecondMask_SBS14_9 : SS[14:9] are don't care in Alarm comparison.
+  *                                          Only SS[8:0] are compared
+  *     @arg ERTC_AlarmSubSecondMask_SBS14_10: SS[14:10] are don't care in Alarm comparison.
+  *                                          Only SS[9:0] are compared
+  *     @arg ERTC_AlarmSubSecondMask_SBS14_11: SS[14:11] are don't care in Alarm comparison.
+  *                                          Only SS[10:0] are compared
+  *     @arg ERTC_AlarmSubSecondMask_SBS14_12: SS[14:12] are don't care in Alarm comparison.
+  *                                          Only SS[11:0] are compared
+  *     @arg ERTC_AlarmSubSecondMask_SBS14_13: SS[14:13] are don't care in Alarm comparison.
+  *                                          Only SS[12:0] are compared
+  *     @arg ERTC_AlarmSubSecondMask_SBS14   : SS[14] is don't care in Alarm comparison.
+  *                                          Only SS[13:0] are compared
+  *     @arg ERTC_AlarmSubSecondMask_None   : SS[14:0] are compared and must match
+  *                                          to activate alarm
+  * @retval None
+  */
+void ERTC_AlarmSubSecondConfig(uint32_t ERTC_Alarm, uint32_t ERTC_AlarmSubSecondValue, uint32_t ERTC_AlarmSubSecondMask)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ERTC_ALARM(ERTC_Alarm));
+  assert_param(IS_ERTC_ALARM_SUB_SECOND_VALUE(ERTC_AlarmSubSecondValue));
+  assert_param(IS_ERTC_ALARM_SUB_SECOND_MASK(ERTC_AlarmSubSecondMask));
+  
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+  
+  /* Configure the Alarm A or Alarm B Sub Second registers */
+  tmpreg = (uint32_t) (uint32_t)(ERTC_AlarmSubSecondValue) | (uint32_t)(ERTC_AlarmSubSecondMask);
+  
+  if (ERTC_Alarm == ERTC_AlA)
+  {
+    /* Configure the Alarm A Sub Second register */
+    ERTC->ALASBS = tmpreg;
+  }
+  else
+  {
+    /* Configure the Alarm B Sub Second register */
+    ERTC->ALBSBS = tmpreg;
+  }
+
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF;
+
+}
+
+/**
+  * @brief  Gets the ERTC Alarm Sub seconds value.
+  * @param  ERTC_Alarm: specifies the alarm to be read.
+  *   This parameter can be one of the following values:
+  *     @arg ERTC_AlA: to select Alarm A
+  *     @arg ERTC_AlB: to select Alarm B
+  * @param  None
+  * @retval ERTC Alarm Sub seconds value.
+  */
+uint32_t ERTC_GetAlarmSubSecond(uint32_t ERTC_Alarm)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Get the RTC_ALRMxR register */
+  if (ERTC_Alarm == ERTC_AlA)
+  {
+    tmpreg = (uint32_t)((ERTC->ALASBS) & ERTC_ALASBS_SBS);
+  }
+  else
+  {
+    tmpreg = (uint32_t)((ERTC->ALBSBS) & ERTC_ALBSBS_SBS);
+  } 
+  
+  return (tmpreg);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group4 WakeUp Timer configuration functions
+ *  @brief   WakeUp Timer configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                 ##### WakeUp Timer configuration functions #####
+ ===============================================================================  
+
+ [..] This section provide functions allowing to program and read the ERTC WakeUp.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the ERTC Wakeup clock source.
+  * @note   The WakeUp Clock source can only be changed when the ERTC WakeUp
+  *         is disabled (Use the ERTC_WakeUpCmd(DISABLE)).      
+  * @param  ERTC_WakeUpClock: Wakeup Clock source.
+  *          This parameter can be one of the following values:
+  *            @arg ERTC_WakeUpClockSelect_RTCCLK_Div16: ERTC Wakeup Counter Clock = RTCCLK/16
+  *            @arg ERTC_WakeUpClockSelect_RTCCLK_Div8: ERTC Wakeup Counter Clock = RTCCLK/8
+  *            @arg ERTC_WakeUpClockSelect_RTCCLK_Div4: ERTC Wakeup Counter Clock = RTCCLK/4
+  *            @arg ERTC_WakeUpClockSelect_RTCCLK_Div2: ERTC Wakeup Counter Clock = RTCCLK/2
+  *            @arg ERTC_WakeUpClockSelect_CK_SPRE_16bits: ERTC Wakeup Counter Clock = CK_SPRE
+  *            @arg ERTC_WakeUpClockSelect_CK_SPRE_17bits: ERTC Wakeup Counter Clock = CK_SPRE
+  * @retval None
+  */
+void ERTC_WakeUpClockConfig(uint32_t ERTC_WakeUpClock)
+{
+  /* Check the parameters */
+  assert_param(IS_ERTC_WAKEUP_CLOCK_SELECT(ERTC_WakeUpClock));
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+
+  /* Clear the Wakeup Timer clock source bits in CTRL register */
+  ERTC->CTRL &= (uint32_t)~ERTC_CTRL_WACKSEL;
+
+  /* Configure the clock source */
+  ERTC->CTRL |= (uint32_t)ERTC_WakeUpClock;
+  
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Configures the ERTC Wakeup counter.
+  * @note   The ERTC WakeUp counter can only be written when the ERTC WakeUp
+  *         is disabled (Use the ERTC_WakeUpCmd(DISABLE)).        
+  * @param  ERTC_WakeUpCounter: specifies the WakeUp counter.
+  *          This parameter can be a value from 0x0000 to 0xFFFF. 
+  * @retval None
+  */
+void ERTC_SetWakeUpCounter(uint32_t ERTC_WakeUpCounter)
+{
+  /* Check the parameters */
+  assert_param(IS_ERTC_WAKEUP_COUNTER(ERTC_WakeUpCounter));
+  
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+  
+  /* Configure the Wakeup Timer counter */
+  ERTC->WATR = (uint32_t)ERTC_WakeUpCounter;
+  
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Returns the ERTC WakeUp timer counter value.
+  * @param  None
+  * @retval The ERTC WakeUp Counter value.
+  */
+uint32_t ERTC_GetWakeUpCounter(void)
+{
+  /* Get the counter value */
+  return ((uint32_t)(ERTC->WATR & ERTC_WATR_WAREV));
+}
+
+/**
+  * @brief  Enables or Disables the ERTC WakeUp timer.
+  * @param  NewState: new state of the WakeUp timer.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+ErrorStatus ERTC_WakeUpCmd(FunctionalState NewState)
+{
+  __IO uint32_t wutcounter = 0x00;
+  uint32_t wutwfstatus = 0x00;
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Wakeup Timer */
+    ERTC->CTRL |= (uint32_t)ERTC_CTRL_WATE;
+    status = SUCCESS;    
+  }
+  else
+  {
+    /* Disable the Wakeup Timer */
+    ERTC->CTRL &= (uint32_t)~ERTC_CTRL_WATE;
+    /* Wait till ERTC WUTWF flag is set and if Time out is reached exit */
+    do
+    {
+      wutwfstatus = ERTC->ISTS & ERTC_ISTS_WATWF;
+      wutcounter++;  
+    } while((wutcounter != INITMODE_TMROUT) && (wutwfstatus == 0x00));
+    
+    if ((ERTC->ISTS & ERTC_ISTS_WATWF) == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }    
+  }
+
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF; 
+  
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group5 Daylight Saving configuration functions
+ *  @brief   Daylight Saving configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+              ##### Daylight Saving configuration functions #####
+ ===============================================================================  
+
+ [..] This section provide functions allowing to configure the ERTC DayLight Saving.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Adds or substract one hour from the current time.
+  * @param  RTC_DayLightSaveOperation: the value of hour adjustment. 
+  *          This parameter can be one of the following values:
+  *            @arg ERTC_DayLightSaving_SUB1H: Substract one hour (winter time)
+  *            @arg ERTC_DayLightSaving_ADD1H: Add one hour (summer time)
+  * @param  ERTC_StoreOperation: Specifies the value to be written in the BCK bit 
+  *                            in CTRL register to store the operation.
+  *          This parameter can be one of the following values:
+  *            @arg ERTC_StoreOperation_Reset: BCK Bit Reset
+  *            @arg ERTC_StoreOperation_Set: BCK Bit Set
+  * @retval None
+  */
+void ERTC_DayLightSavingConfig(uint32_t ERTC_DayLightSaving, uint32_t ERTC_StoreOperation)
+{
+  /* Check the parameters */
+  assert_param(IS_ERTC_DAYLIGHT_SAVING(ERTC_DayLightSaving));
+  assert_param(IS_ERTC_STORE_OPERATION(ERTC_StoreOperation));
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+
+  /* Clear the bits to be configured */
+  ERTC->CTRL &= (uint32_t)~(ERTC_CTRL_BKP);
+
+  /* Configure the RTC_CR register */
+  ERTC->CTRL |= (uint32_t)(ERTC_DayLightSaving | ERTC_StoreOperation);
+
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Returns the ERTC Day Light Saving stored operation.
+  * @param  None
+  * @retval ERTC Day Light Saving stored operation.
+  *          - ERTC_StoreOperation_Reset
+  *          - ERTC_StoreOperation_Set       
+  */
+uint32_t ERTC_GetStoreOperation(void)
+{
+  return (ERTC->CTRL & ERTC_CTRL_BKP);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group6 Output pin Configuration function
+ *  @brief   Output pin Configuration function 
+ *
+@verbatim   
+ ===============================================================================
+                 ##### Output pin Configuration function #####
+ ===============================================================================  
+
+ [..] This section provide functions allowing to configure the ERTC Output source.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the ERTC output source (AFO_ALARM).
+  * @param  ERTC_Output: Specifies which signal will be routed to the ERTC output. 
+  *          This parameter can be one of the following values:
+  *            @arg ERTC_Output_Disable: No output selected
+  *            @arg ERTC_Output_AlarmA: signal of AlarmA mapped to output
+  *            @arg ERTC_Output_AlarmB: signal of AlarmB mapped to output
+  *            @arg ERTC_Output_WakeUp: signal of WakeUp mapped to output
+  * @param  ERTC_OutputPolarity: Specifies the polarity of the output signal. 
+  *          This parameter can be one of the following:
+  *            @arg ERTC_OutputPolarity_High: The output pin is high when the 
+  *                                 ALRAF/ALRBF/WUTF is high (depending on OSEL)
+  *            @arg ERTC_OutputPolarity_Low: The output pin is low when the 
+  *                                 ALRAF/ALRBF/WUTF is high (depending on OSEL)
+  * @retval None
+  */
+void ERTC_OutputConfig(uint32_t ERTC_Output, uint32_t ERTC_OutputPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_ERTC_OUTPUT(ERTC_Output));
+  assert_param(IS_ERTC_OUTPUT_OPOL(ERTC_OutputPolarity));
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+
+  /* Clear the bits to be configured */
+  ERTC->CTRL &= (uint32_t)~(ERTC_CTRL_OSEL | ERTC_CTRL_OPOL);
+
+  /* Configure the output selection and polarity */
+  ERTC->CTRL |= (uint32_t)(ERTC_Output | ERTC_OutputPolarity);
+
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF; 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group7 Digital Calibration configuration functions
+ *  @brief   Coarse Calibration configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+              ##### Digital Calibration configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the Coarse calibration parameters.
+  * @param  ERTC_CalSign: specifies the sign of the coarse calibration value.
+  *          This parameter can be  one of the following values:
+  *            @arg ERTC_DataCalSign_Positive: The value sign is positive 
+  *            @arg ERTC_DataCalSign_Negative: The value sign is negative
+  * @param  Value: value of coarse calibration expressed in ppm (coded on 5 bits).
+  *    
+  * @note   This Calibration value should be between 0 and 63 when using negative
+  *         sign with a 2-ppm step.
+  *           
+  * @note   This Calibration value should be between 0 and 126 when using positive
+  *         sign with a 4-ppm step.
+  *           
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ERTC Coarse calibration are initialized
+  *          - ERROR: ERTC Coarse calibration are not initialized     
+  */
+ErrorStatus ERTC_CoarseCalConfig(uint32_t ERTC_CalSign, uint32_t Value)
+{
+  ErrorStatus status = ERROR;
+   
+  /* Check the parameters */
+  assert_param(IS_ERTC_DATACAL_SIGN(ERTC_CalSign));
+  assert_param(IS_ERTC_DATACAL_VALUE(Value)); 
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (ERTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Set the coarse calibration value */
+    ERTC->CAL = (uint32_t)(ERTC_CalSign | Value);
+    /* Exit Initialization mode */
+    ERTC_ExitInitMode();
+    
+    status = SUCCESS;
+  } 
+
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF; 
+  
+  return status;
+}
+
+/**
+  * @brief  Enables or disables the Coarse calibration process.
+  * @param  NewState: new state of the Coarse calibration.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ERTC Coarse calibration are enabled/disabled
+  *          - ERROR: ERTC Coarse calibration are not enabled/disabled    
+  */
+ErrorStatus ERTC_CoarseCalCmd(FunctionalState NewState)
+{
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+  
+  /* Set Initialization mode */
+  if (ERTC_EnterInitMode() == ERROR)
+  {
+    status =  ERROR;
+  }
+  else
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable the Coarse Calibration */
+      ERTC->CTRL |= (uint32_t)ERTC_CTRL_CDCE;
+    }
+    else
+    { 
+      /* Disable the Coarse Calibration */
+      ERTC->CTRL &= (uint32_t)~ERTC_CTRL_CDCE;
+    }
+    /* Exit Initialization mode */
+    ERTC_ExitInitMode();
+    
+    status = SUCCESS;
+  } 
+  
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF; 
+  
+  return status;
+}
+
+/**
+  * @brief  Enables or disables the ERTC clock to be output through the relative pin.
+  * @param  NewState: new state of the digital calibration Output.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ERTC_CalOutputCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the ERTC clock output */
+    ERTC->CTRL |= (uint32_t)ERTC_CTRL_CALOE;
+  }
+  else
+  { 
+    /* Disable the ERTC clock output */
+    ERTC->CTRL &= (uint32_t)~ERTC_CTRL_CALOE;
+  }
+  
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+  * @param  ERTC_CalOutput : Select the Calibration output Selection .
+  *   This parameter can be one of the following values:
+  *     @arg ERTC_CalOutput_512Hz: A signal has a regular waveform at 512Hz. 
+  *     @arg ERTC_CalOutput_1Hz  : A signal has a regular waveform at 1Hz.
+  * @retval None
+*/
+void ERTC_CalOutputConfig(uint32_t ERTC_CalOutput)
+{
+  /* Check the parameters */
+  assert_param(IS_ERTC_CAL_OUTPUT(ERTC_CalOutput));
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+  
+  /*clear flags before configuration */
+  ERTC->CTRL &= (uint32_t)~(ERTC_CTRL_CALSEL);
+
+  /* Configure the RTC_CR register */
+  ERTC->CTRL |= (uint32_t)ERTC_CalOutput;
+
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Configures the Smooth Calibration Settings.
+  * @param  ERTC_SmoothCalPeriod : Select the Smooth Calibration Period.
+  *   This parameter can be can be one of the following values:
+  *     @arg ERTC_SmoothCalPeriod_32sec : The smooth calibration period is 32s.
+  *     @arg ERTC_SmoothCalPeriod_16sec : The smooth calibration period is 16s.
+  *     @arg ERTC_SmoothCalPeriod_8sec  : The smooth calibration period is 8s.
+  * @param  ERTC_SmoothCalPlusPulses : Select to Set or reset the CALP bit.
+  *   This parameter can be one of the following values:
+  *     @arg ERTC_SmoothCalAddPulses_Set  : Add one RTCCLK pulse every 2**11 pulses.
+  *     @arg ERTC_SmoothCalAddPulses_Reset: No RTCCLK pulses are added.
+  * @param  ERTC_SmouthCalMinusPulsesValue: Select the value of CALM[8:0] bits.
+  *   This parameter can be one any value from 0 to 0x000001FF.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ERTC Calib registers are configured
+  *          - ERROR: ERTC Calib registers are not configured
+*/
+ErrorStatus ERTC_SmoothCalConfig(uint32_t ERTC_SmoothCalPeriod,
+                                  uint32_t ERTC_SmoothCalPlusPulses,
+                                  uint32_t ERTC_SmouthCalMinusPulsesValue)
+{
+  ErrorStatus status = ERROR;
+  uint32_t recalpfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ERTC_SMOOTH_CAL_PERIOD(ERTC_SmoothCalPeriod));
+  assert_param(IS_ERTC_SMOOTH_CAL_ADD(ERTC_SmoothCalPlusPulses));
+  assert_param(IS_ERTC_SMOOTH_CAL_VALUE(ERTC_SmouthCalMinusPulsesValue));
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+  
+  /* check if a calibration is pending*/
+  if ((ERTC->ISTS & ERTC_ISTS_RECALPDF) != RESET)
+  {
+    /* wait until the Calibration is completed*/
+    while (((ERTC->ISTS & ERTC_ISTS_RECALPDF) != RESET) && (recalpfcount != RECALPDF_TMROUT))
+    {
+      recalpfcount++;
+    }
+  }
+
+  /* check if the calibration pending is completed or if there is no calibration operation at all*/
+  if ((ERTC->ISTS & ERTC_ISTS_RECALPDF) == RESET)
+  {
+    /* Configure the Smooth calibration settings */
+    ERTC->CCR = (uint32_t)((uint32_t)ERTC_SmoothCalPeriod | (uint32_t)ERTC_SmoothCalPlusPulses | (uint32_t)ERTC_SmouthCalMinusPulsesValue);
+
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF;
+  
+  return (ErrorStatus)(status);
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_Group8 TimeStamp configuration functions
+ *  @brief   TimeStamp configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                 ##### TimeStamp configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or Disables the ERTC TimeStamp functionality with the 
+  *         specified time stamp pin stimulating edge.
+  * @param  ERTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
+  *         activated.
+  *          This parameter can be one of the following:
+  *            @arg ERTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising 
+  *                                    edge of the related pin.
+  *            @arg ERTC_TimeStampEdge_Falling: the Time stamp event occurs on the 
+  *                                     falling edge of the related pin.
+  * @param  NewState: new state of the TimeStamp.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ERTC_TimeStampCmd(uint32_t ERTC_TimeStampEdge, FunctionalState NewState)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ERTC_TIMESTAMP_EDGE(ERTC_TimeStampEdge));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Get the RTC_CR register and clear the bits to be configured */
+  tmpreg = (uint32_t)(ERTC->CTRL & (uint32_t)~(ERTC_CTRL_TSEDGE | ERTC_CTRL_TSE));
+
+  /* Get the new configuration */
+  if (NewState != DISABLE)
+  {
+    tmpreg |= (uint32_t)(ERTC_TimeStampEdge | ERTC_CTRL_TSE);
+  }
+  else
+  {
+    tmpreg |= (uint32_t)(ERTC_TimeStampEdge);
+  }
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+
+  /* Configure the Time Stamp TSEDGE and Enable bits */
+  ERTC->CTRL = (uint32_t)tmpreg;
+
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Get the ERTC TimeStamp value and masks.
+  * @param  ERTC_Format: specifies the format of the output parameters.
+  *          This parameter can be one of the following values:
+  *            @arg ERTC_Format_BIN: Binary data format 
+  *            @arg ERTC_Format_BCD: BCD data format
+  * @param ERTC_StampTimeStruct: pointer to a ERTC_TimeType structure that will 
+  *                             contains the TimeStamp time values. 
+  * @param ERTC_StampDateStruct: pointer to a ERTC_DateType structure that will 
+  *                             contains the TimeStamp date values.     
+  * @retval None
+  */
+void ERTC_GetTimeStamp(uint32_t ERTC_Format, ERTC_TimeType* ERTC_StampTimeStruct, 
+                                      ERTC_DateType* ERTC_StampDateStruct)
+{
+  uint32_t tmptime = 0, tmpdate = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ERTC_FORMAT(ERTC_Format));
+
+  /* Get the TimeStamp time and date registers values */
+  tmptime = (uint32_t)(ERTC->TSTM & ERTC_TIME_RESERVED_MASK);
+  tmpdate = (uint32_t)(ERTC->TSDT & ERTC_DATE_RESERVED_MASK);
+
+  /* Fill the Time structure fields with the read parameters */
+  ERTC_StampTimeStruct->ERTC_Hours = (uint8_t)((tmptime & (ERTC_TIME_HT | ERTC_TIME_HU)) >> 16);
+  ERTC_StampTimeStruct->ERTC_Minutes = (uint8_t)((tmptime & (ERTC_TIME_MT | ERTC_TIME_MU)) >> 8);
+  ERTC_StampTimeStruct->ERTC_Seconds = (uint8_t)(tmptime & (ERTC_TIME_ST | ERTC_TIME_SU));
+  ERTC_StampTimeStruct->ERTC_AMPM = (uint8_t)((tmptime & (ERTC_TIME_AMPM)) >> 16);  
+
+  /* Fill the Date structure fields with the read parameters */
+  ERTC_StampDateStruct->ERTC_Year = 0;
+  ERTC_StampDateStruct->ERTC_Month = (uint8_t)((tmpdate & (ERTC_DATE_MT | ERTC_DATE_MU)) >> 8);
+  ERTC_StampDateStruct->ERTC_Date = (uint8_t)(tmpdate & (ERTC_DATE_DT | ERTC_DATE_DU));
+  ERTC_StampDateStruct->ERTC_WeekDay = (uint8_t)((tmpdate & (ERTC_DATE_WK)) >> 13);
+
+  /* Check the input parameters format */
+  if (ERTC_Format == ERTC_Format_BIN)
+  {
+    /* Convert the Time structure parameters to Binary format */
+    ERTC_StampTimeStruct->ERTC_Hours = (uint8_t)ERTC_Bcd2ToByte(ERTC_StampTimeStruct->ERTC_Hours);
+    ERTC_StampTimeStruct->ERTC_Minutes = (uint8_t)ERTC_Bcd2ToByte(ERTC_StampTimeStruct->ERTC_Minutes);
+    ERTC_StampTimeStruct->ERTC_Seconds = (uint8_t)ERTC_Bcd2ToByte(ERTC_StampTimeStruct->ERTC_Seconds);
+
+    /* Convert the Date structure parameters to Binary format */
+    ERTC_StampDateStruct->ERTC_Month = (uint8_t)ERTC_Bcd2ToByte(ERTC_StampDateStruct->ERTC_Month);
+    ERTC_StampDateStruct->ERTC_Date = (uint8_t)ERTC_Bcd2ToByte(ERTC_StampDateStruct->ERTC_Date);
+    ERTC_StampDateStruct->ERTC_WeekDay = (uint8_t)ERTC_Bcd2ToByte(ERTC_StampDateStruct->ERTC_WeekDay);
+  }
+}
+
+/**
+  * @brief  Get the ERTC timestamp Sub seconds value.
+  * @param  None
+  * @retval ERTC current timestamp Sub seconds value.
+  */
+uint32_t ERTC_GetTimeStampSubSecond(void)
+{
+  /* Get timestamp sub seconds values from the correspondent registers */
+  return (uint32_t)(ERTC->TSSBS);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group9 Tampers configuration functions
+ *  @brief   Tampers configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                 ##### Tampers configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the select Tamper pin edge.
+  * @param  ERTC_Tamper: Selected tamper pin.
+  *          This parameter can be ERTC_TAMP_1 or ERTC_Tamper 2
+  * @param  ERTC_TamperTrigger: Specifies the trigger on the tamper pin that 
+  *         stimulates tamper event. 
+  *   This parameter can be one of the following values:
+  *     @arg ERTC_TamperTrig_RisingEdge: Rising Edge of the tamper pin causes tamper event.
+  *     @arg ERTC_TamperTrig_FallingEdge: Falling Edge of the tamper pin causes tamper event.
+  *     @arg ERTC_TamperTrig_LowLevel: Low Level of the tamper pin causes tamper event.
+  *     @arg ERTC_TamperTrig_HighLevel: High Level of the tamper pin causes tamper event.
+  * @retval None
+  */
+void ERTC_TamperTriggerConfig(uint32_t ERTC_Tamper, uint32_t ERTC_TamperTrigger)
+{
+  /* Check the parameters */
+  assert_param(IS_ERTC_TAMP(ERTC_Tamper)); 
+  assert_param(IS_ERTC_TAMPER_TRIG(ERTC_TamperTrigger));
+ 
+  if (ERTC_TamperTrigger == ERTC_TamperTrig_RisingEdge)
+  {  
+    /* Configure the RTC_TAFCR register */
+    ERTC->TPAF &= (uint32_t)((uint32_t)~(ERTC_Tamper << 1));	
+  }
+  else
+  { 
+    /* Configure the RTC_TAFCR register */
+    ERTC->TPAF |= (uint32_t)(ERTC_Tamper << 1);  
+  }  
+}
+
+/**
+  * @brief  Enables or Disables the Tamper detection.
+  * @param  ERTC_Tamper: Selected tamper pin.
+  *          This parameter can be ERTC_TAMP_1 or ERTC_TAMP_2
+  * @param  NewState: new state of the tamper pin.
+  *          This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
+  */
+void ERTC_TamperCmd(uint32_t ERTC_Tamper, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ERTC_TAMP(ERTC_Tamper));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected Tamper pin */
+    ERTC->TPAF |= (uint32_t)ERTC_Tamper;
+  }
+  else
+  {
+    /* Disable the selected Tamper pin */
+    ERTC->TPAF &= (uint32_t)~ERTC_Tamper;    
+  }  
+}
+
+/**
+  * @brief  Configures the Tampers Filter.
+  * @param  ERTC_TamperFilter: Specifies the tampers filter.
+  *   This parameter can be one of the following values:
+  *     @arg ERTC_TamperFilter_Disable: Tamper filter is disabled.
+  *     @arg ERTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive 
+  *                                    samples at the active level 
+  *     @arg ERTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive 
+  *                                    samples at the active level
+  *     @arg ERTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive 
+  *                                    samples at the active level 
+  * @retval None
+  */
+void ERTC_TamperFilterConfig(uint32_t ERTC_TamperFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_ERTC_TAMPER_FILTER(ERTC_TamperFilter));
+   
+  /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */
+  ERTC->TPAF &= (uint32_t)~(ERTC_TPAF_TMFLT);
+
+  /* Configure the RTC_TAFCR register */
+  ERTC->TPAF |= (uint32_t)ERTC_TamperFilter;
+}
+
+/**
+  * @brief  Configures the Tampers Sampling Frequency.
+  * @param  ERTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
+  *   This parameter can be one of the following values:
+  *     @arg ERTC_TamperSamplingFreq_CLK_Div32768: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 32768
+  *     @arg ERTC_TamperSamplingFreq_CLK_Div16384: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 16384
+  *     @arg ERTC_TamperSamplingFreq_CLK_Div8192: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 8192
+  *     @arg ERTC_TamperSamplingFreq_CLK_Div4096: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 4096
+  *     @arg ERTC_TamperSamplingFreq_CLK_Div2048: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 2048
+  *     @arg ERTC_TamperSamplingFreq_CLK_Div1024: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 1024
+  *     @arg ERTC_TamperSamplingFreq_CLK_Div512: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 512  
+  *     @arg ERTC_TamperSamplingFreq_CLK_Div256: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 256  
+  * @retval None
+  */
+void ERTC_TamperSamplingFreqConfig(uint32_t ERTC_TamperSamplingFreq)
+{
+  /* Check the parameters */
+  assert_param(IS_ERTC_TAMPER_SAMPLING_FREQ(ERTC_TamperSamplingFreq));
+ 
+  /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */
+  ERTC->TPAF &= (uint32_t)~(ERTC_TPAF_TMFREQ);
+
+  /* Configure the RTC_TAFCR register */
+  ERTC->TPAF |= (uint32_t)ERTC_TamperSamplingFreq;
+}
+
+/**
+  * @brief  Configures the Tampers Pins input Precharge Duration.
+  * @param  ERTC_TamperPrechargeDuration: Specifies the Tampers Pins input
+  *         Precharge Duration.
+  *   This parameter can be one of the following values:
+  *     @arg ERTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are precharged before sampling during 1 RTCCLK cycle
+  *     @arg ERTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are precharged before sampling during 2 RTCCLK cycle
+  *     @arg ERTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are precharged before sampling during 4 RTCCLK cycle    
+  *     @arg ERTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are precharged before sampling during 8 RTCCLK cycle
+  * @retval None
+  */
+void ERTC_TamperPinsPrechargeDuration(uint32_t ERTC_TamperPrechargeDuration)
+{
+  /* Check the parameters */
+  assert_param(IS_ERTC_TAMPER_PRECHARGE_DURATION(ERTC_TamperPrechargeDuration));
+   
+  /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */
+  ERTC->TPAF &= (uint32_t)~(ERTC_TPAF_TMPRCH);
+
+  /* Configure the RTC_TAFCR register */
+  ERTC->TPAF |= (uint32_t)ERTC_TamperPrechargeDuration;
+}
+
+/**
+  * @brief  Enables or Disables the TimeStamp on Tamper Detection Event.
+  * @note   The timestamp is valid even the TSE bit in tamper control register 
+  *         is reset.   
+  * @param  NewState: new state of the timestamp on tamper event.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ERTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+   
+  if (NewState != DISABLE)
+  {
+    /* Save timestamp on tamper detection event */
+    ERTC->TPAF |= (uint32_t)ERTC_TPAF_TMTS;
+  }
+  else
+  {
+    /* Tamper detection does not cause a timestamp to be saved */
+    ERTC->TPAF &= (uint32_t)~ERTC_TPAF_TMTS;    
+  }
+}
+
+/**
+  * @brief  Enables or Disables the Precharge of Tamper pin.
+  * @param  NewState: new state of tamper pull up.
+  *   This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
+  */
+void ERTC_TamperPullUpCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+ if (NewState != DISABLE)
+  {
+    /* Enable precharge of the selected Tamper pin */
+    ERTC->TPAF &= (uint32_t)~ERTC_TPAF_TMPUDIS; 
+  }
+  else
+  {
+    /* Disable precharge of the selected Tamper pin */
+    ERTC->TPAF |= (uint32_t)ERTC_TPAF_TMPUDIS;    
+  } 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group10 Backup Data Registers configuration functions
+ *  @brief   Backup Data Registers configuration functions  
+ *
+@verbatim   
+ ===============================================================================
+             ##### Backup Data Registers configuration functions ##### 
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes a data in a specified ERTC Backup data register.
+  * @param  ERTC_BKP_DT: ERTC Backup data Register number.
+  *          This parameter can be: ERTC_BKP_DTx where x can be from 0 to 19 to 
+  *                          specify the register.
+  * @param  Data: Data to be written in the specified ERTC Backup data register.                     
+  * @retval None
+  */
+void ERTC_WriteBackupRegister(uint32_t ERTC_BKP_DT, uint32_t Data)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ERTC_BKP(ERTC_BKP_DT));
+
+  tmp = ERTC_BASE + 0x50;
+  tmp += (ERTC_BKP_DT * 4);
+
+  /* Write the specified register */
+  *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+  * @brief  Reads data from the specified ERTC Backup data Register.
+  * @param  ERTC_BKP_DT: ERTC Backup data Register number.
+  *          This parameter can be: ERTC_BKP_DTx where x can be from 0 to 19 to 
+  *                          specify the register.                   
+  * @retval None
+  */
+uint32_t ERTC_ReadBackupRegister(uint32_t ERTC_BKP_DT)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ERTC_BKP(ERTC_BKP_DT));
+
+  tmp = ERTC_BASE + 0x50;
+  tmp += (ERTC_BKP_DT * 4);
+  
+  /* Read the specified register */
+  return (*(__IO uint32_t *)tmp);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group11 ERTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions
+ *  @brief   ERTC Tamper and TimeStamp Pins Selection and Output Type Config 
+ *           configuration functions  
+ *
+@verbatim   
+ ==================================================================================================
+ ##### ERTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions ##### 
+ ==================================================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the ERTC Tamper Pin.
+  * @param  ERTC_TamperPin: specifies the ERTC Tamper Pin.
+  *          This parameter can be one of the following values:
+  *            @arg ERTC_TAMPPIN_Default: RTC_AF1 is used as ERTC Tamper Pin.
+  *            @arg ERTC_TAMPPIN_Pos1: RTC_AF2 is selected as ERTC Tamper Pin.    
+  * @retval None
+  */
+void ERTC_TamperPinSelection(uint32_t ERTC_TamperPin)
+{
+  /* Check the parameters */
+  assert_param(IS_ERTC_TAMP_PIN(ERTC_TamperPin));
+  
+  ERTC->TPAF &= (uint32_t)~(ERTC_TPAF_TMPINSEL);
+  ERTC->TPAF |= (uint32_t)(ERTC_TamperPin);  
+}
+
+/**
+  * @brief  Selects the ERTC TimeStamp Pin.
+  * @param  ERTC_TimeStampPin: specifies the ERTC TimeStamp Pin.
+  *          This parameter can be one of the following values:
+  *            @arg ERTC_TimeStampPin_PC13: PC13 is selected as ERTC TimeStamp Pin.
+  *            @arg ERTC_TimeStampPin_PI8: PI8 is selected as ERTC TimeStamp Pin.    
+  * @retval None
+  */
+void ERTC_TimeStampPinSelection(uint32_t ERTC_TimeStampPin)
+{
+  /* Check the parameters */
+  assert_param(IS_ERTC_TIMESTAMP_PIN(ERTC_TimeStampPin));
+  
+  ERTC->TPAF &= (uint32_t)~(ERTC_TPAF_TSINSEL);
+  ERTC->TPAF |= (uint32_t)(ERTC_TimeStampPin);  
+}
+
+/**
+  * @brief  Configures the ERTC Output Pin mode. 
+  * @param  ERTC_OutputType: specifies the ERTC Output (PC13) pin mode.
+  *          This parameter can be one of the following values:
+  *            @arg ERTC_OutputType_OpenDrain: ERTC Output (PC13) is configured in 
+  *                                    Open Drain mode.
+  *            @arg ERTC_OutputType_PushPull:  ERTC Output (PC13) is configured in 
+  *                                    Push Pull mode.    
+  * @retval None
+  */
+void ERTC_OutputTypeConfig(uint32_t ERTC_OutputType)
+{
+  /* Check the parameters */
+  assert_param(IS_ERTC_OUTPUT_TYPE(ERTC_OutputType));
+  
+  ERTC->TPAF &= (uint32_t)~(ERTC_TPAF_ALAOUTTYPE);
+  ERTC->TPAF |= (uint32_t)(ERTC_OutputType);  
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group12 Shift control synchronisation functions
+ *  @brief   Shift control synchronisation functions 
+ *
+@verbatim   
+ ===============================================================================
+              ##### Shift control synchronisation functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the Synchronization Shift Control Settings.
+  * @note   When REFCKON is set, firmware must not write to Shift control register 
+  * @param  ERTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar.
+  *   This parameter can be one of the following values :
+  *     @arg ERTC_ShiftAdd1S_Set  : Add one second to the clock calendar. 
+  *     @arg ERTC_ShiftAdd1S_Reset: No effect.
+  * @param  ERTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
+  *         This parameter can be one any value from 0 to 0x7FFF.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ERTC Shift registers are configured
+  *          - ERROR: ERTC Shift registers are not configured
+*/
+ErrorStatus ERTC_SynchroShiftConfig(uint32_t ERTC_ShiftAdd1S, uint32_t ERTC_ShiftSubFS)
+{
+  ErrorStatus status = ERROR;
+  uint32_t shpfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ERTC_SHIFT_ADD1S(ERTC_ShiftAdd1S));
+  assert_param(IS_ERTC_SHIFT_SUBFS(ERTC_ShiftSubFS));
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+  
+  /* Check if a Shift is pending*/
+  if ((ERTC->ISTS & ERTC_ISTS_SFP) != RESET)
+  {
+    /* Wait until the shift is completed*/
+    while (((ERTC->ISTS & ERTC_ISTS_SFP) != RESET) && (shpfcount != SFP_TMROUT))
+    {
+      shpfcount++;
+    }
+  }
+
+  /* Check if the Shift pending is completed or if there is no Shift operation at all*/
+  if ((ERTC->ISTS & ERTC_ISTS_SFP) == RESET)
+  {
+    /* check if the reference clock detection is disabled */
+    if((ERTC->CTRL & ERTC_CTRL_RFCKON) == RESET)
+    {
+      /* Configure the Shift settings */
+      ERTC->SFCTR = (uint32_t)(uint32_t)(ERTC_ShiftSubFS) | (uint32_t)(ERTC_ShiftAdd1S);
+    
+      if(ERTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF;
+  
+  return (ErrorStatus)(status);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group13 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions  
+ *
+@verbatim   
+ ===============================================================================
+              ##### Interrupts and flags management functions #####
+ ===============================================================================  
+ [..] All ERTC interrupts are connected to the EXTI controller.
+ 
+   (+) To enable the ERTC Alarm interrupt, the following sequence is required:
+       (++) Configure and enable the EXTI Line 17 in interrupt mode and select 
+            the rising edge sensitivity using the EXTI_Init() function.
+       (++) Configure and enable the ERTC_Alarm IRQ channel in the NVIC using the 
+            NVIC_Init() function.
+       (++) Configure the ERTC to generate ERTC alarms (Alarm A and/or Alarm B) using
+            the ERTC_SetAlarmValue() and ERTC_AlarmCmd() functions.
+
+   (+) To enable the ERTC Wakeup interrupt, the following sequence is required:
+       (++) Configure and enable the EXTI Line 22 in interrupt mode and select the
+            rising edge sensitivity using the EXTI_Init() function.
+       (++) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the 
+            NVIC_Init() function.
+       (++) Configure the ERTC to generate the ERTC wakeup timer event using the 
+            ERTC_WakeUpClockConfig(), ERTC_SetWakeUpCounter() and ERTC_WakeUpCmd() 
+            functions.
+
+   (+) To enable the ERTC Tamper interrupt, the following sequence is required:
+       (++) Configure and enable the EXTI Line 21 in interrupt mode and select 
+            the rising edge sensitivity using the EXTI_Init() function.
+       (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the
+            NVIC_Init() function.
+       (++) Configure the ERTC to detect the ERTC tamper event using the 
+            ERTC_TamperTriggerConfig() and ERTC_TamperCmd() functions.
+
+   (+) To enable the ERTC TimeStamp interrupt, the following sequence is required:
+       (++) Configure and enable the EXTI Line 21 in interrupt mode and select the
+            rising edge sensitivity using the EXTI_Init() function.
+       (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the 
+            NVIC_Init() function.
+       (++) Configure the ERTC to detect the ERTC time stamp event using the 
+            ERTC_TimeStampCmd() functions.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified ERTC interrupts.
+  * @param  ERTC_INT: specifies the ERTC interrupt sources to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg ERTC_INT_TS:  Time Stamp interrupt mask
+  *            @arg ERTC_INT_WAT:  WakeUp Timer interrupt mask
+  *            @arg ERTC_INT_ALB:  Alarm B interrupt mask
+  *            @arg ERTC_INT_ALA:  Alarm A interrupt mask
+  *            @arg ERTC_INT_TAMP: Tamper event interrupt mask
+  * @param  NewState: new state of the specified ERTC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ERTC_INTConfig(uint32_t ERTC_INT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ERTC_CONFIG_INT(ERTC_INT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for ERTC registers */
+  ERTC->WPR = 0xCA;
+  ERTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Configure the Interrupts in the RTC_CR register */
+    ERTC->CTRL |= (uint32_t)(ERTC_INT & ~ERTC_TPAF_TMIE);
+    /* Configure the Tamper Interrupt in the RTC_TAFCR */
+    ERTC->TPAF |= (uint32_t)(ERTC_INT & ERTC_TPAF_TMIE);
+  }
+  else
+  {
+    /* Configure the Interrupts in the RTC_CR register */
+    ERTC->CTRL &= (uint32_t)~(ERTC_INT & (uint32_t)~ERTC_TPAF_TMIE);
+    /* Configure the Tamper Interrupt in the RTC_TAFCR */
+    ERTC->TPAF &= (uint32_t)~(ERTC_INT & ERTC_TPAF_TMIE);
+  }
+  /* Enable the write protection for ERTC registers */
+  ERTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Checks whether the specified ERTC flag is set or not.
+  * @param  ERTC_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg ERTC_FLAG_RECALPDF: RECALPF event flag.
+  *            @arg ERTC_FLAG_TP1F: Tamper 1 event flag
+  *            @arg ERTC_FLAG_TP2F: Tamper 2 event flag
+  *            @arg ERTC_FLAG_TSOF: Time Stamp OverFlow flag
+  *            @arg ERTC_FLAG_TSF: Time Stamp event flag
+  *            @arg ERTC_FLAG_WATF: WakeUp Timer flag
+  *            @arg ERTC_FLAG_ALBF: Alarm B flag
+  *            @arg ERTC_FLAG_ALAF: Alarm A flag
+  *            @arg ERTC_FLAG_INITF: Initialization mode flag
+  *            @arg ERTC_FLAG_RSF: Registers Synchronized flag
+  *            @arg ERTC_FLAG_INITS: Registers Configured flag
+  *            @arg ERTC_FLAG_SFP: Shift operation pending flag.
+  *            @arg ERTC_FLAG_WATWF: WakeUp Timer Write flag
+  *            @arg ERTC_FLAG_ALBWF: Alarm B Write flag
+  *            @arg ERTC_FLAG_ALAWF: Alarm A write flag
+  * @retval The new state of ERTC_FLAG (SET or RESET).
+  */
+FlagStatus ERTC_GetFlagStatus(uint32_t ERTC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ERTC_GET_FLAG(ERTC_FLAG));
+  
+  /* Get all the flags */
+  tmpreg = (uint32_t)(ERTC->ISTS & ERTC_FLAGS_MASK);
+  
+  /* Return the status of the flag */
+  if ((tmpreg & ERTC_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the ERTC's pending flags.
+  * @param  ERTC_FLAG: specifies the ERTC flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg ERTC_FLAG_TP1F: Tamper 1 event flag
+  *            @arg ERTC_FLAG_TP2F: Tamper 2 event flag
+  *            @arg ERTC_FLAG_TSOF: Time Stamp Overflow flag 
+  *            @arg ERTC_FLAG_TSF: Time Stamp event flag
+  *            @arg ERTC_FLAG_WATF: WakeUp Timer flag
+  *            @arg ERTC_FLAG_ALBF: Alarm B flag
+  *            @arg ERTC_FLAG_ALAF: Alarm A flag
+  *            @arg ERTC_FLAG_RSF: Registers Synchronized flag
+  * @retval None
+  */
+void ERTC_ClearFlag(uint32_t ERTC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_ERTC_CLEAR_FLAG(ERTC_FLAG));
+
+  /* Clear the Flags in the RTC_ISR register */
+  ERTC->ISTS = (uint32_t)((uint32_t)(~((ERTC_FLAG | ERTC_ISTS_INITM)& 0x0000FFFF) | (uint32_t)(ERTC->ISTS & ERTC_ISTS_INITM)));  
+}
+
+/**
+  * @brief  Checks whether the specified ERTC interrupt has occurred or not.
+  * @param  ERTC_INT: specifies the ERTC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg ERTC_INT_TS: Time Stamp interrupt 
+  *            @arg ERTC_INT_WAT: WakeUp Timer interrupt 
+  *            @arg ERTC_INT_ALB: Alarm B interrupt 
+  *            @arg ERTC_INT_ALA: Alarm A interrupt 
+  *            @arg ERTC_INT_TAMP1: Tamper 1 event interrupt
+  *            @arg ERTC_INT_TAMP2: Tamper 2 event interrupt
+  * @retval The new state of ERTC_INT (SET or RESET).
+  */
+ITStatus ERTC_GetINTStatus(uint32_t ERTC_INT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpreg = 0, enablestatus = 0;
+ 
+  /* Check the parameters */
+  assert_param(IS_ERTC_GET_INT(ERTC_INT));
+  
+  /* Get the TAMPER Interrupt enable bit and pending bit */
+  tmpreg = (uint32_t)(ERTC->TPAF & (ERTC_TPAF_TMIE));
+ 
+  /* Get the Interrupt enable Status */
+  enablestatus = (uint32_t)((ERTC->CTRL & ERTC_INT) | (tmpreg & (ERTC_INT >> 15)) | (tmpreg & (ERTC_INT >> 16)));
+  
+  /* Get the Interrupt pending bit */
+  tmpreg = (uint32_t)((ERTC->ISTS & (uint32_t)(ERTC_INT >> 4)));
+  
+  /* Get the status of the Interrupt */
+  if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the ERTC's interrupt pending bits.
+  * @param  ERTC_INT: specifies the ERTC interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg ERTC_INT_TS: Time Stamp interrupt 
+  *            @arg ERTC_INT_WAT: WakeUp Timer interrupt 
+  *            @arg ERTC_INT_ALB: Alarm B interrupt 
+  *            @arg ERTC_INT_ALA: Alarm A interrupt 
+  *            @arg ERTC_INT_TAMP1: Tamper 1 event interrupt
+  *            @arg ERTC_INT_TAMP2: Tamper 2 event interrupt 
+  * @retval None
+  */
+void ERTC_ClearINTPendingBINT(uint32_t ERTC_INT)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ERTC_CLEAR_INT(ERTC_INT));
+
+  /* Get the RTC_ISR Interrupt pending bits mask */
+  tmpreg = (uint32_t)(ERTC_INT >> 4);
+
+  /* Clear the interrupt pending bits in the RTC_ISR register */
+  ERTC->ISTS = (uint32_t)((uint32_t)(~((tmpreg | ERTC_ISTS_INITM)& 0x0000FFFF) | (uint32_t)(ERTC->ISTS & ERTC_ISTS_INITM))); 
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Converts a 2 digit decimal to BCD format.
+  * @param  Value: Byte to be converted.
+  * @retval Converted byte
+  */
+static uint8_t ERTC_ByteToBcd2(uint8_t Value)
+{
+  uint8_t bcdhigh = 0;
+  
+  while (Value >= 10)
+  {
+    bcdhigh++;
+    Value -= 10;
+  }
+  
+  return  ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+  * @brief  Convert from 2 digit BCD to Binary.
+  * @param  Value: BCD value to be converted.
+  * @retval Converted word
+  */
+static uint8_t ERTC_Bcd2ToByte(uint8_t Value)
+{
+  uint8_t tmp = 0;
+  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+  return (tmp + (Value & (uint8_t)0x0F));
+}
+
+/**
+  * @}
+  */ 
+
+#endif /* AT32F415xx */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_eth.c

@@ -0,0 +1,3078 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_eth.c
+ * Description  : at32f4xx ETH source file
+ * Date         : 2019-12-16
+ * Version      : V1.0.0
+ **************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_eth.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @brief ETH driver modules
+  * @{
+  */
+
+#if defined (AT32F407xx)
+
+/** @defgroup ETH_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ETH_Private_Defines
+  * @{
+  */ 
+/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
+ETH_DMADESCTypeDef  *DMATxDescToSet;
+ETH_DMADESCTypeDef  *DMARxDescToGet;
+ETH_DMADESCTypeDef  *DMAPTPTxDescToSet;
+ETH_DMADESCTypeDef  *DMAPTPRxDescToGet;
+
+/* ETHERNET MAC address offsets */
+#define ETH_MAC_ADDR_HBASE    (ETH_MAC_BASE + 0x40)  /* ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE    (ETH_MAC_BASE + 0x44)  /* ETHERNET MAC address low offset */
+
+/* ETHERNET MACMIIAR register Mask */
+#define ETH_MACMIIAR_CR_MASK    ((uint32_t)0xFFFFFFE3) 
+
+/* ETHERNET MACCR register Mask */
+#define ETH_MACCR_CLEAR_MASK    ((uint32_t)0xFF20810F)  
+
+/* ETHERNET MACFCR register Mask */
+#define ETH_MACFCR_CLEAR_MASK   ((uint32_t)0x0000FF41)
+
+/* ETHERNET DMAOMR register Mask */
+#define ETH_DMAOMR_CLEAR_MASK   ((uint32_t)0xF8DE3F23)
+
+/* ETHERNET Remote Wake-up frame register length */
+#define ETH_WAKEUP_REGISTER_LENGTH      8
+
+/* ETHERNET Missed frames counter Shift */
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT     17
+
+/* ETHERNET DMA Tx descriptors Collision Count Shift */
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT                 3
+
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT                   16
+
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT                   16
+
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
+#define ETH_DMARXDESC_FRAMELENGTHSHIFT                    16
+
+/* ETHERNET errors */
+#define  ETH_ERROR              ((uint32_t)0)
+#define  ETH_SUCCESS            ((uint32_t)1)
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Private_Variables
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Private_FunctionPrototypes
+  * @{
+  */ 
+  
+#ifndef USE_Delay
+static void ETH_Delay(__IO uint32_t nCount);
+#endif /* USE_Delay*/
+  
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the ETHERNET peripheral registers to their default reset values.
+  * @param  None 
+  * @retval None
+  */
+void ETH_DeInit(void)
+{
+  RCC_AHBPeriphResetCmd(RCC_AHBPERIPH_ETHMAC, ENABLE);
+  RCC_AHBPeriphResetCmd(RCC_AHBPERIPH_ETHMAC, DISABLE);
+}
+
+/**
+  * @brief  Initializes the ETHERNET peripheral according to the specified
+  *   parameters in the ETH_InitStruct .
+  * @param ETH_InitStruct: pointer to a ETH_InitType structure that contains
+  *   the configuration information for the specified ETHERNET peripheral.
+  * @param PHYAddress: external PHY address                    
+  * @retval ETH_ERROR: Ethernet initialization failed
+  *         ETH_SUCCESS: Ethernet successfully initialized                 
+  */
+uint32_t ETH_Init(ETH_InitType* ETH_InitStruct, uint16_t PHYAddress)
+{
+  uint32_t RegValue = 0, tmpreg = 0;
+  __IO uint32_t i = 0, addr = 0;
+  RCC_ClockType  rcc_clocks;
+  uint32_t hclk = 60000000;
+  __IO uint32_t timeout = 0;
+  /* Check the parameters */
+  /* MAC --------------------------*/ 
+  assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));
+  assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));
+  assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));
+  assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));
+  assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));
+  assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));
+  assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));
+  assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));
+  assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));
+  assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));
+  assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));
+  assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));
+  assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));
+  assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));
+  assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));
+  assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));
+  assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));
+  assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));
+  assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));
+  assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));
+  assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));  
+  assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));
+  assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));
+  assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));
+  assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));
+  assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));
+  assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));
+  assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));
+  assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));
+  assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));
+  /* DMA --------------------------*/
+  assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));
+  assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));
+  assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));
+  assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));
+  assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));
+  assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));
+  assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));
+  assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));
+  assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));
+  assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));
+  assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));
+  assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));
+  assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); 
+  assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));  
+  assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));       
+  /*-------------------------------- MAC Config ------------------------------*/   
+  /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
+  /* Get the ETHERNET MACMIIAR value */
+  tmpreg = ETH->MACMIIADDR;
+  /* Clear CTRLSTS1 Clock Range CR[2:0] bits */
+  tmpreg &= ETH_MACMIIAR_CR_MASK;
+  /* Get hclk frequency value */
+   RCC_GetClocksFreq(&rcc_clocks);
+  hclk = rcc_clocks.AHBCLK_Freq;
+  /* Set CR bits depending on hclk value */
+  if((hclk >= 20000000)&&(hclk < 35000000))
+  {
+    /* CTRLSTS1 Clock Range between 20-35 MHz */
+    tmpreg |= (uint32_t)ETH_MACMIIADDR_CLKR_DIV16;
+  }
+  else if((hclk >= 35000000)&&(hclk < 60000000))
+  {
+    /* CTRLSTS1 Clock Range between 35-60 MHz */ 
+    tmpreg |= (uint32_t)ETH_MACMIIADDR_CLKR_DIV26;    
+  }  
+  else if((hclk >= 60000000)&&(hclk < 100000000))
+  {
+    /* CSR Clock Range between 60-100 MHz */   
+    tmpreg |= (uint32_t)ETH_MACMIIADDR_CLKR_DIV42;    
+  }
+  else if((hclk >= 100000000)&&(hclk < 150000000))
+  {
+    /* CSR Clock Range between 100-150 MHz */   
+    tmpreg |= (uint32_t)ETH_MACMIIADDR_CLKR_DIV62;    
+  }
+  else if((hclk >= 150000000)&&(hclk < 250000000))
+  {
+    /* CSR Clock Range between 150-250 MHz */   
+    tmpreg |= (uint32_t)ETH_MACMIIADDR_CLKR_DIV102;
+  }
+  else
+  {
+    /* CSR Clock Range between 250-300 MHz */   
+    tmpreg |= (uint32_t)ETH_MACMIIADDR_CLKR_DIV124;
+  }
+  
+
+  /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CTRLSTS1 Clock Range */
+  ETH->MACMIIADDR = (uint32_t)tmpreg;  
+  /*-------------------- PHY initialization and configuration ----------------*/
+  /* Put the PHY in reset mode */
+  if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))
+  {
+    /* Return ERROR in case of write timeout */
+    return ETH_ERROR;
+  }
+  
+  _eth_delay_(PHY_ResetDelay);
+  
+  while (1) /*Wait Reset Complete*/
+  {
+    if ( (ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Reset) == 0 )
+      break;
+    _eth_delay_(PHY_ResetDelay);
+  }
+  
+  if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
+  {  
+    /* We wait for linked satus... */
+    do
+    {
+      timeout++;
+    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));
+    /* Return ERROR in case of timeout */
+    if(timeout == PHY_READ_TO)
+    {
+//      return ETH_ERROR;
+    }
+    /* Reset Timeout counter */
+    timeout = 0;
+    
+    /* Enable Auto-Negotiation */
+    if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))
+    {
+      /* Return ERROR in case of write timeout */
+      return ETH_ERROR;
+    }
+    
+    /* Wait until the autonegotiation will be completed */
+    do
+    {
+      timeout++;
+    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO)); 
+    
+    /* Return ERROR in case of timeout */
+    if(timeout == PHY_READ_TO)
+    {
+      return ETH_ERROR;
+    }
+    
+    /*Get Auto-Negotiation Result*/
+    RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);
+    
+    if((RegValue & PHY_FullDuplex_Speed_100_Status) != (uint32_t)RESET)
+    {
+       ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
+       ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
+    }
+    else if ((RegValue & PHY_HalfDuplex_Speed_100_Status) != (uint32_t)RESET)
+    {
+      ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
+      ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
+    }
+    else if ((RegValue & PHY_FullDuplex_Speed_10_Status) != (uint32_t)RESET)
+    {
+      ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
+      ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
+    }
+    else if ((RegValue & PHY_HalfDuplex_Speed_10_Status) != (uint32_t)RESET)
+    {
+      ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
+      ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
+    } 
+  }
+  else
+  {
+        if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) |
+                                                       (uint16_t)(ETH_InitStruct->ETH_Speed >> 1))))
+        {
+            /* Return ERROR in case of write timeout */
+            return ETH_ERROR;
+        }
+    /* Delay to assure PHY configuration */
+    _eth_delay_(PHY_ConfigDelay);
+    
+  }
+    
+  /*------------------------ ETHERNET MACCR Configuration --------------------*/
+  /* Get the ETHERNET MACCR value */  
+  tmpreg = ETH->MACCTRL;
+  /* Clear WD, PCE, PS, TE and RE bits */
+  tmpreg &= ETH_MACCR_CLEAR_MASK;
+  /* Set the WD bit according to ETH_Watchdog value */
+  /* Set the JD: bit according to ETH_Jabber value */
+  /* Set the IFG bit according to ETH_InterFrameGap value */ 
+  /* Set the DCRS bit according to ETH_CarrierSense value */  
+  /* Set the FES bit according to ETH_Speed value */ 
+  /* Set the DO bit according to ETH_ReceiveOwn value */ 
+  /* Set the LM bit according to ETH_LoopbackMode value */ 
+  /* Set the DM bit according to ETH_Mode value */ 
+  /* Set the IPC bit according to ETH_ChecksumOffload value */                   
+  /* Set the DR bit according to ETH_RetryTransmission value */ 
+  /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ 
+  /* Set the BL bit according to ETH_BackOffLimit value */ 
+  /* Set the DC bit according to ETH_DeferralCheck value */                          
+  tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | 
+                  ETH_InitStruct->ETH_Jabber | 
+                  ETH_InitStruct->ETH_InterFrameGap |
+                  ETH_InitStruct->ETH_CarrierSense |
+                  ETH_InitStruct->ETH_Speed | 
+                  ETH_InitStruct->ETH_ReceiveOwn |
+                  ETH_InitStruct->ETH_LoopbackMode |
+                  ETH_InitStruct->ETH_Mode | 
+                  ETH_InitStruct->ETH_ChecksumOffload |    
+                  ETH_InitStruct->ETH_RetryTransmission | 
+                  ETH_InitStruct->ETH_AutomaticPadCRCStrip | 
+                  ETH_InitStruct->ETH_BackOffLimit | 
+                  ETH_InitStruct->ETH_DeferralCheck);
+  /* Write to ETHERNET MACCR */
+  ETH->MACCTRL = (uint32_t)tmpreg;
+  
+  /*----------------------- ETHERNET MACFFR Configuration --------------------*/ 
+  /* Set the RA bit according to ETH_ReceiveAll value */
+  /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */
+  /* Set the PCF bit according to ETH_PassControlFrames value */
+  /* Set the DBF bit according to ETH_BroadcastFramesReception value */
+  /* Set the DAIF bit according to ETH_DestinationAddrFilter value */
+  /* Set the PR bit according to ETH_PromiscuousMode value */
+  /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
+  /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
+  /* Write to ETHERNET MACFFR */  
+  ETH->MACFRMF = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | 
+                          ETH_InitStruct->ETH_SourceAddrFilter |
+                          ETH_InitStruct->ETH_PassControlFrames |
+                          ETH_InitStruct->ETH_BroadcastFramesReception | 
+                          ETH_InitStruct->ETH_DestinationAddrFilter |
+                          ETH_InitStruct->ETH_PromiscuousMode |
+                          ETH_InitStruct->ETH_MulticastFramesFilter |
+                          ETH_InitStruct->ETH_UnicastFramesFilter); 
+  /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
+  /* Write to ETHERNET MACHTHR */
+  ETH->MACHTH = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
+  /* Write to ETHERNET MACHTLR */
+  ETH->MACHTL = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
+  /*----------------------- ETHERNET MACFCR Configuration --------------------*/
+  /* Get the ETHERNET MACFCR value */  
+  tmpreg = ETH->MACFCTRL;
+  /* Clear xx bits */
+  tmpreg &= ETH_MACFCR_CLEAR_MASK;
+  
+  /* Set the PT bit according to ETH_PauseTime value */
+  /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
+  /* Set the PLT bit according to ETH_PauseLowThreshold value */
+  /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
+  /* Set the RFE bit according to ETH_ReceiveFlowControl value */
+  /* Set the TFE bit according to ETH_TransmitFlowControl value */  
+  tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | 
+                   ETH_InitStruct->ETH_ZeroQuantaPause |
+                   ETH_InitStruct->ETH_PauseLowThreshold |
+                   ETH_InitStruct->ETH_UnicastPauseFrameDetect | 
+                   ETH_InitStruct->ETH_ReceiveFlowControl |
+                   ETH_InitStruct->ETH_TransmitFlowControl); 
+  /* Write to ETHERNET MACFCR */
+  ETH->MACFCTRL = (uint32_t)tmpreg;
+  /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
+  /* Set the ETV bit according to ETH_VLANTagComparison value */
+  /* Set the VL bit according to ETH_VLANTagIdentifier value */  
+  ETH->MACVLT = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | 
+                             ETH_InitStruct->ETH_VLANTagIdentifier); 
+       
+  /*-------------------------------- DMA Config ------------------------------*/
+  /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
+  /* Get the ETHERNET DMAOMR value */  
+  tmpreg = ETH->DMAOPM;
+  /* Clear xx bits */
+  tmpreg &= ETH_DMAOMR_CLEAR_MASK;
+  
+  /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */
+  /* Set the RSF bit according to ETH_ReceiveStoreForward value */
+  /* Set the DFF bit according to ETH_FlushReceivedFrame value */
+  /* Set the TSF bit according to ETH_TransmitStoreForward value */
+  /* Set the TTC bit according to ETH_TransmitThresholdControl value */
+  /* Set the FEF bit according to ETH_ForwardErrorFrames value */
+  /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
+  /* Set the ERTC bit according to ETH_ReceiveThresholdControl value */
+  /* Set the OSF bit according to ETH_SecondFrameOperate value */
+  tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | 
+                  ETH_InitStruct->ETH_ReceiveStoreForward |
+                  ETH_InitStruct->ETH_FlushReceivedFrame |
+                  ETH_InitStruct->ETH_TransmitStoreForward | 
+                  ETH_InitStruct->ETH_TransmitThresholdControl |
+                  ETH_InitStruct->ETH_ForwardErrorFrames |
+                  ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |
+                  ETH_InitStruct->ETH_ReceiveThresholdControl |                                   
+                  ETH_InitStruct->ETH_SecondFrameOperate); 
+  /* Write to ETHERNET DMAOMR */
+  ETH->DMAOPM = (uint32_t)tmpreg;
+  
+  /*----------------------- ETHERNET DMABMR Configuration --------------------*/ 
+  /* Set the AAL bit according to ETH_AddressAlignedBeats value */
+  /* Set the FB bit according to ETH_FixedBurst value */
+  /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
+  /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
+  /* Set the DSL bit according to ETH_DesciptorSkipLength value */
+  /* Set the PR and DA bits according to ETH_DMAArbitration value */         
+  ETH->DMABM = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | 
+                          ETH_InitStruct->ETH_FixedBurst |
+                          ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
+                          ETH_InitStruct->ETH_TxDMABurstLength | 
+                         (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |
+                          ETH_InitStruct->ETH_DMAArbitration |
+                          ETH_DMABM_USP); /* Enable use of separate PBL for Rx and Tx */  
+  /* Return Ethernet configuration success */
+  return ETH_SUCCESS;
+}
+
+/**
+  * @brief  Fills each ETH_InitStruct member with its default value.
+  * @param  ETH_InitStruct: pointer to a ETH_InitType structure which will be initialized.
+  * @retval None
+  */
+void ETH_StructInit(ETH_InitType* ETH_InitStruct)
+{
+  /* ETH_InitStruct members default value */
+  /*------------------------   MAC   -----------------------------------*/     
+  ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;           
+  ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;                   
+  ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;                                                     
+  ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;                                                                                                                          
+  ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;                              
+  ETH_InitStruct->ETH_Speed = ETH_Speed_10M;                       
+  ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;               
+  ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;              
+  ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;                       
+  ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;                                                            
+  ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;                                                                                  
+  ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;                                                         
+  ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;                                                                
+  ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;                                                                                                                  
+  ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;                                                               
+  ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;                                
+  ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;          
+  ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
+  ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;      
+  ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;                                                             
+  ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;      
+  ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;      
+  ETH_InitStruct->ETH_HashTableHigh = 0x0;                
+  ETH_InitStruct->ETH_HashTableLow = 0x0;                     
+  ETH_InitStruct->ETH_PauseTime = 0x0;                 
+  ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;            
+  ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;         
+  ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;   
+  ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;        
+  ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Enable;      
+  ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;          
+  ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;          
+  /*------------------------   DMA   -----------------------------------*/  
+  ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; 
+  ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;       
+  ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;       
+  ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;     
+  ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;  
+  ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;       
+  ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; 
+  ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;   
+  ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
+  ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
+  ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable;
+  ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;
+  ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;
+  ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;
+  ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
+}
+
+/**
+  * @brief  Enables ENET MAC and DMA reception/transmission 
+  * @param  None
+  * @retval None
+  */
+void ETH_Start(void)
+{
+  /* Enable transmit state machine of the MAC for transmission on the MII */  
+  ETH_MACTransmissionCmd(ENABLE);
+  /* Flush Transmit FIFO */
+  ETH_FlushTransmitFIFO();
+  /* Enable receive state machine of the MAC for reception from the MII */  
+  ETH_MACReceptionCmd(ENABLE);
+ 
+  /* Start DMA transmission */
+  ETH_DMATransmissionCmd(ENABLE); 
+  /* Start DMA reception */
+  ETH_DMAReceptionCmd(ENABLE);   
+}
+
+/**
+  * @brief  Transmits a packet, from application buffer, pointed by ppkt.
+  * @param  ppkt: pointer to the application's packet buffer to transmit.
+  * @param  FrameLength: Tx Packet size.
+  * @retval ETH_ERROR: in case of Tx desc owned by DMA
+  *         ETH_SUCCESS: for correct transmission
+  */
+uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength)
+{ 
+  uint32_t offset = 0;
+    
+  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+  if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
+  {
+    /* Return ERROR: OWN bit set */
+    return ETH_ERROR;
+  }
+  
+  /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */      
+  for(offset=0; offset<FrameLength; offset++)       
+  {
+    (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
+  }
+        
+  /* Setting the Frame Length: bits[12:0] */
+  DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);
+  /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */    
+  DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
+  /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
+  /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
+  if ((ETH->DMASTS & ETH_DMASTS_TBU) != (uint32_t)RESET)
+  {
+    /* Clear TBUS ETHERNET DMA flag */
+    ETH->DMASTS = ETH_DMASTS_TBU;
+    /* Resume DMA transmission*/
+    ETH->DMATPD = 0;
+  }
+  
+  /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */  
+  /* Chained Mode */
+  if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
+  {     
+    /* Selects the next DMA Tx descriptor list for next buffer to send */ 
+    DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);    
+  }
+  else /* Ring Mode */
+  {  
+    if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
+    {
+      /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */
+      DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLADDR);      
+    }
+    else
+    {  
+      /* Selects the next DMA Tx descriptor list for next buffer to send */
+      DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABM & ETH_DMABM_DSL) >> 2));      
+    }
+  }
+  /* Return SUCCESS */
+  return ETH_SUCCESS;   
+}
+
+/**
+  * @brief  Receives a packet and copies it to memory pointed by ppkt.
+  * @param  ppkt: pointer to the application packet receive buffer.
+  * @retval ETH_ERROR: if there is error in reception
+  *         framelength: received packet size if packet reception is correct
+  */
+uint32_t ETH_HandleRxPkt(uint8_t *ppkt)
+{ 
+  uint32_t offset = 0, framelength = 0;
+  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+  if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)
+  {
+    /* Return error: OWN bit set */
+    return ETH_ERROR; 
+  }
+  
+  if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && 
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&  
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))  
+  {      
+    /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+    framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;
+    /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
+    for(offset=0; offset<framelength; offset++)       
+    {
+      (*(ppkt + offset)) = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset));
+    }
+  }
+  else
+  {
+    /* Return ERROR */
+    framelength = ETH_ERROR;
+  }
+  /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMARxDescToGet->Status = ETH_DMARxDesc_OWN; 
+ 
+  /* When Rx Buffer unavailable flag is set: clear it and resume reception */
+  if ((ETH->DMASTS & ETH_DMASTS_RBU) != (uint32_t)RESET)  
+  {
+    /* Clear RBUS ETHERNET DMA flag */
+    ETH->DMASTS = ETH_DMASTS_RBU;
+    /* Resume DMA reception */
+    ETH->DMARPD = 0;
+  }
+  
+  /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */      
+  /* Chained Mode */
+  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+  {     
+    /* Selects the next DMA Rx descriptor list for next buffer to read */ 
+    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);    
+  }
+  else /* Ring Mode */
+  {   
+    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+    {
+      /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLADDR);      
+    }
+    else
+    { 
+      /* Selects the next DMA Rx descriptor list for next buffer to read */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABM & ETH_DMABM_DSL) >> 2));      
+    }
+  }
+  
+  /* Return Frame Length/ERROR */
+  return (framelength);  
+}
+
+/**
+  * @brief  Get the size of received the received packet.
+  * @param  None
+  * @retval framelength: received packet size 
+  */
+uint32_t ETH_GetRxPktSize(void)
+{
+  uint32_t frameLength = 0;
+  if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
+  {
+    /* Get the size of the packet: including 4 bytes of the CRC */
+    frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet);
+  }
+ 
+ /* Return Frame Length */ 
+ return frameLength;
+}
+
+/**
+  * @brief  Drop a Received packet (too small packet, etc...)
+  * @param  None
+  * @retval None
+  */
+void ETH_DropRxPkt(void)
+{
+  /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMARxDescToGet->Status = ETH_DMARxDesc_OWN;  
+  /* Chained Mode */
+  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+  {
+    /* Selects the next DMA Rx descriptor list for next buffer read */
+    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
+  }
+  else /* Ring Mode */
+  {
+    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+    {
+      /* Selects the next DMA Rx descriptor list for next buffer read: this will
+         be the first Rx descriptor in this case */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLADDR);
+    }
+    else
+    {
+      /* Selects the next DMA Rx descriptor list for next buffer read */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABM & ETH_DMABM_DSL) >> 2));
+    }
+  }
+}
+
+/*---------------------------------  PHY  ------------------------------------*/
+/**
+  * @brief  Read a PHY register
+  * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. 
+  *   This parameter can be one of the following values: 0,..,31                  
+  * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. 
+  *   This parameter can be one of the following values: 
+  *     @arg PHY_BCR: Tranceiver Basic Control Register 
+  *     @arg PHY_BSR: Tranceiver Basic Status Register 
+  *     @arg PHY_SR : Tranceiver Status Register    
+  *     @arg More PHY register could be read depending on the used PHY
+  * @retval ETH_ERROR: in case of timeout
+  *         MAC MIIDR register value: Data read from the selected PHY register (correct read )
+  */
+uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg)
+{
+  uint32_t tmpreg = 0;     
+__IO uint32_t timeout = 0;
+  /* Check the parameters */
+  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
+  assert_param(IS_ETH_PHY_REG(PHYReg));
+  
+  /* Get the ETHERNET MACMIIAR value */
+  tmpreg = ETH->MACMIIADDR;
+  /* Keep only the CTRLSTS1 Clock Range CR[2:0] bits value */
+  tmpreg &= ~ETH_MACMIIAR_CR_MASK;
+  /* Prepare the MII address register value */
+  tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIADDR_PA); /* Set the PHY device address */
+  tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIADDR_MII);      /* Set the PHY register address */
+  tmpreg &= ~ETH_MACMIIADDR_MIIW;                              /* Set the read mode */
+  tmpreg |= ETH_MACMIIADDR_MIIB;                               /* Set the MII Busy bit */
+  /* Write the result value into the MII Address register */
+  ETH->MACMIIADDR = tmpreg;
+  /* Check for the Busy flag */
+  do
+  {
+    timeout++;
+    tmpreg = ETH->MACMIIADDR;
+  } while ((tmpreg & ETH_MACMIIADDR_MIIB) && (timeout < (uint32_t)PHY_READ_TO));
+  /* Return ERROR in case of timeout */
+  if(timeout == PHY_READ_TO)
+  {
+    return (uint16_t)ETH_ERROR;
+  }
+  
+  /* Return data register value */
+  return (uint16_t)(ETH->MACMIIDT);
+}
+
+/**
+  * @brief  Write to a PHY register
+  * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. 
+  *   This parameter can be one of the following values: 0,..,31
+  * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. 
+  *   This parameter can be one of the following values: 
+  *     @arg PHY_BCR    : Tranceiver Control Register  
+  *     @arg More PHY register could be written depending on the used PHY
+  * @param  PHYValue: the value to write
+  * @retval ETH_ERROR: in case of timeout
+  *         ETH_SUCCESS: for correct write
+  */
+uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue)
+{
+  uint32_t tmpreg = 0;     
+  __IO uint32_t timeout = 0;
+  /* Check the parameters */
+  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
+  assert_param(IS_ETH_PHY_REG(PHYReg));
+  
+  /* Get the ETHERNET MACMIIAR value */
+  tmpreg = ETH->MACMIIADDR;
+  /* Keep only the CTRLSTS1 Clock Range CR[2:0] bits value */
+  tmpreg &= ~ETH_MACMIIAR_CR_MASK;
+  /* Prepare the MII register address value */
+  tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIADDR_PA); /* Set the PHY device address */
+  tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIADDR_MII);      /* Set the PHY register address */
+  tmpreg |= ETH_MACMIIADDR_MIIW;                               /* Set the write mode */
+  tmpreg |= ETH_MACMIIADDR_MIIB;                               /* Set the MII Busy bit */
+  /* Give the value to the MII data register */
+  ETH->MACMIIDT = PHYValue;
+  /* Write the result value into the MII Address register */
+  ETH->MACMIIADDR = tmpreg;
+  /* Check for the Busy flag */
+  do
+  {
+    timeout++;
+    tmpreg = ETH->MACMIIADDR;
+  } while ((tmpreg & ETH_MACMIIADDR_MIIB) && (timeout < (uint32_t)PHY_WRITE_TO));
+  /* Return ERROR in case of timeout */
+  if(timeout == PHY_WRITE_TO)
+  {
+    return ETH_ERROR;
+  }
+  
+  /* Return SUCCESS */
+  return ETH_SUCCESS;  
+}
+
+/**
+  * @brief  Enables or disables the PHY loopBack mode.
+  * @Note: Don't be confused with ETH_MACLoopBackCmd function which enables internal
+  *  loopback at MII level
+  * @param  PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. 
+  *   This parameter can be one of the following values:                   
+  * @param  NewState: new state of the PHY loopBack mode.
+  *   This parameter can be: ENABLE or DISABLE.    
+  * @retval ETH_ERROR: in case of bad PHY configuration
+  *         ETH_SUCCESS: for correct PHY configuration
+  */
+uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState)
+{
+  uint16_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  /* Get the PHY configuration to update it */
+  tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); 
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the PHY loopback mode */
+    tmpreg |= PHY_Loopback;  
+  }
+  else
+  {
+    /* Disable the PHY loopback mode: normal mode */
+    tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback);
+  }
+  /* Update the PHY control register with the new configuration */
+  if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET)
+  {
+    return ETH_SUCCESS;
+  }
+  else
+  {
+    /* Return SUCCESS */
+    return ETH_ERROR; 
+  }   
+}
+
+/*---------------------------------  MAC  ------------------------------------*/
+/**
+  * @brief  Enables or disables the MAC transmission.
+  * @param  NewState: new state of the MAC transmission.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MACTransmissionCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC transmission */
+    ETH->MACCTRL |= ETH_MACCTRL_TE;  
+  }
+  else
+  {
+    /* Disable the MAC transmission */
+    ETH->MACCTRL &= ~ETH_MACCTRL_TE;
+  }
+}
+
+/**
+  * @brief  Enables or disables the MAC reception.
+  * @param  NewState: new state of the MAC reception.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MACReceptionCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC reception */
+    ETH->MACCTRL |= ETH_MACCTRL_RE;  
+  }
+  else
+  {
+    /* Disable the MAC reception */
+    ETH->MACCTRL &= ~ETH_MACCTRL_RE;
+  }
+}
+
+/**
+  * @brief  Checks whether the ETHERNET flow control busy bit is set or not.
+  * @param  None
+  * @retval The new state of flow control busy status bit (SET or RESET).
+  */
+FlagStatus ETH_GetFlowControlBusyStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+  /* The Flow Control register should not be written to until this bit is cleared */
+  if ((ETH->MACFCTRL & ETH_MACFCTRL_FCBBPA) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Initiate a Pause Control Frame (Full-duplex only).
+  * @param  None
+  * @retval None
+  */
+void ETH_InitiatePauseControlFrame(void)  
+{ 
+  /* When Set In full duplex MAC initiates pause control frame */
+  ETH->MACFCTRL |= ETH_MACFCTRL_FCBBPA;  
+}
+
+/**
+  * @brief  Enables or disables the MAC BackPressure operation activation (Half-duplex only).
+  * @param  NewState: new state of the MAC BackPressure operation activation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_BackPressureActivationCmd(FunctionalState NewState)   
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Activate the MAC BackPressure operation */
+    /* In Half duplex: during backpressure, when the MAC receives a new frame,
+    the transmitter starts sending a JAM pattern resulting in a collision */
+    ETH->MACFCTRL |= ETH_MACFCTRL_FCBBPA; 
+  }
+  else
+  {
+    /* Desactivate the MAC BackPressure operation */
+    ETH->MACFCTRL &= ~ETH_MACFCTRL_FCBBPA; 
+  } 
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
+  * @param  ETH_MAC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag   
+  *     @arg ETH_MAC_FLAG_MMCT : MMC transmit flag  
+  *     @arg ETH_MAC_FLAG_MMCR : MMC receive flag   
+  *     @arg ETH_MAC_FLAG_MMC  : MMC flag  
+  *     @arg ETH_MAC_FLAG_PMT  : PMT flag  
+  * @retval The new state of ETHERNET MAC flag (SET or RESET).
+  */
+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); 
+  if ((ETH->MACISTS & ETH_MAC_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET MAC interrupt has occurred or not.
+  * @param  ETH_MAC_IT: specifies the interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MAC_INT_TST   : Time stamp trigger interrupt  
+  *     @arg ETH_MAC_INT_MMCT : MMC transmit interrupt 
+  *     @arg ETH_MAC_INT_MMCR : MMC receive interrupt  
+  *     @arg ETH_MAC_INT_MMC  : MMC interrupt 
+  *     @arg ETH_MAC_INT_PMT  : PMT interrupt 
+  * @retval The new state of ETHERNET MAC interrupt (SET or RESET).
+  */
+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); 
+  if ((ETH->MACISTS & ETH_MAC_IT) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Enables or disables the specified ETHERNET MAC interrupts.
+  * @param  ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be
+  *   enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg ETH_MAC_INT_TST : Time stamp trigger interrupt 
+  *     @arg ETH_MAC_INT_PMT : PMT interrupt 
+  * @param  NewState: new state of the specified ETHERNET MAC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_IT(ETH_MAC_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ETHERNET MAC interrupts */
+    ETH->MACIM &= (~(uint32_t)ETH_MAC_IT);
+  }
+  else
+  {
+    /* Disable the selected ETHERNET MAC interrupts */
+    ETH->MACIM |= ETH_MAC_IT;
+  }
+}
+
+/**
+  * @brief  Configures the selected MAC address.
+  * @param  MacAddr: The MAC addres to configure.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MAC_Address0 : MAC Address0 
+  *     @arg ETH_MAC_Address1 : MAC Address1 
+  *     @arg ETH_MAC_Address2 : MAC Address2
+  *     @arg ETH_MAC_Address3 : MAC Address3
+  * @param  Addr: Pointer on MAC address buffer data (6 bytes).
+  * @retval None
+  */
+void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr)
+{
+  uint32_t tmpreg;
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
+  
+  /* Calculate the selectecd MAC address high register */
+  tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
+  /* Load the selectecd MAC address high register */
+  (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg;
+  /* Calculate the selectecd MAC address low register */
+  tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
+ 
+  /* Load the selectecd MAC address low register */
+  (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg;
+}
+
+/**
+  * @brief  Get the selected MAC address.
+  * @param  MacAddr: The MAC addres to return.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MAC_Address0 : MAC Address0 
+  *     @arg ETH_MAC_Address1 : MAC Address1 
+  *     @arg ETH_MAC_Address2 : MAC Address2
+  *     @arg ETH_MAC_Address3 : MAC Address3
+  * @param  Addr: Pointer on MAC address buffer data (6 bytes).
+  * @retval None
+  */
+void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr)
+{
+  uint32_t tmpreg;
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
+  
+  /* Get the selectecd MAC address high register */
+  tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr));
+ 
+  /* Calculate the selectecd MAC address buffer */
+  Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF);
+  Addr[4] = (tmpreg & (uint8_t)0xFF);
+  /* Load the selectecd MAC address low register */
+  tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr));
+  /* Calculate the selectecd MAC address buffer */
+  Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF);
+  Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF);
+  Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF);
+  Addr[0] = (tmpreg & (uint8_t)0xFF);
+}
+
+/**
+  * @brief  Enables or disables the Address filter module uses the specified
+  *   ETHERNET MAC address for perfect filtering 
+  * @param  MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering.
+  *   This parameter can be one of the following values: 
+  *     @arg ETH_MAC_Address1 : MAC Address1 
+  *     @arg ETH_MAC_Address2 : MAC Address2
+  *     @arg ETH_MAC_Address3 : MAC Address3
+  * @param  NewState: new state of the specified ETHERNET MAC address use.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ETHERNET MAC address for perfect filtering */
+    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1H_AEN;
+  }
+  else
+  {
+    /* Disable the selected ETHERNET MAC address for perfect filtering */
+    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1H_AEN);
+  }
+}
+
+/**
+  * @brief  Set the filter ept_type for the specified ETHERNET MAC address 
+  * @param  MacAddr: specifies the ETHERNET MAC address 
+  *   This parameter can be one of the following values: 
+  *     @arg ETH_MAC_Address1 : MAC Address1 
+  *     @arg ETH_MAC_Address2 : MAC Address2
+  *     @arg ETH_MAC_Address3 : MAC Address3
+  * @param  Filter: specifies the used frame received field for comparaison 
+  *   This parameter can be one of the following values: 
+  *     @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare with the
+  *                                     SA fields of the received frame.
+  *     @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare with the
+  *                                     DA fields of the received frame.
+  * @retval None
+  */
+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
+  assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter));
+  
+  if (Filter != ETH_MAC_AddressFilter_DA)
+  {
+    /* The selected ETHERNET MAC address is used to compare with the SA fields of the
+       received frame. */
+    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1H_SADDR;
+  }
+  else
+  {
+    /* The selected ETHERNET MAC address is used to compare with the DA fields of the
+       received frame. */
+    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1H_SADDR);
+  }
+}
+
+/**
+  * @brief  Set the filter ept_type for the specified ETHERNET MAC address 
+  * @param  MacAddr: specifies the ETHERNET MAC address 
+  *   This parameter can be one of the following values: 
+  *     @arg ETH_MAC_Address1 : MAC Address1 
+  *     @arg ETH_MAC_Address2 : MAC Address2
+  *     @arg ETH_MAC_Address3 : MAC Address3
+  * @param  MaskByte: specifies the used address bytes for comparaison 
+  *   This parameter can be any combination of the following values: 
+  *     @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8].
+  *     @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0].
+  *     @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24].
+  *     @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16].
+  *     @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8].
+  *     @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0].
+  * @retval None
+  */
+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
+  assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte));
+  
+  /* Clear MBC bits in the selected MAC address  high register */
+  (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1H_MBCTRL);
+  /* Set the selected Filetr mask bytes */
+  (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte;
+}
+/*------------------------  DMA Tx/Rx Desciptors -----------------------------*/
+
+/**
+  * @brief  Initializes the DMA Tx descriptors in chain mode.
+  * @param  DMATxDescTab: Pointer on the first Tx desc list 
+  * @param  TxBuff: Pointer on the first TxBuffer list
+  * @param  TxBuffCount: Number of the used Tx desc in the list
+  * @retval None
+  */
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMATxDesc;
+  
+  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+  DMATxDescToSet = DMATxDescTab;
+  /* Fill each DMATxDesc descriptor with the right values */   
+  for(i=0; i < TxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Tx Desc list */
+    DMATxDesc = DMATxDescTab + i;
+    /* Set Second Address Chained bit */
+    DMATxDesc->Status = ETH_DMATxDesc_TCH;  
+       
+    /* Set Buffer1 address pointer */
+    DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
+    
+    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+    if(i < (TxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
+      DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;  
+    }
+  }
+   
+  /* Set Transmit Desciptor List Address Register */
+  ETH->DMATDLADDR = (uint32_t) DMATxDescTab;
+}
+
+/**
+  * @brief  Initializes the DMA Tx descriptors in ring mode.
+  * @param  DMATxDescTab: Pointer on the first Tx desc list 
+  * @param  TxBuff1: Pointer on the first TxBuffer1 list 
+  * @param  TxBuff2: Pointer on the first TxBuffer2 list
+  * @param  TxBuffCount: Number of the used Tx desc in the list
+  *   Note: see decriptor skip length defined in ETH_DMA_InitStruct
+  *   for the number of Words to skip between two unchained descriptors.  
+  * @retval None
+  */
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMATxDesc;
+ 
+  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+  DMATxDescToSet = DMATxDescTab;
+  /* Fill each DMATxDesc descriptor with the right values */  
+  for(i=0; i < TxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Tx Desc list */
+    DMATxDesc = DMATxDescTab + i;
+    /* Set Buffer1 address pointer */
+    DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]);
+    
+    /* Set Buffer2 address pointer */
+    DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]);
+    
+    /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base
+       address of the list, creating a Desciptor Ring */
+    if(i == (TxBuffCount-1))
+    {
+      /* Set Transmit End of Ring bit */
+      DMATxDesc->Status = ETH_DMATxDesc_TER;
+    }
+  }
+   
+  /* Set Transmit Desciptor List Address Register */
+  ETH->DMATDLADDR =  (uint32_t) DMATxDescTab;
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor
+  * @param  ETH_DMATxDescFlag: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine
+  *     @arg ETH_DMATxDesc_IC  : Interrupt on completetion
+  *     @arg ETH_DMATxDesc_LS  : Last Segment
+  *     @arg ETH_DMATxDesc_FS  : First Segment
+  *     @arg ETH_DMATxDesc_DC  : Disable CRC
+  *     @arg ETH_DMATxDesc_DP  : Disable Pad
+  *     @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable
+  *     @arg ETH_DMATxDesc_TER : Transmit End of Ring
+  *     @arg ETH_DMATxDesc_TCH : Second Address Chained
+  *     @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status
+  *     @arg ETH_DMATxDesc_IHE : IP Header Error
+  *     @arg ETH_DMATxDesc_ES  : Error summary
+  *     @arg ETH_DMATxDesc_JT  : Jabber Timeout
+  *     @arg ETH_DMATxDesc_FF  : Frame Flushed: DMA/MTL flushed the frame due to SW flush
+  *     @arg ETH_DMATxDesc_PCE : Payload Checksum Error
+  *     @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission
+  *     @arg ETH_DMATxDesc_NC  : No Carrier: no carrier signal from the tranceiver
+  *     @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision
+  *     @arg ETH_DMATxDesc_EC  : Excessive Collision: transmission aborted after 16 collisions
+  *     @arg ETH_DMATxDesc_VF  : VLAN Frame
+  *     @arg ETH_DMATxDesc_CC  : Collision Count 
+  *     @arg ETH_DMATxDesc_ED  : Excessive Deferral
+  *     @arg ETH_DMATxDesc_UF  : Underflow Error: late data arrival from the memory
+  *     @arg ETH_DMATxDesc_DB  : Deferred Bit
+  * @retval The new state of ETH_DMATxDescFlag (SET or RESET).
+  */
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag));
+  
+  if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Returns the specified ETHERNET DMA Tx Desc collision count.
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor                     
+  * @retval The Transmit descriptor collision counter value.
+  */
+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)
+{
+  /* Return the Receive descriptor frame length */
+  return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT);
+}
+
+/**
+  * @brief  Set the specified DMA Tx Desc Own bit.
+  * @param  DMATxDesc: Pointer on a Tx desc
+  * @retval None
+  */
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc)
+{
+  /* Set the DMA Tx Desc Own bit */
+  DMATxDesc->Status |= ETH_DMATxDesc_OWN;
+}
+
+/**
+  * @brief  Enables or disables the specified DMA Tx Desc Transmit interrupt.
+  * @param  DMATxDesc: Pointer on a Tx desc
+  * @param  NewState: new state of the DMA Tx Desc transmit interrupt.
+  *   This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
+  */
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA Tx Desc Transmit interrupt */
+    DMATxDesc->Status |= ETH_DMATxDesc_IC;
+  }
+  else
+  {
+    /* Disable the DMA Tx Desc Transmit interrupt */
+    DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified DMA Tx Desc Transmit interrupt.
+  * @param  DMATxDesc: Pointer on a Tx desc
+  * @param  DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMATxDesc_LastSegment  : actual Tx desc contain last segment 
+  *     @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment                   
+  * @retval None
+  */
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment));
+  
+  /* Selects the DMA Tx Desc Frame segment */
+  DMATxDesc->Status |= DMATxDesc_FrameSegment;
+}
+
+/**
+  * @brief  Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor 
+  * @param  DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass
+  *     @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum
+  *     @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
+  *     @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header                                                                
+  * @retval None
+  */
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum));
+  
+  /* Set the selected DMA Tx desc checksum insertion control */
+  DMATxDesc->Status |= DMATxDesc_Checksum;
+}
+
+/**
+  * @brief  Enables or disables the DMA Tx Desc CRC.
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor
+  * @param  NewState: new state of the specified DMA Tx Desc CRC.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc CRC */
+    DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC);
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc CRC */
+    DMATxDesc->Status |= ETH_DMATxDesc_DC; 
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Tx Desc end of ring.
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor
+  * @param  NewState: new state of the specified DMA Tx Desc end of ring.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc end of ring */
+    DMATxDesc->Status |= ETH_DMATxDesc_TER;  
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc end of ring */
+    DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); 
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Tx Desc second address chained.
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor
+  * @param  NewState: new state of the specified DMA Tx Desc second address chained.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc second address chained */
+    DMATxDesc->Status |= ETH_DMATxDesc_TCH;  
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc second address chained */
+    DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH); 
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes.
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor
+  * @param  NewState: new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */
+    DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP);
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/
+    DMATxDesc->Status |= ETH_DMATxDesc_DP; 
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Tx Desc time stamp.
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor
+  * @param  NewState: new state of the specified DMA Tx Desc time stamp.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc time stamp */
+    DMATxDesc->Status |= ETH_DMATxDesc_TTSE;  
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc time stamp */
+    DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE); 
+  }
+}
+
+/**
+  * @brief  Configures the specified DMA Tx Desc buffer1 and buffer2 sizes.
+  * @param  DMATxDesc: Pointer on a Tx desc
+  * @param  BufferSize1: specifies the Tx desc buffer1 size.
+  * @param  BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used).
+  * @retval None
+  */
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1));
+  assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2));
+  
+  /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */
+  DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMARXDESC_BUFFER2_SIZESHIFT));
+}
+
+/**
+  * @brief  Initializes the DMA Rx descriptors in chain mode.
+  * @param  DMARxDescTab: Pointer on the first Rx desc list 
+  * @param  RxBuff: Pointer on the first RxBuffer list
+  * @param  RxBuffCount: Number of the used Rx desc in the list
+  * @retval None
+  */
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMARxDesc;
+  
+  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
+  DMARxDescToGet = DMARxDescTab; 
+  /* Fill each DMARxDesc descriptor with the right values */
+  for(i=0; i < RxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Rx Desc list */
+    DMARxDesc = DMARxDescTab+i;
+    /* Set Own bit of the Rx descriptor Status */
+    DMARxDesc->Status = ETH_DMARxDesc_OWN;
+
+    /* Set Buffer1 size and Second Address Chained bit */
+    DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE;  
+    /* Set Buffer1 address pointer */
+    DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
+    
+    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+    if(i < (RxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); 
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
+      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); 
+    }
+  }
+   
+  /* Set Receive Desciptor List Address Register */
+  ETH->DMARDLADDR = (uint32_t) DMARxDescTab;  
+}
+
+/**
+  * @brief  Initializes the DMA Rx descriptors in ring mode.
+  * @param  DMARxDescTab: Pointer on the first Rx desc list 
+  * @param  RxBuff1: Pointer on the first RxBuffer1 list 
+  * @param  RxBuff2: Pointer on the first RxBuffer2 list
+  * @param  RxBuffCount: Number of the used Rx desc in the list
+  *   Note: see decriptor skip length defined in ETH_DMA_InitStruct
+  *   for the number of Words to skip between two unchained descriptors.  
+  * @retval None
+  */
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMARxDesc;
+  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
+  DMARxDescToGet = DMARxDescTab; 
+  /* Fill each DMARxDesc descriptor with the right values */  
+  for(i=0; i < RxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Rx Desc list */
+    DMARxDesc = DMARxDescTab+i; 
+    /* Set Own bit of the Rx descriptor Status */
+    DMARxDesc->Status = ETH_DMARxDesc_OWN; 
+    /* Set Buffer1 size */
+    DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE;  
+    /* Set Buffer1 address pointer */
+    DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]); 
+    
+    /* Set Buffer2 address pointer */
+    DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]); 
+    
+    /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base
+       address of the list, creating a Desciptor Ring */
+    if(i == (RxBuffCount-1))
+    {
+      /* Set Receive End of Ring bit */
+      DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
+    }
+  }
+   
+  /* Set Receive Desciptor List Address Register */
+  ETH->DMARDLADDR = (uint32_t) DMARxDescTab;  
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET Rx Desc flag is set or not.
+  * @param  DMARxDesc: pointer on a DMA Rx descriptor
+  * @param  ETH_DMARxDescFlag: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMARxDesc_OWN:         OWN bit: descriptor is owned by DMA engine 
+  *     @arg ETH_DMARxDesc_AFM:         DA Filter Fail for the rx frame
+  *     @arg ETH_DMARxDesc_ES:          Error summary
+  *     @arg ETH_DMARxDesc_DE:          Desciptor error: no more descriptors for receive frame
+  *     @arg ETH_DMARxDesc_SAF:         SA Filter Fail for the received frame
+  *     @arg ETH_DMARxDesc_LE:          Frame size not matching with length field
+  *     @arg ETH_DMARxDesc_OE:          Overflow Error: Frame was damaged due to buffer overflow
+  *     @arg ETH_DMARxDesc_VLAN:        VLAN Tag: received frame is a VLAN frame
+  *     @arg ETH_DMARxDesc_FS:          First descriptor of the frame
+  *     @arg ETH_DMARxDesc_LS:          Last descriptor of the frame
+  *     @arg ETH_DMARxDesc_IPV4HCE:     IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error 
+  *     @arg ETH_DMARxDesc_LC:          Late collision occurred during reception
+  *     @arg ETH_DMARxDesc_FT:          Frame ept_type - Ethernet, otherwise 802.3
+  *     @arg ETH_DMARxDesc_RWT:         Receive Watchdog Timeout: watchdog timer expired during reception
+  *     @arg ETH_DMARxDesc_RE:          Receive error: error reported by MII interface
+  *     @arg ETH_DMARxDesc_DE:          Dribble bit error: frame contains non int multiple of 8 bits
+  *     @arg ETH_DMARxDesc_CE:          CRC error
+  *     @arg ETH_DMARxDesc_MAMPCE:      Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
+  * @retval The new state of ETH_DMARxDescFlag (SET or RESET).
+  */
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag));
+  if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Set the specified DMA Rx Desc Own bit.
+  * @param  DMARxDesc: Pointer on a Rx desc
+  * @retval None
+  */
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc)
+{
+  /* Set the DMA Rx Desc Own bit */
+  DMARxDesc->Status |= ETH_DMARxDesc_OWN;
+}
+
+/**
+  * @brief  Returns the specified DMA Rx Desc frame length.
+  * @param  DMARxDesc: pointer on a DMA Rx descriptor                     
+  * @retval The Rx descriptor received frame length.
+  */
+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)
+{
+  /* Return the Receive descriptor frame length */
+  return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT);
+}
+
+/**
+  * @brief  Enables or disables the specified DMA Rx Desc receive interrupt.
+  * @param  DMARxDesc: Pointer on a Rx desc
+  * @param  NewState: new state of the specified DMA Rx Desc interrupt.
+  *   This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
+  */
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA Rx Desc receive interrupt */
+    DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC);
+  }
+  else
+  {
+    /* Disable the DMA Rx Desc receive interrupt */
+    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC;
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Rx Desc end of ring.
+  * @param  DMARxDesc: pointer on a DMA Rx descriptor
+  * @param  NewState: new state of the specified DMA Rx Desc end of ring.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Rx Desc end of ring */
+    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;  
+  }
+  else
+  {
+    /* Disable the selected DMA Rx Desc end of ring */
+    DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER); 
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Rx Desc second address chained.
+  * @param  DMARxDesc: pointer on a DMA Rx descriptor
+  * @param  NewState: new state of the specified DMA Rx Desc second address chained.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Rx Desc second address chained */
+    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH;  
+  }
+  else
+  {
+    /* Disable the selected DMA Rx Desc second address chained */
+    DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH); 
+  }
+}
+
+/**
+  * @brief  Returns the specified ETHERNET DMA Rx Desc buffer size.
+  * @param  DMARxDesc: pointer on a DMA Rx descriptor 
+  * @param  DMARxDesc_Buffer: specifies the DMA Rx Desc buffer.
+  *   This parameter can be any one of the following values:
+  *     @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1
+  *     @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2                     
+  * @retval The Receive descriptor frame length.
+  */
+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer));
+  
+  if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1)
+  {
+    /* Return the DMA Rx Desc buffer2 size */
+    return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); 
+  }
+  else
+  {
+    /* Return the DMA Rx Desc buffer1 size */
+    return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); 
+  }
+}
+
+/*---------------------------------  DMA  ------------------------------------*/
+/**
+  * @brief  Resets all MAC subsystem internal registers and logic.
+  * @param  None
+  * @retval None
+  */
+void ETH_SoftwareReset(void)
+{
+  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
+  /* After reset all the registers holds their respective reset values */
+  ETH->DMABM |= ETH_DMABM_SWRST;
+}
+
+/**
+  * @brief  Checks whether the ETHERNET software reset bit is set or not.
+  * @param  None
+  * @retval The new state of DMA Bus Mode register SR bit (SET or RESET).
+  */
+FlagStatus ETH_GetSoftwareResetStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+  if((ETH->DMABM & ETH_DMABM_SWRST) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
+  * @param  ETH_DMA_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag
+  *     @arg ETH_DMA_FLAG_PMT : PMT flag 
+  *     @arg ETH_DMA_FLAG_MMC : MMC flag 
+  *     @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access
+  *     @arg ETH_DMA_FLAG_ReadWriteError    : Error bits 0-write trnsf, 1-read transfr
+  *     @arg ETH_DMA_FLAG_AccessError       : Error bits 0-Rx DMA, 1-Tx DMA
+  *     @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
+  *     @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag  
+  *     @arg ETH_DMA_FLAG_ER  : Early receive flag 
+  *     @arg ETH_DMA_FLAG_FBE : Fatal bus error flag 
+  *     @arg ETH_DMA_FLAG_ET  : Early transmit flag 
+  *     @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag 
+  *     @arg ETH_DMA_FLAG_RPS : Receive process stopped flag 
+  *     @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag 
+  *     @arg ETH_DMA_FLAG_R   : Receive flag 
+  *     @arg ETH_DMA_FLAG_TU  : Underflow flag 
+  *     @arg ETH_DMA_FLAG_RO  : Overflow flag 
+  *     @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag 
+  *     @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag 
+  *     @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag 
+  *     @arg ETH_DMA_FLAG_T   : Transmit flag 
+  * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+  */
+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG)
+{  
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG));
+  if ((ETH->DMASTS & ETH_DMA_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the ETHERNET’s DMA pending flag.
+  * @param  ETH_DMA_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
+  *     @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag 
+  *     @arg ETH_DMA_FLAG_ER  : Early receive flag 
+  *     @arg ETH_DMA_FLAG_FBE : Fatal bus error flag 
+  *     @arg ETH_DMA_FLAG_ETI : Early transmit flag 
+  *     @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag 
+  *     @arg ETH_DMA_FLAG_RPS : Receive process stopped flag 
+  *     @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag 
+  *     @arg ETH_DMA_FLAG_R   : Receive flag 
+  *     @arg ETH_DMA_FLAG_TU  : Transmit Underflow flag 
+  *     @arg ETH_DMA_FLAG_RO  : Receive Overflow flag 
+  *     @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag 
+  *     @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag 
+  *     @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag 
+  *     @arg ETH_DMA_FLAG_T   : Transmit flag
+  * @retval None
+  */
+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG));
+  
+  /* Clear the selected ETHERNET DMA FLAG */
+  ETH->DMASTS = (uint32_t) ETH_DMA_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA interrupt has occured or not.
+  * @param  ETH_DMA_IT: specifies the interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMA_INT_TST : Time-stamp trigger interrupt
+  *     @arg ETH_DMA_INT_PMT : PMT interrupt 
+  *     @arg ETH_DMA_INT_MMC : MMC interrupt
+  *     @arg ETH_DMA_INT_NIS : Normal interrupt summary 
+  *     @arg ETH_DMA_INT_AIS : Abnormal interrupt summary  
+  *     @arg ETH_DMA_INT_ER  : Early receive interrupt 
+  *     @arg ETH_DMA_INT_FBE : Fatal bus error interrupt 
+  *     @arg ETH_DMA_INT_ET  : Early transmit interrupt 
+  *     @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt 
+  *     @arg ETH_DMA_INT_RPS : Receive process stopped interrupt 
+  *     @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt 
+  *     @arg ETH_DMA_INT_R   : Receive interrupt 
+  *     @arg ETH_DMA_INT_TU  : Underflow interrupt 
+  *     @arg ETH_DMA_INT_RO  : Overflow interrupt 
+  *     @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt 
+  *     @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt 
+  *     @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt 
+  *     @arg ETH_DMA_INT_T   : Transmit interrupt 
+  * @retval The new state of ETH_DMA_IT (SET or RESET).
+  */
+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT)
+{  
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT));
+  if ((ETH->DMASTS & ETH_DMA_IT) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the ETHERNET’s DMA IT pending bit.
+  * @param  ETH_DMA_IT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg ETH_DMA_INT_NIS : Normal interrupt summary 
+  *     @arg ETH_DMA_INT_AIS : Abnormal interrupt summary  
+  *     @arg ETH_DMA_INT_ER  : Early receive interrupt 
+  *     @arg ETH_DMA_INT_FBE : Fatal bus error interrupt 
+  *     @arg ETH_DMA_IT_ETI : Early transmit interrupt 
+  *     @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt 
+  *     @arg ETH_DMA_INT_RPS : Receive process stopped interrupt 
+  *     @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt 
+  *     @arg ETH_DMA_INT_R   : Receive interrupt 
+  *     @arg ETH_DMA_INT_TU  : Transmit Underflow interrupt 
+  *     @arg ETH_DMA_INT_RO  : Receive Overflow interrupt 
+  *     @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt 
+  *     @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt 
+  *     @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt 
+  *     @arg ETH_DMA_INT_T   : Transmit interrupt
+  * @retval None
+  */
+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
+  
+  /* Clear the selected ETHERNET DMA IT */
+  ETH->DMASTS = (uint32_t) ETH_DMA_IT;
+}
+
+/**
+  * @brief  Returns the ETHERNET DMA Transmit Process State.
+  * @param  None
+  * @retval The new ETHERNET DMA Transmit Process State:
+  *   This can be one of the following values:
+  *     - ETH_DMA_TransmitProcess_Stopped   : Stopped - Reset or Stop Tx Command issued
+  *     - ETH_DMA_TransmitProcess_Fetching  : Running - fetching the Tx descriptor 
+  *     - ETH_DMA_TransmitProcess_Waiting   : Running - waiting for status
+  *     - ETH_DMA_TransmitProcess_Reading   : unning - reading the data from host memory
+  *     - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe
+  *     - ETH_DMA_TransmitProcess_Closing   : Running - closing Rx descriptor  
+  */
+uint32_t ETH_GetTransmitProcessState(void)
+{
+  return ((uint32_t)(ETH->DMASTS & ETH_DMASTS_TX)); 
+}
+
+/**
+  * @brief  Returns the ETHERNET DMA Receive Process State.
+  * @param  None
+  * @retval The new ETHERNET DMA Receive Process State:
+  *   This can be one of the following values:
+  *     - ETH_DMA_ReceiveProcess_Stopped   : Stopped - Reset or Stop Rx Command issued
+  *     - ETH_DMA_ReceiveProcess_Fetching  : Running - fetching the Rx descriptor 
+  *     - ETH_DMA_ReceiveProcess_Waiting   : Running - waiting for packet
+  *     - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable
+  *     - ETH_DMA_ReceiveProcess_Closing   : Running - closing descriptor
+  *     - ETH_DMA_ReceiveProcess_Queuing   : Running - queuing the recieve frame into host memory  
+  */
+uint32_t ETH_GetReceiveProcessState(void)
+{
+  return ((uint32_t)(ETH->DMASTS & ETH_DMASTS_RECV)); 
+}
+
+/**
+  * @brief  Clears the ETHERNET transmit FIFO.
+  * @param  None                
+  * @retval None
+  */
+void ETH_FlushTransmitFIFO(void)
+{
+  /* Set the Flush Transmit FIFO bit */
+  ETH->DMAOPM |= ETH_DMAOPM_FTXF;  
+}
+
+/**
+  * @brief  Checks whether the ETHERNET transmit FIFO bit is cleared or not.
+  * @param  None                
+  * @retval The new state of ETHERNET flush transmit FIFO bit (SET or RESET).
+  */
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
+{   
+  FlagStatus bitstatus = RESET;
+  if ((ETH->DMAOPM & ETH_DMAOPM_FTXF) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus; 
+}
+
+/**
+  * @brief  Enables or disables the DMA transmission.
+  * @param  NewState: new state of the DMA transmission.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMATransmissionCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA transmission */
+    ETH->DMAOPM |= ETH_DMAOPM_STXE;  
+  }
+  else
+  {
+    /* Disable the DMA transmission */
+    ETH->DMAOPM &= ~ETH_DMAOPM_STXE;
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA reception.
+  * @param  NewState: new state of the DMA reception.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMAReceptionCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA reception */
+    ETH->DMAOPM |= ETH_DMAOPM_SRXE;  
+  }
+  else
+  {
+    /* Disable the DMA reception */
+    ETH->DMAOPM &= ~ETH_DMAOPM_SRXE;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified ETHERNET DMA interrupts.
+  * @param  ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be
+  *   enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg ETH_DMA_INT_NIS : Normal interrupt summary 
+  *     @arg ETH_DMA_INT_AIS : Abnormal interrupt summary  
+  *     @arg ETH_DMA_INT_ER  : Early receive interrupt 
+  *     @arg ETH_DMA_INT_FBE : Fatal bus error interrupt 
+  *     @arg ETH_DMA_INT_ET  : Early transmit interrupt 
+  *     @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt 
+  *     @arg ETH_DMA_INT_RPS : Receive process stopped interrupt 
+  *     @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt 
+  *     @arg ETH_DMA_INT_R   : Receive interrupt 
+  *     @arg ETH_DMA_INT_TU  : Underflow interrupt 
+  *     @arg ETH_DMA_INT_RO  : Overflow interrupt 
+  *     @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt 
+  *     @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt 
+  *     @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt 
+  *     @arg ETH_DMA_INT_T   : Transmit interrupt
+  * @param  NewState: new state of the specified ETHERNET DMA interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ETHERNET DMA interrupts */
+    ETH->DMAIE |= ETH_DMA_IT;
+  }
+  else
+  {
+    /* Disable the selected ETHERNET DMA interrupts */
+    ETH->DMAIE &=(~(uint32_t)ETH_DMA_IT);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA overflow flag is set or not.
+  * @param  ETH_DMA_Overflow: specifies the DMA overflow flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter
+  *     @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter
+  * @retval The new state of ETHERNET DMA overflow Flag (SET or RESET).
+  */
+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow));
+  
+  if ((ETH->DMAMFBOCNT & ETH_DMA_Overflow) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Get the ETHERNET DMA Rx Overflow Missed Frame Counter value.
+  * @param  None
+  * @retval The value of Rx overflow Missed Frame Counter.
+  */
+uint32_t ETH_GetRxOverflowMissedFrameCounter(void)
+{
+  return ((uint32_t)((ETH->DMAMFBOCNT & ETH_DMAMFBOCNT_MFA)>>ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT));
+}
+
+/**
+  * @brief  Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value.
+  * @param  None
+  * @retval The value of Buffer unavailable Missed Frame Counter.
+  */
+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void)
+{
+  return ((uint32_t)(ETH->DMAMFBOCNT) & ETH_DMAMFBOCNT_MFC);
+}
+
+/**
+  * @brief  Get the ETHERNET DMA DMACHTDR register value.
+  * @param  None
+  * @retval The value of the current Tx desc start address.
+  */
+uint32_t ETH_GetCurrentTxDescStartAddress(void)
+{
+  return ((uint32_t)(ETH->DMACTD));
+}
+
+/**
+  * @brief  Get the ETHERNET DMA DMACHRDR register value.
+  * @param  None
+  * @retval The value of the current Rx desc start address.
+  */
+uint32_t ETH_GetCurrentRxDescStartAddress(void)
+{
+  return ((uint32_t)(ETH->DMACRD));
+}
+
+/**
+  * @brief  Get the ETHERNET DMA DMACHTBAR register value.
+  * @param  None
+  * @retval The value of the current Tx buffer address.
+  */
+uint32_t ETH_GetCurrentTxBufferAddress(void)
+{
+  return ((uint32_t)(ETH->DMACTBADDR));
+}
+
+/**
+  * @brief  Get the ETHERNET DMA DMACHRBAR register value.
+  * @param  None
+  * @retval The value of the current Rx buffer address.
+  */
+uint32_t ETH_GetCurrentRxBufferAddress(void)
+{
+  return ((uint32_t)(ETH->DMACRBADDR));
+}
+
+/**
+  * @brief  Resumes the DMA Transmission by writing to the DmaTxPollDemand register
+  *   (the data written could be anything). This forces  the DMA to resume transmission.
+  * @param  None
+  * @retval None.
+  */
+void ETH_ResumeDMATransmission(void)
+{
+  ETH->DMATPD = 0;
+}
+
+/**
+  * @brief  Resumes the DMA Transmission by writing to the DmaRxPollDemand register
+  *   (the data written could be anything). This forces the DMA to resume reception.
+  * @param  None
+  * @retval None.
+  */
+void ETH_ResumeDMAReception(void)
+{
+  ETH->DMARPD = 0;
+}
+
+/*---------------------------------  PMT  ------------------------------------*/
+/**
+  * @brief  Reset Wakeup frame filter register pointer.
+  * @param  None
+  * @retval None
+  */
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
+{  
+  /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */
+  ETH->MACPMTCTRLSTS |= ETH_MACPMTCTRLSTS_WFFPR;  
+}
+
+/**
+  * @brief  Populates the remote wakeup frame registers.
+  * @param  Buffer: Pointer on remote WakeUp Frame Filter Register buffer data (8 words).
+  * @retval None
+  */
+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer)
+{
+  uint32_t i = 0;
+  
+  /* Fill Remote Wake-up Frame Filter register with Buffer data */
+  for(i =0; i<ETH_WAKEUP_REGISTER_LENGTH; i++)
+  {
+    /* Write each time to the same register */ 
+    ETH->MACRWFF = Buffer[i];
+  }
+}
+
+/**
+  * @brief  Enables or disables any unicast packet filtered by the MAC address
+  *   recognition to be a wake-up frame.
+  * @param  NewState: new state of the MAC Global Unicast Wake-Up.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC Global Unicast Wake-Up */
+    ETH->MACPMTCTRLSTS |= ETH_MACPMTCTRLSTS_GLBU;  
+  }
+  else
+  {
+    /* Disable the MAC Global Unicast Wake-Up */ 
+    ETH->MACPMTCTRLSTS &= ~ETH_MACPMTCTRLSTS_GLBU;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET PMT flag is set or not.
+  * @param  ETH_PMT_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset 
+  *     @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received 
+  *     @arg ETH_PMT_FLAG_MPR     : Magic Packet Received
+  * @retval The new state of ETHERNET PMT Flag (SET or RESET).
+  */
+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG));
+  
+  if ((ETH->MACPMTCTRLSTS & ETH_PMT_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Enables or disables the MAC Wake-Up Frame Detection.
+  * @param  NewState: new state of the MAC Wake-Up Frame Detection.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC Wake-Up Frame Detection */
+    ETH->MACPMTCTRLSTS |= ETH_MACPMTCTRLSTS_WFEN;  
+  }
+  else
+  {
+    /* Disable the MAC Wake-Up Frame Detection */ 
+    ETH->MACPMTCTRLSTS &= ~ETH_MACPMTCTRLSTS_WFEN;
+  }
+}
+
+/**
+  * @brief  Enables or disables the MAC Magic Packet Detection.
+  * @param  NewState: new state of the MAC Magic Packet Detection.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC Magic Packet Detection */
+    ETH->MACPMTCTRLSTS |= ETH_MACPMTCTRLSTS_MPEN;  
+  }
+  else
+  {
+    /* Disable the MAC Magic Packet Detection */ 
+    ETH->MACPMTCTRLSTS &= ~ETH_MACPMTCTRLSTS_MPEN;
+  }
+}
+
+/**
+  * @brief  Enables or disables the MAC Power Down.
+  * @param  NewState: new state of the MAC Power Down.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_PowerDownCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC Power Down */
+    /* This puts the MAC in power down mode */
+    ETH->MACPMTCTRLSTS |= ETH_MACPMTCTRLSTS_PD;  
+  }
+  else
+  {
+    /* Disable the MAC Power Down */ 
+    ETH->MACPMTCTRLSTS &= ~ETH_MACPMTCTRLSTS_PD;
+  }
+}
+
+/*---------------------------------  MMC  ------------------------------------*/
+/**
+  * @brief  Enables or disables the MMC Counter Freeze.
+  * @param  NewState: new state of the MMC Counter Freeze.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the MMC Counter Freeze */
+    ETH->MMCCTRL |= ETH_MMCCTRL_MCNTF;
+  }
+  else
+  {
+    /* Disable the MMC Counter Freeze */
+    ETH->MMCCTRL &= ~ETH_MMCCTRL_MCNTF;
+  }
+}
+
+/**
+  * @brief  Enables or disables the MMC Reset On Read.
+  * @param  NewState: new state of the MMC Reset On Read.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MMCResetOnReadCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the MMC Counter reset on read */
+    ETH->MMCCTRL |= ETH_MMCCTRL_RSTOR; 
+  }
+  else
+  {
+    /* Disable the MMC Counter reset on read */
+    ETH->MMCCTRL &= ~ETH_MMCCTRL_RSTOR;
+  }
+}
+
+/**
+  * @brief  Enables or disables the MMC Counter Stop Rollover.
+  * @param  NewState: new state of the MMC Counter Stop Rollover.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Disable the MMC Counter Stop Rollover  */
+    ETH->MMCCTRL &= ~ETH_MMCCTRL_CSR;
+  }
+  else
+  {
+    /* Enable the MMC Counter Stop Rollover */
+    ETH->MMCCTRL |= ETH_MMCCTRL_CSR; 
+  }
+}
+
+/**
+  * @brief  Resets the MMC Counters.
+  * @param  None
+  * @retval None
+  */
+void ETH_MMCCountersReset(void)
+{
+  /* Resets the MMC Counters */
+  ETH->MMCCTRL |= ETH_MMCCTRL_CNTR; 
+}
+
+/**
+  * @brief  Enables or disables the specified ETHERNET MMC interrupts.
+  * @param  ETH_MMC_IT: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+  *   This parameter can be any combination of Tx interrupt or 
+  *   any combination of Rx interrupt (but not both)of the following values: 
+  *     @arg ETH_MMC_INT_TGF   : When Tx good frame counter reaches half the maximum value 
+  *     @arg ETH_MMC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value 
+  *     @arg ETH_MMC_INT_TGFSC : When Tx good single col counter reaches half the maximum value 
+  *     @arg ETH_MMC_INT_RGUF  : When Rx good unicast frames counter reaches half the maximum value  
+  *     @arg ETH_MMC_INT_RFAE  : When Rx alignment error counter reaches half the maximum value 
+  *     @arg ETH_MMC_INT_RFCE  : When Rx crc error counter reaches half the maximum value
+  * @param  NewState: new state of the specified ETHERNET MMC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_ETH_MMC_IT(ETH_MMC_IT));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+   
+  if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
+  {
+    /* Remove egister mak from IT */
+    ETH_MMC_IT &= 0xEFFFFFFF;
+  
+    /* ETHERNET MMC Rx interrupts selected */
+    if (NewState != DISABLE)
+    {
+      /* Enable the selected ETHERNET MMC interrupts */
+      ETH->MMCRIM &=(~(uint32_t)ETH_MMC_IT);
+    }
+    else
+    {
+      /* Disable the selected ETHERNET MMC interrupts */
+      ETH->MMCRIM |= ETH_MMC_IT;    
+    }
+  }
+  else
+  {
+    /* ETHERNET MMC Tx interrupts selected */
+    if (NewState != DISABLE)
+    {
+      /* Enable the selected ETHERNET MMC interrupts */
+      ETH->MMCTIM &=(~(uint32_t)ETH_MMC_IT);
+    }
+    else
+    {
+      /* Disable the selected ETHERNET MMC interrupts */
+      ETH->MMCTIM |= ETH_MMC_IT;    
+    }  
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET MMC IT is set or not.
+  * @param  ETH_MMC_IT: specifies the ETHERNET MMC interrupt.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value  
+  *     @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value 
+  * @retval The value of ETHERNET MMC IT (SET or RESET).
+  */
+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); 
+  
+  if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
+  {
+    /* ETHERNET MMC Rx interrupts selected */
+    /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */ 
+    if ((((ETH->MMCRI & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIM & ETH_MMC_IT) != (uint32_t)RESET))
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+  else
+  {
+    /* ETHERNET MMC Tx interrupts selected */
+    /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */  
+    if ((((ETH->MMCTI & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIM & ETH_MMC_IT) != (uint32_t)RESET))
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }  
+  }    
+    
+  return bitstatus;
+}
+
+/**
+  * @brief  Get the specified ETHERNET MMC register value.
+  * @param  ETH_MMCReg: specifies the ETHERNET MMC register.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MMCCR      : MMC CR register 
+  *     @arg ETH_MMCRIR     : MMC RIR register 
+  *     @arg ETH_MMCTIR     : MMC TIR register 
+  *     @arg ETH_MMCRIMR    : MMC RIMR register 
+  *     @arg ETH_MMCTIMR    : MMC TIMR register 
+  *     @arg ETH_MMCTGFSCCR : MMC TGFSCCR register 
+  *     @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register  
+  *     @arg ETH_MMCTGFCR   : MMC TGFCR register
+  *     @arg ETH_MMCRFCECR  : MMC RFCECR register 
+  *     @arg ETH_MMCRFAECR  : MMC RFAECR register 
+  *     @arg ETH_MMCRGUFCR  : MMC RGUFCRregister 
+  * @retval The value of ETHERNET MMC Register value.
+  */
+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg));
+  
+  /* Return the selected register value */
+  return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg));
+}
+/*---------------------------------  PTP  ------------------------------------*/
+
+/**
+  * @brief  Updated the PTP block for fine correction with the Time Stamp Addend register value.
+  * @param  None
+  * @retval None
+  */
+void ETH_EnablePTPTimeStampAddend(void)
+{
+  /* Enable the PTP block update with the Time Stamp Addend register value */
+  ETH->PTPTSCTRL |= ETH_PTPTSCTRL_TSARU;    
+}
+
+/**
+  * @brief  Enable the PTP Time Stamp interrupt trigger
+  * @param  None
+  * @retval None
+  */
+void ETH_EnablePTPTimeStampInterruptTrigger(void)
+{
+  /* Enable the PTP target time interrupt */
+  ETH->PTPTSCTRL |= ETH_PTPTSCTRL_TSITE;    
+}
+
+/**
+  * @brief  Updated the PTP system time with the Time Stamp Update register value.
+  * @param  None
+  * @retval None
+  */
+void ETH_EnablePTPTimeStampUpdate(void)
+{
+  /* Enable the PTP system time update with the Time Stamp Update register value */
+  ETH->PTPTSCTRL |= ETH_PTPTSCTRL_TSSTU;    
+}
+
+/**
+  * @brief  Initialize the PTP Time Stamp
+  * @param  None
+  * @retval None
+  */
+void ETH_InitializePTPTimeStamp(void)
+{
+  /* Initialize the PTP Time Stamp */
+  ETH->PTPTSCTRL |= ETH_PTPTSCTRL_TSSTI;    
+}
+
+/**
+  * @brief  Selects the PTP Update method
+  * @param  UpdateMethod: the PTP Update method
+  *   This parameter can be one of the following values:
+  *     @arg ETH_PTP_FineUpdate   : Fine Update method 
+  *     @arg ETH_PTP_CoarseUpdate : Coarse Update method 
+  * @retval None
+  */
+void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_UPDATE(UpdateMethod));
+  
+  if (UpdateMethod != ETH_PTP_CoarseUpdate)
+  {
+    /* Enable the PTP Fine Update method */
+    ETH->PTPTSCTRL |= ETH_PTPTSCTRL_TSFCU;
+  }
+  else
+  {
+    /* Disable the PTP Coarse Update method */
+    ETH->PTPTSCTRL &= (~(uint32_t)ETH_PTPTSCTRL_TSFCU);
+  } 
+}
+
+/**
+  * @brief  Enables or disables the PTP time stamp for transmit and receive frames.
+  * @param  NewState: new state of the PTP time stamp for transmit and receive frames
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_PTPTimeStampCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the PTP time stamp for transmit and receive frames */
+    ETH->PTPTSCTRL |= ETH_PTPTSCTRL_TSE;
+  }
+  else
+  {
+    /* Disable the PTP time stamp for transmit and receive frames */
+    ETH->PTPTSCTRL &= (~(uint32_t)ETH_PTPTSCTRL_TSE);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET PTP flag is set or not.
+  * @param  ETH_PTP_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_PTP_FLAG_TSARU : Addend Register Update 
+  *     @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable 
+  *     @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update 
+  *     @arg ETH_PTP_FLAG_TSSTI  : Time Stamp Initialize                       
+  * @retval The new state of ETHERNET PTP Flag (SET or RESET).
+  */
+FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG));
+  
+  if ((ETH->PTPTSCTRL & ETH_PTP_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Sets the system time Sub-Second Increment value.
+  * @param  SubSecondValue: specifies the PTP Sub-Second Increment Register value.
+  * @retval None
+  */
+void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue));
+  /* Set the PTP Sub-Second Increment Register */
+  ETH->PTPSSINC = SubSecondValue;    
+}
+
+/**
+  * @brief  Sets the Time Stamp update sign and values.
+  * @param  Sign: specifies the PTP Time update value sign.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_PTP_PositiveTime : positive time value. 
+  *     @arg ETH_PTP_NegativeTime : negative time value.  
+  * @param  SecondValue: specifies the PTP Time update second value. 
+  * @param  SubSecondValue: specifies the PTP Time update sub-second value.
+  *   This parameter is a 31 bit value, bit32 correspond to the sign.
+  * @retval None
+  */
+void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_TIME_SIGN(Sign));  
+  assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue)); 
+  /* Set the PTP Time Update High Register */
+  ETH->PTPTSHUD = SecondValue;
+  
+  /* Set the PTP Time Update Low Register with sign */
+  ETH->PTPTSLUD = Sign | SubSecondValue;   
+}
+
+/**
+  * @brief  Sets the Time Stamp Addend value.
+  * @param  Value: specifies the PTP Time Stamp Addend Register value.
+  * @retval None
+  */
+void ETH_SetPTPTimeStampAddend(uint32_t Value)
+{
+  /* Set the PTP Time Stamp Addend Register */
+  ETH->PTPTSAD = Value;    
+}
+
+/**
+  * @brief  Sets the Target Time registers values.
+  * @param  HighValue: specifies the PTP Target Time High Register value.
+  * @param  LowValue: specifies the PTP Target Time Low Register value.
+  * @retval None
+  */
+void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue)
+{
+  /* Set the PTP Target Time High Register */
+  ETH->PTPTTH = HighValue;
+  /* Set the PTP Target Time Low Register */
+  ETH->PTPTTL = LowValue;    
+}
+
+/**
+  * @brief  Get the specified ETHERNET PTP register value.
+  * @param  ETH_PTPReg: specifies the ETHERNET PTP register.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_PTPTSCR  : Sub-Second Increment Register 
+  *     @arg ETH_PTPSSIR  : Sub-Second Increment Register 
+  *     @arg ETH_PTPTSHR  : Time Stamp High Register
+  *     @arg ETH_PTPTSLR  : Time Stamp Low Register 
+  *     @arg ETH_PTPTSHUR : Time Stamp High Update Register  
+  *     @arg ETH_PTPTSLUR : Time Stamp Low Update Register
+  *     @arg ETH_PTPTSAR  : Time Stamp Addend Register
+  *     @arg ETH_PTPTTHR  : Target Time High Register 
+  *     @arg ETH_PTPTTLR  : Target Time Low Register 
+  * @retval The value of ETHERNET PTP Register value.
+  */
+uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg));
+  
+  /* Return the selected register value */
+  return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg));
+}
+
+/**
+  * @brief  Initializes the DMA Tx descriptors in chain mode with PTP.
+  * @param  DMATxDescTab: Pointer on the first Tx desc list 
+  * @param  DMAPTPTxDescTab: Pointer on the first PTP Tx desc list
+  * @param  TxBuff: Pointer on the first TxBuffer list
+  * @param  TxBuffCount: Number of the used Tx desc in the list
+  * @retval None
+  */
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab,
+                               uint8_t* TxBuff, uint32_t TxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMATxDesc;
+  
+  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+  DMATxDescToSet = DMATxDescTab;
+  DMAPTPTxDescToSet = DMAPTPTxDescTab;
+  /* Fill each DMATxDesc descriptor with the right values */   
+  for(i=0; i < TxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Tx Desc list */
+    DMATxDesc = DMATxDescTab+i;
+    /* Set Second Address Chained bit and enable PTP */
+    DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE;  
+       
+    /* Set Buffer1 address pointer */
+    DMATxDesc->Buffer1Addr =(uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
+    
+    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+    if(i < (TxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
+      DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;  
+    }
+    /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */
+    (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr;
+    (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr;
+  }
+  /* Store on the last DMAPTPTxDescTab desc status record the first list address */
+  (&DMAPTPTxDescTab[i-1])->Status = (uint32_t) DMAPTPTxDescTab;
+
+  /* Set Transmit Desciptor List Address Register */
+  ETH->DMATDLADDR = (uint32_t) DMATxDescTab;
+}
+
+/**
+  * @brief  Initializes the DMA Rx descriptors in chain mode.
+  * @param  DMARxDescTab: Pointer on the first Rx desc list 
+  * @param  DMAPTPRxDescTab: Pointer on the first PTP Rx desc list
+  * @param  RxBuff: Pointer on the first RxBuffer list
+  * @param  RxBuffCount: Number of the used Rx desc in the list
+  * @retval None
+  */
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab,
+                               uint8_t *RxBuff, uint32_t RxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMARxDesc;
+  
+  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
+  DMARxDescToGet = DMARxDescTab; 
+  DMAPTPRxDescToGet = DMAPTPRxDescTab;
+  /* Fill each DMARxDesc descriptor with the right values */
+  for(i=0; i < RxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Rx Desc list */
+    DMARxDesc = DMARxDescTab+i;
+    /* Set Own bit of the Rx descriptor Status */
+    DMARxDesc->Status = ETH_DMARxDesc_OWN;
+
+    /* Set Buffer1 size and Second Address Chained bit */
+    DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE;  
+    /* Set Buffer1 address pointer */
+    DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
+    
+    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+    if(i < (RxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); 
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
+      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); 
+    }
+    /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */
+    (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr;
+    (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr;
+  }
+  /* Store on the last DMAPTPRxDescTab desc status record the first list address */
+  (&DMAPTPRxDescTab[i-1])->Status = (uint32_t) DMAPTPRxDescTab;
+
+  /* Set Receive Desciptor List Address Register */
+  ETH->DMARDLADDR = (uint32_t) DMARxDescTab;  
+}
+
+/**
+  * @brief  Transmits a packet, from application buffer, pointed by ppkt with Time Stamp values.
+  * @param  ppkt: pointer to application packet buffer to transmit.
+  * @param  FrameLength: Tx Packet size.
+  * @param  PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values.
+  * @retval ETH_ERROR: in case of Tx desc owned by DMA
+  *         ETH_SUCCESS: for correct transmission
+  */
+uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab)
+{
+  uint32_t offset = 0, timeout = 0;
+  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+  if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
+  {
+    /* Return ERROR: OWN bit set */
+    return ETH_ERROR;
+  }
+  /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */      
+  for(offset=0; offset<FrameLength; offset++)
+  {
+    (*(__IO uint8_t *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
+  }
+  /* Setting the Frame Length: bits[12:0] */
+  DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF);
+  /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */    
+  DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
+  /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
+  /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
+  if ((ETH->DMASTS & ETH_DMASTS_TBU) != (uint32_t)RESET)
+  {
+    /* Clear TBUS ETHERNET DMA flag */
+    ETH->DMASTS = ETH_DMASTS_TBU;
+    /* Resume DMA transmission*/
+    ETH->DMATPD = 0;
+  }
+  /* Wait for ETH_DMATxDesc_TTSS flag to be set */
+  do
+  {
+    timeout++;
+  } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));
+  /* Return ERROR in case of timeout */
+  if(timeout == PHY_READ_TO)
+  {
+    return ETH_ERROR;
+  }
+  /* Clear the DMATxDescToSet status register TTSS flag */
+  DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS;
+  *PTPTxTab++ = DMATxDescToSet->Buffer1Addr;
+  *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr;
+  /* Update the ENET DMA current descriptor */
+  /* Chained Mode */
+  if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
+  {  
+    /* Selects the next DMA Tx descriptor list for next buffer read */ 
+    DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr);
+    if(DMAPTPTxDescToSet->Status != 0)
+    { 
+      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status);
+    }
+    else
+    {
+      DMAPTPTxDescToSet++;
+    }
+  }
+  else /* Ring Mode */
+  {  
+    if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
+    {
+      /* Selects the next DMA Tx descriptor list for next buffer read: this will
+         be the first Tx descriptor in this case */
+      DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLADDR); 
+      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLADDR);
+    }
+    else
+    {
+      /* Selects the next DMA Tx descriptor list for next buffer read */
+      DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABM & ETH_DMABM_DSL) >> 2));      
+      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABM & ETH_DMABM_DSL) >> 2));      
+    }
+  }
+  /* Return SUCCESS */
+  return ETH_SUCCESS;
+}
+
+/**
+  * @brief  Receives a packet and copies it to memory pointed by ppkt with Time Stamp values.
+  * @param  ppkt: pointer to application packet receive buffer.  
+  * @param  PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values.
+  * @retval ETH_ERROR: if there is error in reception
+  *         framelength: received packet size if packet reception is correct
+  */
+uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab)
+{
+  uint32_t offset = 0, framelength = 0;
+  /* Check if the descriptor is owned by the ENET or CPU */
+  if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)
+  {
+    /* Return error: OWN bit set */
+    return ETH_ERROR;
+  }
+  if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
+  {
+    /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+    framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;
+    /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ 
+    for(offset=0; offset<framelength; offset++)
+    {
+      (*(ppkt + offset)) = (*(__IO uint8_t *)((DMAPTPRxDescToGet->Buffer1Addr) + offset));
+    }
+  }
+  else
+  {
+    /* Return ERROR */
+    framelength = ETH_ERROR;
+  }
+  /* When Rx Buffer unavailable flag is set: clear it and resume reception */
+  if ((ETH->DMASTS & ETH_DMASTS_RBU) != (uint32_t)RESET)
+  {
+    /* Clear RBUS ETHERNET DMA flag */
+    ETH->DMASTS = ETH_DMASTS_RBU;
+    /* Resume DMA reception */
+    ETH->DMARPD = 0;
+  }
+  *PTPRxTab++ = DMARxDescToGet->Buffer1Addr;
+  *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr;
+  /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMARxDescToGet->Status |= ETH_DMARxDesc_OWN;
+  /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
+  /* Chained Mode */
+  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+  {
+    /* Selects the next DMA Rx descriptor list for next buffer read */
+    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr);
+    if(DMAPTPRxDescToGet->Status != 0)
+    {
+      DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status);
+    }
+    else
+    {
+      DMAPTPRxDescToGet++;
+    }
+  }
+  else /* Ring Mode */
+  {
+    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+    {
+      /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLADDR);
+    }
+    else
+    {
+      /* Selects the next DMA Rx descriptor list for next buffer to read */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABM & ETH_DMABM_DSL) >> 2));      
+    }
+  }
+  /* Return Frame Length/ERROR */
+  return (framelength);
+}
+
+#ifndef USE_Delay
+/**
+  * @brief  Inserts a delay time.
+  * @param  nCount: specifies the delay time length.
+  * @retval None
+  */
+static void ETH_Delay(__IO uint32_t nCount)
+{
+  __IO uint32_t index = 0; 
+  for(index = nCount; index != 0; index--)
+  {
+  }
+}
+#endif /* USE_Delay*/
+
+/**
+  * @}
+  */
+
+#endif /* AT32F407xx */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2009 Artery Technology *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_exti.c

@@ -0,0 +1,261 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_exti.c
+ * Description  : at32f4xx EXTI source file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_exti.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup EXTI
+  * @brief EXTI driver modules
+  * @{
+  */
+
+/** @defgroup EXTI_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Private_Defines
+  * @{
+  */
+
+#define EXTI_LINENONE           ((uint32_t)0x00000)  /* No interrupt selected */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the EXTI peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void EXTI_Reset(void)
+{
+  EXTI->INTEN = 0x00000000;
+  EXTI->EVTEN = 0x00000000;
+  EXTI->RTRSEL = 0x00000000;
+  EXTI->FTRSEL = 0x00000000;
+  EXTI->PND = 0x007FFFFF;
+}
+
+/**
+  * @brief  Initializes the EXTI peripheral according to the specified
+  *         parameters in the EXTI_InitStruct.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitType structure
+  *         that contains the configuration information for the EXTI peripheral.
+  * @retval None
+  */
+void EXTI_Init(EXTI_InitType* EXTI_InitStruct)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineEnable));
+
+  tmp = (uint32_t)EXTI_BASE;
+
+  if (EXTI_InitStruct->EXTI_LineEnable != DISABLE)
+  {
+    /* Clear EXTI line configuration */
+    EXTI->INTEN &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->EVTEN &= ~EXTI_InitStruct->EXTI_Line;
+
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+
+    /* Clear Rising Falling edge configuration */
+    EXTI->RTRSEL &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->FTRSEL &= ~EXTI_InitStruct->EXTI_Line;
+
+    /* Select the trigger for the selected external interrupts */
+    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+    {
+      /* Rising Falling edge */
+      EXTI->RTRSEL |= EXTI_InitStruct->EXTI_Line;
+      EXTI->FTRSEL |= EXTI_InitStruct->EXTI_Line;
+    }
+    else
+    {
+      tmp = (uint32_t)EXTI_BASE;
+      tmp += EXTI_InitStruct->EXTI_Trigger;
+
+      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+    }
+  }
+  else
+  {
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    /* Disable the selected external lines */
+    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
+  }
+}
+
+/**
+  * @brief  Fills each EXTI_InitStruct member with its reset value.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitType structure which will
+  *         be initialized.
+  * @retval None
+  */
+void EXTI_StructInit(EXTI_InitType* EXTI_InitStruct)
+{
+  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+  EXTI_InitStruct->EXTI_LineEnable = DISABLE;
+}
+
+/**
+  * @brief  Generates a Software interrupt.
+  * @param  EXTI_Line: specifies the EXTI lines to be enabled or disabled.
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
+  * @retval None
+  */
+void EXTI_GenerateSWInt(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+
+  EXTI->SWIE |= EXTI_Line;
+}
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  EXTI_Line: specifies the EXTI line flag to check.
+  *   This parameter can be:
+  *     @arg EXTI_Linex: External interrupt line x where x(0..19)
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+  if ((EXTI->PND & EXTI_Line) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
+  * @retval None
+  */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+
+  EXTI->PND = EXTI_Line;
+}
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  EXTI_Line: specifies the EXTI line to check.
+  *   This parameter can be:
+  *     @arg EXTI_Linex: External interrupt line x where x(0..19)
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+ITStatus EXTI_GetIntStatus(uint32_t EXTI_Line)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+  enablestatus =  EXTI->INTEN & EXTI_Line;
+
+  if (((EXTI->PND & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  EXTI_Line: specifies the EXTI lines to clear.
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
+  * @retval None
+  */
+void EXTI_ClearIntPendingBit(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+
+  EXTI->PND = EXTI_Line;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_flash.c

@@ -0,0 +1,2134 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_flash.c
+ * Description  : at32f4xx FMC source file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_flash.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup FLASH
+  * @brief FLASH driver modules
+  * @{
+  */
+
+/** @defgroup FLASH_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Private_Defines
+  * @{
+  */
+
+
+/* Flash Control Register bits */
+#define CTRL_PRGM_Set               ((uint32_t)0x00000001)
+#define CTRL_PRGM_Rst               ((uint32_t)0xFFFFFFFE)
+#define CTRL_PGERS_Set              ((uint32_t)0x00000002)
+#define CTRL_PGERS_Rst              ((uint32_t)0xFFFFFFFD)
+#define CTRL_CHPERS_Set             ((uint32_t)0x00000004)
+#define CTRL_CHPERS_Rst             ((uint32_t)0xFFFFFFFB)
+#define CTRL_UOBPRGM_Set            ((uint32_t)0x00000010)
+#define CTRL_UOBPRGM_Rst            ((uint32_t)0xFFFFFFEF)
+#define CTRL_UOBERS_Set             ((uint32_t)0x00000020)
+#define CTRL_UOBERS_Rst             ((uint32_t)0xFFFFFFDF)
+#define CTRL_STRT_Set               ((uint32_t)0x00000040)
+#define CTRL_LCK_Set                ((uint32_t)0x00000080)
+#define CTRL_UOBWE_Rst              ((uint32_t)0xFFFFFDFF)
+
+/* FLASH Mask */
+#define RDPRT_Mask                  ((uint32_t)0x00000002)
+#define WRPRT0_Mask                 ((uint32_t)0x000000FF)
+#define WRPRT1_Mask                 ((uint32_t)0x0000FF00)
+#define WRPRT2_Mask                 ((uint32_t)0x00FF0000)
+#define WRPRT3_Mask                 ((uint32_t)0xFF000000)
+#define UOB_USR_BTOPT               ((uint16_t)0x0008)
+
+#define OPTION_BYTE_PRT_Key         ((uint16_t)0x00CC)
+
+/* FLASH Keys */
+#define RDPRT_Key                   ((uint16_t)0x00A5)
+#define FLASH_KEY1                  ((uint32_t)0x45670123)
+#define FLASH_KEY2                  ((uint32_t)0xCDEF89AB)
+#define SLIB_UNLOCK_KEY             ((uint32_t)0xA35F6D24)
+
+/* FLASH BANK address */
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+#define FLASH_BNK1_SIZE             ((uint32_t)0x80000)
+#define FLASH_BNK1_END_ADDR         ((uint32_t)0x807FFFF)
+#else
+#define FLASH_BNK1_SIZE             ((*((uint32_t*)0x1FFFF7E0)) * 1024)
+#define FLASH_BNK1_END_ADDR         (((uint32_t)0x8000000) + FLASH_BNK1_SIZE - 1)
+#endif
+#define FLASH_BNK2_END_ADDR         ((uint32_t)0x80FFFFF)
+#define FLASH_BNK3_START_ADDR       ((uint32_t)0x8400000)
+#if defined (AT32F415xx)
+#define FLASH_SYSMEM_START_ADDR     ((uint32_t)0x1FFFAC00)
+#define FLASH_SYSMEM_END_ADDR       ((uint32_t)0x1FFFF3FF)
+#endif
+
+/* Delay definition */
+#define ERS_TIMEOUT                 ((uint32_t)0x10000000)
+#define PRGM_TIMEOUT                ((uint32_t)0x0000F000)
+#define EXT_FLASH_ERS_TIMEOUT       ((uint32_t)0xFFFFFFFF)
+#define EXT_FLASH_PRGM_TIMEOUT      ((uint32_t)0x00080000)
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Private_Macros
+  * @{
+  */
+#define IS_SYS_BOOTLOADER()       ((FLASH->SLIB_CDR0 & FLASH_SLIB_CDR0_BOOT_DIS) == 0x0)
+#define IS_RDP_DISABLE()          (FLASH_GetReadProtectStatus() == RESET)
+                                    
+#define IS_MAIN_SLIB()             ((FLASH->SLIB_CDR0 & FLASH_SLIB_CDR0_SLIB_EN)? 1:0)
+#define IS_SYS_SLIB()             ((FLASH->SLIB_CDR0 & FLASH_SLIB_CDR0_SYS_SLIB_EN)? TRUE:FALSE)
+#define IS_SLIB_DISABLE()          (IS_MAIN_SLIB()? 0:1)
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Unlocks the FLASH Controller.
+  * @note   This function can be used for all at32f4xx devices.
+  *         - For AT32F4xx XL-Density devices this function unlocks Bank1 and Bank2.
+  *         - For all other devices it unlocks Bank1 and it is equivalent
+  *           to FLASH_UnlockBank1 function..
+  * @param  None
+  * @retval None
+  */
+void FLASH_Unlock(void)
+{
+  /* Authorize the FC of Bank1 Access */
+  FLASH->FCKEY = FLASH_KEY1;
+  FLASH->FCKEY = FLASH_KEY2;
+
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+  /* Authorize the FC of Bank2 Access */
+  FLASH->FCKEY2 = FLASH_KEY1;
+  FLASH->FCKEY2 = FLASH_KEY2;
+#endif
+}
+/**
+  * @brief  Unlocks the FLASH Bank1 Controller.
+  * @note   This function can be used for all at32f4xx devices.
+  *         - For AT32F4xx XL-Density devices this function unlocks Bank1.
+  *         - For all other devices it unlocks Bank1 and it is
+  *           equivalent to FLASH_Unlock function.
+  * @param  None
+  * @retval None
+  */
+void FLASH_UnlockBank1(void)
+{
+  /* Authorize the FC of Bank1 Access */
+  FLASH->FCKEY = FLASH_KEY1;
+  FLASH->FCKEY = FLASH_KEY2;
+}
+
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+/**
+  * @brief  Unlocks the FLASH Bank2 Controller.
+  * @note   This function can be used only for AT32F4xx XL-Density devices.
+  * @param  None
+  * @retval None
+  */
+void FLASH_UnlockBank2(void)
+{
+  /* Authorize the FC of Bank2 Access */
+  FLASH->FCKEY2 = FLASH_KEY1;
+  FLASH->FCKEY2 = FLASH_KEY2;
+
+}
+#endif
+
+#if !defined (AT32F415xx)
+/**
+  * @brief  Unlocks the FLASH Bank3 Controller for external flash.
+  * @note   This function can not be used for AT32F415 devices.
+  * @param  None
+  * @retval None
+  */
+void FLASH_UnlockBank3(void)
+{
+  /* Authorize the FC of Bank3 Access */
+  FLASH->FCKEY3 = FLASH_KEY1;
+  FLASH->FCKEY3 = FLASH_KEY2;
+}
+#endif
+
+/**
+  * @brief  Locks the FLASH Controller.
+  * @note   This function can be used for all at32f4xx devices.
+  *         - For AT32F4xx XL-Density devices this function Locks Bank1 and Bank2.
+  *         - For all other devices it Locks Bank1 and it is equivalent
+  *           to FLASH_LockBank1 function.
+  * @param  None
+  * @retval None
+  */
+void FLASH_Lock(void)
+{
+  /* Set the Lock Bit to lock the FC and the CTRL of  Bank1 */
+  FLASH->CTRL |= CTRL_LCK_Set;
+
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+  /* Set the Lock Bit to lock the FC and the CTRL of  Bank2 */
+  FLASH->CTRL2 |= CTRL_LCK_Set;
+#endif
+}
+
+/**
+  * @brief  Locks the FLASH Bank1 Controller.
+  * @note   this function can be used for all at32f4xx devices.
+  *         - For AT32F4xx XL-Density devices this function Locks Bank1.
+  *         - For all other devices it Locks Bank1 and it is equivalent
+  *           to FLASH_Lock function.
+  * @param  None
+  * @retval None
+  */
+void FLASH_LockBank1(void)
+{
+  /* Set the Lock Bit to lock the FC and the CTRL of  Bank1 */
+  FLASH->CTRL |= CTRL_LCK_Set;
+}
+
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+/**
+  * @brief  Locks the FLASH Bank2 Controller.
+  * @note   This function can be used only for AT32F4xx XL-Density devices.
+  * @param  None
+  * @retval None
+  */
+void FLASH_LockBank2(void)
+{
+  /* Set the Lock Bit to lock the FC and the CTRL of  Bank2 */
+  FLASH->CTRL2 |= CTRL_LCK_Set;
+}
+#endif
+
+#if !defined (AT32F415xx)
+/**
+  * @brief  Locks the FLASH Bank3 Controller for external flash.
+  * @note   This function can not be used for AT32F415 devices.
+  * @param  None
+  * @retval None
+  */
+void FLASH_LockBank3(void)
+{
+  /* Set the Lock Bit to lock the FC and the CTRL of  Bank3 */
+  FLASH->CTRL3 |= CTRL_LCK_Set;
+}
+#endif
+
+/**
+  * @brief  Erases a specified FLASH page.
+  * @note   This function can be used for all at32f4xx devices.
+  * @param  Page_Address: The page address to be erased.
+  * @retval FLASH Status: The returned value can be: FLASH_BSY, FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDR(Page_Address));
+
+#if !defined (AT32F415xx)
+  /* BANK3 : External flash */
+  if(Page_Address >= FLASH_BNK3_START_ADDR)
+  {
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForBank3Process(EXT_FLASH_ERS_TIMEOUT);
+
+    if(status == FLASH_PRC_DONE)
+    {
+      /* if the previous process is completed, continue to erase the page */
+      FLASH->CTRL3 |= CTRL_PGERS_Set;
+      FLASH->ADDR3 = Page_Address;
+      FLASH->CTRL3 |= CTRL_STRT_Set;
+
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForBank3Process(EXT_FLASH_ERS_TIMEOUT);
+
+      /* Disable the PGERS Bit */
+      FLASH->CTRL3 &= CTRL_PGERS_Rst;
+    }
+
+    return status;
+  }
+#endif
+#if defined (AT32F415xx)
+  if(Page_Address >= FLASH_SYSMEM_START_ADDR && Page_Address <= FLASH_SYSMEM_END_ADDR)
+  {
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForProcess(ERS_TIMEOUT);
+
+    if(status == FLASH_PRC_DONE)
+    {
+      /* if the previous process is completed, continue to erase the page */
+      FLASH->CTRL |= CTRL_PGERS_Set;
+      FLASH->ADDR = Page_Address;
+      FLASH->CTRL |= CTRL_STRT_Set;
+
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForProcess(ERS_TIMEOUT);
+
+      /* Disable the PGERS Bit */
+      FLASH->CTRL &= CTRL_PGERS_Rst;
+    }
+  }
+#endif
+  
+  if(Page_Address <= FLASH_BNK1_END_ADDR)
+  {
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForBank1Process(ERS_TIMEOUT);
+
+    if(status == FLASH_PRC_DONE)
+    {
+      /* if the previous process is completed, continue to erase the page */
+      FLASH->CTRL |= CTRL_PGERS_Set;
+      FLASH->ADDR = Page_Address;
+      FLASH->CTRL |= CTRL_STRT_Set;
+
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForBank1Process(ERS_TIMEOUT);
+
+      /* Disable the PGERS Bit */
+      FLASH->CTRL &= CTRL_PGERS_Rst;
+    }
+  }
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+  else if((Page_Address > FLASH_BNK1_END_ADDR)&&(Page_Address <= FLASH_BNK2_END_ADDR))
+  {
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForBank2Process(ERS_TIMEOUT);
+
+    if(status == FLASH_PRC_DONE)
+    {
+      /* if the previous process is completed, continue to erase the page */
+      FLASH->CTRL2 |= CTRL_PGERS_Set;
+      FLASH->ADDR2 = Page_Address;
+      FLASH->CTRL2 |= CTRL_STRT_Set;
+
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForBank2Process(ERS_TIMEOUT);
+
+      /* Disable the PGERS Bit */
+      FLASH->CTRL2 &= CTRL_PGERS_Rst;
+    }
+  }
+#endif
+
+  /* Return the Erase Status */
+  return status;
+}
+
+/**
+  * @brief  Erases all internal FLASH pages.
+  * @note   This function can be used for all at32f4xx devices.
+  *         This function will not erase external flash pages.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EraseAllPages(void)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+  /* Wait for last process to be completed */
+  status = FLASH_WaitForBank1Process(ERS_TIMEOUT);
+
+  if(status == FLASH_PRC_DONE)
+  {
+    /* if the previous process is completed, continue to erase all pages */
+    FLASH->CTRL |= CTRL_CHPERS_Set;
+    FLASH->CTRL |= CTRL_STRT_Set;
+
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForBank1Process(ERS_TIMEOUT);
+
+    /* Disable the CHPERS Bit */
+    FLASH->CTRL &= CTRL_CHPERS_Rst;
+  }
+
+  if(status == FLASH_PRC_DONE)
+  {
+    /* if the previous process is completed, continue to erase all pages */
+    FLASH->CTRL2 |= CTRL_CHPERS_Set;
+    FLASH->CTRL2 |= CTRL_STRT_Set;
+
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForBank2Process(ERS_TIMEOUT);
+
+    /* Disable the CHPERS Bit */
+    FLASH->CTRL2 &= CTRL_CHPERS_Rst;
+  }
+
+#else
+  /* Wait for last process to be completed */
+  status = FLASH_WaitForProcess(ERS_TIMEOUT);
+
+  if(status == FLASH_PRC_DONE)
+  {
+    /* if the previous process is completed, continue to erase all pages */
+    FLASH->CTRL |= CTRL_CHPERS_Set;
+    FLASH->CTRL |= CTRL_STRT_Set;
+
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForProcess(ERS_TIMEOUT);
+
+    /* Disable the CHPERS Bit */
+    FLASH->CTRL &= CTRL_CHPERS_Rst;
+  }
+
+#endif
+
+  /* Return the Erase Status */
+  return status;
+}
+
+/**
+  * @brief  Erases all Bank1 FLASH pages.
+  * @note   This function can be used for all at32f4xx devices.
+  *         - For AT32F4xx XL-Density devices this function erases all Bank1 pages.
+  *         - For all other devices it erases all Bank1 pages and it is equivalent
+  *           to FLASH_EraseAllPages function.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EraseBank1AllPages(void)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+  /* Wait for last process to be completed */
+  status = FLASH_WaitForBank1Process(ERS_TIMEOUT);
+
+  if(status == FLASH_PRC_DONE)
+  {
+    /* if the previous process is completed, continue to erase all pages */
+    FLASH->CTRL |= CTRL_CHPERS_Set;
+    FLASH->CTRL |= CTRL_STRT_Set;
+
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForBank1Process(ERS_TIMEOUT);
+
+    /* Disable the CHPERS Bit */
+    FLASH->CTRL &= CTRL_CHPERS_Rst;
+  }
+
+  /* Return the Erase Status */
+  return status;
+}
+
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+/**
+  * @brief  Erases all Bank2 FLASH pages.
+  * @note   This function can be used only for at32f4xx XL-Density devices.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EraseBank2AllPages(void)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+  /* Wait for last process to be completed */
+  status = FLASH_WaitForBank2Process(ERS_TIMEOUT);
+
+  if(status == FLASH_PRC_DONE)
+  {
+    /* if the previous process is completed, continue to erase all pages */
+    FLASH->CTRL2 |= CTRL_CHPERS_Set;
+    FLASH->CTRL2 |= CTRL_STRT_Set;
+
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForBank2Process(ERS_TIMEOUT);
+
+    /* Disable the CHPERS Bit */
+    FLASH->CTRL2 &= CTRL_CHPERS_Rst;
+  }
+
+  /* Return the Erase Status */
+  return status;
+}
+#endif
+
+#if !defined (AT32F415xx)
+/**
+  * @brief  Erases all Bank3 FLASH pages.
+  * @note   This function can not be used for AT32F415 devices.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EraseBank3AllPages(void)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+  if(FLASH_GetSlibState())
+    return FLASH_PGRM_FLR;
+  /* Wait for last process to be completed */
+  status = FLASH_WaitForBank3Process(EXT_FLASH_ERS_TIMEOUT);
+
+  if(status == FLASH_PRC_DONE)
+  {
+    /* if the previous process is completed, continue to erase all pages */
+    FLASH->CTRL3 |= CTRL_CHPERS_Set;
+    FLASH->CTRL3 |= CTRL_STRT_Set;
+
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForBank3Process(EXT_FLASH_ERS_TIMEOUT);
+
+    /* Disable the CHPERS Bit */
+    FLASH->CTRL3 &= CTRL_CHPERS_Rst;
+  }
+
+  /* Return the Erase Status */
+  return status;
+}
+#endif
+
+/**
+  * @brief  Erases the FLASH option bytes.
+  * @note   This functions erases all option bytes except the Read protection (RDP).
+  * @note   This function can be used for all at32f4xx devices.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EraseUserOptionBytes(void)
+{
+  uint16_t rdptmp = RDPRT_Key;
+
+  FLASH_Status status = FLASH_PRC_DONE;
+
+  /* Get the actual read protection Option Byte value */
+  if(FLASH_GetReadProtectStatus() != RESET)
+  {
+    rdptmp = 0x00;
+  }
+
+  /* Wait for last process to be completed */
+  status = FLASH_WaitForProcess(ERS_TIMEOUT);
+
+  if(status == FLASH_PRC_DONE)
+  {
+    /* Authorize the small information block programming */
+    FLASH->OPTKEYR = FLASH_KEY1;
+    FLASH->OPTKEYR = FLASH_KEY2;
+
+    /* if the previous process is completed, continue to erase the option bytes */
+    FLASH->CTRL |= CTRL_UOBERS_Set;
+    FLASH->CTRL |= CTRL_STRT_Set;
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForProcess(ERS_TIMEOUT);
+
+    if(status == FLASH_PRC_DONE)
+    {
+      /* if the erase process is completed, disable the UOBERS Bit */
+      FLASH->CTRL &= CTRL_UOBERS_Rst;
+
+      /* Enable the Option Bytes Programming process */
+      FLASH->CTRL |= CTRL_UOBPRGM_Set;
+      /* Restore the last read protection Option Byte value */
+      UOPTB->RDPRT = (uint16_t)rdptmp;
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+
+      if(status != FLASH_TIMEOUT)
+      {
+        /* if the program process is completed, disable the UOBPRGM Bit */
+        FLASH->CTRL &= CTRL_UOBPRGM_Rst;
+      }
+    }
+    else
+    {
+      if (status != FLASH_TIMEOUT)
+      {
+        /* Disable the UOBPRGM Bit */
+        FLASH->CTRL &= CTRL_UOBPRGM_Rst;
+      }
+    }
+  }
+
+  /* Return the erase status */
+  return status;
+}
+
+/**
+  * @brief  Programs a word at a specified address.
+  * @note   This function can be used for all at32f4xx devices.
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDR(Address));
+
+#if !defined (AT32F415xx)
+  if (Address >= FLASH_BNK3_START_ADDR)
+  {
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForBank3Process(PRGM_TIMEOUT);
+
+    if(status == FLASH_PRC_DONE)
+    {
+      FLASH->CTRL3 |= CTRL_PRGM_Set;
+
+      *(__IO uint32_t*) Address = Data;
+
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForBank3Process(PRGM_TIMEOUT);
+
+      /* Disable the PRGM Bit */
+      FLASH->CTRL3 &= CTRL_PRGM_Rst;
+    }
+
+    return status;
+  }
+#endif
+#if defined (AT32F415xx)
+  if(Address >= FLASH_SYSMEM_START_ADDR && Address <= FLASH_SYSMEM_END_ADDR)
+  {
+    status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+    if(status == FLASH_PRC_DONE)
+    {
+      /* if the previous process is completed, continue to program the new data */
+      FLASH->CTRL |= CTRL_PRGM_Set;
+
+      *(__IO uint32_t*)Address = Data;
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+
+      /* Disable the PRGM Bit */
+      FLASH->CTRL &= CTRL_PRGM_Rst;
+    }
+  }
+#endif  
+  
+  if(Address <= FLASH_BNK1_END_ADDR)
+  {
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForBank1Process(PRGM_TIMEOUT);
+
+    if(status == FLASH_PRC_DONE)
+    {
+      FLASH->CTRL |= CTRL_PRGM_Set;
+
+      *(__IO uint32_t*) Address = Data;
+
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+
+      /* Disable the PRGM Bit */
+      FLASH->CTRL &= CTRL_PRGM_Rst;
+    }
+  }
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+  else if((Address > FLASH_BNK1_END_ADDR)&&(Address <= FLASH_BNK2_END_ADDR))
+  {
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForBank2Process(PRGM_TIMEOUT);
+
+    if(status == FLASH_PRC_DONE)
+    {
+      FLASH->CTRL2 |= CTRL_PRGM_Set;
+
+      *(__IO uint32_t*) Address = Data;
+
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForBank2Process(PRGM_TIMEOUT);
+
+      /* Disable the PRGM Bit */
+      FLASH->CTRL2 &= CTRL_PRGM_Rst;
+    }
+  }
+#endif
+
+  /* Return the Program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a half word at a specified address.
+  * @note   This function can be used for all at32f4xx devices.
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDR(Address));
+
+#if !defined (AT32F415xx)
+  if (Address >= FLASH_BNK3_START_ADDR)
+  {
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForBank3Process(PRGM_TIMEOUT);
+
+    if(status == FLASH_PRC_DONE)
+    {
+      /* if the previous process is completed, continue to program the new data */
+      FLASH->CTRL3 |= CTRL_PRGM_Set;
+
+      *(__IO uint16_t*)Address = Data;
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForBank3Process(PRGM_TIMEOUT);
+
+      /* Disable the PRGM Bit */
+      FLASH->CTRL3 &= CTRL_PRGM_Rst;
+    }
+    return status;
+  }
+#endif
+#if defined (AT32F415xx)
+  if(Address >= FLASH_SYSMEM_START_ADDR && Address <= FLASH_SYSMEM_END_ADDR)
+  {
+    status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+    if(status == FLASH_PRC_DONE)
+    {
+      /* if the previous process is completed, continue to program the new data */
+      FLASH->CTRL |= CTRL_PRGM_Set;
+
+      *(__IO uint16_t*)Address = Data;
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+
+      /* Disable the PRGM Bit */
+      FLASH->CTRL &= CTRL_PRGM_Rst;
+    }
+  }
+#endif
+
+  /* Wait for last process to be completed */
+  if(Address <= FLASH_BNK1_END_ADDR)
+  {
+    status = FLASH_WaitForBank1Process(PRGM_TIMEOUT);
+    if(status == FLASH_PRC_DONE)
+    {
+      /* if the previous process is completed, continue to program the new data */
+      FLASH->CTRL |= CTRL_PRGM_Set;
+
+      *(__IO uint16_t*)Address = Data;
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForBank1Process(PRGM_TIMEOUT);
+
+      /* Disable the PRGM Bit */
+      FLASH->CTRL &= CTRL_PRGM_Rst;
+    }
+  }
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+  else if((Address > FLASH_BNK1_END_ADDR)&&(Address <= FLASH_BNK2_END_ADDR))
+  {
+    status = FLASH_WaitForBank2Process(PRGM_TIMEOUT);
+    if(status == FLASH_PRC_DONE)
+    {
+      /* if the previous process is completed, continue to program the new data */
+      FLASH->CTRL2 |= CTRL_PRGM_Set;
+
+      *(__IO uint16_t*)Address = Data;
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForBank2Process(PRGM_TIMEOUT);
+
+      /* Disable the PRGM Bit */
+      FLASH->CTRL2 &= CTRL_PRGM_Rst;
+    }
+  }
+#endif
+
+  /* Return the Program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a byte at a specified address.
+  * @note   This function can be used for all at32f4xx devices.
+            This function cannot be used to program bank3.
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDR(Address));
+
+#if !defined (AT32F415xx)
+  if (Address >= FLASH_BNK3_START_ADDR)
+  {
+    /* This function cannot be used to program bank3 */
+    return FLASH_WRPRT_FLR;
+  }
+#endif
+#if defined (AT32F415xx)
+  if(Address >= FLASH_SYSMEM_START_ADDR && Address <= FLASH_SYSMEM_END_ADDR)
+  {
+    status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+    if(status == FLASH_PRC_DONE)
+    {
+      /* if the previous process is completed, continue to program the new data */
+      FLASH->CTRL |= CTRL_PRGM_Set;
+
+      *(__IO uint8_t*)Address = Data;
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+
+      /* Disable the PRGM Bit */
+      FLASH->CTRL &= CTRL_PRGM_Rst;
+    }
+  }
+#endif
+  
+  if(Address <= FLASH_BNK1_END_ADDR)
+  {
+    status = FLASH_WaitForBank1Process(PRGM_TIMEOUT);
+    if(status == FLASH_PRC_DONE)
+    {
+      /* if the previous process is completed, continue to program the new data */
+      FLASH->CTRL |= CTRL_PRGM_Set;
+
+      *(__IO uint8_t*)Address = Data;
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForBank1Process(PRGM_TIMEOUT);
+
+      /* Disable the PRGM Bit */
+      FLASH->CTRL &= CTRL_PRGM_Rst;
+    }
+  }
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+  else if((Address > FLASH_BNK1_END_ADDR)&&(Address <= FLASH_BNK2_END_ADDR))
+  {
+    status = FLASH_WaitForBank2Process(PRGM_TIMEOUT);
+    if(status == FLASH_PRC_DONE)
+    {
+      /* if the previous process is completed, continue to program the new data */
+      FLASH->CTRL2 |= CTRL_PRGM_Set;
+
+      *(__IO uint8_t*)Address = Data;
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForBank2Process(PRGM_TIMEOUT);
+
+      /* Disable the PRGM Bit */
+      FLASH->CTRL2 &= CTRL_PRGM_Rst;
+    }
+  }  
+#endif
+  /* Return the Program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a half word at a specified Option Byte Data address.
+  * @note   This function can be used for all at32f4xx devices.
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ProgramUserOptionByteData(uint32_t Address, uint8_t Data)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+  status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+
+  if(status == FLASH_PRC_DONE)
+  {
+    /* Authorize the small information block programming */
+    FLASH->OPTKEYR = FLASH_KEY1;
+    FLASH->OPTKEYR = FLASH_KEY2;
+    /* Enables the Option Bytes Programming process */
+    FLASH->CTRL |= CTRL_UOBPRGM_Set;
+    *(__IO uint16_t*)Address = Data;
+
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program process is completed, disable the UOBPRGM Bit */
+      FLASH->CTRL &= CTRL_UOBPRGM_Rst;
+    }
+  }
+
+  /* Return the Option Byte Data Program Status */
+  return status;
+}
+
+/**
+  * @brief  Write protects the desired pages
+  * @note   This function can be used for all at32f4xx devices.
+  * @param  FLASH_Pages: specifies the address of the pages to be write protected.
+  *   This parameter can be:
+  *     @arg For @b AT32F415xx devices: value between FLASH_WRPRT_PAGE_0to1 and
+  *       FLASH_WRPRT_PAGE_60to61 or FLASH_WRPRT_PAGE_62to63 or FLASH_WRPRT_PAGE_62to127
+  *     @arg For @b AT32F4xx Medium-density_devices: value between FLASH_WRPRT_PAGE_0to3 and
+  *       FLASH_WRPRT_PAGE_60to63 or FLASH_WRPRT_PAGE_124to127
+  *     @arg For @b AT32F4xx High-density_devices: value between FLASH_WRPRT_PAGE_0to1 and
+  *       FLASH_WRPRT_PAGE_60to61 or FLASH_WRPRT_PAGE_62to127 or FLASH_WRPRT_PAGE_62to255
+  *     @arg For @b AT32F4xx XL-density_devices: value between FLASH_WRPRT_PAGE_0to1 and
+  *       FLASH_WRPRT_PAGE_60to61 or FLASH_WRPRT_PAGE_62to511
+  *     @arg FLASH_WRPRT_AllPAGES
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EnableWriteProtect(uint32_t FLASH_Pages)
+{
+  uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+
+  FLASH_Status status = FLASH_PRC_DONE;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_WRPRT_PAGES(FLASH_Pages));
+
+  FLASH_Pages = (uint32_t)(~FLASH_Pages);
+  WRP0_Data = (uint16_t)(FLASH_Pages & WRPRT0_Mask);
+  WRP1_Data = (uint16_t)((FLASH_Pages & WRPRT1_Mask) >> 8);
+  WRP2_Data = (uint16_t)((FLASH_Pages & WRPRT2_Mask) >> 16);
+  WRP3_Data = (uint16_t)((FLASH_Pages & WRPRT3_Mask) >> 24);
+
+  /* Wait for last process to be completed */
+  status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+
+  if(status == FLASH_PRC_DONE)
+  {
+    /* Authorizes the small information block programming */
+    FLASH->OPTKEYR = FLASH_KEY1;
+    FLASH->OPTKEYR = FLASH_KEY2;
+    FLASH->CTRL |= CTRL_UOBPRGM_Set;
+
+    if(WRP0_Data != 0xFF)
+    {
+      UOPTB->WRPRT0 = WRP0_Data;
+
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+    }
+
+    if((status == FLASH_PRC_DONE) && (WRP1_Data != 0xFF))
+    {
+      UOPTB->WRPRT1 = WRP1_Data;
+
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+    }
+
+    if((status == FLASH_PRC_DONE) && (WRP2_Data != 0xFF))
+    {
+      UOPTB->WRPRT2 = WRP2_Data;
+
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+    }
+
+    if((status == FLASH_PRC_DONE) && (WRP3_Data != 0xFF))
+    {
+      UOPTB->WRPRT3 = WRP3_Data;
+
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+    }
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program process is completed, disable the UOBPRGM Bit */
+      FLASH->CTRL &= CTRL_UOBPRGM_Rst;
+    }
+  }
+
+  /* Return the write protection process Status */
+  return status;
+}
+
+/**
+  * @brief  Enables or disables the read out protection.
+  * @note   If the user has already programmed the other option bytes before calling
+  *   this function, he must re-program them since this function erases all option bytes.
+  * @note   This function can be used for all at32f4xx devices.
+  * @param  Newstate: new state of the ReadOut Protection.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ReadProtectConfig(FunctionalState NewState)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  status = FLASH_WaitForProcess(ERS_TIMEOUT);
+
+  if(status == FLASH_PRC_DONE)
+  {
+    /* Authorizes the small information block programming */
+    FLASH->OPTKEYR = FLASH_KEY1;
+    FLASH->OPTKEYR = FLASH_KEY2;
+    FLASH->CTRL |= CTRL_UOBERS_Set;
+    FLASH->CTRL |= CTRL_STRT_Set;
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForProcess(ERS_TIMEOUT);
+
+    if(status == FLASH_PRC_DONE)
+    {
+      /* if the erase process is completed, disable the UOBERS Bit */
+      FLASH->CTRL &= CTRL_UOBERS_Rst;
+      /* Enable the Option Bytes Programming process */
+      FLASH->CTRL |= CTRL_UOBPRGM_Set;
+
+      if(NewState != DISABLE)
+      {
+        UOPTB->RDPRT = 0x00;
+      }
+      else
+      {
+        UOPTB->RDPRT = RDPRT_Key;
+      }
+
+      /* Wait for last process to be completed */
+      status = FLASH_WaitForProcess(ERS_TIMEOUT);
+
+      if(status != FLASH_TIMEOUT)
+      {
+        /* if the program process is completed, disable the UOBPRGM Bit */
+        FLASH->CTRL &= CTRL_UOBPRGM_Rst;
+      }
+    }
+    else
+    {
+      if(status != FLASH_TIMEOUT)
+      {
+        /* Disable the UOBERS Bit */
+        FLASH->CTRL &= CTRL_UOBERS_Rst;
+      }
+    }
+  }
+
+  /* Return the protection process Status */
+  return status;
+}
+
+/**
+  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+  * @note   This function can be used for all at32f4xx devices.
+  * @param  UOB_IWDG: Selects the IWDG mode
+  *   This parameter can be one of the following values:
+  *     @arg UOB_SW_IWDG: Software IWDG selected
+  *     @arg UOB_HW_IWDG: Hardware IWDG selected
+  * @param  UOB_STOP: Reset event when entering STOP mode.
+  *   This parameter can be one of the following values:
+  *     @arg UOB_NO_RST_STP: No reset generated when entering in STOP
+  *     @arg UOB_RST_STP: Reset generated when entering in STOP
+  * @param  UOB_STDBY: Reset event when entering Standby mode.
+  *   This parameter can be one of the following values:
+  *     @arg UOB_NO_RST_STDBY: No reset generated when entering in STANDBY
+  *     @arg UOB_RST_STDBY: Reset generated when entering in STANDBY
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t UOB_IWDG, uint16_t UOB_STOP, uint16_t UOB_STDBY)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+
+  /* Check the parameters */
+  assert_param(IS_UOB_IWDG_CFG(UOB_IWDG));
+  assert_param(IS_UOB_STOP_CFG(UOB_STOP));
+  assert_param(IS_UOB_STDBY_CFG(UOB_STDBY));
+
+  /* Authorize the small information block programming */
+  FLASH->OPTKEYR = FLASH_KEY1;
+  FLASH->OPTKEYR = FLASH_KEY2;
+
+  /* Wait for last process to be completed */
+  status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+
+  if(status == FLASH_PRC_DONE)
+  {
+    /* Enable the Option Bytes Programming process */
+    FLASH->CTRL |= CTRL_UOBPRGM_Set;
+
+    UOPTB->USR = UOB_IWDG | (uint16_t)(UOB_STOP | (uint16_t)(UOB_STDBY | ((uint16_t)0xF8)));
+
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program process is completed, disable the UOBPRGM Bit */
+      FLASH->CTRL &= CTRL_UOBPRGM_Rst;
+    }
+  }
+
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+/**
+  * @brief  Configures to boot from Bank1 or Bank2.
+  * @note   This function can be used only for at32f403_XL density devices.
+  * @param  FLASH_BOOT: select the FLASH Bank to boot from.
+  *   This parameter can be one of the following values:
+  *     @arg FLASH_BOOT_FROM_BANK1: At startup, if boot pins are set in boot from user Flash
+  *        position and this parameter is selected the device will boot from Bank1(Default).
+  *     @arg FLASH_BOOT_FROM_BANK2: At startup, if boot pins are set in boot from user Flash
+  *        position and this parameter is selected the device will boot from Bank2 or Bank1,
+  *        depending on the activation of the bank. The active banks are checked in
+  *        the following order: Bank2, followed by Bank1.
+  *        The active bank is recognized by the value programmed at the base address
+  *        of the respective bank (corresponding to the initial stack pointer value
+  *        in the interrupt vector table).
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_BootOptConfig(uint16_t FLASH_BOOT)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+  assert_param(IS_FLASH_BOOT_CFG(FLASH_BOOT));
+  /* Authorize the small information block programming */
+  FLASH->OPTKEYR = FLASH_KEY1;
+  FLASH->OPTKEYR = FLASH_KEY2;
+
+  /* Wait for last process to be completed */
+  status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+
+  if(status == FLASH_PRC_DONE)
+  {
+    /* Enable the Option Bytes Programming process */
+    FLASH->CTRL |= CTRL_UOBPRGM_Set;
+
+    if(FLASH_BOOT == FLASH_BOOT_FROM_BANK1)
+    {
+      UOPTB->USR |= UOB_USR_BTOPT;
+    }
+    else
+    {
+      UOPTB->USR &= (uint16_t)(~(uint16_t)(UOB_USR_BTOPT));
+    }
+
+    /* Wait for last process to be completed */
+    status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program process is completed, disable the UOBPRGM Bit */
+      FLASH->CTRL &= CTRL_UOBPRGM_Rst;
+    }
+  }
+
+  /* Return the Option Byte program Status */
+  return status;
+}
+#endif
+
+/**
+  * @brief  Returns the FLASH User Option Bytes values.
+  * @note   This function can be used for all at32f4xx devices.
+  * @param  None
+  * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+  *         and RST_STDBY(Bit2).
+  */
+uint32_t FLASH_GetUserOptionByte(void)
+{
+  /* Return the User Option Byte */
+  return (uint32_t)(FLASH->UOB >> 2);
+}
+
+/**
+  * @brief  Returns the FLASH Write Protection Option Bytes Register value.
+  * @note   This function can be used for all at32f4xx devices.
+  * @param  None
+  * @retval The FLASH Write Protection  Option Bytes Register value
+  */
+uint32_t FLASH_GetWriteProtectStatus(void)
+{
+  /* Return the Flash write protection Register value */
+  return (uint32_t)(FLASH->WRPRT);
+}
+
+/**
+  * @brief  Checks whether the FLASH Read Out Protection Status is set or not.
+  * @note   This function can be used for all at32f4xx devices.
+  * @param  None
+  * @retval FLASH ReadOut Protection Status(SET or RESET)
+  */
+FlagStatus FLASH_GetReadProtectStatus(void)
+{
+  FlagStatus readoutstatus = RESET;
+
+  if ((FLASH->UOB & RDPRT_Mask) != (uint32_t)RESET)
+  {
+    readoutstatus = SET;
+  }
+  else
+  {
+    readoutstatus = RESET;
+  }
+
+  return readoutstatus;
+}
+
+/**
+  * @brief  Enables or disables the specified FLASH interrupts.
+  * @note   This function can be used for all at32f4xx devices.
+  *         - For AT32F4xx XL-Density devices, enables or disables the specified FLASH interrupts
+              for Bank1 and Bank2.
+  *         - For other devices it enables or disables the specified FLASH interrupts for Bank1.
+  * @param  FLASH_INT: specifies the FLASH interrupt sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg FLASH_INT_FLR: FLASH Error Interrupt
+  *     @arg FLASH_INT_PRCDN: FLASH end of process Interrupt
+  * @param  NewState: new state of the specified Flash interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState NewState)
+{
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+  /* Check the parameters */
+  assert_param(IS_FLASH_INT(FLASH_INT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if((FLASH_INT & FLASH_INT_BANK2) != 0x0)
+  {
+    if(NewState != DISABLE)
+    {
+      /* Enable the interrupt sources */
+      FLASH->CTRL2 |= (FLASH_INT & FLASH_INT_BANK2_MASK);
+    }
+    else
+    {
+      /* Disable the interrupt sources */
+      FLASH->CTRL2 &= ~(uint32_t)(FLASH_INT & FLASH_INT_BANK2_MASK);
+    }
+  }
+  else if((FLASH_INT & FLASH_INT_BANK3) != 0x0)
+  {
+    if(NewState != DISABLE)
+    {
+      /* Enable the interrupt sources */
+      FLASH->CTRL3 |= (FLASH_INT & FLASH_INT_BANK3_MASK);
+    }
+    else
+    {
+      /* Disable the interrupt sources */
+      FLASH->CTRL3 &= ~(uint32_t)(FLASH_INT & FLASH_INT_BANK3_MASK);
+    }
+  }
+  else
+  {
+    if(NewState != DISABLE)
+    {
+      /* Enable the interrupt sources */
+      FLASH->CTRL |= FLASH_INT;
+    }
+    else
+    {
+      /* Disable the interrupt sources */
+      FLASH->CTRL &= ~(uint32_t)FLASH_INT;
+    }
+  }
+
+#else
+  /* Check the parameters */
+  assert_param(IS_FLASH_INT(FLASH_INT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+#if !defined (AT32F415xx)
+  if((FLASH_INT & FLASH_INT_BANK3) != 0x0)
+  {
+    if(NewState != DISABLE)
+    {
+      /* Enable the interrupt sources */
+      FLASH->CTRL3 |= (FLASH_INT & FLASH_INT_BANK3_MASK);
+    }
+    else
+    {
+      /* Disable the interrupt sources */
+      FLASH->CTRL3 &= ~(uint32_t)(FLASH_INT & FLASH_INT_BANK3_MASK);
+    }
+  }
+  else
+  {
+    if(NewState != DISABLE)
+    {
+      /* Enable the interrupt sources */
+      FLASH->CTRL |= FLASH_INT;
+    }
+    else
+    {
+      /* Disable the interrupt sources */
+      FLASH->CTRL &= ~(uint32_t)FLASH_INT;
+    }
+  }
+#else
+  if(NewState != DISABLE)
+  {
+    /* Enable the interrupt sources */
+    FLASH->CTRL |= FLASH_INT;
+  }
+  else
+  {
+      /* Disable the interrupt sources */
+      FLASH->CTRL &= ~(uint32_t)FLASH_INT;
+  }
+#endif
+
+#endif
+}
+
+/**
+  * @brief  Checks whether the specified FLASH flag is set or not.
+  * @note   This function can be used for all at32f4xx devices.
+  *         - For AT32F4xx XL-Density devices, this function checks whether the specified
+  *           Bank1 or Bank2 flag is set or not.
+  *         - For other devices, it checks whether the specified Bank1 flag is
+  *           set or not.
+  * @param  FLASH_FLAG: specifies the FLASH flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg FLASH_FLAG_BSY: FLASH Busy flag
+  *     @arg FLASH_FLAG_PRGMFLR: FLASH Program error flag
+  *     @arg FLASH_FLAG_WRPRTFLR: FLASH Write protected error flag
+  *     @arg FLASH_FLAG_PRCDN: FLASH End of Operation flag
+  *     @arg FLASH_FLAG_UOBFLR:  FLASH Option Byte error flag
+  * @retval The new state of FLASH_FLAG (SET or RESET).
+  */
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+  /* Check the parameters */
+  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
+
+  if(FLASH_FLAG == FLASH_FLAG_UOBFLR)
+  {
+    if((FLASH->UOB & FLASH_FLAG_UOBFLR) != (uint32_t)RESET)
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+  else
+  {
+    if((FLASH_FLAG & FLASH_FLAG_BANK3) != 0x0)
+    {
+      if((FLASH->STS3 & FLASH_FLAG) != (uint32_t)RESET)
+      {
+        bitstatus = SET;
+      }
+      else
+      {
+        bitstatus = RESET;
+      }
+    }
+    else if((FLASH_FLAG & FLASH_FLAG_BANK2) != 0x0)
+    {
+      if((FLASH->STS2 & FLASH_FLAG) != (uint32_t)RESET)
+      {
+        bitstatus = SET;
+      }
+      else
+      {
+        bitstatus = RESET;
+      }
+    }
+    else
+    {
+      if((FLASH->STS & FLASH_FLAG) != (uint32_t)RESET)
+      {
+        bitstatus = SET;
+      }
+      else
+      {
+        bitstatus = RESET;
+      }
+    }
+  }
+
+#else
+  /* Check the parameters */
+  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
+
+  if(FLASH_FLAG == FLASH_FLAG_UOBFLR)
+  {
+    if((FLASH->UOB & FLASH_FLAG_UOBFLR) != (uint32_t)RESET)
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+  else
+  {
+#if !defined (AT32F415xx)
+    if((FLASH_FLAG & FLASH_FLAG_BANK3) != 0x0)
+    {
+      if((FLASH->STS3 & FLASH_FLAG) != (uint32_t)RESET)
+      {
+        bitstatus = SET;
+      }
+      else
+      {
+        bitstatus = RESET;
+      }
+    }
+    else
+    {
+      if((FLASH->STS & FLASH_FLAG) != (uint32_t)RESET)
+      {
+        bitstatus = SET;
+      }
+      else
+      {
+        bitstatus = RESET;
+      }
+    }
+#else
+   if((FLASH->STS & FLASH_FLAG) != (uint32_t)RESET)
+   {
+     bitstatus = SET;
+   }
+   else
+   {
+     bitstatus = RESET;
+   }    
+#endif
+  }
+
+#endif
+
+  /* Return the new state of FLASH_FLAG (SET or RESET) */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the FLASH's pending flags.
+  * @note   This function can be used for all at32f4xx devices.
+  *         - For AT32F4xx XL-Density devices, this function clears Bank1 or Bank2 pending flags
+  *         - For other devices, it clears Bank1 pending flags.
+  * @param  FLASH_FLAG: specifies the FLASH flags to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg FLASH_FLAG_PRGMFLR: FLASH Program error flag
+  *     @arg FLASH_FLAG_WRPRTFLR: FLASH Write protected error flag
+  *     @arg FLASH_FLAG_PRCDN: FLASH End of Operation flag
+  * @retval None
+  */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+  /* Check the parameters */
+  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
+
+  if((FLASH_FLAG & FLASH_FLAG_BANK3) != 0x0)
+  {
+    /* Clear the flags */
+    FLASH->STS3 = FLASH_FLAG;
+  }
+  else if ((FLASH_FLAG  & FLASH_FLAG_BANK2) != 0x0)
+  {
+    /* Clear the flags */
+    FLASH->STS2 = FLASH_FLAG;
+  }
+  else
+  {
+    /* Clear the flags */
+    FLASH->STS = FLASH_FLAG;
+  }
+
+#else
+  /* Check the parameters */
+  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
+
+#if !defined (AT32F415xx)
+  if((FLASH_FLAG & FLASH_FLAG_BANK3) != 0x0)
+  {
+    /* Clear the flags */
+    FLASH->STS3 = FLASH_FLAG;
+  }
+  else
+  {
+    /* Clear the flags */
+    FLASH->STS = FLASH_FLAG;
+  }
+#else
+  /* Clear the flags */
+  FLASH->STS = FLASH_FLAG;  
+#endif
+
+#endif
+}
+
+/**
+  * @brief  Returns the FLASH Status.
+  * @note   This function can be used for all at32f4xx devices, it is equivalent
+  *         to FLASH_GetBank1Status function.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_BSY, FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR or FLASH_PRC_DONE
+  */
+FLASH_Status FLASH_GetStatus(void)
+{
+  FLASH_Status flashstatus = FLASH_PRC_DONE;
+
+  if((FLASH->STS & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
+  {
+    flashstatus = FLASH_BSY;
+  }
+  else if((FLASH->STS & FLASH_FLAG_PRGMFLR) != 0)
+  {
+    flashstatus = FLASH_PGRM_FLR;
+  }
+  else if((FLASH->STS & FLASH_FLAG_WRPRTFLR) != 0 )
+  {
+    flashstatus = FLASH_WRPRT_FLR;
+  }
+  else
+  {
+    flashstatus = FLASH_PRC_DONE;
+  }
+
+  /* Return the Flash Status */
+  return flashstatus;
+}
+
+/**
+  * @brief  Returns the FLASH Bank1 Status.
+  * @note   This function can be used for all at32f4xx devices, it is equivalent
+  *         to FLASH_GetStatus function.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_BSY, FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR or FLASH_PRC_DONE
+  */
+FLASH_Status FLASH_GetBank1Status(void)
+{
+  FLASH_Status flashstatus = FLASH_PRC_DONE;
+
+  if((FLASH->STS & FLASH_FLAG_BNK1_BSY) == FLASH_FLAG_BSY)
+  {
+    flashstatus = FLASH_BSY;
+  }
+  else if((FLASH->STS & FLASH_FLAG_BNK1_PRGMFLR) != 0)
+  {
+    flashstatus = FLASH_PGRM_FLR;
+  }
+  else if((FLASH->STS & FLASH_FLAG_BNK1_WRPRTFLR) != 0 )
+  {
+    flashstatus = FLASH_WRPRT_FLR;
+  }
+  else
+  {
+    flashstatus = FLASH_PRC_DONE;
+  }
+
+  /* Return the Flash Status */
+  return flashstatus;
+}
+
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+/**
+  * @brief  Returns the FLASH Bank2 Status.
+  * @note   This function can be used for at32f4xx XL-Density devices.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_BSY, FLASH_PGRM_FLR,
+  *        FLASH_WRPRT_FLR or FLASH_PRC_DONE
+  */
+FLASH_Status FLASH_GetBank2Status(void)
+{
+  FLASH_Status flashstatus = FLASH_PRC_DONE;
+
+  if((FLASH->STS2 & (FLASH_FLAG_BNK2_BSY & FLASH_INT_BANK2_MASK)) == (FLASH_FLAG_BNK2_BSY & FLASH_INT_BANK2_MASK))
+  {
+    flashstatus = FLASH_BSY;
+  }
+  else if((FLASH->STS2 & (FLASH_FLAG_BNK2_PRGMFLR & FLASH_INT_BANK2_MASK)) != 0)
+  {
+    flashstatus = FLASH_PGRM_FLR;
+  }
+  else if((FLASH->STS2 & (FLASH_FLAG_BNK2_WRPRTFLR & ~FLASH_INT_BANK2)) != 0 )
+  {
+    flashstatus = FLASH_WRPRT_FLR;
+  }
+  else
+  {
+    flashstatus = FLASH_PRC_DONE;
+  }
+
+  /* Return the Flash Status */
+  return flashstatus;
+}
+#endif
+
+#if !defined (AT32F415xx)
+/**
+  * @brief  Returns the FLASH Bank3 Status.
+  * @note   This function can not be used for AT32F415 devices, it is equivalent
+  *         to FLASH_GetStatus function.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_BSY, FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR or FLASH_PRC_DONE
+  */
+FLASH_Status FLASH_GetBank3Status(void)
+{
+  FLASH_Status flashstatus = FLASH_PRC_DONE;
+
+
+  if((FLASH->STS3 & (FLASH_FLAG_BNK3_BSY & FLASH_INT_BANK3_MASK)) == (FLASH_FLAG_BNK3_BSY & FLASH_INT_BANK3_MASK))
+  {
+    flashstatus = FLASH_BSY;
+  }
+  else if((FLASH->STS3 & (FLASH_FLAG_BNK3_PRGMFLR & FLASH_INT_BANK3_MASK)) != 0)
+  {
+    flashstatus = FLASH_PGRM_FLR;
+  }
+  else if((FLASH->STS3 & (FLASH_FLAG_BNK3_WRPRTFLR & FLASH_INT_BANK3_MASK)) != 0 )
+  {
+    flashstatus = FLASH_WRPRT_FLR;
+  }
+  else
+  {
+    flashstatus = FLASH_PRC_DONE;
+  }
+
+  /* Return the Flash Status */
+  return flashstatus;
+}
+#endif
+
+/**
+  * @brief  Waits for a Flash process to complete or a TIMEOUT to occur.
+  * @note   This function can be used for all at32f4xx devices,
+  *         it is equivalent to FLASH_WaitForBank1Process.
+  *         - For AT32F4xx XL-Density devices this function waits for a Bank1 Flash process
+  *           to complete or a TIMEOUT to occur.
+  *         - For all other devices it waits for a Flash process to complete
+  *           or a TIMEOUT to occur.
+  * @param  Timeout: FLASH programming Timeout
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_WaitForProcess(uint32_t Timeout)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+
+  /* Check for the Flash Status */
+  status = FLASH_GetBank1Status();
+
+  /* Wait for a Flash process to complete or a TIMEOUT to occur */
+  while((status == FLASH_BSY) && (Timeout != 0x00))
+  {
+    status = FLASH_GetBank1Status();
+    Timeout--;
+  }
+
+  if(Timeout == 0x00 )
+  {
+    status = FLASH_TIMEOUT;
+  }
+
+  /* Return the process status */
+  return status;
+}
+
+/**
+  * @brief  Waits for a Flash process on Bank1 to complete or a TIMEOUT to occur.
+  * @note   This function can be used for all at32f4xx devices,
+  *         it is equivalent to FLASH_WaitForProcess.
+  * @param  Timeout: FLASH programming Timeout
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_WaitForBank1Process(uint32_t Timeout)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+
+  /* Check for the Flash Status */
+  status = FLASH_GetBank1Status();
+
+  /* Wait for a Flash process to complete or a TIMEOUT to occur */
+  while((status == FLASH_FLAG_BNK1_BSY) && (Timeout != 0x00))
+  {
+    status = FLASH_GetBank1Status();
+    Timeout--;
+  }
+
+  if(Timeout == 0x00 )
+  {
+    status = FLASH_TIMEOUT;
+  }
+
+  /* Return the process status */
+  return status;
+}
+
+#if defined(AT32F403Cx_XL) || defined(AT32F403Rx_XL) || defined(AT32F403Vx_XL) || defined(AT32F403Zx_XL) || \
+    defined(AT32F403ACGU7) || defined(AT32F403ACGT7) || defined(AT32F403ARGT7) || defined(AT32F403AVGT7) || \
+    defined(AT32F407RGT7)  || defined(AT32F407VGT7)
+/**
+  * @brief  Waits for a Flash process on Bank2 to complete or a TIMEOUT to occur.
+  * @note   This function can be used only for at32f4xx XL-Density devices.
+  * @param  Timeout: FLASH programming Timeout
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_WaitForBank2Process(uint32_t Timeout)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+
+  /* Check for the Flash Status */
+  status = FLASH_GetBank2Status();
+
+  /* Wait for a Flash process to complete or a TIMEOUT to occur */
+  while((status == (FLASH_FLAG_BNK2_BSY & FLASH_INT_BANK2_MASK)) && (Timeout != 0x00))
+  {
+    status = FLASH_GetBank2Status();
+    Timeout--;
+  }
+
+  if(Timeout == 0x00 )
+  {
+    status = FLASH_TIMEOUT;
+  }
+
+  /* Return the process status */
+  return status;
+}
+#endif
+
+#if !defined (AT32F415xx)
+/**
+  * @brief  Waits for a Flash process on Bank3 to complete or a TIMEOUT to occur.
+  * @note   This function can not be used for AT32F415 devices.
+  * @param  Timeout: FLASH programming Timeout
+  * @retval FLASH Status: The returned value can be: FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_WaitForBank3Process(uint32_t Timeout)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+
+  /* Check for the Flash Status */
+  status = FLASH_GetBank3Status();
+
+  /* Wait for a Flash process to complete or a TIMEOUT to occur */
+  while((status == (FLASH_FLAG_BNK3_BSY & FLASH_INT_BANK3_MASK)) && (Timeout != 0x00))
+  {
+    status = FLASH_GetBank3Status();
+    Timeout--;
+  }
+
+  if(Timeout == 0x00 )
+  {
+    status = FLASH_TIMEOUT;
+  }
+
+  /* Return the process status */
+  return status;
+}
+#endif
+
+#if !defined (AT32F415xx)
+/**
+  * @brief To set the end address of encrypted data in BANK3.
+  *        When the address is larger than this value, the writing data will be
+  *        directly written to BANK3 without encryption.
+  * @note   This function can not be used for AT32F415 devices.
+  * @param EndAddress: The end address of encrypted data in BANK3
+  * @retval: None
+  */
+void FLASH_Bank3EncEndAddrConfig(uint32_t EndAddress)
+{
+  assert_param(IS_IN_FLASH_BANK3_RANGE(EndAddress));
+  if((UOPTB->BANK3SCRKEY[0]==0xFFFFFFFF) && (UOPTB->BANK3SCRKEY[1]==0xFFFFFFFF) && \
+     (UOPTB->BANK3SCRKEY[2]==0xFFFFFFFF) && (UOPTB->BANK3SCRKEY[3]==0xFFFFFFFF))
+    return;
+  if((UOPTB->BANK3SCRKEY[0]==0xFF00FF00) && (UOPTB->BANK3SCRKEY[1]==0xFF00FF00) && \
+     (UOPTB->BANK3SCRKEY[2]==0xFF00FF00) && (UOPTB->BANK3SCRKEY[3]==0xFF00FF00))
+    return;  
+  if((UOPTB->BANK3SCRKEY[0]==0x00FF00FF) && (UOPTB->BANK3SCRKEY[1]==0x00FF00FF) && \
+     (UOPTB->BANK3SCRKEY[2]==0x00FF00FF) && (UOPTB->BANK3SCRKEY[3]==0x00FF00FF))
+    return;
+  FLASH->DA = EndAddress;
+}
+#endif
+
+/**
+  * @brief  Enable SLIB in Main Block
+  * @note   This function can be used for all AT32F4xx devices.
+  * @param  Psw: SLIB Password
+  *         StartPage:SLIB Start Page
+  *         DataPage: SLIB data Start Page
+  *         EndPage:  SLIB End Page
+  *         => SLIB Range = Page#N to Page#C
+  * @retval FLASH Status: The returned value can be: FLASH_BSY, FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_SlibMainEnable(uint32_t Psw, uint16_t StartPage, uint16_t DataStartPage, uint16_t EndPage)
+{
+  uint32_t SlibRange;
+  FLASH_Status Status = FLASH_PRC_DONE;
+
+  assert_param(IS_SLIB_DISABLE());
+  assert_param((Psw != 0xFFFFFFFF)&&(Psw != 0x00000000));
+  assert_param((StartPage >= 1)&&(StartPage <= 127)); 
+  assert_param((DataStartPage >= 1)&&(DataStartPage <= 127));
+  assert_param((EndPage >= 1)&&(EndPage <= 127));
+
+  /* Wait for last process to be completed */
+  Status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+  /*check param limits*/
+  if((StartPage>=DataStartPage) || ((DataStartPage>EndPage)&&(DataStartPage!=0x7FF)) || (StartPage>EndPage))
+    return Status;
+  
+  SlibRange = ((uint32_t)DataStartPage<<11&FLASH_SLIB_DATA_START_PAGE) | ((uint32_t)EndPage<<22&FLASH_SLIB_END_PAGE) | ((uint32_t)StartPage&FLASH_SLIB_START_PAGE);
+
+  if(Status == FLASH_PRC_DONE)
+  {
+      /* Unlock SLIB CFG register */
+      FLASH->SLIB_KEYR = SLIB_UNLOCK_KEY;
+
+      /* Configure SLIB, set PSW and RANGE */
+      FLASH->SLIB_SET_PSW = Psw;
+      Status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+
+      FLASH->SLIB_SET_RANGE = SlibRange;
+      Status = FLASH_WaitForProcess(PRGM_TIMEOUT);
+  }
+  return Status;
+}
+
+/**
+  * @brief  Disable SLIB when SLIB enabled
+  * @note   This function can be used for all AT32F4xx devices.
+  * @param  Psw: SLIB Password
+  * @retval SUCCESS or ERROR
+  */
+uint32_t FLASH_SlibDisable(uint32_t Psw)
+{
+  FLASH_Status Status = FLASH_PRC_DONE;
+
+  assert_param(!IS_SLIB_DISABLE());
+
+  /* Write Password to disable SLIB */
+  FLASH->SLIB_PSW = Psw;
+  Status = FLASH_WaitForProcess(ERS_TIMEOUT);
+  
+  if(Status == FLASH_PRC_DONE)
+  {
+    if(FLASH->SLIB_PSW_STS & FLASH_SLIB_PSWSTS_PSW_OK)
+      return SUCCESS;
+    else
+      return ERROR;
+  }
+  
+  return ERROR;
+}
+
+#if !defined (AT32F415xx)
+/**
+ * @brief  Get the value of current remaining SLIB CFG count (range: 256~0)
+ * @note   This function can not be used for AT32F415 devices.
+ * @param  None 
+ * @retval uint32_t
+ */
+uint32_t FLASH_GetSlibCurCnt(void)
+{
+  return ((FLASH->SLIB_PSW_STS & FLASH_SLIB_CNT) >> 16);
+}
+#endif
+
+/**
+  * @brief  Get the SLIB state
+  * @note   This function can be used for all AT32F4xx devices.
+  * @param  None
+  * @retval ENABLE or DISABLE
+  */
+uint8_t FLASH_GetSlibState(void)
+{
+  if(FLASH->SLIB_CDR0&FLASH_SLIB_CDR0_SLIB_EN)
+    return ENABLE;
+  else
+    return DISABLE;
+}
+
+/**
+ * @brief  Get the start page of SLIB
+ * @note   This function can be used for all AT32F4xx devices
+ * @param  None
+ * @retval uint16_t
+ */
+uint16_t FLASH_GetSlibStartPage(void)
+{
+  return (uint16_t)((FLASH->SLIB_CDR1&FLASH_SLIB_SET_START_PAGE)>>0);
+}
+
+/**
+ * @brief  Get the data start page of SLIB
+ * @note   This function can be used for all AT32F4xx devices
+ * @param  None
+ * @retval uint16_t
+ */
+uint16_t FLASH_GetSlibDataStartPage(void)
+{
+  return (uint16_t)((FLASH->SLIB_CDR1&FLASH_SLIB_SET_DATA_START_PAGE)>>11);
+}
+
+/**
+ * @brief  Get the end page of SLIB
+ * @note   This function can be used for all AT32F4xx devices
+ * @param  None
+ * @retval uint16_t
+ */
+uint16_t FLASH_GetSlibEndPage(void)
+{
+  return (uint16_t)((FLASH->SLIB_CDR1&FLASH_SLIB_SET_END_PAGE)>>22);
+}
+
+#if defined (AT32F415xx)
+/**
+  * @brief  Configure System Memory as AP mode
+  * @note   This function can be used only for AT32F415 device.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_BSY, FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_SYS_AP(void)
+{
+  volatile FLASH_Status tStatus = FLASH_PRC_DONE;
+
+  assert_param(IS_SLIB_DISABLE());
+  assert_param(IS_RDP_DISABLE());
+
+  if((FLASH->SLIB_CDR0 & FLASH_SLIB_CDR0_BOOT_DIS) == 0)
+  {
+    FLASH->SLIB_KEYR = SLIB_UNLOCK_KEY;
+    while((FLASH->SLIB_PSW_STS & FLASH_SLIB_UNLOCK) == 0);
+    FLASH->SYS_BOOT_DIS_SET = 0;
+    tStatus = FLASH_WaitForProcess(PRGM_TIMEOUT);
+  }
+  return tStatus;
+}
+#endif /* AT32F415xx */
+
+#if defined (AT32F415xx)
+/**
+  * @brief  Enable SLIB in System Memory
+  * @note   This function can be used only for AT32F415 device.
+  * @param  Psw: SLIB Password
+  *         data_start_page: SLIB data Start Page
+  * @retval FLASH Status: The returned value can be: FLASH_BSY, FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_SlibSysEnable(uint32_t Psw,uint8_t data_start_page)
+{
+  volatile FLASH_Status tStatus = FLASH_PRC_DONE;
+  assert_param(IS_SLIB_DISABLE());
+
+  /* Wait for last process to be completed */
+  tStatus = FLASH_WaitForProcess(PRGM_TIMEOUT);
+  /* Unlock SLIB CFG register */
+  FLASH->SLIB_KEYR = SLIB_UNLOCK_KEY;
+  while((FLASH->SLIB_PSW_STS & FLASH_SLIB_UNLOCK) == 0);
+  
+  /* make sure System Memory as AP mode */
+  if(FLASH->SLIB_CDR0 & FLASH_SLIB_CDR0_BOOT_DIS)
+  {
+    FLASH->SYS_SLIB_SET = (data_start_page<<16)+0x5AA5;
+    tStatus = FLASH_WaitForProcess(PRGM_TIMEOUT);
+    FLASH->SLIB_SET_PSW = Psw;
+    tStatus = FLASH_WaitForProcess(PRGM_TIMEOUT);
+  }
+
+  return tStatus;
+}
+#endif /* AT32F415xx */
+
+#if defined (AT32F415xx)
+/**
+  * @brief  Check whether the option byte protection is set or not.
+  * @note   This function can be used only for AT32F415 device.
+  * @param  None
+  * @retval Flash option byte protection status(SET or RESET)
+  */
+FlagStatus FLASH_GetOptionByteProtectStatus(void)
+{
+  FlagStatus status = RESET;
+  
+  if ((FLASH->UOB & FLASH_UOB_RDPRTEN) != (uint32_t)RESET)
+  {
+    if ((FLASH->UOB & FLASH_UOB_OPTION_BYTE_PRT_EN) != (uint32_t)RESET)
+    {
+      status = SET;
+    }
+  }
+  
+  return status;
+}
+#endif /* AT32F415xx */
+
+#if defined (AT32F415xx)
+/**
+  * @brief  Configure the option byte protection.
+  * @note   If the user has already programmed the other option bytes before calling
+  *         this function, he must re-program them since this function erases all option bytes.
+  * @note   This function can be used only for AT32F415 device.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_BSY, FLASH_PGRM_FLR,
+  *         FLASH_WRPRT_FLR, FLASH_PRC_DONE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_RDPandOptionByteProtectEnable(void)
+{
+  FLASH_Status status = FLASH_PRC_DONE;
+  /* Check the parameters */
+
+  status = FLASH_WaitForProcess(ERS_TIMEOUT);
+    
+  if(status == FLASH_PRC_DONE)
+  {
+    /* Unlock OTP2 */
+    FLASH->OPTKEYR = FLASH_KEY1;
+    FLASH->OPTKEYR = FLASH_KEY2;
+
+    /* Erase OTP2 */
+    FLASH->CTRL |= CTRL_UOBERS_Set;
+    FLASH->CTRL |= CTRL_STRT_Set;
+    status = FLASH_WaitForProcess(ERS_TIMEOUT);
+
+    if(status == FLASH_PRC_DONE)
+    {
+      FLASH->CTRL &= CTRL_UOBERS_Rst;
+
+      /* Program OTP2 */
+      FLASH->CTRL |= CTRL_UOBPRGM_Set;      
+      UOPTB->RDPRT = OPTION_BYTE_PRT_Key;
+      status = FLASH_WaitForProcess(ERS_TIMEOUT);
+
+      if(status != FLASH_TIMEOUT)
+      {
+        FLASH->CTRL &= CTRL_UOBPRGM_Rst;
+      }
+    }
+    else
+    {
+      if(status != FLASH_TIMEOUT)
+      {
+        FLASH->CTRL &= CTRL_UOBERS_Rst;
+      }
+    }
+
+    /* Disable OTP write enable bit */
+    FLASH->CTRL &= CTRL_UOBWE_Rst;
+  }
+  return status;
+}
+#endif /* AT32F415xx */
+
+#if defined (AT32F415xx)
+/**
+  * @brief  Disable the option byte protection.
+  * @note   This function can be used only for AT32F415 device.
+  * @param  None
+  * @retval None
+  */
+void FLASH_OptionByteProtectDisable(void)
+{
+  volatile FLASH_Status tStatus = FLASH_PRC_DONE;
+
+  if (FLASH_GetOptionByteProtectStatus() != SET) 
+  {
+    /* option byte protection is not set */
+    return;
+  }
+  FLASH->CTRL |= FLASH_CTRL_OPTION_BYTE_PRT_DIS_TRIG;
+  tStatus = FLASH_WaitForProcess(ERS_TIMEOUT);
+}
+#endif /* AT32F415xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_gpio.c

@@ -0,0 +1,1166 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_gpio.c
+ * Description  : at32f4xx GPIO source file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_gpio.h"
+#include "at32f4xx_rcc.h"
+#include <math.h>
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup GPIO
+  * @brief GPIO driver modules
+  * @{
+  */
+
+/** @defgroup GPIO_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Defines
+  * @{
+  */
+
+/* ------------ RCC registers bit address in the alias region ----------------*/
+#define AFIO_OFFSET                 (AFIO_BASE - PERIPH_BASE)
+
+/* --- EVENTCR Register -----*/
+
+/* Alias word address of EVOE bit */
+#define EVCR_OFFSET                 (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber              ((uint8_t)0x07)
+#define EVCR_EVOE_BB                (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
+
+
+/* ---  MAPR Register ---*/
+/* Alias word address of MII_RMII_SEL bit */
+#define MAP_OFFSET                 (AFIO_OFFSET + 0x04)
+#define MII_RMII_SEL_BitNumber      ((u8)0x17)
+#define MAPR_MII_RMII_SEL_BB        (PERIPH_BB_BASE + (MAP_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
+
+
+#define EVCR_PORTPINCONFIG_MASK     ((uint16_t)0xFF80)
+#define LSB_MASK                    ((uint16_t)0xFFFF)
+#define DBGAFR_POSITION_MASK        ((uint32_t)0x000F0000)
+#define DBGAFR_SWJCONF_MASK          ((uint32_t)0xF0FFFFFF)
+#define DBGAFR_LOCATION_MASK        ((uint32_t)0x00200000)
+#define DBGAFR_NUMBITS_MASK         ((uint32_t)0x00100000)
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @retval None
+  */
+void GPIO_Reset(GPIO_Type* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  if (GPIOx == GPIOA)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_GPIOA, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_GPIOA, DISABLE);
+  }
+  else if (GPIOx == GPIOB)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_GPIOB, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_GPIOB, DISABLE);
+  }
+  else if (GPIOx == GPIOC)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_GPIOC, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_GPIOC, DISABLE);
+  }
+  else if (GPIOx == GPIOD)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_GPIOD, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_GPIOD, DISABLE);
+  }
+#if defined (AT32F403xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+  else if (GPIOx == GPIOE)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_GPIOE, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_GPIOE, DISABLE);
+  }
+#endif
+#if !defined (AT32F403Axx) && !defined (AT32F407xx)
+  else if (GPIOx == GPIOF)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_GPIOF, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_GPIOF, DISABLE);
+  }
+#endif
+#ifdef AT32F403xx
+  else if (GPIOx == GPIOG)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_GPIOG, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_GPIOG, DISABLE);
+  }
+#endif
+}
+
+/**
+  * @brief  Deinitializes the Alternate Functions (remap, event control
+  *   and EXTI configuration) registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void GPIO_AFIOReset(void)
+{
+  RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_AFIO, ENABLE);
+  RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_AFIO, DISABLE);
+}
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified
+  *         parameters in the GPIO_InitStruct.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitType structure that
+  *         contains the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void GPIO_Init(GPIO_Type* GPIOx, GPIO_InitType* GPIO_InitStruct)
+{
+  uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
+  uint32_t tmpreg = 0x00, pinmask = 0x00;
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_MDE(GPIO_InitStruct->GPIO_Mode));
+  assert_param(IS_GPIO_PINS(GPIO_InitStruct->GPIO_Pins));
+
+  /*---------------------------- GPIO Mode Configuration -----------------------*/
+  currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+
+  if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
+  {
+    /* Check the parameters */
+    assert_param(IS_GPIO_MAXSPEED(GPIO_InitStruct->GPIO_MaxSpeed));
+    /* Output mode */
+    currentmode |= (uint32_t)GPIO_InitStruct->GPIO_MaxSpeed;
+  }
+
+  /*---------------------------- GPIO CRL Configuration ------------------------*/
+  /* Configure the eight low port pins */
+  if (((uint32_t)GPIO_InitStruct->GPIO_Pins & ((uint32_t)0x00FF)) != 0x00)
+  {
+    tmpreg = GPIOx->CTRLL;
+
+    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+    {
+      pos = ((uint32_t)0x01) << pinpos;
+      /* Get the port pins position */
+      currentpin = (GPIO_InitStruct->GPIO_Pins) & pos;
+
+      if (currentpin == pos)
+      {
+        pos = pinpos << 2;
+        /* Clear the corresponding low control register bits */
+        pinmask = ((uint32_t)0x0F) << pos;
+        tmpreg &= ~pinmask;
+        /* Write the mode configuration in the corresponding bits */
+        tmpreg |= (currentmode << pos);
+
+        /* Reset the corresponding ODR bit */
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IN_PD)
+        {
+          GPIOx->BRE = (((uint32_t)0x01) << pinpos);
+        }
+        else
+        {
+          /* Set the corresponding ODR bit */
+          if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IN_PU)
+          {
+            GPIOx->BSRE = (((uint32_t)0x01) << pinpos);
+          }
+        }
+      }
+    }
+
+    GPIOx->CTRLL = tmpreg;
+  }
+
+  /*---------------------------- GPIO CRH Configuration ------------------------*/
+  /* Configure the eight high port pins */
+  if (GPIO_InitStruct->GPIO_Pins > 0x00FF)
+  {
+    tmpreg = GPIOx->CTRLH;
+
+    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+    {
+      pos = (((uint32_t)0x01) << (pinpos + 0x08));
+      /* Get the port pins position */
+      currentpin = ((GPIO_InitStruct->GPIO_Pins) & pos);
+
+      if (currentpin == pos)
+      {
+        pos = pinpos << 2;
+        /* Clear the corresponding high control register bits */
+        pinmask = ((uint32_t)0x0F) << pos;
+        tmpreg &= ~pinmask;
+        /* Write the mode configuration in the corresponding bits */
+        tmpreg |= (currentmode << pos);
+
+        /* Reset the corresponding ODR bit */
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IN_PD)
+        {
+          GPIOx->BRE = (((uint32_t)0x01) << (pinpos + 0x08));
+        }
+
+        /* Set the corresponding ODR bit */
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IN_PU)
+        {
+          GPIOx->BSRE = (((uint32_t)0x01) << (pinpos + 0x08));
+        }
+      }
+    }
+
+    GPIOx->CTRLH = tmpreg;
+  }
+}
+
+/**
+  * @brief  Fills each GPIO_InitStruct member with its default value.
+  * @param  GPIO_InitStruct : pointer to a GPIO_InitType structure which will
+  *         be initialized.
+  * @retval None
+  */
+void GPIO_StructInit(GPIO_InitType* GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->GPIO_Pins  = GPIO_Pins_All;
+  GPIO_InitStruct->GPIO_MaxSpeed = GPIO_MaxSpeed_2MHz;
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
+}
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin:  specifies the port bit to read.
+  *   This parameter can be GPIO_Pin_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+uint8_t GPIO_ReadInputDataBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PINS(GPIO_Pin));
+
+  if ((GPIOx->IPTDT & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO input data port.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @retval GPIO input data port value.
+  */
+uint16_t GPIO_ReadInputData(GPIO_Type* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  return ((uint16_t)GPIOx->IPTDT);
+}
+
+/**
+  * @brief  Reads the specified output data port bit.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin:  specifies the port bit to read.
+  *   This parameter can be GPIO_Pin_x where x can be (0..15).
+  * @retval The output port pin value.
+  */
+uint8_t GPIO_ReadOutputDataBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PINS(GPIO_Pin));
+
+  if ((GPIOx->OPTDT & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO output data port.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @retval GPIO output data port value.
+  */
+uint16_t GPIO_ReadOutputData(GPIO_Type* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  return ((uint16_t)GPIOx->OPTDT);
+}
+
+/**
+  * @brief  Sets the selected data port bits.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_SetBits(GPIO_Type* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PINS(GPIO_Pin));
+
+  GPIOx->BSRE = GPIO_Pin;
+}
+
+/**
+  * @brief  Clears the selected data port bits.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_ResetBits(GPIO_Type* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PINS(GPIO_Pin));
+
+  GPIOx->BRE = GPIO_Pin;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *   This parameter can be one of GPIO_Pin_x where x can be (0..15).
+  * @param  BitVal: specifies the value to be written to the selected bit.
+  *   This parameter can be one of the BitState enum values:
+  *     @arg Bit_RESET: to clear the port pin
+  *     @arg Bit_SET: to set the port pin
+  * @retval None
+  */
+void GPIO_WriteBit(GPIO_Type* GPIOx, uint16_t GPIO_Pin, BitState BitVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PINS(GPIO_Pin));
+  assert_param(IS_GPIO_BIT_STATE(BitVal));
+
+  if (BitVal != Bit_RESET)
+  {
+    GPIOx->BSRE = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BRE = GPIO_Pin;
+  }
+}
+
+/**
+  * @brief  Writes data to the specified GPIO data port.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  PortVal: specifies the value to be written to the port output data register.
+  * @retval None
+  */
+void GPIO_Write(GPIO_Type* GPIOx, uint16_t PortVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  GPIOx->OPTDT = PortVal;
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_PinsLockConfig(GPIO_Type* GPIOx, uint16_t GPIO_Pin)
+{
+  uint32_t tmp = 0x00010000;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PINS(GPIO_Pin));
+
+  tmp |= GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LOCK = tmp;
+  /* Reset LCKK bit */
+  GPIOx->LOCK =  GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LOCK = tmp;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LOCK;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LOCK;
+}
+
+/**
+  * @brief  Selects the GPIO pin used as Event output.
+  * @param  GPIO_PortSource: selects the GPIO port to be used as source
+  *   for Event output.
+  *   This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
+  * @param  GPIO_PinSource: specifies the pin for the Event output.
+  *   This parameter can be GPIO_PinSourcex where x can be (0..15).
+  * @retval None
+  */
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+  uint32_t tmpreg = 0x00;
+  /* Check the parameters */
+  assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
+  assert_param(IS_GPIO_PINS_SOURCE(GPIO_PinSource));
+
+  tmpreg = AFIO->EVCTRL;
+  /* Clear the PORT[6:4] and PIN[3:0] bits */
+  tmpreg &= EVCR_PORTPINCONFIG_MASK;
+  tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
+  tmpreg |= GPIO_PinSource;
+  AFIO->EVCTRL = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Event Output.
+  * @param  NewState: new state of the Event output.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void GPIO_EventOutputCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Changes the mapping of the specified pin.
+  * @param  GPIO_Remap: selects the pin to remap.
+  *   This parameter can be one of the following values:
+  *     @arg GPIO_Remap01_SPI1           : SPI1 Alternate Function mapping01
+  *     @arg GPIO_Remap10_SPI1           : SPI1 Alternate Function mapping10
+  *     @arg GPIO_Remap_I2C1             : I2C1 Alternate Function mapping
+  *     @arg GPIO_Remap_USART1           : USART1 Alternate Function mapping
+  *     @arg GPIO_Remap_USART2           : USART2 Alternate Function mapping
+  *     @arg GPIO_PartialRemap_USART3    : USART3 Partial Alternate Function mapping
+  *     @arg GPIO_FullRemap_USART3       : USART3 Full Alternate Function mapping
+  *     @arg GPIO_PartialRemap_TMR1      : TMR1 Partial Alternate Function mapping
+  *     @arg GPIO_FullRemap_TMR1         : TMR1 Full Alternate Function mapping
+  *     @arg GPIO_PartialRemap1_TMR2     : TMR2 Partial1 Alternate Function mapping
+  *     @arg GPIO_PartialRemap2_TMR2     : TMR2 Partial2 Alternate Function mapping
+  *     @arg GPIO_FullRemap_TMR2         : TMR2 Full Alternate Function mapping
+  *     @arg GPIO_PartialRemap_TMR3      : TMR3 Partial Alternate Function mapping
+  *     @arg GPIO_FullRemap_TMR3         : TMR3 Full Alternate Function mapping
+  *     @arg GPIO_Remap_TMR4             : TMR4 Alternate Function mapping
+  *     @arg GPIO_Remap1_CAN1            : CAN1 Alternate Function mapping
+  *     @arg GPIO_Remap2_CAN1            : CAN1 Alternate Function mapping
+  *     @arg GPIO_Remap_PD01            : PD01 Alternate Function mapping
+  *     @arg GPIO_Remap_TMR5CH4_LSI      : LSI connected to TMR5 Channel4 input capture for calibration
+  *     @arg GPIO_Remap_ADC1_EXTRGINJ    : ADC1 External Trigger Injected Conversion remapping
+  *     @arg GPIO_Remap_ADC1_EXTRGREG    : ADC1 External Trigger Regular Conversion remapping
+  *     @arg GPIO_Remap_ADC2_EXTRGINJ    : ADC2 External Trigger Injected Conversion remapping
+  *     @arg GPIO_Remap_ADC2_EXTRGREG    : ADC2 External Trigger Regular Conversion remapping
+  *     @arg GPIO_Remap_SWJ_NoJNTRST     : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
+  *     @arg GPIO_Remap_SWJ_JTAGDisable  : JTAG-DP Disabled and SW-DP Enabled
+  *     @arg GPIO_Remap_SWJ_AllDisable   : Full SWJ Disabled (JTAG-DP + SW-DP)
+  *     @arg GPIO_Remap_TMR15            : TMR15 Alternate Function mapping
+  *     @arg GPIO_Remap_TMR9             : TMR9 Alternate Function mapping
+  *     @arg GPIO_Remap_TMR10            : TMR10 Alternate Function mapping
+  *     @arg GPIO_Remap_TMR11            : TMR11 Alternate Function mapping
+  *     @arg GPIO_Remap_TMR13            : TMR13 Alternate Function mapping
+  *     @arg GPIO_Remap_TMR14            : TMR14 Alternate Function mapping
+  *     @arg GPIO_Remap_XMC_NADV         : XMC_NADV Alternate Function mapping
+  *     @arg GPIO_Remap_SPI4             : SPI4 Alternate Function mapping
+  *     @arg GPIO_Remap_I2C3             : I2C3 Alternate Function mapping
+  *     @arg GPIO_Remap01_SDIO2          : SDIO2 Alternate Function mapping 01:CK/CMD Remaped None,D0~D3 Remaped to PA4~PA7.
+  *     @arg GPIO_Remap10_SDIO2          : SDIO2 Alternate Function mapping 10:CK/CMD Remaped to PA2/PA3,D0~D3 Remaped None.
+  *     @arg GPIO_Remap11_SDIO2          : SDIO2 Alternate Function mapping 11:CK/CMD Remaped to PA2/PA3,D0~D3 Remaped to PA4~PA7.
+  *     @arg GPIO_Remap_EXT_FLASH        : EXT_FLASH Alternate Function mapping
+  
+  *     @arg AFIO_MAP3_TMR9_0010         : TMR9 Alternate Function mapping:
+  *     @arg AFIO_MAP3_TMR10_0010        : TMR10 Alternate Function mapping:
+  *     @arg AFIO_MAP3_TMR11_0010        : TMR11 Alternate Function mapping:
+  *     @arg AFIO_MAP4_TMR1_0001         : TMR1 Alternate Function mapping 
+  *     @arg AFIO_MAP4_TMR2_0001         : TMR2 Alternate Function mapping 0001
+  *     @arg AFIO_MAP4_TMR2_0010         : TMR2 Alternate Function mapping 0010
+  *     @arg AFIO_MAP4_TMR2_0011         : TMR2 Alternate Function mapping 0011
+  *     @arg AFIO_MAP4_TMR3_0010         : TMR3 Alternate Function mapping 0010
+  *     @arg AFIO_MAP4_TMR3_0011         : TMR3 Alternate Function mapping 0011
+  *     @arg AFIO_MAP4_TMR5_0001         : TMR5 Alternate Function mapping 0001: CH1/CH2
+  *     @arg AFIO_MAP4_TMR5_1000         : TMR5 Alternate Function mapping 1000: CH4 
+  *     @arg AFIO_MAP4_TMR5_1001         : TMR5 Alternate Function mapping 1001: CH1/CH2+CH4 
+  *     @arg AFIO_MAP5_I2C1_0001         : I2C1 Alternate Function mapping 0001
+  *     @arg AFIO_MAP5_I2C1_0011         : I2C1 Alternate Function mapping 0011
+  *     @arg AFIO_MAP5_I2C2_0001         : I2C2 Alternate Function mapping 0001
+  *     @arg AFIO_MAP5_I2C2_0010         : I2C2 Alternate Function mapping 0010
+  *     @arg AFIO_MAP5_I2C2_0011         : I2C2 Alternate Function mapping 0011
+  *     @arg AFIO_MAP5_SPI1_0001         : SPI1 Alternate Function mapping 
+  *     @arg AFIO_MAP5_SPI2_0001         : SPI2 Alternate Function mapping 
+  *     @arg AFIO_MAP6_CAN1_0010         : CAN1 Alternate Function mapping 
+  *     @arg AFIO_MAP6_CAN2_0001         : CAN2 Alternate Function mapping 
+  *     @arg AFIO_MAP6_SDIO_0100         : SDIO Alternate Function mapping 100 
+  *     @arg AFIO_MAP6_SDIO_0101         : SDIO Alternate Function mapping 101 
+  *     @arg AFIO_MAP6_SDIO_0110         : SDIO Alternate Function mapping 110 
+  *     @arg AFIO_MAP6_SDIO_0111         : SDIO Alternate Function mapping 111 
+  *     @arg AFIO_MAP6_USART1_0001       : USART1 Alternate Function mapping 
+  *     @arg AFIO_MAP6_USART3_0001       : USART3 Partial Alternate Function mapping 
+  *     @arg AFIO_MAP6_UART4_0001        : UART4 Alternate Function mapping 
+  *     @arg AFIO_MAP7_SPIF_1000         : EXT_FLASH Alternate Function mapping  
+  *     @arg AFIO_MAP7_SPIF_1001         : EXT_FLASH Alternate Function enable  
+  *     @arg AFIO_MAP7_ADC1_0001         : ADC1 External Trigger Injected Conversion remapping 
+  *     @arg AFIO_MAP7_ADC1_0010         : ADC1 External Trigger Regular Conversion remapping 
+  *     @arg AFIO_MAP7_ADC1_0011         : ADC1 External Trigger Regular & Injected Conversion remapping 
+  *     @arg AFIO_MAP7_ADC2_0001         : ADC2 External Trigger Injected Conversion remapping 
+  *     @arg AFIO_MAP7_ADC2_0010         : ADC2 External Trigger Regular Conversion remapping 
+  *     @arg AFIO_MAP7_ADC2_0011         : ADC2 External Trigger Regular & Injected Conversion remapping 
+  *     @arg AFIO_MAP7_SWJTAG_0001       : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST 
+  *     @arg AFIO_MAP7_SWJTAG_0010       : JTAG-DP Disabled and SW-DP Enabled 
+  *     @arg AFIO_MAP7_SWJTAG_0100       : Full SWJ Disabled (JTAG-DP + SW-DP) 
+  *     @arg AFIO_MAP7_PD01_0001         : PD01 Alternate Function mapping 
+  * @param  NewState: new state of the port pin remapping.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void GPIO_PinsRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
+{
+#ifndef AT32F403xx
+  if(IS_GREMAP(GPIO_Remap))
+  {
+    uint32_t reg_ost = 0x00, bit_ost = 0x00, Remap_Addr, Remap_val;
+    volatile uint32_t *AFIO_MAPx;
+
+    /* Calculate the remap register value by parameter GPIO_Remap */
+    Remap_Addr = GPIO_Remap & 0x7FFFFFFF;
+    reg_ost = Remap_Addr >> 7;
+    Remap_Addr &= 0x7f;
+    bit_ost = Remap_Addr >> 4;
+    Remap_Addr &= 0x0f;
+    
+#ifdef AT32F415xx
+    if(reg_ost != AFIO_MAP8)
+      Remap_val = Remap_Addr << (bit_ost * 4);
+    else
+      Remap_val = Remap_Addr << (bit_ost/2 * 4);
+#else
+    Remap_val = Remap_Addr << (bit_ost * 4);
+#endif
+    
+    switch(reg_ost)
+    {
+      case AFIO_MAP3:
+        AFIO_MAPx = &(AFIO->MAP3);
+        break;
+
+      case AFIO_MAP4:
+        AFIO_MAPx = &(AFIO->MAP4);
+        break;
+
+      case AFIO_MAP5:
+        AFIO_MAPx = &(AFIO->MAP5);
+        break;
+
+      case AFIO_MAP6:
+        AFIO_MAPx = &(AFIO->MAP6);
+        break;
+
+      case AFIO_MAP7:
+        AFIO_MAPx = &(AFIO->MAP7);
+        break;
+      
+#ifndef AT32F413xx
+      case AFIO_MAP8:
+        AFIO_MAPx = &(AFIO->MAP8);
+        break;
+#endif
+      
+      default:
+        break;
+    }
+
+    if(bit_ost == BITS0)
+    {
+#ifdef AT32F415xx
+      if(reg_ost == AFIO_MAP8)
+      {
+        *AFIO_MAPx &= 0xFFFFFFFC;
+      }else
+      {
+        *AFIO_MAPx &= OFFSET_MASK0;
+      }
+#else
+      *AFIO_MAPx &= OFFSET_MASK0;
+#endif
+    }
+    else if(bit_ost == BITS1)
+    {
+      #ifdef AT32F415xx
+      if(reg_ost == AFIO_MAP8)
+      {
+        *AFIO_MAPx &= 0xFFFFFFF3;
+      }else
+      {
+        *AFIO_MAPx &= OFFSET_MASK1;
+      }
+      #elif defined (AT32F403Axx) || defined (AT32F407xx)
+      if(reg_ost == AFIO_MAP4)
+      {
+        if(Remap_Addr > 4)
+        {
+          *AFIO_MAPx &= 0xFFFFFF3F;
+        }else
+        {
+          *AFIO_MAPx &= 0xFFFFFFCF;
+        }
+      }else
+      {
+        *AFIO_MAPx &= OFFSET_MASK1;
+      }
+      #else
+      *AFIO_MAPx &= OFFSET_MASK1;
+      #endif
+    }
+    else if(bit_ost == BITS2)
+    {
+#ifdef AT32F415xx
+      if(reg_ost == AFIO_MAP8)
+      {
+        *AFIO_MAPx &= 0xFFFFFFCF;
+      }else
+      {
+        *AFIO_MAPx &= OFFSET_MASK2;
+      }
+#else
+      *AFIO_MAPx &= OFFSET_MASK2;
+#endif
+    }
+    else if(bit_ost == BITS3)
+    {
+#ifdef AT32F415xx
+      if(reg_ost == AFIO_MAP8)
+      {
+        *AFIO_MAPx &= 0xFFFFFF3F;
+      }else
+      {
+        *AFIO_MAPx &= OFFSET_MASK3;
+      }
+#else
+      *AFIO_MAPx &= OFFSET_MASK3;
+#endif
+    }
+    else if(bit_ost == BITS4)
+    {
+      *AFIO_MAPx &= OFFSET_MASK4;
+    }
+    else if(bit_ost == BITS5)
+    {
+      *AFIO_MAPx &= OFFSET_MASK5;
+    }
+    else if(bit_ost == BITS6)
+    {
+      *AFIO_MAPx &= OFFSET_MASK6;
+    }
+    else if(bit_ost == BITS7)
+    {
+      *AFIO_MAPx &= OFFSET_MASK7;
+    }
+
+    if(NewState == ENABLE)
+    {
+      *AFIO_MAPx |= Remap_val;
+    }
+
+  }
+  else
+#endif
+  {
+    /* Check the parameters */
+    assert_param(IS_GPIO_REMAP(GPIO_Remap));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    switch(GPIO_Remap)
+    {
+    case GPIO_Remap_I2C1:
+    case GPIO_Remap_USART1:
+    case GPIO_Remap_PD01:
+    case GPIO_Remap_TMR5CH4_LSI:
+    case GPIO_Remap_ADC1_EXTRGINJ:
+    case GPIO_Remap_ADC1_EXTRGREG:
+#if defined (AT32F403xx) || defined (AT32F403Axx) || defined (AT32F407xx)
+    case GPIO_Remap_USART2:
+    case GPIO_Remap_TMR4:
+#endif
+#ifndef AT32F415xx
+    case GPIO_Remap_ADC2_EXTRGINJ:
+    case GPIO_Remap_ADC2_EXTRGREG:
+#endif
+      AFIO->MAP &= ~GPIO_Remap;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_Remap;
+      }
+
+      break;
+
+    case GPIO_Remap01_SPI1:
+      AFIO->MAP &= 0x7FFFFFFE;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_Remap01_SPI1;
+      }
+
+      break;
+      
+#ifdef AT32F403xx
+    case GPIO_Remap10_SPI1:
+      AFIO->MAP &= 0x7FFFFFFE;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_Remap10_SPI1;
+      }
+
+      break;
+#endif
+      
+    case GPIO_PartialRemap_USART3:
+      AFIO->MAP &= 0xFFFFFFCF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_PartialRemap_USART3;
+      }
+
+      break;
+      
+#ifdef AT32F415xx
+    case GPIO_PartialRemap2_USART3:
+      AFIO->MAP &= 0xFFFFFFCF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_PartialRemap2_USART3;
+      }
+
+      break;
+      
+    case GPIO_PartialRemap2_TMR1:
+      AFIO->MAP &= 0xFFFFFF3F;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_PartialRemap2_TMR1;
+      }
+
+      break;
+#endif
+
+#if defined (AT32F403xx) || defined (AT32F403Axx) || defined (AT32F407xx)
+    case GPIO_FullRemap_USART3:
+      AFIO->MAP &= 0xFFFFFFCF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_FullRemap_USART3;
+      }
+
+      break;
+#endif
+
+    case GPIO_PartialRemap_TMR1:
+      AFIO->MAP &= 0xFFFFFF3F;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_PartialRemap_TMR1;
+      }
+
+      break;
+
+#if defined (AT32F403xx) || defined (AT32F403Axx) || defined (AT32F407xx)
+    case GPIO_FullRemap_TMR1:
+      AFIO->MAP &= 0xFFFFFF3F;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_FullRemap_TMR1;
+      }
+
+      break;
+#endif
+
+    case GPIO_PartialRemap1_TMR2:
+      AFIO->MAP &= 0xFFFFFCFF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_PartialRemap1_TMR2;
+      }
+
+      break;
+
+    case GPIO_PartialRemap2_TMR2:
+      AFIO->MAP &= 0xFFFFFCFF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_PartialRemap2_TMR2;
+      }
+
+      break;
+
+    case GPIO_FullRemap_TMR2:
+      AFIO->MAP &= 0xFFFFFCFF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_FullRemap_TMR2;
+      }
+
+      break;
+
+    case GPIO_PartialRemap_TMR3:
+      AFIO->MAP &= 0xFFFFF3FF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_PartialRemap_TMR3;
+      }
+
+      break;
+
+    case GPIO_FullRemap_TMR3:
+      AFIO->MAP &= 0xFFFFF3FF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_FullRemap_TMR3;
+      }
+
+      break;
+
+    case GPIO_Remap1_CAN1:
+      AFIO->MAP &= 0xFFFF9FFF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_Remap1_CAN1;
+      }
+
+      break;
+
+#if defined (AT32F403xx) || defined (AT32F403Axx) || defined (AT32F407xx)
+    case GPIO_Remap2_CAN1:
+      AFIO->MAP &= 0xFFFF9FFF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_Remap2_CAN1;
+      }
+
+      break;
+#endif
+
+    case GPIO_Remap_SWJ_NoJNTRST:
+      AFIO->MAP &= 0xF8FFFFFF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_Remap_SWJ_NoJNTRST;
+      }
+
+      break;
+
+    case GPIO_Remap_SWJ_JTAGDisable:
+      AFIO->MAP &= 0xF8FFFFFF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_Remap_SWJ_JTAGDisable;
+      }
+
+      break;
+
+    case GPIO_Remap_SWJ_AllDisable:
+      AFIO->MAP &= 0xF8FFFFFF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_Remap_SWJ_AllDisable;
+      }
+
+      break;
+      
+#if defined (AT32F403Axx) || defined (AT32F407xx)
+    case GPIO_Remap_PTP_PPS:
+      AFIO->MAP &= ~GPIO_Remap_PTP_PPS;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_Remap_PTP_PPS;
+      }
+
+      break;
+      
+    case GPIO_Remap_TMR2ITR1:
+      AFIO->MAP &= ~GPIO_Remap_TMR2ITR1;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_Remap_TMR2ITR1;
+      }
+
+      break;
+      
+    case GPIO_Remap_SPI3:
+      AFIO->MAP &= ~GPIO_Remap_SPI3;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_Remap_SPI3;
+      }
+
+      break;
+      
+    case GPIO_Remap_MII_RMII:
+      AFIO->MAP &= ~GPIO_Remap_MII_RMII;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_Remap_MII_RMII;
+      }
+
+      break;
+      
+    case GPIO_Remap_CAN2:
+      AFIO->MAP &= ~GPIO_Remap_CAN2;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_Remap_CAN2;
+      }
+
+      break;
+      
+    case GPIO_Remap_ETH:
+      AFIO->MAP &= ~GPIO_Remap_ETH;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP |= GPIO_Remap_ETH;
+      }
+
+      break;
+#endif
+      
+#if defined (AT32F403xx)
+    case GPIO_Remap_TMR15:
+    case GPIO_Remap_TMR10:
+    case GPIO_Remap_TMR11:
+    case GPIO_Remap_TMR13:
+    case GPIO_Remap_TMR14:
+      AFIO->MAP2 &= ~(GPIO_Remap & 0x003FFFFF);
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP2 |= (GPIO_Remap & 0x003FFFFF);
+      }
+
+      break;
+#endif
+      
+#if defined (AT32F403xx) || defined (AT32F403Axx) || defined (AT32F407xx)
+    case GPIO_Remap_TMR9:
+    case GPIO_Remap_XMC_NADV:
+    case GPIO_Remap_SPI4:
+    case GPIO_Remap_I2C3:
+    case GPIO_Remap_EXT_FLASH:
+      AFIO->MAP2 &= ~(GPIO_Remap & 0x003FFFFF);
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP2 |= (GPIO_Remap & 0x003FFFFF);
+      }
+
+      break;
+
+    case GPIO_Remap01_SDIO2:
+      AFIO->MAP2 &= 0xFFE7FFFF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP2 |= (GPIO_Remap01_SDIO2 & 0x003FFFFF);
+      }
+
+      break;
+
+    case GPIO_Remap10_SDIO2:
+      AFIO->MAP2 &= 0xFFE7FFFF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP2 |= (GPIO_Remap10_SDIO2 & 0x003FFFFF);
+      }
+
+      break;
+
+    case GPIO_Remap11_SDIO2:
+      AFIO->MAP2 &= 0xFFE7FFFF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP2 |= (GPIO_Remap11_SDIO2 & 0x003FFFFF);
+      }
+
+      break;
+#elif defined (AT32F413xx)
+    case GPIO_Remap_EXT_FLASH:
+      AFIO->MAP2 &= ~(GPIO_Remap & 0x003FFFFF);
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP2 |= (GPIO_Remap & 0x003FFFFF);
+      }
+
+      break;
+#elif defined (AT32F415xx)
+    case GPIO_Remap01_COMP:
+      AFIO->MAP2 &= 0xF3FFFFFF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP2 |= (GPIO_Remap01_COMP & 0xBFFFFFFF);
+      }
+
+      break;
+      
+    case GPIO_Remap10_COMP:
+      AFIO->MAP2 &= 0xF3FFFFFF;
+
+      if(NewState == ENABLE)
+      {
+        AFIO->MAP2 |= (GPIO_Remap10_COMP & 0xBFFFFFFF);
+      }
+
+      break;
+#endif
+      
+    default:
+      break;
+    }
+  }
+}
+
+/**
+  * @brief  Selects the GPIO pin used as EXTI Line.
+  * @param  GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
+  *   This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
+  * @param  GPIO_PinSource: specifies the EXTI line to be configured.
+  *   This parameter can be GPIO_PinSourcex where x can be (0..15).
+  * @retval None
+  */
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+  uint32_t tmp = 0x00;
+  /* Check the parameters */
+  assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
+  assert_param(IS_GPIO_PINS_SOURCE(GPIO_PinSource));
+
+  tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
+  AFIO->EXTIC[GPIO_PinSource >> 0x02] &= ~tmp;
+  AFIO->EXTIC[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
+}
+
+/**
+  * @brief  Selects the Ethernet media interface.
+  * @note   This function applies only to AT32 Connectivity line devices.  
+  * @param  GPIO_ETH_MediaInterface: specifies the Media Interface mode.
+  *   This parameter can be one of the following values:
+  *     @arg GPIO_ETH_MediaInterface_MII: MII mode
+  *     @arg GPIO_ETH_MediaInterface_RMII: RMII mode    
+  * @retval None
+  */
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) 
+{ 
+  assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); 
+  /* Configure MII_RMII selection bit */ 
+  *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; 
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_i2c.c

@@ -0,0 +1,1251 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_i2c.c
+ * Description  : at32f4xx I2C source file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_i2c.h"
+#include "at32f4xx_rcc.h"
+
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup I2C
+  * @brief I2C driver modules
+  * @{
+  */
+
+/** @defgroup I2C_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Private_Defines
+  * @{
+  */
+
+/* I2C SPE mask */
+#define CTRL1_PEN_Set               ((uint16_t)0x0001)
+#define CTRL1_PEN_Reset             ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CTRL1_STARTGEN_Set          ((uint16_t)0x0100)
+#define CTRL1_STARTGEN_Reset        ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CTRL1_STOPGEN_Set           ((uint16_t)0x0200)
+#define CTRL1_STOPGEN_Reset         ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CTRL1_ACKEN_Set             ((uint16_t)0x0400)
+#define CTRL1_ACKEN_Reset           ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CTRL1_GCEN_Set              ((uint16_t)0x0040)
+#define CTRL1_GCEN_Reset            ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CTRL1_SWRESET_Set           ((uint16_t)0x8000)
+#define CTRL1_SWRESET_Reset         ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CTRL1_PECTRA_Set            ((uint16_t)0x1000)
+#define CTRL1_PECTRA_Reset          ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CTRL1_PECEN_Set             ((uint16_t)0x0020)
+#define CTRL1_PECEN_Reset           ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CTRL1_ARPEN_Set             ((uint16_t)0x0010)
+#define CTRL1_ARPEN_Reset           ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CTRL1_NOCLKSTRETCH_Set      ((uint16_t)0x0080)
+#define CTRL1_NOCLKSTRETCH_Reset    ((uint16_t)0xFF7F)
+
+/* I2C registers Masks */
+#define CTRL1_CLEAR_MASK            ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CTRL2_DMAEN_Set             ((uint16_t)0x0800)
+#define CTRL2_DMAEN_Reset           ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CTRL2_DMALAST_Set           ((uint16_t)0x1000)
+#define CTRL2_DMALAST_Reset         ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CTRL2_CLKFREQ_Reset         ((uint16_t)0xFF00)
+
+/* I2C ADD0 mask */
+#define OADDR1_ADDR0_Set            ((uint16_t)0x0001)
+#define OADDR1_ADDR0_Reset          ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OADDR2_DUALEN_Set           ((uint16_t)0x0001)
+#define OADDR2_DUALEN_Reset         ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OADDR2_ADDR2_Reset          ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CLKCTRL_FSMODE_Set          ((uint16_t)0x8000)
+
+/* I2C CCR mask */
+#define CLKCTRL_CLKCTRL_Set         ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+#define FLAG_Mask                   ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define INTEN_Mask                  ((uint32_t)0x07000000)
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the I2Cx peripheral registers to their default reset values.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @retval None
+  */
+void I2C_DeInit(I2C_Type* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  if (I2Cx == I2C1)
+  {
+    /* Enable I2C1 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_I2C1, ENABLE);
+    /* Release I2C1 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_I2C1, DISABLE);
+  }
+  else if (I2Cx == I2C2)
+  {
+    /* Enable I2C2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_I2C2, ENABLE);
+    /* Release I2C2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_I2C2, DISABLE);
+  }
+#ifdef AT32F403xx
+  else if (I2Cx == I2C3)
+  {
+    /* Enable I2C3 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_I2C3, ENABLE);
+    /* Release I2C3 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_I2C3, DISABLE);
+  }
+#endif
+}
+
+/**
+  * @brief  Initializes the I2Cx peripheral according to the specified
+  *   parameters in the I2C_InitStruct.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_InitStruct: pointer to a I2C_InitType structure that
+  *   contains the configuration information for the specified I2C peripheral.
+  * @retval None
+  */
+void I2C_Init(I2C_Type* I2Cx, I2C_InitType* I2C_InitStruct)
+{
+  uint16_t tmpreg = 0, freqrange = 0;
+  uint16_t result = 0x04;
+  uint32_t pclk1 = 8000000;
+  RCC_ClockType  rcc_clocks;
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_BIT_RATE(I2C_InitStruct->I2C_BitRate));
+  assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+  assert_param(IS_I2C_FM_DUTY_CYCLE(I2C_InitStruct->I2C_FmDutyCycle));
+  assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddr1));
+  assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
+  assert_param(IS_I2C_ADDR_MODE(I2C_InitStruct->I2C_AddrMode));
+
+  /*---------------------------- I2Cx CTRL2 Configuration ------------------------*/
+  /* Get the I2Cx CTRL2 value */
+  tmpreg = I2Cx->CTRL2;
+  /* Clear frequency FREQ[7:0] bits */
+  tmpreg &= CTRL2_CLKFREQ_Reset;
+  /* Get pclk1 frequency value */
+  RCC_GetClocksFreq(&rcc_clocks);
+  pclk1 = rcc_clocks.APB1CLK_Freq;
+  /* Set frequency bits depending on pclk1 value */
+  freqrange = (uint16_t)(pclk1 / 1000000);
+  tmpreg |= freqrange;
+  /* Write to I2Cx CTRL2 */
+  I2Cx->CTRL2 = tmpreg;
+
+  /*---------------------------- I2Cx CCR Configuration ------------------------*/
+  /* Disable the selected I2C peripheral to configure TRISE */
+  I2Cx->CTRL1 &= CTRL1_PEN_Reset;
+  /* Reset tmpreg value */
+  /* Clear F/S, DUTY and CCR[11:0] bits */
+  tmpreg = 0;
+
+  /* Configure speed in standard mode */
+  if (I2C_InitStruct->I2C_BitRate <= 100000)
+  {
+    /* Standard mode speed calculate */
+    result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_BitRate << 1));
+
+    /* Test if CCR value is under 0x4*/
+    if (result < 0x04)
+    {
+      /* Set minimum allowed value */
+      result = 0x04;
+    }
+
+    /* Set speed value for standard mode */
+    tmpreg |= result;
+    /* Set Maximum Rise Time for standard mode */
+    I2Cx->TMRISE = freqrange + 1;
+  }
+  /* Configure speed in fast mode */
+  else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
+  {
+    if (I2C_InitStruct->I2C_FmDutyCycle == I2C_FmDutyCycle_2_1)
+    {
+      /* Fast mode speed calculate: Tlow/Thigh = 2 */
+      result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_BitRate * 3));
+    }
+    else /*I2C_InitStruct->I2C_DutyCycle == I2C_FmDutyCycle_16_9*/
+    {
+      /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+      result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_BitRate * 25));
+      /* Set DUTY bit */
+      result |= I2C_FmDutyCycle_16_9;
+    }
+
+    /* Test if CCR value is under 0x1*/
+    if ((result & CLKCTRL_CLKCTRL_Set) == 0)
+    {
+      /* Set minimum allowed value */
+      result |= (uint16_t)0x0001;
+    }
+
+    /* Set speed value and set F/S bit for fast mode */
+    tmpreg |= (uint16_t)(result | CLKCTRL_FSMODE_Set);
+    /* Set Maximum Rise Time for fast mode */
+    I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
+  }
+
+  /* Write to I2Cx CCR */
+  I2Cx->CLKCTRL = tmpreg;
+  /* Enable the selected I2C peripheral */
+  I2Cx->CTRL1 |= CTRL1_PEN_Set;
+
+  /*---------------------------- I2Cx CTRL1 Configuration ------------------------*/
+  /* Get the I2Cx CTRL1 value */
+  tmpreg = I2Cx->CTRL1;
+  /* Clear ACK, SMBTYPE and  SMBUS bits */
+  tmpreg &= CTRL1_CLEAR_MASK;
+  /* Configure I2Cx: mode and acknowledgement */
+  /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
+  /* Set ACK bit according to I2C_Ack value */
+  tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
+  /* Write to I2Cx CTRL1 */
+  I2Cx->CTRL1 = tmpreg;
+
+  /*---------------------------- I2Cx OAR1 Configuration -----------------------*/
+  /* Set I2Cx Own Address1 and acknowledged address */
+  I2Cx->OADDR1 = (I2C_InitStruct->I2C_AddrMode | I2C_InitStruct->I2C_OwnAddr1);
+}
+
+/**
+  * @brief  Fills each I2C_InitStruct member with its default value.
+  * @param  I2C_InitStruct: pointer to an I2C_InitType structure which will be initialized.
+  * @retval None
+  */
+void I2C_StructInit(I2C_InitType* I2C_InitStruct)
+{
+  /*---------------- Reset I2C init structure parameters values ----------------*/
+  /* initialize the I2C_ClockSpeed member */
+  I2C_InitStruct->I2C_BitRate = 5000;
+  /* Initialize the I2C_Mode member */
+  I2C_InitStruct->I2C_Mode = I2C_Mode_I2CDevice;
+  /* Initialize the I2C_DutyCycle member */
+  I2C_InitStruct->I2C_FmDutyCycle = I2C_FmDutyCycle_2_1;
+  /* Initialize the I2C_OwnAddress1 member */
+  I2C_InitStruct->I2C_OwnAddr1 = 0;
+  /* Initialize the I2C_Ack member */
+  I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+  /* Initialize the I2C_AcknowledgedAddress member */
+  I2C_InitStruct->I2C_AddrMode = I2C_AddrMode_7bit;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C peripheral.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_Cmd(I2C_Type* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C peripheral */
+    I2Cx->CTRL1 |= CTRL1_PEN_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C peripheral */
+    I2Cx->CTRL1 &= CTRL1_PEN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C DMA requests.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C DMA transfer.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DMACmd(I2C_Type* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C DMA requests */
+    I2Cx->CTRL2 |= CTRL2_DMAEN_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C DMA requests */
+    I2Cx->CTRL2 &= CTRL2_DMAEN_Reset;
+  }
+}
+
+/**
+  * @brief  Specifies if the next DMA transfer will be the last one.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C DMA last transfer.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DMALastTransferCmd(I2C_Type* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Next DMA transfer is the last transfer */
+    I2Cx->CTRL2 |= CTRL2_DMALAST_Set;
+  }
+  else
+  {
+    /* Next DMA transfer is not the last transfer */
+    I2Cx->CTRL2 &= CTRL2_DMALAST_Reset;
+  }
+}
+
+/**
+  * @brief  Generates I2Cx communication START condition.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C START condition generation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void I2C_GenerateSTART(I2C_Type* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Generate a START condition */
+    I2Cx->CTRL1 |= CTRL1_STARTGEN_Set;
+  }
+  else
+  {
+    /* Disable the START condition generation */
+    I2Cx->CTRL1 &= CTRL1_STARTGEN_Reset;
+  }
+}
+
+/**
+  * @brief  Generates I2Cx communication STOP condition.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C STOP condition generation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void I2C_GenerateSTOP(I2C_Type* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Generate a STOP condition */
+    I2Cx->CTRL1 |= CTRL1_STOPGEN_Set;
+  }
+  else
+  {
+    /* Disable the STOP condition generation */
+    I2Cx->CTRL1 &= CTRL1_STOPGEN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C acknowledge feature.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C Acknowledgement.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void I2C_AcknowledgeConfig(I2C_Type* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the acknowledgement */
+    I2Cx->CTRL1 |= CTRL1_ACKEN_Set;
+  }
+  else
+  {
+    /* Disable the acknowledgement */
+    I2Cx->CTRL1 &= CTRL1_ACKEN_Reset;
+  }
+}
+
+/**
+  * @brief  Configures the specified I2C own address2.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  Address: specifies the 7bit I2C own address2.
+  * @retval None.
+  */
+void I2C_OwnAddress2Config(I2C_Type* I2Cx, uint8_t Address)
+{
+  uint16_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Get the old register value */
+  tmpreg = I2Cx->OADDR2;
+
+  /* Reset I2Cx Own address2 bit [7:1] */
+  tmpreg &= OADDR2_ADDR2_Reset;
+
+  /* Set I2Cx Own address2 */
+  tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+
+  /* Store the new register value */
+  I2Cx->OADDR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C dual addressing mode.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C dual addressing mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DualAddressCmd(I2C_Type* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable dual addressing mode */
+    I2Cx->OADDR2 |= OADDR2_DUALEN_Set;
+  }
+  else
+  {
+    /* Disable dual addressing mode */
+    I2Cx->OADDR2 &= OADDR2_DUALEN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C general call feature.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C General call.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GeneralCallCmd(I2C_Type* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable generall call */
+    I2Cx->CTRL1 |= CTRL1_GCEN_Set;
+  }
+  else
+  {
+    /* Disable generall call */
+    I2Cx->CTRL1 &= CTRL1_GCEN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C interrupts.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_INT: specifies the I2C interrupts sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg I2C_INT_BUF: Buffer interrupt mask
+  *     @arg I2C_INT_EVT: Event interrupt mask
+  *     @arg I2C_INT_ERR: Error interrupt mask
+  * @param  NewState: new state of the specified I2C interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_INTConfig(I2C_Type* I2Cx, uint16_t I2C_INT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_I2C_CONFIG_INT(I2C_INT));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C interrupts */
+    I2Cx->CTRL2 |= I2C_INT;
+  }
+  else
+  {
+    /* Disable the selected I2C interrupts */
+    I2Cx->CTRL2 &= (uint16_t)~I2C_INT;
+  }
+}
+
+/**
+  * @brief  Sends a data byte through the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  Data: Byte to be transmitted..
+  * @retval None
+  */
+void I2C_SendData(I2C_Type* I2Cx, uint8_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  /* Write in the DR register the data to be sent */
+  I2Cx->DT = Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @retval The value of the received data.
+  */
+uint8_t I2C_ReceiveData(I2C_Type* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  /* Return the data in the DR register */
+  return (uint8_t)I2Cx->DT;
+}
+
+/**
+  * @brief  Transmits the address byte to select the slave device.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  Address: specifies the slave address which will be transmitted
+  * @param  I2C_Direction: specifies whether the I2C device will be a
+  *   Transmitter or a Receiver. This parameter can be one of the following values
+  *     @arg I2C_Direction_Transmit: Transmitter mode
+  *     @arg I2C_Direction_Receive: Receiver mode
+  * @retval None.
+  */
+void I2C_Send7bitAddress(I2C_Type* I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_DIRECTION(I2C_Direction));
+
+  /* Test on the direction to set/reset the read/write bit */
+  if (I2C_Direction != I2C_Direction_Transmit)
+  {
+    /* Set the address bit0 for read */
+    Address |= OADDR1_ADDR0_Set;
+  }
+  else
+  {
+    /* Reset the address bit0 for write */
+    Address &= OADDR1_ADDR0_Reset;
+  }
+
+  /* Send the address */
+  I2Cx->DT = Address;
+}
+
+/**
+  * @brief  Reads the specified I2C register and returns its value.
+  * @param  I2C_Register: specifies the register to read.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_Register_CTRL1:   CTRL1 register.
+  *     @arg I2C_Register_CTRL2:   CTRL2 register.
+  *     @arg I2C_Register_OADDR1:  OAR1 register.
+  *     @arg I2C_Register_OADDR2:  OAR2 register.
+  *     @arg I2C_Register_DT:      DR register.
+  *     @arg I2C_Register_STS1:    SR1 register.
+  *     @arg I2C_Register_STS2:    SR2 register.
+  *     @arg I2C_Register_CLKCTRL: CCR register.
+  *     @arg I2C_Register_TMRISE:  TRISE register.
+  * @retval The value of the read register.
+  */
+uint16_t I2C_ReadRegister(I2C_Type* I2Cx, uint8_t I2C_Register)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_REGISTER(I2C_Register));
+
+  tmp = (uint32_t) I2Cx;
+  tmp += I2C_Register;
+
+  /* Return the selected register value */
+  return (*(__IO uint16_t *) tmp);
+}
+
+/**
+  * @brief  Enables or disables the specified I2C software reset.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C software reset.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SoftwareResetCmd(I2C_Type* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Peripheral under reset */
+    I2Cx->CTRL1 |= CTRL1_SWRESET_Set;
+  }
+  else
+  {
+    /* Peripheral not under reset */
+    I2Cx->CTRL1 &= CTRL1_SWRESET_Reset;
+  }
+}
+
+/**
+  * @brief  Selects the specified I2C NACK position in master receiver mode.
+  *         This function is useful in I2C Master Receiver mode when the number
+  *         of data to be received is equal to 2. In this case, this function
+  *         should be called (with parameter I2C_NACKPosition_Next) before data
+  *         reception starts,as described in the 2-byte reception procedure
+  *         recommended in Reference Manual in Section: Master receiver.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_NACKPosition: specifies the NACK position.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
+  *          received byte.
+  *     @arg I2C_NACKPosition_Current: indicates that current byte is the last
+  *          received byte.
+  *
+  * @note    This function configures the same bit (POS) as I2C_PECPositionConfig()
+  *          but is intended to be used in I2C mode while I2C_PECPositionConfig()
+  *          is intended to used in SMBUS mode.
+  *
+  * @retval None
+  */
+void I2C_NACKPositionConfig(I2C_Type* I2Cx, uint16_t I2C_NACKPosition)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
+
+  /* Check the input parameter */
+  if (I2C_NACKPosition == I2C_NACKPosition_Next)
+  {
+    /* Next byte in shift register is the last received byte */
+    I2Cx->CTRL1 |= I2C_NACKPosition_Next;
+  }
+  else
+  {
+    /* Current byte in shift register is the last received byte */
+    I2Cx->CTRL1 &= I2C_NACKPosition_Current;
+  }
+}
+
+/**
+  * @brief  Drives the SMBusAlert pin high or low for the specified I2C.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_SMBusAlert: specifies SMBAlert pin level.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
+  *     @arg I2C_SMBusAlert_High: SMBAlert pin driven high
+  * @retval None
+  */
+void I2C_SMBusAlertConfig(I2C_Type* I2Cx, uint16_t I2C_SMBusAlert)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
+
+  if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
+  {
+    /* Drive the SMBusAlert pin Low */
+    I2Cx->CTRL1 |= I2C_SMBusAlert_Low;
+  }
+  else
+  {
+    /* Drive the SMBusAlert pin High  */
+    I2Cx->CTRL1 &= I2C_SMBusAlert_High;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C PEC transfer.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C PEC transmission.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_TransmitPEC(I2C_Type* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C PEC transmission */
+    I2Cx->CTRL1 |= CTRL1_PECTRA_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C PEC transmission */
+    I2Cx->CTRL1 &= CTRL1_PECTRA_Reset;
+  }
+}
+
+/**
+  * @brief  Selects the specified I2C PEC position.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_PECPosition: specifies the PEC position.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_PECPosition_Next: indicates that the next byte is PEC
+  *     @arg I2C_PECPosition_Current: indicates that current byte is PEC
+  *
+  * @note    This function configures the same bit (POS) as I2C_NACKPositionConfig()
+  *          but is intended to be used in SMBUS mode while I2C_NACKPositionConfig()
+  *          is intended to used in I2C mode.
+  *
+  * @retval None
+  */
+void I2C_PECPositionConfig(I2C_Type* I2Cx, uint16_t I2C_PECPosition)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
+
+  if (I2C_PECPosition == I2C_PECPosition_Next)
+  {
+    /* Next byte in shift register is PEC */
+    I2Cx->CTRL1 |= I2C_PECPosition_Next;
+  }
+  else
+  {
+    /* Current byte in shift register is PEC */
+    I2Cx->CTRL1 &= I2C_PECPosition_Current;
+  }
+}
+
+/**
+  * @brief  Enables or disables the PEC value calculation of the transferred bytes.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx PEC value calculation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_CalculatePEC(I2C_Type* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C PEC calculation */
+    I2Cx->CTRL1 |= CTRL1_PECEN_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C PEC calculation */
+    I2Cx->CTRL1 &= CTRL1_PECEN_Reset;
+  }
+}
+
+/**
+  * @brief  Returns the PEC value for the specified I2C.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @retval The PEC value.
+  */
+uint8_t I2C_GetPEC(I2C_Type* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  /* Return the selected I2C PEC value */
+  return ((I2Cx->STS2) >> 8);
+}
+
+/**
+  * @brief  Enables or disables the specified I2C ARP.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx ARP.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ARPCmd(I2C_Type* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C ARP */
+    I2Cx->CTRL1 |= CTRL1_ARPEN_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C ARP */
+    I2Cx->CTRL1 &= CTRL1_ARPEN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C Clock stretching.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Clock stretching.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_StretchClockCmd(I2C_Type* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState == DISABLE)
+  {
+    /* Enable the selected I2C Clock stretching */
+    I2Cx->CTRL1 |= CTRL1_NOCLKSTRETCH_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C Clock stretching */
+    I2Cx->CTRL1 &= CTRL1_NOCLKSTRETCH_Reset;
+  }
+}
+
+/**
+  * @brief  Selects the specified I2C fast mode duty cycle.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_DutyCycle: specifies the fast mode duty cycle.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_FmDutyCycle_2_1: I2C fast mode Tlow/Thigh = 2
+  *     @arg I2C_FmDutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
+  * @retval None
+  */
+void I2C_FastModeDutyCycleConfig(I2C_Type* I2Cx, uint16_t I2C_DutyCycle)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_FM_DUTY_CYCLE(I2C_DutyCycle));
+
+  if (I2C_DutyCycle != I2C_FmDutyCycle_16_9)
+  {
+    /* I2C fast mode Tlow/Thigh=2 */
+    I2Cx->CLKCTRL &= I2C_FmDutyCycle_2_1;
+  }
+  else
+  {
+    /* I2C fast mode Tlow/Thigh=16/9 */
+    I2Cx->CLKCTRL |= I2C_FmDutyCycle_16_9;
+  }
+}
+
+/**
+  * @brief  Checks whether the last I2Cx Event is equal to the one passed
+  *   as parameter.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_EVENT: specifies the event to be checked.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_EVENT_SLAVE_ADDRESS_TRANSMITTER_MATCHED             : EV1
+  *     @arg I2C_EVENT_SLAVE_ADDRESS_RECEIVER_MATCHED                : EV1
+  *     @arg I2C_EVENT_SLAVE_SECONDADDRESS_TRANSMITTER_MATCHED       : EV1
+  *     @arg I2C_EVENT_SLAVE_SECONDADDRESS_RECEIVER_MATCHED          : EV1
+  *     @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED              : EV1
+  *     @arg I2C_EVENT_SLAVE_DATA_RECEIVED                           : EV2
+  *     @arg (I2C_EVENT_SLAVE_DATA_RECEIVED | I2C_FLAG_DUALF)        : EV2
+  *     @arg (I2C_EVENT_SLAVE_DATA_RECEIVED | I2C_FLAG_GCADDRF)      : EV2
+  *     @arg I2C_EVENT_SLAVE_DATA_TRANSMITTED                        : EV3
+  *     @arg (I2C_EVENT_SLAVE_DATA_TRANSMITTED | I2C_FLAG_DUALF)     : EV3
+  *     @arg (I2C_EVENT_SLAVE_DATA_TRANSMITTED | I2C_FLAG_GCADDRF)   : EV3
+  *     @arg I2C_EVENT_SLAVE_ACK_FAILURE_DETECTED                    : EV3_2
+  *     @arg I2C_EVENT_SLAVE_STOP_DETECTED                           : EV4
+  *     @arg I2C_EVENT_MASTER_START_GENERATED                        : EV5
+  *     @arg I2C_EVENT_MASTER_ADDRESS | I2C_EVENT_MASTER_TRANSMITTER : EV6
+  *     @arg I2C_EVENT_MASTER_ADDRESS_WITH_RECEIVER                  : EV6
+  *     @arg I2C_EVENT_MASTER_DATA_RECEIVED                          : EV7
+  *     @arg I2C_EVENT_MASTER_DATA_TRANSMITTING                      : EV8
+  *     @arg I2C_EVENT_MASTER_DATA_TRANSMITTED                       : EV8_2
+  *     @arg I2C_EVENT_MASTER_ADDRESS10_GENERATED                    : EV9
+  *
+  * @note: For detailed description of Events, please refer to section
+  *    I2C_Events in at32f4xx_i2c.h file.
+  *
+  * @retval An ErrorStatus enumeration value:
+  * - SUCCESS: Last event is equal to the I2C_EVENT
+  * - ERROR: Last event is different from the I2C_EVENT
+  */
+ErrorStatus I2C_CheckEvent(I2C_Type* I2Cx, uint32_t I2C_EVENT)
+{
+  uint32_t lastevent = 0;
+  uint32_t flag1 = 0, flag2 = 0;
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_EVENT(I2C_EVENT));
+
+  /* Read the I2Cx status register */
+  flag1 = I2Cx->STS1;
+  flag2 = I2Cx->STS2;
+  flag2 = flag2 << 16;
+
+  /* Get the last event value from I2C status register */
+  lastevent = (flag1 | flag2) & FLAG_Mask;
+
+  /* Check whether the last event contains the I2C_EVENT */
+  if ((lastevent & I2C_EVENT) == I2C_EVENT)
+  {
+    /* SUCCESS: last event is equal to I2C_EVENT */
+    status = SUCCESS;
+  }
+  else
+  {
+    /* ERROR: last event is different from I2C_EVENT */
+    status = ERROR;
+  }
+
+  /* Return status */
+  return status;
+}
+
+/**
+  * @brief  Returns the last I2Cx Event.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  *
+  * @note: For detailed description of Events, please refer to section
+  *    I2C_Events in at32f4xx_i2c.h file.
+  *
+  * @retval The last event
+  */
+uint32_t I2C_GetLastEvent(I2C_Type* I2Cx)
+{
+  uint32_t lastevent = 0;
+  uint32_t flag1 = 0, flag2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Read the I2Cx status register */
+  flag1 = I2Cx->STS1;
+  flag2 = I2Cx->STS2;
+  flag2 = flag2 << 16;
+
+  /* Get the last event value from I2C status register */
+  lastevent = (flag1 | flag2) & FLAG_Mask;
+
+  /* Return status */
+  return lastevent;
+}
+
+/**
+  * @brief  Checks whether the specified I2C flag is set or not.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
+  *     @arg I2C_FLAG_SMBHOSTADDRF: SMBus host header (Slave mode)
+  *     @arg I2C_FLAG_SMBDEFTADDRF: SMBus default header (Slave mode)
+  *     @arg I2C_FLAG_GCADDRF: General call header flag (Slave mode)
+  *     @arg I2C_FLAG_TRF: Transmitter/Receiver flag
+  *     @arg I2C_FLAG_BUSYF: Bus busy flag
+  *     @arg I2C_FLAG_MSF: Master/Slave flag
+  *     @arg I2C_FLAG_SMBALERTF: SMBus Alert flag
+  *     @arg I2C_FLAG_TIMOUT: Timeout or Tlow error flag
+  *     @arg I2C_FLAG_PECERR: PEC error in reception flag
+  *     @arg I2C_FLAG_OVRUN: Overrun/Underrun flag (Slave mode)
+  *     @arg I2C_FLAG_ACKFAIL: Acknowledge failure flag
+  *     @arg I2C_FLAG_ARLOST: Arbitration lost flag (Master mode)
+  *     @arg I2C_FLAG_BUSERR: Bus error flag
+  *     @arg I2C_FLAG_TDE: Data register empty flag (Transmitter)
+  *     @arg I2C_FLAG_RDNE: Data register not empty (Receiver) flag
+  *     @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
+  *     @arg I2C_FLAG_ADDR10F: 10-bit header sent flag (Master mode)
+  *     @arg I2C_FLAG_BTFF: Byte transfer finished flag
+  *     @arg I2C_FLAG_ADDRF: Address sent flag (Master mode) "ADSL"
+  *   Address matched flag (Slave mode)"ENDA"
+  *     @arg I2C_FLAG_STARTF: Start bit flag (Master mode)
+  * @retval The new state of I2C_FLAG (SET or RESET).
+  */
+FlagStatus I2C_GetFlagStatus(I2C_Type* I2Cx, uint32_t I2C_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+  /* Get the I2Cx peripheral base address */
+  i2cxbase = (uint32_t)I2Cx;
+
+  /* Read flag register index */
+  i2creg = I2C_FLAG >> 28;
+
+  /* Get bit[23:0] of the flag */
+  I2C_FLAG &= FLAG_Mask;
+
+  if(i2creg != 0)
+  {
+    /* Get the I2Cx SR1 register address */
+    i2cxbase += 0x14;
+  }
+  else
+  {
+    /* Flag in I2Cx SR2 Register */
+    I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+    /* Get the I2Cx SR2 register address */
+    i2cxbase += 0x18;
+  }
+
+  if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+  {
+    /* I2C_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_FLAG is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the I2C_FLAG status */
+  return  bitstatus;
+}
+
+
+
+/**
+  * @brief  Clears the I2Cx's pending flags.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg I2C_FLAG_SMBALERTF: SMBus Alert flag
+  *     @arg I2C_FLAG_TIMOUT: Timeout or Tlow error flag
+  *     @arg I2C_FLAG_PECERR: PEC error in reception flag
+  *     @arg I2C_FLAG_OVRUN: Overrun/Underrun flag (Slave mode)
+  *     @arg I2C_FLAG_ACKFAIL: Acknowledge failure flag
+  *     @arg I2C_FLAG_ARLOST: Arbitration lost flag (Master mode)
+  *     @arg I2C_FLAG_BUSERR: Bus error flag
+  *
+  * @note
+  *   - STOPF (STOP detection) is cleared by software sequence: a read operation
+  *     to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
+  *     to I2C_CTRL1 register (I2C_Cmd() to re-enable the I2C peripheral).
+  *   - ADD10 (10-bit header sent) is cleared by software sequence: a read
+  *     operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
+  *     second byte of the address in DR register.
+  *   - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+  *     operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
+  *     read/write to I2C_DR register (I2C_SendData()).
+  *   - ADDR (Address sent) is cleared by software sequence: a read operation to
+  *     I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to
+  *     I2C_SR2 register ((void)(I2Cx->SR2)).
+  *   - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
+  *     register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
+  *     register  (I2C_SendData()).
+  * @retval None
+  */
+void I2C_ClearFlag(I2C_Type* I2Cx, uint32_t I2C_FLAG)
+{
+  uint32_t flagpos = 0;
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+  /* Get the I2C flag position */
+  flagpos = I2C_FLAG & FLAG_Mask;
+  /* Clear the selected I2C flag */
+  I2Cx->STS1 = (uint16_t)~flagpos;
+}
+
+/**
+  * @brief  Checks whether the specified I2C interrupt has occurred or not.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_INT: specifies the interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_INT_SMBALERTF: SMBus Alert flag
+  *     @arg I2C_INT_TIMOUT: Timeout or Tlow error flag
+  *     @arg I2C_INT_PECERR: PEC error in reception flag
+  *     @arg I2C_INT_OVRUN: Overrun/Underrun flag (Slave mode)
+  *     @arg I2C_INT_ACKFAIL: Acknowledge failure flag
+  *     @arg I2C_INT_ARLOST: Arbitration lost flag (Master mode)
+  *     @arg I2C_INT_BUSERR: Bus error flag
+  *     @arg I2C_INT_TDE: Data register empty flag (Transmitter)
+  *     @arg I2C_INT_RDNE: Data register not empty (Receiver) flag
+  *     @arg I2C_INT_STOPF: Stop detection flag (Slave mode)
+  *     @arg I2C_INT_ADDR10F: 10-bit header sent flag (Master mode)
+  *     @arg I2C_INT_BTFF: Byte transfer finished flag
+  *     @arg I2C_INT_ADDRF: Address sent flag (Master mode) "ADSL"
+  *                       Address matched flag (Slave mode)"ENDAD"
+  *     @arg I2C_INT_STARTF: Start bit flag (Master mode)
+  * @retval The new state of I2C_INT (SET or RESET).
+  */
+ITStatus I2C_GetINTStatus(I2C_Type* I2Cx, uint32_t I2C_INT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_INT(I2C_INT));
+
+  /* Check if the interrupt source is enabled or not */
+  enablestatus = (uint32_t)(((I2C_INT & INTEN_Mask) >> 16) & (I2Cx->CTRL2)) ;
+
+  /* Get bit[23:0] of the flag */
+  I2C_INT &= FLAG_Mask;
+
+  /* Check the status of the specified I2C flag */
+  if (((I2Cx->STS1 & I2C_INT) != (uint32_t)RESET) && enablestatus)
+  {
+    /* I2C_INT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_INT is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the I2C_INT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the I2Cx interrupt pending bits.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_INT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg I2C_INT_SMBALERTF: SMBus Alert interrupt
+  *     @arg I2C_INT_TIMOUT: Timeout or Tlow error interrupt
+  *     @arg I2C_INT_PECERR: PEC error in reception  interrupt
+  *     @arg I2C_INT_OVRUN: Overrun/Underrun interrupt (Slave mode)
+  *     @arg I2C_INT_ACKFAIL: Acknowledge failure interrupt
+  *     @arg I2C_INT_ARLOST: Arbitration lost interrupt (Master mode)
+  *     @arg I2C_INT_BUSERR: Bus error interrupt
+  *
+  * @note
+  *   - STOPF (STOP detection) is cleared by software sequence: a read operation
+  *     to I2C_SR1 register (I2C_GetINTStatus()) followed by a write operation to
+  *     I2C_CTRL1 register (I2C_Cmd() to re-enable the I2C peripheral).
+  *   - ADD10 (10-bit header sent) is cleared by software sequence: a read
+  *     operation to I2C_SR1 (I2C_GetINTStatus()) followed by writing the second
+  *     byte of the address in I2C_DR register.
+  *   - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+  *     operation to I2C_SR1 register (I2C_GetINTStatus()) followed by a
+  *     read/write to I2C_DR register (I2C_SendData()).
+  *   - ADDR (Address sent) is cleared by software sequence: a read operation to
+  *     I2C_SR1 register (I2C_GetINTStatus()) followed by a read operation to
+  *     I2C_SR2 register ((void)(I2Cx->SR2)).
+  *   - SB (Start Bit) is cleared by software sequence: a read operation to
+  *     I2C_SR1 register (I2C_GetINTStatus()) followed by a write operation to
+  *     I2C_DR register (I2C_SendData()).
+  * @retval None
+  */
+void I2C_ClearITPendingBit(I2C_Type* I2Cx, uint32_t I2C_INT)
+{
+  uint32_t flagpos = 0;
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_INT(I2C_INT));
+  /* Get the I2C flag position */
+  flagpos = I2C_INT & FLAG_Mask;
+  /* Clear the selected I2C flag */
+  I2Cx->STS1 = (uint16_t)~flagpos;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_iwdg.c

@@ -0,0 +1,181 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_iwdg.c
+ * Description  : at32f4xx IWDG source file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_iwdg.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup IWDG
+  * @brief IWDG driver modules
+  * @{
+  */
+
+/** @defgroup IWDG_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_Defines
+  * @{
+  */
+
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+
+/* KR register bit mask */
+#define KR_KEY_Reload           ((uint16_t)0xAAAA)
+#define KR_KEY_Enable           ((uint16_t)0xCCCC)
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+  * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+  *   This parameter can be one of the following values:
+  *     @arg IWDG_KeyRegWrite_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+  *     @arg IWDG_KeyRegWrite_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+  * @retval None
+  */
+void IWDG_KeyRegWrite(uint16_t IWDG_WriteAccess)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_KEY_REG_WRITE(IWDG_WriteAccess));
+  IWDG->KEY = IWDG_WriteAccess;
+}
+
+/**
+  * @brief  Sets IWDG Prescaler value.
+  * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
+  *   This parameter can be one of the following values:
+  *     @arg IWDG_Psc_4: IWDG prescaler set to 4
+  *     @arg IWDG_Psc_8: IWDG prescaler set to 8
+  *     @arg IWDG_Psc_16: IWDG prescaler set to 16
+  *     @arg IWDG_Psc_32: IWDG prescaler set to 32
+  *     @arg IWDG_Psc_64: IWDG prescaler set to 64
+  *     @arg IWDG_Psc_128: IWDG prescaler set to 128
+  *     @arg IWDG_Psc_256: IWDG prescaler set to 256
+  * @retval None
+  */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_PSC(IWDG_Prescaler));
+  IWDG->PSC = IWDG_Prescaler;
+}
+
+/**
+  * @brief  Sets IWDG Reload value.
+  * @param  Reload: specifies the IWDG Reload value.
+  *   This parameter must be a number between 0 and 0x0FFF.
+  * @retval None
+  */
+void IWDG_SetReload(uint16_t Reload)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_RLD(Reload));
+  IWDG->RLD = Reload;
+}
+
+/**
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  *   (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_ReloadCounter(void)
+{
+  IWDG->KEY = KR_KEY_Reload;
+}
+
+/**
+  * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_Enable(void)
+{
+  IWDG->KEY = KR_KEY_Enable;
+}
+
+/**
+  * @brief  Checks whether the specified IWDG flag is set or not.
+  * @param  IWDG_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg IWDG_FLAG_PSCF: Prescaler Value Update on going
+  *     @arg IWDG_FLAG_RLDF: Reload Value Update on going
+  * @retval The new state of IWDG_FLAG (SET or RESET).
+  */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+
+  if ((IWDG->STS & IWDG_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_pwr.c

@@ -0,0 +1,377 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_pwr.c
+ * Description  : at32f4xx PWR source file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_pwr.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup PWR
+  * @brief PWR driver modules
+  * @{
+  */
+
+/** @defgroup PWR_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_Defines
+  * @{
+  */
+
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET                  (PWR_BASE - PERIPH_BASE)
+
+/* --- CTRL Register ---*/
+
+/* Alias word address of DBP bit */
+#define CTRL_OFFSET                 (PWR_OFFSET + 0x00)
+#define DBP_BitNumber                0x08
+#define CTRL_DBP_BB                 (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber              0x04
+#define CTRL_PVDE_BB                (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* --- CTRLSTS Register ---*/
+
+/* Alias word address of EWUP bit */
+#define CTRLSTS_OFFSET              (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber              0x08
+#define CTRLSTS_EWUP_BB             (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CTRL register bit mask */
+#if defined (AT32F403xx) || defined (AT32F413xx)
+    #define CTRL_DS_MASK                ((uint32_t)0xFFFFFFFD)
+#else
+    #define CTRL_DS_MASK                ((uint32_t)0xFFFFFFFC)
+#endif
+#define CTRL_PVDS_MASK              ((uint32_t)0xFFFFFF1F)
+
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void PWR_Reset(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_PWR, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_PWR, DISABLE);
+}
+
+/**
+  * @brief  Enables or disables access to the RTC and backup registers.
+  * @param  NewState: new state of the access to the RTC and backup registers.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_BackupAccessCtrl(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CTRL_DBP_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the Power Voltage Detector(PVD).
+  * @param  NewState: new state of the PVD.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_PVDCtrl(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CTRL_PVDE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @param  PWR_PVDLevel: specifies the PVD detection level
+  *   This parameter can be one of the following values:
+  *     @arg PWR_PVDS_2V2: PVD detection level set to 2.2V
+  *     @arg PWR_PVDS_2V3: PVD detection level set to 2.3V
+  *     @arg PWR_PVDS_2V4: PVD detection level set to 2.4V
+  *     @arg PWR_PVDS_2V5: PVD detection level set to 2.5V
+  *     @arg PWR_PVDS_2V6: PVD detection level set to 2.6V
+  *     @arg PWR_PVDS_2V7: PVD detection level set to 2.7V
+  *     @arg PWR_PVDS_2V8: PVD detection level set to 2.8V
+  *     @arg PWR_PVDS_2V9: PVD detection level set to 2.9V
+  * @retval None
+  */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+  tmpreg = PWR->CTRL;
+  /* Clear PLS[7:5] bits */
+  tmpreg &= CTRL_PVDS_MASK;
+  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+  tmpreg |= PWR_PVDLevel;
+  /* Store the new value */
+  PWR->CTRL = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the WakeUp Pin functionality.
+  * @param  NewState: new state of the WakeUp Pin functionality.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_WakeUpPinCtrl(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CTRLSTS_EWUP_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enters Sleep mode.
+  * @note   In Sleep mode, all I/O pins keep the same state as in Run mode.
+  * @param  PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *             @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
+  *             @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
+
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+  
+  /* Select SLEEP mode entry -------------------------------------------------*/
+  if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+	__WFE();
+	__WFE();
+  }
+}
+
+#if defined (AT32F403xx) || defined (AT32F413xx)
+/**
+  * @brief  Enters STOP mode.
+  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+  *     @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tmpreg = PWR->CTRL;
+  /* Clear PDDS bit */
+  tmpreg &= CTRL_DS_MASK;
+  /* Store the new value */
+  PWR->CTRL = tmpreg;
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
+
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+	__WFE();
+	__WFE();
+  }
+
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+}
+#else
+/**
+  * @brief  Enters STOP mode.
+  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_Regulator_ON: STOP mode with regulator ON
+  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+  *     @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tmpreg = PWR->CTRL;
+  /* Clear PDDS bit */
+  tmpreg &= CTRL_DS_MASK;
+  /* Set PWR_Regulator value */
+  tmpreg |= PWR_Regulator;
+  /* Store the new value */
+  PWR->CTRL = tmpreg;
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
+
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+	__WFE();
+	__WFE();
+  }
+
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+}
+#endif
+
+/**
+  * @brief  Enters STANDBY mode.
+  * @param  None
+  * @retval None
+  */
+void PWR_EnterSTANDBYMode(void)
+{
+  /* Clear Wake-up flag */
+  PWR->CTRL |= PWR_CTRL_CLWUF;
+  /* Select STANDBY mode */
+  PWR->CTRL |= PWR_CTRL_PDDS;
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
+  /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM   )
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @brief  Checks whether the specified PWR flag is set or not.
+  * @param  PWR_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_FLAG_WUF: Wake Up flag
+  *     @arg PWR_FLAG_SBF: StandBy flag
+  *     @arg PWR_FLAG_PVDO: PVD Output
+  * @retval The new state of PWR_FLAG (SET or RESET).
+  */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+
+  if ((PWR->CTRLSTS & PWR_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the PWR's pending flags.
+  * @param  PWR_FLAG: specifies the flag to clear.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_FLAG_WUF: Wake Up flag
+  *     @arg PWR_FLAG_SBF: StandBy flag
+  * @retval None
+  */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+
+  PWR->CTRL |=  PWR_FLAG << 2;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_rcc.c

@@ -0,0 +1,1468 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_rcc.c
+ * Description  : at32f4xx RCC source file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup RCC
+  * @brief RCC driver modules
+  * @{
+  */
+
+/** @defgroup RCC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Private_Defines
+  * @{
+  */
+
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET                  (RCC_BASE - PERIPH_BASE)
+
+/* --- CTRL Register ---*/
+
+/* Alias word address of HSIEN bit */
+#define CTRL_OFFSET                 (RCC_OFFSET + 0x00)
+#define HSIEN_BitPos                0x00
+#define CTRL_HSIEN_BB               (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (HSIEN_BitPos * 4))
+
+/* Alias word address of PLLEN bit */
+#define PLLEN_BitPos                0x18
+#define CTRL_PLLEN_BB               (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PLLEN_BitPos * 4))
+
+/* Alias word address of HSECFDEN bit */
+#define HSECFDEN_BitPos             0x13
+#define CTRL_HSECFDEN_BB            (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (HSECFDEN_BitPos * 4))
+
+#define HSICAL_BitPos               (8)
+#if defined (AT32F403xx)
+#define HSITWK_BitPos               (3)
+#else
+#define HSITWK_BitPos               (2)
+#endif
+
+/* --- CFG Register ---*/
+
+/* Alias word address of USBPSC bit */
+#define CFG_OFFSET                  (RCC_OFFSET + 0x04)
+
+/* --- BDC Register ---*/
+#if defined (AT32F415xx)
+/* Alias word address of ERTCEN bit */
+#define BDC_OFFSET                  (RCC_OFFSET + 0x20)
+#define ERTCEN_BitPos                0x0F
+#define BDC_ERTCEN_BB                (PERIPH_BB_BASE + (BDC_OFFSET * 32) + (ERTCEN_BitPos * 4))
+#else
+/* Alias word address of RTCEN bit */
+#define BDC_OFFSET                  (RCC_OFFSET + 0x20)
+#define RTCEN_BitPos                0x0F
+#define BDC_RTCEN_BB                (PERIPH_BB_BASE + (BDC_OFFSET * 32) + (RTCEN_BitPos * 4))
+#endif
+
+/* Alias word address of BDRST bit */
+#define BDRST_BitPos                0x10
+#define BDC_BDRST_BB                (PERIPH_BB_BASE + (BDC_OFFSET * 32) + (BDRST_BitPos * 4))
+
+/* --- CTRLSTS Register ---*/
+
+/* Alias word address of LSIEN bit */
+#define CTRLSTS_OFFSET              (RCC_OFFSET + 0x24)
+#define LSIEN_BitPos                0x00
+#define CTRLSTS_LSIEN_BB            (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (LSIEN_BitPos * 4))
+
+#define MISC_OFFSET                (RCC_OFFSET + 0x30)
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+
+/* CFG register bit mask */
+#define CFG_PLL_Mask                RCC_CFG_PLLCFG_MASK
+
+#define CFG_ADCPSC_Pos              ((uint32_t)14)
+#define CFG_ADCPSCBit2_IdxMask      ((uint32_t)4)
+
+#define CFG_ADCPSC_Rst_Mask         ((uint32_t)~RCC_CFG_ADCPSC)
+#define CFG_ADCPSC_Set_Mask         ((uint32_t)0x0000C000)
+#define CFG_ADCPSCBit2_Set_Mask     ((uint32_t)0x10000000)
+
+/* RCC Flag Mask */
+#define FLAG_Mask                   ((uint8_t)0x1F)
+
+/* CLKINT register byte 2 (Bits[15:8]) base address */
+#define CLKINT_BYTE2_EN_ADDR        ((uint32_t)0x40021009)
+
+/* CLKINT register byte 3 (Bits[23:16]) base address */
+#define CLKINT_BYTE3_CLR_ADDR       ((uint32_t)0x4002100A)
+
+/* BDC register base address */
+#define BDC_BYTE0_LSE_ADDR          (PERIPH_BASE + BDC_OFFSET)
+
+/* MISC register base address */
+#define MISC_BYTE0_HSICALKEY_ADDR   (PERIPH_BASE + MISC_OFFSET)
+#define MISC_HSICAL_ENABLE_KEY      ((uint8_t)0x5A)
+#define MISC_HSICAL_DISABLE_KEY     ((uint8_t)0x0)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Private_Variables
+  * @{
+  */
+static __I uint8_t APBAHBPscTable[8] = {1, 2, 3, 4, 6, 7, 8, 9};
+static __I uint8_t ADCPscTable[8] = {2, 4, 6, 8, 2, 12, 8, 16};
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Private_FunctionPrototypes
+  * @{
+  */
+static void RCC_HSEENDelay(uint32_t);
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @param  None
+  * @retval None
+  */
+void RCC_Reset(void)
+{
+  /* Set HSIEN bit */
+  RCC->CTRL |= (uint32_t)0x00000001;
+
+  /* Reset SYSCLKSEL, AHBPSC, APB1PSC, APB2PSC, ADCPSC and CLKOUT bits */
+  RCC->CFG &= (uint32_t)0xE8FF0000;
+
+  /* Reset HSEEN, HSECFDEN and PLLEN bits */
+  RCC->CTRL &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYPS bit */
+  RCC->CTRL &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLRC, PLLHSEPSC, PLLMUL, PLLFREQRANGE, and USBPSC bits */
+  RCC->CFG &= (uint32_t)0x1700FFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CLKINT = 0x009F0000;
+
+  /* Reset USB768B, CLKOUT[3], HSICAL_KEY[7:0] */
+  RCC->MISC &= 0xFEFEFF00;
+}
+
+/**
+  * @brief  Configures the External High Speed oscillator (HSE).
+  * @note   HSE can not be stopped if it is used directly or through the PLL as system clock.
+  * @param  RCC_HSE: specifies the new state of the HSE.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_HSE_DISABLE: HSE oscillator OFF
+  *     @arg RCC_HSE_ENABLE: HSE oscillator ON
+  *     @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
+  * @retval None
+  */
+void RCC_HSEConfig(uint32_t RCC_HSE)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_HSE(RCC_HSE));
+  /* Reset HSEEN and HSEBYPS bits before configuring the HSE ------------------*/
+  /* Reset HSEEN bit */
+  RCC->CTRL &= ~RCC_CTRL_HSEEN;
+  /* Reset HSEBYPS bit */
+  RCC->CTRL &= ~RCC_CTRL_HSEBYPS;
+
+  /* Configure HSE (RCC_HSE_DISABLE is already covered by the code section above) */
+  switch(RCC_HSE)
+  {
+  case RCC_HSE_ENABLE:
+    /* Set HSEEN bit */
+    RCC->CTRL |= RCC_CTRL_HSEEN;
+    break;
+
+  case RCC_HSE_BYPASS:
+    /* Set HSEBYPS and HSEEN bits */
+    RCC->CTRL |= RCC_CTRL_HSEBYPS | RCC_CTRL_HSEEN;
+    break;
+
+  default:
+    break;
+  }
+}
+
+/**
+  * @brief  Waits for HSE start-up.
+  * @param  None
+  * @retval An ErrorStatus enumuration value:
+  * - SUCCESS: HSE oscillator is stable and ready to use
+  * - ERROR: HSE oscillator not yet ready
+  */
+ErrorStatus RCC_WaitForHSEStable(void)
+{
+  __IO uint32_t StartUpCounter = 0;
+  ErrorStatus status = ERROR;
+  FlagStatus HSEStatus = RESET;
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSESTBL);
+    StartUpCounter++;
+  }
+  while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+  
+  /* Delay for HSE Stable */
+  RCC_HSEENDelay(HSE_STABLE_DELAY);
+
+  if (RCC_GetFlagStatus(RCC_FLAG_HSESTBL) != RESET)
+  {
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
+  * @param  HSITweakValue: specifies the calibration trimming value.
+  *   This parameter must be a number between 0 and 0x1F.
+  * @retval None
+  */
+void RCC_SetHSITweakValue(uint8_t HSITweakValue)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_RCC_TWEAK_VALUE(HSITweakValue));
+  tmpreg = RCC->CTRL;
+  /* Clear HSITWK[4:0] bits */
+  tmpreg &= ~RCC_CTRL_HSITWK;
+  /* Set the HSITWK[4:0] bits according to HSITweakValue value */
+  tmpreg |= (uint32_t)HSITweakValue << HSITWK_BitPos;
+  /* Store the new value */
+  RCC->CTRL = tmpreg;
+}
+
+
+/**
+  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
+  * @param  HSICalibValue: specifies the calibration value.
+  *   This parameter must be a number between 0 and 0xFF.
+  * @retval None
+  */
+void RCC_SetHSICalibValue(uint8_t HSICalibValue)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_RCC_CALIB_VALUE(HSICalibValue));
+
+  /* Enable write HSICAL */
+  *(__IO uint8_t *) MISC_BYTE0_HSICALKEY_ADDR = MISC_HSICAL_ENABLE_KEY;
+
+  /* Get RCC_CTRL and clear HSICAL bits */
+  tmpreg = RCC->CTRL & (~RCC_CTRL_HSICAL);
+  /* Set the HSICAL[7:0] bits according to HSICalibValue value */
+  tmpreg |= (uint32_t)HSICalibValue << HSICAL_BitPos;
+  /* Store the new value */
+  RCC->CTRL = tmpreg;
+
+  /* Disable write HSICAL */
+  *(__IO uint8_t *) MISC_BYTE0_HSICALKEY_ADDR = MISC_HSICAL_DISABLE_KEY;
+}
+
+
+/**
+  * @brief  Enables or disables the Internal High Speed oscillator (HSI).
+  * @note   HSI can not be stopped if it is used directly or through the PLL as system clock.
+  * @param  NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_HSICmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CTRL_HSIEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the PLL clock source and multiplication factor.
+  * @note   This function must be used only when the PLL is disabled.
+  * @param  RCC_PLLRefClk: specifies the PLL entry clock source.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_PLLRefClk_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
+  *     @arg RCC_PLLRefClk_HSE_Div1: HSE oscillator clock selected as PLL clock entry
+  *     @arg RCC_PLLRefClk_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry
+  * @param  RCC_PLLMult: specifies the PLL multiplication factor.
+  *   			This parameter can be RCC_PLLMult_x where x:[2,64]
+  * @param  RCC_PLLRange: specifies the PLL frequency range
+  *     @arg RCC_Range_LessEqual_72Mhz: When PLL output is less than or equal to 72 MHz.
+  *     @arg RCC_Range_GreatThan_72Mhz: When PLL output is greater than 72 MHz.
+  *
+  * @retval None
+  */
+void RCC_PLLConfig(uint32_t RCC_PLLRefClk, uint32_t RCC_PLLMult, uint32_t RCC_PLLRange)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL_CFG(RCC_PLLRefClk));
+  assert_param(IS_RCC_PLL_MULT(RCC_PLLMult));
+  assert_param(IS_RCC_PLL_RANGE(RCC_PLLRange));
+
+  tmpreg = RCC->CFG;
+  /* Clear PLLRC, PLLHSEPSC and PLLMULT[5:0] bits */
+  tmpreg &= CFG_PLL_Mask;
+  /* Set the PLL configuration bits */
+  tmpreg |= RCC_PLLRefClk | RCC_PLLMult | RCC_PLLRange;
+  /* Store the new value */
+  RCC->CFG = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the PLL.
+  * @note   The PLL can not be disabled if it is used as system clock.
+  * @param  NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CTRL_PLLEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the system clock (SYSCLK).
+  * @param  RCC_SYSCLKSelect: specifies the clock source used as system clock.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_SYSCLKSelction_HSI: HSI selected as system clock
+  *     @arg RCC_SYSCLKSelction_HSE: HSE selected as system clock
+  *     @arg RCC_SYSCLKSelction_PLL: PLL selected as system clock
+  * @retval None
+  */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSelect)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_RCC_SYSCLK_CFG(RCC_SYSCLKSelect));
+  tmpreg = RCC->CFG;
+  /* Clear SYSCLKSEL[1:0] bits */
+  tmpreg &= ~RCC_CFG_SYSCLKSEL;
+  /* Set SYSCLKSEL[1:0] bits according to RCC_SYSCLKSelect value */
+  tmpreg |= RCC_SYSCLKSelect;
+  /* Store the new value */
+  RCC->CFG = tmpreg;
+}
+
+/**
+  * @brief  Returns the clock source used as system clock.
+  * @param  None
+  * @retval The clock source used as system clock. The returned value can
+  *   be one of the following:
+  *     - 0x00: HSI used as system clock
+  *     - 0x04: HSE used as system clock
+  *     - 0x08: PLL used as system clock
+  */
+uint8_t RCC_GetSYSCLKSelction(void)
+{
+  return ((uint8_t)(RCC->CFG & RCC_CFG_SYSCLKSTS));
+}
+
+/**
+  * @brief  Configures the AHB clock (HCLK).
+  * @param  RCC_SYSCLK_Div: defines the AHB clock divider. This clock is derived from
+  *   the system clock (SYSCLK).
+  *   This parameter can be one of the following values:
+  *     @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
+  *     @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
+  *     @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
+  *     @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
+  *     @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
+  *     @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
+  *     @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+  *     @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+  *     @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+  * @retval None
+  */
+void RCC_AHBCLKConfig(uint32_t RCC_SYSCLK_Div)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_RCC_AHBCLK(RCC_SYSCLK_Div));
+  tmpreg = RCC->CFG;
+  /* Clear AHBPSC[3:0] bits */
+  tmpreg &= ~RCC_CFG_AHBPSC;
+  /* Set AHBPSC[3:0] bits according to RCC_SYSCLK_Div value */
+  tmpreg |= RCC_SYSCLK_Div;
+  /* Store the new value */
+  RCC->CFG = tmpreg;
+}
+
+/**
+  * @brief  Configures the Low Speed APB clock (PCLK1).
+  * @param  RCC_HCLK_Div: defines the APB1 clock divider. This clock is derived from
+  *   the AHB clock (HCLK).
+  *   This parameter can be one of the following values:
+  *     @arg RCC_AHBCLK_Div1: APB1 clock = HCLK
+  *     @arg RCC_AHBCLK_Div2: APB1 clock = HCLK/2
+  *     @arg RCC_AHBCLK_Div4: APB1 clock = HCLK/4
+  *     @arg RCC_AHBCLK_Div8: APB1 clock = HCLK/8
+  *     @arg RCC_AHBCLK_Div16: APB1 clock = HCLK/16
+  * @retval None
+  */
+void RCC_APB1CLKConfig(uint32_t RCC_HCLK_Div)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_RCC_APBCLK(RCC_HCLK_Div));
+  tmpreg = RCC->CFG;
+  /* Clear APB1PSC[2:0] bits */
+  tmpreg &= ~RCC_CFG_APB1PSC;
+  /* Set APB1PSC[2:0] bits according to RCC_HCLK_Div value */
+  tmpreg |= RCC_HCLK_Div;
+  /* Store the new value */
+  RCC->CFG = tmpreg;
+}
+
+/**
+  * @brief  Configures the High Speed APB clock (PCLK2).
+  * @param  RCC_HCLK_Div: defines the APB2 clock divider. This clock is derived from
+  *   the AHB clock (HCLK).
+  *   This parameter can be one of the following values:
+  *     @arg RCC_AHBCLK_Div1: APB2 clock = HCLK
+  *     @arg RCC_AHBCLK_Div2: APB2 clock = HCLK/2
+  *     @arg RCC_AHBCLK_Div4: APB2 clock = HCLK/4
+  *     @arg RCC_AHBCLK_Div8: APB2 clock = HCLK/8
+  *     @arg RCC_AHBCLK_Div16: APB2 clock = HCLK/16
+  * @retval None
+  */
+void RCC_APB2CLKConfig(uint32_t RCC_HCLK_Div)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_RCC_APBCLK(RCC_HCLK_Div));
+  tmpreg = RCC->CFG;
+  /* Clear APB2PSC[2:0] bits */
+  tmpreg &= ~RCC_CFG_APB2PSC;
+  /* Set APB2PSC[2:0] bits according to RCC_HCLK_Div value */
+  tmpreg |= RCC_HCLK_Div << 3;
+  /* Store the new value */
+  RCC->CFG = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the specified RCC interrupts.
+  * @param  RCC_INT: specifies the RCC interrupt sources to be enabled or disabled.
+  *   this parameter can be any combination of the following values.
+  *     @arg RCC_INT_LSISTBL: LSI ready interrupt
+  *     @arg RCC_INT_LSESTBL: LSE ready interrupt
+  *     @arg RCC_INT_HSISTBL: HSI ready interrupt
+  *     @arg RCC_INT_HSESTBL: HSE ready interrupt
+  *     @arg RCC_INT_PLLSTBL: PLL ready interrupt
+  *
+  * @param  NewState: new state of the specified RCC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_INTConfig(uint8_t RCC_INT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_INT_EN(RCC_INT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Perform Byte access to RCC_CLKINT bits to enable the selected interrupts */
+    *(__IO uint8_t *) CLKINT_BYTE2_EN_ADDR |= RCC_INT;
+  }
+  else
+  {
+    /* Perform Byte access to RCC_CLKINT bits to disable the selected interrupts */
+    *(__IO uint8_t *) CLKINT_BYTE2_EN_ADDR &= (uint8_t)~RCC_INT;
+  }
+}
+
+/**
+  * @brief  Configures the USB clock (USBCLK).
+  * @param  RCC_USBCLKSelect: specifies the USB clock source. This clock is
+  *   derived from the PLL output.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_USBCLKSelection_PLL_Div1_5:  PLL clock divided by 1.5 selected as USB clock source
+  *     @arg RCC_USBCLKSelection_PLL_Div1:    PLL clock selected as USB clock source
+  *     @arg RCC_USBCLKSelection_PLL_Div2_5:  PLL clock divided by 2.5 selected as USB clock source
+  *     @arg RCC_USBCLKSelection_PLL_Div2:    PLL clock divided by 2 selected as USB clock source
+  *     @arg RCC_USBCLKSelection_PLL_Div3_5:  PLL clock divided by 3.5 selected as USB clock source
+  *     @arg RCC_USBCLKSelection_PLL_Div3:    PLL clock divided by 3 selected as USB clock source
+  *     @arg RCC_USBCLKSelection_PLL_Div4:    PLL clock divided by 4 selected as USB clock source
+  * @retval None
+  */
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSelect)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_USBCLK_CFG(RCC_USBCLKSelect));
+
+  tmpreg = RCC->CFG;
+  /* Clear USBPSC[2:0] bits */
+  tmpreg &= ~RCC_CFG_USBPSC;
+  /* Set USBPSC[2:0] bits according to RCC_USBCLKSelect value */
+  tmpreg |= RCC_USBCLKSelect;
+  /* Store the new value */
+  RCC->CFG = tmpreg;
+}
+
+/**
+  * @brief  Configures the ADC clock (ADCCLK).
+  * @param  RCC_PCLK2_Div: defines the ADC clock divider. This clock is derived from
+  *   the APB2 clock (PCLK2).
+  *   This parameter can be one of the following values:
+  *     @arg RCC_APB2CLK_Div2:  ADC clock = PCLK2/2
+  *     @arg RCC_APB2CLK_Div4:  ADC clock = PCLK2/4
+  *     @arg RCC_APB2CLK_Div6:  ADC clock = PCLK2/6
+  *     @arg RCC_APB2CLK_Div8:  ADC clock = PCLK2/8
+  *     @arg RCC_APB2CLK_Div12: ADC clock = PCLK2/12
+  *     @arg RCC_APB2CLK_Div16: ADC clock = PCLK2/16
+  * @retval None
+  */
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2_Div)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_RCC_ADCCLK(RCC_PCLK2_Div));
+  tmpreg = RCC->CFG;
+  /* Clear ADCPSC[2:0] bits */
+  tmpreg &= CFG_ADCPSC_Rst_Mask;
+  /* Set ADCPSC[2:0] bits according to RCC_PCLK2_Div value */
+  tmpreg |= RCC_PCLK2_Div;
+  /* Store the new value */
+  RCC->CFG = tmpreg;
+}
+
+/**
+  * @brief  Configures the External Low Speed oscillator (LSE).
+  * @param  RCC_LSE: specifies the new state of the LSE.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_LSE_DISABLE: LSE oscillator OFF
+  *     @arg RCC_LSE_ENABLE:  LSE oscillator ON
+  *     @arg RCC_LSE_BYPASS:  LSE oscillator bypassed with external clock
+  * @retval None  
+  */
+void RCC_LSEConfig(uint8_t RCC_LSE)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_LSE(RCC_LSE));
+  /* Reset LSEEN and LSEBYPS bits before configuring the LSE ------------------*/
+  /* Reset LSEEN bit */
+  *(__IO uint8_t *) BDC_BYTE0_LSE_ADDR = RCC_LSE_DISABLE;
+  /* Reset LSEBYPS bit */
+  *(__IO uint8_t *) BDC_BYTE0_LSE_ADDR = RCC_LSE_DISABLE;
+
+  /* Configure LSE (RCC_LSE_DISABLE is already covered by the code section above) */
+  switch(RCC_LSE)
+  {
+  case RCC_LSE_ENABLE:
+    /* Set LSEEN bit */
+    *(__IO uint8_t *) BDC_BYTE0_LSE_ADDR = RCC_LSE_ENABLE;
+    break;
+
+  case RCC_LSE_BYPASS:
+    /* Set LSEBYPS and LSEEN bits */
+    *(__IO uint8_t *) BDC_BYTE0_LSE_ADDR = RCC_LSE_BYPASS | RCC_LSE_ENABLE;
+    break;
+
+  default:
+    break;
+  }
+}
+
+/**
+  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
+  * @note   LSI can not be disabled if the IWDG is running.
+  * @param  NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_LSICmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CTRLSTS_LSIEN_BB = (uint32_t)NewState;
+}
+
+#if defined (AT32F415xx)
+/**
+  * @brief  Configures the ERTC clock (ERTCCLK).
+  * @note   Once the ERTC clock is selected it can't be changed unless the Backup domain is reset.
+  * @param  RCC_ERTCCLKSelect: specifies the ERTC clock source.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_ERTCCLKSelection_LSE: LSE selected as ERTC clock
+  *     @arg RCC_ERTCCLKSelection_LSI: LSI selected as ERTC clock
+  *     @arg RCC_ERTCCLKSelection_HSE_Div128: HSE clock divided by 128 selected as ERTC clock
+  * @retval None
+  */
+void RCC_ERTCCLKConfig(uint32_t RCC_ERTCCLKSelect)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_ERTCCLK_SEL(RCC_ERTCCLKSelect));
+  /* Select the RTC clock source */
+  RCC->BDC |= RCC_ERTCCLKSelect;
+}
+#else
+/**
+  * @brief  Configures the RTC clock (RTCCLK).
+  * @note   Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
+  * @param  RCC_RTCCLKSelect: specifies the RTC clock source.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_RTCCLKSelection_LSE: LSE selected as RTC clock
+  *     @arg RCC_RTCCLKSelection_LSI: LSI selected as RTC clock
+  *     @arg RCC_RTCCLKSelection_HSE_Div128: HSE clock divided by 128 selected as RTC clock
+  * @retval None
+  */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSelect)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_RTCCLK_SEL(RCC_RTCCLKSelect));
+  /* Select the RTC clock source */
+  RCC->BDC |= RCC_RTCCLKSelect;
+}
+#endif
+
+#if defined (AT32F415xx)
+/**
+  * @brief  Enables or disables the ERTC clock.
+  * @note   This function must be used only after the ERTC clock was selected using the RCC_ERTCCLKConfig function.
+  * @param  NewState: new state of the ERTC clock. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_ERTCCLKCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) BDC_ERTCEN_BB = (uint32_t)NewState;
+}
+#else
+/**
+  * @brief  Enables or disables the RTC clock.
+  * @note   This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
+  * @param  NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) BDC_RTCEN_BB = (uint32_t)NewState;
+}
+#endif
+/**
+  * @brief  Returns the frequencies of different on chip clocks.
+  * @param  RCC_Clocks: pointer to a RCC_ClockType structure which will hold
+  *         the clocks frequencies.
+  * @note   The result of this function could be not correct when using
+  *         fractional value for HSE crystal.
+  * @retval None
+  */
+void RCC_GetClocksFreq(RCC_ClockType* RCC_Clocks)
+{
+#if defined (AT32F415xx)
+  uint32_t pllcfgen = 0, pllfref = 0, pllns = 0, pllms = 0, pllfr = 0;
+  uint32_t retfref = 0, retfr = 0; 
+#endif
+  uint32_t tmp = 0, pllmult = 0, pllrefclk = 0, psc = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFG & RCC_CFG_SYSCLKSTS;
+
+  switch (tmp)
+  {
+  case 0x00:  /* HSI used as system clock */
+    RCC_Clocks->SYSCLK_Freq = HSI_VALUE;
+    break;
+
+  case 0x04:  /* HSE used as system clock */
+    RCC_Clocks->SYSCLK_Freq = HSE_VALUE;
+    break;
+
+  case 0x08:  /* PLL used as system clock */
+#if defined (AT32F415xx)
+    /* Get_ClocksFreq for PLLconfig2 */
+    pllcfgen = BIT_READ(RCC->PLL, PLL_CFGEN_MASK);
+
+    if(pllcfgen == PLL_CFGEN_ENABLE)
+    {
+      pllfref = BIT_READ(RCC->PLL, PLL_FREF_MASK);
+      pllns = BIT_READ(RCC->PLL, PLL_NS_MASK);
+      pllms = BIT_READ(RCC->PLL, PLL_MS_MASK);
+      pllfr = BIT_READ(RCC->PLL, PLL_FR_MASK);
+
+      RCC_FREF_VALUE(pllfref, retfref);
+      RCC_FR_VALUE(pllfr, retfr);
+
+      RCC_Clocks->SYSCLK_Freq = (retfref * (pllns >> PLL_NS_POS)) / \
+      ((pllms >> PLL_MS_POS) * retfr) * 1000000;
+    }else
+#endif
+    {
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmult = BIT_READ(RCC->CFG, RCC_CFG_PLLMULT);
+      pllrefclk = RCC->CFG & RCC_CFG_PLLRC;
+      pllmult = RCC_GET_PLLMULT(pllmult);
+  
+      if (pllrefclk == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        RCC_Clocks->SYSCLK_Freq = (HSI_VALUE >> 1) * pllmult;
+      }
+      else
+      {
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFG & RCC_CFG_PLLHSEPSC) != (uint32_t)RESET)
+        {
+          /* HSE oscillator clock divided by 2 */
+          RCC_Clocks->SYSCLK_Freq = (HSE_VALUE >> 1) * pllmult;
+        }
+        else
+        {
+          RCC_Clocks->SYSCLK_Freq = HSE_VALUE * pllmult;
+        }
+      }
+    }
+#if !defined (AT32F415xx)
+    if (((RCC->CFG & RCC_CFG_PLLRANGE) == 0) && (RCC_Clocks->SYSCLK_Freq > RCC_PLL_RANGE))
+    {
+      /* Not setup PLLRANGE, fixed in 72 MHz */
+      RCC_Clocks->SYSCLK_Freq = RCC_PLL_RANGE;
+    }
+#endif
+    break;
+
+  default:
+    RCC_Clocks->SYSCLK_Freq = HSI_VALUE;
+    break;
+  }
+
+  /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
+  /* Get HCLK prescaler */
+  tmp = (RCC->CFG & (RCC_CFG_AHBPSC ^ RCC_CFG_AHBPSC_3)) >> 4;
+  psc = (RCC->CFG & RCC_CFG_AHBPSC_3) ? APBAHBPscTable[tmp] : 0;
+
+  /* HCLK clock frequency */
+  RCC_Clocks->AHBCLK_Freq = RCC_Clocks->SYSCLK_Freq >> psc;
+  /* Get PCLK1 prescaler */
+  tmp = (RCC->CFG & (RCC_CFG_APB1PSC ^ RCC_CFG_APB1PSC_2)) >> 8;
+  psc = (RCC->CFG & RCC_CFG_APB1PSC_2) ? APBAHBPscTable[tmp] : 0;
+  /* PCLK1 clock frequency */
+  RCC_Clocks->APB1CLK_Freq = RCC_Clocks->AHBCLK_Freq >> psc;
+  /* Get PCLK2 prescaler */
+  tmp = (RCC->CFG & (RCC_CFG_APB2PSC ^ RCC_CFG_APB2PSC_2)) >> 11;
+  psc = (RCC->CFG & RCC_CFG_APB2PSC_2) ? APBAHBPscTable[tmp] : 0;
+  /* PCLK2 clock frequency */
+  RCC_Clocks->APB2CLK_Freq = RCC_Clocks->AHBCLK_Freq >> psc;
+
+  /* Get ADCCLK prescaler */
+  tmp = (RCC->CFG & CFG_ADCPSC_Set_Mask) >> CFG_ADCPSC_Pos;
+
+  if (RCC->CFG & CFG_ADCPSCBit2_Set_Mask)
+  {
+    tmp |= CFG_ADCPSCBit2_IdxMask;
+  }
+
+  psc = ADCPscTable[tmp];
+  /* ADCCLK clock frequency */
+  RCC_Clocks->ADCCLK_Freq = RCC_Clocks->APB2CLK_Freq / psc;
+}
+
+/**
+  * @brief  Enables or disables the AHB peripheral clock.
+  * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
+  *   This parameter can be any combination of the
+  *   following values:
+  *     @arg RCC_AHBPERIPH_DMA1
+  *     @arg RCC_AHBPERIPH_DMA2
+  *     @arg RCC_AHBPERIPH_SRAM
+  *     @arg RCC_AHBPERIPH_FLASH
+  *     @arg RCC_AHBPERIPH_CRC
+  *     @arg RCC_AHBPERIPH_XMC
+  *     @arg RCC_AHBPERIPH_SDIO1
+  *     @arg RCC_AHBPERIPH_SDIO2
+  *
+  * @note SRAM and FLASH clock can be disabled only during sleep mode.
+  * @param  NewState: new state of the specified peripheral clock.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->AHBEN |= RCC_AHBPeriph;
+  }
+  else
+  {
+    RCC->AHBEN &= ~RCC_AHBPeriph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
+  *   This parameter can be any combination of the following values:
+  *     @arg RCC_APB2PERIPH_AFIO,   RCC_APB2PERIPH_GPIOA,   RCC_APB2PERIPH_GPIOB,
+  *          RCC_APB2PERIPH_GPIOC,  RCC_APB2PERIPH_GPIOD,   RCC_APB2PERIPH_GPIOE,
+  *          RCC_APB2PERIPH_GPIOF,  RCC_APB2PERIPH_GPIOG,   RCC_APB2PERIPH_ADC1,
+  *          RCC_APB2PERIPH_ADC2,   RCC_APB2PERIPH_TMR1,    RCC_APB2PERIPH_SPI1,
+  *          RCC_APB2PERIPH_TMR8,   RCC_APB2PERIPH_USART1,  RCC_APB2PERIPH_ADC3,
+  *          RCC_APB2PERIPH_TMR15,  RCC_APB2PERIPH_TMR9,    RCC_APB2PERIPH_TMR10,
+  *          RCC_APB2PERIPH_TMR11
+  * @param  NewState: new state of the specified peripheral clock.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB2EN |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2EN &= ~RCC_APB2Periph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
+  *   This parameter can be any combination of the following values:
+  *     @arg RCC_APB1PERIPH_TMR2,   RCC_APB1PERIPH_TMR3,   RCC_APB1PERIPH_TMR4,
+  *          RCC_APB1PERIPH_TMR5,   RCC_APB1PERIPH_TMR6,   RCC_APB1PERIPH_TMR7,
+  *          RCC_APB1PERIPH_WWDG,   RCC_APB1PERIPH_SPI2,   RCC_APB1PERIPH_SPI3,
+  *          RCC_APB1PERIPH_SPI4,   RCC_APB1PERIPH_USART2, RCC_APB1PERIPH_USART3,
+  *          RCC_APB1Periph_USART4, RCC_APB1Periph_USART5, RCC_APB1PERIPH_I2C1,
+  *          RCC_APB1PERIPH_I2C2,   RCC_APB1PERIPH_I2C3,   RCC_APB1PERIPH_USB,
+  *          RCC_APB1PERIPH_CAN1,   RCC_APB1PERIPH_BKP,    RCC_APB1PERIPH_PWR,
+  *          RCC_APB1PERIPH_DAC,    RCC_APB1PERIPH_TMR12,  RCC_APB1PERIPH_TMR13,
+  *          RCC_APB1PERIPH_TMR14
+  * @param  NewState: new state of the specified peripheral clock.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB1EN |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1EN &= ~RCC_APB1Periph;
+  }
+}
+
+#if defined (AT32F403Axx) || defined (AT32F407xx)
+/**
+  * @brief  Forces or releases High Speed AHB Bus reset.
+  * @param  RCC_AHBPeriph: specifies the AHB peripheral to reset.
+  *   This parameter can be any combination of the following values:
+  *     @arg RCC_AHBPERIPH_ETHMAC
+  * @param  NewState: new state of the specified peripheral reset.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->AHBRST |= RCC_AHBPeriph;
+  }
+  else
+  {
+    RCC->AHBRST &= ~RCC_AHBPeriph;
+  }
+}
+#endif
+
+/**
+  * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
+  *   This parameter can be any combination of the following values:
+  *     @arg RCC_APB2PERIPH_AFIO,  RCC_APB2PERIPH_GPIOA,  RCC_APB2PERIPH_GPIOB,
+  *          RCC_APB2PERIPH_GPIOC, RCC_APB2PERIPH_GPIOD,  RCC_APB2PERIPH_GPIOE,
+  *          RCC_APB2PERIPH_GPIOF, RCC_APB2PERIPH_GPIOG,  RCC_APB2PERIPH_ADC1,
+  *          RCC_APB2PERIPH_ADC2,  RCC_APB2PERIPH_TMR1,   RCC_APB2PERIPH_SPI1,
+  *          RCC_APB2PERIPH_TMR8,  RCC_APB2PERIPH_USART1, RCC_APB2PERIPH_ADC3,
+  *          RCC_APB2PERIPH_TMR15, RCC_APB2PERIPH_TMR9,   RCC_APB2PERIPH_TMR10,
+  *          RCC_APB2PERIPH_TMR11
+  * @param  NewState: new state of the specified peripheral reset.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB2RST |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2RST &= ~RCC_APB2Periph;
+  }
+}
+
+/**
+  * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
+  *   This parameter can be any combination of the following values:
+  *     @arg RCC_APB1PERIPH_TMR2,   RCC_APB1PERIPH_TMR3,   RCC_APB1PERIPH_TMR4,
+  *          RCC_APB1PERIPH_TMR5,   RCC_APB1PERIPH_TMR6,   RCC_APB1PERIPH_TMR7,
+  *          RCC_APB1PERIPH_WWDG,   RCC_APB1PERIPH_SPI2,   RCC_APB1PERIPH_SPI3,
+  *          RCC_APB1PERIPH_SPI4,   RCC_APB1PERIPH_USART2, RCC_APB1PERIPH_USART3,
+  *          RCC_APB1Periph_USART4, RCC_APB1Periph_USART5, RCC_APB1PERIPH_I2C1,
+  *          RCC_APB1PERIPH_I2C2,   RCC_APB1PERIPH_I2C3,   RCC_APB1PERIPH_USB,
+  *          RCC_APB1PERIPH_CAN1,   RCC_APB1PERIPH_BKP,    RCC_APB1PERIPH_PWR,
+  *          RCC_APB1PERIPH_DAC,    RCC_APB1PERIPH_TMR12,  RCC_APB1PERIPH_TMR13,
+  *          RCC_APB1PERIPH_TMR14
+  * @param  NewState: new state of the specified peripheral clock.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB1RST |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1RST &= ~RCC_APB1Periph;
+  }
+}
+
+/**
+  * @brief  Forces or releases the Backup domain reset.
+  * @param  NewState: new state of the Backup domain reset.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) BDC_BDRST_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the Clock Security System.
+  * @param  NewState: new state of the Clock Security System..
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_HSEClockFailureDetectorCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CTRL_HSECFDEN_BB = (uint32_t)NewState;
+}
+
+#if defined (AT32F403xx)
+/**
+  * @brief  Selects the clock source to output on CLKOUT pin.
+  * @param  RCC_CLKOUT: specifies the clock source to output.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_CLKOUT_NOCLK:    No clock selected
+  *     @arg RCC_CLKOUT_SYSCLK:   System clock selected
+  *     @arg RCC_CLKOUT_HSI:      HSI oscillator clock selected
+  *     @arg RCC_CLKOUT_HSE:      HSE oscillator clock selected
+  *     @arg RCC_CLKOUT_PLL_Div2: PLL clock divided by 2 selected
+  *     @arg RCC_CLKOUT_PLL_Div4: PLL clock divided by 4 selected
+  *     @arg RCC_CLKOUT_USB:      USB clock selected
+  *     @arg RCC_CLKOUT_ADC:      ADC clock selected
+  * @retval None
+  */
+void RCC_CLKOUTConfig(uint32_t RCC_CLKOUT)
+{
+    uint32_t tmpreg = 0;
+
+		/* Check the parameters */
+		assert_param(IS_RCC_CLKOUT(RCC_CLKOUT));
+
+    if((RCC_CLKOUT >> 28) == 0)
+		{
+			// Clear CLKOUT[3];
+			RCC->MISC &= ~RCC_MISC_CLKOUT_3;
+
+			tmpreg = RCC->CFG;
+			/* Clear CLKOUT[2:0] bits */
+			tmpreg &= ~RCC_CFG_CLKOUT;
+			/* Set CLKOUT[2:0] bits according to RCC_CLKOUT value */
+			tmpreg |= RCC_CLKOUT;
+			/* Store the new value */
+			RCC->CFG = tmpreg;
+		}
+		else if((RCC_CLKOUT >> 28) == 1)
+		{
+			// Set CLKOUT[3];
+			RCC->MISC &= ~RCC_MISC_CLKOUT_3;
+			RCC->MISC |= RCC_MISC_CLKOUT_3;
+
+			tmpreg = RCC->CFG;
+			/* Clear CLKOUT[2:0] bits */
+			tmpreg &= ~RCC_CFG_CLKOUT;
+			/* Set CLKOUT[2:0] bits according to RCC_CLKOUT value */
+			tmpreg |= (RCC_CLKOUT & 0xFFFFFFF);
+			/* Store the new value */
+			RCC->CFG = tmpreg;
+		}
+}
+#else
+/**
+  * @brief  Selects the clock source to output on CLKOUT pin.
+  * @param  RCC_CLKOUT: specifies the clock source to output.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_CLKOUT_NOCLK:    No clock selected
+  *     @arg RCC_CLKOUT_SYSCLK:   System clock selected
+  *     @arg RCC_CLKOUT_HSI:      HSI oscillator clock selected
+  *     @arg RCC_CLKOUT_HSE:      HSE oscillator clock selected
+  *     @arg RCC_CLKOUT_PLL_Div2: PLL clock divided by 2 selected
+  *     @arg RCC_CLKOUT_PLL_Div4: PLL clock divided by 4 selected
+  *     @arg RCC_CLKOUT_USB:      USB clock selected
+  *     @arg RCC_CLKOUT_ADC:      ADC clock selected
+  * @note Just only at32f413xx & at32f415xx
+  *     @arg RCC_CLKOUT_LSI:      LSI clock selected
+  *     @arg RCC_CLKOUT_LSE:      LSE clock selected
+  * @param  RCC_CLKOUTPRE: specifies the clock output prescaler.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_MCOPRE_1  : division by 1 applied to CLKOUT clock
+  *     @arg RCC_MCOPRE_2  : division by 2 applied to CLKOUT clock
+  *     @arg RCC_MCOPRE_4  : division by 4 applied to CLKOUT clock
+  *     @arg RCC_MCOPRE_8  : division by 8 applied to CLKOUT clock
+  *     @arg RCC_MCOPRE_16 : division by 16 applied to CLKOUT clock
+  *     @arg RCC_MCOPRE_64 : division by 64 applied to CLKOUT clock
+  *     @arg RCC_MCOPRE_128: division by 128 applied to CLKOUT clock
+  *     @arg RCC_MCOPRE_256: division by 256 applied to CLKOUT clock
+  *     @arg RCC_MCOPRE_512: division by 512 applied to CLKOUT clock
+  * @retval None
+  */
+void RCC_CLKOUTConfig(uint32_t RCC_CLKOUT, uint32_t RCC_CLKOUTPRE)
+{
+    uint32_t tmpreg = 0;
+
+		/* Check the parameters */
+		assert_param(IS_RCC_CLKOUT(RCC_CLKOUT));
+    assert_param(IS_RCC_MCO(RCC_CLKOUTPRE));
+  
+    /* Config MCOPRE */
+    RCC->MISC &= ~RCC_MCOPRE_MASK;
+    RCC->MISC |= RCC_CLKOUTPRE;
+
+    if((RCC_CLKOUT >> 28) == 0)
+		{
+			// Clear CLKOUT[3];
+			RCC->MISC &= ~RCC_MISC_CLKOUT_3;
+
+			tmpreg = RCC->CFG;
+			/* Clear CLKOUT[2:0] bits */
+			tmpreg &= ~RCC_CFG_CLKOUT;
+			/* Set CLKOUT[2:0] bits according to RCC_CLKOUT value */
+			tmpreg |= RCC_CLKOUT;
+			/* Store the new value */
+			RCC->CFG = tmpreg;
+		}
+		else if((RCC_CLKOUT >> 28) == 1)
+		{
+			// Set CLKOUT[3];
+			RCC->MISC &= ~RCC_MISC_CLKOUT_3;
+			RCC->MISC |= RCC_MISC_CLKOUT_3;
+
+			tmpreg = RCC->CFG;
+			/* Clear CLKOUT[2:0] bits */
+			tmpreg &= ~RCC_CFG_CLKOUT;
+			/* Set CLKOUT[2:0] bits according to RCC_CLKOUT value */
+			tmpreg |= (RCC_CLKOUT & 0xFFFFFFF);
+			/* Store the new value */
+			RCC->CFG = tmpreg;
+		}
+}
+#endif
+/**
+  * @brief  Checks whether the specified RCC flag is set or not.
+  * @param  RCC_Flag: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_FLAG_HSISTBL:  HSI oscillator clock ready
+  *     @arg RCC_FLAG_HSESTBL:  HSE oscillator clock ready
+  *     @arg RCC_FLAG_PLLSTBL:  PLL clock ready
+  *     @arg RCC_FLAG_LSESTBL:  LSE oscillator clock ready
+  *     @arg RCC_FLAG_LSISTBL:  LSI oscillator clock ready
+  *     @arg RCC_FLAG_PINRST:   Pin reset
+  *     @arg RCC_FLAG_PORST:    POR/PDR reset
+  *     @arg RCC_FLAG_SWRST:    Software reset
+  *     @arg RCC_FLAG_IWDGRST:  Independent Watchdog reset
+  *     @arg RCC_FLAG_WWDGRST:  Window Watchdog reset
+  *     @arg RCC_FLAG_LPRST:    Low Power reset
+  *
+  * @retval The new state of RCC_Flag (SET or RESET).
+  */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_Flag)
+{
+  uint32_t tmp = 0;
+  uint32_t statusreg = 0;
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_RCC_FLAG(RCC_Flag));
+
+  /* Get the RCC register index */
+  tmp = RCC_Flag >> 5;
+
+  if (tmp == 1)               /* The flag to check is in CTRL register */
+  {
+    statusreg = RCC->CTRL;
+  }
+  else if (tmp == 2)          /* The flag to check is in BDC register */
+  {
+    statusreg = RCC->BDC;
+  }
+  else                       /* The flag to check is in CTRLSTS register */
+  {
+    statusreg = RCC->CTRLSTS;
+  }
+
+  /* Get the flag position */
+  tmp = RCC_Flag & FLAG_Mask;
+
+  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RCC reset flags.
+  * @note   The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORST, RCC_FLAG_SWRST,
+  *   RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPRST
+  * @param  None
+  * @retval None
+  */
+void RCC_ClearFlag(void)
+{
+  /* Set RSTFC bit to clear the reset flags */
+  RCC->CTRLSTS |= RCC_CTRLSTS_RSTFC;
+}
+
+/**
+  * @brief  Checks whether the specified RCC interrupt has occurred or not.
+  * @param  RCC_INT: specifies the RCC interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_INT_LSISTBL: LSI ready interrupt
+  *     @arg RCC_INT_LSESTBL: LSE ready interrupt
+  *     @arg RCC_INT_HSISTBL: HSI ready interrupt
+  *     @arg RCC_INT_HSESTBL: HSE ready interrupt
+  *     @arg RCC_INT_PLLSTBL: PLL ready interrupt
+  *     @arg RCC_INT_HSECFD:  Clock Security System interrupt
+  *
+  * @retval The new state of RCC_INT (SET or RESET).
+  */
+ITStatus RCC_GetINTStatus(uint8_t RCC_INT)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_RCC_INT_STS(RCC_INT));
+
+  /* Check the status of the specified RCC interrupt */
+  if ((RCC->CLKINT & RCC_INT) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  /* Return the RCC_INT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the RCC's interrupt pending bits.
+  * @param  RCC_INT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the
+  *   following values:
+  *     @arg RCC_INT_LSISTBL: LSI ready interrupt
+  *     @arg RCC_INT_LSESTBL: LSE ready interrupt
+  *     @arg RCC_INT_HSISTBL: HSI ready interrupt
+  *     @arg RCC_INT_HSESTBL: HSE ready interrupt
+  *     @arg RCC_INT_PLLSTBL: PLL ready interrupt
+  *
+  *     @arg RCC_INT_HSECFD: Clock Security System interrupt
+  * @retval None
+  */
+void RCC_ClearINTPendingBit(uint8_t RCC_INT)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_INT_CLR(RCC_INT));
+
+  /* Perform Byte access to RCC_CLKINT[23:16] bits to clear the selected interrupt
+     pending bits */
+  *(__IO uint8_t *) CLKINT_BYTE3_CLR_ADDR = RCC_INT;
+}
+
+/**
+  * @brief  Delay After HSE Enable,.
+  * @param  delay: Number Of Nops.
+  * @retval None
+  */
+static void RCC_HSEENDelay(uint32_t delay)
+{
+  uint32_t i;
+
+  for(i = 0; i < delay; i++)
+    ;
+}
+
+#if defined (AT32F413xx) || defined (AT32F415xx) || \
+    defined (AT32F403Axx)|| defined (AT32F407xx)
+/**
+  * @brief  Enables or disables the Auto Step Mode.
+  * @note   This function called when sysclk greater than 108Mhz.
+  * @param  NewState: new state of the Step Mode. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_StepModeCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if(ENABLE == NewState)
+	{
+    RCC->MISC2 |= RCC_MISC2_AUTO_STEP_EN;
+	}
+	else
+	{
+    RCC->MISC2 &= ~RCC_MISC2_AUTO_STEP_EN;
+	}
+}
+
+/**
+  * @brief  Enables or disables to get USB clock source from HSI 48M directly.
+  * @note   Attention: If enable, the hsi clock frequency also has fixed 48M.
+  * @param  NewState: new state of the USB clock source. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_HSI2USB48M(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if(ENABLE == NewState)
+	{
+    RCC->MISC  |= RCC_MISC_HSI_DIV_EN;
+    RCC->MISC2 |= RCC_MISC2_HSI_FOR_USB;
+	}
+	else
+	{
+    RCC->MISC  &= ~RCC_MISC_HSI_DIV_EN;
+    RCC->MISC2 &= ~RCC_MISC2_HSI_FOR_USB;
+	}
+}
+#endif
+
+#if defined (AT32F403Axx)|| defined (AT32F407xx)
+/**
+  * @brief  HSE Divider configura.
+  * @note   This function config HSE divider.
+  * @param  HSEDiv: RCC_HSE_DIV_2. HSE divider 2 for pll.
+  *                 RCC_HSE_DIV_3. HSE divider 3 for pll.
+  *                 RCC_HSE_DIV_4. HSE divider 4 for pll.
+  *                 RCC_HSE_DIV_5. HSE divider 5 for pll.
+  * @retval None
+  */
+void RCC_HSEDivConfig(uint32_t HSEDiv)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_HSEDIV(HSEDiv));
+
+  RCC->MISC2 &= ~RCC_HSE_DIV_MASK;
+  RCC->MISC2 |= HSEDiv;
+}
+#endif
+
+#if defined (AT32F413xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+/**
+  * @brief  Enables or disables the USB INT remap.
+  * @note   Remap the default USB_HP_IRQn & USB_LP_IRQn (19,20) to other IRQns(73, 74).
+  * @param  NewState: new state of the USB INT remap. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_USBINTRemap(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if(ENABLE == NewState)
+	{
+    RCC->INTCTRL |= RCC_INTCTRL_USB_INT_CTRL;
+	}
+	else
+	{
+    RCC->INTCTRL &= ~RCC_INTCTRL_USB_INT_CTRL;
+	}
+}
+
+/**
+  * @brief  Enables or disables MCO output to TMR10_CH0.
+  * @note   This function can enable MCO inner connect to TMR10_CH0.
+  * @param  NewState: new state of the MCO to TMR10_CH0. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_MCO2TMR10(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if(ENABLE == NewState)
+	{
+    RCC->TEST  |= RCC_TEST_MCO2TMR_EN;
+	}
+	else
+	{
+    RCC->TEST  &= ~RCC_TEST_MCO2TMR_EN;
+	}
+}
+#endif
+
+#if defined (AT32F415xx)
+/**
+  * @brief  Config pll with RCC_PLL.
+  * @note   This function can usd RCC_PLL register to config pll, not RCC_CFG_MULT.
+  *                        PLL_freq_n_Mhz * PLL_ns
+  *         PLL clock = -------------------------------
+  *                           PLL_ms * PLL_fr_n
+  *         ATTEMTION:
+  *                  31 <= PLL_ns <= 500
+  *                  1  <= PLL_ms <= 15
+  *
+  *                       PLL_freq_n_Mhz * PLL_ns
+  *         500Mhz <=  ------------------------------ <= 1000Mhz
+  *                               PLL_ms
+  * @param  PLL_fref: The freqence of PLL source clock.
+  *     @arg PLL_FREF_4M :  reference clock 4Mhz
+  *     @arg PLL_FREF_6M :  reference clock 6Mhz
+  *     @arg PLL_FREF_8M :  reference clock 8Mhz
+  *     @arg PLL_FREF_12M:  reference clock 12Mhz
+  *     @arg PLL_FREF_16M:  reference clock 16Mhz
+  *     @arg PLL_FREF_25M:  reference clock 25Mhz
+  * @param  PLL_ns: PLL register ns value.
+  * @param  PLL_ms: PLL register ms value.
+  * @param  PLL_fr: VCO output divider
+  *     @arg PLL_FR_1 :  output divider 1
+  *     @arg PLL_FR_2 :  output divider 2
+  *     @arg PLL_FR_4 :  output divider 4
+  *     @arg PLL_FR_8 :  output divider 8
+  *     @arg PLL_FR_16:  output divider 16
+  *     @arg PLL_FR_32:  output divider 32
+  * @retval None
+  */
+void RCC_PLLconfig2(uint32_t PLL_fref, uint32_t PLL_ns, uint32_t PLL_ms, uint32_t PLL_fr)
+{
+	volatile uint32_t result = 0;
+  uint32_t pll_reg = 0, ret = 0;
+
+  assert_param(IS_RCC_FR(PLL_fr));
+  assert_param(IS_RCC_FREF(PLL_fref));
+  assert_param(IS_RCC_NS_VALUE(PLL_ns));
+  assert_param(IS_RCC_MS_VALUE(PLL_ms));
+
+  RCC_FREF_VALUE(PLL_fref, ret);
+
+  result = PLL_ns * ret / PLL_ms;
+
+  assert_param(IS_RCC_RESULT_VALUE(result));
+
+  pll_reg = RCC->PLL;
+
+  /* Clear PLL */
+  pll_reg &= ~(PLL_FR_MASK | PLL_MS_MASK | PLL_NS_MASK | PLL_FREF_MASK | PLL_CFGEN_MASK);
+
+  /* Config pll */
+  pll_reg |= (PLL_fref | (PLL_ns << PLL_NS_POS) | (PLL_ms << PLL_MS_POS) | PLL_fr);
+
+  /* Enable PLLGEN */
+  pll_reg |= PLL_CFGEN_ENABLE;
+
+  RCC->PLL = pll_reg;
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_rtc.c

@@ -0,0 +1,337 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_rtc.c
+ * Description  : at32f4xx RTC source file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_rtc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup RTC
+  * @brief RTC driver modules
+  * @{
+  */
+
+#if defined (AT32F403xx) || defined (AT32F413xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+
+/** @defgroup RTC_Private_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Private_Defines
+  * @{
+  */
+#define RTC_LSB_MASK            ((uint32_t)0x0000FFFF)  /*!< RTC LSB Mask */
+#define DIVH_MSB_MASK           ((uint32_t)0x000F0000)  /*!< RTC Prescaler MSB Mask */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified RTC interrupts.
+  * @param  RTC_INT: specifies the RTC interrupts sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_INT_OV: Overflow interrupt
+  *     @arg RTC_INT_ALA: Alarm interrupt
+  *     @arg RTC_INT_PACE: Second interrupt
+  * @param  NewState: new state of the specified RTC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_INTConfig(uint16_t RTC_INT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_INT(RTC_INT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RTC->CTRLH |= RTC_INT;
+  }
+  else
+  {
+    RTC->CTRLH &= (uint16_t)~RTC_INT;
+  }
+}
+
+/**
+  * @brief  Enters the RTC configuration mode.
+  * @param  None
+  * @retval None
+  */
+void RTC_EnterConfigMode(void)
+{
+  /* Set the CNF flag to enter in the Configuration Mode */
+  RTC->CTRLL |= RTC_CTRLL_CMF;
+}
+
+/**
+  * @brief  Exits from the RTC configuration mode.
+  * @param  None
+  * @retval None
+  */
+void RTC_ExitConfigMode(void)
+{
+  /* Reset the CNF flag to exit from the Configuration Mode */
+  RTC->CTRLL &= (uint16_t)~((uint16_t)RTC_CTRLL_CMF);
+}
+
+/**
+  * @brief  Gets the RTC counter value.
+  * @param  None
+  * @retval RTC counter value.
+  */
+uint32_t RTC_GetCounter(void)
+{
+  uint16_t tmp = 0;
+  tmp = RTC->CNTL;
+  return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
+}
+
+/**
+  * @brief  Sets the RTC counter value.
+  * @param  CounterValue: RTC counter new value.
+  * @retval None
+  */
+void RTC_SetCounter(uint32_t CounterValue)
+{
+  RTC_EnterConfigMode();
+  /* Set RTC COUNTER MSB word */
+  RTC->CNTH = CounterValue >> 16;
+  /* Set RTC COUNTER LSB word */
+  RTC->CNTL = (CounterValue & RTC_LSB_MASK);
+  RTC_ExitConfigMode();
+}
+
+/**
+  * @brief  Sets the RTC prescaler value.
+  * @param  PrescalerValue: RTC prescaler new value.
+  * @retval None
+  */
+void RTC_SetDIV(uint32_t PrescalerValue)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_DIV(PrescalerValue));
+
+  RTC_EnterConfigMode();
+  /* Set RTC PRESCALER MSB word */
+  RTC->DIVH = (PrescalerValue & DIVH_MSB_MASK) >> 16;
+  /* Set RTC PRESCALER LSB word */
+  RTC->DIVL = (PrescalerValue & RTC_LSB_MASK);
+  RTC_ExitConfigMode();
+}
+
+/**
+  * @brief  Sets the RTC alarm value.
+  * @param  AlarmValue: RTC alarm new value.
+  * @retval None
+  */
+void RTC_SetAlarmValue(uint32_t AlarmValue)
+{
+  RTC_EnterConfigMode();
+  /* Set the ALARM MSB word */
+  RTC->ALAH = AlarmValue >> 16;
+  /* Set the ALARM LSB word */
+  RTC->ALAL = (AlarmValue & RTC_LSB_MASK);
+  RTC_ExitConfigMode();
+}
+
+/**
+  * @brief  Gets the RTC divider value.
+  * @param  None
+  * @retval RTC Divider value.
+  */
+uint32_t RTC_GetDivider(void)
+{
+  uint32_t tmp = 0x00;
+  tmp = ((uint32_t)RTC->DIVCNTH & (uint32_t)0x000F) << 16;
+  tmp |= RTC->DIVCNTL;
+  return tmp;
+}
+
+/**
+  * @brief  Waits until last write operation on RTC registers has finished.
+  * @note   This function must be called before any write to RTC registers.
+  * @param  None
+  * @retval None
+  */
+void RTC_WaitForLastTask(void)
+{
+  /* Loop until RTOFF flag is set */
+  while ((RTC->CTRLL & RTC_FLAG_RTF) == (uint16_t)RESET)
+  {
+  }
+}
+
+/**
+  * @brief  Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
+  *   are synchronized with RTC APB clock.
+  * @note   This function must be called before any read operation after an APB reset
+  *   or an APB clock stop.
+  * @param  None
+  * @retval None
+  */
+void RTC_WaitForSynchro(void)
+{
+  /* Clear RSF flag */
+  RTC->CTRLL &= (uint16_t)~RTC_FLAG_RSYNF;
+
+  /* Loop until RSF flag is set */
+  while ((RTC->CTRLL & RTC_FLAG_RSYNF) == (uint16_t)RESET)
+  {
+  }
+}
+
+/**
+  * @brief  Checks whether the specified RTC flag is set or not.
+  * @param  RTC_FLAG: specifies the flag to check.
+  *   This parameter can be one the following values:
+  *     @arg RTC_FLAG_RTF: RTC Operation OFF flag
+  *     @arg RTC_FLAG_RSYNF: Registers Synchronized flag
+  *     @arg RTC_FLAG_OV: Overflow flag
+  *     @arg RTC_FLAG_ALA: Alarm flag
+  *     @arg RTC_FLAG_PACE: Second flag
+  * @retval The new state of RTC_FLAG (SET or RESET).
+  */
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+
+  if ((RTC->CTRLL & RTC_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's pending flags.
+  * @param  RTC_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_FLAG_RSYNF: Registers Synchronized flag. This flag is cleared only after
+  *                        an APB reset or an APB Clock stop.
+  *     @arg RTC_FLAG_OV: Overflow flag
+  *     @arg RTC_FLAG_ALA: Alarm flag
+  *     @arg RTC_FLAG_PACE: Second flag
+  * @retval None
+  */
+void RTC_ClearFlag(uint16_t RTC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+  /* Clear the corresponding RTC flag */
+  RTC->CTRLL &= (uint16_t)~RTC_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified RTC interrupt has occurred or not.
+  * @param  RTC_INT: specifies the RTC interrupts sources to check.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_INT_OV: Overflow interrupt
+  *     @arg RTC_INT_ALA: Alarm interrupt
+  *     @arg RTC_INT_PACE: Second interrupt
+  * @retval The new state of the RTC_INT (SET or RESET).
+  */
+ITStatus RTC_GetINTStatus(uint16_t RTC_INT)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_INT(RTC_INT));
+
+  bitstatus = (ITStatus)(RTC->CTRLL & RTC_INT);
+
+  if (((RTC->CTRLH & RTC_INT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's interrupt pending bits.
+  * @param  RTC_INT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_INT_OV: Overflow interrupt
+  *     @arg RTC_INT_ALA: Alarm interrupt
+  *     @arg RTC_INT_PACE: Second interrupt
+  * @retval None
+  */
+void RTC_ClearINTPendingBit(uint16_t RTC_INT)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_INT(RTC_INT));
+
+  /* Clear the corresponding RTC pending bit */
+  RTC->CTRLL &= (uint16_t)~RTC_INT;
+}
+
+/**
+  * @}
+  */
+
+#endif /* AT32F403xx || AT32F413xx || AT32F403Axx || AT32F407xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_sdio.c

@@ -0,0 +1,913 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_sdio.c
+ * Description  : at32f4xx SDIO source file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_sdio.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SDIO
+  * @brief SDIO driver modules
+  * @{
+  */
+
+/** @defgroup SDIO_Private_TypesDefinitions
+  * @{
+  */
+
+/* --- CLKCR Register ---*/
+
+/* SDIO CLKEN mask */
+#define CLKCTRL_CLKEN_Set           ((uint32_t)0x00000100)
+#define CLKCTRL_CLKEN_Rst           ((uint32_t)0xFFFFFEFF)
+
+
+/* --- CMD Register ---*/
+
+/* SDIO SDIOSUSPEND mask */
+#define CMD_SDIOSUSP_Set            ((uint32_t)0x00000800)
+#define CMD_SDIOSUSP_Rst            ((uint32_t)0xFFFFF7FF)
+
+/* SDIO ENCMDCOMPL mask */
+#define CMD_CMPLSGNLEN_Set          ((uint32_t)0x00001000)
+#define CMD_CMPLSGNLEN_Rst          ((uint32_t)0xFFFFEFFF)
+
+/* SDIO INTDIS mask */
+#define CMD_INTDIS_Set              ((uint32_t)0x00002000)
+#define CMD_INTDIS_Rst              ((uint32_t)0xFFFFDFFF)
+
+/* SDIO ATACMD mask */
+#define CMD_ATACMD_Set              ((uint32_t)0x00004000)
+#define CMD_ATACMD_Rst              ((uint32_t)0xFFFFBFFF)
+
+
+/* --- DTCTRL Register ---*/
+
+/* SDIO ATACMD mask */
+#define DTCTRL_DMAEN_Set            ((uint32_t)0x00000008)
+#define DTCTRL_DMAEN_Rst            ((uint32_t)0xFFFFFFF7)
+
+/* SDIO RWSTART mask */
+#define DTCTRL_RWSTART_Set          ((uint32_t)0x00000100)
+#define DTCTRL_RWSTART_Rst          ((uint32_t)0xFFFFFEFF)
+
+/* SDIO RWSTOP mask */
+#define DTCTRL_RWSTOP_Set           ((uint32_t)0x00000200)
+#define DTCTRL_RWSTOP_Rst           ((uint32_t)0xFFFFFDFF)
+
+/* SDIO RWMOD mask */
+#define DTCTRL_RWMOD_Set            ((uint32_t)0x00000400)
+
+/* SDIO SDIOEN mask */
+#define DTCTRL_SDIOEN_Set           ((uint32_t)0x00000800)
+#define DTCTRL_SDIOEN_Rst           ((uint32_t)0xFFFFF7FF)
+
+/* ---------------------- SDIO registers bit mask ------------------------ */
+
+/* --- CLKCR Register ---*/
+
+/* CLKCR register clear mask */
+#define CLKCTRL_CLEAR_MASK          ((uint32_t)0xFFFE0100)
+
+/* --- PWRCTRL Register ---*/
+
+/* SDIO PWRCTRL Mask */
+#define PWR_PWRCTRL_MASK            ((uint32_t)0xFFFFFFFC)
+
+/* --- DTCTRL Register ---*/
+
+/* SDIO DTCTRL Clear Mask */
+#define DTCTRL_CLEAR_MASK           ((uint32_t)0xFFFFFF08)
+#define DTCTRL_RWMOD_MASK           ((uint32_t)0xFFFFFBFF)
+
+/* --- CMD Register ---*/
+
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK              ((uint32_t)0xFFFFF800)
+
+/* SDIO RESP Registers Address Offset */
+#define SDIO_RSP_ADDR_OFFSET        ((uint32_t)0x14)
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SDIO peripheral registers to their default reset values.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @retval None
+  */
+void SDIO_Reset(SDIO_Type * SDIOx)
+{
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  SDIOx->POWER = 0x00000000;
+  SDIOx->CLKCTRL = 0x00000000;
+  SDIOx->ARG = 0x00000000;
+  SDIOx->CMD = 0x00000000;
+  SDIOx->DTTMR = 0x00000000;
+  SDIOx->DTLEN = 0x00000000;
+  SDIOx->DTCTRL = 0x00000000;
+  SDIOx->INTCLR = 0x00C007FF;
+  SDIOx->INTEN = 0x00000000;
+}
+
+/**
+  * @brief  Initializes the SDIO peripheral according to the specified
+  *         parameters in the SDIO_InitStruct.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_InitStruct : pointer to a SDIO_InitType structure
+  *         that contains the configuration information for the SDIO peripheral.
+  * @retval None
+  */
+void SDIO_Init(SDIO_Type * SDIOx, SDIO_InitType* SDIO_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_CLK_EDGE(SDIO_InitStruct->SDIO_ClkEdge));
+  assert_param(IS_SDIO_CLK_BYPASS(SDIO_InitStruct->SDIO_ClkBypass));
+  assert_param(IS_SDIO_CLK_POWER_SAVE(SDIO_InitStruct->SDIO_ClkPowerSave));
+  assert_param(IS_SDIO_BUS_WIDTH(SDIO_InitStruct->SDIO_BusWidth));
+  assert_param(IS_SDIO_FLOW_CTRL(SDIO_InitStruct->SDIO_FlowCtrl));
+
+  /*---------------------------- SDIO CLKCR Configuration ------------------------*/
+  /* Get the SDIOx CLKCR value */
+  tmpreg = SDIOx->CLKCTRL;
+
+  /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
+  tmpreg &= CLKCTRL_CLEAR_MASK;
+
+  /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
+  /* Set BYPASS bit according to SDIO_ClockBypass value */
+  /* Set WIDBUS bits according to SDIO_BusWide value */
+  /* Set NEGEDGE bits according to SDIO_ClockEdge value */
+  /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
+  tmpreg |= (SDIO_InitStruct->SDIO_ClkPowerSave | SDIO_InitStruct->SDIO_ClkBypass |
+             SDIO_InitStruct->SDIO_BusWidth | SDIO_InitStruct->SDIO_ClkEdge | SDIO_InitStruct->SDIO_FlowCtrl);
+
+  /* Set CLKDIV bits according to SDIO_ClockDiv value */
+  tmpreg |= ((SDIO_InitStruct->SDIO_ClkPsc & 0x00FF) | ((SDIO_InitStruct->SDIO_ClkPsc & 0x0300) << 7));
+  /* Write to SDIOx CLKCR */
+  SDIOx->CLKCTRL = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_InitStruct member with its default value.
+  * @param  SDIO_InitStruct: pointer to an SDIO_InitType structure which
+  *   will be initialized.
+  * @retval None
+  */
+void SDIO_StructInit(SDIO_InitType* SDIO_InitStruct)
+{
+  /* SDIO_InitStruct members default value */
+  SDIO_InitStruct->SDIO_ClkPsc = 0x00;
+  SDIO_InitStruct->SDIO_ClkEdge = SDIO_ClkEdge_Rising;
+  SDIO_InitStruct->SDIO_ClkBypass = SDIO_ClkBypass_Disable;
+  SDIO_InitStruct->SDIO_ClkPowerSave = SDIO_ClkPowerSave_Disable;
+  SDIO_InitStruct->SDIO_BusWidth = SDIO_BusWidth_1b;
+  SDIO_InitStruct->SDIO_FlowCtrl = SDIO_FlowCtrl_Disable;
+}
+
+/**
+  * @brief  Enables or disables the SDIO Clock.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_ClockCmd(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the SDIO Clock. */
+    SDIOx->CLKCTRL |= CLKCTRL_CLKEN_Set;
+  }
+  else
+  {
+    /* Disable the SDIO Clock. */
+    SDIOx->CLKCTRL &= CLKCTRL_CLKEN_Rst;
+  }
+}
+
+/**
+  * @brief  Sets the power status of the controller.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_PowerState: new state of the Power state.
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_PowerSave_OFF
+  *     @arg SDIO_PowerSave_ON
+  * @retval None
+  */
+void SDIO_SetPowerSaveState(SDIO_Type * SDIOx, uint32_t SDIO_PowerState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_POWER_SAVE(SDIO_PowerState));
+
+  SDIOx->POWER &= PWR_PWRCTRL_MASK;
+  SDIOx->POWER |= SDIO_PowerState;
+}
+
+/**
+  * @brief  Gets the power status of the controller.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @retval Power status of the controller. The returned value can
+  *   be one of the following:
+  * - 0x00: Power OFF
+  * - 0x02: Power UP
+  * - 0x03: Power ON
+  */
+uint32_t SDIO_GetPowerSaveState(SDIO_Type * SDIOx)
+{
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  return (SDIOx->POWER & (~PWR_PWRCTRL_MASK));
+}
+
+/**
+  * @brief  Enables or disables the SDIO interrupts.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_INT: specifies the SDIO interrupt sources to be enabled or disabled.
+  *   This parameter can be one or a combination of the following values:
+  *     @arg SDIO_INT_CMDFAIL:    Command response received (CRC check failed) interrupt
+  *     @arg SDIO_INT_DTFAIL:     Data block sent/received (CRC check failed) interrupt
+  *     @arg SDIO_INT_CMDTIMEOUT: Command response timeout interrupt
+  *     @arg SDIO_INT_DTTIMEOUT:  Data timeout interrupt
+  *     @arg SDIO_INT_TXERRU:     Transmit FIFO underrun error interrupt
+  *     @arg SDIO_INT_RXERRO:     Received FIFO overrun error interrupt
+  *     @arg SDIO_INT_CMDRSPCMPL: Command response received (CRC check passed) interrupt
+  *     @arg SDIO_INT_CMDCMPL:    Command sent (no response required) interrupt
+  *     @arg SDIO_INT_DTCMPL:     Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *     @arg SDIO_INT_SBITERR:    Start bit not detected on all data signals in wide bus mode interrupt
+  *     @arg SDIO_INT_DTBLKCMPL:  Data block sent/received (CRC check passed) interrupt
+  *     @arg SDIO_INT_DOCMD:      Command transfer in progress interrupt
+  *     @arg SDIO_INT_DOTX:       Data transmit in progress interrupt
+  *     @arg SDIO_INT_DORX:       Data receive in progress interrupt
+  *     @arg SDIO_INT_TXBUF_H:    Transmit FIFO Half Empty interrupt
+  *     @arg SDIO_INT_RXBUF_H:    Receive FIFO Half Full interrupt
+  *     @arg SDIO_INT_TXBUF_F:    Transmit FIFO full interrupt
+  *     @arg SDIO_INT_RXBUF_F:    Receive FIFO full interrupt
+  *     @arg SDIO_INT_TXBUF_E:    Transmit FIFO empty interrupt
+  *     @arg SDIO_INT_RXBUF_E:    Receive FIFO empty interrupt
+  *     @arg SDIO_INT_TXBUF:      Data available in transmit FIFO interrupt
+  *     @arg SDIO_INT_RXBUF:      Data available in receive FIFO interrupt
+  *     @arg SDIO_INT_SDIOIF:     SD I/O interrupt received interrupt
+  *     @arg SDIO_INT_ATACMPL:    CE-ATA command completion signal received for CMD61 interrupt
+  * @param  NewState: new state of the specified SDIO interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_INTConfig(SDIO_Type * SDIOx, uint32_t SDIO_INT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_INT(SDIO_INT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the SDIO interrupts */
+    SDIOx->INTEN |= SDIO_INT;
+  }
+  else
+  {
+    /* Disable the SDIO interrupts */
+    SDIOx->INTEN &= ~SDIO_INT;
+  }
+}
+
+/**
+  * @brief  Enables or disables the SDIO DMA request.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of the selected SDIO DMA request.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_DMACmd(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SDIO DMA request. */
+    SDIOx->DTCTRL |= DTCTRL_DMAEN_Set;
+  }
+  else
+  {
+    /* Disable the selected SDIO DMA request. */
+    SDIOx->DTCTRL &= DTCTRL_DMAEN_Rst;
+  }
+}
+
+/**
+  * @brief  Initializes the SDIO Command according to the specified
+  *         parameters in the SDIO_CmdInitStruct and send the command.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_CmdInitStruct : pointer to a SDIO_CmdInitType
+  *         structure that contains the configuration information for the SDIO command.
+  * @retval None
+  */
+void SDIO_SendCommand(SDIO_Type * SDIOx, SDIO_CmdInitType *SDIO_CmdInitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_CMD_IDX(SDIO_CmdInitStruct->SDIO_CmdIdx));
+  assert_param(IS_SDIO_RSP_TYPE(SDIO_CmdInitStruct->SDIO_Resp));
+  assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
+  assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
+
+  /*---------------------------- SDIOx ARG Configuration ------------------------*/
+  /* Set the SDIOx Argument value */
+  SDIOx->ARG = SDIO_CmdInitStruct->SDIO_Argu;
+
+  /*---------------------------- SDIOx CMD Configuration ------------------------*/
+  /* Get the SDIOx CMD value */
+  tmpreg = SDIOx->CMD;
+  /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
+  tmpreg &= CMD_CLEAR_MASK;
+  /* Set CMDINDEX bits according to SDIO_CmdIndex value */
+  /* Set WAITRESP bits according to SDIO_Response value */
+  /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
+  /* Set CPSMEN bits according to SDIO_CPSM value */
+  tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIdx | SDIO_CmdInitStruct->SDIO_Resp
+            | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
+
+  /* Write to SDIOx CMD */
+  SDIOx->CMD = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_CmdInitStruct member with its default value.
+  * @param  SDIO_CmdInitStruct: pointer to an SDIO_CmdInitType
+  *         structure which will be initialized.
+  * @retval None
+  */
+void SDIO_CmdStructInit(SDIO_CmdInitType* SDIO_CmdInitStruct)
+{
+  /* SDIO_CmdInitStruct members default value */
+  SDIO_CmdInitStruct->SDIO_Argu = 0x00;
+  SDIO_CmdInitStruct->SDIO_CmdIdx = 0x00;
+  SDIO_CmdInitStruct->SDIO_Resp = SDIO_Rsp_No;
+  SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
+}
+
+/**
+  * @brief  Returns command index of last command for which response received.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @retval Returns the command index of the last command response received.
+  */
+uint8_t SDIO_GetCommandResponse(SDIO_Type * SDIOx)
+{
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  return (uint8_t)(SDIOx->RSPCMD);
+}
+
+/**
+  * @brief  Returns response received from the card for the last command.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_RESP: Specifies the SDIO response register.
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_RSP1: Response Register 1
+  *     @arg SDIO_RSP2: Response Register 2
+  *     @arg SDIO_RSP3: Response Register 3
+  *     @arg SDIO_RSP4: Response Register 4
+  * @retval The Corresponding response register value.
+  */
+uint32_t SDIO_GetResponse(SDIO_Type * SDIOx, uint32_t SDIO_RESP)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_RSP(SDIO_RESP));
+
+  tmp = (uint32_t)&SDIOx->RSP1 + SDIO_RESP;
+
+  return (*(__IO uint32_t *) tmp);
+}
+
+/**
+  * @brief  Initializes the SDIO data path according to the specified
+  *   parameters in the SDIO_DataInitStruct.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitType structure that
+  *   contains the configuration information for the SDIO command.
+  * @retval None
+  */
+void SDIO_DataConfig(SDIO_Type * SDIOx, SDIO_DataInitType* SDIO_DataInitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_DATA_LEN(SDIO_DataInitStruct->SDIO_DataLen));
+  assert_param(IS_SDIO_BLK_SIZE(SDIO_DataInitStruct->SDIO_DataBlkSize));
+  assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
+  assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
+  assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
+
+  /*---------------------------- SDIO DTIMER Configuration ---------------------*/
+  /* Set the SDIOx Data TimeOut value */
+  SDIOx->DTTMR = SDIO_DataInitStruct->SDIO_DataTimeOut;
+
+  /*---------------------------- SDIOx DLEN Configuration -----------------------*/
+  /* Set the SDIOx DataLength value */
+  SDIOx->DTLEN = SDIO_DataInitStruct->SDIO_DataLen;
+
+  /*---------------------------- SDIO DTCTRL Configuration ----------------------*/
+  /* Get the SDIOx DTCTRL value */
+  tmpreg = SDIOx->DTCTRL;
+  /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
+  tmpreg &= DTCTRL_CLEAR_MASK;
+  /* Set DEN bit according to SDIO_DPSM value */
+  /* Set DTMODE bit according to SDIO_TransferMode value */
+  /* Set DTDIR bit according to SDIO_TransferDir value */
+  /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
+  tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlkSize | SDIO_DataInitStruct->SDIO_TransferDir
+            | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
+
+  /* Write to SDIOx DTCTRL */
+  SDIOx->DTCTRL = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_DataInitStruct member with its default value.
+  * @param  SDIO_DataInitStruct: pointer to an SDIO_DataInitType structure which
+  *         will be initialized.
+  * @retval None
+  */
+void SDIO_DataStructInit(SDIO_DataInitType* SDIO_DataInitStruct)
+{
+  /* SDIO_DataInitStruct members default value */
+  SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
+  SDIO_DataInitStruct->SDIO_DataLen = 0x00;
+  SDIO_DataInitStruct->SDIO_DataBlkSize = SDIO_DataBlkSize_1b;
+  SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
+  SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
+  SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
+}
+
+/**
+  * @brief  Returns number of remaining data bytes to be transferred.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @retval Number of remaining data bytes to be transferred
+  */
+uint32_t SDIO_GetDataCounter(SDIO_Type * SDIOx)
+{
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  return SDIOx->DTCNTR;
+}
+
+/**
+  * @brief  Read one data word from Rx FIFO.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @retval Data received
+  */
+uint32_t SDIO_ReadData(SDIO_Type * SDIOx)
+{
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  return SDIOx->BUF;
+}
+
+/**
+  * @brief  Write one data word to Tx FIFO.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  Data: 32-bit data word to write.
+  * @retval None
+  */
+void SDIO_WriteData(SDIO_Type * SDIOx, uint32_t Data)
+{
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  SDIOx->BUF = Data;
+}
+
+/**
+  * @brief  Returns the number of words left to be written to or read from FIFO.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @retval Remaining number of words.
+  */
+uint32_t SDIO_GetBUFCount(SDIO_Type * SDIOx)
+{
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  return SDIOx->BUFCNTR;
+}
+
+/**
+  * @brief  Starts the SD I/O Read Wait operation.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of the Start SDIO Read Wait operation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_StartSDIOReadWait(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Start SDIO Read Wait operation. */
+    SDIOx->DTCTRL |= DTCTRL_RWSTART_Set;
+  }
+  else
+  {
+    /* Disable the Start SDIO Read Wait operation. */
+    SDIOx->DTCTRL &= DTCTRL_RWSTART_Rst;
+  }
+}
+
+/**
+  * @brief  Stops the SD I/O Read Wait operation.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of the Stop SDIO Read Wait operation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_StopSDIOReadWait(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Stop SDIO Read Wait operation. */
+    SDIOx->DTCTRL |= DTCTRL_RWSTOP_Set;
+  }
+  else
+  {
+    /* Disable the Stop SDIO Read Wait operation. */
+    SDIOx->DTCTRL &= DTCTRL_RWSTOP_Rst;
+  }
+}
+
+/**
+  * @brief  Sets one of the two options of inserting read wait interval.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
+  *   This parameter can be:
+  *     @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
+  *     @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
+  * @retval None
+  */
+void SDIO_SetSDIOReadWaitMode(SDIO_Type * SDIOx, uint32_t SDIO_ReadWaitMode)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
+
+  SDIOx->DTCTRL &= DTCTRL_RWMOD_MASK;
+
+  SDIOx->DTCTRL |= SDIO_ReadWaitMode;
+}
+
+/**
+  * @brief  Enables or disables the SD I/O Mode Operation.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of SDIO specific operation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_SetSDIOOperation(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable SDIO specific operation. */
+    SDIOx->DTCTRL |= DTCTRL_SDIOEN_Set;
+  }
+  else
+  {
+    /* Disable SDIO specific operation. */
+    SDIOx->DTCTRL &= DTCTRL_SDIOEN_Rst;
+  }
+}
+
+/**
+  * @brief  Enables or disables the SD I/O Mode suspend command sending.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of the SD I/O Mode suspend command.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_SendSDIOSuspendCmd(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable SD I/O Mode suspend command. */
+    SDIOx->CMD |= CMD_SDIOSUSP_Set;
+  }
+  else
+  {
+    /* Disable SD I/O Mode suspend command. */
+    SDIOx->CMD &= CMD_SDIOSUSP_Rst;
+  }
+}
+
+/**
+  * @brief  Enables or disables the command completion signal.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of command completion signal.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_CommandCompletionCmd(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the command completion signal. */
+    SDIOx->CMD |= CMD_CMPLSGNLEN_Set;
+  }
+  else
+  {
+    /* Disable the command completion signal. */
+    SDIOx->CMD &= CMD_CMPLSGNLEN_Rst;
+  }
+}
+
+/**
+  * @brief  Enables or disables the CE-ATA interrupt.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_ATAINTCmd(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable ATA Interrupt. */
+    SDIOx->CMD &= CMD_INTDIS_Rst;
+  }
+  else
+  {
+    /* Disable CE-ATA command. */
+    SDIOx->CMD |= CMD_INTDIS_Set;
+  }
+}
+
+/**
+  * @brief  Sends CE-ATA command (CMD61).
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_SendATACmd(SDIO_Type * SDIOx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable CE-ATA command. */
+    SDIOx->CMD |= CMD_ATACMD_Set;
+  }
+  else
+  {
+    /* Disable CE-ATA command. */
+    SDIOx->CMD &= CMD_ATACMD_Rst;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified SDIO flag is set or not.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_FLG_CMDFAIL:    Command response received (CRC check failed)
+  *     @arg SDIO_FLG_DTFAIL:     Data block sent/received (CRC check failed)
+  *     @arg SDIO_FLG_CMDTIMEOUT: Command response timeout
+  *     @arg SDIO_FLG_DTTIMEOUT:  Data timeout
+  *     @arg SDIO_FLG_TXERRU:     Transmit FIFO underrun error
+  *     @arg SDIO_FLG_RXERRO:     Received FIFO overrun error
+  *     @arg SDIO_FLG_CMDRSPCMPL: Command response received (CRC check passed)
+  *     @arg SDIO_FLG_CMDCMPL:    Command sent (no response required)
+  *     @arg SDIO_FLG_DTCMPL:     Data end (data counter, SDIDCOUNT, is zero)
+  *     @arg SDIO_FLG_SBITERR:    Start bit not detected on all data signals in wide bus mode.
+  *     @arg SDIO_FLG_DTBLKCMPL:  Data block sent/received (CRC check passed)
+  *     @arg SDIO_FLG_DOCMD:      Command transfer in progress
+  *     @arg SDIO_FLG_DOTX:       Data transmit in progress
+  *     @arg SDIO_FLG_DORX:       Data receive in progress
+  *     @arg SDIO_FLG_TXBUF_H:    Transmit FIFO Half Empty
+  *     @arg SDIO_FLG_RXBUF_H:    Receive FIFO Half Full
+  *     @arg SDIO_FLG_TXBUF_F:    Transmit FIFO full
+  *     @arg SDIO_FLG_RXBUF_F:    Receive FIFO full
+  *     @arg SDIO_FLG_TXBUF_E:    Transmit FIFO empty
+  *     @arg SDIO_FLG_RXBUF_E:    Receive FIFO empty
+  *     @arg SDIO_FLG_TXBUF:      Data available in transmit FIFO
+  *     @arg SDIO_FLG_RXBUF:      Data available in receive FIFO
+  *     @arg SDIO_FLG_SDIOIF:     SD I/O interrupt received
+  *     @arg SDIO_FLG_ATACMPL:    CE-ATA command completion signal received for CMD61
+  * @retval The new state of SDIO_FLAG (SET or RESET).
+  */
+FlagStatus SDIO_GetFlagStatus(SDIO_Type * SDIOx, uint32_t SDIO_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_FLG(SDIO_FLAG));
+
+  if ((SDIOx->STS & SDIO_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SDIO's pending flags.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_FLAG: specifies the flag to clear.
+  *   This parameter can be one or a combination of the following values:
+  *     @arg SDIO_FLG_CMDFAIL:    Command response received (CRC check failed)
+  *     @arg SDIO_FLG_DTFAIL:     Data block sent/received (CRC check failed)
+  *     @arg SDIO_FLG_CMDTIMEOUT: Command response timeout
+  *     @arg SDIO_FLG_DTTIMEOUT:  Data timeout
+  *     @arg SDIO_FLG_TXERRU:     Transmit FIFO underrun error
+  *     @arg SDIO_FLG_RXERRO:     Received FIFO overrun error
+  *     @arg SDIO_FLG_CMDRSPCMPL: Command response received (CRC check passed)
+  *     @arg SDIO_FLG_CMDCMPL:    Command sent (no response required)
+  *     @arg SDIO_FLG_DTCMPL:     Data end (data counter, SDIDCOUNT, is zero)
+  *     @arg SDIO_FLG_SBITERR:    Start bit not detected on all data signals in wide bus mode
+  *     @arg SDIO_FLG_DTBLKCMPL:  Data block sent/received (CRC check passed)
+  *     @arg SDIO_FLG_SDIOIF:     SD I/O interrupt received
+  *     @arg SDIO_FLG_ATACMPL:    CE-ATA command completion signal received for CMD61
+  * @retval None
+  */
+void SDIO_ClearFlag(SDIO_Type * SDIOx, uint32_t SDIO_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_CLEAR_FLG(SDIO_FLAG));
+
+  SDIOx->INTCLR = SDIO_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified SDIO interrupt has occurred or not.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_INT: specifies the SDIO interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_INT_CMDFAIL:    Command response received (CRC check failed) interrupt
+  *     @arg SDIO_INT_DTFAIL:     Data block sent/received (CRC check failed) interrupt
+  *     @arg SDIO_INT_CMDTIMEOUT: Command response timeout interrupt
+  *     @arg SDIO_INT_DTTIMEOUT:  Data timeout interrupt
+  *     @arg SDIO_INT_TXERRU:     Transmit FIFO underrun error interrupt
+  *     @arg SDIO_INT_RXERRO:     Received FIFO overrun error interrupt
+  *     @arg SDIO_INT_CMDRSPCMPL: Command response received (CRC check passed) interrupt
+  *     @arg SDIO_INT_CMDCMPL:    Command sent (no response required) interrupt
+  *     @arg SDIO_INT_DTCMPL:     Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *     @arg SDIO_INT_SBITERR:    Start bit not detected on all data signals in wide bus mode interrupt
+  *     @arg SDIO_INT_DTBLKCMPL:  Data block sent/received (CRC check passed) interrupt
+  *     @arg SDIO_INT_DOCMD:      Command transfer in progress interrupt
+  *     @arg SDIO_INT_DOTX:       Data transmit in progress interrupt
+  *     @arg SDIO_INT_DORX:       Data receive in progress interrupt
+  *     @arg SDIO_INT_TXBUF_H:    Transmit FIFO Half Empty interrupt
+  *     @arg SDIO_INT_RXBUF_H:    Receive FIFO Half Full interrupt
+  *     @arg SDIO_INT_TXBUF_F:    Transmit FIFO full interrupt
+  *     @arg SDIO_INT_RXBUF_F:    Receive FIFO full interrupt
+  *     @arg SDIO_INT_TXBUF_E:    Transmit FIFO empty interrupt
+  *     @arg SDIO_INT_RXBUF_E:    Receive FIFO empty interrupt
+  *     @arg SDIO_INT_TXBUF:      Data available in transmit FIFO interrupt
+  *     @arg SDIO_INT_RXBUF:      Data available in receive FIFO interrupt
+  *     @arg SDIO_INT_SDIOIF:     SD I/O interrupt received interrupt
+  *     @arg SDIO_INT_ATACMPL:    CE-ATA command completion signal received for CMD61 interrupt
+  * @retval The new state of SDIO_INT (SET or RESET).
+  */
+ITStatus SDIO_GetINTStatus(SDIO_Type * SDIOx, uint32_t SDIO_INT)
+{
+  ITStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_GET_INT(SDIO_INT));
+
+  if ((SDIOx->STS & SDIO_INT) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SDIO's interrupt pending bits.
+  * @param  SDIOx: where x can be 1 or 2 to select the SDIO peripheral.
+  * @param  SDIO_INT: specifies the interrupt pending bit to clear.
+  *   This parameter can be one or a combination of the following values:
+  *     @arg SDIO_INT_CMDFAIL:    Command response received (CRC check failed) interrupt
+  *     @arg SDIO_INT_DTFAIL:     Data block sent/received (CRC check failed) interrupt
+  *     @arg SDIO_INT_CMDTIMEOUT: Command response timeout interrupt
+  *     @arg SDIO_INT_DTTIMEOUT:  Data timeout interrupt
+  *     @arg SDIO_INT_TXERRU:     Transmit FIFO underrun error interrupt
+  *     @arg SDIO_INT_RXERRO:     Received FIFO overrun error interrupt
+  *     @arg SDIO_INT_CMDRSPCMPL: Command response received (CRC check passed) interrupt
+  *     @arg SDIO_INT_CMDCMPL:    Command sent (no response required) interrupt
+  *     @arg SDIO_INT_DTCMPL:     Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *     @arg SDIO_INT_SBITERR:    Start bit not detected on all data signals in wide bus mode interrupt
+  *     @arg SDIO_INT_SDIOIF:     SD I/O interrupt received interrupt
+  *     @arg SDIO_INT_ATACMPL:    CE-ATA command completion signal received for CMD61
+  * @retval None
+  */
+void SDIO_ClearINTPendingBit(SDIO_Type * SDIOx, uint32_t SDIO_INT)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_PERIPH(SDIOx));
+  assert_param(IS_SDIO_CLEAR_INT(SDIO_INT));
+
+  SDIOx->INTCLR = SDIO_INT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_spi.c

@@ -0,0 +1,897 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_spi.c
+ * Description  : at32f4xx SPI source file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_spi.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SPI
+  * @brief SPI driver modules
+  * @{
+  */
+
+/** @defgroup SPI_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SPI_Private_Defines
+  * @{
+  */
+
+/* SPI SPE mask */
+#define CTRL1_SPIEN_SET         ((uint16_t)0x0040)
+#define CTRL1_SPIEN_RESET       ((uint16_t)0xFFBF)
+
+/* I2S I2SE mask */
+#define I2SCTRL_I2SEN_SET       ((uint16_t)0x0400)
+#define I2SCTRL_I2SEN_RESET     ((uint16_t)0xFBFF)
+
+/* SPI CRCNext mask */
+#define CTRL1_CTN_SET           ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CTRL1_CCE_SET           ((uint16_t)0x2000)
+#define CTRL1_CCE_RESET         ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CTRL2_NSSOE_SET         ((uint16_t)0x0004)
+#define CTRL2_NSSOE_RESET       ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CTRL1_CLEAR_MASK        ((uint16_t)0x3040)
+#define I2SCTRL_CLEAR_MASK      ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_MODE_SEL            ((uint16_t)0xF7FF)
+#define I2S_MODE_SEL            ((uint16_t)0x0800)
+
+/* I2S clock source selection masks */
+#define I2S2_CLK_SRC            ((uint32_t)(0x00020000))
+#define I2S3_CLK_SRC            ((uint32_t)(0x00040000))
+#define I2S_MUL_MASK            ((uint32_t)(0x0000F000))
+#define I2S_DIV_MASK            ((uint32_t)(0x000000F0))
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SPIx peripheral registers to their default
+  *         reset values (Affects also the I2Ss).
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @retval None
+  */
+void SPI_I2S_Reset(SPI_Type* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  if (SPIx == SPI1)
+  {
+    /* Enable SPI1 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_SPI1, ENABLE);
+    /* Release SPI1 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_SPI1, DISABLE);
+  }
+  else if (SPIx == SPI2)
+  {
+    /* Enable SPI2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_SPI2, ENABLE);
+    /* Release SPI2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_SPI2, DISABLE);
+  }
+#if defined (AT32F403xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+  else if (SPIx == SPI3)
+  {
+    /* Enable SPI3 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_SPI3, ENABLE);
+    /* Release SPI3 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_SPI3, DISABLE);
+  }
+  else if (SPIx == SPI4)
+  {
+    /* Enable SPI4 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_SPI4, ENABLE);
+    /* Release SPI4 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_SPI4, DISABLE);
+  }
+#endif
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified
+  *         parameters in the SPI_InitStruct.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @param  SPI_InitStruct: pointer to a SPI_InitType structure that
+  *         contains the configuration information for the specified SPI peripheral.
+  * @retval None
+  */
+void SPI_Init(SPI_Type* SPIx, SPI_InitType* SPI_InitStruct)
+{
+  uint16_t tmpreg = 0;
+
+  /* check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Check the SPI parameters */
+  assert_param(IS_SPI_TRANS_MODE(SPI_InitStruct->SPI_TransMode));
+  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+  assert_param(IS_SPI_FRAMESIZE(SPI_InitStruct->SPI_FrameSize));
+  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+  assert_param(IS_SPI_NSSSEL(SPI_InitStruct->SPI_NSSSEL));
+  assert_param(IS_SPI_MCLKP(SPI_InitStruct->SPI_MCLKP));
+  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
+  assert_param(IS_SPI_CPOLY(SPI_InitStruct->SPI_CPOLY));
+
+  /*---------------------------- SPIx CTRL1 Configuration ------------------------*/
+  /* Get the SPIx CTRL1 value */
+  tmpreg = SPIx->CTRL1;
+  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+  tmpreg &= CTRL1_CLEAR_MASK;
+  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+     master/salve mode, CPOL and CPHA */
+  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+  /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
+  /* Set LSBFirst bit according to SPI_FirstBit value */
+  /* Set BR bits according to SPI_BaudRatePrescaler value */
+  /* Set CPOL bit according to SPI_CPOL value */
+  /* Set CPHA bit according to SPI_CPHA value */
+
+  if (SPI_InitStruct->SPI_MCLKP & SPI_MCLKP_OVER_256)
+  {
+    /* MCLKP is over 256 */
+    SPIx->CTRL2 |= SPI_CTRL2_MCLKP_3;
+  }
+  else
+  {
+    SPIx->CTRL2 &= ~SPI_CTRL2_MCLKP_3;
+  }
+
+  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_TransMode | SPI_InitStruct->SPI_Mode |
+                       SPI_InitStruct->SPI_FrameSize | SPI_InitStruct->SPI_CPOL |
+                       SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSSSEL |
+                       (SPI_InitStruct->SPI_MCLKP & 0x7FFF) | SPI_InitStruct->SPI_FirstBit);
+  /* Write to SPIx CTRL1 */
+  SPIx->CTRL1 = tmpreg;
+
+
+  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+  SPIx->I2SCTRL &= SPI_MODE_SEL;
+
+  /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+  /* Write to SPIx CRCPOLY */
+  SPIx->CPOLY = SPI_InitStruct->SPI_CPOLY;
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified
+  *         parameters in the I2S_InitStruct.
+  * @param  SPIx: where x can be 2, 3, or 4 to select the SPI peripheral
+  *         (configured in I2S mode).
+  * @param  I2S_InitStruct: pointer to an I2S_InitType structure that
+  *         contains the configuration information for the specified SPI peripheral
+  *         configured in I2S mode.
+  * @note
+  *  The function calculates the optimal prescaler needed to obtain the most
+  *  accurate audio frequency (depending on the I2S clock source, the PLL values
+  *  and the product configuration). But in case the prescaler value is greater
+  *  than 511, the default value (0x02) will be configured instead.  *
+  * @retval None
+  */
+void I2S_Init(SPI_Type* SPIx, I2S_InitType* I2S_InitStruct)
+{
+  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+  uint32_t tmp = 0;
+  RCC_ClockType RCC_Clocks;
+  uint32_t sourceclock = 0;
+
+  /* Check the I2S parameters */
+  assert_param(IS_SPI_I2S_PERIPH(SPIx));
+  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+  assert_param(IS_I2S_AUDIOPROTOCOL(I2S_InitStruct->I2s_AudioProtocol));
+  assert_param(IS_I2S_FRAMEFORMAT(I2S_InitStruct->I2S_FrameFormat));
+  assert_param(IS_I2S_MCLKOE(I2S_InitStruct->I2S_MCLKOE));
+  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
+  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
+
+  /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+  SPIx->I2SCTRL &= I2SCTRL_CLEAR_MASK;
+  SPIx->I2SCLKP = 0x0002;
+
+  /* Get the I2SCFGR register value */
+  tmpreg = SPIx->I2SCTRL;
+
+  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+  if(I2S_InitStruct->I2S_AudioFreq == I2S_AUDIOFREQ_DEFAULT)
+  {
+    i2sodd = (uint16_t)0;
+    i2sdiv = (uint16_t)2;
+  }
+  /* If the requested audio frequency is not the default, compute the prescaler */
+  else
+  {
+    /* Check the frame length (For the Prescaler computing) */
+    if(I2S_InitStruct->I2S_FrameFormat == I2S_FRAMEFORMAT_DL16BIT_CHL16BIT)
+    {
+      /* Packet length is 16 bits */
+      packetlength = 1;
+    }
+    else
+    {
+      /* Packet length is 32 bits */
+      packetlength = 2;
+    }
+
+    /* Get the I2S clock source mask depending on the peripheral number */
+    if(((uint32_t)SPIx) == SPI2_BASE)
+    {
+      /* The mask is relative to I2S2 */
+      tmp = I2S2_CLK_SRC;
+    }
+    else
+    {
+      /* The mask is relative to I2S3 */
+      tmp = I2S3_CLK_SRC;
+    }
+
+    /* Check the I2S clock source configuration depending on the Device */
+    /* I2S Clock source is System clock: Get System Clock frequency */
+    RCC_GetClocksFreq(&RCC_Clocks);
+
+    /* Get the source clock value: based on System Clock value */
+    sourceclock = RCC_Clocks.SYSCLK_Freq;
+
+    /* Compute the Real divider depending on the MCLK output state with a floating point */
+    if(I2S_InitStruct->I2S_MCLKOE == I2S_MCLKOE_ENABLE)
+    {
+      /* MCLK output is enabled */
+      tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+    else
+    {
+      /* MCLK output is disabled */
+      tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+
+    /* Remove the floating point */
+    tmp = tmp / 10;
+
+    /* Check the parity of the divider */
+    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+
+    /* Compute the i2sdiv prescaler */
+    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+
+    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+    i2sodd = (uint16_t) (i2sodd << 8);
+  }
+
+  /* Test if the divider is 1 or 0 or greater than 0xFF */
+  if ((i2sdiv < 2) || (i2sdiv > I2S_DIV_VALUE_MAX))
+  {
+    /* Set the default values */
+    i2sdiv = 2;
+    i2sodd = 0;
+  }
+  else if (i2sdiv & I2S_DIV_EXT_VALUE_MASK)
+  {
+    /* Shift I2SDIV[9:8] to SPI_I2SCLKP[11:10] */
+    i2sdiv |= ((i2sdiv & I2S_DIV_EXT_VALUE_MASK) << I2S_DIV_EXT_VALUE_LSHIFT_OFFSET);
+    i2sdiv &= ~I2S_DIV_EXT_VALUE_MASK;
+  }
+
+  /* Write to SPIx I2SPR register the computed value */
+  SPIx->I2SCLKP = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOE));
+
+  /* Configure the I2S with the SPI_InitStruct values */
+  tmpreg |= (uint16_t)(I2S_MODE_SEL | (uint16_t)(I2S_InitStruct->I2S_Mode | \
+                       (uint16_t)(I2S_InitStruct->I2s_AudioProtocol | (uint16_t)(I2S_InitStruct->I2S_FrameFormat | \
+                                  (uint16_t)I2S_InitStruct->I2S_CPOL))));
+
+  /* Write to SPIx I2SCFGR */
+  SPIx->I2SCTRL = tmpreg;
+}
+
+/**
+  * @brief  Fills each SPI_InitStruct member with its default value.
+  * @param  SPI_InitStruct : pointer to a SPI_InitType structure which will be initialized.
+  * @retval None
+  */
+void SPI_DefaultInitParaConfig(SPI_InitType* SPI_InitStruct)
+{
+  /*--------------- Reset SPI init structure parameters values -----------------*/
+  /* Initialize the SPI_Direction member */
+  SPI_InitStruct->SPI_TransMode = SPI_TRANSMODE_FULLDUPLEX;
+  /* initialize the SPI_Mode member */
+  SPI_InitStruct->SPI_Mode = SPI_MODE_SLAVE;
+  /* initialize the SPI_DataSize member */
+  SPI_InitStruct->SPI_FrameSize = SPI_FRAMESIZE_8BIT;
+  /* Initialize the SPI_CPOL member */
+  SPI_InitStruct->SPI_CPOL = SPI_CPOL_LOW;
+  /* Initialize the SPI_CPHA member */
+  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1EDGE;
+  /* Initialize the SPI_NSS member */
+  SPI_InitStruct->SPI_NSSSEL = SPI_NSSSEL_HARD;
+  /* Initialize the SPI_BaudRatePrescaler member */
+  SPI_InitStruct->SPI_MCLKP = SPI_MCLKP_2;
+  /* Initialize the SPI_FirstBit member */
+  SPI_InitStruct->SPI_FirstBit = SPI_FIRSTBIT_MSB;
+  /* Initialize the SPI_CRCPolynomial member */
+  SPI_InitStruct->SPI_CPOLY = 7;
+}
+
+/**
+  * @brief  Fills each I2S_InitStruct member with its default value.
+  * @param  I2S_InitStruct : pointer to a I2S_InitType structure which will be initialized.
+  * @retval None
+  */
+void I2S_DefaultInit(I2S_InitType* I2S_InitStruct)
+{
+  /*--------------- Reset I2S init structure parameters values -----------------*/
+  /* Initialize the I2S_Mode member */
+  I2S_InitStruct->I2S_Mode = I2S_MODE_SLAVETX;
+
+  /* Initialize the I2S_Standard member */
+  I2S_InitStruct->I2s_AudioProtocol = I2S_AUDIOPROTOCOL_PHILLIPS;
+
+  /* Initialize the I2S_DataFormat member */
+  I2S_InitStruct->I2S_FrameFormat = I2S_FRAMEFORMAT_DL16BIT_CHL16BIT;
+
+  /* Initialize the I2S_MCLKOutput member */
+  I2S_InitStruct->I2S_MCLKOE = I2S_MCLKOE_DISABLE;
+
+  /* Initialize the I2S_AudioFreq member */
+  I2S_InitStruct->I2S_AudioFreq = I2S_AUDIOFREQ_DEFAULT;
+
+  /* Initialize the I2S_CPOL member */
+  I2S_InitStruct->I2S_CPOL = I2S_CPOL_LOW;
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_Enable(SPI_Type* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral */
+    SPIx->CTRL1 |= CTRL1_SPIEN_SET;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral */
+    SPIx->CTRL1 &= CTRL1_SPIEN_RESET;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
+  * @param  SPIx: where x can be 2, 3, or 4 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2S_Enable(SPI_Type* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_I2S_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral (in I2S mode) */
+    SPIx->I2SCTRL |= I2SCTRL_I2SEN_SET;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral (in I2S mode) */
+    SPIx->I2SCTRL &= I2SCTRL_I2SEN_RESET;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified SPI/I2S interrupts.
+  * @param  SPIx: where x can be
+  *   - 1, 2, 3, or 4 in SPI mode
+  *   - 2, 3, or 4 in I2S mode
+  * @param  SPI_I2S_INT: specifies the SPI/I2S interrupt source to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_I2S_INT_TE: Tx buffer empty interrupt mask
+  *     @arg SPI_I2S_INT_RNE: Rx buffer not empty interrupt mask
+  *     @arg SPI_I2S_INT_ERR: Error interrupt mask
+  * @param  NewState: new state of the specified SPI/I2S interrupt.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_I2S_INTConfig(SPI_Type* SPIx, uint8_t SPI_I2S_INT, FunctionalState NewState)
+{
+  uint16_t itpos = 0, itmask = 0 ;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_CONFIG_INT(SPI_I2S_INT));
+
+  /* Get the SPI/I2S INT index */
+  itpos = SPI_I2S_INT >> 4;
+
+  /* Set the INT mask */
+  itmask = (uint16_t)1 << (uint16_t)itpos;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI/I2S interrupt */
+    SPIx->CTRL2 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected SPI/I2S interrupt */
+    SPIx->CTRL2 &= (uint16_t)~itmask;
+  }
+}
+
+/**
+  * @brief  Enables or disables the SPIx/I2Sx DMA interface.
+  * @param  SPIx: where x can be
+  *   - 1, 2, 3, or 4 in SPI mode
+  *   - 2, 3, or 4 in I2S mode
+  * @param  SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg SPI_I2S_DMA_TX: Tx buffer DMA transfer request
+  *     @arg SPI_I2S_DMA_RX: Rx buffer DMA transfer request
+  * @param  NewState: new state of the selected SPI/I2S DMA transfer request.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_I2S_DMAEnable(SPI_Type* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_DMA(SPI_I2S_DMAReq));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI/I2S DMA requests */
+    SPIx->CTRL2 |= SPI_I2S_DMAReq;
+  }
+  else
+  {
+    /* Disable the selected SPI/I2S DMA requests */
+    SPIx->CTRL2 &= (uint16_t)~SPI_I2S_DMAReq;
+  }
+}
+
+/**
+  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
+  * @param  SPIx: where x can be
+  *   - 1, 2, 3, or 4 in SPI mode
+  *   - 2, 3, or 4 in I2S mode
+  * @param  Data : Data to be transmitted.
+  * @retval None
+  */
+void SPI_I2S_TxData(SPI_Type* SPIx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Write in the DR register the data to be sent */
+  SPIx->DT = Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral.
+  * @param  SPIx: where x can be
+  *   - 1, 2, 3, or 4 in SPI mode
+  *   - 2, 3, or 4 in I2S mode
+  * @retval The value of the received data.
+  */
+uint16_t SPI_I2S_RxData(SPI_Type* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Return the data in the DR register */
+  return SPIx->DT;
+}
+
+/**
+  * @brief  Configures internally by software the NSS pin for the selected SPI.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_ISS_SET: Set NSS pin internally
+  *     @arg SPI_ISS_RESET: Reset NSS pin internally
+  * @retval None
+  */
+void SPI_NSSInternalSoftwareConfig(SPI_Type* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_ISS(SPI_NSSInternalSoft));
+
+  if (SPI_NSSInternalSoft != SPI_ISS_RESET)
+  {
+    /* Set NSS pin internally by software */
+    SPIx->CTRL1 |= SPI_ISS_SET;
+  }
+  else
+  {
+    /* Reset NSS pin internally by software */
+    SPIx->CTRL1 &= SPI_ISS_RESET;
+  }
+}
+
+/**
+  * @brief  Enables or disables the SS output for the selected SPI.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx SS output.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_NSSHardwareOutputEnable(SPI_Type* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI SS output */
+    SPIx->CTRL2 |= CTRL2_NSSOE_SET;
+  }
+  else
+  {
+    /* Disable the selected SPI SS output */
+    SPIx->CTRL2 &= CTRL2_NSSOE_RESET;
+  }
+}
+
+/**
+  * @brief  Configures the data size for the selected SPI.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @param  SPI_DataSize: specifies the SPI data size.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_FRAMESIZE_16BIT: Set data frame format to 16bit
+  *     @arg SPI_FRAMESIZE_8BIT: Set data frame format to 8bit
+  * @retval None
+  */
+void SPI_FrameSizeConfig(SPI_Type* SPIx, uint16_t SPI_DataSize)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_FRAMESIZE(SPI_DataSize));
+  /* Clear DFF bit */
+  SPIx->CTRL1 &= (uint16_t)~SPI_FRAMESIZE_16BIT;
+  /* Set new DFF bit value */
+  SPIx->CTRL1 |= SPI_DataSize;
+}
+
+/**
+  * @brief  Transmit the SPIx CRC value.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @retval None
+  */
+void SPI_TxCRC(SPI_Type* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Enable the selected SPI CRC transmission */
+  SPIx->CTRL1 |= CTRL1_CTN_SET;
+}
+
+/**
+  * @brief  Enables or disables the CRC value calculation of the transferred bytes.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx CRC value calculation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_CRCEN(SPI_Type* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI CRC calculation */
+    SPIx->CTRL1 |= CTRL1_CCE_SET;
+  }
+  else
+  {
+    /* Disable the selected SPI CRC calculation */
+    SPIx->CTRL1 &= CTRL1_CCE_RESET;
+  }
+}
+
+/**
+  * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @param  SPI_CRC: specifies the CRC register to be read.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_CRC_TX: Selects Tx CRC register
+  *     @arg SPI_CRC_RX: Selects Rx CRC register
+  * @retval The selected CRC register value..
+  */
+uint16_t SPI_GetCRC(SPI_Type* SPIx, uint8_t SPI_CRC)
+{
+  uint16_t crcreg = 0;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_CRC(SPI_CRC));
+
+  if (SPI_CRC != SPI_CRC_RX)
+  {
+    /* Get the Tx CRC register */
+    crcreg = SPIx->TCRC;
+  }
+  else
+  {
+    /* Get the Rx CRC register */
+    crcreg = SPIx->RCRC;
+  }
+
+  /* Return the selected CRC register */
+  return crcreg;
+}
+
+/**
+  * @brief  Returns the CRC Polynomial register value for the specified SPI.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @retval The CRC Polynomial register value.
+  */
+uint16_t SPI_GetCRCPolynomial(SPI_Type* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Return the CRC polynomial register */
+  return SPIx->CPOLY;
+}
+
+/**
+  * @brief  Selects the data transfer direction in bi-directional mode for the specified SPI.
+  * @param  SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
+  * @param  SPI_Direction: specifies the data transfer direction in bi-directional mode.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_HALFDUPLEX_TX: Selects Tx transmission direction
+  *     @arg SPI_HALFDUPLEX_RX: Selects Rx receive direction
+  * @retval None
+  */
+void SPI_HalfDuplexTransModeConfig(SPI_Type* SPIx, uint16_t SPI_Direction)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_DIRECTION(SPI_Direction));
+
+  if (SPI_Direction == SPI_HALFDUPLEX_TX)
+  {
+    /* Set the Tx only mode */
+    SPIx->CTRL1 |= SPI_HALFDUPLEX_TX;
+  }
+  else
+  {
+    /* Set the Rx only mode */
+    SPIx->CTRL1 &= SPI_HALFDUPLEX_RX;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified SPI/I2S flag is set or not.
+  * @param  SPIx: where x can be
+  *   - 1, 2, 3, or 4 in SPI mode
+  *   - 2, 3, or 4 in I2S mode
+  * @param  SPI_I2S_FLAG: specifies the SPI/I2S flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_I2S_FLAG_TE: Transmit buffer empty flag.
+  *     @arg SPI_I2S_FLAG_RNE: Receive buffer not empty flag.
+  *     @arg SPI_I2S_FLAG_BUSY: Busy flag.
+  *     @arg SPI_I2S_FLAG_OVR: Overrun flag.
+  *     @arg SPI_FLAG_MODF: Mode Fault flag.
+  *     @arg SPI_FLAG_CERR: CRC Error flag.
+  *     @arg I2S_FLAG_UDR: Underrun Error flag.
+  *     @arg I2S_FLAG_CS: Channel Side flag.
+  * @retval The new state of SPI_I2S_FLAG (SET or RESET).
+  */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_Type* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+
+  /* Check the status of the specified SPI/I2S flag */
+  if ((SPIx->STS & SPI_I2S_FLAG) != (uint16_t)RESET)
+  {
+    /* SPI_I2S_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_FLAG is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the SPI_I2S_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the SPIx CRC Error (CRCERR) flag.
+  * @param  SPIx: where x can be
+  *   - 1, 2, 3, or 4 in SPI mode
+  * @param  SPI_I2S_FLAG: specifies the SPI flag to clear.
+  *   This function clears only CRCERR flag.
+  * @note
+  *   - OVR (OverRun error) flag is cleared by software sequence: a read
+  *     operation to SPI_DT register (SPI_I2S_RxData()) followed by a read
+  *     operation to SPI_STS register (SPI_I2S_GetFlagStatus()).
+  *   - UDR (UnderRun error) flag is cleared by a read operation to
+  *     SPI_STS register (SPI_I2S_GetFlagStatus()).
+  *   - MODF (Mode Fault) flag is cleared by software sequence: a read/write
+  *     operation to SPI_STS register (SPI_I2S_GetFlagStatus()) followed by a
+  *     write operation to SPI_CTRL1 register (SPI_Enable() to enable the SPI).
+  * @retval None
+  */
+void SPI_I2S_ClearFlag(SPI_Type* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
+
+  /* Clear the selected SPI CRC Error (CRCERR) flag */
+  SPIx->STS = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified SPI/I2S interrupt has occurred or not.
+  * @param  SPIx: where x can be
+  *   - 1, 2, 3, or 4 in SPI mode
+  *   - 2, 3, or 4 in I2S mode
+  * @param  SPI_I2S_INT: specifies the SPI/I2S interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_I2S_INT_TE: Transmit buffer empty interrupt.
+  *     @arg SPI_I2S_INT_RNE: Receive buffer not empty interrupt.
+  *     @arg SPI_I2S_INT_OVR: Overrun interrupt.
+  *     @arg SPI_INT_MODF: Mode Fault interrupt.
+  *     @arg SPI_INT_CERR: CRC Error interrupt.
+  *     @arg I2S_INT_UDR: Underrun Error interrupt.
+  * @retval The new state of SPI_I2S_INT (SET or RESET).
+  */
+ITStatus SPI_I2S_GetITStatus(SPI_Type* SPIx, uint8_t SPI_I2S_INT)
+{
+  ITStatus bitstatus = RESET;
+  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_GET_INT(SPI_I2S_INT));
+
+  /* Get the SPI/I2S INT index */
+  itpos = 0x01 << (SPI_I2S_INT & 0x0F);
+
+  /* Get the SPI/I2S INT mask */
+  itmask = SPI_I2S_INT >> 4;
+
+  /* Set the INT mask */
+  itmask = 0x01 << itmask;
+
+  /* Get the SPI_I2S_INT enable bit status */
+  enablestatus = (SPIx->CTRL2 & itmask) ;
+
+  /* Check the status of the specified SPI/I2S interrupt */
+  if (((SPIx->STS & itpos) != (uint16_t)RESET) && enablestatus)
+  {
+    /* SPI_I2S_INT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_INT is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the SPI_I2S_INT status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+  * @param  SPIx: where x can be
+  *   - 1, 2, 3, or 4 in SPI mode
+  * @param  SPI_I2S_INT: specifies the SPI interrupt pending bit to clear.
+  *   This function clears only CRCERR interrupt pending bit.
+  * @note
+  *   - OVR (OverRun Error) interrupt pending bit is cleared by software
+  *     sequence: a read operation to SPI_DT register (SPI_I2S_RxData())
+  *     followed by a read operation to SPI_STS register (SPI_I2S_GetITStatus()).
+  *   - UDR (UnderRun Error) interrupt pending bit is cleared by a read
+  *     operation to SPI_STS register (SPI_I2S_GetITStatus()).
+  *   - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
+  *     a read/write operation to SPI_STS register (SPI_I2S_GetITStatus())
+  *     followed by a write operation to SPI_CTRL1 register (SPI_Enable() to enable
+  *     the SPI).
+  * @retval None
+  */
+void SPI_I2S_ClearINTPendingBit(SPI_Type* SPIx, uint8_t SPI_I2S_INT)
+{
+  uint16_t itpos = 0;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_CLEAR_INT(SPI_I2S_INT));
+
+  /* Get the SPI INT index */
+  itpos = 0x01 << (SPI_I2S_INT & 0x0F);
+
+  /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
+  SPIx->STS = (uint16_t)~itpos;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_tim.c

@@ -0,0 +1,2997 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_tim.c
+ * Description  : at32f4xx TTMER source file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_tim.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup TMR
+  * @brief TMR driver modules
+  * @{
+  */
+
+/** @defgroup TMR_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TMR_Private_Defines
+  * @{
+  */
+
+/* ---------------------- TMR registers bit mask ------------------------ */
+#define SMC_ETR_Mask               ((uint16_t)0x00FF)
+#define CCMR_Offset                ((uint16_t)0x0018)
+#define CCE_CCE_Set                ((uint16_t)0x0001)
+#define	CCE_CCNE_Set               ((uint16_t)0x0004)
+
+/**
+  * @}
+  */
+
+/** @defgroup TMR_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TMR_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TMR_Private_FunctionPrototypes
+  * @{
+  */
+
+static void TI1_Config(TMR_Type* TMRx, uint16_t TMR_ICPolarity, uint16_t TMR_ICSelection,
+                       uint16_t TMR_ICFilter);
+static void TI2_Config(TMR_Type* TMRx, uint16_t TMR_ICPolarity, uint16_t TMR_ICSelection,
+                       uint16_t TMR_ICFilter);
+static void TI3_Config(TMR_Type* TMRx, uint16_t TMR_ICPolarity, uint16_t TMR_ICSelection,
+                       uint16_t TMR_ICFilter);
+static void TI4_Config(TMR_Type* TMRx, uint16_t TMR_ICPolarity, uint16_t TMR_ICSelection,
+                       uint16_t TMR_ICFilter);
+/**
+  * @}
+  */
+
+/** @defgroup TMR_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TMR_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TMR_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TMR_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the TMRx peripheral registers to their default reset values.
+  * @param  TMRx: where x can be 1 to 15 to select the TMR peripheral.
+  * @retval None
+  */
+void TMR_Reset(TMR_Type* TMRx)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+
+  if (TMRx == TMR1)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_TMR1, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_TMR1, DISABLE);
+  }
+  else if (TMRx == TMR2)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR2, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR2, DISABLE);
+  }
+  else if (TMRx == TMR3)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR3, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR3, DISABLE);
+  }
+  else if (TMRx == TMR4)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR4, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR4, DISABLE);
+  }
+  else if (TMRx == TMR5)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR5, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR5, DISABLE);
+  }
+#if defined (AT32F403xx)
+  else if (TMRx == TMR6)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR6, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR6, DISABLE);
+  }
+  else if (TMRx == TMR7)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR7, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR7, DISABLE);
+  }
+#endif
+#if defined (AT32F403xx) || defined (AT32F413xx)
+  else if (TMRx == TMR8)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_TMR8, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_TMR8, DISABLE);
+  }
+#endif
+  else if (TMRx == TMR9)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_TMR9, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_TMR9, DISABLE);
+  }
+  else if (TMRx == TMR10)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_TMR10, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_TMR10, DISABLE);
+  }
+  else if (TMRx == TMR11)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_TMR11, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_TMR11, DISABLE);
+  }
+#if defined (AT32F403xx)
+  else if (TMRx == TMR12)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR12, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR12, DISABLE);
+  }
+  else if (TMRx == TMR13)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR13, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR13, DISABLE);
+  }
+  else if (TMRx == TMR14)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR14, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_TMR14, DISABLE);
+  }
+  else if (TMRx == TMR15)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_TMR15, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_TMR15, DISABLE);
+  }
+#endif
+}
+
+/**
+  * @brief  Initializes the TMRx Time Base Unit peripheral according to
+  *         the specified parameters in the TMR_TimeBaseInitStruct.
+  * @param  TMRx: where x can be 1 to 15 to select the TMR peripheral.
+  * @param  TMR_TimeBaseInitStruct: pointer to a TMR_TimerBaseInitType
+  *         structure that contains the configuration information for the
+  *         specified TMR peripheral.
+  * @retval None
+  */
+void TMR_TimeBaseInit(TMR_Type* TMRx, TMR_TimerBaseInitType* TMR_TimeBaseInitStruct)
+{
+  uint16_t tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  assert_param(IS_TMR_COUNTER_DIR(TMR_TimeBaseInitStruct->TMR_CounterMode));
+  assert_param(IS_TMR_CKD_DIV(TMR_TimeBaseInitStruct->TMR_ClockDivision));
+
+  tmpcr1 = TMRx->CTRL1;
+
+  if((TMRx == TMR1) || (TMRx == TMR2) ||
+#if !defined (AT32F415xx)
+     (TMRx == TMR8) ||
+#endif
+#if defined (AT32F403xx)
+     (TMRx == TMR15) ||
+#endif
+     (TMRx == TMR3) || (TMRx == TMR4) || (TMRx == TMR5))
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= (uint16_t)(~((uint16_t)(TMR_CTRL1_DIR | TMR_CTRL1_CMSEL)));
+    tmpcr1 |= (uint32_t)TMR_TimeBaseInitStruct->TMR_CounterMode;
+  }
+
+#ifdef AT32F403xx
+  if((TMRx != TMR6) && (TMRx != TMR7))
+  {
+    /* Set the clock division */
+    tmpcr1 &= (uint16_t)(~((uint16_t)TMR_CTRL1_CLKDIV));
+    tmpcr1 |= (uint32_t)TMR_TimeBaseInitStruct->TMR_ClockDivision;
+  }
+#endif
+
+  TMRx->CTRL1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TMRx->AR = TMR_TimeBaseInitStruct->TMR_Period ;
+
+  /* Set the Prescaler value */
+  TMRx->DIV = TMR_TimeBaseInitStruct->TMR_DIV;
+
+#ifdef AT32F415xx
+	if (TMRx == TMR1)
+#elif defined AT32F413xx
+    if ((TMRx == TMR1) || (TMRx == TMR8))
+#elif defined AT32F403xx
+    if ((TMRx == TMR1) || (TMRx == TMR8) || (TMRx == TMR15))
+#endif
+  {
+    /* Set the Repetition Counter value */
+    TMRx->RC = TMR_TimeBaseInitStruct->TMR_RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler and the Repetition counter
+     values immediately */
+  TMRx->EVEG = TMR_DIVReloadMode_Immediate;
+}
+
+/**
+  * @brief  Initializes the TIMx Plus Mode according to the specified
+  *         parameters.
+  * @param  TIMx: where x can be  2 or 5 to select the TIM peripheral.
+  * @param  TIMx_PLUS_MODE_STATE: eable or disable the plus mode
+  * @ex	    TMR_Plus_Mode_Enable
+  *         TMR_Plus_Mode_Disable	
+  * @retval None
+  */
+void TMR_SelectPlusMode(TMR_Type* TMRx, uint16_t TMRx_PLUS_MODE_STATE)
+{
+	/* Check the parameters */
+  assert_param(IS_TMR_PLUSMODE_PERIPH(TMRx));
+	assert_param(IS_TMR_PLUS_MODE_STATE(TMRx_PLUS_MODE_STATE));
+	/*Config TIMx plus mode*/
+	if((TMRx == TMR2) || (TMRx == TMR5))
+	{
+		/*Enable*/
+		if(TMRx_PLUS_MODE_STATE)
+		{
+			TMRx->CTRL1 &= (uint16_t)(~((uint16_t)TMR_Plus_Mode_Enable));
+			TMRx->CTRL1 |= TMRx_PLUS_MODE_STATE;
+		}
+		/*Disable*/
+		else
+		{
+			TMRx->CTRL1 &= (uint16_t)(~((uint16_t)TMR_Plus_Mode_Enable));
+			TMRx->CTRL1 |= TMRx_PLUS_MODE_STATE;
+		}
+	}
+}
+
+
+
+/**
+  * @brief  Initializes the TMRx Channel1 according to the specified
+  *         parameters in the TMR_OCInitStruct.
+  * @param  TMRx: where x can be  1 to 15 except 6 and 7 to select the TMR peripheral.
+  * @param  TMR_OCInitStruct: pointer to a TMR_OCInitType structure
+  *         that contains the configuration information for the specified TMR peripheral.
+  * @retval None
+  */
+void TMR_OC1Init(TMR_Type* TMRx, TMR_OCInitType* TMR_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST8_PERIPH(TMRx));
+  assert_param(IS_TMR_OC_MODE(TMR_OCInitStruct->TMR_OCMode));
+  assert_param(IS_TMR_OUTPUT_STATE(TMR_OCInitStruct->TMR_OutputState));
+  assert_param(IS_TMR_OC_POLARITY(TMR_OCInitStruct->TMR_OCPolarity));
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TMRx->CCE &= (uint16_t)(~(uint16_t)TMR_CCE_C1EN);
+  /* Get the TMRx CCE register value */
+  tmpccer = TMRx->CCE;
+  /* Get the TMRx CR2 register value */
+  tmpcr2 =  TMRx->CTRL2;
+
+  /* Get the TMRx CCMR1 register value */
+  tmpccmrx = TMRx->CCM1;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= (uint16_t)(~((uint16_t)TMR_CCM1_OC1MODE));
+  tmpccmrx &= (uint16_t)(~((uint16_t)TMR_CCM1_C1SEL));
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= TMR_OCInitStruct->TMR_OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)(~((uint16_t)TMR_CCE_C1P));
+  /* Set the Output Compare Polarity */
+  tmpccer |= TMR_OCInitStruct->TMR_OCPolarity;
+
+  /* Set the Output State */
+  tmpccer |= TMR_OCInitStruct->TMR_OutputState;
+
+#ifdef AT32F415xx
+	if (TMRx == TMR1)
+#elif defined AT32F413xx
+    if ((TMRx == TMR1) || (TMRx == TMR8))
+#elif defined AT32F403xx
+    if ((TMRx == TMR1) || (TMRx == TMR8) || (TMRx == TMR15))
+#endif  
+  {
+    assert_param(IS_TMR_OUTPUTN_STATE(TMR_OCInitStruct->TMR_OutputNState));
+    assert_param(IS_TMR_OCN_POLARITY(TMR_OCInitStruct->TMR_OCNPolarity));
+    assert_param(IS_TMR_OCNIDLE_STATE(TMR_OCInitStruct->TMR_OCNIdleState));
+    assert_param(IS_TMR_OCIDLE_STATE(TMR_OCInitStruct->TMR_OCIdleState));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint16_t)(~((uint16_t)TMR_CCE_C1NP));
+    /* Set the Output N Polarity */
+    tmpccer |= TMR_OCInitStruct->TMR_OCNPolarity;
+
+    /* Reset the Output N State */
+    tmpccer &= (uint16_t)(~((uint16_t)TMR_CCE_C1NEN));
+    /* Set the Output N State */
+    tmpccer |= TMR_OCInitStruct->TMR_OutputNState;
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint16_t)(~((uint16_t)TMR_CTRL2_OC1IS));
+    tmpcr2 &= (uint16_t)(~((uint16_t)TMR_CTRL2_OC1NIS));
+
+    /* Set the Output Idle state */
+    tmpcr2 |= TMR_OCInitStruct->TMR_OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= TMR_OCInitStruct->TMR_OCNIdleState;
+  }
+
+  /* Write to TMRx CR2 */
+  TMRx->CTRL2 = tmpcr2;
+
+  /* Write to TMRx CCMR1 */
+  TMRx->CCM1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TMRx->CC1 = TMR_OCInitStruct->TMR_Pulse;
+
+  /* Write to TMRx CCE */
+  TMRx->CCE = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TMRx Channel2 according to the specified
+  *         parameters in the TMR_OCInitStruct.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
+  *         the TMR peripheral.
+  * @param  TMR_OCInitStruct: pointer to a TMR_OCInitType structure
+  *         that contains the configuration information for the specified TMR peripheral.
+  * @retval None
+  */
+void TMR_OC2Init(TMR_Type* TMRx, TMR_OCInitType* TMR_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+  assert_param(IS_TMR_OC_MODE(TMR_OCInitStruct->TMR_OCMode));
+  assert_param(IS_TMR_OUTPUT_STATE(TMR_OCInitStruct->TMR_OutputState));
+  assert_param(IS_TMR_OC_POLARITY(TMR_OCInitStruct->TMR_OCPolarity));
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TMRx->CCE &= (uint16_t)(~((uint16_t)TMR_CCE_C2EN));
+
+  /* Get the TMRx CCE register value */
+  tmpccer = TMRx->CCE;
+  /* Get the TMRx CR2 register value */
+  tmpcr2 =  TMRx->CTRL2;
+
+  /* Get the TMRx CCMR1 register value */
+  tmpccmrx = TMRx->CCM1;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint16_t)(~((uint16_t)TMR_CCM1_OC2MODE));
+  tmpccmrx &= (uint16_t)(~((uint16_t)TMR_CCM1_C2SEL));
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (uint16_t)(TMR_OCInitStruct->TMR_OCMode << 8);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)(~((uint16_t)TMR_CCE_C2P));
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint16_t)(TMR_OCInitStruct->TMR_OCPolarity << 4);
+
+  /* Set the Output State */
+  tmpccer |= (uint16_t)(TMR_OCInitStruct->TMR_OutputState << 4);
+
+#ifdef AT32F415xx
+	if (TMRx == TMR1)
+#elif defined AT32F413xx
+    if ((TMRx == TMR1) || (TMRx == TMR8))
+#elif defined AT32F403xx
+    if ((TMRx == TMR1) || (TMRx == TMR8) || (TMRx == TMR15))
+#endif
+  {
+    assert_param(IS_TMR_OUTPUTN_STATE(TMR_OCInitStruct->TMR_OutputNState));
+    assert_param(IS_TMR_OCN_POLARITY(TMR_OCInitStruct->TMR_OCNPolarity));
+    assert_param(IS_TMR_OCNIDLE_STATE(TMR_OCInitStruct->TMR_OCNIdleState));
+    assert_param(IS_TMR_OCIDLE_STATE(TMR_OCInitStruct->TMR_OCIdleState));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint16_t)(~((uint16_t)TMR_CCE_C2NP));
+    /* Set the Output N Polarity */
+    tmpccer |= (uint16_t)(TMR_OCInitStruct->TMR_OCNPolarity << 4);
+
+    /* Reset the Output N State */
+    tmpccer &= (uint16_t)(~((uint16_t)TMR_CCE_C2NEN));
+    /* Set the Output N State */
+    tmpccer |= (uint16_t)(TMR_OCInitStruct->TMR_OutputNState << 4);
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint16_t)(~((uint16_t)TMR_CTRL2_OC2IS));
+    tmpcr2 &= (uint16_t)(~((uint16_t)TMR_CTRL2_OC2NIS));
+
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint16_t)(TMR_OCInitStruct->TMR_OCIdleState << 2);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (uint16_t)(TMR_OCInitStruct->TMR_OCNIdleState << 2);
+  }
+
+  /* Write to TMRx CR2 */
+  TMRx->CTRL2 = tmpcr2;
+
+  /* Write to TMRx CCMR1 */
+  TMRx->CCM1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TMRx->CC2 = TMR_OCInitStruct->TMR_Pulse;
+
+  /* Write to TMRx CCE */
+  TMRx->CCE = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TMRx Channel3 according to the specified
+  *         parameters in the TMR_OCInitStruct.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_OCInitStruct: pointer to a TMR_OCInitType structure
+  *         that contains the configuration information for the specified TMR peripheral.
+  * @retval None
+  */
+void TMR_OC3Init(TMR_Type* TMRx, TMR_OCInitType* TMR_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_OC_MODE(TMR_OCInitStruct->TMR_OCMode));
+  assert_param(IS_TMR_OUTPUT_STATE(TMR_OCInitStruct->TMR_OutputState));
+  assert_param(IS_TMR_OC_POLARITY(TMR_OCInitStruct->TMR_OCPolarity));
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TMRx->CCE &= (uint16_t)(~((uint16_t)TMR_CCE_C3EN));
+
+  /* Get the TMRx CCE register value */
+  tmpccer = TMRx->CCE;
+  /* Get the TMRx CR2 register value */
+  tmpcr2 =  TMRx->CTRL2;
+
+  /* Get the TMRx CCMR2 register value */
+  tmpccmrx = TMRx->CCM2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint16_t)(~((uint16_t)TMR_CCM2_OC3MODE));
+  tmpccmrx &= (uint16_t)(~((uint16_t)TMR_CCM2_C3SEL));
+  /* Select the Output Compare Mode */
+  tmpccmrx |= TMR_OCInitStruct->TMR_OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)(~((uint16_t)TMR_CCE_C3P));
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint16_t)(TMR_OCInitStruct->TMR_OCPolarity << 8);
+
+  /* Set the Output State */
+  tmpccer |= (uint16_t)(TMR_OCInitStruct->TMR_OutputState << 8);
+
+#ifdef AT32F415xx
+	if (TMRx == TMR1)
+#elif defined AT32F413xx
+    if ((TMRx == TMR1) || (TMRx == TMR8))
+#elif defined AT32F403xx
+    if ((TMRx == TMR1) || (TMRx == TMR8) || (TMRx == TMR15))
+#endif
+  {
+    assert_param(IS_TMR_OUTPUTN_STATE(TMR_OCInitStruct->TMR_OutputNState));
+    assert_param(IS_TMR_OCN_POLARITY(TMR_OCInitStruct->TMR_OCNPolarity));
+    assert_param(IS_TMR_OCNIDLE_STATE(TMR_OCInitStruct->TMR_OCNIdleState));
+    assert_param(IS_TMR_OCIDLE_STATE(TMR_OCInitStruct->TMR_OCIdleState));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint16_t)(~((uint16_t)TMR_CCE_C3NP));
+    /* Set the Output N Polarity */
+    tmpccer |= (uint16_t)(TMR_OCInitStruct->TMR_OCNPolarity << 8);
+    /* Reset the Output N State */
+    tmpccer &= (uint16_t)(~((uint16_t)TMR_CCE_C3NEN));
+
+    /* Set the Output N State */
+    tmpccer |= (uint16_t)(TMR_OCInitStruct->TMR_OutputNState << 8);
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint16_t)(~((uint16_t)TMR_CTRL2_OC3IS));
+    tmpcr2 &= (uint16_t)(~((uint16_t)TMR_CTRL2_OC3NIS));
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint16_t)(TMR_OCInitStruct->TMR_OCIdleState << 4);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (uint16_t)(TMR_OCInitStruct->TMR_OCNIdleState << 4);
+  }
+
+  /* Write to TMRx CR2 */
+  TMRx->CTRL2 = tmpcr2;
+
+  /* Write to TMRx CCMR2 */
+  TMRx->CCM2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TMRx->CC3 = TMR_OCInitStruct->TMR_Pulse;
+
+  /* Write to TMRx CCE */
+  TMRx->CCE = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TMRx Channel4 according to the specified
+  *         parameters in the TMR_OCInitStruct.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_OCInitStruct: pointer to a TMR_OCInitType structure
+  *         that contains the configuration information for the specified TMR peripheral.
+  * @retval None
+  */
+void TMR_OC4Init(TMR_Type* TMRx, TMR_OCInitType* TMR_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_OC_MODE(TMR_OCInitStruct->TMR_OCMode));
+  assert_param(IS_TMR_OUTPUT_STATE(TMR_OCInitStruct->TMR_OutputState));
+  assert_param(IS_TMR_OC_POLARITY(TMR_OCInitStruct->TMR_OCPolarity));
+  /* Disable the Channel 2: Reset the CC4E Bit */
+  TMRx->CCE &= (uint16_t)(~((uint16_t)TMR_CCE_C4EN));
+
+  /* Get the TMRx CCE register value */
+  tmpccer = TMRx->CCE;
+  /* Get the TMRx CR2 register value */
+  tmpcr2 =  TMRx->CTRL2;
+
+  /* Get the TMRx CCMR2 register value */
+  tmpccmrx = TMRx->CCM2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint16_t)(~((uint16_t)TMR_CCM2_OC4MODE));
+  tmpccmrx &= (uint16_t)(~((uint16_t)TMR_CCM2_CC4S));
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (uint16_t)(TMR_OCInitStruct->TMR_OCMode << 8);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)(~((uint16_t)TMR_CCE_C4P));
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint16_t)(TMR_OCInitStruct->TMR_OCPolarity << 12);
+
+  /* Set the Output State */
+  tmpccer |= (uint16_t)(TMR_OCInitStruct->TMR_OutputState << 12);
+
+#ifdef AT32F415xx
+	if (TMRx == TMR1)
+#elif defined AT32F413xx
+    if ((TMRx == TMR1) || (TMRx == TMR8))
+#elif defined AT32F403xx
+    if ((TMRx == TMR1) || (TMRx == TMR8) || (TMRx == TMR15))
+#endif
+  {
+    assert_param(IS_TMR_OCIDLE_STATE(TMR_OCInitStruct->TMR_OCIdleState));
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= (uint16_t)(~((uint16_t)TMR_CTRL2_OC4IS));
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint16_t)(TMR_OCInitStruct->TMR_OCIdleState << 6);
+  }
+
+  /* Write to TMRx CR2 */
+  TMRx->CTRL2 = tmpcr2;
+
+  /* Write to TMRx CCMR2 */
+  TMRx->CCM2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TMRx->CC4 = TMR_OCInitStruct->TMR_Pulse;
+
+  /* Write to TMRx CCE */
+  TMRx->CCE = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TMR peripheral according to the specified
+  *         parameters in the TMR_ICInitStruct.
+  * @param  TMRx: where x can be  1 to 15 except 6 and 7 to select the TMR peripheral.
+  * @param  TMR_ICInitStruct: pointer to a TMR_ICInitType structure
+  *         that contains the configuration information for the specified TMR peripheral.
+  * @retval None
+  */
+void TMR_ICInit(TMR_Type* TMRx, TMR_ICInitType* TMR_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_CHANNEL(TMR_ICInitStruct->TMR_Channel));
+  assert_param(IS_TMR_IC_SELECTION(TMR_ICInitStruct->TMR_ICSelection));
+  assert_param(IS_TMR_IC_DIV(TMR_ICInitStruct->TMR_ICDIV));
+  assert_param(IS_TMR_IC_FILTER(TMR_ICInitStruct->TMR_ICFilter));
+
+    if((TMRx == TMR1) || (TMRx == TMR2) ||
+#if !defined (AT32F415xx)
+     (TMRx == TMR8) ||
+#endif
+#if defined (AT32F403xx)
+     (TMRx == TMR15) || 
+#endif
+
+     (TMRx == TMR3) || (TMRx == TMR4) || (TMRx == TMR5))
+  {
+    assert_param(IS_TMR_IC_POLARITY(TMR_ICInitStruct->TMR_ICPolarity));
+  }
+  else
+  {
+    assert_param(IS_TMR_IC_POLARITY_LITE(TMR_ICInitStruct->TMR_ICPolarity));
+  }
+
+  if (TMR_ICInitStruct->TMR_Channel == TMR_Channel_1)
+  {
+    assert_param(IS_TMR_LIST8_PERIPH(TMRx));
+    /* TI1 Configuration */
+    TI1_Config(TMRx, TMR_ICInitStruct->TMR_ICPolarity,
+               TMR_ICInitStruct->TMR_ICSelection,
+               TMR_ICInitStruct->TMR_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TMR_SetIC1DIV(TMRx, TMR_ICInitStruct->TMR_ICDIV);
+  }
+  else if (TMR_ICInitStruct->TMR_Channel == TMR_Channel_2)
+  {
+    assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+    /* TI2 Configuration */
+    TI2_Config(TMRx, TMR_ICInitStruct->TMR_ICPolarity,
+               TMR_ICInitStruct->TMR_ICSelection,
+               TMR_ICInitStruct->TMR_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TMR_SetIC2DIV(TMRx, TMR_ICInitStruct->TMR_ICDIV);
+  }
+  else if (TMR_ICInitStruct->TMR_Channel == TMR_Channel_3)
+  {
+    assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+    /* TI3 Configuration */
+    TI3_Config(TMRx,  TMR_ICInitStruct->TMR_ICPolarity,
+               TMR_ICInitStruct->TMR_ICSelection,
+               TMR_ICInitStruct->TMR_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TMR_SetIC3DIV(TMRx, TMR_ICInitStruct->TMR_ICDIV);
+  }
+  else
+  {
+    assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+    /* TI4 Configuration */
+    TI4_Config(TMRx, TMR_ICInitStruct->TMR_ICPolarity,
+               TMR_ICInitStruct->TMR_ICSelection,
+               TMR_ICInitStruct->TMR_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TMR_SetIC4DIV(TMRx, TMR_ICInitStruct->TMR_ICDIV);
+  }
+}
+
+/**
+  * @brief  Configures the TMR peripheral according to the specified
+  *         parameters in the TMR_ICInitStruct to measure an external PWM signal.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TMR peripheral.
+  * @param  TMR_ICInitStruct: pointer to a TMR_ICInitType structure
+  *         that contains the configuration information for the specified TMR peripheral.
+  * @retval None
+  */
+void TMR_PWMIConfig(TMR_Type* TMRx, TMR_ICInitType* TMR_ICInitStruct)
+{
+  uint16_t icoppositepolarity = TMR_ICPolarity_Rising;
+  uint16_t icoppositeselection = TMR_ICSelection_DirectTI;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+
+  /* Select the Opposite Input Polarity */
+  if (TMR_ICInitStruct->TMR_ICPolarity == TMR_ICPolarity_Rising)
+  {
+    icoppositepolarity = TMR_ICPolarity_Falling;
+  }
+  else
+  {
+    icoppositepolarity = TMR_ICPolarity_Rising;
+  }
+
+  /* Select the Opposite Input */
+  if (TMR_ICInitStruct->TMR_ICSelection == TMR_ICSelection_DirectTI)
+  {
+    icoppositeselection = TMR_ICSelection_IndirectTI;
+  }
+  else
+  {
+    icoppositeselection = TMR_ICSelection_DirectTI;
+  }
+
+  if (TMR_ICInitStruct->TMR_Channel == TMR_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TMRx, TMR_ICInitStruct->TMR_ICPolarity, TMR_ICInitStruct->TMR_ICSelection,
+               TMR_ICInitStruct->TMR_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TMR_SetIC1DIV(TMRx, TMR_ICInitStruct->TMR_ICDIV);
+    /* TI2 Configuration */
+    TI2_Config(TMRx, icoppositepolarity, icoppositeselection, TMR_ICInitStruct->TMR_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TMR_SetIC2DIV(TMRx, TMR_ICInitStruct->TMR_ICDIV);
+  }
+  else
+  {
+    /* TI2 Configuration */
+    TI2_Config(TMRx, TMR_ICInitStruct->TMR_ICPolarity, TMR_ICInitStruct->TMR_ICSelection,
+               TMR_ICInitStruct->TMR_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TMR_SetIC2DIV(TMRx, TMR_ICInitStruct->TMR_ICDIV);
+    /* TI1 Configuration */
+    TI1_Config(TMRx, icoppositepolarity, icoppositeselection, TMR_ICInitStruct->TMR_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TMR_SetIC1DIV(TMRx, TMR_ICInitStruct->TMR_ICDIV);
+  }
+}
+
+/**
+  * @brief  Configures the: Break feature, dead time, Lock level, the OSSI,
+  *         the OSSR State and the AOE(automatic output enable).
+  * @param  TMRx: where x can be  1 or 8 to select the TMR
+  * @param  TMR_BDTRInitStruct: pointer to a TMR_BRKDTInitType structure that
+  *         contains the BDTR Register configuration  information for the TMR peripheral.
+  * @retval None
+  */
+void TMR_BRKDTConfig(TMR_Type* TMRx, TMR_BRKDTInitType *TMR_BDTRInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST2_PERIPH(TMRx));
+  assert_param(IS_TMR_OSIMR_STATE(TMR_BDTRInitStruct->TMR_OSIMRState));
+  assert_param(IS_TMR_OSIMI_STATE(TMR_BDTRInitStruct->TMR_OSIMIState));
+  assert_param(IS_TMR_LOCK_grade(TMR_BDTRInitStruct->TMR_LOCKgrade));
+  assert_param(IS_TMR_BREAK_STATE(TMR_BDTRInitStruct->TMR_Break));
+  assert_param(IS_TMR_BREAK_POLARITY(TMR_BDTRInitStruct->TMR_BreakPolarity));
+  assert_param(IS_TMR_AUTOMATIC_OUTPUT_STATE(TMR_BDTRInitStruct->TMR_AutomaticOutput));
+  /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+  TMRx->BRKDT = (uint32_t)TMR_BDTRInitStruct->TMR_OSIMRState | TMR_BDTRInitStruct->TMR_OSIMIState |
+                TMR_BDTRInitStruct->TMR_LOCKgrade | TMR_BDTRInitStruct->TMR_DeadTime |
+                TMR_BDTRInitStruct->TMR_Break | TMR_BDTRInitStruct->TMR_BreakPolarity |
+                TMR_BDTRInitStruct->TMR_AutomaticOutput;
+}
+
+/**
+  * @brief  Fills each TMR_TimeBaseInitStruct member with its default value.
+  * @param  TMR_TimeBaseInitStruct : pointer to a TMR_TimerBaseInitType
+  *         structure which will be initialized.
+  * @retval None
+  */
+void TMR_TimeBaseStructInit(TMR_TimerBaseInitType* TMR_TimeBaseInitStruct)
+{
+  /* Set the default configuration */
+  TMR_TimeBaseInitStruct->TMR_Period = 0xFFFF;
+  TMR_TimeBaseInitStruct->TMR_DIV = 0x0000;
+  TMR_TimeBaseInitStruct->TMR_ClockDivision = TMR_CKD_DIV1;
+  TMR_TimeBaseInitStruct->TMR_CounterMode = TMR_CounterDIR_Up;
+  TMR_TimeBaseInitStruct->TMR_RepetitionCounter = 0x0000;
+}
+
+/**
+  * @brief  Fills each TMR_OCInitStruct member with its default value.
+  * @param  TMR_OCInitStruct : pointer to a TMR_OCInitType structure which will
+  *         be initialized.
+  * @retval None
+  */
+void TMR_OCStructInit(TMR_OCInitType* TMR_OCInitStruct)
+{
+  /* Set the default configuration */
+  TMR_OCInitStruct->TMR_OCMode = TMR_OCMode_Timing;
+  TMR_OCInitStruct->TMR_OutputState = TMR_OutputState_Disable;
+  TMR_OCInitStruct->TMR_OutputNState = TMR_OutputNState_Disable;
+  TMR_OCInitStruct->TMR_Pulse = 0x0000;
+  TMR_OCInitStruct->TMR_OCPolarity = TMR_OCPolarity_High;
+  TMR_OCInitStruct->TMR_OCNPolarity = TMR_OCPolarity_High;
+  TMR_OCInitStruct->TMR_OCIdleState = TMR_OCIdleState_Reset;
+  TMR_OCInitStruct->TMR_OCNIdleState = TMR_OCNIdleState_Reset;
+}
+
+/**
+  * @brief  Fills each TMR_ICInitStruct member with its default value.
+  * @param  TMR_ICInitStruct: pointer to a TMR_ICInitType structure which will
+  *         be initialized.
+  * @retval None
+  */
+void TMR_ICStructInit(TMR_ICInitType* TMR_ICInitStruct)
+{
+  /* Set the default configuration */
+  TMR_ICInitStruct->TMR_Channel = TMR_Channel_1;
+  TMR_ICInitStruct->TMR_ICPolarity = TMR_ICPolarity_Rising;
+  TMR_ICInitStruct->TMR_ICSelection = TMR_ICSelection_DirectTI;
+  TMR_ICInitStruct->TMR_ICDIV = TMR_ICDIV_DIV1;
+  TMR_ICInitStruct->TMR_ICFilter = 0x00;
+}
+
+/**
+  * @brief  Fills each TMR_BDTRInitStruct member with its default value.
+  * @param  TMR_BDTRInitStruct: pointer to a TMR_BRKDTInitType structure which
+  *         will be initialized.
+  * @retval None
+  */
+void TMR_BRKDTStructInit(TMR_BRKDTInitType* TMR_BDTRInitStruct)
+{
+  /* Set the default configuration */
+  TMR_BDTRInitStruct->TMR_OSIMRState = TMR_OSIMRState_Disable;
+  TMR_BDTRInitStruct->TMR_OSIMIState = TMR_OSIMIState_Disable;
+  TMR_BDTRInitStruct->TMR_LOCKgrade = TMR_LOCKgrade_OFF;
+  TMR_BDTRInitStruct->TMR_DeadTime = 0x00;
+  TMR_BDTRInitStruct->TMR_Break = TMR_Break_Disable;
+  TMR_BDTRInitStruct->TMR_BreakPolarity = TMR_BreakPolarity_Low;
+  TMR_BDTRInitStruct->TMR_AutomaticOutput = TMR_AutomaticOutput_Disable;
+}
+
+/**
+  * @brief  Enables or disables the specified TMR peripheral.
+  * @param  TMRx: where x can be 1 to 15 to select the TMRx peripheral.
+  * @param  NewState: new state of the TMRx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TMR_Cmd(TMR_Type* TMRx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the TMR Counter */
+    TMRx->CTRL1 |= TMR_CTRL1_CNTEN;
+  }
+  else
+  {
+    /* Disable the TMR Counter */
+    TMRx->CTRL1 &= (uint16_t)(~((uint16_t)TMR_CTRL1_CNTEN));
+  }
+}
+
+/**
+  * @brief  Enables or disables the TMR peripheral Main Outputs.
+  * @param  TMRx: where x can be 1, 8, 15 to select the TMRx peripheral.
+  * @param  NewState: new state of the TMR peripheral Main Outputs.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TMR_CtrlPWMOutputs(TMR_Type* TMRx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST2_PERIPH(TMRx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the TMR Main Output */
+    TMRx->BRKDT |= TMR_BRKDT_MOEN;
+  }
+  else
+  {
+    /* Disable the TMR Main Output */
+    TMRx->BRKDT &= (uint16_t)(~((uint16_t)TMR_BRKDT_MOEN));
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified TMR interrupts.
+  * @param  TMRx: where x can be 1 to 15 to select the TMRx peripheral.
+  * @param  TMR_INT: specifies the TMR interrupts sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg TMR_INT_Overflow: TMR update Interrupt source
+  *     @arg TMR_INT_CC1: TMR Capture Compare 1 Interrupt source
+  *     @arg TMR_INT_CC2: TMR Capture Compare 2 Interrupt source
+  *     @arg TMR_INT_CC3: TMR Capture Compare 3 Interrupt source
+  *     @arg TMR_INT_CC4: TMR Capture Compare 4 Interrupt source
+  *     @arg TMR_INT_HALL: TMR Commutation Interrupt source
+  *     @arg TMR_INT_Trigger: TMR Trigger Interrupt source
+  *     @arg TMR_INT_Break: TMR Break Interrupt source
+  * @note
+  *   - TMR6 and TMR7 can only generate an update interrupt.
+  *   - TMR9, TMR12 and TMR15 can have only TMR_INT_Overflow, TMR_INT_CC1,
+  *      TMR_INT_CC2 or TMR_INT_Trigger.
+  *   - TMR10, TMR11, TMR13, TMR14 can have TMR_INT_Overflow or TMR_INT_CC1.
+  *   - TMR_INT_Break is used only with TMR1, TMR8 and TMR15.
+  *   - TMR_INT_HALL is used only with TMR1, TMR8, TMR15.
+  * @param  NewState: new state of the TMR interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TMR_INTConfig(TMR_Type* TMRx, uint16_t TMR_INT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  assert_param(IS_TMR_INT(TMR_INT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    TMRx->DIE |= TMR_INT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    TMRx->DIE &= (uint16_t)~TMR_INT;
+  }
+}
+
+/**
+  * @brief  Configures the TMRx event to be generate by software.
+  * @param  TMRx: where x can be 1 to 15 to select the TMR peripheral.
+  * @param  TMR_EventSource: specifies the event source.
+  *   This parameter can be one or more of the following values:
+  *     @arg TMR_EventSource_Update: Timer update Event source
+  *     @arg TMR_EventSource_CC1: Timer Capture Compare 1 Event source
+  *     @arg TMR_EventSource_CC2: Timer Capture Compare 2 Event source
+  *     @arg TMR_EventSource_CC3: Timer Capture Compare 3 Event source
+  *     @arg TMR_EventSource_CC4: Timer Capture Compare 4 Event source
+  *     @arg TMR_EventSource_HALL: Timer COM event source
+  *     @arg TMR_EventSource_Trigger: Timer Trigger Event source
+  *     @arg TMR_EventSource_Break: Timer Break event source
+  * @note
+  *   - TMR6 and TMR7 can only generate an update event.
+  *   - TMR_EventSource_HALL and TMR_EventSource_Break are used only with TMR1 and TMR8.
+  * @retval None
+  */
+void TMR_GenerateEvent(TMR_Type* TMRx, uint16_t TMR_EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  assert_param(IS_TMR_EVENT_SOURCE(TMR_EventSource));
+
+  /* Set the event sources */
+  TMRx->EVEG = TMR_EventSource;
+}
+
+/**
+  * @brief  Configures the TMRx's DMA interface.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5, 8, 15 to select
+  *   the TMR peripheral.
+  * @param  TMR_DMABase: DMA Base address.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_DMABase_CTRL1, TMR_DMABase_CTRL2, TMR_DMABase_SMC,
+  *          TMR_DMABase_DIE, TMR_DMABase_STS, TMR_DMABase_EVEG,
+  *          TMR_DMABase_CCM1, TMR_DMABase_CCM2, TMR_DMABase_CCE,
+  *          TMR_DMABase_CNT, TMR_DMABase_DIV, TMR_DMABase_AR,
+  *          TMR_DMABase_RC, TMR_DMABase_CC1, TMR_DMABase_CC2,
+  *          TMR_DMABase_CC3, TMR_DMABase_CC4, TMR_DMABase_BRKDT,
+  *          TMR_DMABase_DMAC.
+  * @param  TMR_DMABurstLength: DMA Burst length.
+  *   This parameter can be one value between:
+  *   TMR_DMABurstLength_1Transfer and TMR_DMABurstLength_18Transfers.
+  * @retval None
+  */
+void TMR_DMAConfig(TMR_Type* TMRx, uint16_t TMR_DMABase, uint16_t TMR_DMABurstLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST4_PERIPH(TMRx));
+  assert_param(IS_TMR_DMA_BASE(TMR_DMABase));
+  assert_param(IS_TMR_DMA_LENGTH(TMR_DMABurstLength));
+  /* Set the DMA Base and the DMA Burst Length */
+  TMRx->DMAC = TMR_DMABase | TMR_DMABurstLength;
+}
+
+/**
+  * @brief  Enables or disables the TMRx's DMA Requests.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5, 6, 7, 8, 15
+  *   to select the TMR peripheral.
+  * @param  TMR_DMASource: specifies the DMA Request sources.
+  *   This parameter can be any combination of the following values:
+  *     @arg TMR_DMA_Update: TMR update Interrupt source
+  *     @arg TMR_DMA_CC1: TMR Capture Compare 1 DMA source
+  *     @arg TMR_DMA_CC2: TMR Capture Compare 2 DMA source
+  *     @arg TMR_DMA_CC3: TMR Capture Compare 3 DMA source
+  *     @arg TMR_DMA_CC4: TMR Capture Compare 4 DMA source
+  *     @arg TMR_DMA_HALL: TMR Commutation DMA source
+  *     @arg TMR_DMA_Trigger: TMR Trigger DMA source
+  * @param  NewState: new state of the DMA Request sources.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TMR_DMACmd(TMR_Type* TMRx, uint16_t TMR_DMASource, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST9_PERIPH(TMRx));
+  assert_param(IS_TMR_DMA_SOURCE(TMR_DMASource));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA sources */
+    TMRx->DIE |= TMR_DMASource;
+  }
+  else
+  {
+    /* Disable the DMA sources */
+    TMRx->DIE &= (uint16_t)~TMR_DMASource;
+  }
+}
+
+/**
+  * @brief  Configures the TMRx internal Clock
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15
+  *         to select the TMR peripheral.
+  * @retval None
+  */
+void TMR_InternalClockConfig(TMR_Type* TMRx)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+  /* Disable slave mode to clock the prescaler directly with the internal clock */
+  TMRx->SMC &=  (uint16_t)(~((uint16_t)TMR_SMC_SMSEL));
+}
+
+/**
+  * @brief  Configures the TMRx Internal Trigger as External Clock
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5, 9, 12 or 15 to select the TMR peripheral.
+  * @param  TMR_ITRSource: Trigger source.
+  *   This parameter can be one of the following values:
+  * @param  TMR_TRGSEL_ITR0: Internal Trigger 0
+  * @param  TMR_TRGSEL_ITR1: Internal Trigger 1
+  * @param  TMR_TRGSEL_ITR2: Internal Trigger 2
+  * @param  TMR_TRGSEL_ITR3: Internal Trigger 3
+  * @retval None
+  */
+void TMR_ITRxExternalClockConfig(TMR_Type* TMRx, uint16_t TMR_InputTriggerSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+  assert_param(IS_TMR_INTERNAL_TRIGGER_SELECTION(TMR_InputTriggerSource));
+  /* Select the Internal Trigger */
+  TMR_SelectInputTrigger(TMRx, TMR_InputTriggerSource);
+  /* Select the External clock mode1 */
+  TMRx->SMC |= TMR_SlaveMode_External1;
+}
+
+/**
+  * @brief  Configures the TMRx Trigger as External Clock
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5, 9, 12 or 15 to select the TMR peripheral.
+  * @param  TMR_TIxExternalCLKSource: Trigger source.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
+  *     @arg TMR_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
+  *     @arg TMR_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
+  * @param  TMR_ICPolarity: specifies the TIx Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ICPolarity_Rising
+  *     @arg TMR_ICPolarity_Falling
+  * @param  ICFilter : specifies the filter value.
+  *   This parameter must be a value between 0x0 and 0xF.
+  * @retval None
+  */
+void TMR_TIxExternalClockConfig(TMR_Type* TMRx, uint16_t TMR_TIxExternalCLKSource,
+                                uint16_t TMR_ICPolarity, uint16_t ICFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+  assert_param(IS_TMR_TIXCLK_SOURCE(TMR_TIxExternalCLKSource));
+  assert_param(IS_TMR_IC_POLARITY(TMR_ICPolarity));
+  assert_param(IS_TMR_IC_FILTER(ICFilter));
+
+  /* Configure the Timer Input Clock Source */
+  if (TMR_TIxExternalCLKSource == TMR_TIxExternalCLK1Source_TI2)
+  {
+    TI2_Config(TMRx, TMR_ICPolarity, TMR_ICSelection_DirectTI, ICFilter);
+  }
+  else
+  {
+    TI1_Config(TMRx, TMR_ICPolarity, TMR_ICSelection_DirectTI, ICFilter);
+  }
+
+  /* Select the Trigger source */
+  TMR_SelectInputTrigger(TMRx, TMR_TIxExternalCLKSource);
+  /* Select the External clock mode1 */
+  TMRx->SMC |= TMR_SlaveMode_External1;
+}
+
+/**
+  * @brief  Configures the External clock Mode1
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_ExtTRGPrescaler: The external Trigger Prescaler.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ExtTRGDIV_OFF: ETRP Prescaler OFF.
+  *     @arg TMR_ExtTRGDIV_DIV2: ETRP frequency divided by 2.
+  *     @arg TMR_ExtTRGDIV_DIV4: ETRP frequency divided by 4.
+  *     @arg TMR_ExtTRGDIV_DIV8: ETRP frequency divided by 8.
+  * @param  TMR_ExtTRGPolarity: The external Trigger Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *     @arg TMR_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *   This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TMR_ETRClockMode1Config(TMR_Type* TMRx, uint16_t TMR_ExtTRGPrescaler, uint16_t TMR_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter)
+{
+  uint16_t tmpsmcr = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_EXT_DIV(TMR_ExtTRGPrescaler));
+  assert_param(IS_TMR_EXT_POLARITY(TMR_ExtTRGPolarity));
+  assert_param(IS_TMR_EXT_FILTER(ExtTRGFilter));
+  /* Configure the ETR Clock source */
+  TMR_ETRConfig(TMRx, TMR_ExtTRGPrescaler, TMR_ExtTRGPolarity, ExtTRGFilter);
+
+  /* Get the TMRx SMCR register value */
+  tmpsmcr = TMRx->SMC;
+  /* Reset the SMS Bits */
+  tmpsmcr &= (uint16_t)(~((uint16_t)TMR_SMC_SMSEL));
+  /* Select the External clock mode1 */
+  tmpsmcr |= TMR_SlaveMode_External1;
+  /* Select the Trigger selection : ETRF */
+  tmpsmcr &= (uint16_t)(~((uint16_t)TMR_SMC_TRGSEL));
+  tmpsmcr |= TMR_TRGSEL_ETRF;
+  /* Write to TMRx SMCR */
+  TMRx->SMC = tmpsmcr;
+}
+
+/**
+  * @brief  Configures the External clock Mode2
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_ExtTRGPrescaler: The external Trigger Prescaler.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ExtTRGDIV_OFF: ETRP Prescaler OFF.
+  *     @arg TMR_ExtTRGDIV_DIV2: ETRP frequency divided by 2.
+  *     @arg TMR_ExtTRGDIV_DIV4: ETRP frequency divided by 4.
+  *     @arg TMR_ExtTRGDIV_DIV8: ETRP frequency divided by 8.
+  * @param  TMR_ExtTRGPolarity: The external Trigger Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *     @arg TMR_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *   This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TMR_ETRClockMode2Config(TMR_Type* TMRx, uint16_t TMR_ExtTRGPrescaler,
+                             uint16_t TMR_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_EXT_DIV(TMR_ExtTRGPrescaler));
+  assert_param(IS_TMR_EXT_POLARITY(TMR_ExtTRGPolarity));
+  assert_param(IS_TMR_EXT_FILTER(ExtTRGFilter));
+  /* Configure the ETR Clock source */
+  TMR_ETRConfig(TMRx, TMR_ExtTRGPrescaler, TMR_ExtTRGPolarity, ExtTRGFilter);
+  /* Enable the External clock mode2 */
+  TMRx->SMC |= TMR_SMC_ECLKEN;
+}
+
+/**
+  * @brief  Configures the TMRx External Trigger (ETR).
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_ExtTRGPrescaler: The external Trigger Prescaler.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ExtTRGDIV_OFF: ETRP Prescaler OFF.
+  *     @arg TMR_ExtTRGDIV_DIV2: ETRP frequency divided by 2.
+  *     @arg TMR_ExtTRGDIV_DIV4: ETRP frequency divided by 4.
+  *     @arg TMR_ExtTRGDIV_DIV8: ETRP frequency divided by 8.
+  * @param  TMR_ExtTRGPolarity: The external Trigger Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *     @arg TMR_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *   This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TMR_ETRConfig(TMR_Type* TMRx, uint16_t TMR_ExtTRGPrescaler, uint16_t TMR_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter)
+{
+  uint16_t tmpsmcr = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_EXT_DIV(TMR_ExtTRGPrescaler));
+  assert_param(IS_TMR_EXT_POLARITY(TMR_ExtTRGPolarity));
+  assert_param(IS_TMR_EXT_FILTER(ExtTRGFilter));
+  tmpsmcr = TMRx->SMC;
+  /* Reset the ETR Bits */
+  tmpsmcr &= SMC_ETR_Mask;
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint16_t)(TMR_ExtTRGPrescaler | (uint16_t)(TMR_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+  /* Write to TMRx SMCR */
+  TMRx->SMC = tmpsmcr;
+}
+
+/**
+  * @brief  Configures the TMRx Prescaler.
+  * @param  TMRx: where x can be 1 to 15 to select the TMR peripheral.
+  * @param  Prescaler: specifies the Prescaler Register value
+  * @param  TMR_PSCReloadMode: specifies the TMR Prescaler Reload mode
+  *   This parameter can be one of the following values:
+  *     @arg TMR_DIVReloadMode_Update: The Prescaler is loaded at the update event.
+  *     @arg TMR_DIVReloadMode_Immediate: The Prescaler is loaded immediately.
+  * @retval None
+  */
+void TMR_DIVConfig(TMR_Type* TMRx, uint16_t Prescaler, uint16_t TMR_PSCReloadMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  assert_param(IS_TMR_DIV_RELOAD(TMR_PSCReloadMode));
+  /* Set the Prescaler value */
+  TMRx->DIV = Prescaler;
+  /* Set or reset the UG Bit */
+  TMRx->EVEG = TMR_PSCReloadMode;
+}
+
+/**
+  * @brief  Specifies the TMRx Counter Mode to be used.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_CounterMode: specifies the Counter Mode to be used
+  *   This parameter can be one of the following values:
+  *     @arg TMR_CounterDIR_Up: TMR Up Counting Mode
+  *     @arg TMR_CounterDIR_Down: TMR Down Counting Mode
+  *     @arg TMR_CounterDIR_CenterAligned1: TMR Center Aligned Mode1
+  *     @arg TMR_CounterDIR_CenterAligned2: TMR Center Aligned Mode2
+  *     @arg TMR_CounterDIR_CenterAligned3: TMR Center Aligned Mode3
+  * @retval None
+  */
+void TMR_CounterModeConfig(TMR_Type* TMRx, uint16_t TMR_CounterMode)
+{
+  uint16_t tmpcr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_COUNTER_DIR(TMR_CounterMode));
+  tmpcr1 = TMRx->CTRL1;
+  /* Reset the CMS and DIR Bits */
+  tmpcr1 &= (uint16_t)(~((uint16_t)(TMR_CTRL1_DIR | TMR_CTRL1_CMSEL)));
+  /* Set the Counter Mode */
+  tmpcr1 |= TMR_CounterMode;
+  /* Write to TMRx CR1 register */
+  TMRx->CTRL1 = tmpcr1;
+}
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TMR peripheral.
+  * @param  TMR_InputTriggerSource: The Input Trigger source.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_TRGSEL_ITR0: Internal Trigger 0
+  *     @arg TMR_TRGSEL_ITR1: Internal Trigger 1
+  *     @arg TMR_TRGSEL_ITR2: Internal Trigger 2
+  *     @arg TMR_TRGSEL_ITR3: Internal Trigger 3
+  *     @arg TMR_TRGSEL_TI1F_ED: TI1 Edge Detector
+  *     @arg TMR_TRGSEL_TI1FP1: Filtered Timer Input 1
+  *     @arg TMR_TRGSEL_TI2FP2: Filtered Timer Input 2
+  *     @arg TMR_TRGSEL_ETRF: External Trigger input
+  * @retval None
+  */
+void TMR_SelectInputTrigger(TMR_Type* TMRx, uint16_t TMR_InputTriggerSource)
+{
+  uint16_t tmpsmcr = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+  assert_param(IS_TMR_TRIGGER_SELECTION(TMR_InputTriggerSource));
+  /* Get the TMRx SMCR register value */
+  tmpsmcr = TMRx->SMC;
+  /* Reset the TS Bits */
+  tmpsmcr &= (uint16_t)(~((uint16_t)TMR_SMC_TRGSEL));
+  /* Set the Input Trigger source */
+  tmpsmcr |= TMR_InputTriggerSource;
+  /* Write to TMRx SMCR */
+  TMRx->SMC = tmpsmcr;
+}
+
+/**
+  * @brief  Configures the TMRx Encoder Interface.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_EncoderMode: specifies the TMRx Encoder Mode.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
+  *     @arg TMR_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
+  *     @arg TMR_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
+  *                                on the level of the other input.
+  * @param  TMR_IC1Polarity: specifies the IC1 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ICPolarity_Falling: IC Falling edge.
+  *     @arg TMR_ICPolarity_Rising: IC Rising edge.
+  * @param  TMR_IC2Polarity: specifies the IC2 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ICPolarity_Falling: IC Falling edge.
+  *     @arg TMR_ICPolarity_Rising: IC Rising edge.
+  * @retval None
+  */
+void TMR_EncoderInterfaceConfig(TMR_Type* TMRx, uint16_t TMR_EncoderMode,
+                                uint16_t TMR_IC1Polarity, uint16_t TMR_IC2Polarity)
+{
+  uint16_t tmpsmcr = 0;
+  uint16_t tmpccmr1 = 0;
+  uint16_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST5_PERIPH(TMRx));
+  assert_param(IS_TMR_ENCODER_MODE(TMR_EncoderMode));
+  assert_param(IS_TMR_IC_POLARITY(TMR_IC1Polarity));
+  assert_param(IS_TMR_IC_POLARITY(TMR_IC2Polarity));
+
+  /* Get the TMRx SMCR register value */
+  tmpsmcr = TMRx->SMC;
+
+  /* Get the TMRx CCMR1 register value */
+  tmpccmr1 = TMRx->CCM1;
+
+  /* Get the TMRx CCE register value */
+  tmpccer = TMRx->CCE;
+
+  /* Set the encoder Mode */
+  tmpsmcr &= (uint16_t)(~((uint16_t)TMR_SMC_SMSEL));
+  tmpsmcr |= TMR_EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TMR_CCM1_C1SEL)) & (uint16_t)(~((uint16_t)TMR_CCM1_C2SEL)));
+  tmpccmr1 |= TMR_CCM1_C1SEL_0 | TMR_CCM1_C2SEL_0;
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TMR_CCE_C1P)) & ((uint16_t)~((uint16_t)TMR_CCE_C2P)));
+  tmpccer |= (uint16_t)(TMR_IC1Polarity | (uint16_t)(TMR_IC2Polarity << (uint16_t)4));
+
+  /* Write to TMRx SMCR */
+  TMRx->SMC = tmpsmcr;
+  /* Write to TMRx CCMR1 */
+  TMRx->CCM1 = tmpccmr1;
+  /* Write to TMRx CCE */
+  TMRx->CCE = tmpccer;
+}
+
+/**
+  * @brief  Forces the TMRx output 1 waveform to active or inactive level.
+  * @param  TMRx: where x can be  1 to 15 except 6 and 7 to select the TMR peripheral.
+  * @param  TMR_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ForcedAction_Active: Force active level on OC1REF
+  *     @arg TMR_ForcedAction_InActive: Force inactive level on OC1REF.
+  * @retval None
+  */
+void TMR_ForcedOC1Config(TMR_Type* TMRx, uint16_t TMR_ForcedAction)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST8_PERIPH(TMRx));
+  assert_param(IS_TMR_FORCED_ACTION(TMR_ForcedAction));
+  tmpccmr1 = TMRx->CCM1;
+  /* Reset the OC1M Bits */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TMR_CCM1_OC1MODE);
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= TMR_ForcedAction;
+  /* Write to TMRx CCMR1 register */
+  TMRx->CCM1 = tmpccmr1;
+}
+
+/**
+  * @brief  Forces the TMRx output 2 waveform to active or inactive level.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TMR peripheral.
+  * @param  TMR_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ForcedAction_Active: Force active level on OC2REF
+  *     @arg TMR_ForcedAction_InActive: Force inactive level on OC2REF.
+  * @retval None
+  */
+void TMR_ForcedOC2Config(TMR_Type* TMRx, uint16_t TMR_ForcedAction)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+  assert_param(IS_TMR_FORCED_ACTION(TMR_ForcedAction));
+  tmpccmr1 = TMRx->CCM1;
+  /* Reset the OC2M Bits */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TMR_CCM1_OC2MODE);
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= (uint16_t)(TMR_ForcedAction << 8);
+  /* Write to TMRx CCMR1 register */
+  TMRx->CCM1 = tmpccmr1;
+}
+
+/**
+  * @brief  Forces the TMRx output 3 waveform to active or inactive level.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ForcedAction_Active: Force active level on OC3REF
+  *     @arg TMR_ForcedAction_InActive: Force inactive level on OC3REF.
+  * @retval None
+  */
+void TMR_ForcedOC3Config(TMR_Type* TMRx, uint16_t TMR_ForcedAction)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_FORCED_ACTION(TMR_ForcedAction));
+  tmpccmr2 = TMRx->CCM2;
+  /* Reset the OC1M Bits */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TMR_CCM2_OC3MODE);
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= TMR_ForcedAction;
+  /* Write to TMRx CCMR2 register */
+  TMRx->CCM2 = tmpccmr2;
+}
+
+/**
+  * @brief  Forces the TMRx output 4 waveform to active or inactive level.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ForcedAction_Active: Force active level on OC4REF
+  *     @arg TMR_ForcedAction_InActive: Force inactive level on OC4REF.
+  * @retval None
+  */
+void TMR_ForcedOC4Config(TMR_Type* TMRx, uint16_t TMR_ForcedAction)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_FORCED_ACTION(TMR_ForcedAction));
+  tmpccmr2 = TMRx->CCM2;
+  /* Reset the OC2M Bits */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TMR_CCM2_OC4MODE);
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= (uint16_t)(TMR_ForcedAction << 8);
+  /* Write to TMRx CCMR2 register */
+  TMRx->CCM2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or disables TMRx peripheral Preload register on ARR.
+  * @param  TMRx: where x can be  1 to 15 to select the TMR peripheral.
+  * @param  NewState: new state of the TMRx peripheral Preload register
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TMR_ARPreloadConfig(TMR_Type* TMRx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the ARR Preload Bit */
+    TMRx->CTRL1 |= TMR_CTRL1_ARPEN;
+  }
+  else
+  {
+    /* Reset the ARR Preload Bit */
+    TMRx->CTRL1 &= (uint16_t)~((uint16_t)TMR_CTRL1_ARPEN);
+  }
+}
+
+/**
+  * @brief  Selects the TMR peripheral Commutation event.
+  * @param  TMRx: where x can be  1, 8, 15 to select the TMRx peripheral
+  * @param  NewState: new state of the Commutation event.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TMR_SelectHALL(TMR_Type* TMRx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST2_PERIPH(TMRx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the COM Bit */
+    TMRx->CTRL2 |= TMR_CTRL2_CUSEL;
+  }
+  else
+  {
+    /* Reset the COM Bit */
+    TMRx->CTRL2 &= (uint16_t)~((uint16_t)TMR_CTRL2_CUSEL);
+  }
+}
+
+/**
+  * @brief  Selects the TMRx peripheral Capture Compare DMA source.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5, 8, 15 to select
+  *         the TMR peripheral.
+  * @param  NewState: new state of the Capture Compare DMA source
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TMR_SelectCCDMA(TMR_Type* TMRx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST4_PERIPH(TMRx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the CCDS Bit */
+    TMRx->CTRL2 |= TMR_CTRL2_CDSEL;
+  }
+  else
+  {
+    /* Reset the CCDS Bit */
+    TMRx->CTRL2 &= (uint16_t)~((uint16_t)TMR_CTRL2_CDSEL);
+  }
+}
+
+/**
+  * @brief  Sets or Resets the TMR peripheral Capture Compare Preload Control bit.
+  * @param  TMRx: where x can be   1, 2, 3, 4, 5, 8 or 15
+  *         to select the TMRx peripheral
+  * @param  NewState: new state of the Capture Compare Preload Control bit
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TMR_CCPreloadControl(TMR_Type* TMRx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST5_PERIPH(TMRx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the CCPC Bit */
+    TMRx->CTRL2 |= TMR_CTRL2_CPC;
+  }
+  else
+  {
+    /* Reset the CCPC Bit */
+    TMRx->CTRL2 &= (uint16_t)~((uint16_t)TMR_CTRL2_CPC);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TMRx peripheral Preload register on CCR1.
+  * @param  TMRx: where x can be  1 to 15 except 6 and 7 to select the TMR peripheral.
+  * @param  TMR_OCPreload: new state of the TMRx peripheral Preload register
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCPreload_Enable
+  *     @arg TMR_OCPreload_Disable
+  * @retval None
+  */
+void TMR_OC1PreloadConfig(TMR_Type* TMRx, uint16_t TMR_OCPreload)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST8_PERIPH(TMRx));
+  assert_param(IS_TMR_OCPRELOAD_STATE(TMR_OCPreload));
+  tmpccmr1 = TMRx->CCM1;
+  /* Reset the OC1PE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TMR_CCM1_OC1PEN);
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr1 |= TMR_OCPreload;
+  /* Write to TMRx CCMR1 register */
+  TMRx->CCM1 = tmpccmr1;
+}
+
+/**
+  * @brief  Enables or disables the TMRx peripheral Preload register on CCR2.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
+  *         the TMR peripheral.
+  * @param  TMR_OCPreload: new state of the TMRx peripheral Preload register
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCPreload_Enable
+  *     @arg TMR_OCPreload_Disable
+  * @retval None
+  */
+void TMR_OC2PreloadConfig(TMR_Type* TMRx, uint16_t TMR_OCPreload)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+  assert_param(IS_TMR_OCPRELOAD_STATE(TMR_OCPreload));
+  tmpccmr1 = TMRx->CCM1;
+  /* Reset the OC2PE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TMR_CCM1_OC2PEN);
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr1 |= (uint16_t)(TMR_OCPreload << 8);
+  /* Write to TMRx CCMR1 register */
+  TMRx->CCM1 = tmpccmr1;
+}
+
+/**
+  * @brief  Enables or disables the TMRx peripheral Preload register on CCR3.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_OCPreload: new state of the TMRx peripheral Preload register
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCPreload_Enable
+  *     @arg TMR_OCPreload_Disable
+  * @retval None
+  */
+void TMR_OC3PreloadConfig(TMR_Type* TMRx, uint16_t TMR_OCPreload)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_OCPRELOAD_STATE(TMR_OCPreload));
+  tmpccmr2 = TMRx->CCM2;
+  /* Reset the OC3PE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TMR_CCM2_OC3PEN);
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr2 |= TMR_OCPreload;
+  /* Write to TMRx CCMR2 register */
+  TMRx->CCM2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or disables the TMRx peripheral Preload register on CCR4.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_OCPreload: new state of the TMRx peripheral Preload register
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCPreload_Enable
+  *     @arg TMR_OCPreload_Disable
+  * @retval None
+  */
+void TMR_OC4PreloadConfig(TMR_Type* TMRx, uint16_t TMR_OCPreload)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_OCPRELOAD_STATE(TMR_OCPreload));
+  tmpccmr2 = TMRx->CCM2;
+  /* Reset the OC4PE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TMR_CCM2_OC4PE);
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr2 |= (uint16_t)(TMR_OCPreload << 8);
+  /* Write to TMRx CCMR2 register */
+  TMRx->CCM2 = tmpccmr2;
+}
+
+/**
+  * @brief  Configures the TMRx Output Compare 1 Fast feature.
+  * @param  TMRx: where x can be  1 to 15 except 6 and 7 to select the TMR peripheral.
+  * @param  TMR_OCFast: new state of the Output Compare Fast Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCFast_Enable: TMR output compare fast enable
+  *     @arg TMR_OCFast_Disable: TMR output compare fast disable
+  * @retval None
+  */
+void TMR_OC1FastConfig(TMR_Type* TMRx, uint16_t TMR_OCFast)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST8_PERIPH(TMRx));
+  assert_param(IS_TMR_OCFAST_STATE(TMR_OCFast));
+  /* Get the TMRx CCMR1 register value */
+  tmpccmr1 = TMRx->CCM1;
+  /* Reset the OC1FE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TMR_CCM1_OC1FEN);
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr1 |= TMR_OCFast;
+  /* Write to TMRx CCMR1 */
+  TMRx->CCM1 = tmpccmr1;
+}
+
+/**
+  * @brief  Configures the TMRx Output Compare 2 Fast feature.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
+  *         the TMR peripheral.
+  * @param  TMR_OCFast: new state of the Output Compare Fast Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCFast_Enable: TMR output compare fast enable
+  *     @arg TMR_OCFast_Disable: TMR output compare fast disable
+  * @retval None
+  */
+void TMR_OC2FastConfig(TMR_Type* TMRx, uint16_t TMR_OCFast)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+  assert_param(IS_TMR_OCFAST_STATE(TMR_OCFast));
+  /* Get the TMRx CCMR1 register value */
+  tmpccmr1 = TMRx->CCM1;
+  /* Reset the OC2FE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TMR_CCM1_OC2FNE);
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr1 |= (uint16_t)(TMR_OCFast << 8);
+  /* Write to TMRx CCMR1 */
+  TMRx->CCM1 = tmpccmr1;
+}
+
+/**
+  * @brief  Configures the TMRx Output Compare 3 Fast feature.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_OCFast: new state of the Output Compare Fast Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCFast_Enable: TMR output compare fast enable
+  *     @arg TMR_OCFast_Disable: TMR output compare fast disable
+  * @retval None
+  */
+void TMR_OC3FastConfig(TMR_Type* TMRx, uint16_t TMR_OCFast)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_OCFAST_STATE(TMR_OCFast));
+  /* Get the TMRx CCMR2 register value */
+  tmpccmr2 = TMRx->CCM2;
+  /* Reset the OC3FE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TMR_CCM2_OC3FEN);
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr2 |= TMR_OCFast;
+  /* Write to TMRx CCMR2 */
+  TMRx->CCM2 = tmpccmr2;
+}
+
+/**
+  * @brief  Configures the TMRx Output Compare 4 Fast feature.
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_OCFast: new state of the Output Compare Fast Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCFast_Enable: TMR output compare fast enable
+  *     @arg TMR_OCFast_Disable: TMR output compare fast disable
+  * @retval None
+  */
+void TMR_OC4FastConfig(TMR_Type* TMRx, uint16_t TMR_OCFast)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_OCFAST_STATE(TMR_OCFast));
+  /* Get the TMRx CCMR2 register value */
+  tmpccmr2 = TMRx->CCM2;
+  /* Reset the OC4FE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TMR_CCM2_OC4FE);
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr2 |= (uint16_t)(TMR_OCFast << 8);
+  /* Write to TMRx CCMR2 */
+  TMRx->CCM2 = tmpccmr2;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF1 signal on an external event
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_OCClear: new state of the Output Compare Clear Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCClear_Enable: TMR Output clear enable
+  *     @arg TMR_OCClear_Disable: TMR Output clear disable
+  * @retval None
+  */
+void TMR_ClearOC1Ref(TMR_Type* TMRx, uint16_t TMR_OCClear)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_OCCLEAR_STATE(TMR_OCClear));
+
+  tmpccmr1 = TMRx->CCM1;
+
+  /* Reset the OC1CE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TMR_CCM1_C1CDIS);
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr1 |= TMR_OCClear;
+  /* Write to TMRx CCMR1 register */
+  TMRx->CCM1 = tmpccmr1;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF2 signal on an external event
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_OCClear: new state of the Output Compare Clear Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCClear_Enable: TMR Output clear enable
+  *     @arg TMR_OCClear_Disable: TMR Output clear disable
+  * @retval None
+  */
+void TMR_ClearOC2Ref(TMR_Type* TMRx, uint16_t TMR_OCClear)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_OCCLEAR_STATE(TMR_OCClear));
+  tmpccmr1 = TMRx->CCM1;
+  /* Reset the OC2CE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TMR_CCM1_OC2CDIS);
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr1 |= (uint16_t)(TMR_OCClear << 8);
+  /* Write to TMRx CCMR1 register */
+  TMRx->CCM1 = tmpccmr1;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF3 signal on an external event
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_OCClear: new state of the Output Compare Clear Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCClear_Enable: TMR Output clear enable
+  *     @arg TMR_OCClear_Disable: TMR Output clear disable
+  * @retval None
+  */
+void TMR_ClearOC3Ref(TMR_Type* TMRx, uint16_t TMR_OCClear)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_OCCLEAR_STATE(TMR_OCClear));
+  tmpccmr2 = TMRx->CCM2;
+  /* Reset the OC3CE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TMR_CCM2_OC3CDIS);
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr2 |= TMR_OCClear;
+  /* Write to TMRx CCMR2 register */
+  TMRx->CCM2 = tmpccmr2;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF4 signal on an external event
+  * @param  TMRx: where x can be  1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_OCClear: new state of the Output Compare Clear Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCClear_Enable: TMR Output clear enable
+  *     @arg TMR_OCClear_Disable: TMR Output clear disable
+  * @retval None
+  */
+void TMR_ClearOC4Ref(TMR_Type* TMRx, uint16_t TMR_OCClear)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_OCCLEAR_STATE(TMR_OCClear));
+  tmpccmr2 = TMRx->CCM2;
+  /* Reset the OC4CE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TMR_CCM2_OC4CDIS);
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr2 |= (uint16_t)(TMR_OCClear << 8);
+  /* Write to TMRx CCMR2 register */
+  TMRx->CCM2 = tmpccmr2;
+}
+
+/**
+  * @brief  Configures the TMRx channel 1 polarity.
+  * @param  TMRx: where x can be 1 to 15 except 6 and 7 to select the TMR peripheral.
+  * @param  TMR_OCPolarity: specifies the OC1 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCPolarity_High: Output Compare active high
+  *     @arg TMR_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TMR_OC1PolarityConfig(TMR_Type* TMRx, uint16_t TMR_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST8_PERIPH(TMRx));
+  assert_param(IS_TMR_OC_POLARITY(TMR_OCPolarity));
+  tmpccer = TMRx->CCE;
+  /* Set or Reset the CC1P Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TMR_CCE_C1P);
+  tmpccer |= TMR_OCPolarity;
+  /* Write to TMRx CCE register */
+  TMRx->CCE = tmpccer;
+}
+
+/**
+  * @brief  Configures the TMRx Channel 1N polarity.
+  * @param  TMRx: where x can be 1, 8, 15 to select the TMR peripheral.
+  * @param  TMR_OCNPolarity: specifies the OC1N Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCNPolarity_High: Output Compare active high
+  *     @arg TMR_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TMR_OC1NPolarityConfig(TMR_Type* TMRx, uint16_t TMR_OCNPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST2_PERIPH(TMRx));
+  assert_param(IS_TMR_OCN_POLARITY(TMR_OCNPolarity));
+
+  tmpccer = TMRx->CCE;
+  /* Set or Reset the CC1NP Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TMR_CCE_C1NP);
+  tmpccer |= TMR_OCNPolarity;
+  /* Write to TMRx CCE register */
+  TMRx->CCE = tmpccer;
+}
+
+/**
+  * @brief  Configures the TMRx channel 2 polarity.
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TMR peripheral.
+  * @param  TMR_OCPolarity: specifies the OC2 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCPolarity_High: Output Compare active high
+  *     @arg TMR_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TMR_OC2PolarityConfig(TMR_Type* TMRx, uint16_t TMR_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+  assert_param(IS_TMR_OC_POLARITY(TMR_OCPolarity));
+  tmpccer = TMRx->CCE;
+  /* Set or Reset the CC2P Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TMR_CCE_C2P);
+  tmpccer |= (uint16_t)(TMR_OCPolarity << 4);
+  /* Write to TMRx CCE register */
+  TMRx->CCE = tmpccer;
+}
+
+/**
+  * @brief  Configures the TMRx Channel 2N polarity.
+  * @param  TMRx: where x can be 1 or 8 to select the TMR peripheral.
+  * @param  TMR_OCNPolarity: specifies the OC2N Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCNPolarity_High: Output Compare active high
+  *     @arg TMR_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TMR_OC2NPolarityConfig(TMR_Type* TMRx, uint16_t TMR_OCNPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST1_PERIPH(TMRx));
+  assert_param(IS_TMR_OCN_POLARITY(TMR_OCNPolarity));
+
+  tmpccer = TMRx->CCE;
+  /* Set or Reset the CC2NP Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TMR_CCE_C2NP);
+  tmpccer |= (uint16_t)(TMR_OCNPolarity << 4);
+  /* Write to TMRx CCE register */
+  TMRx->CCE = tmpccer;
+}
+
+/**
+  * @brief  Configures the TMRx channel 3 polarity.
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_OCPolarity: specifies the OC3 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCPolarity_High: Output Compare active high
+  *     @arg TMR_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TMR_OC3PolarityConfig(TMR_Type* TMRx, uint16_t TMR_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_OC_POLARITY(TMR_OCPolarity));
+  tmpccer = TMRx->CCE;
+  /* Set or Reset the CC3P Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TMR_CCE_C3P);
+  tmpccer |= (uint16_t)(TMR_OCPolarity << 8);
+  /* Write to TMRx CCE register */
+  TMRx->CCE = tmpccer;
+}
+
+/**
+  * @brief  Configures the TMRx Channel 3N polarity.
+  * @param  TMRx: where x can be 1 or 8 to select the TMR peripheral.
+  * @param  TMR_OCNPolarity: specifies the OC3N Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCNPolarity_High: Output Compare active high
+  *     @arg TMR_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TMR_OC3NPolarityConfig(TMR_Type* TMRx, uint16_t TMR_OCNPolarity)
+{
+  uint16_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST1_PERIPH(TMRx));
+  assert_param(IS_TMR_OCN_POLARITY(TMR_OCNPolarity));
+
+  tmpccer = TMRx->CCE;
+  /* Set or Reset the CC3NP Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TMR_CCE_C3NP);
+  tmpccer |= (uint16_t)(TMR_OCNPolarity << 8);
+  /* Write to TMRx CCER register */
+  TMRx->CCE = tmpccer;
+}
+
+/**
+  * @brief  Configures the TMRx channel 4 polarity.
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_OCPolarity: specifies the OC4 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCPolarity_High: Output Compare active high
+  *     @arg TMR_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TMR_OC4PolarityConfig(TMR_Type* TMRx, uint16_t TMR_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_OC_POLARITY(TMR_OCPolarity));
+  tmpccer = TMRx->CCE;
+  /* Set or Reset the CC4P Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TMR_CCE_C4P);
+  tmpccer |= (uint16_t)(TMR_OCPolarity << 12);
+  /* Write to TMRx CCE register */
+  TMRx->CCE = tmpccer;
+}
+
+/**
+  * @brief  Enables or disables the TMR Capture Compare Channel x.
+  * @param  TMRx: where x can be 1 to 15 except 6 and 7 to select the TMR peripheral.
+  * @param  TMR_Channel: specifies the TMR Channel
+  *   This parameter can be one of the following values:
+  *     @arg TMR_Channel_1: TMR Channel 1
+  *     @arg TMR_Channel_2: TMR Channel 2
+  *     @arg TMR_Channel_3: TMR Channel 3
+  *     @arg TMR_Channel_4: TMR Channel 4
+  * @param  TMR_CCx: specifies the TMR Channel CCxE bit new state.
+  *   This parameter can be: TMR_CCx_Enable or TMR_CCx_Disable.
+  * @retval None
+  */
+void TMR_CCxCmd(TMR_Type* TMRx, uint16_t TMR_Channel, uint16_t TMR_CCx)
+{
+  uint16_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST8_PERIPH(TMRx));
+  assert_param(IS_TMR_CHANNEL(TMR_Channel));
+  assert_param(IS_TMR_CCX(TMR_CCx));
+
+  tmp = CCE_CCE_Set << TMR_Channel;
+
+  /* Reset the CCxE Bit */
+  TMRx->CCE &= (uint16_t)~ tmp;
+
+  /* Set or reset the CCxE Bit */
+  TMRx->CCE |=  (uint16_t)(TMR_CCx << TMR_Channel);
+}
+
+/**
+  * @brief  Enables or disables the TMR Capture Compare Channel xN.
+  * @param  TMRx: where x can be 1, 8, 15 to select the TMR peripheral.
+  * @param  TMR_Channel: specifies the TMR Channel
+  *   This parameter can be one of the following values:
+  *     @arg TMR_Channel_1: TMR Channel 1
+  *     @arg TMR_Channel_2: TMR Channel 2
+  *     @arg TMR_Channel_3: TMR Channel 3
+  * @param  TMR_CCxN: specifies the TMR Channel CCxNE bit new state.
+  *   This parameter can be: TMR_CCxN_Enable or TMR_CCxN_Disable.
+  * @retval None
+  */
+void TMR_CCxNCmd(TMR_Type* TMRx, uint16_t TMR_Channel, uint16_t TMR_CCxN)
+{
+  uint16_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST2_PERIPH(TMRx));
+  assert_param(IS_TMR_COMPLEMENTARY_CHANNEL(TMR_Channel));
+  assert_param(IS_TMR_CCXN(TMR_CCxN));
+
+  tmp = CCE_CCNE_Set << TMR_Channel;
+
+  /* Reset the CCxNE Bit */
+  TMRx->CCE &= (uint16_t) ~tmp;
+
+  /* Set or reset the CCxNE Bit */
+  TMRx->CCE |=  (uint16_t)(TMR_CCxN << TMR_Channel);
+}
+
+/**
+  * @brief  Selects the TMR Output Compare Mode.
+  * @note   This function disables the selected channel before changing the Output
+  *         Compare Mode.
+  *         User has to enable this channel using TMR_CCxCmd and TMR_CCxNCmd functions.
+  * @param  TMRx: where x can be 1 to 15 except 6 and 7 to select the TMR peripheral.
+  * @param  TMR_Channel: specifies the TMR Channel
+  *   This parameter can be one of the following values:
+  *     @arg TMR_Channel_1: TMR Channel 1
+  *     @arg TMR_Channel_2: TMR Channel 2
+  *     @arg TMR_Channel_3: TMR Channel 3
+  *     @arg TMR_Channel_4: TMR Channel 4
+  * @param  TMR_OCMode: specifies the TMR Output Compare Mode.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OCMode_Timing
+  *     @arg TMR_OCMode_Active
+  *     @arg TMR_OCMode_Toggle
+  *     @arg TMR_OCMode_PWM1
+  *     @arg TMR_OCMode_PWM2
+  *     @arg TMR_ForcedAction_Active
+  *     @arg TMR_ForcedAction_InActive
+  * @retval None
+  */
+void TMR_SelectOCxM(TMR_Type* TMRx, uint16_t TMR_Channel, uint16_t TMR_OCMode)
+{
+  uint32_t tmp = 0;
+  uint16_t tmp1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST8_PERIPH(TMRx));
+  assert_param(IS_TMR_CHANNEL(TMR_Channel));
+  assert_param(IS_TMR_OCM(TMR_OCMode));
+
+  tmp = (uint32_t) TMRx;
+  tmp += CCMR_Offset;
+
+  tmp1 = CCE_CCE_Set << (uint16_t)TMR_Channel;
+
+  /* Disable the Channel: Reset the CCxE Bit */
+  TMRx->CCE &= (uint16_t) ~tmp1;
+
+  if((TMR_Channel == TMR_Channel_1) || (TMR_Channel == TMR_Channel_3))
+  {
+    tmp += (TMR_Channel >> 1);
+
+    /* Reset the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TMR_CCM1_OC1MODE);
+
+    /* Configure the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp |= TMR_OCMode;
+  }
+  else
+  {
+    tmp += (uint16_t)(TMR_Channel - (uint16_t)4) >> (uint16_t)1;
+
+    /* Reset the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TMR_CCM1_OC2MODE);
+
+    /* Configure the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp |= (uint16_t)(TMR_OCMode << 8);
+  }
+}
+
+/**
+  * @brief  Enables or Disables the TMRx Update event.
+  * @param  TMRx: where x can be 1 to 15 to select the TMR peripheral.
+  * @param  NewState: new state of the TMRx UDIS bit
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TMR_UpdateDisableConfig(TMR_Type* TMRx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the Update Disable Bit */
+    TMRx->CTRL1 |= TMR_CTRL1_UEVDIS;
+  }
+  else
+  {
+    /* Reset the Update Disable Bit */
+    TMRx->CTRL1 &= (uint16_t)~((uint16_t)TMR_CTRL1_UEVDIS);
+  }
+}
+
+/**
+  * @brief  Configures the TMRx Update Request Interrupt source.
+  * @param  TMRx: where x can be 1 to 15 to select the TMR peripheral.
+  * @param  TMR_UpdateSource: specifies the Update source.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_UpdateSource_Regular: Source of update is the counter overflow/underflow
+                                       or the setting of UG bit, or an update generation
+                                       through the slave mode controller.
+  *     @arg TMR_UpdateSource_Global: Source of update is counter overflow/underflow.
+  * @retval None
+  */
+void TMR_UpdateRequestConfig(TMR_Type* TMRx, uint16_t TMR_UpdateSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  assert_param(IS_TMR_UPDATE_SOURCE(TMR_UpdateSource));
+
+  if (TMR_UpdateSource != TMR_UpdateSource_Global)
+  {
+    /* Set the URS Bit */
+    TMRx->CTRL1 |= TMR_CTRL1_UVERS;
+  }
+  else
+  {
+    /* Reset the URS Bit */
+    TMRx->CTRL1 &= (uint16_t)~((uint16_t)TMR_CTRL1_UVERS);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TMRx's Hall sensor interface.
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  NewState: new state of the TMRx Hall sensor interface.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TMR_SelectHallSensor(TMR_Type* TMRx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the TI1S Bit */
+    TMRx->CTRL2 |= TMR_CTRL2_TI1SEL;
+  }
+  else
+  {
+    /* Reset the TI1S Bit */
+    TMRx->CTRL2 &= (uint16_t)~((uint16_t)TMR_CTRL2_TI1SEL);
+  }
+}
+
+/**
+  * @brief  Selects the TMRx's One Pulse Mode.
+  * @param  TMRx: where x can be 1 to 15 to select the TMR peripheral.
+  * @param  TMR_OPMode: specifies the OPM Mode to be used.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_OPMode_Once
+  *     @arg TMR_OPMode_Repetitive
+  * @retval None
+  */
+void TMR_SelectOnePulseMode(TMR_Type* TMRx, uint16_t TMR_OPMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  assert_param(IS_TMR_OPM_MODE(TMR_OPMode));
+  /* Reset the OPM Bit */
+  TMRx->CTRL1 &= (uint16_t)~((uint16_t)TMR_CTRL1_OPMODE);
+  /* Configure the OPM Mode */
+  TMRx->CTRL1 |= TMR_OPMode;
+}
+
+/**
+  * @brief  Selects the TMRx Trigger Output Mode.
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TMR peripheral.
+  * @param  TMR_TRGOSource: specifies the Trigger Output source.
+  *   This paramter can be one of the following values:
+  *
+  *  - For all TMRx
+  *     @arg TMR_TRGOSource_Reset:  The UG bit in the TMR_EGR register is used as the trigger output (TRGO).
+  *     @arg TMR_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
+  *     @arg TMR_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
+  *
+  *  - For all TMRx except TMR6 and TMR7
+  *     @arg TMR_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
+  *                              is to be set, as soon as a capture or compare match occurs (TRGO).
+  *     @arg TMR_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
+  *     @arg TMR_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
+  *     @arg TMR_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
+  *     @arg TMR_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
+  *
+  * @retval None
+  */
+void TMR_SelectOutputTrigger(TMR_Type* TMRx, uint16_t TMR_TRGOSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST7_PERIPH(TMRx));
+  assert_param(IS_TMR_TRGO_SOURCE(TMR_TRGOSource));
+  /* Reset the MMS Bits */
+  TMRx->CTRL2 &= (uint16_t)~((uint16_t)TMR_CTRL2_MMSEL);
+  /* Select the TRGO source */
+  TMRx->CTRL2 |=  TMR_TRGOSource;
+}
+
+/**
+  * @brief  Selects the TMRx Slave Mode.
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TMR peripheral.
+  * @param  TMR_SlaveMode: specifies the Timer Slave Mode.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
+  *                               the counter and triggers an update of the registers.
+  *     @arg TMR_SlaveMode_Gate:     The counter clock is enabled when the trigger signal (TRGI) is high.
+  *     @arg TMR_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI.
+  *     @arg TMR_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
+  * @retval None
+  */
+void TMR_SelectSlaveMode(TMR_Type* TMRx, uint16_t TMR_SlaveMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+  assert_param(IS_TMR_SLAVE_MODE(TMR_SlaveMode));
+  /* Reset the SMS Bits */
+  TMRx->SMC &= (uint16_t)~((uint16_t)TMR_SMC_SMSEL);
+  /* Select the Slave Mode */
+  TMRx->SMC |= TMR_SlaveMode;
+}
+
+/**
+  * @brief  Sets or Resets the TMRx Master/Slave Mode.
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TMR peripheral.
+  * @param  TMR_MasterSlaveMode: specifies the Timer Master Slave Mode.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_MasterSlaveMode_Enable: synchronization between the current timer
+  *                                      and its slaves (through TRGO).
+  *     @arg TMR_MasterSlaveMode_Disable: No action
+  * @retval None
+  */
+void TMR_SelectMasterSlaveMode(TMR_Type* TMRx, uint16_t TMR_MasterSlaveMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+  assert_param(IS_TMR_MSMODE_STATE(TMR_MasterSlaveMode));
+  /* Reset the MSM Bit */
+  TMRx->SMC &= (uint16_t)~((uint16_t)TMR_SMC_MSMODE);
+
+  /* Set or Reset the MSM Bit */
+  TMRx->SMC |= TMR_MasterSlaveMode;
+}
+
+/**
+  * @brief  Sets the TMRx Counter Register value
+  * @param  TMRx: where x can be 1 to 15 to select the TMR peripheral.
+  * @param  Counter: specifies the Counter register new value.
+  * @retval None
+  */
+void TMR_SetCounter(TMR_Type* TMRx, uint32_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  /* Set the Counter Register value */
+  TMRx->CNT = Counter;
+}
+
+/**
+  * @brief  Sets the TMRx Autoreload Register value
+  * @param  TMRx: where x can be 1 to 15 to select the TMR peripheral.
+  * @param  Autoreload: specifies the Autoreload register new value.
+  * @retval None
+  */
+void TMR_SetAutoreload(TMR_Type* TMRx, uint32_t Autoreload)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  /* Set the Autoreload Register value */
+  TMRx->AR = Autoreload;
+}
+
+/**
+  * @brief  Sets the TMRx Capture Compare1 Register value
+  * @param  TMRx: where x can be 1 to 15 except 6 and 7 to select the TMR peripheral.
+  * @param  Compare1: specifies the Capture Compare1 register new value.
+  * @retval None
+  */
+void TMR_SetCompare1(TMR_Type* TMRx, uint32_t Compare1)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST8_PERIPH(TMRx));
+  /* Set the Capture Compare1 Register value */
+  TMRx->CC1 = Compare1;
+}
+
+/**
+  * @brief  Sets the TMRx Capture Compare2 Register value
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TMR peripheral.
+  * @param  Compare2: specifies the Capture Compare2 register new value.
+  * @retval None
+  */
+void TMR_SetCompare2(TMR_Type* TMRx, uint32_t Compare2)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+  /* Set the Capture Compare2 Register value */
+  TMRx->CC2 = Compare2;
+}
+
+/**
+  * @brief  Sets the TMRx Capture Compare3 Register value
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  Compare3: specifies the Capture Compare3 register new value.
+  * @retval None
+  */
+void TMR_SetCompare3(TMR_Type* TMRx, uint32_t Compare3)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  /* Set the Capture Compare3 Register value */
+  TMRx->CC3 = Compare3;
+}
+
+/**
+  * @brief  Sets the TMRx Capture Compare4 Register value
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  Compare4: specifies the Capture Compare4 register new value.
+  * @retval None
+  */
+void TMR_SetCompare4(TMR_Type* TMRx, uint32_t Compare4)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  /* Set the Capture Compare4 Register value */
+  TMRx->CC4 = Compare4;
+}
+
+/**
+  * @brief  Sets the TMRx Input Capture 1 prescaler.
+  * @param  TMRx: where x can be 1 to 15 except 6 and 7 to select the TMR peripheral.
+  * @param  TMR_ICPSC: specifies the Input Capture1 prescaler new value.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ICDIV_DIV1: no prescaler
+  *     @arg TMR_ICDIV_DIV2: capture is done once every 2 events
+  *     @arg TMR_ICDIV_DIV4: capture is done once every 4 events
+  *     @arg TMR_ICDIV_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TMR_SetIC1DIV(TMR_Type* TMRx, uint16_t TMR_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST8_PERIPH(TMRx));
+  assert_param(IS_TMR_IC_DIV(TMR_ICPSC));
+  /* Reset the IC1PSC Bits */
+  TMRx->CCM1 &= (uint16_t)~((uint16_t)TMR_CCM1_IC1DIV);
+  /* Set the IC1PSC value */
+  TMRx->CCM1 |= TMR_ICPSC;
+}
+
+/**
+  * @brief  Sets the TMRx Input Capture 2 prescaler.
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TMR peripheral.
+  * @param  TMR_ICPSC: specifies the Input Capture2 prescaler new value.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ICDIV_DIV1: no prescaler
+  *     @arg TMR_ICDIV_DIV2: capture is done once every 2 events
+  *     @arg TMR_ICDIV_DIV4: capture is done once every 4 events
+  *     @arg TMR_ICDIV_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TMR_SetIC2DIV(TMR_Type* TMRx, uint16_t TMR_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+  assert_param(IS_TMR_IC_DIV(TMR_ICPSC));
+  /* Reset the IC2PSC Bits */
+  TMRx->CCM1 &= (uint16_t)~((uint16_t)TMR_CCM1_IC2DIV);
+  /* Set the IC2PSC value */
+  TMRx->CCM1 |= (uint16_t)(TMR_ICPSC << 8);
+}
+
+/**
+  * @brief  Sets the TMRx Input Capture 3 prescaler.
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_ICPSC: specifies the Input Capture3 prescaler new value.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ICDIV_DIV1: no prescaler
+  *     @arg TMR_ICDIV_DIV2: capture is done once every 2 events
+  *     @arg TMR_ICDIV_DIV4: capture is done once every 4 events
+  *     @arg TMR_ICDIV_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TMR_SetIC3DIV(TMR_Type* TMRx, uint16_t TMR_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_IC_DIV(TMR_ICPSC));
+  /* Reset the IC3PSC Bits */
+  TMRx->CCM2 &= (uint16_t)~((uint16_t)TMR_CCM2_IC3DIV);
+  /* Set the IC3PSC value */
+  TMRx->CCM2 |= TMR_ICPSC;
+}
+
+/**
+  * @brief  Sets the TMRx Input Capture 4 prescaler.
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_ICPSC: specifies the Input Capture4 prescaler new value.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ICDIV_DIV1: no prescaler
+  *     @arg TMR_ICDIV_DIV2: capture is done once every 2 events
+  *     @arg TMR_ICDIV_DIV4: capture is done once every 4 events
+  *     @arg TMR_ICDIV_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TMR_SetIC4DIV(TMR_Type* TMRx, uint16_t TMR_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  assert_param(IS_TMR_IC_DIV(TMR_ICPSC));
+  /* Reset the IC4PSC Bits */
+  TMRx->CCM2 &= (uint16_t)~((uint16_t)TMR_CCM2_IC4DIV);
+  /* Set the IC4PSC value */
+  TMRx->CCM2 |= (uint16_t)(TMR_ICPSC << 8);
+}
+
+/**
+  * @brief  Sets the TMRx Clock Division value.
+  * @param  TMRx: where x can be  1 to 15 except 6 and 7 to select
+  *   the TMR peripheral.
+  * @param  TMR_CKD: specifies the clock division value.
+  *   This parameter can be one of the following value:
+  *     @arg TMR_CKD_DIV1: TDTS = Tck_tim
+  *     @arg TMR_CKD_DIV2: TDTS = 2*Tck_tim
+  *     @arg TMR_CKD_DIV4: TDTS = 4*Tck_tim
+  * @retval None
+  */
+void TMR_SetClockDivision(TMR_Type* TMRx, uint16_t TMR_CKD)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST8_PERIPH(TMRx));
+  assert_param(IS_TMR_CKD_DIV(TMR_CKD));
+  /* Reset the CKD Bits */
+  TMRx->CTRL1 &= (uint16_t)~((uint16_t)TMR_CTRL1_CLKDIV);
+  /* Set the CKD value */
+  TMRx->CTRL1 |= TMR_CKD;
+}
+
+/**
+  * @brief  Gets the TMRx Input Capture 1 value.
+  * @param  TMRx: where x can be 1 to 15 except 6 and 7 to select the TMR peripheral.
+  * @retval Capture Compare 1 Register value.
+  */
+uint32_t TMR_GetCapture1(TMR_Type* TMRx)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST8_PERIPH(TMRx));
+  /* Get the Capture 1 Register value */
+  return TMRx->CC1;
+}
+
+/**
+  * @brief  Gets the TMRx Input Capture 2 value.
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TMR peripheral.
+  * @retval Capture Compare 2 Register value.
+  */
+uint32_t TMR_GetCapture2(TMR_Type* TMRx)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST6_PERIPH(TMRx));
+  /* Get the Capture 2 Register value */
+  return TMRx->CC2;
+}
+
+/**
+  * @brief  Gets the TMRx Input Capture 3 value.
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @retval Capture Compare 3 Register value.
+  */
+uint32_t TMR_GetCapture3(TMR_Type* TMRx)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  /* Get the Capture 3 Register value */
+  return TMRx->CC3;
+}
+
+/**
+  * @brief  Gets the TMRx Input Capture 4 value.
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @retval Capture Compare 4 Register value.
+  */
+uint32_t TMR_GetCapture4(TMR_Type* TMRx)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_LIST3_PERIPH(TMRx));
+  /* Get the Capture 4 Register value */
+  return TMRx->CC4;
+}
+
+/**
+  * @brief  Gets the TMRx Counter value.
+  * @param  TMRx: where x can be 1 to 15 to select the TMR peripheral.
+  * @retval Counter Register value.
+  */
+uint32_t TMR_GetCounter(TMR_Type* TMRx)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  /* Get the Counter Register value */
+  return TMRx->CNT;
+}
+
+/**
+  * @brief  Gets the TMRx Prescaler value.
+  * @param  TMRx: where x can be 1 to 15 to select the TMR peripheral.
+  * @retval Prescaler Register value.
+  */
+uint16_t TMR_GetDIV(TMR_Type* TMRx)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  /* Get the Prescaler Register value */
+  return TMRx->DIV;
+}
+
+/**
+  * @brief  Checks whether the specified TMR flag is set or not.
+  * @param  TMRx: where x can be 1 to 15 to select the TMR peripheral.
+  * @param  TMR_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_FLAG_Update: TMR update Flag
+  *     @arg TMR_FLAG_CC1: TMR Capture Compare 1 Flag
+  *     @arg TMR_FLAG_CC2: TMR Capture Compare 2 Flag
+  *     @arg TMR_FLAG_CC3: TMR Capture Compare 3 Flag
+  *     @arg TMR_FLAG_CC4: TMR Capture Compare 4 Flag
+  *     @arg TMR_FLAG_HALL: TMR Commutation Flag
+  *     @arg TMR_FLAG_Trigger: TMR Trigger Flag
+  *     @arg TMR_FLAG_Break: TMR Break Flag
+  *     @arg TMR_FLAG_C1OF: TMR Capture Compare 1 overcapture Flag
+  *     @arg TMR_FLAG_C2OF: TMR Capture Compare 2 overcapture Flag
+  *     @arg TMR_FLAG_C3OF: TMR Capture Compare 3 overcapture Flag
+  *     @arg TMR_FLAG_C4OF: TMR Capture Compare 4 overcapture Flag
+  * @note
+  *   - TMR6 and TMR7 can have only one update flag.
+  *   - TMR9, TMR12 and TMR15 can have only TMR_FLAG_Update, TMR_FLAG_CC1,
+  *      TMR_FLAG_CC2 or TMR_FLAG_Trigger.
+  *   - TMR10, TMR11, TMR13, TMR14 can have TMR_FLAG_Update or TMR_FLAG_CC1.
+  *   - TMR_FLAG_Break is used only with TMR1, TMR8 and TMR15.
+  *   - TMR_FLAG_HALL is used only with TMR1, TMR8, TMR15.
+  * @retval The new state of TMR_FLAG (SET or RESET).
+  */
+FlagStatus TMR_GetFlagStatus(TMR_Type* TMRx, uint16_t TMR_FLAG)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  assert_param(IS_TMR_GET_FLAG(TMR_FLAG));
+
+  if ((TMRx->STS & TMR_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the TMRx's pending flags.
+  * @param  TMRx: where x can be 1 to 15 to select the TMR peripheral.
+  * @param  TMR_FLAG: specifies the flag bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg TMR_FLAG_Update: TMR update Flag
+  *     @arg TMR_FLAG_CC1: TMR Capture Compare 1 Flag
+  *     @arg TMR_FLAG_CC2: TMR Capture Compare 2 Flag
+  *     @arg TMR_FLAG_CC3: TMR Capture Compare 3 Flag
+  *     @arg TMR_FLAG_CC4: TMR Capture Compare 4 Flag
+  *     @arg TMR_FLAG_HALL: TMR Commutation Flag
+  *     @arg TMR_FLAG_Trigger: TMR Trigger Flag
+  *     @arg TMR_FLAG_Break: TMR Break Flag
+  *     @arg TMR_FLAG_C1OF: TMR Capture Compare 1 overcapture Flag
+  *     @arg TMR_FLAG_C2OF: TMR Capture Compare 2 overcapture Flag
+  *     @arg TMR_FLAG_C3OF: TMR Capture Compare 3 overcapture Flag
+  *     @arg TMR_FLAG_C4OF: TMR Capture Compare 4 overcapture Flag
+  * @note
+  *   - TMR6 and TMR7 can have only one update flag.
+  *   - TMR9, TMR12 and TMR15 can have only TMR_FLAG_Update, TMR_FLAG_CC1,
+  *      TMR_FLAG_CC2 or TMR_FLAG_Trigger.
+  *   - TMR10, TMR11, TMR13, TMR14 can have TMR_FLAG_Update or TMR_FLAG_CC1.
+  *   - TMR_FLAG_Break is used only with TMR1, TMR8 and TMR15.
+  *   - TMR_FLAG_HALL is used only with TMR1, TMR8, TMR15.
+  * @retval None
+  */
+void TMR_ClearFlag(TMR_Type* TMRx, uint16_t TMR_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  assert_param(IS_TMR_CLEAR_FLAG(TMR_FLAG));
+
+  /* Clear the flags */
+  TMRx->STS = (uint16_t)~TMR_FLAG;
+}
+
+/**
+  * @brief  Checks whether the TMR interrupt has occurred or not.
+  * @param  TMRx: where x can be 1 to 15 to select the TMR peripheral.
+  * @param  TMR_INT: specifies the TMR interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_INT_Overflow: TMR update Interrupt source
+  *     @arg TMR_INT_CC1: TMR Capture Compare 1 Interrupt source
+  *     @arg TMR_INT_CC2: TMR Capture Compare 2 Interrupt source
+  *     @arg TMR_INT_CC3: TMR Capture Compare 3 Interrupt source
+  *     @arg TMR_INT_CC4: TMR Capture Compare 4 Interrupt source
+  *     @arg TMR_INT_HALL: TMR Commutation Interrupt source
+  *     @arg TMR_INT_Trigger: TMR Trigger Interrupt source
+  *     @arg TMR_INT_Break: TMR Break Interrupt source
+  * @note
+  *   - TMR6 and TMR7 can generate only an update interrupt.
+  *   - TMR9, TMR12 and TMR15 can have only TMR_INT_Overflow, TMR_INT_CC1,
+  *      TMR_INT_CC2 or TMR_INT_Trigger.
+  *   - TMR10, TMR11, TMR13, TMR14 can have TMR_INT_Overflow or TMR_INT_CC1.
+  *   - TMR_INT_Break is used only with TMR1, TMR8 and TMR15.
+  *   - TMR_INT_HALL is used only with TMR1, TMR8, TMR15.
+  * @retval The new state of the TMR_INT(SET or RESET).
+  */
+ITStatus TMR_GetINTStatus(TMR_Type* TMRx, uint16_t TMR_INT)
+{
+  ITStatus bitstatus = RESET;
+  uint16_t itstatus = 0x0, itenable = 0x0;
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  assert_param(IS_TMR_GET_INT(TMR_INT));
+
+  itstatus = TMRx->STS & TMR_INT;
+
+  itenable = TMRx->DIE & TMR_INT;
+
+  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the TMRx's interrupt pending bits.
+  * @param  TMRx: where x can be 1 to 15 to select the TMR peripheral.
+  * @param  TMR_INT: specifies the pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg TMR_INT_Overflow: TMR1 update Interrupt source
+  *     @arg TMR_INT_CC1: TMR Capture Compare 1 Interrupt source
+  *     @arg TMR_INT_CC2: TMR Capture Compare 2 Interrupt source
+  *     @arg TMR_INT_CC3: TMR Capture Compare 3 Interrupt source
+  *     @arg TMR_INT_CC4: TMR Capture Compare 4 Interrupt source
+  *     @arg TMR_INT_HALL: TMR Commutation Interrupt source
+  *     @arg TMR_INT_Trigger: TMR Trigger Interrupt source
+  *     @arg TMR_INT_Break: TMR Break Interrupt source
+  * @note
+  *   - TMR6 and TMR7 can generate only an update interrupt.
+  *   - TMR9, TMR12 and TMR15 can have only TMR_INT_Overflow, TMR_INT_CC1,
+  *      TMR_INT_CC2 or TMR_INT_Trigger.
+  *   - TMR10, TMR11, TMR13, TMR14 can have TMR_INT_Overflow or TMR_INT_CC1.
+  *   - TMR_INT_Break is used only with TMR1, TMR8 and TMR15.
+  *   - TMR_INT_HALL is used only with TMR1, TMR8, TMR15.
+  * @retval None
+  */
+void TMR_ClearITPendingBit(TMR_Type* TMRx, uint16_t TMR_INT)
+{
+  /* Check the parameters */
+  assert_param(IS_TMR_ALL_PERIPH(TMRx));
+  assert_param(IS_TMR_INT(TMR_INT));
+  /* Clear the INT pending Bit */
+  TMRx->STS = (uint16_t)~TMR_INT;
+}
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TMRx: where x can be 1 to 15 except 6 and 7 to select the TMR peripheral.
+  * @param  TMR_ICPolarity : The Input Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ICPolarity_Rising
+  *     @arg TMR_ICPolarity_Falling
+  * @param  TMR_ICSelection: specifies the input to be used.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ICSelection_DirectTI: TMR Input 1 is selected to be connected to IC1.
+  *     @arg TMR_ICSelection_IndirectTI: TMR Input 1 is selected to be connected to IC2.
+  *     @arg TMR_ICSelection_TRC: TMR Input 1 is selected to be connected to TRC.
+  * @param  TMR_ICFilter: Specifies the Input Capture Filter.
+  *   This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI1_Config(TMR_Type* TMRx, uint16_t TMR_ICPolarity, uint16_t TMR_ICSelection,
+                       uint16_t TMR_ICFilter)
+{
+  uint16_t tmpccmr1 = 0, tmpccer = 0;
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TMRx->CCE &= (uint16_t)~((uint16_t)TMR_CCE_C1EN);
+  tmpccmr1 = TMRx->CCM1;
+  tmpccer = TMRx->CCE;
+  /* Select the Input and set the filter */
+  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TMR_CCM1_C1SEL)) & ((uint16_t)~((uint16_t)TMR_CCM1_IC1F)));
+  tmpccmr1 |= (uint16_t)(TMR_ICSelection | (uint16_t)(TMR_ICFilter << (uint16_t)4));
+
+
+  if((TMRx == TMR1) || (TMRx == TMR2) ||
+#if !defined (AT32F415xx)
+     (TMRx == TMR8) ||
+#endif
+#if defined (AT32F403xx)
+     (TMRx == TMR15) ||
+#endif
+      (TMRx == TMR3) || (TMRx == TMR4) || (TMRx == TMR5))
+  {
+    /* Select the Polarity and set the CC1E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TMR_CCE_C1P));
+    tmpccer |= (uint16_t)(TMR_ICPolarity | (uint16_t)TMR_CCE_C1EN);
+  }
+  else
+  {
+    /* Select the Polarity and set the CC1E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TMR_CCE_C1P | TMR_CCE_C1NP));
+    tmpccer |= (uint16_t)(TMR_ICPolarity | (uint16_t)TMR_CCE_C1EN);
+  }
+
+  /* Write to TMRx CCMR1 and CCE registers */
+  TMRx->CCM1 = tmpccmr1;
+  TMRx->CCE = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TMR peripheral.
+  * @param  TMR_ICPolarity : The Input Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ICPolarity_Rising
+  *     @arg TMR_ICPolarity_Falling
+  * @param  TMR_ICSelection: specifies the input to be used.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ICSelection_DirectTI: TMR Input 2 is selected to be connected to IC2.
+  *     @arg TMR_ICSelection_IndirectTI: TMR Input 2 is selected to be connected to IC1.
+  *     @arg TMR_ICSelection_TRC: TMR Input 2 is selected to be connected to TRC.
+  * @param  TMR_ICFilter: Specifies the Input Capture Filter.
+  *   This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI2_Config(TMR_Type* TMRx, uint16_t TMR_ICPolarity, uint16_t TMR_ICSelection,
+                       uint16_t TMR_ICFilter)
+{
+  uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TMRx->CCE &= (uint16_t)~((uint16_t)TMR_CCE_C2EN);
+  tmpccmr1 = TMRx->CCM1;
+  tmpccer = TMRx->CCE;
+  tmp = (uint16_t)(TMR_ICPolarity << 4);
+  /* Select the Input and set the filter */
+  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TMR_CCM1_C2SEL)) & ((uint16_t)~((uint16_t)TMR_CCM1_IC2DF)));
+  tmpccmr1 |= (uint16_t)(TMR_ICFilter << 12);
+  tmpccmr1 |= (uint16_t)(TMR_ICSelection << 8);
+
+  if((TMRx == TMR1) || (TMRx == TMR2) ||
+#if !defined (AT32F415xx)
+     (TMRx == TMR8) ||
+#endif
+#if defined (AT32F403xx)
+     (TMRx == TMR15) ||
+#endif
+      (TMRx == TMR3) || (TMRx == TMR4) || (TMRx == TMR5))
+  {
+    /* Select the Polarity and set the CC2E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TMR_CCE_C2P));
+    tmpccer |=  (uint16_t)(tmp | (uint16_t)TMR_CCE_C2EN);
+  }
+  else
+  {
+    /* Select the Polarity and set the CC2E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TMR_CCE_C2P | TMR_CCE_C2NP));
+    tmpccer |= (uint16_t)(tmp  | (uint16_t)TMR_CCE_C2EN);
+  }
+
+  /* Write to TMRx CCMR1 and CCE registers */
+  TMRx->CCM1 = tmpccmr1 ;
+  TMRx->CCE = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_ICPolarity : The Input Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ICPolarity_Rising
+  *     @arg TMR_ICPolarity_Falling
+  * @param  TMR_ICSelection: specifies the input to be used.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ICSelection_DirectTI: TMR Input 3 is selected to be connected to IC3.
+  *     @arg TMR_ICSelection_IndirectTI: TMR Input 3 is selected to be connected to IC4.
+  *     @arg TMR_ICSelection_TRC: TMR Input 3 is selected to be connected to TRC.
+  * @param  TMR_ICFilter: Specifies the Input Capture Filter.
+  *   This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI3_Config(TMR_Type* TMRx, uint16_t TMR_ICPolarity, uint16_t TMR_ICSelection,
+                       uint16_t TMR_ICFilter)
+{
+  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TMRx->CCE &= (uint16_t)~((uint16_t)TMR_CCE_C3EN);
+  tmpccmr2 = TMRx->CCM2;
+  tmpccer = TMRx->CCE;
+  tmp = (uint16_t)(TMR_ICPolarity << 8);
+  /* Select the Input and set the filter */
+  tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TMR_CCM2_C3SEL)) & ((uint16_t)~((uint16_t)TMR_CCM2_IC3DF)));
+  tmpccmr2 |= (uint16_t)(TMR_ICSelection | (uint16_t)(TMR_ICFilter << (uint16_t)4));
+
+  if((TMRx == TMR1) || (TMRx == TMR2) ||
+#if !defined (AT32F415xx)
+     (TMRx == TMR8) ||
+#endif
+#if defined (AT32F403xx)
+     (TMRx == TMR15) ||
+#endif
+      (TMRx == TMR3) || (TMRx == TMR4) || (TMRx == TMR5))
+  {
+    /* Select the Polarity and set the CC3E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TMR_CCE_C3P));
+    tmpccer |= (uint16_t)(tmp | (uint16_t)TMR_CCE_C3EN);
+  }
+  else
+  {
+    /* Select the Polarity and set the CC3E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TMR_CCE_C3P | TMR_CCE_C3NP));
+    tmpccer |= (uint16_t)(tmp | (uint16_t)TMR_CCE_C3EN);
+  }
+
+  /* Write to TMRx CCMR2 and CCE registers */
+  TMRx->CCM2 = tmpccmr2;
+  TMRx->CCE = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TMRx: where x can be 1, 2, 3, 4, 5 or 8 to select the TMR peripheral.
+  * @param  TMR_ICPolarity : The Input Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ICPolarity_Rising
+  *     @arg TMR_ICPolarity_Falling
+  * @param  TMR_ICSelection: specifies the input to be used.
+  *   This parameter can be one of the following values:
+  *     @arg TMR_ICSelection_DirectTI: TMR Input 4 is selected to be connected to IC4.
+  *     @arg TMR_ICSelection_IndirectTI: TMR Input 4 is selected to be connected to IC3.
+  *     @arg TMR_ICSelection_TRC: TMR Input 4 is selected to be connected to TRC.
+  * @param  TMR_ICFilter: Specifies the Input Capture Filter.
+  *   This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI4_Config(TMR_Type* TMRx, uint16_t TMR_ICPolarity, uint16_t TMR_ICSelection,
+                       uint16_t TMR_ICFilter)
+{
+  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TMRx->CCE &= (uint16_t)~((uint16_t)TMR_CCE_C4EN);
+  tmpccmr2 = TMRx->CCM2;
+  tmpccer = TMRx->CCE;
+  tmp = (uint16_t)(TMR_ICPolarity << 12);
+  /* Select the Input and set the filter */
+  tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TMR_CCM2_CC4S) & ((uint16_t)~((uint16_t)TMR_CCM2_IC4DF)));
+  tmpccmr2 |= (uint16_t)(TMR_ICSelection << 8);
+  tmpccmr2 |= (uint16_t)(TMR_ICFilter << 12);
+
+  if((TMRx == TMR1) || (TMRx == TMR2) ||
+#if !defined (AT32F415xx)
+     (TMRx == TMR8) ||
+#endif
+#if defined (AT32F403xx)
+     (TMRx == TMR15) ||
+#endif
+      (TMRx == TMR3) || (TMRx == TMR4) || (TMRx == TMR5))
+  {
+    /* Select the Polarity and set the CC4E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TMR_CCE_C4P));
+    tmpccer |= (uint16_t)(tmp | (uint16_t)TMR_CCE_C4EN);
+  }
+  else
+  {
+    /* Select the Polarity and set the CC4E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TMR_CCE_C3P | TMR_CCE_C4NP));
+    tmpccer |= (uint16_t)(tmp | (uint16_t)TMR_CCE_C4EN);
+  }
+
+  /* Write to TMRx CCMR2 and CCE registers */
+  TMRx->CCM2 = tmpccmr2;
+  TMRx->CCE = tmpccer;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_usart.c

@@ -0,0 +1,1056 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_usart.c
+ * Description  : at32f4xx USART source file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_usart.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup USART
+  * @brief USART driver modules
+  * @{
+  */
+
+/** @defgroup USART_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_Defines
+  * @{
+  */
+
+#define CTRL1_UEN_Set               ((uint16_t)0x2000)  /*!< USART Enable Mask */
+#define CTRL1_UEN_Reset             ((uint16_t)0xDFFF)  /*!< USART Disable Mask */
+
+#define CTRL1_WUMODE_Mask           ((uint16_t)0xF7FF)  /*!< USART WakeUp Method Mask */
+
+#define CTRL1_RECMUTE_Set           ((uint16_t)0x0002)  /*!< USART mute mode Enable Mask */
+#define CTRL1_RECMUTE_Reset         ((uint16_t)0xFFFD)  /*!< USART mute mode Enable Mask */
+#define CTRL1_SBRK_Set              ((uint16_t)0x0001)  /*!< USART Break Character send Mask */
+#define CTRL1_CLEAR_MASK            ((uint16_t)0xE9F3)  /*!< USART CTRL1 Mask */
+#define CTRL2_ADDRESS_Mask          ((uint16_t)0xFFF0)  /*!< USART address Mask */
+
+#define CTRL2_LINEN_Set             ((uint16_t)0x4000)  /*!< USART LIN Enable Mask */
+#define CTRL2_LINEN_Reset           ((uint16_t)0xBFFF)  /*!< USART LIN Disable Mask */
+
+#define CTRL2_LBDLEN_Mask           ((uint16_t)0xFFDF)  /*!< USART LIN Break detection Mask */
+#define CTRL2_STOPB_CLEAR_Mask      ((uint16_t)0xCFFF)  /*!< USART CTRL2 STOP Bits Mask */
+#define CTRL2_CLOCK_CLEAR_Mask      ((uint16_t)0xF0FF)  /*!< USART CTRL2 Clock Mask */
+
+#define CTRL3_SCMEN_Set             ((uint16_t)0x0020)  /*!< USART SC Enable Mask */
+#define CTRL3_SCMEN_Reset           ((uint16_t)0xFFDF)  /*!< USART SC Disable Mask */
+
+#define CTRL3_NACKEN_Set            ((uint16_t)0x0010)  /*!< USART SC NACK Enable Mask */
+#define CTRL3_NACKEN_Reset          ((uint16_t)0xFFEF)  /*!< USART SC NACK Disable Mask */
+
+#define CTRL3_HALFSEL_Set           ((uint16_t)0x0008)  /*!< USART Half-Duplex Enable Mask */
+#define CTRL3_HALFSEL_Reset         ((uint16_t)0xFFF7)  /*!< USART Half-Duplex Disable Mask */
+
+#define CTRL3_IRDALP_Mask           ((uint16_t)0xFFFB)  /*!< USART IrDA LowPower mode Mask */
+#define CTRL3_CLEAR_Mask            ((uint16_t)0xFCFF)  /*!< USART CR3 Mask */
+
+#define CTRL3_IRDAEN_Set            ((uint16_t)0x0002)  /*!< USART IrDA Enable Mask */
+#define CTRL3_IRDAEN_Reset          ((uint16_t)0xFFFD)  /*!< USART IrDA Disable Mask */
+#define GTPR_LSB_Mask               ((uint16_t)0x00FF)  /*!< Guard Time Register LSB Mask */
+#define GTPR_MSB_Mask               ((uint16_t)0xFF00)  /*!< Guard Time Register MSB Mask */
+#define INT_Mask                    ((uint16_t)0x001F)  /*!< USART Interrupt Mask */
+
+/* USART OverSampling-8 Mask */
+#define CTRL1_OVER8_Set             ((u16)0x8000)  /* USART OVER8 mode Enable Mask */
+#define CTRL1_OVER8_Reset           ((u16)0x7FFF)  /* USART OVER8 mode Disable Mask */
+
+/* USART One Bit Sampling Mask */
+#define CTRL3_ONEBITE_Set           ((u16)0x0800)  /* USART ONEBITE mode Enable Mask */
+#define CTRL3_ONEBITE_Reset         ((u16)0xF7FF)  /* USART ONEBITE mode Disable Mask */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the USARTx peripheral registers to their default reset values.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *      USART1, USART2, USART3, UART4 or UART5.
+  * @retval None
+  */
+void USART_Reset(USART_Type* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+  if (USARTx == USART1)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_USART1, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2PERIPH_USART1, DISABLE);
+  }
+  else if (USARTx == USART2)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_USART2, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_USART2, DISABLE);
+  }
+  else if (USARTx == USART3)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_USART3, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_USART3, DISABLE);
+  }
+  else if (USARTx == UART4)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_UART4, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_UART4, DISABLE);
+  }
+  else if (USARTx == UART5)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_UART5, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_UART5, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the USARTx peripheral according to the specified
+  *         parameters in the USART_InitStruct .
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_InitStruct: pointer to a USART_InitType structure
+  *         that contains the configuration information for the specified USART
+  *         peripheral.
+  * @retval None
+  */
+void USART_Init(USART_Type* USARTx, USART_InitType* USART_InitStruct)
+{
+  uint32_t tmpreg = 0x00, apbclock = 0x00;
+  uint32_t integerdivider = 0x00;
+  uint32_t fractionaldivider = 0x00;
+  uint32_t usartxbase = 0;
+  RCC_ClockType RCC_ClocksStatus;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
+  assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
+  assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
+  assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
+  assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
+  assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
+
+  /* The hardware flow control is available only for USART1, USART2 and USART3 */
+  if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }
+
+  usartxbase = (uint32_t)USARTx;
+
+  /*---------------------------- USART CTRL2 Configuration -----------------------*/
+  tmpreg = USARTx->CTRL2;
+  /* Clear STOP[13:12] bits */
+  tmpreg &= CTRL2_STOPB_CLEAR_Mask;
+  /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+  /* Set STOP[13:12] bits according to USART_StopBits value */
+  tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
+
+  /* Write to USART CTRL2 */
+  USARTx->CTRL2 = (uint16_t)tmpreg;
+
+  /*---------------------------- USART CTRL1 Configuration -----------------------*/
+  tmpreg = USARTx->CTRL1;
+  /* Clear M, PCE, PS, TE and RE bits */
+  tmpreg &= CTRL1_CLEAR_MASK;
+  /* Configure the USART Word Length, Parity and mode ----------------------- */
+  /* Set the M bits according to USART_WordLength value */
+  /* Set PCE and PS bits according to USART_Parity value */
+  /* Set TE and RE bits according to USART_Mode value */
+  tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+            USART_InitStruct->USART_Mode;
+  /* Write to USART CTRL1 */
+  USARTx->CTRL1 = (uint16_t)tmpreg;
+
+  /*---------------------------- USART CR3 Configuration -----------------------*/
+  tmpreg = USARTx->CTRL3;
+  /* Clear CTSE and RTSE bits */
+  tmpreg &= CTRL3_CLEAR_Mask;
+  /* Configure the USART HFC -------------------------------------------------*/
+  /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
+  tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+  /* Write to USART CR3 */
+  USARTx->CTRL3 = (uint16_t)tmpreg;
+
+  /*---------------------------- USART BRR Configuration -----------------------*/
+  /* Configure the USART Baud Rate -------------------------------------------*/
+  RCC_GetClocksFreq(&RCC_ClocksStatus);
+
+  if (usartxbase == USART1_BASE)
+  {
+    apbclock = RCC_ClocksStatus.APB2CLK_Freq;
+  }
+  else
+  {
+    apbclock = RCC_ClocksStatus.APB1CLK_Freq;
+  }
+
+  /* Determine the integer part */
+  if ((USARTx->CTRL1 & CTRL1_OVER8_Set) != 0)
+  {
+    /* Integer part computing in case Oversampling mode is 8 Samples */
+    integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
+  }
+  else /* if ((USARTx->CTRL1 & CTRL1_OVER8_Set) == 0) */
+  {
+    /* Integer part computing in case Oversampling mode is 16 Samples */
+    integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
+  }
+
+  tmpreg = (integerdivider / 100) << 4;
+
+  /* Determine the fractional part */
+  fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
+
+  /* Implement the fractional part in the register */
+  if ((USARTx->CTRL1 & CTRL1_OVER8_Set) != 0)
+  {
+    tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
+  }
+  else /* if ((USARTx->CTRL1 & CTRL1_OVER8_Set) == 0) */
+  {
+    tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
+  }
+
+  /* Write to USART BRR */
+  USARTx->BAUDR = (uint16_t)tmpreg;
+}
+
+/**
+  * @brief  Fills each USART_InitStruct member with its default value.
+  * @param  USART_InitStruct: pointer to a USART_InitType structure
+  *         which will be initialized.
+  * @retval None
+  */
+void USART_StructInit(USART_InitType* USART_InitStruct)
+{
+  /* USART_InitStruct members default value */
+  USART_InitStruct->USART_BaudRate = 9600;
+  USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+  USART_InitStruct->USART_StopBits = USART_StopBits_1;
+  USART_InitStruct->USART_Parity = USART_Parity_No ;
+  USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+  USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+}
+
+/**
+  * @brief  Initializes the USARTx peripheral Clock according to the
+  *          specified parameters in the USART_ClockInitStruct .
+  * @param  USARTx: where x can be 1, 2, 3 to select the USART peripheral.
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitType
+  *         structure that contains the configuration information for the specified
+  *         USART peripheral.
+  * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
+  * @retval None
+  */
+void USART_ClockInit(USART_Type* USARTx, USART_ClockInitType* USART_ClockInitStruct)
+{
+  uint32_t tmpreg = 0x00;
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
+  assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
+  assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
+  assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
+
+  /*---------------------------- USART CTRL2 Configuration -----------------------*/
+  tmpreg = USARTx->CTRL2;
+  /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+  tmpreg &= CTRL2_CLOCK_CLEAR_Mask;
+  /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
+  /* Set CLKEN bit according to USART_Clock value */
+  /* Set CPOL bit according to USART_CPOL value */
+  /* Set CPHA bit according to USART_CPHA value */
+  /* Set LBCL bit according to USART_LastBit value */
+  tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
+            USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
+  /* Write to USART CTRL2 */
+  USARTx->CTRL2 = (uint16_t)tmpreg;
+}
+
+/**
+  * @brief  Fills each USART_ClockInitStruct member with its default value.
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitType
+  *         structure which will be initialized.
+  * @retval None
+  */
+void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct)
+{
+  /* USART_ClockInitStruct members default value */
+  USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+  USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+  USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+  USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/**
+  * @brief  Enables or disables the specified USART peripheral.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *         This parameter can be one of the following values:
+  *           USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USARTx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_Cmd(USART_Type* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected USART by setting the UE bit in the CTRL1 register */
+    USARTx->CTRL1 |= CTRL1_UEN_Set;
+  }
+  else
+  {
+    /* Disable the selected USART by clearing the UE bit in the CTRL1 register */
+    USARTx->CTRL1 &= CTRL1_UEN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified USART interrupts.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_INT: specifies the USART interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg USART_INT_CTSF:  CTS change interrupt (not available for UART4 and UART5)
+  *     @arg USART_INT_LBDF:  LIN Break detection interrupt
+  *     @arg USART_INT_TDE:  Transmit Data Register empty interrupt
+  *     @arg USART_INT_TRAC:   Transmission complete interrupt
+  *     @arg USART_INT_RDNE: Receive Data register not empty interrupt
+  *     @arg USART_INT_IDLEF: Idle line detection interrupt
+  *     @arg USART_INT_PERR:   Parity Error interrupt
+  *     @arg USART_INT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @param  NewState: new state of the specified USARTx interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_INTConfig(USART_Type* USARTx, uint16_t USART_INT, FunctionalState NewState)
+{
+  uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+  uint32_t usartxbase = 0x00;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CONFIG_INT(USART_INT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* The CTS interrupt is not available for UART4 and UART5 */
+  if (USART_INT == USART_INT_CTSF)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }
+
+  usartxbase = (uint32_t)USARTx;
+
+  /* Get the USART register index */
+  usartreg = (((uint8_t)USART_INT) >> 0x05);
+
+  /* Get the interrupt position */
+  itpos = USART_INT & INT_Mask;
+  itmask = (((uint32_t)0x01) << itpos);
+
+  if (usartreg == 0x01) /* The INT is in CTRL1 register */
+  {
+    usartxbase += 0x0C;
+  }
+  else if (usartreg == 0x02) /* The INT is in CTRL2 register */
+  {
+    usartxbase += 0x10;
+  }
+  else /* The INT is in CR3 register */
+  {
+    usartxbase += 0x14;
+  }
+
+  if (NewState != DISABLE)
+  {
+    *(__IO uint32_t*)usartxbase  |= itmask;
+  }
+  else
+  {
+    *(__IO uint32_t*)usartxbase &= ~itmask;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's DMA interface.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_DMAReq: specifies the DMA request.
+  *   This parameter can be any combination of the following values:
+  *     @arg USART_DMAReq_Tx: USART DMA transmit request
+  *     @arg USART_DMAReq_Rx: USART DMA receive request
+  * @param  NewState: new state of the DMA Request sources.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_DMACmd(USART_Type* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DMAREQ(USART_DMAReq));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+       DMAR bits in the USART CR3 register */
+    USARTx->CTRL3 |= USART_DMAReq;
+  }
+  else
+  {
+    /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+       DMAR bits in the USART CR3 register */
+    USARTx->CTRL3 &= (uint16_t)~USART_DMAReq;
+  }
+}
+
+/**
+  * @brief  Sets the address of the USART node.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_Address: Indicates the address of the USART node.
+  * @retval None
+  */
+void USART_SetAddress(USART_Type* USARTx, uint8_t USART_Address)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_ADDRESS(USART_Address));
+
+  /* Clear the USART address */
+  USARTx->CTRL2 &= CTRL2_ADDRESS_Mask;
+  /* Set the USART address node */
+  USARTx->CTRL2 |= USART_Address;
+}
+
+/**
+  * @brief  Selects the USART WakeUp method.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_WakeUp: specifies the USART wakeup method.
+  *   This parameter can be one of the following values:
+  *     @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
+  *     @arg USART_WakeUp_AddressMark: WakeUp by an address mark
+  * @retval None
+  */
+void USART_WakeUpConfig(USART_Type* USARTx, uint16_t USART_WakeUp)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_WAKEUP(USART_WakeUp));
+
+  USARTx->CTRL1 &= CTRL1_WUMODE_Mask;
+  USARTx->CTRL1 |= USART_WakeUp;
+}
+
+/**
+  * @brief  Determines if the USART is in mute mode or not.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART mute mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_ReceiverWakeUpCmd(USART_Type* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the USART mute mode  by setting the RWU bit in the CTRL1 register */
+    USARTx->CTRL1 |= CTRL1_RECMUTE_Set;
+  }
+  else
+  {
+    /* Disable the USART mute mode by clearing the RWU bit in the CTRL1 register */
+    USARTx->CTRL1 &= CTRL1_RECMUTE_Reset;
+  }
+}
+
+/**
+  * @brief  Sets the USART LIN Break detection length.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_LINBreakDetectLength: specifies the LIN break detection length.
+  *   This parameter can be one of the following values:
+  *     @arg USART_LINBreakDetectLength_10b: 10-bit break detection
+  *     @arg USART_LINBreakDetectLength_11b: 11-bit break detection
+  * @retval None
+  */
+void USART_LINBreakDetectLengthConfig(USART_Type* USARTx, uint16_t USART_LINBreakDetectLength)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+
+  USARTx->CTRL2 &= CTRL2_LBDLEN_Mask;
+  USARTx->CTRL2 |= USART_LINBreakDetectLength;
+}
+
+/**
+  * @brief  Enables or disables the USART’s LIN mode.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART LIN mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_LINCmd(USART_Type* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the LIN mode by setting the LINEN bit in the CTRL2 register */
+    USARTx->CTRL2 |= CTRL2_LINEN_Set;
+  }
+  else
+  {
+    /* Disable the LIN mode by clearing the LINEN bit in the CTRL2 register */
+    USARTx->CTRL2 &= CTRL2_LINEN_Reset;
+  }
+}
+
+/**
+  * @brief  Transmits single data through the USARTx peripheral.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  Data: the data to transmit.
+  * @retval None
+  */
+void USART_SendData(USART_Type* USARTx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DATA(Data));
+
+  /* Transmit Data */
+  USARTx->DT = (Data & (uint16_t)0x01FF);
+}
+
+/**
+  * @brief  Returns the most recent received data by the USARTx peripheral.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @retval The received data.
+  */
+uint16_t USART_ReceiveData(USART_Type* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+  /* Receive Data */
+  return (uint16_t)(USARTx->DT & (uint16_t)0x01FF);
+}
+
+/**
+  * @brief  Transmits break characters.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @retval None
+  */
+void USART_SendBreak(USART_Type* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+  /* Send break characters */
+  USARTx->CTRL1 |= CTRL1_SBRK_Set;
+}
+
+/**
+  * @brief  Sets the specified USART guard time.
+  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+  * @param  USART_GuardTime: specifies the guard time.
+  * @note The guard time bits are not available for UART4 and UART5.
+  * @retval None
+  */
+void USART_SetGuardTime(USART_Type* USARTx, uint8_t USART_GuardTime)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+
+  /* Clear the USART Guard time */
+  USARTx->GTP &= GTPR_LSB_Mask;
+  /* Set the USART guard time */
+  USARTx->GTP |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+  * @brief  Sets the system clock prescaler.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_Prescaler: specifies the prescaler clock.
+  * @note   The function is used for IrDA mode with UART4 and UART5.
+  * @retval None
+  */
+void USART_SetPrescaler(USART_Type* USARTx, uint8_t USART_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+  /* Clear the USART prescaler */
+  USARTx->GTP &= GTPR_MSB_Mask;
+  /* Set the USART prescaler */
+  USARTx->GTP |= USART_Prescaler;
+}
+
+/**
+  * @brief  Enables or disables the USART’s Smart Card mode.
+  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the Smart Card mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @note The Smart Card mode is not available for UART4 and UART5.
+  * @retval None
+  */
+void USART_SmartCardCmd(USART_Type* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+    USARTx->CTRL3 |= CTRL3_SCMEN_Set;
+  }
+  else
+  {
+    /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
+    USARTx->CTRL3 &= CTRL3_SCMEN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables NACK transmission.
+  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the NACK transmission.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @note The Smart Card mode is not available for UART4 and UART5.
+  * @retval None
+  */
+void USART_SmartCardNACKCmd(USART_Type* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
+    USARTx->CTRL3 |= CTRL3_NACKEN_Set;
+  }
+  else
+  {
+    /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
+    USARTx->CTRL3 &= CTRL3_NACKEN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART’s Half Duplex communication.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART Communication.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_HalfDuplexCmd(USART_Type* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+    USARTx->CTRL3 |= CTRL3_HALFSEL_Set;
+  }
+  else
+  {
+    /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
+    USARTx->CTRL3 &= CTRL3_HALFSEL_Reset;
+  }
+}
+
+
+/**
+  * @brief  Enables or disables the USART's 8x oversampling mode.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART one bit sampling method.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @note
+  *     This function has to be called before calling USART_Init()
+  *     function in order to have correct baudrate Divider value.
+  * @retval None
+  */
+void USART_OverSampling8Cmd(USART_Type* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CTRL1 register */
+    USARTx->CTRL1 |= CTRL1_OVER8_Set;
+  }
+  else
+  {
+    /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CTRL1 register */
+    USARTx->CTRL1 &= CTRL1_OVER8_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's one bit sampling method.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART one bit sampling method.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_OneBitMethodCmd(USART_Type* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
+    USARTx->CTRL3 |= CTRL3_ONEBITE_Set;
+  }
+  else
+  {
+    /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */
+    USARTx->CTRL3 &= CTRL3_ONEBITE_Reset;
+  }
+}
+
+/**
+  * @brief  Configures the USART's IrDA interface.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_IrDAMode: specifies the IrDA mode.
+  *   This parameter can be one of the following values:
+  *     @arg USART_IrDAMode_LowPower
+  *     @arg USART_IrDAMode_Normal
+  * @retval None
+  */
+void USART_IrDAConfig(USART_Type* USARTx, uint16_t USART_IrDAMode)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+
+  USARTx->CTRL3 &= CTRL3_IRDALP_Mask;
+  USARTx->CTRL3 |= USART_IrDAMode;
+}
+
+/**
+  * @brief  Enables or disables the USART's IrDA interface.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the IrDA mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_IrDACmd(USART_Type* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+    USARTx->CTRL3 |= CTRL3_IRDAEN_Set;
+  }
+  else
+  {
+    /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
+    USARTx->CTRL3 &= CTRL3_IRDAEN_Reset;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified USART flag is set or not.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg USART_FLAG_CTSF:  CTS Change flag (not available for UART4 and UART5)
+  *     @arg USART_FLAG_LBDF:  LIN Break detection flag
+  *     @arg USART_FLAG_TDE:  Transmit data register empty flag
+  *     @arg USART_FLAG_TRAC:   Transmission Complete flag
+  *     @arg USART_FLAG_RDNE: Receive data register not empty flag
+  *     @arg USART_FLAG_IDLEF: Idle Line detection flag
+  *     @arg USART_FLAG_ORERR:  OverRun Error flag
+  *     @arg USART_FLAG_NERR:   Noise Error flag
+  *     @arg USART_FLAG_FERR:   Framing Error flag
+  *     @arg USART_FLAG_PERR:   Parity Error flag
+  * @retval The new state of USART_FLAG (SET or RESET).
+  */
+FlagStatus USART_GetFlagStatus(USART_Type* USARTx, uint16_t USART_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_FLAG(USART_FLAG));
+
+  /* The CTS flag is not available for UART4 and UART5 */
+  if (USART_FLAG == USART_FLAG_CTSF)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }
+
+  if ((USARTx->STS & USART_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the USARTx's pending flags.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg USART_FLAG_CTSF:  CTS Change flag (not available for UART4 and UART5).
+  *     @arg USART_FLAG_LBDF:  LIN Break detection flag.
+  *     @arg USART_FLAG_TRAC:   Transmission Complete flag.
+  *     @arg USART_FLAG_RDNE: Receive data register not empty flag.
+  *
+  * @note
+  *   - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+  *     error) and IDLE (Idle line detected) flags are cleared by software
+  *     sequence: a read operation to USART_SR register (USART_GetFlagStatus())
+  *     followed by a read operation to USART_DR register (USART_ReceiveData()).
+  *   - RXNE flag can be also cleared by a read to the USART_DR register
+  *     (USART_ReceiveData()).
+  *   - TC flag can be also cleared by software sequence: a read operation to
+  *     USART_SR register (USART_GetFlagStatus()) followed by a write operation
+  *     to USART_DR register (USART_SendData()).
+  *   - TXE flag is cleared only by a write to the USART_DR register
+  *     (USART_SendData()).
+  * @retval None
+  */
+void USART_ClearFlag(USART_Type* USARTx, uint16_t USART_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+
+  /* The CTS flag is not available for UART4 and UART5 */
+  if ((USART_FLAG & USART_FLAG_CTSF) == USART_FLAG_CTSF)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }
+
+  USARTx->STS = (uint16_t)~USART_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified USART interrupt has occurred or not.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_INT: specifies the USART interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg USART_INT_CTSF:  CTS change interrupt (not available for UART4 and UART5)
+  *     @arg USART_INT_LBDF:  LIN Break detection interrupt
+  *     @arg USART_INT_TDE:  Tansmit Data Register empty interrupt
+  *     @arg USART_INT_TRAC:   Transmission complete interrupt
+  *     @arg USART_INT_RDNE: Receive Data register not empty interrupt
+  *     @arg USART_INT_IDLEF: Idle line detection interrupt
+  *     @arg USART_INT_ORERR:  OverRun Error interrupt
+  *     @arg USART_INT_NERR:   Noise Error interrupt
+  *     @arg USART_INT_FERR:   Framing Error interrupt
+  *     @arg USART_INT_PERR:   Parity Error interrupt
+  * @retval The new state of USART_INT (SET or RESET).
+  */
+ITStatus USART_GetITStatus(USART_Type* USARTx, uint16_t USART_INT)
+{
+  uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_GET_INT(USART_INT));
+
+  /* The CTS interrupt is not available for UART4 and UART5 */
+  if (USART_INT == USART_INT_CTSF)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }
+
+  /* Get the USART register index */
+  usartreg = (((uint8_t)USART_INT) >> 0x05);
+  /* Get the interrupt position */
+  itmask = USART_INT & INT_Mask;
+  itmask = (uint32_t)0x01 << itmask;
+
+  if (usartreg == 0x01) /* The INT  is in CTRL1 register */
+  {
+    itmask &= USARTx->CTRL1;
+  }
+  else if (usartreg == 0x02) /* The INT  is in CTRL2 register */
+  {
+    itmask &= USARTx->CTRL2;
+  }
+  else /* The INT  is in CR3 register */
+  {
+    itmask &= USARTx->CTRL3;
+  }
+
+  bitpos = USART_INT >> 0x08;
+  bitpos = (uint32_t)0x01 << bitpos;
+  bitpos &= USARTx->STS;
+
+  if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the USARTx's interrupt pending bits.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_INT: specifies the interrupt pending bit to clear.
+  *   This parameter can be one of the following values:
+  *     @arg USART_INT_CTSF:  CTS change interrupt (not available for UART4 and UART5)
+  *     @arg USART_INT_LBDF:  LIN Break detection interrupt
+  *     @arg USART_INT_TRAC:   Transmission complete interrupt.
+  *     @arg USART_INT_RDNE: Receive Data register not empty interrupt.
+  *
+  * @note
+  *   - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+  *     error) and IDLE (Idle line detected) pending bits are cleared by
+  *     software sequence: a read operation to USART_SR register
+  *     (USART_GetITStatus()) followed by a read operation to USART_DR register
+  *     (USART_ReceiveData()).
+  *   - RXNE pending bit can be also cleared by a read to the USART_DR register
+  *     (USART_ReceiveData()).
+  *   - TC pending bit can be also cleared by software sequence: a read
+  *     operation to USART_SR register (USART_GetITStatus()) followed by a write
+  *     operation to USART_DR register (USART_SendData()).
+  *   - TXE pending bit is cleared only by a write to the USART_DR register
+  *     (USART_SendData()).
+  * @retval None
+  */
+void USART_ClearITPendingBit(USART_Type* USARTx, uint16_t USART_INT)
+{
+  uint16_t bitpos = 0x00, itmask = 0x00;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLEAR_INT(USART_INT));
+
+  /* The CTS interrupt is not available for UART4 and UART5 */
+  if (USART_INT == USART_INT_CTSF)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }
+
+  bitpos = USART_INT >> 0x08;
+  itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+  USARTx->STS = (uint16_t)~itmask;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_wwdg.c

@@ -0,0 +1,213 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_wwdg.c
+ * Description  : at32f4xx WWDG source file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_wwdg.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup WWDG
+  * @brief WWDG driver modules
+  * @{
+  */
+
+/** @defgroup WWDG_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Private_Defines
+  * @{
+  */
+
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFSET         (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFG_OFFSET          (WWDG_OFFSET + 0x04)
+#define EWIEN_BitPos        0x09
+#define CFG_EWIEN_BBMAP     (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (EWIEN_BitPos * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CTRL_EN_Set         ((uint32_t)0x00000080)
+
+/* CFR register bit mask */
+#define CFG_PSC_Mask        ((uint32_t)0xFFFFFE7F)
+#define CFG_WCNTR_Mask      ((uint32_t)0xFFFFFF80)
+#define BIT_Mask            ((uint8_t)0x7F)
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void WWDG_Reset(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_WWDG, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1PERIPH_WWDG, DISABLE);
+}
+
+/**
+  * @brief  Sets the WWDG Prescaler.
+  * @param  WWDG_Prescaler: specifies the WWDG Prescaler.
+  *   This parameter can be one of the following values:
+  *     @arg WWDG_Psc_1: WWDG counter clock = (PCLK1/4096)/1
+  *     @arg WWDG_Psc_2: WWDG counter clock = (PCLK1/4096)/2
+  *     @arg WWDG_Psc_4: WWDG counter clock = (PCLK1/4096)/4
+  *     @arg WWDG_Psc_8: WWDG counter clock = (PCLK1/4096)/8
+  * @retval None
+  */
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_WWDG_PSC(WWDG_Prescaler));
+  /* Clear WDGTB[1:0] bits */
+  tmpreg = WWDG->CFG & CFG_PSC_Mask;
+  /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+  tmpreg |= WWDG_Prescaler;
+  /* Store the new value */
+  WWDG->CFG = tmpreg;
+}
+
+/**
+  * @brief  Sets the WWDG window value.
+  * @param  WindowValue: specifies the window value to be compared to the downcounter.
+  *   This parameter value must be lower than 0x80.
+  * @retval None
+  */
+void WWDG_SetWindowCounter(uint8_t WindowValue)
+{
+  __IO uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_WWDG_WCNTR(WindowValue));
+  /* Clear W[6:0] bits */
+
+  tmpreg = WWDG->CFG & CFG_WCNTR_Mask;
+
+  /* Set W[6:0] bits according to WindowValue value */
+  tmpreg |= WindowValue & (uint32_t) BIT_Mask;
+
+  /* Store the new value */
+  WWDG->CFG = tmpreg;
+}
+
+/**
+  * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
+  * @param  None
+  * @retval None
+  */
+void WWDG_EnableINT(void)
+{
+  *(__IO uint32_t *) CFG_EWIEN_BBMAP = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Sets the WWDG counter value.
+  * @param  Counter: specifies the watchdog counter value.
+  *   This parameter must be a number between 0x40 and 0x7F.
+  * @retval None
+  */
+void WWDG_SetCounter(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_CNTR(Counter));
+  /* Write to T[6:0] bits to configure the counter value, no need to do
+     a read-modify-write; writing a 0 to WDGA bit does nothing */
+  WWDG->CTRL = Counter & BIT_Mask;
+}
+
+/**
+  * @brief  Enables WWDG and load the counter value.
+  * @param  Counter: specifies the watchdog counter value.
+  *   This parameter must be a number between 0x40 and 0x7F.
+  * @retval None
+  */
+void WWDG_Enable(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_CNTR(Counter));
+  WWDG->CTRL = CTRL_EN_Set | Counter;
+}
+
+/**
+  * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
+  * @param  None
+  * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
+  */
+FlagStatus WWDG_GetFlagStatus(void)
+{
+  return (FlagStatus)(WWDG->STS);
+}
+
+/**
+  * @brief  Clears Early Wakeup interrupt flag.
+  * @param  None
+  * @retval None
+  */
+void WWDG_ClearFlag(void)
+{
+  WWDG->STS = (uint32_t)RESET;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/at32f4xx_xmc.c

@@ -0,0 +1,884 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_xmc.c
+ * Description  : at32f4xx XMC source file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f4xx_xmc.h"
+#include "at32f4xx_rcc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup XMC
+  * @brief XMC driver modules
+  * @{
+  */
+
+#if defined (AT32F403xx) || defined (AT32F403Axx) || defined (AT32F407xx)
+
+/** @defgroup XMC_Private_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Private_Defines
+  * @{
+  */
+
+/* --------------------- XMC registers bit mask ---------------------------- */
+
+/* XMC BCRx Mask */
+#define BK1CTRLx_EN_Set                     ((uint32_t)0x00000001)
+#define BK1CTRLx_EN_Reset                   ((uint32_t)0x000FFFFE)
+#define BK1CTRLx_NOREN_Set                  ((uint32_t)0x00000040)
+
+/* XMC PCRx Mask */
+#define BKxCTRL_EN_Set                      ((uint32_t)0x00000004)
+#define BKxCTRL_EN_Reset                    ((uint32_t)0x000FFFFB)
+#define BKxCTRL_ECCEN_Set                   ((uint32_t)0x00000040)
+#define BKxCTRL_ECCEN_Reset                 ((uint32_t)0x000FFFBF)
+#define BKxCTRL_Device_NAND                 ((uint32_t)0x00000008)
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup XMC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the XMC NOR/SRAM Banks registers to their default
+  *         reset values.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank1_NORSRAM1: XMC Bank1 NOR/SRAM1
+  *     @arg XMC_Bank1_NORSRAM2: XMC Bank1 NOR/SRAM2
+  *     @arg XMC_Bank1_NORSRAM3: XMC Bank1 NOR/SRAM3
+  *     @arg XMC_Bank1_NORSRAM4: XMC Bank1 NOR/SRAM4
+  * @retval None
+  */
+void XMC_NORSRAMReset(uint32_t XMC_Bank)
+{
+  /* Check the parameter */
+  assert_param(IS_XMC_NORSRAM_REGION(XMC_Bank));
+
+  /* XMC_Bank1_NORSRAM1 */
+  if(XMC_Bank == XMC_Bank1_NORSRAM1)
+  {
+    XMC_Bank1->BK1CTRLR[XMC_Bank] = 0x000030DB;
+  }
+  /* XMC_Bank1_NORSRAM2,  XMC_Bank1_NORSRAM3 or XMC_Bank1_NORSRAM4 */
+  else
+  {
+    XMC_Bank1->BK1CTRLR[XMC_Bank] = 0x000030D2;
+  }
+
+  XMC_Bank1->BK1CTRLR[XMC_Bank + 1] = 0x0FFFFFFF;
+  XMC_Bank1E->BK1TMGWR[XMC_Bank] = 0x0FFFFFFF;
+}
+
+/**
+  * @brief  Deinitializes the XMC NAND Banks registers to their default reset values.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  * @retval None
+  */
+void XMC_NANDReset(uint32_t XMC_Bank)
+{
+  /* Check the parameter */
+  assert_param(IS_XMC_NAND_BANK(XMC_Bank));
+
+  if(XMC_Bank == XMC_Bank2_NAND)
+  {
+    /* Set the XMC_Bank2 registers to their reset values */
+    XMC_Bank2->BK2CTRL = 0x00000018;
+    XMC_Bank2->BK2STS = 0x00000040;
+    XMC_Bank2->BK2TMGMEM = 0xFCFCFCFC;
+    XMC_Bank2->BK2TMGATT = 0xFCFCFCFC;
+  }
+  /* XMC_Bank3_NAND */
+  else
+  {
+    /* Set the XMC_Bank3 registers to their reset values */
+    XMC_Bank3->BK3CTRL = 0x00000018;
+    XMC_Bank3->BK3STS = 0x00000040;
+    XMC_Bank3->BK3TMGMEM = 0xFCFCFCFC;
+    XMC_Bank3->BK3TMGATT = 0xFCFCFCFC;
+  }
+}
+
+/**
+  * @brief  Deinitializes the XMC PCCARD Bank registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void XMC_PCCARDReset(void)
+{
+  /* Set the XMC_Bank4 registers to their reset values */
+  XMC_Bank4->BK4CTRL = 0x00000018;
+  XMC_Bank4->BK4STS = 0x00000000;
+  XMC_Bank4->BK4TMGMEM = 0xFCFCFCFC;
+  XMC_Bank4->BK4TMGATT = 0xFCFCFCFC;
+  XMC_Bank4->BK4TMGIO = 0xFCFCFCFC;
+}
+
+/**
+  * @brief  Initializes the XMC NOR/SRAM Banks according to the specified
+  *         parameters in the XMC_NORSRAMInitStruct.
+  * @param  XMC_NORSRAMInitStruct : pointer to a XMC_NORSRAMInitType
+  *         structure that contains the configuration information for
+  *        the XMC NOR/SRAM specified Banks.
+  * @retval None
+  */
+void XMC_NORSRAMInit(XMC_NORSRAMInitType* XMC_NORSRAMInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_XMC_NORSRAM_REGION(XMC_NORSRAMInitStruct->XMC_Bank));
+  assert_param(IS_XMC_MUX(XMC_NORSRAMInitStruct->XMC_DataAdrMux));
+  assert_param(IS_XMC_DEVICE(XMC_NORSRAMInitStruct->XMC_Dev));
+  assert_param(IS_XMC_BUS_TYPE(XMC_NORSRAMInitStruct->XMC_BusType));
+  assert_param(IS_XMC_BURSTMODE(XMC_NORSRAMInitStruct->XMC_EnableBurstMode));
+  assert_param(IS_XMC_ASYNWAIT(XMC_NORSRAMInitStruct->XMC_EnableAsynWait));
+  assert_param(IS_XMC_WAIT_SIGNAL_LEVEL(XMC_NORSRAMInitStruct->XMC_WaitSignalLv));
+  assert_param(IS_XMC_BURSTMODE_SPLIT(XMC_NORSRAMInitStruct->XMC_EnableBurstModeSplit));
+  assert_param(IS_XMC_WAIT_SIGNAL_CONFIG(XMC_NORSRAMInitStruct->XMC_WaitSignalConfig));
+  assert_param(IS_XMC_WRITE_OPERATION(XMC_NORSRAMInitStruct->XMC_EnableWrite));
+  assert_param(IS_XMC_WAIT_SIGNAL(XMC_NORSRAMInitStruct->XMC_EnableWaitSignal));
+  assert_param(IS_XMC_WRITE_TIMING(XMC_NORSRAMInitStruct->XMC_EnableWriteTiming));
+  assert_param(IS_XMC_WRITE_BURST_SYN(XMC_NORSRAMInitStruct->XMC_WriteBurstSyn));
+  assert_param(IS_XMC_ADDRESS_OP_TIME(XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_AdrOpTime));
+  assert_param(IS_XMC_ADDRESS_HOLD_TIME(XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_AdrHoldTime));
+  assert_param(IS_XMC_DATA_OP_TIME(XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_DataOpTime));
+  assert_param(IS_XMC_INTERVAL_BETWEEN_OP_TIME(XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_IntervalBetweenOP));
+  assert_param(IS_XMC_CLK_DIV(XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_CLKPsc));
+  assert_param(IS_XMC_DATA_STABLE_TIME(XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_DataStableTime));
+  assert_param(IS_XMC_MODE(XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_Mode));
+
+  /* Bank1 NOR/SRAM control register configuration */
+  XMC_Bank1->BK1CTRLR[XMC_NORSRAMInitStruct->XMC_Bank] =
+    (uint32_t)XMC_NORSRAMInitStruct->XMC_DataAdrMux |
+    XMC_NORSRAMInitStruct->XMC_Dev |
+    XMC_NORSRAMInitStruct->XMC_BusType |
+    XMC_NORSRAMInitStruct->XMC_EnableBurstMode |
+    XMC_NORSRAMInitStruct->XMC_EnableAsynWait |
+    XMC_NORSRAMInitStruct->XMC_WaitSignalLv |
+    XMC_NORSRAMInitStruct->XMC_EnableBurstModeSplit |
+    XMC_NORSRAMInitStruct->XMC_WaitSignalConfig |
+    XMC_NORSRAMInitStruct->XMC_EnableWrite |
+    XMC_NORSRAMInitStruct->XMC_EnableWaitSignal |
+    XMC_NORSRAMInitStruct->XMC_EnableWriteTiming |
+    XMC_NORSRAMInitStruct->XMC_WriteBurstSyn;
+
+  if(XMC_NORSRAMInitStruct->XMC_Dev == XMC_Dev_NOR)
+  {
+    XMC_Bank1->BK1CTRLR[XMC_NORSRAMInitStruct->XMC_Bank] |= (uint32_t)BK1CTRLx_NOREN_Set;
+  }
+
+  /* Bank1 NOR/SRAM timing register configuration */
+  XMC_Bank1->BK1CTRLR[XMC_NORSRAMInitStruct->XMC_Bank + 1] =
+    (uint32_t)XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_AdrOpTime |
+    (XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_AdrHoldTime << 4) |
+    (XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_DataOpTime << 8) |
+    (XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_IntervalBetweenOP << 16) |
+    (XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_CLKPsc << 20) |
+    (XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_DataStableTime << 24) |
+    XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_Mode;
+
+
+  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
+  if(XMC_NORSRAMInitStruct->XMC_EnableWriteTiming == XMC_WriteTiming_Enable)
+  {
+    assert_param(IS_XMC_ADDRESS_OP_TIME(XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_AdrOpTime));
+    assert_param(IS_XMC_ADDRESS_HOLD_TIME(XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_AdrHoldTime));
+    assert_param(IS_XMC_DATA_OP_TIME(XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_DataOpTime));
+    assert_param(IS_XMC_CLK_DIV(XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_CLKPsc));
+    assert_param(IS_XMC_DATA_STABLE_TIME(XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_DataStableTime));
+    assert_param(IS_XMC_MODE(XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_Mode));
+    XMC_Bank1E->BK1TMGWR[XMC_NORSRAMInitStruct->XMC_Bank] =
+      (uint32_t)XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_AdrOpTime |
+      (XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_AdrHoldTime << 4 ) |
+      (XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_DataOpTime << 8) |
+      (XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_CLKPsc << 20) |
+      (XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_DataStableTime << 24) |
+      XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_Mode;
+  }
+  else
+  {
+    XMC_Bank1E->BK1TMGWR[XMC_NORSRAMInitStruct->XMC_Bank] = 0x0FFFFFFF;
+  }
+}
+
+/**
+  * @brief  Initializes the XMC NAND Banks according to the specified
+  *         parameters in the XMC_NANDInitStruct.
+  * @param  XMC_NANDInitStruct : pointer to a XMC_NANDInitType
+  *         structure that contains the configuration information for the XMC
+  *         NAND specified Banks.
+  * @retval None
+  */
+void XMC_NANDInit(XMC_NANDInitType* XMC_NANDInitStruct)
+{
+  uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
+
+  /* Check the parameters */
+  assert_param( IS_XMC_NAND_BANK(XMC_NANDInitStruct->XMC_Bank));
+  assert_param( IS_XMC_WAIT_OPERATION(XMC_NANDInitStruct->XMC_EnableWait));
+  assert_param( IS_XMC_BUS_TYPE(XMC_NANDInitStruct->XMC_BusType));
+  assert_param( IS_XMC_ECC_OPERATION(XMC_NANDInitStruct->XMC_EnableECC));
+  assert_param( IS_XMC_ECCPAGE_SIZE(XMC_NANDInitStruct->XMC_ECCPageSize));
+  assert_param( IS_XMC_DELAY_CR_TIME(XMC_NANDInitStruct->XMC_DelayTimeCR));
+  assert_param( IS_XMC_DELAY_AR_TIME(XMC_NANDInitStruct->XMC_DelayTimeAR));
+  assert_param(IS_XMC_SETUP_TIME(XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_SetupTime));
+  assert_param(IS_XMC_OP_TIME(XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_OpTime));
+  assert_param(IS_XMC_HOLD_TIME(XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_HoldTime));
+  assert_param(IS_XMC_WRITE_SETUP_TIME(XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_WriteSetupTime));
+  assert_param(IS_XMC_SETUP_TIME(XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_SetupTime));
+  assert_param(IS_XMC_OP_TIME(XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_OpTime));
+  assert_param(IS_XMC_HOLD_TIME(XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_HoldTime));
+  assert_param(IS_XMC_WRITE_SETUP_TIME(XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_WriteSetupTime));
+
+  /* Set the tmppcr value according to XMC_NANDInitStruct parameters */
+  tmppcr = (uint32_t)XMC_NANDInitStruct->XMC_EnableWait |
+           BKxCTRL_Device_NAND |
+           XMC_NANDInitStruct->XMC_BusType |
+           XMC_NANDInitStruct->XMC_EnableECC |
+           XMC_NANDInitStruct->XMC_ECCPageSize |
+           (XMC_NANDInitStruct->XMC_DelayTimeCR << 9 ) |
+           (XMC_NANDInitStruct->XMC_DelayTimeAR << 13);
+
+  /* Set tmppmem value according to XMC_CommonSpaceTimingStructure parameters */
+  tmppmem = (uint32_t)XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_SetupTime |
+            (XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_OpTime << 8) |
+            (XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_HoldTime << 16) |
+            (XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_WriteSetupTime << 24);
+
+  /* Set tmppatt value according to XMC_AttributeSpaceTimingStructure parameters */
+  tmppatt = (uint32_t)XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_SetupTime |
+            (XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_OpTime << 8) |
+            (XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_HoldTime << 16) |
+            (XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_WriteSetupTime << 24);
+
+  if(XMC_NANDInitStruct->XMC_Bank == XMC_Bank2_NAND)
+  {
+    /* XMC_Bank2_NAND registers configuration */
+    XMC_Bank2->BK2CTRL = tmppcr;
+    XMC_Bank2->BK2TMGMEM = tmppmem;
+    XMC_Bank2->BK2TMGATT = tmppatt;
+  }
+  else
+  {
+    /* XMC_Bank3_NAND registers configuration */
+    XMC_Bank3->BK3CTRL = tmppcr;
+    XMC_Bank3->BK3TMGMEM = tmppmem;
+    XMC_Bank3->BK3TMGATT = tmppatt;
+  }
+}
+
+/**
+  * @brief  Initializes the XMC PCCARD Bank according to the specified
+  *         parameters in the XMC_PCCARDInitStruct.
+  * @param  XMC_PCCARDInitStruct : pointer to a XMC_PCCARDInitType
+  *         structure that contains the configuration information for the XMC
+  *         PCCARD Bank.
+  * @retval None
+  */
+void XMC_PCCARDInit(XMC_PCCARDInitType* XMC_PCCARDInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_XMC_WAIT_OPERATION(XMC_PCCARDInitStruct->XMC_EnableWait));
+  assert_param(IS_XMC_DELAY_CR_TIME(XMC_PCCARDInitStruct->XMC_DelayTimeCR));
+  assert_param(IS_XMC_DELAY_AR_TIME(XMC_PCCARDInitStruct->XMC_DelayTimeAR));
+
+  assert_param(IS_XMC_SETUP_TIME(XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_SetupTime));
+  assert_param(IS_XMC_OP_TIME(XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_OpTime));
+  assert_param(IS_XMC_HOLD_TIME(XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_HoldTime));
+  assert_param(IS_XMC_WRITE_SETUP_TIME(XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_WriteSetupTime));
+
+  assert_param(IS_XMC_SETUP_TIME(XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_SetupTime));
+  assert_param(IS_XMC_OP_TIME(XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_OpTime));
+  assert_param(IS_XMC_HOLD_TIME(XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_HoldTime));
+  assert_param(IS_XMC_WRITE_SETUP_TIME(XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_WriteSetupTime));
+  assert_param(IS_XMC_SETUP_TIME(XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_SetupTime));
+  assert_param(IS_XMC_OP_TIME(XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_OpTime));
+  assert_param(IS_XMC_HOLD_TIME(XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_HoldTime));
+  assert_param(IS_XMC_WRITE_SETUP_TIME(XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_WriteSetupTime));
+
+  /* Set the PCR4 register value according to XMC_PCCARDInitStruct parameters */
+  XMC_Bank4->BK4CTRL = (uint32_t)XMC_PCCARDInitStruct->XMC_EnableWait |
+                       XMC_BusType_16b |
+                       (XMC_PCCARDInitStruct->XMC_DelayTimeCR << 9) |
+                       (XMC_PCCARDInitStruct->XMC_DelayTimeAR << 13);
+
+  /* Set PMEM4 register value according to XMC_CommonSpaceTimingStructure parameters */
+  XMC_Bank4->BK4TMGMEM = (uint32_t)XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_SetupTime |
+                         (XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_OpTime << 8) |
+                         (XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_HoldTime << 16) |
+                         (XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_WriteSetupTime << 24);
+
+  /* Set PATT4 register value according to XMC_AttributeSpaceTimingStructure parameters */
+  XMC_Bank4->BK4TMGATT = (uint32_t)XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_SetupTime |
+                         (XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_OpTime << 8) |
+                         (XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_HoldTime << 16) |
+                         (XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_WriteSetupTime << 24);
+
+  /* Set PIO4 register value according to XMC_IOSpaceTimingStructure parameters */
+  XMC_Bank4->BK4TMGIO = (uint32_t)XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_SetupTime |
+                        (XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_OpTime << 8) |
+                        (XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_HoldTime << 16) |
+                        (XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_WriteSetupTime << 24);
+}
+
+/**
+  * @brief  Fills each XMC_NORSRAMInitStruct member with its default value.
+  * @param  XMC_NORSRAMInitStruct: pointer to a XMC_NORSRAMInitType
+  *         structure which will be initialized.
+  * @retval None
+  */
+void XMC_NORSRAMStructInit(XMC_NORSRAMInitType* XMC_NORSRAMInitStruct)
+{
+  /* Reset NOR/SRAM Init structure parameters values */
+  XMC_NORSRAMInitStruct->XMC_Bank = XMC_Bank1_NORSRAM1;
+  XMC_NORSRAMInitStruct->XMC_DataAdrMux = XMC_DataAdrMux_Enable;
+  XMC_NORSRAMInitStruct->XMC_Dev = XMC_Dev_SRAM;
+  XMC_NORSRAMInitStruct->XMC_BusType = XMC_BusType_8b;
+  XMC_NORSRAMInitStruct->XMC_EnableBurstMode = XMC_BurstMode_Disable;
+  XMC_NORSRAMInitStruct->XMC_EnableAsynWait = XMC_AsynWait_Disable;
+  XMC_NORSRAMInitStruct->XMC_WaitSignalLv = XMC_WaitSignalLv_Low;
+  XMC_NORSRAMInitStruct->XMC_EnableBurstModeSplit = XMC_BurstModeSplit_Disable;
+  XMC_NORSRAMInitStruct->XMC_WaitSignalConfig = XMC_WaitSignalConfig_BeforeWaitState;
+  XMC_NORSRAMInitStruct->XMC_EnableWrite = XMC_WriteOperation_Enable;
+  XMC_NORSRAMInitStruct->XMC_EnableWaitSignal = XMC_WaitSignal_Enable;
+  XMC_NORSRAMInitStruct->XMC_EnableWriteTiming = XMC_WriteTiming_Disable;
+  XMC_NORSRAMInitStruct->XMC_WriteBurstSyn = XMC_WriteBurstSyn_Disable;
+  XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_AdrOpTime = 0xF;
+  XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_AdrHoldTime = 0xF;
+  XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_DataOpTime = 0xFF;
+  XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_IntervalBetweenOP = 0xF;
+  XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_CLKPsc = 0xF;
+  XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_DataStableTime = 0xF;
+  XMC_NORSRAMInitStruct->XMC_RWTimingStruct->XMC_Mode = XMC_Mode_A;
+  XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_AdrOpTime = 0xF;
+  XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_AdrHoldTime = 0xF;
+  XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_DataOpTime = 0xFF;
+  XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_IntervalBetweenOP = 0xF;
+  XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_CLKPsc = 0xF;
+  XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_DataStableTime = 0xF;
+  XMC_NORSRAMInitStruct->XMC_WTimingStruct->XMC_Mode = XMC_Mode_A;
+}
+
+/**
+  * @brief  Fills each XMC_NANDInitStruct member with its default value.
+  * @param  XMC_NANDInitStruct: pointer to a XMC_NANDInitType
+  *         structure which will be initialized.
+  * @retval None
+  */
+void XMC_NANDStructInit(XMC_NANDInitType* XMC_NANDInitStruct)
+{
+  /* Reset NAND Init structure parameters values */
+  XMC_NANDInitStruct->XMC_Bank = XMC_Bank2_NAND;
+  XMC_NANDInitStruct->XMC_EnableWait = XMC_WaitOperation_Disable;
+  XMC_NANDInitStruct->XMC_BusType = XMC_BusType_8b;
+  XMC_NANDInitStruct->XMC_EnableECC = XMC_ECCOperation_Disable;
+  XMC_NANDInitStruct->XMC_ECCPageSize = XMC_ECCPageSize_256Bytes;
+  XMC_NANDInitStruct->XMC_DelayTimeCR = 0x0;
+  XMC_NANDInitStruct->XMC_DelayTimeAR = 0x0;
+  XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_SetupTime = 0xFC;
+  XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_OpTime = 0xFC;
+  XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_HoldTime = 0xFC;
+  XMC_NANDInitStruct->XMC_CommonSpaceTimingStruct->XMC_WriteSetupTime = 0xFC;
+  XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_SetupTime = 0xFC;
+  XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_OpTime = 0xFC;
+  XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_HoldTime = 0xFC;
+  XMC_NANDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_WriteSetupTime = 0xFC;
+}
+
+/**
+  * @brief  Fills each XMC_PCCARDInitStruct member with its default value.
+  * @param  XMC_PCCARDInitStruct: pointer to a XMC_PCCARDInitType
+  *         structure which will be initialized.
+  * @retval None
+  */
+void XMC_PCCARDStructInit(XMC_PCCARDInitType* XMC_PCCARDInitStruct)
+{
+  /* Reset PCCARD Init structure parameters values */
+  XMC_PCCARDInitStruct->XMC_EnableWait = XMC_WaitOperation_Disable;
+  XMC_PCCARDInitStruct->XMC_DelayTimeCR = 0x0;
+  XMC_PCCARDInitStruct->XMC_DelayTimeAR = 0x0;
+  XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_SetupTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_OpTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_HoldTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_CommonSpaceTimingStruct->XMC_WriteSetupTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_SetupTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_OpTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_HoldTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_AttributeSpaceTimingStruct->XMC_WriteSetupTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_SetupTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_OpTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_HoldTime = 0xFC;
+  XMC_PCCARDInitStruct->XMC_IOSpaceTimingStruct->XMC_WriteSetupTime = 0xFC;
+}
+
+/**
+  * @brief  Config the bus turnaround phase
+  * @param  XMC_SubBank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_SubBank1_NORSRAM1: XMC SubBank1 NOR/SRAM1
+  *     @arg XMC_SubBank1_NORSRAM2: XMC SubBank1 NOR/SRAM2
+  *     @arg XMC_SubBank1_NORSRAM3: XMC SubBank1 NOR/SRAM3
+  *     @arg XMC_SubBank1_NORSRAM4: XMC SubBank1 NOR/SRAM4
+  * @param  W2W_Timing: Bus turnaround phase for consecutive write duration.from 0 to 255 HCLK, default:8 HCLK
+  * @param  R2R_Timing: Bus turnaround phase for consecutive read duration.from 0 to 255 HCLK, default:8 HCLK
+  * @retval None
+  */
+void XMC_ExtTimingConfig(uint32_t XMC_SubBank, uint8_t W2W_Timing, uint8_t R2R_Timing)
+{
+  assert_param(IS_XMC_Sub_NORSRAM_REGION(XMC_SubBank)); 
+  
+  XMC_Bank1H->BK1EXT[XMC_SubBank] &= 0;
+  XMC_Bank1H->BK1EXT[XMC_SubBank] |= (W2W_Timing|(R2R_Timing<<8));  
+}
+
+/**
+  * @brief  Enables or disables the specified NOR/SRAM Memory Bank.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank1_NORSRAM1: XMC Bank1 NOR/SRAM1
+  *     @arg XMC_Bank1_NORSRAM2: XMC Bank1 NOR/SRAM2
+  *     @arg XMC_Bank1_NORSRAM3: XMC Bank1 NOR/SRAM3
+  *     @arg XMC_Bank1_NORSRAM4: XMC Bank1 NOR/SRAM4
+  * @param  NewState: new state of the XMC_Bank. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void XMC_NORSRAMCmd(uint32_t XMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_XMC_NORSRAM_REGION(XMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
+    XMC_Bank1->BK1CTRLR[XMC_Bank] |= BK1CTRLx_EN_Set;
+  }
+  else
+  {
+    /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
+    XMC_Bank1->BK1CTRLR[XMC_Bank] &= BK1CTRLx_EN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified NAND Memory Bank.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  * @param  NewState: new state of the XMC_Bank. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void XMC_NANDCmd(uint32_t XMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_XMC_NAND_BANK(XMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
+    if(XMC_Bank == XMC_Bank2_NAND)
+    {
+      XMC_Bank2->BK2CTRL |= BKxCTRL_EN_Set;
+    }
+    else
+    {
+      XMC_Bank3->BK3CTRL |= BKxCTRL_EN_Set;
+    }
+  }
+  else
+  {
+    /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
+    if(XMC_Bank == XMC_Bank2_NAND)
+    {
+      XMC_Bank2->BK2CTRL &= BKxCTRL_EN_Reset;
+    }
+    else
+    {
+      XMC_Bank3->BK3CTRL &= BKxCTRL_EN_Reset;
+    }
+  }
+}
+
+/**
+  * @brief  Enables or disables the PCCARD Memory Bank.
+  * @param  NewState: new state of the PCCARD Memory Bank.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void XMC_PCCARDCmd(FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
+    XMC_Bank4->BK4CTRL |= BKxCTRL_EN_Set;
+  }
+  else
+  {
+    /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
+    XMC_Bank4->BK4CTRL &= BKxCTRL_EN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the XMC NAND ECC feature.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  * @param  NewState: new state of the XMC NAND ECC feature.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void XMC_NANDECCCmd(uint32_t XMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_XMC_NAND_BANK(XMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
+    if(XMC_Bank == XMC_Bank2_NAND)
+    {
+      XMC_Bank2->BK2CTRL |= BKxCTRL_ECCEN_Set;
+    }
+    else
+    {
+      XMC_Bank3->BK3CTRL |= BKxCTRL_ECCEN_Set;
+    }
+  }
+  else
+  {
+    /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
+    if(XMC_Bank == XMC_Bank2_NAND)
+    {
+      XMC_Bank2->BK2CTRL &= BKxCTRL_ECCEN_Reset;
+    }
+    else
+    {
+      XMC_Bank3->BK3CTRL &= BKxCTRL_ECCEN_Reset;
+    }
+  }
+}
+
+/**
+  * @brief  Returns the error correction code register value.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  * @retval The Error Correction Code (ECC) value.
+  */
+uint32_t XMC_GetECC(uint32_t XMC_Bank)
+{
+  uint32_t eccval = 0x00000000;
+
+  if(XMC_Bank == XMC_Bank2_NAND)
+  {
+    /* Get the BK2ECC register value */
+    eccval = XMC_Bank2->BK2ECC;
+  }
+  else
+  {
+    /* Get the BK3ECC register value */
+    eccval = XMC_Bank3->BK3ECC;
+  }
+
+  /* Return the error correction code value */
+  return(eccval);
+}
+
+/**
+  * @brief  Enables or disables the specified XMC interrupts.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  *     @arg XMC_Bank4_PCCARD: XMC Bank4 PCCARD
+  * @param  XMC_INT: specifies the XMC interrupt sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg XMC_INT_RisingEdge: Rising edge detection interrupt.
+  *     @arg XMC_INT_Level: Level edge detection interrupt.
+  *     @arg XMC_INT_FallingEdge: Falling edge detection interrupt.
+  * @param  NewState: new state of the specified XMC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void XMC_INTConfig(uint32_t XMC_Bank, uint32_t XMC_INT, FunctionalState NewState)
+{
+  assert_param(IS_XMC_INT_BANK(XMC_Bank));
+  assert_param(IS_XMC_INT(XMC_INT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected XMC_Bank2 interrupts */
+    if(XMC_Bank == XMC_Bank2_NAND)
+    {
+      XMC_Bank2->BK2STS |= XMC_INT;
+    }
+    /* Enable the selected XMC_Bank3 interrupts */
+    else if (XMC_Bank == XMC_Bank3_NAND)
+    {
+      XMC_Bank3->BK3STS |= XMC_INT;
+    }
+    /* Enable the selected XMC_Bank4 interrupts */
+    else
+    {
+      XMC_Bank4->BK4STS |= XMC_INT;
+    }
+  }
+  else
+  {
+    /* Disable the selected XMC_Bank2 interrupts */
+    if(XMC_Bank == XMC_Bank2_NAND)
+    {
+
+      XMC_Bank2->BK2STS &= (uint32_t)~XMC_INT;
+    }
+    /* Disable the selected XMC_Bank3 interrupts */
+    else if (XMC_Bank == XMC_Bank3_NAND)
+    {
+      XMC_Bank3->BK3STS &= (uint32_t)~XMC_INT;
+    }
+    /* Disable the selected XMC_Bank4 interrupts */
+    else
+    {
+      XMC_Bank4->BK4STS &= (uint32_t)~XMC_INT;
+    }
+  }
+}
+
+/**
+  * @brief  Checks whether the specified XMC flag is set or not.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  *     @arg XMC_Bank4_PCCARD: XMC Bank4 PCCARD
+  * @param  XMC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg XMC_FLAG_RisingEdge: Rising egde detection Flag.
+  *     @arg XMC_FLAG_Level: Level detection Flag.
+  *     @arg XMC_FLAG_FallingEdge: Falling egde detection Flag.
+  *     @arg XMC_FLAG_FEMPT: Fifo empty Flag.
+  * @retval The new state of XMC_FLAG (SET or RESET).
+  */
+FlagStatus XMC_GetFlagStatus(uint32_t XMC_Bank, uint32_t XMC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpsr = 0x00000000;
+
+  /* Check the parameters */
+  assert_param(IS_XMC_GETFLAG_BANK(XMC_Bank));
+  assert_param(IS_XMC_GET_FLAG(XMC_FLAG));
+
+  if(XMC_Bank == XMC_Bank2_NAND)
+  {
+    tmpsr = XMC_Bank2->BK2STS;
+  }
+  else if(XMC_Bank == XMC_Bank3_NAND)
+  {
+    tmpsr = XMC_Bank3->BK3STS;
+  }
+  /* XMC_Bank4_PCCARD*/
+  else
+  {
+    tmpsr = XMC_Bank4->BK4STS;
+  }
+
+  /* Get the flag status */
+  if ((tmpsr & XMC_FLAG) != (uint16_t)RESET )
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the XMC's pending flags.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  *     @arg XMC_Bank4_PCCARD: XMC Bank4 PCCARD
+  * @param  XMC_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg XMC_FLAG_RisingEdge: Rising egde detection Flag.
+  *     @arg XMC_FLAG_Level: Level detection Flag.
+  *     @arg XMC_FLAG_FallingEdge: Falling egde detection Flag.
+  * @retval None
+  */
+void XMC_ClearFlag(uint32_t XMC_Bank, uint32_t XMC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_XMC_GETFLAG_BANK(XMC_Bank));
+  assert_param(IS_XMC_CLEAR_FLAG(XMC_FLAG)) ;
+
+  if(XMC_Bank == XMC_Bank2_NAND)
+  {
+    XMC_Bank2->BK2STS &= ~XMC_FLAG;
+  }
+  else if(XMC_Bank == XMC_Bank3_NAND)
+  {
+    XMC_Bank3->BK3STS &= ~XMC_FLAG;
+  }
+  /* XMC_Bank4_PCCARD*/
+  else
+  {
+    XMC_Bank4->BK4STS &= ~XMC_FLAG;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified XMC interrupt has occurred or not.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  *     @arg XMC_Bank4_PCCARD: XMC Bank4 PCCARD
+  * @param  XMC_INT: specifies the XMC interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg XMC_INT_RisingEdge: Rising edge detection interrupt.
+  *     @arg XMC_INT_Level: Level edge detection interrupt.
+  *     @arg XMC_INT_FallingEdge: Falling edge detection interrupt.
+  * @retval The new state of XMC_INT (SET or RESET).
+  */
+ITStatus XMC_GetINTStatus(uint32_t XMC_Bank, uint32_t XMC_INT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
+
+  /* Check the parameters */
+  assert_param(IS_XMC_INT_BANK(XMC_Bank));
+  assert_param(IS_XMC_GET_INT(XMC_INT));
+
+  if(XMC_Bank == XMC_Bank2_NAND)
+  {
+    tmpsr = XMC_Bank2->BK2STS;
+  }
+  else if(XMC_Bank == XMC_Bank3_NAND)
+  {
+    tmpsr = XMC_Bank3->BK3STS;
+  }
+  /* XMC_Bank4_PCCARD*/
+  else
+  {
+    tmpsr = XMC_Bank4->BK4STS;
+  }
+
+  itstatus = tmpsr & XMC_INT;
+
+  itenable = tmpsr & (XMC_INT >> 3);
+
+  if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the XMC's interrupt pending bits.
+  * @param  XMC_Bank: specifies the XMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg XMC_Bank2_NAND: XMC Bank2 NAND
+  *     @arg XMC_Bank3_NAND: XMC Bank3 NAND
+  *     @arg XMC_Bank4_PCCARD: XMC Bank4 PCCARD
+  * @param  XMC_INT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg XMC_INT_RisingEdge: Rising edge detection interrupt.
+  *     @arg XMC_INT_Level: Level edge detection interrupt.
+  *     @arg XMC_INT_FallingEdge: Falling edge detection interrupt.
+  * @retval None
+  */
+void XMC_ClearINTPendingBit(uint32_t XMC_Bank, uint32_t XMC_INT)
+{
+  /* Check the parameters */
+  assert_param(IS_XMC_INT_BANK(XMC_Bank));
+  assert_param(IS_XMC_INT(XMC_INT));
+
+  if(XMC_Bank == XMC_Bank2_NAND)
+  {
+    XMC_Bank2->BK2STS &= ~(XMC_INT >> 3);
+  }
+  else if(XMC_Bank == XMC_Bank3_NAND)
+  {
+    XMC_Bank3->BK3STS &= ~(XMC_INT >> 3);
+  }
+  /* XMC_Bank4_PCCARD*/
+  else
+  {
+    XMC_Bank4->BK4STS &= ~(XMC_INT >> 3);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* AT32F403xx || AT32F403Axx || AT32F407xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/src/misc.c

@@ -0,0 +1,214 @@
+/**
+ **************************************************************************
+ * File Name    : misc.c
+ * Description  : at32f4xx MISC source file
+ * Date         : 2018-10-08
+ * Version      : V1.0.5
+ **************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "misc.h"
+
+/** @addtogroup at32f4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup MISC
+  * @brief MISC driver modules
+  * @{
+  */
+
+/** @defgroup MISC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Defines
+  * @{
+  */
+
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Configures the priority grouping: pre-emption priority and subpriority.
+  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+  *                                4 bits for subpriority
+  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+  *                                3 bits for subpriority
+  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+  *                                2 bits for subpriority
+  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+  *                                1 bits for subpriority
+  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+  *                                0 bits for subpriority
+  * @retval None
+  */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+
+  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+  * @brief  Initializes the NVIC peripheral according to the specified
+  *         parameters in the NVIC_InitStruct.
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitType structure that contains
+  *         the configuration information for the specified NVIC peripheral.
+  * @retval None
+  */
+void NVIC_Init(NVIC_InitType* NVIC_InitStruct)
+{
+  uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+  {
+    /* Compute the Corresponding IRQ Priority --------------------------------*/
+    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700)) >> 0x08;
+    tmppre = (0x4 - tmppriority);
+    tmpsub = tmpsub >> tmppriority;
+
+    tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+    tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+    tmppriority = tmppriority << 0x04;
+
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+    /* Enable the Selected IRQ Channels --------------------------------------*/
+    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+  else
+  {
+    /* Disable the Selected IRQ Channels -------------------------------------*/
+    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+}
+
+/**
+  * @brief  Sets the vector table location and Offset.
+  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_VectTab_RAM
+  *     @arg NVIC_VectTab_FLASH
+  * @param  Offset: Vector Table base offset field. This value must be a multiple
+  *         of 0x200.
+  * @retval None
+  */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+  assert_param(IS_NVIC_OFFSET(Offset));
+
+  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+  * @brief  Selects the condition for the system to enter low power mode.
+  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_LP_SEVONPEND
+  *     @arg NVIC_LP_SLEEPDEEP
+  *     @arg NVIC_LP_SLEEPONEXIT
+  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_LP(LowPowerMode));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    SCB->SCR |= LowPowerMode;
+  }
+  else
+  {
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+  }
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  SysTick_CLKSource: specifies the SysTick clock source.
+  *   This parameter can be one of the following values:
+  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+  {
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/inc/at32f4xx.h

@@ -0,0 +1,9908 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx.h
+ * Description  : at32f4xx peripheral access layer header file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup at32f4xx
+  * @{
+  */
+
+#ifndef __AT32F4xx_H
+#define __AT32F4xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/* Uncomment the line below according to the target AT32 device used in your
+   application
+  */
+#if !defined (AT32F403Cx_MD) && !defined (AT32F403Cx_HD) && \
+    !defined (AT32F403Cx_XL) && !defined (AT32F403Rx_HD) && \
+    !defined (AT32F403Rx_XL) && !defined (AT32F403Vx_HD) && \
+    !defined (AT32F403Vx_XL) && !defined (AT32F403Zx_HD) && \
+    !defined (AT32F403Zx_XL) && \
+    !defined (AT32F413Kx_MD) && !defined (AT32F413Kx_HD) && \
+    !defined (AT32F413Cx_MD) && !defined (AT32F413Cx_HD) && \
+    !defined (AT32F413Rx_MD) && !defined (AT32F413Rx_HD) && \
+    !defined (AT32FEBKCx_MD) && !defined (TS32F401CBU7)  && \
+    !defined (AT32F415C8T7)  && !defined (AT32F415CBT7)  && !defined (AT32F415CCT7)  && \
+    !defined (AT32F415CBU7)  && !defined (AT32F415CCU7)  && !defined (AT32F415R8T7)  && \
+    !defined (AT32F415RBT7)  && !defined (AT32F415RCT7)  && !defined (AT32F415K8U7_4)&& \
+    !defined (AT32F415KBU7_4)&& !defined (AT32F415KCU7_4)&& !defined (AT32F415R8T7_7)&& \
+    !defined (AT32F415RBT7_7)&& !defined (AT32F415RCT7_7)&& \
+    !defined (AT32F407RGT7)  && !defined (AT32F407VGT7)  && !defined (AT32F407RCT7)  && \
+    !defined (AT32F407VCT7)  && \
+    !defined (AT32F403AVCT7) && !defined (AT32F403ARCT7) && !defined (AT32F403ACCT7) && \
+    !defined (AT32F403ACCU7) && !defined (AT32F403AVGT7) && !defined (AT32F403ACGT7) && \
+    !defined (AT32F403ARGT7) && !defined (AT32F403ACGU7) && !defined (AT32F403AVET7) && \
+    !defined (AT32F403ARET7) && !defined (AT32F403ACEU7) && !defined (AT32F403ACET7)
+/* #define AT32F403Cx_MD */   /*!< AT32F403Cx_MD: LQFP48, Medium density devices: AT32F403CB */
+/* #define AT32F403Cx_HD */   /*!< AT32F403Cx_HD: LQFP48, High density devices: AT32F403CC, AT32F403CE */
+/* #define AT32F403Cx_XL */   /*!< AT32F403Cx_XL: LQFP48, XL-density devices: AT32F403CG */
+/* #define AT32F403Rx_HD */   /*!< AT32F403Rx_HD: LQFP64, High density devices: AT32F403RC, AT32F403RE */
+/* #define AT32F403Rx_XL */   /*!< AT32F403Rx_XL: LQFP64, XL-density devices: AT32F403RG */
+/* #define AT32F403Vx_HD */   /*!< AT32F403Vx_HD: LQFP100, High density devices: AT32F403VC, AT32F403VE */
+/* #define AT32F403Vx_XL */   /*!< AT32F403Vx_XL: LQFP100, XL-density devices: AT32F403VG */
+/* #define AT32F403Zx_HD */   /*!< AT32F403Zx_HD: LQFP144, High density devices: AT32F403ZC, AT32F403ZE */
+/* #define AT32F403Zx_XL */   /*!< AT32F403Zx_XL: LQFP144, XL-density devices: AT32F403ZG */
+
+/* #define AT32F413Kx_MD */   /*!< AT32F413Kx_MD: LQFP32, Medium density devices: AT32F413KB */
+/* #define AT32F413Kx_HD */   /*!< AT32F413Kx_HD: LQFP32, High density devices: AT32F413KC */
+/* #define AT32F413Cx_MD */   /*!< AT32F413Cx_MD: LQFP48, Medium density devices: AT32F413C8, AT32F413CB */
+/* #define AT32F413Cx_HD */   /*!< AT32F413Cx_HD: LQFP48, High density devices: AT32F413CC */
+/* #define AT32F413Rx_MD */   /*!< AT32F413Rx_MD: LQFP64, Medium density devices: AT32F413RB */
+/* #define AT32F413Rx_HD */   /*!< AT32F413Rx_HD: LQFP64, High density devices: AT32F413RC */
+/* #define AT32FEBKCx_MD */   /*!< AT32FEBKCx_MD: LQFP48, Medium density devices: AT32FEBKC8*/
+/* #define TS32F401CBU7 */    /*!< TS32F401CBU7: QFN48, Medium density devices: TS32F401CBU7 */
+
+/* #define AT32F415C8T7 */    /*!< AT32F415C8T7: LQFP48, Medium density devices: AT32F415C8T7 */
+/* #define AT32F415CBT7 */    /*!< AT32F415CBT7: LQFP48, Medium density devices: AT32F415CBT7 */
+/* #define AT32F415CCT7 */    /*!< AT32F415CCT7: LQFP48, High density devices: AT32F415CCT7 */
+/* #define AT32F415CBU7 */    /*!< AT32F415CBU7: QFN48, Medium density devices: AT32F415CBU7 */
+/* #define AT32F415CCU7 */    /*!< AT32F415CCU7: QFN48, High density devices: AT32F415CCU7 */
+/* #define AT32F415R8T7 */    /*!< AT32F415R8T7: LQFP64, Medium density devices: AT32F415R8T7 */
+/* #define AT32F415RBT7 */    /*!< AT32F415RBT7: LQFP64, Medium density devices: AT32F415RBT7 */
+/* #define AT32F415RCT7 */    /*!< AT32F415RCT7: LQFP64, High density devices: AT32F415RCT7 */
+/* #define AT32F415K8U7_4 */  /*!< AT32F415K8U7_4: QFN32, Medium density devices: AT32F415K8U7_4 */
+/* #define AT32F415KBU7_4 */  /*!< AT32F415KBU7_4: QFN32, Medium density devices: AT32F415KBU7_4 */
+/* #define AT32F415KCU7_4 */  /*!< AT32F415KCU7_4: QFN32, High density devices: AT32F415KCU7_4 */
+/* #define AT32F415R8T7_7 */  /*!< AT32F415R8T7_7: LQFP64, Medium density devices: AT32F415R8T7_7 */
+/* #define AT32F415RBT7_7 */  /*!< AT32F415RBT7_7: LQFP64, Medium density devices: AT32F415RBT7_7 */
+/* #define AT32F415RCT7_7 */  /*!< AT32F415RCT7_7: LQFP64, High density devices: AT32F415RCT7_7 */
+
+/* #define AT32F407RGT7 */    /*!< AT32F407RGT7: LQFP64, XL-density devices: AT32F407RGT7 */
+/* #define AT32F407VGT7 */    /*!< AT32F407VGT7: LQFP100, XL-density devices: AT32F407VGT7 */
+/* #define AT32F407RET7 */    /*!< AT32F407RET7: LQFP64, XL-density devices: AT32F407RET7 */
+/* #define AT32F407VET7 */    /*!< AT32F407VET7: LQFP100, XL-density devices: AT32F407VET7 */
+/* #define AT32F407RCT7 */    /*!< AT32F407RCT7: LQFP64, High density devices: AT32F407RCT7 */
+/* #define AT32F407VCT7 */    /*!< AT32F407VCT7: LQFP100, High density devices: AT32F407VCT7 */
+
+/* #define AT32F403AVCT7 */   /*!< AT32F403AVCT7: LQFP100, High density devices: AT32F403AVCT7 */
+/* #define AT32F403ARCT7 */   /*!< AT32F403ARCT7: LQFP64, High density devices: AT32F403ARCT7 */
+/* #define AT32F403ACCT7 */   /*!< AT32F403ACCT7: LQFP48, High density devices: AT32F403ACCT7 */
+/* #define AT32F403ACCU7 */   /*!< AT32F403ACCU7: QFN48, High density devices: AT32F403ACCU7 */
+/* #define AT32F403AVET7 */   /*!< AT32F403AVET7: LQFP100, XL-density devices: AT32F403AVET7 */
+/* #define AT32F403ARET7 */   /*!< AT32F403ARET7: LQFP64, XL-density devices: AT32F403ARET7 */
+/* #define AT32F403ACET7 */   /*!< AT32F403ACET7: LQFP48, XL-density devices: AT32F403ACET7 */
+/* #define AT32F403ACEU7 */   /*!< AT32F403ACEU7: QFN48, XL-density devices: AT32F403ACEU7 */
+/* #define AT32F403AVGT7 */   /*!< AT32F403AVGT7: LQFP100, XL-density devices: AT32F403AVGT7 */
+/* #define AT32F403ACGT7 */   /*!< AT32F403ACGT7: LQFP48, XL-density devices: AT32F403ACGT7 */
+/* #define AT32F403ARGT7 */   /*!< AT32F403ARGT7: LQFP64, XL-density devices: AT32F403ARGT7 */
+/* #define AT32F403ACGU7 */   /*!< AT32F403ACGU7: QFN48, XL-density devices: AT32F403ACGU7 */
+
+#endif
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+
+ - Medium-density devices are at32f4xx microcontrollers where
+   the Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density devices are at32f4xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are at32f4xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+  */
+
+#if !defined (AT32F403Cx_MD) && !defined (AT32F403Cx_HD) && \
+    !defined (AT32F403Cx_XL) && !defined (AT32F403Rx_HD) && \
+    !defined (AT32F403Rx_XL) && !defined (AT32F403Vx_HD) && \
+    !defined (AT32F403Vx_XL) && !defined (AT32F403Zx_HD) && \
+    !defined (AT32F403Zx_XL) && \
+    !defined (AT32F413Kx_MD) && !defined (AT32F413Kx_HD) && \
+    !defined (AT32F413Cx_MD) && !defined (AT32F413Cx_HD) && \
+    !defined (AT32F413Rx_MD) && !defined (AT32F413Rx_HD) && \
+    !defined (AT32FEBKCx_MD) && !defined (TS32F401CBU7)  && \
+    !defined (AT32F415C8T7)  && !defined (AT32F415CBT7)  && !defined (AT32F415CCT7)  && \
+    !defined (AT32F415CBU7)  && !defined (AT32F415CCU7)  && !defined (AT32F415R8T7)  && \
+    !defined (AT32F415RBT7)  && !defined (AT32F415RCT7)  && !defined (AT32F415K8U7_4)&& \
+    !defined (AT32F415KBU7_4)&& !defined (AT32F415KCU7_4)&& !defined (AT32F415R8T7_7)&& \
+    !defined (AT32F415RBT7_7)&& !defined (AT32F415RCT7_7)&& \
+    !defined (AT32F407RGT7)  && !defined (AT32F407VGT7)  && !defined (AT32F407RCT7)  && \
+    !defined (AT32F407VCT7)  && !defined (AT32F407RET7)  && !defined (AT32F407VET7)  && \
+    !defined (AT32F403AVCT7) && !defined (AT32F403ARCT7) && !defined (AT32F403ACCT7) && \
+    !defined (AT32F403ACCU7) && !defined (AT32F403AVGT7) && !defined (AT32F403ACGT7) && \
+    !defined (AT32F403ARGT7) && !defined (AT32F403ACGU7) && !defined (AT32F403AVET7) && \
+    !defined (AT32F403ARET7) && !defined (AT32F403ACET7) && !defined (AT32F403ACEU7)
+#error "Please select first the target at32f4xx device used in your application (in at32f4xx.h file)"
+#endif
+
+#if defined (AT32F403Cx_MD) || defined (AT32F403Cx_HD) || \
+    defined (AT32F403Cx_XL) || defined (AT32F403Rx_HD) || \
+    defined (AT32F403Rx_XL) || defined (AT32F403Vx_HD) || \
+    defined (AT32F403Vx_XL) || defined (AT32F403Zx_HD) || \
+    defined (AT32F403Zx_XL)
+
+    #define AT32F403xx
+#endif
+
+#if defined (AT32F413Kx_MD) || defined (AT32F413Kx_HD) || \
+    defined (AT32F413Cx_MD) || defined (AT32F413Cx_HD) || \
+    defined (AT32F413Rx_MD) || defined (AT32F413Rx_HD) || \
+    defined (AT32FEBKCx_MD) || defined (TS32F401CBU7)
+
+    #define AT32F413xx
+#endif
+
+#if defined (AT32F415C8T7)  || defined (AT32F415CBT7)  || defined (AT32F415CCT7)  || \
+    defined (AT32F415CBU7)  || defined (AT32F415CCU7)  || defined (AT32F415R8T7)  || \
+    defined (AT32F415RBT7)  || defined (AT32F415RCT7)  || defined (AT32F415K8U7_4)|| \
+    defined (AT32F415KBU7_4)|| defined (AT32F415KCU7_4)|| defined (AT32F415R8T7_7)|| \
+    defined (AT32F415RBT7_7)|| defined (AT32F415RCT7_7)
+
+    #define AT32F415xx
+#endif
+
+#if defined (AT32F407RGT7)  || defined (AT32F407VGT7)  || defined (AT32F407RCT7)  || \
+    defined (AT32F407VCT7)  || defined (AT32F407VET7)  || defined (AT32F407RET7)
+
+    #define AT32F407xx
+#endif
+
+#if defined (AT32F403AVCT7) || defined (AT32F403ARCT7) || defined (AT32F403ACCT7) || \
+    defined (AT32F403ACCU7) || defined (AT32F403AVGT7) || defined (AT32F403ACGT7) || \
+    defined (AT32F403ARGT7) || defined (AT32F403ACGU7) || defined (AT32F403AVET7) || \
+    defined (AT32F403ACET7) || defined (AT32F403ARET7) || defined (AT32F403ACEU7)
+
+    #define AT32F403Axx
+#endif
+
+#if !defined  USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  #ifdef _RTE_
+    #include "RTE_Components.h"
+    #ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK
+      #define USE_STDPERIPH_DRIVER
+    #endif
+  #endif
+#endif
+
+#if !defined  LIBRARY_VERSION
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+/*#define LIBRARY_VERSION*/
+#endif
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application
+
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */
+#if !defined  HSE_VALUE
+#define HSE_VALUE               ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+   Timeout value
+   */
+#define HSE_STARTUP_TIMEOUT     ((uint16_t)0x3000) /*!< Time out for HSE start up */
+
+#define HSI_VALUE               ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+
+/**
+ * @brief at32f4xx Standard Peripheral Library version number
+   */
+#define __AT32F4xx_LIBRARY_VERSION_MAIN     (0x01) /*!< [31:24] main version */
+#define __AT32F4xx_LIBRARY_VERSION_MIDDLE   (0x00) /*!< [23:16] middle version */
+#define __AT32F4xx_LIBRARY_VERSION_MINOR    (0x01) /*!< [15:8]  minor version */
+#define __AT32F4xx_LIBRARY_VERSION_RC       (0x00) /*!< [7:0]  release candidate */
+#define __AT32F4xx_LIBRARY_VERSION          ( (__AT32F4xx_LIBRARY_VERSION_MAIN << 24)\
+                                             |(__AT32F4xx_LIBRARY_VERSION_MIDDLE << 16)\
+                                             |(__AT32F4xx_LIBRARY_VERSION_MINOR << 8)\
+                                             |(__AT32F4xx_LIBRARY_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             0     /*!< AT32 devices do not provide an MPU           */
+#define __NVIC_PRIO_BITS          4     /*!< AT32 uses 4 Bits for the Priority Levels     */
+#define __Vendor_SysTickConfig    0     /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             1U    /*!< FPU present                                  */
+
+/**
+ * @brief at32f4xx Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum IRQn
+{
+    /******  Cortex-M4 Processor Exceptions Numbers ***************************************************/
+    Reset_IRQn                  = -15,    /*!< 1 Reset Vector, invoked on Power up and warm reset   */
+    NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
+    HardFault_IRQn              = -13,    /*!< 3 Hard Fault, all classes of Fault                   */
+    MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt              */
+    BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                      */
+    UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                    */
+    SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                       */
+    DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                 */
+    PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                       */
+    SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                   */
+
+    /******  AT32 specific Interrupt Numbers *********************************************************/
+    WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */
+    PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */
+#ifdef AT32F415xx
+    TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line*/
+    ERTC_WKUP_IRQn              = 3,      /*!< ERTC Wakeup interrupt through the EXTI line          */
+#else
+    TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */
+    RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */
+#endif
+    FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */
+    RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */
+    EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */
+    EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */
+    EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */
+    EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */
+    EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */
+    DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */
+    DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */
+    DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */
+    DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */
+    DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */
+    DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */
+    DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */
+
+#ifdef AT32F403Cx_MD
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    TMR8_BRK_TMR12_IRQn         = 43,     /*!< TMR8 Break Interrupt                                 */
+    TMR8_OV_TMR13_IRQn          = 44,     /*!< TMR8 Update Interrupt                                */
+    TMR8_TRG_HALL_TMR14_IRQn    = 45,     /*!< TMR8 Trigger and Commutation Interrupt               */
+    TMR8_CC_IRQn                = 46,     /*!< TMR8 Capture Compare Interrupt                       */
+    ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+    TMR6_GLOBAL_IRQn            = 54,     /*!< TMR6 global Interrupt                                */
+    TMR7_GLOBAL_IRQn            = 55,     /*!< TMR7 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    SDIO2_IRQn                  = 60,     /*!< SDIO2 global Interrupt                               */
+    I2C3_EV_IRQn                = 61,     /*!< I2C3 event interrupt                                 */
+    I2C3_ER_IRQn                = 62,     /*!< I2C3 error interrupt                                 */
+#endif /* AT32F403Cx_MD */
+
+#ifdef AT32F403Cx_HD
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    TMR8_BRK_TMR12_IRQn         = 43,     /*!< TMR8 Break Interrupt                                 */
+    TMR8_OV_TMR13_IRQn          = 44,     /*!< TMR8 Update Interrupt                                */
+    TMR8_TRG_HALL_TMR14_IRQn    = 45,     /*!< TMR8 Trigger and Commutation Interrupt               */
+    TMR8_CC_IRQn                = 46,     /*!< TMR8 Capture Compare Interrupt                       */
+    ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+    TMR6_GLOBAL_IRQn            = 54,     /*!< TMR6 global Interrupt                                */
+    TMR7_GLOBAL_IRQn            = 55,     /*!< TMR7 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    SDIO2_IRQn                  = 60,     /*!< SDIO2 global Interrupt                               */
+    I2C3_EV_IRQn                = 61,     /*!< I2C3 event interrupt                                 */
+    I2C3_ER_IRQn                = 62,     /*!< I2C3 error interrupt                                 */
+#endif /* AT32F403Cx_HD */
+
+#ifdef AT32F403Cx_XL
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    TMR8_BRK_TMR12_IRQn         = 43,     /*!< TMR8 Break Interrupt                                 */
+    TMR8_OV_TMR13_IRQn          = 44,     /*!< TMR8 Update Interrupt                                */
+    TMR8_TRG_HALL_TMR14_IRQn    = 45,     /*!< TMR8 Trigger and Commutation Interrupt               */
+    TMR8_CC_IRQn                = 46,     /*!< TMR8 Capture Compare Interrupt                       */
+    ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+    TMR6_GLOBAL_IRQn            = 54,     /*!< TMR6 global Interrupt                                */
+    TMR7_GLOBAL_IRQn            = 55,     /*!< TMR7 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    SDIO2_IRQn                  = 60,     /*!< SDIO2 global Interrupt                               */
+    I2C3_EV_IRQn                = 61,     /*!< I2C3 event interrupt                                 */
+    I2C3_ER_IRQn                = 62,     /*!< I2C3 error interrupt                                 */
+#endif /* AT32F403Cx_XL */
+
+#ifdef AT32F403Rx_HD
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    TMR8_BRK_TMR12_IRQn         = 43,     /*!< TMR8 Break Interrupt                                 */
+    TMR8_OV_TMR13_IRQn          = 44,     /*!< TMR8 Update Interrupt                                */
+    TMR8_TRG_HALL_TMR14_IRQn    = 45,     /*!< TMR8 Trigger and Commutation Interrupt               */
+    TMR8_CC_IRQn                = 46,     /*!< TMR8 Capture Compare Interrupt                       */
+    ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+    SDIO1_IRQn                  = 49,     /*!< SDIO global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+    UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+    UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+    TMR6_GLOBAL_IRQn            = 54,     /*!< TMR6 global Interrupt                                */
+    TMR7_GLOBAL_IRQn            = 55,     /*!< TMR7 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    SDIO2_IRQn                  = 60,     /*!< SDIO2 global Interrupt                               */
+    I2C3_EV_IRQn                = 61,     /*!< I2C3 event interrupt                                 */
+    I2C3_ER_IRQn                = 62,     /*!< I2C3 error interrupt                                 */
+#endif /* AT32F403Rx_HD */
+
+#ifdef AT32F403Rx_XL
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    TMR8_BRK_TMR12_IRQn         = 43,     /*!< TMR8 Break Interrupt                                 */
+    TMR8_OV_TMR13_IRQn          = 44,     /*!< TMR8 Update Interrupt                                */
+    TMR8_TRG_HALL_TMR14_IRQn    = 45,     /*!< TMR8 Trigger and Commutation Interrupt               */
+    TMR8_CC_IRQn                = 46,     /*!< TMR8 Capture Compare Interrupt                       */
+    ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+    SDIO1_IRQn                  = 49,     /*!< SDIO global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+    UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+    UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+    TMR6_GLOBAL_IRQn            = 54,     /*!< TMR6 global Interrupt                                */
+    TMR7_GLOBAL_IRQn            = 55,     /*!< TMR7 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    SDIO2_IRQn                  = 60,     /*!< SDIO2 global Interrupt                               */
+    I2C3_EV_IRQn                = 61,     /*!< I2C3 event interrupt                                 */
+    I2C3_ER_IRQn                = 62,     /*!< I2C3 error interrupt                                 */
+#endif /* AT32F403Rx_XL */
+
+#ifdef AT32F403Vx_HD
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    TMR8_BRK_TMR12_IRQn         = 43,     /*!< TMR8 Break Interrupt                                 */
+    TMR8_OV_TMR13_IRQn          = 44,     /*!< TMR8 Update Interrupt                                */
+    TMR8_TRG_HALL_TMR14_IRQn    = 45,     /*!< TMR8 Trigger and Commutation Interrupt               */
+    TMR8_CC_IRQn                = 46,     /*!< TMR8 Capture Compare Interrupt                       */
+    ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+    XMC_IRQn                    = 48,     /*!< XMC global Interrupt                                 */
+    SDIO1_IRQn                  = 49,     /*!< SDIO global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+    UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+    UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+    TMR6_GLOBAL_IRQn            = 54,     /*!< TMR6 global Interrupt                                */
+    TMR7_GLOBAL_IRQn            = 55,     /*!< TMR7 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    SDIO2_IRQn                  = 60,     /*!< SDIO2 global Interrupt                               */
+    I2C3_EV_IRQn                = 61,     /*!< I2C3 event interrupt                                 */
+    I2C3_ER_IRQn                = 62,     /*!< I2C3 error interrupt                                 */
+    SPI4_IRQn                   = 63,     /*!< SPI4 global Interrupt                                */
+#endif /* AT32F403Vx_HD */
+
+#ifdef AT32F403Vx_XL
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    TMR8_BRK_TMR12_IRQn         = 43,     /*!< TMR8 Break Interrupt                                 */
+    TMR8_OV_TMR13_IRQn          = 44,     /*!< TMR8 Update Interrupt                                */
+    TMR8_TRG_HALL_TMR14_IRQn    = 45,     /*!< TMR8 Trigger and Commutation Interrupt               */
+    TMR8_CC_IRQn                = 46,     /*!< TMR8 Capture Compare Interrupt                       */
+    ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+    XMC_IRQn                    = 48,     /*!< XMC global Interrupt                                 */
+    SDIO1_IRQn                  = 49,     /*!< SDIO global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+    UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+    UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+    TMR6_GLOBAL_IRQn            = 54,     /*!< TMR6 global Interrupt                                */
+    TMR7_GLOBAL_IRQn            = 55,     /*!< TMR7 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    SDIO2_IRQn                  = 60,     /*!< SDIO2 global Interrupt                               */
+    I2C3_EV_IRQn                = 61,     /*!< I2C3 event interrupt                                 */
+    I2C3_ER_IRQn                = 62,     /*!< I2C3 error interrupt                                 */
+    SPI4_IRQn                   = 63,     /*!< SPI4 global Interrupt                                */
+#endif /* AT32F403Vx_XL */
+
+#ifdef AT32F403Zx_HD
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    TMR8_BRK_TMR12_IRQn         = 43,     /*!< TMR8 Break Interrupt                                 */
+    TMR8_OV_TMR13_IRQn          = 44,     /*!< TMR8 Update Interrupt                                */
+    TMR8_TRG_HALL_TMR14_IRQn    = 45,     /*!< TMR8 Trigger and Commutation Interrupt               */
+    TMR8_CC_IRQn                = 46,     /*!< TMR8 Capture Compare Interrupt                       */
+    ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+    XMC_IRQn                    = 48,     /*!< XMC global Interrupt                                 */
+    SDIO1_IRQn                  = 49,     /*!< SDIO global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+    UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+    UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+    TMR6_GLOBAL_IRQn            = 54,     /*!< TMR6 global Interrupt                                */
+    TMR7_GLOBAL_IRQn            = 55,     /*!< TMR7 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    SDIO2_IRQn                  = 60,     /*!< SDIO2 global Interrupt                               */
+    I2C3_EV_IRQn                = 61,     /*!< I2C3 event interrupt                                 */
+    I2C3_ER_IRQn                = 62,     /*!< I2C3 error interrupt                                 */
+    SPI4_IRQn                   = 63,     /*!< SPI4 global Interrupt                                */
+    TMR15_BRK_IRQn              = 64,     /*!< TMR15 Break interrupt                                */
+    TMR15_OV_IRQn               = 65,     /*!< TMR15 Update interrupt                               */
+    TMR15_TRG_HALL_IRQn         = 66,     /*!< TMR15 Trigger and Commutation Interrupt              */
+    TMR15_CC_IRQn               = 67      /*!< TMR15 Capture Compare Interrupt                      */
+#endif /* AT32F403Zx_HD */
+
+#ifdef AT32F403Zx_XL
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    TMR8_BRK_TMR12_IRQn         = 43,     /*!< TMR8 Break Interrupt                                 */
+    TMR8_OV_TMR13_IRQn          = 44,     /*!< TMR8 Update Interrupt                                */
+    TMR8_TRG_HALL_TMR14_IRQn    = 45,     /*!< TMR8 Trigger and Commutation Interrupt               */
+    TMR8_CC_IRQn                = 46,     /*!< TMR8 Capture Compare Interrupt                       */
+    ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+    XMC_IRQn                    = 48,     /*!< XMC global Interrupt                                 */
+    SDIO1_IRQn                  = 49,     /*!< SDIO global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+    UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+    UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+    TMR6_GLOBAL_IRQn            = 54,     /*!< TMR6 global Interrupt                                */
+    TMR7_GLOBAL_IRQn            = 55,     /*!< TMR7 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    SDIO2_IRQn                  = 60,     /*!< SDIO2 global Interrupt                               */
+    I2C3_EV_IRQn                = 61,     /*!< I2C3 event interrupt                                 */
+    I2C3_ER_IRQn                = 62,     /*!< I2C3 error interrupt                                 */
+    SPI4_IRQn                   = 63,     /*!< SPI4 global Interrupt                                */
+    TMR15_BRK_IRQn              = 64,     /*!< TMR15 Break interrupt                                */
+    TMR15_OV_IRQn               = 65,     /*!< TMR15 Update interrupt                               */
+    TMR15_TRG_HALL_IRQn         = 66,     /*!< TMR15 Trigger and Commutation Interrupt              */
+    TMR15_CC_IRQn               = 67      /*!< TMR15 Capture Compare Interrupt                      */
+#endif /* AT32F403Zx_XL */
+
+#if defined (AT32F413Kx_MD) || defined (AT32F413Kx_HD)
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    ACC_IRQn                    = 72,     /*!< ACC interrupt                                        */
+    USB_HP_IRQn                 = 73,     /*!< USB Device High Priority Interrupts                  */
+    USB_LP_IRQn                 = 74,     /*!< USB Device Low Priority Interrupts                   */
+    DMA2_Channel6_7_IRQn        = 75,     /*!< DMA2 Channel6 and Channel7 global interrupts         */
+#endif /* AT32F413Kx_MD || AT32F413Kx_HD */
+
+#if defined (AT32F413Cx_MD) || defined (TS32F401CBU7)
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    CAN2_TX_IRQn                = 68,     /*!< CAN2 TX Interrupt                                    */
+    CAN2_RX0_IRQn               = 69,     /*!< CAN2 RX0 Interrupt                                   */
+    CAN2_RX1_IRQn               = 70,     /*!< CAN2 RX1 Interrupt                                   */
+    CAN2_SCE_IRQn               = 71,     /*!< CAN2 SCE Interrupt                                   */
+    ACC_IRQn                    = 72,     /*!< ACC interrupt                                        */
+    USB_HP_IRQn                 = 73,     /*!< USB Device High Priority Interrupts                  */
+    USB_LP_IRQn                 = 74,     /*!< USB Device Low Priority Interrupts                   */
+    DMA2_Channel6_7_IRQn        = 75,     /*!< DMA2 Channel6 and Channel7 global interrupts         */
+#endif /* AT32F413Cx_MD || TS32F401CBU7 */
+
+#if defined (AT32F413Cx_HD)
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    TMR8_BRK_TMR12_IRQn         = 43,     /*!< TMR8 Break Interrupt                                 */
+    TMR8_OV_TMR13_IRQn          = 44,     /*!< TMR8 Update Interrupt                                */
+    TMR8_TRG_HALL_TMR14_IRQn    = 45,     /*!< TMR8 Trigger and Commutation Interrupt               */
+    TMR8_CC_IRQn                = 46,     /*!< TMR8 Capture Compare Interrupt                       */
+    SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    CAN2_TX_IRQn                = 68,     /*!< CAN2 TX Interrupt                                    */
+    CAN2_RX0_IRQn               = 69,     /*!< CAN2 RX0 Interrupt                                   */
+    CAN2_RX1_IRQn               = 70,     /*!< CAN2 RX1 Interrupt                                   */
+    CAN2_SCE_IRQn               = 71,     /*!< CAN2 SCE Interrupt                                   */
+    ACC_IRQn                    = 72,     /*!< ACC interrupt                                        */
+    USB_HP_IRQn                 = 73,     /*!< USB Device High Priority Interrupts                  */
+    USB_LP_IRQn                 = 74,     /*!< USB Device Low Priority Interrupts                   */
+    DMA2_Channel6_7_IRQn        = 75,     /*!< DMA2 Channel6 and Channel7 global interrupts         */
+#endif /*AT32F413Cx_HD */
+
+#if defined (AT32F413Rx_MD)
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+    UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    CAN2_TX_IRQn                = 68,     /*!< CAN2 TX Interrupt                                    */
+    CAN2_RX0_IRQn               = 69,     /*!< CAN2 RX0 Interrupt                                   */
+    CAN2_RX1_IRQn               = 70,     /*!< CAN2 RX1 Interrupt                                   */
+    CAN2_SCE_IRQn               = 71,     /*!< CAN2 SCE Interrupt                                   */
+    ACC_IRQn                    = 72,     /*!< ACC interrupt                                        */
+    USB_HP_IRQn                 = 73,     /*!< USB Device High Priority Interrupts                  */
+    USB_LP_IRQn                 = 74,     /*!< USB Device Low Priority Interrupts                   */
+    DMA2_Channel6_7_IRQn        = 75,     /*!< DMA2 Channel6 and Channel7 global interrupts         */
+#endif /* AT32F413Rx_MD*/
+
+#if defined (AT32F413Rx_HD)
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    TMR8_BRK_TMR12_IRQn         = 43,     /*!< TMR8 Break Interrupt                                 */
+    TMR8_OV_TMR13_IRQn          = 44,     /*!< TMR8 Update Interrupt                                */
+    TMR8_TRG_HALL_TMR14_IRQn    = 45,     /*!< TMR8 Trigger and Commutation Interrupt               */
+    TMR8_CC_IRQn                = 46,     /*!< TMR8 Capture Compare Interrupt                       */
+    SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+    UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    CAN2_TX_IRQn                = 68,     /*!< CAN2 TX Interrupt                                    */
+    CAN2_RX0_IRQn               = 69,     /*!< CAN2 RX0 Interrupt                                   */
+    CAN2_RX1_IRQn               = 70,     /*!< CAN2 RX1 Interrupt                                   */
+    CAN2_SCE_IRQn               = 71,     /*!< CAN2 SCE Interrupt                                   */
+    ACC_IRQn                    = 72,     /*!< ACC interrupt                                        */
+    USB_HP_IRQn                 = 73,     /*!< USB Device High Priority Interrupts                  */
+    USB_LP_IRQn                 = 74,     /*!< USB Device Low Priority Interrupts                   */
+    DMA2_Channel6_7_IRQn        = 75,     /*!< DMA2 Channel6 and Channel7 global interrupts         */
+#endif /*AT32F413Rx_HD */
+
+#if defined (AT32FEBKCx_MD)
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    USB_HP_IRQn                 = 73,     /*!< USB Device High Priority Interrupts                  */
+    USB_LP_IRQn                 = 74,     /*!< USB Device Low Priority Interrupts                   */
+    DMA2_Channel6_7_IRQn        = 75,     /*!< DMA2 Channel6 and Channel7 global interrupts         */
+#endif /* AT32FEBKCx_MD*/
+
+#if defined (AT32F415K8U7_4) || defined (AT32F415KBU7_4) || defined (AT32F415KCU7_4)
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupts                                   */
+    CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupts                                  */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    ERTCAlarm_IRQn              = 41,     /*!< ERTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    USBOTG_IRQn                 = 67,     /*!< USBOTG interrupt                                     */
+    COMP1_IRQn                  = 70,     /*!< Compare1 Interrupts                                  */
+    COMP2_IRQn                  = 71,     /*!< Compare2 Interrupts                                  */
+    ACC_IRQn                    = 72,     /*!< ACC interrupt                                        */
+    DMA2_Channel6_7_IRQn        = 75,     /*!< DMA2 Channel6 and Channel7 global interrupts         */
+#endif /* AT32F415K8U7_4 || AT32F415KBU7_4 || AT32F415KCU7_4 */
+
+#if defined (AT32F415C8T7) || defined (AT32F415CBT7) || defined (AT32F415CCT7) ||\
+    defined (AT32F415CBU7) || defined (AT32F415CCU7)
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupts                                   */
+    CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupts                                  */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    ERTCAlarm_IRQn              = 41,     /*!< ERTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    USBOTG_IRQn                 = 67,     /*!< USBOTG interrupt                                     */
+    COMP1_IRQn                  = 70,     /*!< Compare1 Interrupts                                  */
+    COMP2_IRQn                  = 71,     /*!< Compare2 Interrupts                                  */
+    ACC_IRQn                    = 72,     /*!< ACC interrupt                                        */
+    DMA2_Channel6_7_IRQn        = 75,     /*!< DMA2 Channel6 and Channel7 global interrupts         */
+#endif /* AT32F415C8T7 || AT32F415CBT7 || AT32F415CCT7 || AT32F415CBU7 || AT32F415CCU7 */
+
+#if defined (AT32F415R8T7) || defined (AT32F415R8T7_7) || \
+    defined (AT32F415RBT7) || defined (AT32F415RBT7_7) || \
+    defined (AT32F415RCT7) || defined (AT32F415RCT7_7)
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupts                                   */
+    CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupts                                  */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_HALL_TMR11_IRQn    = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    ERTCAlarm_IRQn              = 41,     /*!< ERTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+    UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    USBOTG_IRQn                 = 67,     /*!< USBOTG interrupt                                     */
+    COMP1_IRQn                  = 70,     /*!< Compare1 Interrupts                                  */
+    COMP2_IRQn                  = 71,     /*!< Compare2 Interrupts                                  */
+    ACC_IRQn                    = 72,     /*!< ACC interrupt                                        */
+    DMA2_Channel6_7_IRQn        = 75,     /*!< DMA2 Channel6 and Channel7 global interrupts         */
+#endif /* AT32F415R8T7 || AT32F415R8T7_7 || AT32F415RBT7 || AT32F415RBT7_7 || AT32F415RCT7 || AT32F415RCT7_7 */
+
+#if defined (AT32F403AVCT7) || defined (AT32F403ARCT7) || \
+    defined (AT32F403AVET7) || defined (AT32F403ARET7) || \
+    defined (AT32F403AVGT7) || defined (AT32F403ARGT7)
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_COM_TMR11_IRQn     = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_I2S2EXT_IRQn           = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    TMR8_BRK_TMR12_IRQn         = 43,     /*!< TMR8 Break Interrupt                                 */
+    TMR8_OV_TMR13_IRQn          = 44,     /*!< TMR8 Update Interrupt                                */
+    TMR8_TRG_COM_TMR14_IRQn     = 45,     /*!< TMR8 Trigger and Commutation Interrupt               */
+    TMR8_CC_IRQn                = 46,     /*!< TMR8 Capture Compare Interrupt                       */
+    ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+    XMC_IRQn                    = 48,     /*!< XMC global Interrupt                                 */
+    SDIO1_IRQn                  = 49,     /*!< SDIO global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    SPI3_I2S3EXT_IRQn           = 51,     /*!< SPI3 global Interrupt                                */
+    UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+    UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+    TMR6_GLOBAL_IRQn            = 54,     /*!< TMR6 global Interrupt                                */
+    TMR7_GLOBAL_IRQn            = 55,     /*!< TMR7 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    SDIO2_IRQn                  = 60,     /*!< SDIO2 global Interrupt                               */
+    I2C3_EV_IRQn                = 61,     /*!< I2C3 event interrupt                                 */
+    I2C3_ER_IRQn                = 62,     /*!< I2C3 error interrupt                                 */
+    SPI4_IRQn                   = 63,     /*!< SPI4 global Interrupt                                */
+    CAN2_TX_IRQn                = 68,     /*!< CAN2 Tx interrupt                                    */
+    CAN2_RX0_IRQn               = 69,     /*!< CAN2 Rx0 interrupt                                   */
+    CAN2_RX1_IRQn               = 70,     /*!< CAN2 Rx1 Interrupt                                   */
+    CAN2_SCE_IRQn               = 71,     /*!< CAN2 SCE Interrupt                                   */
+    ACC_IRQn                    = 72,     /*!< ACC Interrupt                                        */
+    USB_HP_IRQn                 = 73,     /*!< USB HP Interrupt                                     */
+    USB_LP_IRQn                 = 74,     /*!< USB LP Interrupt                                     */
+    DMA2_Channel6_7_IRQn        = 75,     /*!< DMA2 Channel 6 and Channel 7 global Interrupt        */
+    USART6_IRQn                 = 76,     /*!< USART6 Interrupt                                     */
+    UART7_IRQn                  = 77,     /*!< UART7 Interrupt                                      */
+    UART8_IRQn                  = 78,     /*!< UART8 Interrupt                                      */
+#endif /* AT32F403AVCT7 || AT32F403ARCT7 || AT32F403AVGT7 || \
+          AT32F403ARGT7 || AT32F403AVET7 || AT32F403ARET7 */
+
+
+#if defined (AT32F403ACCT7) || defined (AT32F403ACCU7) || \
+    defined (AT32F403ACET7) || defined (AT32F403ACEU7) || \
+    defined (AT32F403ACGT7) || defined (AT32F403ACGU7)
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_COM_TMR11_IRQn     = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_I2S2EXT_IRQn           = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    TMR8_BRK_TMR12_IRQn         = 43,     /*!< TMR8 Break Interrupt                                 */
+    TMR8_OV_TMR13_IRQn          = 44,     /*!< TMR8 Update Interrupt                                */
+    TMR8_TRG_COM_TMR14_IRQn     = 45,     /*!< TMR8 Trigger and Commutation Interrupt               */
+    TMR8_CC_IRQn                = 46,     /*!< TMR8 Capture Compare Interrupt                       */
+    ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    SPI3_I2S3EXT_IRQn           = 51,     /*!< SPI3 global Interrupt                                */
+    UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+    UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+    TMR6_GLOBAL_IRQn            = 54,     /*!< TMR6 global Interrupt                                */
+    TMR7_GLOBAL_IRQn            = 55,     /*!< TMR7 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    SDIO2_IRQn                  = 60,     /*!< SDIO2 global Interrupt                               */
+    I2C3_EV_IRQn                = 61,     /*!< I2C3 event interrupt                                 */
+    I2C3_ER_IRQn                = 62,     /*!< I2C3 error interrupt                                 */
+    SPI4_IRQn                   = 63,     /*!< SPI4 global Interrupt                                */
+    CAN2_TX_IRQn                = 68,     /*!< CAN2 Tx interrupt                                    */
+    CAN2_RX0_IRQn               = 69,     /*!< CAN2 Rx0 interrupt                                   */
+    CAN2_RX1_IRQn               = 70,     /*!< CAN2 Rx1 Interrupt                                   */
+    CAN2_SCE_IRQn               = 71,     /*!< CAN2 SCE Interrupt                                   */
+    ACC_IRQn                    = 72,     /*!< ACC Interrupt                                        */
+    USB_HP_IRQn                 = 73,     /*!< USB HP Interrupt                                     */
+    USB_LP_IRQn                 = 74,     /*!< USB LP Interrupt                                     */
+    DMA2_Channel6_7_IRQn        = 75,     /*!< DMA2 Channel 6 and Channel 7 global Interrupt        */
+    USART6_IRQn                 = 76,     /*!< USART6 Interrupt                                     */
+    UART7_IRQn                  = 77,     /*!< UART7 Interrupt                                      */
+#endif /* AT32F403ACCT7 || AT32F403ACCU7 || AT32F403ACGT7 || \
+          AT32F403ACGU7 || AT32F403ACEU7 || AT32F403ACET7 */
+
+#if defined (AT32F407VCT7) || defined (AT32F407RCT7) || \
+    defined (AT32F407VET7) || defined (AT32F407RET7) || \
+    defined (AT32F407VGT7) || defined (AT32F407RGT7)
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+    USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+    CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break Interrupt                                 */
+    TMR1_OV_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt                                */
+    TMR1_TRG_COM_TMR11_IRQn     = 26,     /*!< TMR1 Trigger and Commutation Interrupt               */
+    TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                       */
+    TMR2_GLOBAL_IRQn            = 28,     /*!< TMR2 global Interrupt                                */
+    TMR3_GLOBAL_IRQn            = 29,     /*!< TMR3 global Interrupt                                */
+    TMR4_GLOBAL_IRQn            = 30,     /*!< TMR4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_I2S2EXT_IRQn           = 36,     /*!< SPI2 global Interrupt                                */
+    USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+    USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+    USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    TMR8_BRK_TMR12_IRQn         = 43,     /*!< TMR8 Break Interrupt                                 */
+    TMR8_OV_TMR13_IRQn          = 44,     /*!< TMR8 Update Interrupt                                */
+    TMR8_TRG_COM_TMR14_IRQn     = 45,     /*!< TMR8 Trigger and Commutation Interrupt               */
+    TMR8_CC_IRQn                = 46,     /*!< TMR8 Capture Compare Interrupt                       */
+    ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+    XMC_IRQn                    = 48,     /*!< XMC global Interrupt                                 */
+    SDIO1_IRQn                  = 49,     /*!< SDIO global Interrupt                                */
+    TMR5_GLOBAL_IRQn            = 50,     /*!< TMR5 global Interrupt                                */
+    SPI3_I2S3EXT_IRQn           = 51,     /*!< SPI3 global Interrupt                                */
+    UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+    UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+    TMR6_GLOBAL_IRQn            = 54,     /*!< TMR6 global Interrupt                                */
+    TMR7_GLOBAL_IRQn            = 55,     /*!< TMR7 global Interrupt                                */
+    DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+    DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+    DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+    DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+    SDIO2_IRQn                  = 60,     /*!< SDIO2 global Interrupt                               */
+    I2C3_EV_IRQn                = 61,     /*!< I2C3 event interrupt                                 */
+    I2C3_ER_IRQn                = 62,     /*!< I2C3 error interrupt                                 */
+    SPI4_IRQn                   = 63,     /*!< SPI4 global Interrupt                                */
+    CAN2_TX_IRQn                = 68,     /*!< CAN2 Tx interrupt                                    */
+    CAN2_RX0_IRQn               = 69,     /*!< CAN2 Rx0 interrupt                                   */
+    CAN2_RX1_IRQn               = 70,     /*!< CAN2 Rx1 Interrupt                                   */
+    CAN2_SCE_IRQn               = 71,     /*!< CAN2 SCE Interrupt                                   */
+    ACC_IRQn                    = 72,     /*!< ACC Interrupt                                        */
+    USB_HP_IRQn                 = 73,     /*!< USB HP Interrupt                                     */
+    USB_LP_IRQn                 = 74,     /*!< USB LP Interrupt                                     */
+    DMA2_Channel6_7_IRQn        = 75,     /*!< DMA2 Channel 6 and Channel 7 global Interrupt        */
+    USART6_IRQn                 = 76,     /*!< USART6 Interrupt                                     */
+    UART7_IRQn                  = 77,     /*!< UART7 Interrupt                                      */
+    UART8_IRQn                  = 78,     /*!< UART8 Interrupt                                      */
+    ETH_IRQn                    = 79,     /*!< ETH Interrupt                                        */
+    ETH_WKUP_IRQn               = 80,     /*!< ETH Wakeup Interrupt                                 */
+#endif /* AT32F407VCT7 || AT32F407RCT7 || AT32F407VGT7 || \
+          AT32F407RGT7 || AT32F407RET7 || AT32F407VET7 */
+
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"
+#include "system_at32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */
+
+typedef int32_t  INT32;
+typedef int16_t  INT16;
+typedef int8_t   INT8;
+typedef uint32_t UINT32;
+typedef uint16_t UINT16;
+typedef uint8_t  UINT8;
+
+/** at32f4xx Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef int32_t  s32;
+typedef int16_t  s16;
+typedef int8_t   s8;
+
+typedef const int32_t sc32;  /*!< Read Only */
+typedef const int16_t sc16;  /*!< Read Only */
+typedef const int8_t  sc8;   /*!< Read Only */
+
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef __I int32_t vsc32;  /*!< Read Only */
+typedef __I int16_t vsc16;  /*!< Read Only */
+typedef __I int8_t  vsc8;   /*!< Read Only */
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef const uint32_t uc32;  /*!< Read Only */
+typedef const uint16_t uc16;  /*!< Read Only */
+typedef const uint8_t  uc8;   /*!< Read Only */
+
+typedef __IO uint32_t vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef __I uint32_t vuc32;  /*!< Read Only */
+typedef __I uint16_t vuc16;  /*!< Read Only */
+typedef __I uint8_t  vuc8;   /*!< Read Only */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/** at32f4xx Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSEStartUp_TimeOut   HSE_STARTUP_TIMEOUT
+#define HSE_Value            HSE_VALUE
+#define HSI_Value            HSI_VALUE
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief HSI Auto Clock Calibration
+  */
+typedef struct
+{
+  __IO uint32_t STS;
+  __IO uint32_t CTRL1;
+  __IO uint32_t CTRL2;
+  __IO uint32_t C1;
+  __IO uint32_t C2;
+  __IO uint32_t C3;
+} ACC_Type;
+
+/**
+  * @brief Analog to Digital Converter
+  */
+typedef struct
+{
+    __IO uint32_t STS;
+    __IO uint32_t CTRL1;
+    __IO uint32_t CTRL2;
+    __IO uint32_t SMPT1;
+    __IO uint32_t SMPT2;
+    __IO uint32_t JOFS1;
+    __IO uint32_t JOFS2;
+    __IO uint32_t JOFS3;
+    __IO uint32_t JOFS4;
+    __IO uint32_t WHTR;
+    __IO uint32_t WLTR;
+    __IO uint32_t RSQ1;
+    __IO uint32_t RSQ2;
+    __IO uint32_t RSQ3;
+    __IO uint32_t JSQ;
+    __IO uint32_t JDOR1;
+    __IO uint32_t JDOR2;
+    __IO uint32_t JDOR3;
+    __IO uint32_t JDOR4;
+    __IO uint32_t RDOR;
+} ADC_Type;
+
+/**
+  * @brief Backup Registers
+  */
+#if !defined (AT32F415xx)
+typedef struct
+{
+    uint32_t  RESERVED0;
+    __IO uint16_t DT1;
+    uint16_t  RESERVED1;
+    __IO uint16_t DT2;
+    uint16_t  RESERVED2;
+    __IO uint16_t DT3;
+    uint16_t  RESERVED3;
+    __IO uint16_t DT4;
+    uint16_t  RESERVED4;
+    __IO uint16_t DT5;
+    uint16_t  RESERVED5;
+    __IO uint16_t DT6;
+    uint16_t  RESERVED6;
+    __IO uint16_t DT7;
+    uint16_t  RESERVED7;
+    __IO uint16_t DT8;
+    uint16_t  RESERVED8;
+    __IO uint16_t DT9;
+    uint16_t  RESERVED9;
+    __IO uint16_t DT10;
+    uint16_t  RESERVED10;
+    __IO uint16_t RTCCAL;
+    uint16_t  RESERVED11;
+    __IO uint16_t CTRL;
+    uint16_t  RESERVED12;
+    __IO uint16_t CTRLSTS;
+    uint16_t  RESERVED13[5];
+    __IO uint16_t DT11;
+    uint16_t  RESERVED14;
+    __IO uint16_t DT12;
+    uint16_t  RESERVED15;
+    __IO uint16_t DT13;
+    uint16_t  RESERVED16;
+    __IO uint16_t DT14;
+    uint16_t  RESERVED17;
+    __IO uint16_t DT15;
+    uint16_t  RESERVED18;
+    __IO uint16_t DT16;
+    uint16_t  RESERVED19;
+    __IO uint16_t DT17;
+    uint16_t  RESERVED20;
+    __IO uint16_t DT18;
+    uint16_t  RESERVED21;
+    __IO uint16_t DT19;
+    uint16_t  RESERVED22;
+    __IO uint16_t DT20;
+    uint16_t  RESERVED23;
+    __IO uint16_t DT21;
+    uint16_t  RESERVED24;
+    __IO uint16_t DT22;
+    uint16_t  RESERVED25;
+    __IO uint16_t DT23;
+    uint16_t  RESERVED26;
+    __IO uint16_t DT24;
+    uint16_t  RESERVED27;
+    __IO uint16_t DT25;
+    uint16_t  RESERVED28;
+    __IO uint16_t DT26;
+    uint16_t  RESERVED29;
+    __IO uint16_t DT27;
+    uint16_t  RESERVED30;
+    __IO uint16_t DT28;
+    uint16_t  RESERVED31;
+    __IO uint16_t DT29;
+    uint16_t  RESERVED32;
+    __IO uint16_t DT30;
+    uint16_t  RESERVED33;
+    __IO uint16_t DT31;
+    uint16_t  RESERVED34;
+    __IO uint16_t DT32;
+    uint16_t  RESERVED35;
+    __IO uint16_t DT33;
+    uint16_t  RESERVED36;
+    __IO uint16_t DT34;
+    uint16_t  RESERVED37;
+    __IO uint16_t DT35;
+    uint16_t  RESERVED38;
+    __IO uint16_t DT36;
+    uint16_t  RESERVED39;
+    __IO uint16_t DT37;
+    uint16_t  RESERVED40;
+    __IO uint16_t DT38;
+    uint16_t  RESERVED41;
+    __IO uint16_t DT39;
+    uint16_t  RESERVED42;
+    __IO uint16_t DT40;
+    uint16_t  RESERVED43;
+    __IO uint16_t DT41;
+    uint16_t  RESERVED44;
+    __IO uint16_t DT42;
+    uint16_t  RESERVED45;
+} BKP_Type;
+#endif
+
+/**
+  * @brief Controller Area Network TxMailBox
+  */
+typedef struct
+{
+    __IO uint32_t TMI;
+    __IO uint32_t TDT;
+    __IO uint32_t TDL;
+    __IO uint32_t TDH;
+} CAN_TxMailBox_Type;
+
+/**
+  * @brief Controller Area Network FIFOMailBox
+  */
+typedef struct
+{
+    __IO uint32_t RFI;
+    __IO uint32_t RDT;
+    __IO uint32_t RDL;
+    __IO uint32_t RDH;
+} CAN_FIFOMailBox_Type;
+
+/**
+  * @brief Controller Area Network FilterRegister
+  */
+typedef struct
+{
+    __IO uint32_t FBR1;
+    __IO uint32_t FBR2;
+} CAN_FilterRegister_Type;
+
+/**
+  * @brief Controller Area Network
+  */
+typedef struct
+{
+    __IO uint32_t MCTRL;
+    __IO uint32_t MSTS;
+    __IO uint32_t TSTS;
+    __IO uint32_t RF0;
+    __IO uint32_t RF1;
+    __IO uint32_t INTEN;
+    __IO uint32_t ESTS;
+    __IO uint32_t BTMG;
+    uint32_t  RESERVED0[88];
+    CAN_TxMailBox_Type TxMailBox[3];
+    CAN_FIFOMailBox_Type FIFOMailBox[2];
+    uint32_t  RESERVED1[12];
+    __IO uint32_t FM;
+    __IO uint32_t FM1;
+    uint32_t  RESERVED2;
+    __IO uint32_t FS1;
+    uint32_t  RESERVED3;
+    __IO uint32_t FFA1;
+    uint32_t  RESERVED4;
+    __IO uint32_t FA1;
+    uint32_t  RESERVED5[8];
+    CAN_FilterRegister_Type FilterRegister[14];
+} CAN_Type;
+
+/**
+  * @brief Comparator 
+  */
+typedef struct
+{
+  __IO uint32_t CTRLSTS1;     /*!< COMP comparator control and status register, Address offset: 0x1C */
+  __IO uint32_t CTRLSTS2;
+  __IO uint32_t G_FILTER_EN;
+  __IO uint32_t HIGH_PULSE;
+  __IO uint32_t LOW_PULSE;    
+} COMP_Type;
+
+/**
+  * @brief CRC calculation unit
+  */
+typedef struct
+{
+    __IO uint32_t DT;
+    __IO uint8_t  IDT;
+    uint8_t   RESERVED0;
+    uint16_t  RESERVED1;
+    __IO uint32_t CTRL;
+} CRC_Type;
+
+/**
+  * @brief Digital to Analog Converter
+  */
+typedef struct
+{
+    __IO uint32_t CTRL;
+    __IO uint32_t SWTRG;
+    __IO uint32_t HDR12R1;
+    __IO uint32_t HDR12L1;
+    __IO uint32_t HDR8R1;
+    __IO uint32_t HDR12R2;
+    __IO uint32_t HDR12L2;
+    __IO uint32_t HDR8R2;
+    __IO uint32_t HDR12RD;
+    __IO uint32_t HDR12LD;
+    __IO uint32_t HDR8RD;
+    __IO uint32_t ODT1;
+    __IO uint32_t ODT2;
+} DAC_Type;
+
+/**
+  * @brief MCU Debug
+  */
+typedef struct
+{
+    __IO uint32_t IDCR;
+    __IO uint32_t CTRL;
+} MCUDBG_Type;
+
+/**
+  * @brief DMA Controller
+  */
+typedef struct
+{
+    __IO uint32_t CHCTRL;
+    __IO uint32_t TCNT;
+    __IO uint32_t CPBA;
+    __IO uint32_t CMBA;
+} DMA_Channel_Type;
+
+typedef struct
+{
+    __IO uint32_t ISTS;
+    __IO uint32_t ICLR;
+    uint32_t  RESERVED[38];
+    __IO uint32_t DMA_SRC_SEL0;
+    __IO uint32_t DMA_SRC_SEL1;	
+} DMA_Type;
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+typedef struct
+{
+    __IO uint32_t INTEN;
+    __IO uint32_t EVTEN;
+    __IO uint32_t RTRSEL;
+    __IO uint32_t FTRSEL;
+    __IO uint32_t SWIE;
+    __IO uint32_t PND;
+} EXTI_Type;
+
+/**
+  * @brief FLASH Registers
+  */
+typedef struct
+{
+    __IO uint32_t ACR;
+    __IO uint32_t FCKEY;
+    __IO uint32_t OPTKEYR;
+    __IO uint32_t STS;
+    __IO uint32_t CTRL;
+    __IO uint32_t ADDR;
+    uint32_t RESERVED0;
+    __IO uint32_t UOB;
+    __IO uint32_t WRPRT;  
+    uint32_t RESERVED1[8];
+    __IO uint32_t FCKEY2;
+    uint32_t RESERVED2;
+    __IO uint32_t STS2;
+    __IO uint32_t CTRL2;
+    __IO uint32_t ADDR2;
+    uint32_t RESERVED3[7];
+#if defined (AT32F415xx)
+    __IO uint32_t SLIB_CDR0;
+    __IO uint32_t SLIB_CDR1;
+    __IO uint32_t SLIB_PSW;
+    __IO uint32_t SLIB_PSW_STS;
+    __IO uint32_t CRC_AR;
+    __IO uint32_t CRC_CR;
+    __IO uint32_t CRC_OUTR;
+    uint32_t RESERVED4[3];
+#else
+    uint32_t RESERVED5[4];
+    __IO uint32_t FCKEY3;
+    __IO uint32_t B3SEL;
+    __IO uint32_t STS3;
+    __IO uint32_t CTRL3;
+    __IO uint32_t ADDR3;
+    __IO uint32_t DA;
+#endif
+    uint32_t RESERVED6[12];
+#if defined (AT32F415xx)
+    uint32_t RESERVED7[6];
+#else
+    __IO uint32_t SLIB_CDR0;
+    __IO uint32_t SLIB_CDR1;
+    __IO uint32_t SLIB_PSW;
+    __IO uint32_t SLIB_PSW_STS;
+    __IO uint32_t SLIB_SET_PSW;
+    __IO uint32_t SLIB_SET_RANGE;
+#endif
+    uint32_t RESERVED8[3];
+#if defined (AT32F415xx)
+    uint32_t RESERVED9[3];
+#else
+    __IO uint32_t SLIB_KEYR;
+    __IO uint32_t CRC_DR;
+    __IO uint32_t CRC_OUTR;
+#endif
+#if defined (AT32F415xx)
+    uint32_t RESERVED10[25];
+    __IO uint32_t SLIB_SET_PSW;
+    __IO uint32_t SLIB_SET_RANGE;
+    __IO uint32_t SYS_SLIB_SET;
+    __IO uint32_t SYS_BOOT_DIS_SET;
+    __IO uint32_t SLIB_KEYR;
+#endif
+} FLASH_Type;
+
+/**
+  * @brief Option Bytes Registers
+  */
+typedef struct
+{
+    __IO uint16_t RDPRT;
+    __IO uint16_t USR;
+    __IO uint16_t DATA0;
+    __IO uint16_t DATA1;
+    __IO uint16_t WRPRT0;
+    __IO uint16_t WRPRT1;
+    __IO uint16_t WRPRT2;
+    __IO uint16_t WRPRT3;
+#if !defined (AT32F415xx)
+    __IO uint16_t EOPB0;
+    __IO uint16_t EOPB1;
+    __IO uint16_t HID[4];
+    __IO uint32_t Reserved;
+    __IO uint32_t BANK3SCRKEY[4];
+#endif
+} UOB_Type;
+
+/**
+  * @brief Flexible Static Memory Controller
+  */
+typedef struct
+{
+    __IO uint32_t BK1CTRLR[8];
+} XMC_Bank1_Type;
+
+/**
+  * @brief Flexible Static Memory Controller Bank1E
+  */
+typedef struct
+{
+    __IO uint32_t BK1TMGWR[7];
+} XMC_Bank1Ext_Type;
+
+/**
+  * @brief Flexible Static Memory Controller Bank1H
+  */
+typedef struct
+{
+    __IO uint32_t BK1EXT[4];
+} XMC_Bank1Hide_Type;
+
+/**
+  * @brief Flexible Static Memory Controller Bank2
+  */
+typedef struct
+{
+    __IO uint32_t BK2CTRL;
+    __IO uint32_t BK2STS;
+    __IO uint32_t BK2TMGMEM;
+    __IO uint32_t BK2TMGATT;
+    uint32_t  RESERVED0;
+    __IO uint32_t BK2ECC;
+} XMC_Bank2_Type;
+
+/**
+  * @brief Flexible Static Memory Controller Bank3
+  */
+typedef struct
+{
+    __IO uint32_t BK3CTRL;
+    __IO uint32_t BK3STS;
+    __IO uint32_t BK3TMGMEM;
+    __IO uint32_t BK3TMGATT;
+    uint32_t  RESERVED0;
+    __IO uint32_t BK3ECC;
+} XMC_Bank3_Type;
+
+/**
+  * @brief Flexible Static Memory Controller Bank4
+  */
+typedef struct
+{
+    __IO uint32_t BK4CTRL;
+    __IO uint32_t BK4STS;
+    __IO uint32_t BK4TMGMEM;
+    __IO uint32_t BK4TMGATT;
+    __IO uint32_t BK4TMGIO;
+} XMC_Bank4_Type;
+
+/**
+  * @brief General Purpose I/O
+  */
+typedef struct
+{
+    __IO uint32_t CTRLL;
+    __IO uint32_t CTRLH;
+    __IO uint32_t IPTDT;
+    __IO uint32_t OPTDT;
+    __IO uint32_t BSRE;
+    __IO uint32_t BRE;
+    __IO uint32_t LOCK;
+#if defined (AT32F403Axx) || defined (AT32F407xx) 
+    uint32_t RESERVED0;
+    __IO uint32_t SRCTR;
+    uint32_t RESERVED1;	
+    uint32_t RESERVED2;	
+    uint32_t RESERVED3;	
+    uint32_t RESERVED4;	
+    uint32_t RESERVED5;	
+    uint32_t RESERVED6;	
+    __IO uint32_t HDRV;
+#endif
+} GPIO_Type;
+
+/**
+  * @brief Alternate Function I/O
+  */
+typedef struct
+{
+    __IO uint32_t EVCTRL;
+    __IO uint32_t MAP;
+    __IO uint32_t EXTIC[4];
+    uint32_t RESERVED0;
+    __IO uint32_t MAP2;
+#ifndef AT32F403xx
+    __IO uint32_t MAP3;
+    __IO uint32_t MAP4;
+    __IO uint32_t MAP5;
+    __IO uint32_t MAP6;
+    __IO uint32_t MAP7;
+#ifndef AT32F413xx
+    __IO uint32_t MAP8;
+#endif
+#endif
+} AFIO_Type;
+
+/**
+  * @brief Inter Integrated Circuit Interface
+  */
+typedef struct
+{
+    __IO uint16_t CTRL1;
+    uint16_t  RESERVED0;
+    __IO uint16_t CTRL2;
+    uint16_t  RESERVED1;
+    __IO uint16_t OADDR1;
+    uint16_t  RESERVED2;
+    __IO uint16_t OADDR2;
+    uint16_t  RESERVED3;
+    __IO uint16_t DT;
+    uint16_t  RESERVED4;
+    __IO uint16_t STS1;
+    uint16_t  RESERVED5;
+    __IO uint16_t STS2;
+    uint16_t  RESERVED6;
+    __IO uint16_t CLKCTRL;
+    uint16_t  RESERVED7;
+    __IO uint16_t TMRISE;
+    uint16_t  RESERVED8;
+} I2C_Type;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+typedef struct
+{
+    __IO uint32_t KEY;
+    __IO uint32_t PSC;
+    __IO uint32_t RLD;
+    __IO uint32_t STS;
+} IWDG_Type;
+
+/**
+  * @brief Power Control
+  */
+typedef struct
+{
+    __IO uint32_t CTRL;
+    __IO uint32_t CTRLSTS;
+} PWR_Type;
+
+/**
+  * @brief Reset and Clock Control
+  */
+typedef struct
+{
+    __IO uint32_t CTRL;
+    __IO uint32_t CFG;
+    __IO uint32_t CLKINT;
+    __IO uint32_t APB2RST;
+    __IO uint32_t APB1RST;
+    __IO uint32_t AHBEN;
+    __IO uint32_t APB2EN;
+    __IO uint32_t APB1EN;
+    __IO uint32_t BDC;
+    __IO uint32_t CTRLSTS;
+#if defined (AT32F415xx)
+    __IO uint32_t AHBRST;
+    __IO uint32_t PLL;
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+    __IO uint32_t AHBRST;
+    __IO uint32_t RESERVED;
+#else
+    __IO uint32_t RESERVED[2];
+#endif
+    __IO uint32_t MISC;
+#if defined (AT32F413xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+    __IO uint32_t RESERVED1[7];
+    __IO uint32_t TEST;
+    __IO uint32_t MISC2;
+    __IO uint32_t RESERVED2;
+    __IO uint32_t INTCTRL;
+#elif defined (AT32F415xx)
+    __IO uint32_t RESERVED1[8];
+    __IO uint32_t MISC2;
+#endif
+} RCC_Type;
+
+/**
+  * @brief Real-Time Clock
+  */
+#if defined (AT32F415xx)
+typedef struct
+{
+  __IO uint32_t TIME;     /*!< ERTC time register,                                        Address offset: 0x00 */
+  __IO uint32_t DATE;     /*!< ERTC date register,                                        Address offset: 0x04 */
+  __IO uint32_t CTRL;     /*!< ERTC control register,                                     Address offset: 0x08 */
+  __IO uint32_t ISTS;     /*!< ERTC initialization and status register,                   Address offset: 0x0C */
+  __IO uint32_t PSC;      /*!< ERTC prescaler register,                                   Address offset: 0x10 */
+  __IO uint32_t WATR;     /*!< ERTC wakeup timer register,                                Address offset: 0x14 */
+  __IO uint32_t CAL;      /*!< ERTC calibration register,                                 Address offset: 0x18 */
+  __IO uint32_t ALA;      /*!< ERTC alarm A register,                                     Address offset: 0x1C */
+  __IO uint32_t ALB;      /*!< ERTC alarm B register,                                     Address offset: 0x20 */
+  __IO uint32_t WPR;      /*!< ERTC write protection register,                            Address offset: 0x24 */
+  __IO uint32_t SBSR;     /*!< ERTC sub second register,                                  Address offset: 0x28 */
+  __IO uint32_t SFCTR;    /*!< ERTC shift control register,                               Address offset: 0x2C */
+  __IO uint32_t TSTM;     /*!< ERTC time stamp time register,                             Address offset: 0x30 */
+  __IO uint32_t TSDT;     /*!< ERTC time stamp date register,                             Address offset: 0x34 */
+  __IO uint32_t TSSBS;    /*!< ERTC time-stamp sub second register,                       Address offset: 0x38 */
+  __IO uint32_t CCR;      /*!< ERTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TPAF;     /*!< ERTC tamper and alternate function configuration register, Address offset: 0x40 */
+  __IO uint32_t ALASBS;   /*!< ERTC alarm A sub second register,                          Address offset: 0x44 */
+  __IO uint32_t ALBSBS;   /*!< ERTC alarm B sub second register,                          Address offset: 0x48 */
+  uint32_t RESERVED7;     /*!< Reserved, 0x4C                                                                 */
+  __IO uint32_t BKP0DT;   /*!< ERTC backup register 1,                                    Address offset: 0x50 */
+  __IO uint32_t BKP1DT;   /*!< ERTC backup register 1,                                    Address offset: 0x54 */
+  __IO uint32_t BKP2DT;   /*!< ERTC backup register 2,                                    Address offset: 0x58 */
+  __IO uint32_t BKP3DT;   /*!< ERTC backup register 3,                                    Address offset: 0x5C */
+  __IO uint32_t BKP4DT;   /*!< ERTC backup register 4,                                    Address offset: 0x60 */
+  __IO uint32_t BKP5DT;   /*!< ERTC backup register 5,                                    Address offset: 0x64 */
+  __IO uint32_t BKP6DT;   /*!< ERTC backup register 6,                                    Address offset: 0x68 */
+  __IO uint32_t BKP7DT;   /*!< ERTC backup register 7,                                    Address offset: 0x6C */
+  __IO uint32_t BKP8DT;   /*!< ERTC backup register 8,                                    Address offset: 0x70 */
+  __IO uint32_t BKP9DT;   /*!< ERTC backup register 9,                                    Address offset: 0x74 */
+  __IO uint32_t BKP10DT;  /*!< ERTC backup register 10,                                   Address offset: 0x78 */
+  __IO uint32_t BKP11DT;  /*!< ERTC backup register 11,                                   Address offset: 0x7C */
+  __IO uint32_t BKP12DT;  /*!< ERTC backup register 12,                                   Address offset: 0x80 */
+  __IO uint32_t BKP13DT;  /*!< ERTC backup register 13,                                   Address offset: 0x84 */
+  __IO uint32_t BKP14DT;  /*!< ERTC backup register 14,                                   Address offset: 0x88 */
+  __IO uint32_t BKP15DT;  /*!< ERTC backup register 15,                                   Address offset: 0x8C */
+  __IO uint32_t BKP16DT;  /*!< ERTC backup register 16,                                   Address offset: 0x90 */
+  __IO uint32_t BKP17DT;  /*!< ERTC backup register 17,                                   Address offset: 0x94 */
+  __IO uint32_t BKP18DT;  /*!< ERTC backup register 18,                                   Address offset: 0x98 */
+  __IO uint32_t BKP19DT;  /*!< ERTC backup register 19,                                   Address offset: 0x9C */
+} ERTC_Type;
+#else
+typedef struct
+{
+    __IO uint16_t CTRLH;
+    uint16_t  RESERVED0;
+    __IO uint16_t CTRLL;
+    uint16_t  RESERVED1;
+    __IO uint16_t DIVH;
+    uint16_t  RESERVED2;
+    __IO uint16_t DIVL;
+    uint16_t  RESERVED3;
+    __IO uint16_t DIVCNTH;
+    uint16_t  RESERVED4;
+    __IO uint16_t DIVCNTL;
+    uint16_t  RESERVED5;
+    __IO uint16_t CNTH;
+    uint16_t  RESERVED6;
+    __IO uint16_t CNTL;
+    uint16_t  RESERVED7;
+    __IO uint16_t ALAH;
+    uint16_t  RESERVED8;
+    __IO uint16_t ALAL;
+    uint16_t  RESERVED9;
+} RTC_Type;
+#endif
+/**
+  * @brief SD host Interface
+  */
+typedef struct
+{
+    __IO uint32_t POWER;
+    __IO uint32_t CLKCTRL;
+    __IO uint32_t ARG;
+    __IO uint32_t CMD;
+    __I uint32_t RSPCMD;
+    __I uint32_t RSP1;
+    __I uint32_t RSP2;
+    __I uint32_t RSP3;
+    __I uint32_t RSP4;
+    __IO uint32_t DTTMR;
+    __IO uint32_t DTLEN;
+    __IO uint32_t DTCTRL;
+    __I uint32_t DTCNTR;
+    __I uint32_t STS;
+    __IO uint32_t INTCLR;
+    __IO uint32_t INTEN;
+    uint32_t  RESERVED0[2];
+    __I uint32_t BUFCNTR;
+    uint32_t  RESERVED1[13];
+    __IO uint32_t BUF;
+} SDIO_Type;
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+typedef struct
+{
+    __IO uint16_t CTRL1;
+    uint16_t  RESERVED0;
+    __IO uint16_t CTRL2;
+    uint16_t  RESERVED1;
+    __IO uint16_t STS;
+    uint16_t  RESERVED2;
+    __IO uint16_t DT;
+    uint16_t  RESERVED3;
+    __IO uint16_t CPOLY;
+    uint16_t  RESERVED4;
+    __IO uint16_t RCRC;
+    uint16_t  RESERVED5;
+    __IO uint16_t TCRC;
+    uint16_t  RESERVED6;
+    __IO uint16_t I2SCTRL;
+    uint16_t  RESERVED7;
+    __IO uint16_t I2SCLKP;
+    uint16_t  RESERVED8;
+} SPI_Type;
+
+/**
+  * @brief TIMER
+  */
+typedef struct
+{
+    __IO uint16_t CTRL1;
+    uint16_t  RESERVED0;
+    __IO uint16_t CTRL2;
+    uint16_t  RESERVED1;
+    __IO uint16_t SMC;
+    uint16_t  RESERVED2;
+    __IO uint16_t DIE;
+    uint16_t  RESERVED3;
+    __IO uint16_t STS;
+    uint16_t  RESERVED4;
+    __IO uint16_t EVEG;
+    uint16_t  RESERVED5;
+    __IO uint16_t CCM1;
+    uint16_t  RESERVED6;
+    __IO uint16_t CCM2;
+    uint16_t  RESERVED7;
+    __IO uint16_t CCE;
+    uint16_t  RESERVED8;
+	__IO uint32_t CNT;
+    __IO uint16_t DIV;
+    uint16_t  RESERVED10;
+	__IO uint32_t AR;
+    __IO uint16_t RC;
+    uint16_t  RESERVED12;
+    __IO uint32_t CC1;
+    __IO uint32_t CC2;
+    __IO uint32_t CC3;
+    __IO uint32_t CC4;
+    __IO uint16_t BRKDT;
+    uint16_t  RESERVED17;
+    __IO uint16_t DMAC;
+    uint16_t  RESERVED18;
+    __IO uint16_t DMABA;
+    uint16_t  RESERVED19;
+} TMR_Type;
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+typedef struct
+{
+    __IO uint16_t STS;
+    uint16_t  RESERVED0;
+    __IO uint16_t DT;
+    uint16_t  RESERVED1;
+    __IO uint16_t BAUDR;
+    uint16_t  RESERVED2;
+    __IO uint16_t CTRL1;
+    uint16_t  RESERVED3;
+    __IO uint16_t CTRL2;
+    uint16_t  RESERVED4;
+    __IO uint16_t CTRL3;
+    uint16_t  RESERVED5;
+    __IO uint16_t GTP;
+    uint16_t  RESERVED6;
+} USART_Type;
+
+/**
+  * @brief Window WATCHDOG
+  */
+typedef struct
+{
+    __IO uint32_t CTRL;
+    __IO uint32_t CFG;
+    __IO uint32_t STS;
+} WWDG_Type;
+
+/** 
+  * @brief Ethernet MAC
+  */
+
+typedef struct
+{
+  __IO uint32_t MACCTRL;
+  __IO uint32_t MACFRMF;
+  __IO uint32_t MACHTH;
+  __IO uint32_t MACHTL;
+  __IO uint32_t MACMIIADDR;
+  __IO uint32_t MACMIIDT;
+  __IO uint32_t MACFCTRL;
+  __IO uint32_t MACVLT;             /*    8 */
+       uint32_t RESERVED0[2];
+  __IO uint32_t MACRWFF;             /*   11 */
+  __IO uint32_t MACPMTCTRLSTS;
+       uint32_t RESERVED1[2];
+  __IO uint32_t MACISTS;                 /*   15 */
+  __IO uint32_t MACIM;
+  __IO uint32_t MACA0H;
+  __IO uint32_t MACA0L;
+  __IO uint32_t MACA1H;
+  __IO uint32_t MACA1L;
+  __IO uint32_t MACA2H;
+  __IO uint32_t MACA2L;
+  __IO uint32_t MACA3H;
+  __IO uint32_t MACA3L;               /*   24 */
+       uint32_t RESERVED2[40];
+  __IO uint32_t MMCCTRL;                 /*   65 */
+  __IO uint32_t MMCRI;
+  __IO uint32_t MMCTI;
+  __IO uint32_t MMCRIM;
+  __IO uint32_t MMCTIM;               /*   69 */
+       uint32_t RESERVED3[14];
+  __IO uint32_t MMCTFSCC;            /*   84 */
+  __IO uint32_t MMCTFMSCC;
+       uint32_t RESERVED4[5];
+  __IO uint32_t MMCTFCNT;
+       uint32_t RESERVED5[10];
+  __IO uint32_t MMCRFCECNT;
+  __IO uint32_t MMCRFAECNT;
+       uint32_t RESERVED6[10];
+  __IO uint32_t MMCRGUFCNT;
+       uint32_t RESERVED7[334];
+  __IO uint32_t PTPTSCTRL;
+  __IO uint32_t PTPSSINC;
+  __IO uint32_t PTPTSH;
+  __IO uint32_t PTPTSL;
+  __IO uint32_t PTPTSHUD;
+  __IO uint32_t PTPTSLUD;
+  __IO uint32_t PTPTSAD;
+  __IO uint32_t PTPTTH;
+  __IO uint32_t PTPTTL;
+       uint32_t RESERVED8[567];
+  __IO uint32_t DMABM;
+  __IO uint32_t DMATPD;
+  __IO uint32_t DMARPD;
+  __IO uint32_t DMARDLADDR;
+  __IO uint32_t DMATDLADDR;
+  __IO uint32_t DMASTS;
+  __IO uint32_t DMAOPM;
+  __IO uint32_t DMAIE;
+  __IO uint32_t DMAMFBOCNT;
+       uint32_t RESERVED9[9];
+  __IO uint32_t DMACTD;
+  __IO uint32_t DMACRD;
+  __IO uint32_t DMACTBADDR;
+  __IO uint32_t DMACRBADDR;
+} ETH_Type;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define EXT_FLASH_BASE        ((uint32_t)0x08400000) /*!< External FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#if defined (AT32F403xx) || defined (AT32F403Axx) || defined (AT32F407xx)
+ #define XMC_R_BASE           ((uint32_t)0xA0000000) /*!< XMC registers base address */
+#endif
+
+#define UOB_BASE              ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+#define DBGMCU_BASE           ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/** Peripheral memory map */
+#define APB1PERIPH_BASE       (PERIPH_BASE)
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
+
+#define TMR2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TMR3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TMR4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define TMR5_BASE             (APB1PERIPH_BASE + 0x0C00)
+#if !defined (AT32F415xx)
+ #define RTC_BASE             (APB1PERIPH_BASE + 0x2800)
+#else
+ #define ERTC_BASE            (APB1PERIPH_BASE + 0x2800)
+#endif
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
+
+#if !defined (AT32F415xx)
+ #define BKP_BASE             (APB1PERIPH_BASE + 0x6C00)
+#endif
+
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+
+#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
+
+#if defined (AT32F413xx) || defined (AT32F415xx)
+ #define GPIOA_BASE           (PERIPH_BASE + 0x10800)
+ #define GPIOB_BASE           (PERIPH_BASE + 0x10C00)
+ #define GPIOC_BASE           (PERIPH_BASE + 0x11000)
+ #define GPIOD_BASE           (PERIPH_BASE + 0x11400)
+ #define GPIOF_BASE           (PERIPH_BASE + 0x11C00)
+#elif defined (AT32F403xx)
+ #define GPIOA_BASE           (APB2PERIPH_BASE + 0x0800)
+ #define GPIOB_BASE           (APB2PERIPH_BASE + 0x0C00)
+ #define GPIOC_BASE           (APB2PERIPH_BASE + 0x1000)
+ #define GPIOD_BASE           (APB2PERIPH_BASE + 0x1400)
+ #define GPIOE_BASE           (APB2PERIPH_BASE + 0x1800)
+ #define GPIOF_BASE           (APB2PERIPH_BASE + 0x1C00)
+ #define GPIOG_BASE           (APB2PERIPH_BASE + 0x2000)
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+ #define GPIOA_BASE           (APB2PERIPH_BASE + 0x0800)
+ #define GPIOB_BASE           (APB2PERIPH_BASE + 0x0C00)
+ #define GPIOC_BASE           (APB2PERIPH_BASE + 0x1000)
+ #define GPIOD_BASE           (APB2PERIPH_BASE + 0x1400)
+ #define GPIOE_BASE           (APB2PERIPH_BASE + 0x1800)
+#endif
+
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
+#define TMR1_BASE             (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#if !defined (AT32F415xx)
+ #define TMR8_BASE            (APB2PERIPH_BASE + 0x3400)
+#endif
+
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
+#define TMR9_BASE             (APB2PERIPH_BASE + 0x4C00)
+#define TMR10_BASE            (APB2PERIPH_BASE + 0x5000)
+#define TMR11_BASE            (APB2PERIPH_BASE + 0x5400)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)
+
+#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
+
+#if defined (AT32F415xx)
+ #define ACC_BASE             (APB2PERIPH_BASE + 0x5800)
+ #define SDIO_BASE            (PERIPH_BASE + 0x18000)
+ #define USBOTG_BASE          (PERIPH_BASE + 0x10000000)
+ #define COMP_BASE            (APB1PERIPH_BASE + 0x2400)
+ #define DMA2_Channel6_BASE   (AHBPERIPH_BASE + 0x046C)
+ #define DMA2_Channel7_BASE   (AHBPERIPH_BASE + 0x0480)
+#elif defined (AT32F413xx)
+ #if !defined (AT32FEBKCx_MD)
+  #define CAN2_BASE           (APB1PERIPH_BASE + 0x6800)
+  #define ACC_BASE            (APB2PERIPH_BASE + 0x5800)
+  #define SDIO_BASE           (PERIPH_BASE + 0x18000)
+ #endif
+ #define DMA2_Channel6_BASE   (AHBPERIPH_BASE + 0x046C)
+ #define DMA2_Channel7_BASE   (AHBPERIPH_BASE + 0x0480)
+#elif defined (AT32F403xx)
+ #define TMR6_BASE            (APB1PERIPH_BASE + 0x1000)
+ #define TMR7_BASE            (APB1PERIPH_BASE + 0x1400)
+ #define TMR12_BASE           (APB1PERIPH_BASE + 0x1800)
+ #define TMR13_BASE           (APB1PERIPH_BASE + 0x1C00)
+ #define TMR14_BASE           (APB1PERIPH_BASE + 0x2000)
+ #define SPI3_BASE            (APB1PERIPH_BASE + 0x3C00)
+ #define SPI4_BASE            (APB1PERIPH_BASE + 0x4000)
+ #define I2C3_BASE            (APB1PERIPH_BASE + 0x6800)
+ #define DAC_BASE             (APB1PERIPH_BASE + 0x7400)
+ #define ADC3_BASE            (APB2PERIPH_BASE + 0x3C00)
+ #define TMR15_BASE           (APB2PERIPH_BASE + 0x4000)
+ #define SDIO1_BASE           (PERIPH_BASE + 0x18000)
+ #define SDIO2_BASE           (AHBPERIPH_BASE + 0x3400)
+ #define XMC_Bank1_R_BASE     (XMC_R_BASE + 0x0000) /*!< XMC Bank1 registers base address */
+ #define XMC_Bank1E_R_BASE    (XMC_R_BASE + 0x0104) /*!< XMC Bank1E registers base address */
+ #define XMC_Bank1E_H_BASE    (XMC_R_BASE + 0x0220) /*!< XMC Bank1H registers base address */
+ #define XMC_Bank2_R_BASE     (XMC_R_BASE + 0x0060) /*!< XMC Bank2 registers base address */
+ #define XMC_Bank3_R_BASE     (XMC_R_BASE + 0x0080) /*!< XMC Bank3 registers base address */
+ #define XMC_Bank4_R_BASE     (XMC_R_BASE + 0x00A0) /*!< XMC Bank4 registers base address */
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+ #define TMR6_BASE            (APB1PERIPH_BASE + 0x1000)
+ #define TMR7_BASE            (APB1PERIPH_BASE + 0x1400)
+ #define TMR12_BASE           (APB1PERIPH_BASE + 0x1800)
+ #define TMR13_BASE           (APB1PERIPH_BASE + 0x1C00)
+ #define TMR14_BASE           (APB1PERIPH_BASE + 0x2000)
+ #define SPI3_BASE            (APB1PERIPH_BASE + 0x3C00)
+ #define SPI4_BASE            (APB1PERIPH_BASE + 0x4000)
+ #define CAN2_BASE            (APB1PERIPH_BASE + 0x6800)
+ #define DAC_BASE             (APB1PERIPH_BASE + 0x7400)
+ #define ADC3_BASE            (APB2PERIPH_BASE + 0x3C00)
+ #define ACC_BASE             (APB2PERIPH_BASE + 0x5800)
+ #define I2C3_BASE            (APB2PERIPH_BASE + 0x5C00)
+ #define USART6_BASE          (APB2PERIPH_BASE + 0x6000)
+ #define UART7_BASE           (APB2PERIPH_BASE + 0x6400)
+ #define UART8_BASE           (APB2PERIPH_BASE + 0x6800)
+ #define I2S2EXT_BASE         (APB2PERIPH_BASE + 0x6C00)
+ #define I2S3EXT_BASE         (APB2PERIPH_BASE + 0x7000)
+ #define SDIO1_BASE           (PERIPH_BASE + 0x18000)
+ #define SDIO2_BASE           (AHBPERIPH_BASE + 0x3400)
+ #define DMA2_Channel6_BASE   (AHBPERIPH_BASE + 0x046C)
+ #define DMA2_Channel7_BASE   (AHBPERIPH_BASE + 0x0480)
+ #define XMC_Bank1_R_BASE     (XMC_R_BASE + 0x0000) /*!< XMC Bank1 registers base address */
+ #define XMC_Bank1E_R_BASE    (XMC_R_BASE + 0x0104) /*!< XMC Bank1E registers base address */
+ #define XMC_Bank1E_H_BASE    (XMC_R_BASE + 0x0220) /*!< XMC Bank1H registers base address */
+ #define XMC_Bank2_R_BASE     (XMC_R_BASE + 0x0060) /*!< XMC Bank2 registers base address */
+ #define XMC_Bank3_R_BASE     (XMC_R_BASE + 0x0080) /*!< XMC Bank3 registers base address */
+ #define XMC_Bank4_R_BASE     (XMC_R_BASE + 0x00A0) /*!< XMC Bank4 registers base address */
+#endif
+
+#if defined (AT32F407xx)
+ #define ETH_BASE             (AHBPERIPH_BASE + 0x8000)
+ #define ETH_MAC_BASE         (ETH_BASE)
+ #define ETH_MMC_BASE         (ETH_BASE + 0x0100)
+ #define ETH_PTP_BASE         (ETH_BASE + 0x0700)
+ #define ETH_DMA_BASE         (ETH_BASE + 0x1000)
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#if defined (AT32F415xx)
+ #define ACC                ((ACC_Type *) ACC_BASE)
+ #define COMP               ((COMP_Type *)COMP_BASE)
+ #define SDIO               ((SDIO_Type *) SDIO_BASE)
+ #define USBOTG             ((USBOTG_Type *) USBOTG_BASE)
+ #define DMA2_Channel6      ((DMA_Channel_Type *) DMA2_Channel6_BASE)
+ #define DMA2_Channel7      ((DMA_Channel_Type *) DMA2_Channel7_BASE)
+#elif defined (AT32F413xx)
+ #if !defined (AT32FEBKCx_MD)
+  #define CAN2              ((CAN_Type *) CAN2_BASE)
+  #define SDIO              ((SDIO_Type *) SDIO_BASE)
+  #define ACC               ((ACC_Type *) ACC_BASE)
+ #endif
+ #define DMA2_Channel6      ((DMA_Channel_Type *) DMA2_Channel6_BASE)
+ #define DMA2_Channel7      ((DMA_Channel_Type *) DMA2_Channel7_BASE)
+#elif defined (AT32F403xx)
+ #define TMR6               ((TMR_Type *) TMR6_BASE)
+ #define TMR7               ((TMR_Type *) TMR7_BASE)
+ #define TMR12              ((TMR_Type *) TMR12_BASE)
+ #define TMR13              ((TMR_Type *) TMR13_BASE)
+ #define TMR14              ((TMR_Type *) TMR14_BASE)
+ #define SPI3               ((SPI_Type *) SPI3_BASE)
+ #define SPI4               ((SPI_Type *) SPI4_BASE)
+ #define I2C3               ((I2C_Type *) I2C3_BASE)
+ #define DAC                ((DAC_Type *) DAC_BASE)
+ #define GPIOE              ((GPIO_Type *) GPIOE_BASE)
+ #define GPIOG              ((GPIO_Type *) GPIOG_BASE)
+ #define ADC3               ((ADC_Type *) ADC3_BASE)
+ #define TMR15              ((TMR_Type *) TMR15_BASE)
+ #define SDIO1              ((SDIO_Type *) SDIO1_BASE)
+ #define SDIO2              ((SDIO_Type *) SDIO2_BASE)
+ #define XMC_Bank1          ((XMC_Bank1_Type *) XMC_Bank1_R_BASE)
+ #define XMC_Bank1E         ((XMC_Bank1Ext_Type *) XMC_Bank1E_R_BASE)
+ #define XMC_Bank1H         ((XMC_Bank1Hide_Type *) XMC_Bank1E_H_BASE)
+ #define XMC_Bank2          ((XMC_Bank2_Type *) XMC_Bank2_R_BASE)
+ #define XMC_Bank3          ((XMC_Bank3_Type *) XMC_Bank3_R_BASE)
+ #define XMC_Bank4          ((XMC_Bank4_Type *) XMC_Bank4_R_BASE)
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+ #define TMR6               ((TMR_Type *) TMR6_BASE)
+ #define TMR7               ((TMR_Type *) TMR7_BASE)
+ #define TMR12              ((TMR_Type *) TMR12_BASE)
+ #define TMR13              ((TMR_Type *) TMR13_BASE)
+ #define TMR14              ((TMR_Type *) TMR14_BASE)
+ #define SPI3               ((SPI_Type *) SPI3_BASE)
+ #define SPI4               ((SPI_Type *) SPI4_BASE)
+ #define CAN2               ((CAN_Type *) CAN2_BASE)
+ #define I2C3               ((I2C_Type *) I2C3_BASE)
+ #define DAC                ((DAC_Type *) DAC_BASE)
+ #define GPIOE              ((GPIO_Type *) GPIOE_BASE)
+ #define ADC3               ((ADC_Type *) ADC3_BASE)
+ #define ACC                ((ACC_Type *) ACC_BASE)
+ #define USART6             ((USART_Type *) USART6_BASE)
+ #define UART7              ((USART_Type *) UART7_BASE)
+ #define UART8              ((USART_Type *) UART8_BASE)
+ #define I2S2EXT            ((SPI_Type *) I2S2EXT_BASE)
+ #define I2S3EXT            ((SPI_Type *) I2S3EXT_BASE)
+ #define SDIO1              ((SDIO_Type *) SDIO1_BASE)
+ #define SDIO2              ((SDIO_Type *) SDIO2_BASE)
+ #define XMC_Bank1          ((XMC_Bank1_Type *) XMC_Bank1_R_BASE)
+ #define XMC_Bank1E         ((XMC_Bank1Ext_Type *) XMC_Bank1E_R_BASE)
+ #define XMC_Bank1H         ((XMC_Bank1Hide_Type *) XMC_Bank1E_H_BASE)
+ #define XMC_Bank2          ((XMC_Bank2_Type *) XMC_Bank2_R_BASE)
+ #define XMC_Bank3          ((XMC_Bank3_Type *) XMC_Bank3_R_BASE)
+ #define XMC_Bank4          ((XMC_Bank4_Type *) XMC_Bank4_R_BASE)
+ #define DMA2_Channel6      ((DMA_Channel_Type *) DMA2_Channel6_BASE)
+ #define DMA2_Channel7      ((DMA_Channel_Type *) DMA2_Channel7_BASE)
+#endif
+
+#if !defined (AT32F415xx)
+ #define TMR8               ((TMR_Type *) TMR8_BASE)
+#endif
+
+#define TMR2                ((TMR_Type *) TMR2_BASE)
+#define TMR3                ((TMR_Type *) TMR3_BASE)
+#define TMR4                ((TMR_Type *) TMR4_BASE)
+#define TMR5                ((TMR_Type *) TMR5_BASE)
+#if !defined (AT32F415xx)
+ #define RTC                ((RTC_Type *) RTC_BASE)
+#else
+ #define ERTC               ((ERTC_Type *) ERTC_BASE)
+#endif
+#define WWDG                ((WWDG_Type *) WWDG_BASE)
+#define IWDG                ((IWDG_Type *) IWDG_BASE)
+#define SPI2                ((SPI_Type *) SPI2_BASE)
+#define USART2              ((USART_Type *) USART2_BASE)
+#define USART3              ((USART_Type *) USART3_BASE)
+#define UART4               ((USART_Type *) UART4_BASE)
+#define UART5               ((USART_Type *) UART5_BASE)
+#define I2C1                ((I2C_Type *) I2C1_BASE)
+#define I2C2                ((I2C_Type *) I2C2_BASE)
+#define CAN1                ((CAN_Type *) CAN1_BASE)
+#define BKP                 ((BKP_Type *) BKP_BASE)
+#define PWR                 ((PWR_Type *) PWR_BASE)
+#define AFIO                ((AFIO_Type *) AFIO_BASE)
+#define EXTI                ((EXTI_Type *) EXTI_BASE)
+#define GPIOA               ((GPIO_Type *) GPIOA_BASE)
+#define GPIOB               ((GPIO_Type *) GPIOB_BASE)
+#define GPIOC               ((GPIO_Type *) GPIOC_BASE)
+#define GPIOD               ((GPIO_Type *) GPIOD_BASE)
+#if !defined (AT32F403Axx) && !defined (AT32F407xx)
+ #define GPIOF              ((GPIO_Type *) GPIOF_BASE)
+#endif
+#define ADC1                ((ADC_Type *) ADC1_BASE)
+#define ADC2                ((ADC_Type *) ADC2_BASE)
+#define TMR1                ((TMR_Type *) TMR1_BASE)
+#define SPI1                ((SPI_Type *) SPI1_BASE)
+#define USART1              ((USART_Type *) USART1_BASE)
+#define TMR9                ((TMR_Type *) TMR9_BASE)
+#define TMR10               ((TMR_Type *) TMR10_BASE)
+#define TMR11               ((TMR_Type *) TMR11_BASE)
+#define DMA1                ((DMA_Type *) DMA1_BASE)
+#define DMA2                ((DMA_Type *) DMA2_BASE)
+#define DMA1_Channel1       ((DMA_Channel_Type *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_Type *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_Type *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_Type *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_Type *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_Type *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_Type *) DMA1_Channel7_BASE)
+#define DMA2_Channel1       ((DMA_Channel_Type *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_Type *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_Type *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_Type *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_Type *) DMA2_Channel5_BASE)
+#define RCC                 ((RCC_Type *) RCC_BASE)
+#define CRC                 ((CRC_Type *) CRC_BASE)
+#define FLASH               ((FLASH_Type *) FLASH_R_BASE)
+#define UOPTB               ((UOB_Type *) UOB_BASE)
+#define DBGMCU              ((MCUDBG_Type *) DBGMCU_BASE)
+
+#if defined (AT32F407xx)
+ #define ETH                ((ETH_Type *) ETH_BASE)
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+* @{
+*/
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CRC_DT register  *********************/
+#define  CRC_DT_DR                              ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/*******************  Bit definition for CRC_IDT register  ********************/
+#define  CRC_IDT_IDR                            ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+
+/********************  Bit definition for CRC_CTRL register  ********************/
+#define  CRC_CTRL_RST                           ((uint8_t)0x01)        /*!< RESET bit */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*********************  Bit definition for COMP_CTRLSTS register  *************/
+/* COMP1 bits definition */
+#define COMP_CTRLSTS_COMP1EN                    ((uint32_t)0x00000001)        /*!< COMP1 enable */
+#define COMP_CTRLSTS_COMP1SW1                   ((uint32_t)0x00000002)        /*!< SW1 switch control */
+#define COMP_CTRLSTS_COMP1MDE                   ((uint32_t)0x0000000C)        /*!< COMP1 power mode */
+#define COMP_CTRLSTS_COMP1MDE_0                 ((uint32_t)0x00000004)        /*!< COMP1 power mode bit 0 */
+#define COMP_CTRLSTS_COMP1MDE_1                 ((uint32_t)0x00000008)        /*!< COMP1 power mode bit 1 */
+#define COMP_CTRLSTS_COMP1INSEL                 ((uint32_t)0x00000070)        /*!< COMP1 inverting input select */
+#define COMP_CTRLSTS_COMP1INSEL_0               ((uint32_t)0x00000010)        /*!< COMP1 inverting input select bit 0 */
+#define COMP_CTRLSTS_COMP1INSEL_1               ((uint32_t)0x00000020)        /*!< COMP1 inverting input select bit 1 */
+#define COMP_CTRLSTS_COMP1INSEL_2               ((uint32_t)0x00000040)        /*!< COMP1 inverting input select bit 2 */
+#define COMP_CTRLSTS_COMP1OUTSEL                ((uint32_t)0x00000700)        /*!< COMP1 output select */
+#define COMP_CTRLSTS_COMP1OUTSEL_0              ((uint32_t)0x00000100)        /*!< COMP1 output select bit 0 */
+#define COMP_CTRLSTS_COMP1OUTSEL_1              ((uint32_t)0x00000200)        /*!< COMP1 output select bit 1 */
+#define COMP_CTRLSTS_COMP1OUTSEL_2              ((uint32_t)0x00000400)        /*!< COMP1 output select bit 2 */
+#define COMP_CTRLSTS_COMP1POL                   ((uint32_t)0x00000800)        /*!< COMP1 output polarity */
+#define COMP_CTRLSTS_COMP1HYST                  ((uint32_t)0x00003000)        /*!< COMP1 hysteresis */
+#define COMP_CTRLSTS_COMP1HYST_0                ((uint32_t)0x00001000)        /*!< COMP1 hysteresis bit 0 */
+#define COMP_CTRLSTS_COMP1HYST_1                ((uint32_t)0x00002000)        /*!< COMP1 hysteresis bit 1 */
+#define COMP_CTRLSTS_COMP1OUT                   ((uint32_t)0x00004000)        /*!< COMP1 output level */
+#define COMP_CTRLSTS_COMP1LOCK                  ((uint32_t)0x00008000)        /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CTRLSTS_COMP2EN                    ((uint32_t)0x00010000)        /*!< COMP2 enable */
+#define COMP_CTRLSTS_COMP2MDE                   ((uint32_t)0x000C0000)        /*!< COMP2 power mode */
+#define COMP_CTRLSTS_COMP2MDE_0                 ((uint32_t)0x00040000)        /*!< COMP2 power mode bit 0 */
+#define COMP_CTRLSTS_COMP2MDE_1                 ((uint32_t)0x00080000)        /*!< COMP2 power mode bit 1 */
+#define COMP_CTRLSTS_COMP2INSEL                 ((uint32_t)0x00700000)        /*!< COMP2 inverting input select */
+#define COMP_CTRLSTS_COMP2INSEL_0               ((uint32_t)0x00100000)        /*!< COMP2 inverting input select bit 0 */
+#define COMP_CTRLSTS_COMP2INSEL_1               ((uint32_t)0x00200000)        /*!< COMP2 inverting input select bit 1 */
+#define COMP_CTRLSTS_COMP2INSEL_2               ((uint32_t)0x00400000)        /*!< COMP2 inverting input select bit 2 */
+#define COMP_CTRLSTS_WNDWEN                     ((uint32_t)0x00800000)        /*!< Comparators window mode enable */
+#define COMP_CTRLSTS_COMP2OUTSEL                ((uint32_t)0x07000000)        /*!< COMP2 output select */
+#define COMP_CTRLSTS_COMP2OUTSEL_0              ((uint32_t)0x01000000)        /*!< COMP2 output select bit 0 */
+#define COMP_CTRLSTS_COMP2OUTSEL_1              ((uint32_t)0x02000000)        /*!< COMP2 output select bit 1 */
+#define COMP_CTRLSTS_COMP2OUTSEL_2              ((uint32_t)0x04000000)        /*!< COMP2 output select bit 2 */
+#define COMP_CTRLSTS_COMP2POL                   ((uint32_t)0x08000000)        /*!< COMP2 output polarity */
+#define COMP_CTRLSTS_COMP2HYST                  ((uint32_t)0x30000000)        /*!< COMP2 hysteresis */
+#define COMP_CTRLSTS_COMP2HYST_0                ((uint32_t)0x10000000)        /*!< COMP2 hysteresis bit 0 */
+#define COMP_CTRLSTS_COMP2HYST_1                ((uint32_t)0x20000000)        /*!< COMP2 hysteresis bit 1 */
+#define COMP_CTRLSTS_COMP2OUT                   ((uint32_t)0x40000000)        /*!< COMP2 output level */
+#define COMP_CTRLSTS_COMP2LOCK                  ((uint32_t)0x80000000)        /*!< COMP2 lock */
+
+/***************  Bit definition for COMP_G_FILTER_EN register  ***************/
+#define COMP_G_FILTER_EN_GFE                    ((uint16_t)0x0001)            /*!< Comparators Glitch filter enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CTRL register  ********************/
+#define  PWR_CTRL_PDDS                          ((uint16_t)0x0002)            /*!< Power Down Deepsleep */
+#define  PWR_CTRL_CLWUF                         ((uint16_t)0x0004)            /*!< Clear Wakeup Flag */
+#define  PWR_CTRL_CLSBF                         ((uint16_t)0x0008)            /*!< Clear Standby Flag */
+#define  PWR_CTRL_PVDEN                         ((uint16_t)0x0010)            /*!< Power Voltage Detector Enable */
+
+#define  PWR_CTRL_PVDS                          ((uint16_t)0x00E0)            /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CTRL_PVDS_0                        ((uint16_t)0x0020)            /*!< Bit 0 */
+#define  PWR_CTRL_PVDS_1                        ((uint16_t)0x0040)            /*!< Bit 1 */
+#define  PWR_CTRL_PVDS_2                        ((uint16_t)0x0080)            /*!< Bit 2 */
+
+/** PVD level configuration */                                                
+#define  PWR_CTRL_PVDS_2V2                      ((uint16_t)0x0000)            /*!< PVD level 2.2V */
+#define  PWR_CTRL_PVDS_2V3                      ((uint16_t)0x0020)            /*!< PVD level 2.3V */
+#define  PWR_CTRL_PVDS_2V4                      ((uint16_t)0x0040)            /*!< PVD level 2.4V */
+#define  PWR_CTRL_PVDS_2V5                      ((uint16_t)0x0060)            /*!< PVD level 2.5V */
+#define  PWR_CTRL_PVDS_2V6                      ((uint16_t)0x0080)            /*!< PVD level 2.6V */
+#define  PWR_CTRL_PVDS_2V7                      ((uint16_t)0x00A0)            /*!< PVD level 2.7V */
+#define  PWR_CTRL_PVDS_2V8                      ((uint16_t)0x00C0)            /*!< PVD level 2.8V */
+#define  PWR_CTRL_PVDS_2V9                      ((uint16_t)0x00E0)            /*!< PVD level 2.9V */
+
+#define  PWR_CTRL_DBP                           ((uint16_t)0x0100)            /*!< Disable Backup Domain write protection */
+
+/*******************  Bit definition for PWR_CTRLSTS register  ********************/
+#define  PWR_CTRLSTS_WUF                        ((uint16_t)0x0001)            /*!< Wakeup Flag */
+#define  PWR_CTRLSTS_SBF                        ((uint16_t)0x0002)            /*!< Standby Flag */
+#define  PWR_CTRLSTS_PVD                        ((uint16_t)0x0004)            /*!< PVD Output */
+#define  PWR_CTRLSTS_WUPEN                      ((uint16_t)0x0100)            /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Backup registers                                */
+/*                                                                            */
+/******************************************************************************/
+#if !defined (AT32F415xx)
+/*******************  Bit definition for BKP_DT1 register  ********************/
+#define  BKP_DT1_D                              ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT2 register  ********************/
+#define  BKP_DT2_D                              ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT3 register  ********************/
+#define  BKP_DT3_D                              ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT4 register  ********************/
+#define  BKP_DT4_D                              ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT5 register  ********************/
+#define  BKP_DT5_D                              ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT6 register  ********************/
+#define  BKP_DT6_D                              ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT7 register  ********************/
+#define  BKP_DT7_D                              ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT8 register  ********************/
+#define  BKP_DT8_D                              ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT9 register  ********************/
+#define  BKP_DT9_D                              ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT10 register  *******************/
+#define  BKP_DT10_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT11 register  *******************/
+#define  BKP_DT11_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT12 register  *******************/
+#define  BKP_DT12_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT13 register  *******************/
+#define  BKP_DT13_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT14 register  *******************/
+#define  BKP_DT14_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT15 register  *******************/
+#define  BKP_DT15_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT16 register  *******************/
+#define  BKP_DT16_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT17 register  *******************/
+#define  BKP_DT17_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/******************  Bit definition for BKP_DT18 register  ********************/
+#define  BKP_DT18_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT19 register  *******************/
+#define  BKP_DT19_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT20 register  *******************/
+#define  BKP_DT20_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT21 register  *******************/
+#define  BKP_DT21_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT22 register  *******************/
+#define  BKP_DT22_D                             ((uint16_t)0xFFFF)           /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT23 register  *******************/
+#define  BKP_DT23_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT24 register  *******************/
+#define  BKP_DT24_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT25 register  *******************/
+#define  BKP_DT25_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT26 register  *******************/
+#define  BKP_DT26_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT27 register  *******************/
+#define  BKP_DT27_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT28 register  *******************/
+#define  BKP_DT28_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT29 register  *******************/
+#define  BKP_DT29_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT30 register  *******************/
+#define  BKP_DT30_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT31 register  *******************/
+#define  BKP_DT31_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT32 register  *******************/
+#define  BKP_DT32_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT33 register  *******************/
+#define  BKP_DT33_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT34 register  *******************/
+#define  BKP_DT34_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT35 register  *******************/
+#define  BKP_DT35_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT36 register  *******************/
+#define  BKP_DT36_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT37 register  *******************/
+#define  BKP_DT37_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT38 register  *******************/
+#define  BKP_DT38_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT39 register  *******************/
+#define  BKP_DT39_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT40 register  *******************/
+#define  BKP_DT40_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT41 register  *******************/
+#define  BKP_DT41_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/*******************  Bit definition for BKP_DT42 register  *******************/
+#define  BKP_DT42_D                             ((uint16_t)0xFFFF)            /*!< Backup data */
+
+/******************  Bit definition for BKP_RTCCAL register  *******************/
+#define  BKP_RTCCAL_CAL                         ((uint16_t)0x007F)            /*!< Calibration value */
+#define  BKP_RTCCAL_OT1CAL                      ((uint16_t)0x0080)            /*!< Calibration Clock Output */
+#define  BKP_RTCCAL_OT2EN                       ((uint16_t)0x0100)            /*!< Alarm or Second Output Enable */
+#define  BKP_RTCCAL_OT2SEL                      ((uint16_t)0x0200)            /*!< Alarm or Second Output Selection */
+
+/********************  Bit definition for BKP_CTRL register  ********************/
+#define  BKP_CTRL_TPEN                          ((uint8_t)0x01)               /*!< TAMPER pin enable */
+#define  BKP_CTRL_TPALV                         ((uint8_t)0x02)               /*!< TAMPER pin active level */
+
+/*******************  Bit definition for BKP_CTRLSTS register  ********************/
+#define  BKP_CTRLSTS_CTPEF                      ((uint16_t)0x0001)            /*!< Clear Tamper event */
+#define  BKP_CTRLSTS_CTPIF                      ((uint16_t)0x0002)            /*!< Clear Tamper Interrupt */
+#define  BKP_CTRLSTS_TPIEN                      ((uint16_t)0x0004)            /*!< TAMPER Pin interrupt enable */
+#define  BKP_CTRLSTS_TPEF                       ((uint16_t)0x0100)            /*!< Tamper Event Flag */
+#define  BKP_CTRLSTS_TPIF                       ((uint16_t)0x0200)            /*!< Tamper Interrupt Flag */
+#endif
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CTRL register  ********************/
+#define  RCC_CTRL_HSIEN                         ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
+#define  RCC_CTRL_HSISTBL                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
+#if defined (AT32F403xx)
+ #define  RCC_CTRL_HSITWK                       ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
+#else
+ #define  RCC_CTRL_HSITWK                       ((uint32_t)0x000000FE)        /*!< Internal High Speed clock trimming */
+#endif
+#define  RCC_CTRL_HSICAL                        ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
+#define  RCC_CTRL_HSEEN                         ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
+#define  RCC_CTRL_HSESTBL                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
+#define  RCC_CTRL_HSEBYPS                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
+#define  RCC_CTRL_HSECFDEN                      ((uint32_t)0x00080000)        /*!< Clock Security System enable */
+#define  RCC_CTRL_PLLEN                         ((uint32_t)0x01000000)        /*!< PLL enable */
+#define  RCC_CTRL_PLLSTBL                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
+
+/*******************  Bit definition for RCC_CFG register  *******************/
+/** SYSCLKSEL configuration */
+#define  RCC_CFG_SYSCLKSEL                      ((uint32_t)0x00000003)        /*!< SYSCLKSEL[1:0] bits (System clock Switch) */
+#define  RCC_CFG_SYSCLKSEL_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFG_SYSCLKSEL_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  RCC_CFG_SYSCLKSEL_HSI                  ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFG_SYSCLKSEL_HSE                  ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFG_SYSCLKSEL_PLL                  ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+
+/** SYSCLKSTST configuration */
+#define  RCC_CFG_SYSCLKSTS                      ((uint32_t)0x0000000C)        /*!< SYSCLKSTST[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFG_SYSCLKSTS_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFG_SYSCLKSTS_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  RCC_CFG_SYSCLKSTS_HSI                  ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFG_SYSCLKSTS_HSE                  ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFG_SYSCLKSTS_PLL                  ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+
+/** AHBPSC configuration */
+#define  RCC_CFG_AHBPSC                         ((uint32_t)0x000000F0)        /*!< AHBPSC[3:0] bits (AHB prescaler) */
+#define  RCC_CFG_AHBPSC_0                       ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFG_AHBPSC_1                       ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFG_AHBPSC_2                       ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFG_AHBPSC_3                       ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  RCC_CFG_AHBPSC_DIV1                    ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFG_AHBPSC_DIV2                    ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFG_AHBPSC_DIV4                    ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFG_AHBPSC_DIV8                    ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFG_AHBPSC_DIV16                   ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFG_AHBPSC_DIV64                   ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFG_AHBPSC_DIV128                  ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFG_AHBPSC_DIV256                  ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFG_AHBPSC_DIV512                  ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+/** APB1PSC configuration */
+#define  RCC_CFG_APB1PSC                        ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFG_APB1PSC_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFG_APB1PSC_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFG_APB1PSC_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
+
+#define  RCC_CFG_APB1PSC_DIV1                   ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFG_APB1PSC_DIV2                   ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFG_APB1PSC_DIV4                   ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFG_APB1PSC_DIV8                   ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFG_APB1PSC_DIV16                  ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+/** APB2PSC configuration */
+#define  RCC_CFG_APB2PSC                        ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFG_APB2PSC_0                      ((uint32_t)0x00000800)        /*!< Bit 0 */
+#define  RCC_CFG_APB2PSC_1                      ((uint32_t)0x00001000)        /*!< Bit 1 */
+#define  RCC_CFG_APB2PSC_2                      ((uint32_t)0x00002000)        /*!< Bit 2 */
+
+#define  RCC_CFG_APB2PSC_DIV1                   ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFG_APB2PSC_DIV2                   ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
+#define  RCC_CFG_APB2PSC_DIV4                   ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
+#define  RCC_CFG_APB2PSC_DIV8                   ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
+#define  RCC_CFG_APB2PSC_DIV16                  ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
+
+#define  RCC_CFG_PLLRC                          ((uint32_t)0x00010000)        /*!< PLL entry clock source */
+#define  RCC_CFG_PLLHSEPSC                      ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+
+
+/** ADCPSC configuration */
+#define  RCC_CFG_ADCPSC                         ((uint32_t)0x1000C000)        /*!< ADCPSC[1:0] bits (ADC prescaler) */
+#define  RCC_CFG_ADCPSC_0                       ((uint32_t)0x00004000)        /*!< Bit 0 */
+#define  RCC_CFG_ADCPSC_1                       ((uint32_t)0x00008000)        /*!< Bit 1 */
+#define  RCC_CFG_ADCPSC_2                       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  RCC_CFG_ADCPSC_DIV2                    ((uint32_t)0x00000000)        /*!< PCLK2 divided by 2 */
+#define  RCC_CFG_ADCPSC_DIV4                    ((uint32_t)0x00004000)        /*!< PCLK2 divided by 4 */
+#define  RCC_CFG_ADCPSC_DIV6                    ((uint32_t)0x00008000)        /*!< PCLK2 divided by 6 */
+#define  RCC_CFG_ADCPSC_DIV8                    ((uint32_t)0x0000C000)        /*!< PCLK2 divided by 8 */
+#define  RCC_CFG_ADCPSC_DIV12                   ((uint32_t)0x10004000)        /*!< PCLK2 divided by 12 */
+#define  RCC_CFG_ADCPSC_DIV16                   ((uint32_t)0x1000C000)        /*!< PCLK2 divided by 16 */
+
+#define  RCC_CFG_PLLCFG_MASK                    ((uint32_t)0x1FC0FFFF)        /*!< Mask for PLLRANGE, PLLHSEPSC, PLLMULT, PLLRC */
+
+
+/** PLLMULT configuration */
+#define  RCC_CFG_PLLMULT                        ((uint32_t)0x603C0000)        /*!< PLLMUL[5:0] bits (PLL multiplication factor) */
+#define  RCC_CFG_PLLMULT_0                      ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFG_PLLMULT_1                      ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFG_PLLMULT_2                      ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFG_PLLMULT_3                      ((uint32_t)0x00200000)        /*!< Bit 3 */
+#define  RCC_CFG_PLLMULT_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
+#define  RCC_CFG_PLLMULT_5                      ((uint32_t)0x40000000)        /*!< Bit 5 */
+#define  RCC_CFG_PLLMULT_LB_MASK                ((uint32_t)0x003C0000)
+#define  RCC_CFG_PLLMULT_HB_MASK                ((uint32_t)0x60000000)
+#define  RCC_CFG_PLLMULT_LB_POS                 ((uint32_t)18)
+#define  RCC_CFG_PLLMULT_HB_POS                 ((uint32_t)29)
+#define  RCC_CFG_PLLMULT_HB_OFFSET              ((uint32_t)4)
+
+
+#define  RCC_CFG_PLLRANGE                       ((uint32_t)0x80000000)        /*!< PLL Frequency range.  */
+#define  RCC_CFG_PLLRANGE_LE72MHZ               ((uint32_t)0x00000000)        /*!< When PLL frequency is less than or equal to 72MHz */
+#define  RCC_CFG_PLLRANGE_GT72MHZ               ((uint32_t)0x80000000)        /*!< When PLL frequency is greater than 72MHz */
+
+#define  RCC_CFG_PLLRC_HSI_DIV2                 ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define  RCC_CFG_PLLRC_HSE                      ((uint32_t)0x00010000)        /*!< HSE clock selected as PLL entry clock source */
+
+#define  RCC_CFG_PLLHSEPSC_HSE                  ((uint32_t)0x00000000)        /*!< HSE clock not divided for PLL entry */
+#define  RCC_CFG_PLLHSEPSC_HSE_DIV2             ((uint32_t)0x00020000)        /*!< HSE clock divided by 2 for PLL entry */
+
+#define  RCC_CFG_PLLMULT2                       ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+#define  RCC_CFG_PLLMULT3                       ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+#define  RCC_CFG_PLLMULT4                       ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+#define  RCC_CFG_PLLMULT5                       ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+#define  RCC_CFG_PLLMULT6                       ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+#define  RCC_CFG_PLLMULT7                       ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+#define  RCC_CFG_PLLMULT8                       ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+#define  RCC_CFG_PLLMULT9                       ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+#define  RCC_CFG_PLLMULT10                      ((uint32_t)0x00200000)        /*!< PLL input clock*10 */
+#define  RCC_CFG_PLLMULT11                      ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+#define  RCC_CFG_PLLMULT12                      ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+#define  RCC_CFG_PLLMULT13                      ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+#define  RCC_CFG_PLLMULT14                      ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+#define  RCC_CFG_PLLMULT15                      ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+#define  RCC_CFG_PLLMULT16                      ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+
+#define  RCC_CFG_PLLMULT17                      ((uint32_t)0x20000000)        /*!< PLL input clock*17 */
+#define  RCC_CFG_PLLMULT18                      ((uint32_t)0x20040000)        /*!< PLL input clock*18 */
+#define  RCC_CFG_PLLMULT19                      ((uint32_t)0x20080000)        /*!< PLL input clock*19 */
+#define  RCC_CFG_PLLMULT20                      ((uint32_t)0x200C0000)        /*!< PLL input clock*20 */
+#define  RCC_CFG_PLLMULT21                      ((uint32_t)0x20100000)        /*!< PLL input clock*21 */
+#define  RCC_CFG_PLLMULT22                      ((uint32_t)0x20140000)        /*!< PLL input clock*22 */
+#define  RCC_CFG_PLLMULT23                      ((uint32_t)0x20180000)        /*!< PLL input clock*23 */
+#define  RCC_CFG_PLLMULT24                      ((uint32_t)0x201C0000)        /*!< PLL input clock*24 */
+#define  RCC_CFG_PLLMULT25                      ((uint32_t)0x20200000)        /*!< PLL input clock*25 */
+#define  RCC_CFG_PLLMULT26                      ((uint32_t)0x20240000)        /*!< PLL input clock*26 */
+#define  RCC_CFG_PLLMULT27                      ((uint32_t)0x20280000)        /*!< PLL input clock*27 */
+#define  RCC_CFG_PLLMULT28                      ((uint32_t)0x202C0000)        /*!< PLL input clock*28 */
+#define  RCC_CFG_PLLMULT29                      ((uint32_t)0x20300000)        /*!< PLL input clock*29 */
+#define  RCC_CFG_PLLMULT30                      ((uint32_t)0x20340000)        /*!< PLL input clock*30 */
+#define  RCC_CFG_PLLMULT31                      ((uint32_t)0x20380000)        /*!< PLL input clock*31 */
+#define  RCC_CFG_PLLMULT32                      ((uint32_t)0x203C0000)        /*!< PLL input clock*32 */
+#define  RCC_CFG_PLLMULT33                      ((uint32_t)0x40000000)        /*!< PLL input clock*33 */
+#define  RCC_CFG_PLLMULT34                      ((uint32_t)0x40040000)        /*!< PLL input clock*34 */
+#define  RCC_CFG_PLLMULT35                      ((uint32_t)0x40080000)        /*!< PLL input clock*35 */
+#define  RCC_CFG_PLLMULT36                      ((uint32_t)0x400C0000)        /*!< PLL input clock*36 */
+#define  RCC_CFG_PLLMULT37                      ((uint32_t)0x40100000)        /*!< PLL input clock*37 */
+#define  RCC_CFG_PLLMULT38                      ((uint32_t)0x40140000)        /*!< PLL input clock*38 */
+#define  RCC_CFG_PLLMULT39                      ((uint32_t)0x40180000)        /*!< PLL input clock*39 */
+#define  RCC_CFG_PLLMULT40                      ((uint32_t)0x401C0000)        /*!< PLL input clock*40 */
+#define  RCC_CFG_PLLMULT41                      ((uint32_t)0x40200000)        /*!< PLL input clock*41 */
+#define  RCC_CFG_PLLMULT42                      ((uint32_t)0x40240000)        /*!< PLL input clock*42 */
+#define  RCC_CFG_PLLMULT43                      ((uint32_t)0x40280000)        /*!< PLL input clock*43 */
+#define  RCC_CFG_PLLMULT44                      ((uint32_t)0x402C0000)        /*!< PLL input clock*44 */
+#define  RCC_CFG_PLLMULT45                      ((uint32_t)0x40300000)        /*!< PLL input clock*45 */
+#define  RCC_CFG_PLLMULT46                      ((uint32_t)0x40340000)        /*!< PLL input clock*46 */
+#define  RCC_CFG_PLLMULT47                      ((uint32_t)0x40380000)        /*!< PLL input clock*47 */
+#define  RCC_CFG_PLLMULT48                      ((uint32_t)0x403C0000)        /*!< PLL input clock*48 */
+#define  RCC_CFG_PLLMULT49                      ((uint32_t)0x60000000)        /*!< PLL input clock*49 */
+#define  RCC_CFG_PLLMULT50                      ((uint32_t)0x60040000)        /*!< PLL input clock*50 */
+#define  RCC_CFG_PLLMULT51                      ((uint32_t)0x60080000)        /*!< PLL input clock*51 */
+#define  RCC_CFG_PLLMULT52                      ((uint32_t)0x600C0000)        /*!< PLL input clock*52 */
+#define  RCC_CFG_PLLMULT53                      ((uint32_t)0x60100000)        /*!< PLL input clock*53 */
+#define  RCC_CFG_PLLMULT54                      ((uint32_t)0x60140000)        /*!< PLL input clock*54 */
+#define  RCC_CFG_PLLMULT55                      ((uint32_t)0x60180000)        /*!< PLL input clock*55 */
+#define  RCC_CFG_PLLMULT56                      ((uint32_t)0x601C0000)        /*!< PLL input clock*56 */
+#define  RCC_CFG_PLLMULT57                      ((uint32_t)0x60200000)        /*!< PLL input clock*57 */
+#define  RCC_CFG_PLLMULT58                      ((uint32_t)0x60240000)        /*!< PLL input clock*58 */
+#define  RCC_CFG_PLLMULT59                      ((uint32_t)0x60280000)        /*!< PLL input clock*59 */
+#define  RCC_CFG_PLLMULT60                      ((uint32_t)0x602C0000)        /*!< PLL input clock*60 */
+#define  RCC_CFG_PLLMULT61                      ((uint32_t)0x60300000)        /*!< PLL input clock*61 */
+#define  RCC_CFG_PLLMULT62                      ((uint32_t)0x60340000)        /*!< PLL input clock*62 */
+#define  RCC_CFG_PLLMULT63                      ((uint32_t)0x60380000)        /*!< PLL input clock*63 */
+#define  RCC_CFG_PLLMULT64                      ((uint32_t)0x603C0000)        /*!< PLL input clock*64 */
+
+#define  RCC_CFG_USBPSC                         ((uint32_t)0x08C00000)        /*!< USB Device prescaler */
+#define  RCC_CFG_USBPSC_0                       ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  RCC_CFG_USBPSC_1                       ((uint32_t)0x00800000)        /*!< Bit 1 */
+#define  RCC_CFG_USBPSC_2                       ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  RCC_CFG_USBPSC_DIV1_5                  ((uint32_t)0x00000000)        /*!< SYSCLK divided by 1.5 selected as USB clock source */
+#define  RCC_CFG_USBPSC_DIV1                    ((uint32_t)0x00400000)        /*!< SYSCLK selected as USB clock source */
+#define  RCC_CFG_USBPSC_DIV2_5                  ((uint32_t)0x00800000)        /*!< SYSCLK divided by 2.5 selected as USB clock source */
+#define  RCC_CFG_USBPSC_DIV2                    ((uint32_t)0x00C00000)        /*!< SYSCLK divided by 2 selected as USB clock source */
+#define  RCC_CFG_USBPSC_DIV3_5                  ((uint32_t)0x08000000)        /*!< SYSCLK divided by 3.5 selected as USB clock source */
+#define  RCC_CFG_USBPSC_DIV3                    ((uint32_t)0x08400000)        /*!< SYSCLK divided by 3 selected as USB clock source */
+#define  RCC_CFG_USBPSC_DIV4                    ((uint32_t)0x08800000)        /*!< SYSCLK divided by 4 selected as USB clock source */
+#define  RCC_CFG_USBPSC_DIV4_0                  ((uint32_t)0x08C00000)        /*!< SYSCLK divided by 4 selected as USB clock source */
+
+/** CLKOUT configuration */
+#define  RCC_CFG_CLKOUT                         ((uint32_t)0x07000000)        /*!< CLKOUT[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_CFG_CLKOUT_0                       ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  RCC_CFG_CLKOUT_1                       ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  RCC_CFG_CLKOUT_2                       ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define  RCC_CFG_CLKOUT_NOCLK                   ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CFG_CLKOUT_SYSCLK                  ((uint32_t)0x04000000)        /*!< System clock selected as CLKOUT source */
+#define  RCC_CFG_CLKOUT_HSI                     ((uint32_t)0x05000000)        /*!< HSI clock selected as CLKOUT source */
+#define  RCC_CFG_CLKOUT_HSE                     ((uint32_t)0x06000000)        /*!< HSE clock selected as CLKOUT source  */
+#define  RCC_CFG_CLKOUT_PLL_DIV2                ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as CLKOUT source */
+
+/********************  Bit definition for RCC_CLKINT register  ********************/
+#define  RCC_CLKINT_LSISTBLF                    ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CLKINT_LSESTBLF                    ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CLKINT_HSISTBLF                    ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CLKINT_HSESTBLF                    ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CLKINT_PLLSTBLF                    ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CLKINT_HSECFDF                     ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CLKINT_LSISTBLIE                   ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CLKINT_LSESTBLIE                   ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CLKINT_HSISTBLIE                   ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CLKINT_HSESTBLIE                   ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CLKINT_PLLSTBLIE                   ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CLKINT_LSISTBLFC                   ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CLKINT_LSESTBLFC                   ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CLKINT_HSISTBLFC                   ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CLKINT_HSESTBLFC                   ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CLKINT_PLLSTBLFC                   ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CLKINT_HSECFDFC                    ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+/*****************  Bit definition for RCC_APB2RST register  *****************/
+#define  RCC_APB2RST_AFIORST                    ((uint32_t)0x00000001)        /*!< Alternate Function I/O reset */
+#define  RCC_APB2RST_GPIOARST                   ((uint32_t)0x00000004)        /*!< I/O port A reset */
+#define  RCC_APB2RST_GPIOBRST                   ((uint32_t)0x00000008)        /*!< I/O port B reset */
+#define  RCC_APB2RST_GPIOCRST                   ((uint32_t)0x00000010)        /*!< I/O port C reset */
+#define  RCC_APB2RST_GPIODRST                   ((uint32_t)0x00000020)        /*!< I/O port D reset */
+#define  RCC_APB2RST_ADC1RST                    ((uint32_t)0x00000200)        /*!< ADC 1 interface reset */
+#define  RCC_APB2RST_TMR1RST                    ((uint32_t)0x00000800)        /*!< TMR1 Timer reset */
+#define  RCC_APB2RST_SPI1RST                    ((uint32_t)0x00001000)        /*!< SPI 1 reset */
+#define  RCC_APB2RST_USART1RST                  ((uint32_t)0x00004000)        /*!< USART1 reset */
+
+#if !defined (AT32F415xx)
+ #define  RCC_APB2RST_ADC2RST                   ((uint32_t)0x00000400)        /*!< ADC 2 interface reset */
+#endif
+
+#if !defined (AT32F413Kx_MD) && !defined (AT32F413Kx_HD) && \
+    !defined (AT32F413Cx_MD) && !defined (AT32F413Rx_MD) && \
+	!defined (AT32FEBKCx_MD) && !defined (TS32F401CBU7)  && \
+    !defined (AT32F415xx)
+ #define  RCC_APB2RST_TMR8RST                   ((uint32_t)0x00002000)        /*!< TMR8 Timer reset */
+#endif
+
+#if !defined (AT32F403Axx) || !defined (AT32F407xx)
+ #define  RCC_APB2RST_GPIOFRST                  ((uint32_t)0x00000080)        /*!< I/O port F reset */
+#endif
+
+#if !defined (AT32FEBKCx_MD)
+ #define  RCC_APB2RST_TMR9RST                   ((uint32_t)0x00080000)         /*!< TMR9 Timer reset */
+ #define  RCC_APB2RST_TMR10RST                  ((uint32_t)0x00100000)         /*!< TMR10 Timer reset */
+ #define  RCC_APB2RST_TMR11RST                  ((uint32_t)0x00200000)         /*!< TMR11 Timer reset */
+#endif
+
+#if defined (AT32F403xx)
+ #define  RCC_APB2RST_GPIOERST                  ((uint32_t)0x00000040)        /*!< I/O port E reset */
+ #define  RCC_APB2RST_GPIOGRST                  ((uint32_t)0x00000100)        /*!< I/O port G reset */
+ #define  RCC_APB2RST_ADC3RST                   ((uint32_t)0x00008000)        /*!< ADC3 interface reset */
+ #define  RCC_APB2RST_TMR15RST                  ((uint32_t)0x00010000)        /*!< TMR15 Timer reset */
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+ #define  RCC_APB2RST_GPIOERST                  ((uint32_t)0x00000040)        /*!< I/O port E reset */
+ #define  RCC_APB2RST_ADC3RST                   ((uint32_t)0x00008000)        /*!< ADC3 interface reset */
+ #define  RCC_APB2RST_I2C3RST                   ((uint32_t)0x00800000)        /*!< I2C3 interface reset */
+ #define  RCC_APB2RST_USART6RST                 ((uint32_t)0x01000000)        /*!< USART6 interface reset */
+ #define  RCC_APB2RST_UART7RST                  ((uint32_t)0x02000000)        /*!< UART7 interface reset */
+ #define  RCC_APB2RST_UART8RST                  ((uint32_t)0x04000000)        /*!< UART8 interface reset */
+#endif
+
+#if !defined (AT32F403xx)
+ #if !defined (AT32FEBKCx_MD)
+  #define  RCC_APB2RST_ACCRST                   ((uint32_t)0x00400000)         /*!< ACC reset */
+ #endif
+#endif
+
+#if defined (AT32F415xx)
+ #define  RCC_APB2RST_EFCBRST                   ((uint32_t)0x00800000)         /*!< EFCB reset */
+#endif
+/*****************  Bit definition for RCC_APB1RST register  *****************/
+#define  RCC_APB1RST_TMR2RST                    ((uint32_t)0x00000001)        /*!< Timer 2 reset */
+#define  RCC_APB1RST_TMR3RST                    ((uint32_t)0x00000002)        /*!< Timer 3 reset */
+#define  RCC_APB1RST_WWDGRST                    ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
+#define  RCC_APB1RST_USART2RST                  ((uint32_t)0x00020000)        /*!< USART 2 reset */
+#define  RCC_APB1RST_I2C1RST                    ((uint32_t)0x00200000)        /*!< I2C 1 reset */
+#define  RCC_APB1RST_CAN1RST                    ((uint32_t)0x02000000)        /*!< CAN1 reset */
+#define  RCC_APB1RST_PWRRST                     ((uint32_t)0x10000000)        /*!< Power interface reset */
+#define  RCC_APB1RST_TMR4RST                    ((uint32_t)0x00000004)        /*!< Timer 4 reset */
+#define  RCC_APB1RST_SPI2RST                    ((uint32_t)0x00004000)        /*!< SPI 2 reset */
+#define  RCC_APB1RST_I2C2RST                    ((uint32_t)0x00400000)        /*!< I2C 2 reset */
+#define  RCC_APB1RST_TMR5RST                    ((uint32_t)0x00000008)        /*!< Timer 5 reset */
+
+#if !defined (AT32F415xx)
+ #define  RCC_APB1RST_BKPRST                    ((uint32_t)0x08000000)        /*!< Backup interface reset */
+ #define  RCC_APB1RST_USBRST                    ((uint32_t)0x00800000)        /*!< USB Device reset */
+#endif
+
+#if defined (AT32F415xx)
+ #define  RCC_APB1RST_COMPRST                   ((uint32_t)0x00000200)        /*!< Compare reset */
+#endif
+
+#if defined (AT32F403Vx_HD) || defined (AT32F403Zx_HD) || \
+    defined (AT32F403Vx_XL) || defined (AT32F403Zx_XL) || \
+    defined (AT32F403Axx)   || defined (AT32F407xx)
+ #define  RCC_APB1RST_SPI4RST                   ((uint32_t)0x00010000)        /*!< SPI 4 reset */
+#endif /* AT32F403Vx_HD || AT32F403Zx_HD || AT32F403Vx_XL || AT32F403Zx_XL 
+          AT32F403Axx   || AT32F407xx */
+
+#if !defined (AT32F413Kx_MD) && !defined (AT32F413Kx_HD) && \
+    !defined (AT32F415K8U7_4)&& !defined (AT32F415KBU7_4)&& \
+    !defined (AT32F415KCU7_4)
+ #define  RCC_APB1RST_USART3RST                 ((uint32_t)0x00040000)        /*!< USART 3 reset */
+#endif
+
+#if !defined (AT32F413Kx_MD) && !defined (AT32F413Kx_HD) && \
+    !defined (AT32F413Cx_MD) && !defined (AT32F413Cx_HD) && \
+    !defined (AT32FEBKCx_MD) && !defined (TS32F401CBU7)  && \
+    !defined (AT32F415K8U7_4)&& !defined (AT32F415KBU7_4)&& \
+    !defined (AT32F415KCU7_4)&& !defined (AT32F415C8T7)  && \
+    !defined (AT32F415CBT7)  && !defined (AT32F415CCT7)  && \
+    !defined (AT32F415CBU7)  && !defined (AT32F415CCU7)
+ #define  RCC_APB1RST_UART4RST                  ((uint32_t)0x00080000)        /*!< UART 4 reset */
+ #define  RCC_APB1RST_UART5RST                  ((uint32_t)0x00100000)        /*!< UART 5 reset */
+#endif
+
+#if defined (AT32F413Cx_HD) || defined (AT32F413Cx_MD) || \
+    defined (AT32F413Rx_HD) || defined (AT32F413Rx_MD) || \
+    defined (TS32F401CBU7)
+ #define  RCC_APB1RST_CAN2RST                   ((uint32_t)0x80000000)        /*!< CAN2 reset */
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+ #define  RCC_APB1RST_CAN2RST                   ((uint32_t)0x04000000)        /*!< CAN2 reset */
+#endif
+
+#if defined (AT32F403xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+ #define  RCC_APB1RST_TMR6RST                   ((uint32_t)0x00000010)        /*!< Timer 6 reset */
+ #define  RCC_APB1RST_TMR7RST                   ((uint32_t)0x00000020)        /*!< Timer 7 reset */
+ #define  RCC_APB1RST_SPI3RST                   ((uint32_t)0x00008000)        /*!< SPI 3 reset */
+ #define  RCC_APB1RST_I2C3RST                   ((uint32_t)0x04000000)        /*!< I2C 3 reset */
+ #define  RCC_APB1RST_TMR12RST                  ((uint32_t)0x00000040)        /*!< TMR12 Timer reset */
+ #define  RCC_APB1RST_TMR13RST                  ((uint32_t)0x00000080)        /*!< TMR13 Timer reset */
+ #define  RCC_APB1RST_TMR14RST                  ((uint32_t)0x00000100)        /*!< TMR14 Timer reset */
+ #define  RCC_APB1RST_DACRST                    ((uint32_t)0x20000000)        /*!< DAC interface reset */
+#endif
+
+/******************  Bit definition for RCC_AHBEN register  ******************/
+#define  RCC_AHBEN_DMA1EN                       ((uint16_t)0x0001)            /*!< DMA1 clock enable */
+#define  RCC_AHBEN_DMA2EN                       ((uint16_t)0x0002)            /*!< DMA2 clock enable */
+#define  RCC_AHBEN_SRAMEN                       ((uint16_t)0x0004)            /*!< SRAM interface clock enable */
+#define  RCC_AHBEN_FLASHEN                      ((uint16_t)0x0010)            /*!< FLITF clock enable */
+#define  RCC_AHBEN_CRCEN                        ((uint16_t)0x0040)            /*!< CRC clock enable */
+
+#if !defined (AT32FEBKCx_MD) && !defined (AT32F403Cx_HD) && \
+    !defined (AT32F403Cx_MD) && !defined (AT32F403Cx_XL) && \
+    !defined (AT32F403ACCT7) && !defined (AT32F403ACCU7) && \
+    !defined (AT32F403ACET7) && !defined (AT32F403ACEU7) && \
+    !defined (AT32F403ACGT7) && !defined (AT32F403ACGU7)
+ #define  RCC_AHBEN_SDIO1EN                     ((uint16_t)0x0400)            /*!< SDIO1 clock enable */
+#endif
+
+#if defined (AT32F403Vx_HD) || defined (AT32F403Zx_HD) || \
+    defined (AT32F403Vx_XL) || defined (AT32F403Zx_XL) || \
+    defined (AT32F403ARCT7) || defined (AT32F403ARGT7) || \
+    defined (AT32F403ARET7) || defined (AT32F403AVET7) || \
+    defined (AT32F403AVCT7) || defined (AT32F403AVGT7) || \
+    defined (AT32F407xx)
+ #define  RCC_AHBEN_XMCEN                       ((uint16_t)0x0100)            /*!< XMC clock enable */
+#endif /* AT32F403Vx_HD || AT32F403Zx_HD || AT32F403Vx_XL ||
+          AT32F403Zx_XL || AT32F403ARCT7 || AT32F403ARGT7 ||
+          AT32F403AVCT7 || AT32F403AVGT7 || AT32F403ARET7 ||
+          AT32F403AVET7 || AT32F407xx */
+
+#if defined (AT32F403Vx_HD) || defined (AT32F403Vx_XL) || \
+    defined (AT32F403Zx_HD) || defined (AT32F403Zx_XL) || \
+    defined (AT32F403Rx_HD) || defined (AT32F403Rx_XL) || \
+    defined (AT32F403Axx)   || defined (AT32F407xx)
+ #define  RCC_AHBEN_SDIO2EN                     ((uint16_t)0x0800)            /*!< SDIO2 clock enable */
+#endif
+
+#if defined (AT32F415xx)
+ #define  RCC_AHBEN_USBEN                       ((uint16_t)0x1000)            /*!< USB clock enable */
+#endif
+
+#if defined (AT32F403Axx) || defined (AT32F407xx)
+ #define  RCC_AHBEN_ETHMACEN                    ((uint16_t)0x00004000)        /*!< ETHMAC clock enable */
+ #define  RCC_AHBEN_ETHMACTXEN                  ((uint16_t)0x00008000)        /*!< ETHMACTX clock enable */
+ #define  RCC_AHBEN_ETHMACRXEN                  ((uint16_t)0x00010000)        /*!< ETHMACRX clock enable */
+ #define  RCC_AHBEN_ETHMACPTPEN                 ((uint16_t)0x10000000)        /*!< ETHMACPTP clock enable */
+#endif
+
+/******************  Bit definition for RCC_APB2EN register  *****************/
+#define  RCC_APB2EN_AFIOEN                      ((uint32_t)0x00000001)        /*!< Alternate Function I/O clock enable */
+#define  RCC_APB2EN_GPIOAEN                     ((uint32_t)0x00000004)        /*!< I/O port A clock enable */
+#define  RCC_APB2EN_GPIOBEN                     ((uint32_t)0x00000008)        /*!< I/O port B clock enable */
+#define  RCC_APB2EN_GPIOCEN                     ((uint32_t)0x00000010)        /*!< I/O port C clock enable */
+#define  RCC_APB2EN_GPIODEN                     ((uint32_t)0x00000020)        /*!< I/O port D clock enable */
+#define  RCC_APB2EN_ADC1EN                      ((uint32_t)0x00000200)        /*!< ADC 1 interface clock enable */
+#define  RCC_APB2EN_TMR1EN                      ((uint32_t)0x00000800)        /*!< TMR1 Timer clock enable */
+#define  RCC_APB2EN_SPI1EN                      ((uint32_t)0x00001000)        /*!< SPI 1 clock enable */
+#define  RCC_APB2EN_USART1EN                    ((uint32_t)0x00004000)        /*!< USART1 clock enable */
+
+#if !defined (AT32F415xx)
+ #define  RCC_APB2EN_ADC2EN                     ((uint32_t)0x00000400)        /*!< ADC 2 interface clock enable */
+#endif
+
+#if !defined (AT32F413Kx_MD) && !defined (AT32F413Kx_HD) && \
+    !defined (AT32F413Cx_MD) && !defined (AT32F413Rx_MD) && \
+    !defined (AT32FEBKCx_MD) && !defined (TS32F401CBU7)  && \
+    !defined (AT32F415xx)
+ #define  RCC_APB2EN_TMR8EN                     ((uint32_t)0x00002000)        /*!< TMR8 Timer clock enable */
+#endif
+
+#define  RCC_APB2EN_GPIOFEN                     ((uint32_t)0x00000080)        /*!< I/O port F clock enable */
+
+#if !defined (AT32FEBKCx_MD)
+ #define  RCC_APB2EN_TMR9EN                     ((uint32_t)0x00080000)        /*!< TMR9 Timer clock enable  */
+ #define  RCC_APB2EN_TMR10EN                    ((uint32_t)0x00100000)        /*!< TMR10 Timer clock enable  */
+ #define  RCC_APB2EN_TMR11EN                    ((uint32_t)0x00200000)        /*!< TMR11 Timer clock enable */
+#endif
+
+#if defined (AT32F403xx)
+ #define  RCC_APB2EN_GPIOEEN                    ((uint32_t)0x00000040)        /*!< I/O port E clock enable */
+ #define  RCC_APB2EN_GPIOGEN                    ((uint32_t)0x00000100)        /*!< I/O port G clock enable */
+ #define  RCC_APB2EN_ADC3EN                     ((uint32_t)0x00008000)        /*!< DMA1 clock enable */
+ #define  RCC_APB2EN_TMR15EN                    ((uint32_t)0x00010000)        /*!< TMR15 Timer clock enable */
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+ #define  RCC_APB2EN_GPIOEEN                    ((uint32_t)0x00000040)        /*!< I/O port E clock enable */
+ #define  RCC_APB2EN_ADC3EN                     ((uint32_t)0x00008000)        /*!< ADC3 interface clock enable */
+ #define  RCC_APB2EN_I2C3EN                     ((uint32_t)0x00800000)        /*!< I2C3 interface clock enable */
+ #define  RCC_APB2EN_USART6EN                   ((uint32_t)0x01000000)        /*!< USART6 interface clock enable */
+ #define  RCC_APB2EN_UART7EN                    ((uint32_t)0x02000000)        /*!< UART7 interface clock enable */
+ #define  RCC_APB2EN_UART8EN                    ((uint32_t)0x04000000)        /*!< UART8 interface clock enable */
+#endif
+
+#if !defined (AT32F403xx)
+ #if !defined (AT32FEBKCx_MD)
+  #define  RCC_APB2EN_ACCEN                     ((uint32_t)0x00400000)        /*!< ACC enable */
+ #endif
+#endif
+
+#if defined (AT32F415xx)
+ #define  RCC_APB2EN_EFCBEN                     ((uint32_t)0x00800000)        /*!< EFCB enable */
+#endif
+
+/*****************  Bit definition for RCC_APB1EN register  ******************/
+#define  RCC_APB1EN_TMR2EN                      ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
+#define  RCC_APB1EN_TMR3EN                      ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1EN_WWDGEN                      ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1EN_USART2EN                    ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
+#define  RCC_APB1EN_I2C1EN                      ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
+#define  RCC_APB1EN_CAN1EN                      ((uint32_t)0x02000000)        /*!< CAN1 clock enable */
+#define  RCC_APB1EN_PWREN                       ((uint32_t)0x10000000)        /*!< Power interface clock enable */
+#define  RCC_APB1EN_TMR4EN                      ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
+#define  RCC_APB1EN_SPI2EN                      ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
+#define  RCC_APB1EN_I2C2EN                      ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
+#define  RCC_APB1EN_TMR5EN                      ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
+
+#if !defined (AT32F415xx)
+ #define  RCC_APB1EN_BKPEN                      ((uint32_t)0x08000000)        /*!< Backup interface clock enable */
+ #define  RCC_APB1EN_USBEN                      ((uint32_t)0x00800000)        /*!< USB Device clock enable */
+#endif
+
+#if defined (AT32F415xx)
+ #define  RCC_APB1EN_COMPEN                     ((uint32_t)0x00000200)        /*!< Compare enable */
+#endif
+
+#if defined (AT32F403Vx_HD) || defined (AT32F403Zx_HD) || \
+    defined (AT32F403Vx_XL) || defined (AT32F403Zx_XL) || \
+    defined (AT32F403Axx)   || defined (AT32F407xx)
+ #define  RCC_APB1EN_SPI4EN                     ((uint32_t)0x00010000)        /*!< SPI 4 clock enable */
+#endif /* AT32F403Vx_HD || AT32F403Zx_HD || AT32F403Vx_XL || AT32F403Zx_XL 
+          AT32F403Axx   || AT32F407xx */
+
+#if !defined (AT32F413Kx_MD) && !defined (AT32F413Kx_HD) && \
+    !defined (AT32F415K8U7_4)&& !defined (AT32F415KBU7_4)&& \
+    !defined (AT32F415KCU7_4)
+ #define  RCC_APB1EN_USART3EN                   ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
+#endif
+
+#if !defined (AT32F413Kx_MD) && !defined (AT32F413Kx_HD) && \
+    !defined (AT32F413Cx_MD) && !defined (AT32F413Cx_HD) && \
+    !defined (AT32FEBKCx_MD) && !defined (TS32F401CBU7)  && \
+    !defined (AT32F415K8U7_4)&& !defined (AT32F415KBU7_4)&& \
+    !defined (AT32F415KCU7_4)&& !defined (AT32F415C8T7)  && \
+    !defined (AT32F415CBT7)  && !defined (AT32F415CCT7)  && \
+    !defined (AT32F415CBU7)  && !defined (AT32F415CCU7)
+ #define  RCC_APB1EN_UART4EN                    ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
+ #define  RCC_APB1EN_UART5EN                    ((uint32_t)0x00100000)        /*!< UART 5 clock enable */
+#endif
+
+#if defined (AT32F413Cx_HD) || defined (AT32F413Cx_MD) || \
+    defined (AT32F413Rx_HD) || defined (AT32F413Rx_MD) || \
+    defined (TS32F401CBU7)
+ #define  RCC_APB1EN_CAN2EN                     ((uint32_t)0x80000000)        /*!< CAN2 enable */
+#elif defined (AT32F403Axx) || defined (AT32F407xx)
+ #define  RCC_APB1EN_CAN2EN                     ((uint32_t)0x04000000)        /*!< CAN2 enable */
+#endif
+
+#if defined (AT32F403xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+ #define  RCC_APB1EN_TMR6EN                     ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+ #define  RCC_APB1EN_TMR7EN                     ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+ #define  RCC_APB1EN_SPI3EN                     ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
+ #define  RCC_APB1EN_I2C3EN                     ((uint32_t)0x04000000)        /*!< I2C 3 clock enable */
+ #define  RCC_APB1EN_TMR12EN                    ((uint32_t)0x00000040)        /*!< TMR12 Timer clock enable  */
+ #define  RCC_APB1EN_TMR13EN                    ((uint32_t)0x00000080)        /*!< TMR13 Timer clock enable  */
+ #define  RCC_APB1EN_TMR14EN                    ((uint32_t)0x00000100)        /*!< TMR14 Timer clock enable */
+ #define  RCC_APB1EN_DACEN                      ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
+#endif
+
+/*******************  Bit definition for RCC_BDC register  *******************/
+#if !defined (AT32F415xx)
+ #define  RCC_BDC_LSEEN                         ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+ #define  RCC_BDC_LSESTBL                       ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+ #define  RCC_BDC_LSEBYPS                       ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+ #define  RCC_BDC_RTCSEL                        ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+ #define  RCC_BDC_RTCSEL_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
+ #define  RCC_BDC_RTCSEL_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+ /** RTC congiguration */                       
+ #define  RCC_BDC_RTCSEL_NOCLK                  ((uint32_t)0x00000000)        /*!< No clock */
+ #define  RCC_BDC_RTCSEL_LSE                    ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+ #define  RCC_BDC_RTCSEL_LSI                    ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+ #define  RCC_BDC_RTCSEL_HSE_DIV128             ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+ #define  RCC_BDC_RTCEN                         ((uint32_t)0x00008000)        /*!< RTC clock enable */
+ #define  RCC_BDC_BDRST                         ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+#else
+ #define  RCC_BDC_LSEEN                         ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+ #define  RCC_BDC_LSESTBL                       ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+ #define  RCC_BDC_LSEBYPS                       ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+ #define  RCC_BDC_ERTCSEL                       ((uint32_t)0x00000300)        /*!< ERTCSEL[1:0] bits (ERTC clock source selection) */
+ #define  RCC_BDC_ERTCSEL_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+ #define  RCC_BDC_ERTCSEL_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+ /** ERTC congiguration */                      
+ #define  RCC_BDC_ERTCSEL_NOCLK                 ((uint32_t)0x00000000)        /*!< No clock */
+ #define  RCC_BDC_ERTCSEL_LSE                   ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as ERTC clock */
+ #define  RCC_BDC_ERTCSEL_LSI                   ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as ERTC clock */
+ #define  RCC_BDC_ERTCSEL_HSE_DIV128            ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as ERTC clock */
+
+ #define  RCC_BDC_ERTCEN                        ((uint32_t)0x00008000)        /*!< ERTC clock enable */
+ #define  RCC_BDC_BDRST                         ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+#endif
+/*******************  Bit definition for RCC_CTRLSTS register  ********************/
+#define  RCC_CTRLSTS_LSIEN                      ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CTRLSTS_LSISTBL                    ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CTRLSTS_RSTFC                      ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CTRLSTS_PINRSTF                    ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CTRLSTS_PORSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CTRLSTS_SWRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CTRLSTS_IWDGRSTF                   ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CTRLSTS_WWDGRSTF                   ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CTRLSTS_LPRSTF                     ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+/*******************  Bit definition for RCC_AHBRST register  ********************/
+#if defined (AT32F415xx)
+ #define  RCC_AHBRST_USBRST                     ((uint32_t)0x00001000)        /*!< USB reset */
+#endif /* AT32F415xx */
+
+#if defined (AT32F403Axx) || defined (AT32F407xx)
+ #define  RCC_AHBRST_ETHMACRST                  ((uint32_t)0x00004000)        /*!< ETHMAC reset */
+#endif /* AT32F43Axx || AT32F407 */
+
+/*******************  Bit definition for RCC_PLL register  ********************/
+#if defined (AT32F415xx)
+ #define  RCC_PLL_PLLFR                         ((uint32_t)0x00000007)        /*!< PLL FR Configuration Value */
+ #define  RCC_PLL_PLLFR_0                       ((uint32_t)0x00000000)        /*!< PLL FR Configuration VCO */
+ #define  RCC_PLL_PLLFR_2                       ((uint32_t)0x00000001)        /*!< PLL FR Configuration VCO/2 */
+ #define  RCC_PLL_PLLFR_4                       ((uint32_t)0x00000002)        /*!< PLL FR Configuration VCO/4 */
+ #define  RCC_PLL_PLLFR_8                       ((uint32_t)0x00000003)        /*!< PLL FR Configuration VCO/8 */
+ #define  RCC_PLL_PLLFR_16                      ((uint32_t)0x00000004)        /*!< PLL FR Configuration VCO/16 */
+ #define  RCC_PLL_PLLFR_32                      ((uint32_t)0x00000005)        /*!< PLL FR Configuration VCO/32 */
+ #define  RCC_PLL_PLLMS                         ((uint32_t)0x000000F0)        /*!< PLL MS Configuration Value */
+ #define  RCC_PLL_PLLNS                         ((uint32_t)0x0001FF00)        /*!< PLL NS Configuration Value */
+ #define  RCC_PLL_PLLFREF                       ((uint32_t)0x07000000)        /*!< PLL FREF Configuration Table */
+ #define  RCC_PLL_PLLFREF_4M                    ((uint32_t)0x00000000)        /*!< PLL FREF Configuration Table */
+ #define  RCC_PLL_PLLFREF_6M                    ((uint32_t)0x01000000)        /*!< PLL FREF Configuration Table */
+ #define  RCC_PLL_PLLFREF_8M                    ((uint32_t)0x02000000)        /*!< PLL FREF Configuration Table */
+ #define  RCC_PLL_PLLFREF_12M                   ((uint32_t)0x03000000)        /*!< PLL FREF Configuration Table */
+ #define  RCC_PLL_PLLFREF_16M                   ((uint32_t)0x04000000)        /*!< PLL FREF Configuration Table */
+ #define  RCC_PLL_PLLFREF_25M                   ((uint32_t)0x05000000)        /*!< PLL FREF Configuration Table */
+ #define  RCC_PLL_PLLCFGEN                      ((uint32_t)0x80000000)        /*!< PLL CFGEN Configuration enable */
+#endif /* AT32F415xx */
+
+/*******************  Bit definition for RCC_MISC register  ********************/
+#define  RCC_MISC_HSICAL_KEY                    ((uint32_t)0x000000FF)        /*!< HSICAL KEY */
+#define  RCC_MISC_CLKOUT_3                      ((uint32_t)0x00010000)        /*!< CLKOUT Bit 3 */
+
+#if defined (AT32F403xx) || defined (AT32F413xx)  || \
+    defined (AT32F403Axx)|| defined (AT32F407xx)
+ #define  RCC_MISC_USB768B                      ((uint32_t)0x01000000)        /*!< USB SRAM size */
+#endif /* AT32F403xx | AT32F413xx | AT32F403Axx | AT32F407xx */
+
+#if defined (AT32F413xx) || defined (AT32F403Axx) || \
+    defined (AT32F407xx)
+#define  RCC_MISC_DIV_EN                        ((uint32_t)0x20000000)        /*!< HSI48 Div 6 enable */
+#endif /* AT32F413xx | AT32F403Axx | AT32F407xx */
+
+#if !defined (AT32F403xx)
+ #define  RCC_MISC_HSI_DIV_EN                   ((uint32_t)0x02000000)        /*!< HSI DIV enable */
+ #define  RCC_MISC_MCOPRE_MASK                  ((uint32_t)0xF0000000)        /*!< MCO Divider Mask Value */
+ #define  RCC_MISC_MCOPRE_1                     ((uint32_t)0x10000000)        /*!< MCO Div 1 Configure */
+ #define  RCC_MISC_MCOPRE_2                     ((uint32_t)0x80000000)        /*!< MCO Div 2 Configure */
+ #define  RCC_MISC_MCOPRE_4                     ((uint32_t)0x90000000)        /*!< MCO Div 4 Configure */
+ #define  RCC_MISC_MCOPRE_8                     ((uint32_t)0xA0000000)        /*!< MCO Div 8 Configure */
+ #define  RCC_MISC_MCOPRE_16                    ((uint32_t)0xB0000000)        /*!< MCO Div 16 Configure */
+ #define  RCC_MISC_MCOPRE_64                    ((uint32_t)0xC0000000)        /*!< MCO Div 64 Configure */
+ #define  RCC_MISC_MCOPRE_128                   ((uint32_t)0xD0000000)        /*!< MCO Div 128 Configure */
+ #define  RCC_MISC_MCOPRE_256                   ((uint32_t)0xE0000000)        /*!< MCO Div 256 Configure */
+ #define  RCC_MISC_MCOPRE_512                   ((uint32_t)0xF0000000)        /*!< MCO Div 512 Configure */
+#endif /* !AT32F403xx */
+
+/*******************  Bit definition for RCC_TEST register  ********************/
+#define  RCC_TEST_MCO2TMR_EN                    ((uint32_t)0x00010000)        /*!< CLKOUT to TMR10 Ch 0 */
+
+/*******************  Bit definition for RCC_MISC2 register  *******************/
+#define  RCC_MISC2_AUTO_STEP_EN                 ((uint32_t)0x00000030)        /*!< Auto Step Mode */
+#define  RCC_MISC2_HSI_FOR_USB                  ((uint32_t)0x00000100)        /*!< HSI48 for USB */
+#define  RCC_MISC2_HSI_SYS_CTRL                 ((uint32_t)0x00000200)        /*!< HSI48 for SYSCLK */
+
+#define  RCC_MISC2_HSE_DIV_CTRL                 ((uint32_t)0x00003000)        /*!< HSE Div */
+#define  RCC_MISC2_HSE_DIV_CTRL_2               ((uint32_t)0x00000000)        /*!< HSE Div 2 */
+#define  RCC_MISC2_HSE_DIV_CTRL_3               ((uint32_t)0x00001000)        /*!< HSE Div 3 */
+#define  RCC_MISC2_HSE_DIV_CTRL_4               ((uint32_t)0x00002000)        /*!< HSE Div 4 */
+#define  RCC_MISC2_HSE_DIV_CTRL_5               ((uint32_t)0x00003000)        /*!< HSE Div 5 */
+
+/*****************  Bit definition for RCC_INTCTRL register  *******************/
+#define  RCC_INTCTRL_USB_INT_CTRL               ((uint32_t)0x00000001)        /*!< USB interrupt remap */
+
+/******************************************************************************/
+/*                                                                            */
+/*                General Purpose and Alternate Function I/O                  */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for GPIO_CTRLL register  *******************/
+#define  GPIO_CTRLL_MDE                         ((uint32_t)0x33333333)        /*!< Port x mode bits */
+
+#define  GPIO_CTRLL_MDE0                        ((uint32_t)0x00000003)        /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define  GPIO_CTRLL_MDE0_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  GPIO_CTRLL_MDE0_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  GPIO_CTRLL_MDE1                        ((uint32_t)0x00000030)        /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define  GPIO_CTRLL_MDE1_0                      ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  GPIO_CTRLL_MDE1_1                      ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  GPIO_CTRLL_MDE2                        ((uint32_t)0x00000300)        /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define  GPIO_CTRLL_MDE2_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  GPIO_CTRLL_MDE2_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+#define  GPIO_CTRLL_MDE3                        ((uint32_t)0x00003000)        /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define  GPIO_CTRLL_MDE3_0                      ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  GPIO_CTRLL_MDE3_1                      ((uint32_t)0x00002000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLL_MDE4                        ((uint32_t)0x00030000)        /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define  GPIO_CTRLL_MDE4_0                      ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  GPIO_CTRLL_MDE4_1                      ((uint32_t)0x00020000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLL_MDE5                        ((uint32_t)0x00300000)        /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define  GPIO_CTRLL_MDE5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  GPIO_CTRLL_MDE5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLL_MDE6                        ((uint32_t)0x03000000)        /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define  GPIO_CTRLL_MDE6_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  GPIO_CTRLL_MDE6_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLL_MDE7                        ((uint32_t)0x30000000)        /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define  GPIO_CTRLL_MDE7_0                      ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  GPIO_CTRLL_MDE7_1                      ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLL_CONF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
+
+#define  GPIO_CTRLL_CONF0                       ((uint32_t)0x0000000C)        /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define  GPIO_CTRLL_CONF0_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  GPIO_CTRLL_CONF0_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  GPIO_CTRLL_CONF1                       ((uint32_t)0x000000C0)        /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define  GPIO_CTRLL_CONF1_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  GPIO_CTRLL_CONF1_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  GPIO_CTRLL_CONF2                       ((uint32_t)0x00000C00)        /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define  GPIO_CTRLL_CONF2_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  GPIO_CTRLL_CONF2_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+
+#define  GPIO_CTRLL_CONF3                       ((uint32_t)0x0000C000)        /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define  GPIO_CTRLL_CONF3_0                     ((uint32_t)0x00004000)        /*!< Bit 0 */
+#define  GPIO_CTRLL_CONF3_1                     ((uint32_t)0x00008000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLL_CONF4                       ((uint32_t)0x000C0000)        /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define  GPIO_CTRLL_CONF4_0                     ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  GPIO_CTRLL_CONF4_1                     ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLL_CONF5                       ((uint32_t)0x00C00000)        /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define  GPIO_CTRLL_CONF5_0                     ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  GPIO_CTRLL_CONF5_1                     ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLL_CONF6                       ((uint32_t)0x0C000000)        /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define  GPIO_CTRLL_CONF6_0                     ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  GPIO_CTRLL_CONF6_1                     ((uint32_t)0x08000000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLL_CONF7                       ((uint32_t)0xC0000000)        /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define  GPIO_CTRLL_CONF7_0                     ((uint32_t)0x40000000)        /*!< Bit 0 */
+#define  GPIO_CTRLL_CONF7_1                     ((uint32_t)0x80000000)        /*!< Bit 1 */
+
+/*******************  Bit definition for GPIO_CTRLH register  *******************/
+#define  GPIO_CTRLH_MDE                         ((uint32_t)0x33333333)        /*!< Port x mode bits */
+
+#define  GPIO_CTRLH_MDE8                        ((uint32_t)0x00000003)        /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define  GPIO_CTRLH_MDE8_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  GPIO_CTRLH_MDE8_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  GPIO_CTRLH_MDE9                        ((uint32_t)0x00000030)        /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define  GPIO_CTRLH_MDE9_0                      ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  GPIO_CTRLH_MDE9_1                      ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  GPIO_CTRLH_MDE10                       ((uint32_t)0x00000300)        /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define  GPIO_CTRLH_MDE10_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  GPIO_CTRLH_MDE10_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+#define  GPIO_CTRLH_MDE11                       ((uint32_t)0x00003000)        /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define  GPIO_CTRLH_MDE11_0                     ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  GPIO_CTRLH_MDE11_1                     ((uint32_t)0x00002000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLH_MDE12                       ((uint32_t)0x00030000)        /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define  GPIO_CTRLH_MDE12_0                     ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  GPIO_CTRLH_MDE12_1                     ((uint32_t)0x00020000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLH_MDE13                       ((uint32_t)0x00300000)        /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define  GPIO_CTRLH_MDE13_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  GPIO_CTRLH_MDE13_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLH_MDE14                       ((uint32_t)0x03000000)        /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define  GPIO_CTRLH_MDE14_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  GPIO_CTRLH_MDE14_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLH_MDE15                       ((uint32_t)0x30000000)        /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define  GPIO_CTRLH_MDE15_0                     ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  GPIO_CTRLH_MDE15_1                     ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLH_CONF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
+
+#define  GPIO_CTRLH_CONF8                       ((uint32_t)0x0000000C)        /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define  GPIO_CTRLH_CONF8_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  GPIO_CTRLH_CONF8_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  GPIO_CTRLH_CONF9                       ((uint32_t)0x000000C0)        /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define  GPIO_CTRLH_CONF9_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  GPIO_CTRLH_CONF9_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  GPIO_CTRLH_CONF10                      ((uint32_t)0x00000C00)        /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define  GPIO_CTRLH_CONF10_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  GPIO_CTRLH_CONF10_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
+
+#define  GPIO_CTRLH_CONF11                      ((uint32_t)0x0000C000)        /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define  GPIO_CTRLH_CONF11_0                    ((uint32_t)0x00004000)        /*!< Bit 0 */
+#define  GPIO_CTRLH_CONF11_1                    ((uint32_t)0x00008000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLH_CONF12                      ((uint32_t)0x000C0000)        /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define  GPIO_CTRLH_CONF12_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  GPIO_CTRLH_CONF12_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLH_CONF13                      ((uint32_t)0x00C00000)        /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define  GPIO_CTRLH_CONF13_0                    ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  GPIO_CTRLH_CONF13_1                    ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLH_CONF14                      ((uint32_t)0x0C000000)        /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define  GPIO_CTRLH_CONF14_0                    ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  GPIO_CTRLH_CONF14_1                    ((uint32_t)0x08000000)        /*!< Bit 1 */
+
+#define  GPIO_CTRLH_CONF15                      ((uint32_t)0xC0000000)        /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define  GPIO_CTRLH_CONF15_0                    ((uint32_t)0x40000000)        /*!< Bit 0 */
+#define  GPIO_CTRLH_CONF15_1                    ((uint32_t)0x80000000)        /*!< Bit 1 */
+
+/********************  Bit definition for GPIO_IPTDT register  *******************/
+#define GPIO_IPTDT_IPTDT0                       ((uint16_t)0x0001)            /*!< Port input data, bit 0 */
+#define GPIO_IPTDT_IPTDT1                       ((uint16_t)0x0002)            /*!< Port input data, bit 1 */
+#define GPIO_IPTDT_IPTDT2                       ((uint16_t)0x0004)            /*!< Port input data, bit 2 */
+#define GPIO_IPTDT_IPTDT3                       ((uint16_t)0x0008)            /*!< Port input data, bit 3 */
+#define GPIO_IPTDT_IPTDT4                       ((uint16_t)0x0010)            /*!< Port input data, bit 4 */
+#define GPIO_IPTDT_IPTDT5                       ((uint16_t)0x0020)            /*!< Port input data, bit 5 */
+#define GPIO_IPTDT_IPTDT6                       ((uint16_t)0x0040)            /*!< Port input data, bit 6 */
+#define GPIO_IPTDT_IPTDT7                       ((uint16_t)0x0080)            /*!< Port input data, bit 7 */
+#define GPIO_IPTDT_IPTDT8                       ((uint16_t)0x0100)            /*!< Port input data, bit 8 */
+#define GPIO_IPTDT_IPTDT9                       ((uint16_t)0x0200)            /*!< Port input data, bit 9 */
+#define GPIO_IPTDT_IPTDT10                      ((uint16_t)0x0400)            /*!< Port input data, bit 10 */
+#define GPIO_IPTDT_IPTDT11                      ((uint16_t)0x0800)            /*!< Port input data, bit 11 */
+#define GPIO_IPTDT_IPTDT12                      ((uint16_t)0x1000)            /*!< Port input data, bit 12 */
+#define GPIO_IPTDT_IPTDT13                      ((uint16_t)0x2000)            /*!< Port input data, bit 13 */
+#define GPIO_IPTDT_IPTDT14                      ((uint16_t)0x4000)            /*!< Port input data, bit 14 */
+#define GPIO_IPTDT_IPTDT15                      ((uint16_t)0x8000)            /*!< Port input data, bit 15 */
+
+/*******************  Bit definition for GPIO_OPTDT register  *******************/
+#define GPIO_OPTDT_OPTDT0                       ((uint16_t)0x0001)            /*!< Port output data, bit 0 */
+#define GPIO_OPTDT_OPTDT1                       ((uint16_t)0x0002)            /*!< Port output data, bit 1 */
+#define GPIO_OPTDT_OPTDT2                       ((uint16_t)0x0004)            /*!< Port output data, bit 2 */
+#define GPIO_OPTDT_OPTDT3                       ((uint16_t)0x0008)            /*!< Port output data, bit 3 */
+#define GPIO_OPTDT_OPTDT4                       ((uint16_t)0x0010)            /*!< Port output data, bit 4 */
+#define GPIO_OPTDT_OPTDT5                       ((uint16_t)0x0020)            /*!< Port output data, bit 5 */
+#define GPIO_OPTDT_OPTDT6                       ((uint16_t)0x0040)            /*!< Port output data, bit 6 */
+#define GPIO_OPTDT_OPTDT7                       ((uint16_t)0x0080)            /*!< Port output data, bit 7 */
+#define GPIO_OPTDT_OPTDT8                       ((uint16_t)0x0100)            /*!< Port output data, bit 8 */
+#define GPIO_OPTDT_OPTDT9                       ((uint16_t)0x0200)            /*!< Port output data, bit 9 */
+#define GPIO_OPTDT_OPTDT10                      ((uint16_t)0x0400)            /*!< Port output data, bit 10 */
+#define GPIO_OPTDT_OPTDT11                      ((uint16_t)0x0800)            /*!< Port output data, bit 11 */
+#define GPIO_OPTDT_OPTDT12                      ((uint16_t)0x1000)            /*!< Port output data, bit 12 */
+#define GPIO_OPTDT_OPTDT13                      ((uint16_t)0x2000)            /*!< Port output data, bit 13 */
+#define GPIO_OPTDT_OPTDT14                      ((uint16_t)0x4000)            /*!< Port output data, bit 14 */
+#define GPIO_OPTDT_OPTDT15                      ((uint16_t)0x8000)            /*!< Port output data, bit 15 */
+
+/******************  Bit definition for GPIO_BSRE register  *******************/
+#define GPIO_BSRE_BST0                          ((uint32_t)0x00000001)        /*!< Port x Set bit 0 */
+#define GPIO_BSRE_BST1                          ((uint32_t)0x00000002)        /*!< Port x Set bit 1 */
+#define GPIO_BSRE_BST2                          ((uint32_t)0x00000004)        /*!< Port x Set bit 2 */
+#define GPIO_BSRE_BST3                          ((uint32_t)0x00000008)        /*!< Port x Set bit 3 */
+#define GPIO_BSRE_BST4                          ((uint32_t)0x00000010)        /*!< Port x Set bit 4 */
+#define GPIO_BSRE_BST5                          ((uint32_t)0x00000020)        /*!< Port x Set bit 5 */
+#define GPIO_BSRE_BST6                          ((uint32_t)0x00000040)        /*!< Port x Set bit 6 */
+#define GPIO_BSRE_BST7                          ((uint32_t)0x00000080)        /*!< Port x Set bit 7 */
+#define GPIO_BSRE_BST8                          ((uint32_t)0x00000100)        /*!< Port x Set bit 8 */
+#define GPIO_BSRE_BST9                          ((uint32_t)0x00000200)        /*!< Port x Set bit 9 */
+#define GPIO_BSRE_BST10                         ((uint32_t)0x00000400)        /*!< Port x Set bit 10 */
+#define GPIO_BSRE_BST11                         ((uint32_t)0x00000800)        /*!< Port x Set bit 11 */
+#define GPIO_BSRE_BST12                         ((uint32_t)0x00001000)        /*!< Port x Set bit 12 */
+#define GPIO_BSRE_BST13                         ((uint32_t)0x00002000)        /*!< Port x Set bit 13 */
+#define GPIO_BSRE_BST14                         ((uint32_t)0x00004000)        /*!< Port x Set bit 14 */
+#define GPIO_BSRE_BST15                         ((uint32_t)0x00008000)        /*!< Port x Set bit 15 */
+
+#define GPIO_BSRE_BRE0                          ((uint32_t)0x00010000)        /*!< Port x Reset bit 0 */
+#define GPIO_BSRE_BRE1                          ((uint32_t)0x00020000)        /*!< Port x Reset bit 1 */
+#define GPIO_BSRE_BRE2                          ((uint32_t)0x00040000)        /*!< Port x Reset bit 2 */
+#define GPIO_BSRE_BRE3                          ((uint32_t)0x00080000)        /*!< Port x Reset bit 3 */
+#define GPIO_BSRE_BRE4                          ((uint32_t)0x00100000)        /*!< Port x Reset bit 4 */
+#define GPIO_BSRE_BRE5                          ((uint32_t)0x00200000)        /*!< Port x Reset bit 5 */
+#define GPIO_BSRE_BRE6                          ((uint32_t)0x00400000)        /*!< Port x Reset bit 6 */
+#define GPIO_BSRE_BRE7                          ((uint32_t)0x00800000)        /*!< Port x Reset bit 7 */
+#define GPIO_BSRE_BRE8                          ((uint32_t)0x01000000)        /*!< Port x Reset bit 8 */
+#define GPIO_BSRE_BRE9                          ((uint32_t)0x02000000)        /*!< Port x Reset bit 9 */
+#define GPIO_BSRE_BRE10                         ((uint32_t)0x04000000)        /*!< Port x Reset bit 10 */
+#define GPIO_BSRE_BRE11                         ((uint32_t)0x08000000)        /*!< Port x Reset bit 11 */
+#define GPIO_BSRE_BRE12                         ((uint32_t)0x10000000)        /*!< Port x Reset bit 12 */
+#define GPIO_BSRE_BRE13                         ((uint32_t)0x20000000)        /*!< Port x Reset bit 13 */
+#define GPIO_BSRE_BRE14                         ((uint32_t)0x40000000)        /*!< Port x Reset bit 14 */
+#define GPIO_BSRE_BRE15                         ((uint32_t)0x80000000)        /*!< Port x Reset bit 15 */
+
+/*******************  Bit definition for GPIO_BRE register  *******************/
+#define GPIO_BRE_BRE0                           ((uint16_t)0x0001)            /*!< Port x Reset bit 0 */
+#define GPIO_BRE_BRE1                           ((uint16_t)0x0002)            /*!< Port x Reset bit 1 */
+#define GPIO_BRE_BRE2                           ((uint16_t)0x0004)            /*!< Port x Reset bit 2 */
+#define GPIO_BRE_BRE3                           ((uint16_t)0x0008)            /*!< Port x Reset bit 3 */
+#define GPIO_BRE_BRE4                           ((uint16_t)0x0010)            /*!< Port x Reset bit 4 */
+#define GPIO_BRE_BRE5                           ((uint16_t)0x0020)            /*!< Port x Reset bit 5 */
+#define GPIO_BRE_BRE6                           ((uint16_t)0x0040)            /*!< Port x Reset bit 6 */
+#define GPIO_BRE_BRE7                           ((uint16_t)0x0080)            /*!< Port x Reset bit 7 */
+#define GPIO_BRE_BRE8                           ((uint16_t)0x0100)            /*!< Port x Reset bit 8 */
+#define GPIO_BRE_BRE9                           ((uint16_t)0x0200)            /*!< Port x Reset bit 9 */
+#define GPIO_BRE_BRE10                          ((uint16_t)0x0400)            /*!< Port x Reset bit 10 */
+#define GPIO_BRE_BRE11                          ((uint16_t)0x0800)            /*!< Port x Reset bit 11 */
+#define GPIO_BRE_BRE12                          ((uint16_t)0x1000)            /*!< Port x Reset bit 12 */
+#define GPIO_BRE_BRE13                          ((uint16_t)0x2000)            /*!< Port x Reset bit 13 */
+#define GPIO_BRE_BRE14                          ((uint16_t)0x4000)            /*!< Port x Reset bit 14 */
+#define GPIO_BRE_BRE15                          ((uint16_t)0x8000)            /*!< Port x Reset bit 15 */
+
+/******************  Bit definition for GPIO_LOCK register  *******************/
+#define GPIO_LOCK_LOCK0                         ((uint32_t)0x00000001)        /*!< Port x Lock bit 0 */
+#define GPIO_LOCK_LOCK1                         ((uint32_t)0x00000002)        /*!< Port x Lock bit 1 */
+#define GPIO_LOCK_LOCK2                         ((uint32_t)0x00000004)        /*!< Port x Lock bit 2 */
+#define GPIO_LOCK_LOCK3                         ((uint32_t)0x00000008)        /*!< Port x Lock bit 3 */
+#define GPIO_LOCK_LOCK4                         ((uint32_t)0x00000010)        /*!< Port x Lock bit 4 */
+#define GPIO_LOCK_LOCK5                         ((uint32_t)0x00000020)        /*!< Port x Lock bit 5 */
+#define GPIO_LOCK_LOCK6                         ((uint32_t)0x00000040)        /*!< Port x Lock bit 6 */
+#define GPIO_LOCK_LOCK7                         ((uint32_t)0x00000080)        /*!< Port x Lock bit 7 */
+#define GPIO_LOCK_LOCK8                         ((uint32_t)0x00000100)        /*!< Port x Lock bit 8 */
+#define GPIO_LOCK_LOCK9                         ((uint32_t)0x00000200)        /*!< Port x Lock bit 9 */
+#define GPIO_LOCK_LOCK10                        ((uint32_t)0x00000400)        /*!< Port x Lock bit 10 */
+#define GPIO_LOCK_LOCK11                        ((uint32_t)0x00000800)        /*!< Port x Lock bit 11 */
+#define GPIO_LOCK_LOCK12                        ((uint32_t)0x00001000)        /*!< Port x Lock bit 12 */
+#define GPIO_LOCK_LOCK13                        ((uint32_t)0x00002000)        /*!< Port x Lock bit 13 */
+#define GPIO_LOCK_LOCK14                        ((uint32_t)0x00004000)        /*!< Port x Lock bit 14 */
+#define GPIO_LOCK_LOCK15                        ((uint32_t)0x00008000)        /*!< Port x Lock bit 15 */
+#define GPIO_LOCK_LOCKK                         ((uint32_t)0x00010000)        /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for AFIO_EVCTRL register  *******************/
+#define AFIO_EVCTRL_PIN                         ((uint8_t)0x0F)               /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCTRL_PIN_B0                      ((uint8_t)0x01)               /*!< Bit 0 */
+#define AFIO_EVCTRL_PIN_B1                      ((uint8_t)0x02)               /*!< Bit 1 */
+#define AFIO_EVCTRL_PIN_B2                      ((uint8_t)0x04)               /*!< Bit 2 */
+#define AFIO_EVCTRL_PIN_B3                      ((uint8_t)0x08)               /*!< Bit 3 */
+
+/** PIN configuration */
+#define AFIO_EVCTRL_PIN_PN0                     ((uint8_t)0x00)               /*!< Pin 0 selected */
+#define AFIO_EVCTRL_PIN_PN1                     ((uint8_t)0x01)               /*!< Pin 1 selected */
+#define AFIO_EVCTRL_PIN_PN2                     ((uint8_t)0x02)               /*!< Pin 2 selected */
+#define AFIO_EVCTRL_PIN_PN3                     ((uint8_t)0x03)               /*!< Pin 3 selected */
+#define AFIO_EVCTRL_PIN_PN4                     ((uint8_t)0x04)               /*!< Pin 4 selected */
+#define AFIO_EVCTRL_PIN_PN5                     ((uint8_t)0x05)               /*!< Pin 5 selected */
+#define AFIO_EVCTRL_PIN_PN6                     ((uint8_t)0x06)               /*!< Pin 6 selected */
+#define AFIO_EVCTRL_PIN_PN7                     ((uint8_t)0x07)               /*!< Pin 7 selected */
+#define AFIO_EVCTRL_PIN_PN8                     ((uint8_t)0x08)               /*!< Pin 8 selected */
+#define AFIO_EVCTRL_PIN_PN9                     ((uint8_t)0x09)               /*!< Pin 9 selected */
+#define AFIO_EVCTRL_PIN_PN10                    ((uint8_t)0x0A)               /*!< Pin 10 selected */
+#define AFIO_EVCTRL_PIN_PN11                    ((uint8_t)0x0B)               /*!< Pin 11 selected */
+#define AFIO_EVCTRL_PIN_PN12                    ((uint8_t)0x0C)               /*!< Pin 12 selected */
+#define AFIO_EVCTRL_PIN_PN13                    ((uint8_t)0x0D)               /*!< Pin 13 selected */
+#define AFIO_EVCTRL_PIN_PN14                    ((uint8_t)0x0E)               /*!< Pin 14 selected */
+#define AFIO_EVCTRL_PIN_PN15                    ((uint8_t)0x0F)               /*!< Pin 15 selected */
+
+#define AFIO_EVCTRL_PORT                        ((uint8_t)0x70)               /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCTRL_PORT_B0                     ((uint8_t)0x10)               /*!< Bit 0 */
+#define AFIO_EVCTRL_PORT_B1                     ((uint8_t)0x20)               /*!< Bit 1 */
+#define AFIO_EVCTRL_PORT_B2                     ((uint8_t)0x40)               /*!< Bit 2 */
+
+/** PORT configuration */
+#define AFIO_EVCTRL_PORT_PTA                    ((uint8_t)0x00)               /*!< Port A selected */
+#define AFIO_EVCTRL_PORT_PTB                    ((uint8_t)0x10)               /*!< Port B selected */
+#define AFIO_EVCTRL_PORT_PTC                    ((uint8_t)0x20)               /*!< Port C selected */
+#define AFIO_EVCTRL_PORT_PTD                    ((uint8_t)0x30)               /*!< Port D selected */
+#define AFIO_EVCTRL_PORT_PTE                    ((uint8_t)0x40)               /*!< Port E selected */
+
+#define AFIO_EVCTRL_EVOEN                       ((uint8_t)0x80)               /*!< Event Output Enable */
+
+/******************  Bit definition for AFIO_MAP register  *******************/
+#define AFIO_MAP_SPI1_REMAP                     ((uint32_t)0x00000001)        /*!< SPI1 remapping */
+#define AFIO_MAP_I2C1_REMAP                     ((uint32_t)0x00000002)        /*!< I2C1 remapping */
+#define AFIO_MAP_USART1_REMAP                   ((uint32_t)0x00000004)        /*!< USART1 remapping */
+#define AFIO_MAP_USART2_REMAP                   ((uint32_t)0x00000008)        /*!< USART2 remapping */
+
+#define AFIO_MAP_USART3_REMAP                   ((uint32_t)0x00000030)        /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAP_USART3_REMAP_B0                ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define AFIO_MAP_USART3_REMAP_B1                ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+/** USART3_REMAP configuration */
+#define AFIO_MAP_USART3_REMAP_NONEREMAP         ((uint32_t)0x00000000)        /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAP_USART3_REMAP_PARTIALREMAP      ((uint32_t)0x00000010)        /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAP_USART3_REMAP_FULLREMAP         ((uint32_t)0x00000030)        /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAP_TMR1_REMAP                     ((uint32_t)0x000000C0)        /*!< TMR1_REMAP[1:0] bits (TMR1 remapping) */
+#define AFIO_MAP_TMR1_REMAP_B0                  ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define AFIO_MAP_TMR1_REMAP_B1                  ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+/** TMR1_REMAP configuration */
+#define AFIO_MAP_TMR1_REMAP_NONEREMAP           ((uint32_t)0x00000000)        /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAP_TMR1_REMAP_PARTIALREMAP        ((uint32_t)0x00000040)        /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAP_TMR1_REMAP_FULLREMAP           ((uint32_t)0x000000C0)        /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAP_TMR2_REMAP                     ((uint32_t)0x00000300)        /*!< TMR2_REMAP[1:0] bits (TMR2 remapping) */
+#define AFIO_MAP_TMR2_REMAP_B0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define AFIO_MAP_TMR2_REMAP_B1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/** TMR2_REMAP configuration */
+#define AFIO_MAP_TMR2_REMAP_NONEREMAP           ((uint32_t)0x00000000)        /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAP_TMR2_REMAP_PARTIALREMAP1       ((uint32_t)0x00000100)        /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAP_TMR2_REMAP_PARTIALREMAP2       ((uint32_t)0x00000200)        /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAP_TMR2_REMAP_FULLREMAP           ((uint32_t)0x00000300)        /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAP_TMR3_REMAP                     ((uint32_t)0x00000C00)        /*!< TMR3_REMAP[1:0] bits (TMR3 remapping) */
+#define AFIO_MAP_TMR3_REMAP_B0                  ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define AFIO_MAP_TMR3_REMAP_B1                  ((uint32_t)0x00000800)        /*!< Bit 1 */
+
+/** TMR3_REMAP configuration */
+#define AFIO_MAP_TMR3_REMAP_NONEREMAP           ((uint32_t)0x00000000)        /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAP_TMR3_REMAP_PARTIALREMAP        ((uint32_t)0x00000800)        /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAP_TMR3_REMAP_FULLREMAP           ((uint32_t)0x00000C00)        /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAP_TMR4_REMAP                     ((uint32_t)0x00001000)        /*!< TMR4_REMAP bit (TMR4 remapping) */
+
+#define AFIO_MAP_CAN_REMAP                      ((uint32_t)0x00006000)        /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAP_CAN_REMAP_B0                   ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define AFIO_MAP_CAN_REMAP_B1                   ((uint32_t)0x00004000)        /*!< Bit 1 */
+
+/** CAN_REMAP configuration */
+#define AFIO_MAP_CAN_REMAP_RE1                  ((uint32_t)0x00000000)        /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAP_CAN_REMAP_RE2                  ((uint32_t)0x00004000)        /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAP_CAN_REMAP_RE3                  ((uint32_t)0x00006000)        /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAP_PTD01_REMAP                    ((uint32_t)0x00008000)        /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAP_TMR5CH4_INTLRE                 ((uint32_t)0x00010000)        /*!< TMR5 Channel4 Internal Remap */
+#define AFIO_MAP_ADC1_EXTRGINJ_REMAP            ((uint32_t)0x00020000)        /*!< ADC 1 External Trigger Injected Conversion remapping */
+#define AFIO_MAP_ADC1_EXTRGREG_REMAP            ((uint32_t)0x00040000)        /*!< ADC 1 External Trigger Regular Conversion remapping */
+#define AFIO_MAP_ADC2_EXTRGINJ_REMAP            ((uint32_t)0x00080000)        /*!< ADC 2 External Trigger Injected Conversion remapping */
+#define AFIO_MAP_ADC2_EXTRGREG_REMAP            ((uint32_t)0x00100000)        /*!< ADC 2 External Trigger Regular Conversion remapping */
+
+/** SWJ_CFG configuration */
+#define AFIO_MAP_SWJTAG_CONF                    ((uint32_t)0x07000000)        /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAP_SWJTAG_CONF_B0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define AFIO_MAP_SWJTAG_CONF_B1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define AFIO_MAP_SWJTAG_CONF_B2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define AFIO_MAP_SWJTAG_CONF_FULL               ((uint32_t)0x00000000)        /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAP_SWJTAG_CONF_NOJNTRST           ((uint32_t)0x01000000)        /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAP_SWJTAG_CONF_JTAGDISABLE        ((uint32_t)0x02000000)        /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAP_SWJTAG_CONF_ALLDISABLE         ((uint32_t)0x04000000)        /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+/*****************  Bit definition for AFIO_EXTIC1 register  *****************/
+#define AFIO_EXTIC1_EXTINT0                     ((uint16_t)0x000F)            /*!< EXTI 0 configuration */
+#define AFIO_EXTIC1_EXTINT1                     ((uint16_t)0x00F0)            /*!< EXTI 1 configuration */
+#define AFIO_EXTIC1_EXTINT2                     ((uint16_t)0x0F00)            /*!< EXTI 2 configuration */
+#define AFIO_EXTIC1_EXTINT3                     ((uint16_t)0xF000)            /*!< EXTI 3 configuration */
+
+/** EXTI0 configuration */
+#define AFIO_EXTIC1_EXTINT0_PTA                 ((uint16_t)0x0000)            /*!< PA[0] pin */
+#define AFIO_EXTIC1_EXTINT0_PTB                 ((uint16_t)0x0001)            /*!< PB[0] pin */
+#define AFIO_EXTIC1_EXTINT0_PTC                 ((uint16_t)0x0002)            /*!< PC[0] pin */
+#define AFIO_EXTIC1_EXTINT0_PTD                 ((uint16_t)0x0003)            /*!< PD[0] pin */
+#define AFIO_EXTIC1_EXTINT0_PTE                 ((uint16_t)0x0004)            /*!< PE[0] pin */
+#define AFIO_EXTIC1_EXTINT0_PTF                 ((uint16_t)0x0005)            /*!< PF[0] pin */
+#define AFIO_EXTIC1_EXTINT0_PTG                 ((uint16_t)0x0006)            /*!< PG[0] pin */
+
+/** EXTI1 configuration */
+#define AFIO_EXTIC1_EXTINT1_PTA                 ((uint16_t)0x0000)            /*!< PA[1] pin */
+#define AFIO_EXTIC1_EXTINT1_PTB                 ((uint16_t)0x0010)            /*!< PB[1] pin */
+#define AFIO_EXTIC1_EXTINT1_PTC                 ((uint16_t)0x0020)            /*!< PC[1] pin */
+#define AFIO_EXTIC1_EXTINT1_PTD                 ((uint16_t)0x0030)            /*!< PD[1] pin */
+#define AFIO_EXTIC1_EXTINT1_PTE                 ((uint16_t)0x0040)            /*!< PE[1] pin */
+#define AFIO_EXTIC1_EXTINT1_PTF                 ((uint16_t)0x0050)            /*!< PF[1] pin */
+#define AFIO_EXTIC1_EXTINT1_PTG                 ((uint16_t)0x0060)            /*!< PG[1] pin */
+
+/** EXTI2 configuration */
+#define AFIO_EXTIC1_EXTINT2_PTA                 ((uint16_t)0x0000)            /*!< PA[2] pin */
+#define AFIO_EXTIC1_EXTINT2_PTB                 ((uint16_t)0x0100)            /*!< PB[2] pin */
+#define AFIO_EXTIC1_EXTINT2_PTC                 ((uint16_t)0x0200)            /*!< PC[2] pin */
+#define AFIO_EXTIC1_EXTINT2_PTD                 ((uint16_t)0x0300)            /*!< PD[2] pin */
+#define AFIO_EXTIC1_EXTINT2_PTE                 ((uint16_t)0x0400)            /*!< PE[2] pin */
+#define AFIO_EXTIC1_EXTINT2_PTF                 ((uint16_t)0x0500)            /*!< PF[2] pin */
+#define AFIO_EXTIC1_EXTINT2_PTG                 ((uint16_t)0x0600)            /*!< PG[2] pin */
+
+/** EXTI3 configuration */
+#define AFIO_EXTIC1_EXTINT3_PTA                 ((uint16_t)0x0000)            /*!< PA[3] pin */
+#define AFIO_EXTIC1_EXTINT3_PTB                 ((uint16_t)0x1000)            /*!< PB[3] pin */
+#define AFIO_EXTIC1_EXTINT3_PTC                 ((uint16_t)0x2000)            /*!< PC[3] pin */
+#define AFIO_EXTIC1_EXTINT3_PTD                 ((uint16_t)0x3000)            /*!< PD[3] pin */
+#define AFIO_EXTIC1_EXTINT3_PTE                 ((uint16_t)0x4000)            /*!< PE[3] pin */
+#define AFIO_EXTIC1_EXTINT3_PTF                 ((uint16_t)0x5000)            /*!< PF[3] pin */
+#define AFIO_EXTIC1_EXTINT3_PTG                 ((uint16_t)0x6000)            /*!< PG[3] pin */
+
+/*****************  Bit definition for AFIO_EXTIC2 register  *****************/
+#define AFIO_EXTIC2_EXTINT4                     ((uint16_t)0x000F)            /*!< EXTI 4 configuration */
+#define AFIO_EXTIC2_EXTINT5                     ((uint16_t)0x00F0)            /*!< EXTI 5 configuration */
+#define AFIO_EXTIC2_EXTINT6                     ((uint16_t)0x0F00)            /*!< EXTI 6 configuration */
+#define AFIO_EXTIC2_EXTINT7                     ((uint16_t)0xF000)            /*!< EXTI 7 configuration */
+
+/** EXTI4 configuration */
+#define AFIO_EXTIC2_EXTINT4_PTA                 ((uint16_t)0x0000)            /*!< PA[4] pin */
+#define AFIO_EXTIC2_EXTINT4_PTB                 ((uint16_t)0x0001)            /*!< PB[4] pin */
+#define AFIO_EXTIC2_EXTINT4_PTC                 ((uint16_t)0x0002)            /*!< PC[4] pin */
+#define AFIO_EXTIC2_EXTINT4_PTD                 ((uint16_t)0x0003)            /*!< PD[4] pin */
+#define AFIO_EXTIC2_EXTINT4_PTE                 ((uint16_t)0x0004)            /*!< PE[4] pin */
+#define AFIO_EXTIC2_EXTINT4_PTF                 ((uint16_t)0x0005)            /*!< PF[4] pin */
+#define AFIO_EXTIC2_EXTINT4_PTG                 ((uint16_t)0x0006)            /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTIC2_EXTINT5_PTA                 ((uint16_t)0x0000)            /*!< PA[5] pin */
+#define AFIO_EXTIC2_EXTINT5_PTB                 ((uint16_t)0x0010)            /*!< PB[5] pin */
+#define AFIO_EXTIC2_EXTINT5_PTC                 ((uint16_t)0x0020)            /*!< PC[5] pin */
+#define AFIO_EXTIC2_EXTINT5_PTD                 ((uint16_t)0x0030)            /*!< PD[5] pin */
+#define AFIO_EXTIC2_EXTINT5_PTE                 ((uint16_t)0x0040)            /*!< PE[5] pin */
+#define AFIO_EXTIC2_EXTINT5_PTF                 ((uint16_t)0x0050)            /*!< PF[5] pin */
+#define AFIO_EXTIC2_EXTINT5_PTG                 ((uint16_t)0x0060)            /*!< PG[5] pin */
+
+/** EXTI6 configuration */
+#define AFIO_EXTIC2_EXTINT6_PTA                 ((uint16_t)0x0000)            /*!< PA[6] pin */
+#define AFIO_EXTIC2_EXTINT6_PTB                 ((uint16_t)0x0100)            /*!< PB[6] pin */
+#define AFIO_EXTIC2_EXTINT6_PTC                 ((uint16_t)0x0200)            /*!< PC[6] pin */
+#define AFIO_EXTIC2_EXTINT6_PTD                 ((uint16_t)0x0300)            /*!< PD[6] pin */
+#define AFIO_EXTIC2_EXTINT6_PTE                 ((uint16_t)0x0400)            /*!< PE[6] pin */
+#define AFIO_EXTIC2_EXTINT6_PTF                 ((uint16_t)0x0500)            /*!< PF[6] pin */
+#define AFIO_EXTIC2_EXTINT6_PTG                 ((uint16_t)0x0600)            /*!< PG[6] pin */
+
+/** EXTI7 configuration */
+#define AFIO_EXTIC2_EXTINT7_PTA                 ((uint16_t)0x0000)            /*!< PA[7] pin */
+#define AFIO_EXTIC2_EXTINT7_PTB                 ((uint16_t)0x1000)            /*!< PB[7] pin */
+#define AFIO_EXTIC2_EXTINT7_PTC                 ((uint16_t)0x2000)            /*!< PC[7] pin */
+#define AFIO_EXTIC2_EXTINT7_PTD                 ((uint16_t)0x3000)            /*!< PD[7] pin */
+#define AFIO_EXTIC2_EXTINT7_PTE                 ((uint16_t)0x4000)            /*!< PE[7] pin */
+#define AFIO_EXTIC2_EXTINT7_PTF                 ((uint16_t)0x5000)            /*!< PF[7] pin */
+#define AFIO_EXTIC2_EXTINT7_PTG                 ((uint16_t)0x6000)            /*!< PG[7] pin */
+
+/*****************  Bit definition for AFIO_EXTIC3 register  *****************/
+#define AFIO_EXTIC3_EXTINT8                     ((uint16_t)0x000F)            /*!< EXTI 8 configuration */
+#define AFIO_EXTIC3_EXTINT9                     ((uint16_t)0x00F0)            /*!< EXTI 9 configuration */
+#define AFIO_EXTIC3_EXTINT10                    ((uint16_t)0x0F00)            /*!< EXTI 10 configuration */
+#define AFIO_EXTIC3_EXTINT11                    ((uint16_t)0xF000)            /*!< EXTI 11 configuration */
+
+/** EXTI8 configuration */
+#define AFIO_EXTIC3_EXTINT8_PTA                 ((uint16_t)0x0000)            /*!< PA[8] pin */
+#define AFIO_EXTIC3_EXTINT8_PTB                 ((uint16_t)0x0001)            /*!< PB[8] pin */
+#define AFIO_EXTIC3_EXTINT8_PTC                 ((uint16_t)0x0002)            /*!< PC[8] pin */
+#define AFIO_EXTIC3_EXTINT8_PTD                 ((uint16_t)0x0003)            /*!< PD[8] pin */
+#define AFIO_EXTIC3_EXTINT8_PTE                 ((uint16_t)0x0004)            /*!< PE[8] pin */
+#define AFIO_EXTIC3_EXTINT8_PTF                 ((uint16_t)0x0005)            /*!< PF[8] pin */
+#define AFIO_EXTIC3_EXTINT8_PTG                 ((uint16_t)0x0006)            /*!< PG[8] pin */
+
+/** EXTI9 configuration */
+#define AFIO_EXTIC3_EXTINT9_PTA                 ((uint16_t)0x0000)            /*!< PA[9] pin */
+#define AFIO_EXTIC3_EXTINT9_PTB                 ((uint16_t)0x0010)            /*!< PB[9] pin */
+#define AFIO_EXTIC3_EXTINT9_PTC                 ((uint16_t)0x0020)            /*!< PC[9] pin */
+#define AFIO_EXTIC3_EXTINT9_PTD                 ((uint16_t)0x0030)            /*!< PD[9] pin */
+#define AFIO_EXTIC3_EXTINT9_PTE                 ((uint16_t)0x0040)            /*!< PE[9] pin */
+#define AFIO_EXTIC3_EXTINT9_PTF                 ((uint16_t)0x0050)            /*!< PF[9] pin */
+#define AFIO_EXTIC3_EXTINT9_PTG                 ((uint16_t)0x0060)            /*!< PG[9] pin */
+
+/** EXTI10 configuration */
+#define AFIO_EXTIC3_EXTINT10_PTA                ((uint16_t)0x0000)            /*!< PA[10] pin */
+#define AFIO_EXTIC3_EXTINT10_PTB                ((uint16_t)0x0100)            /*!< PB[10] pin */
+#define AFIO_EXTIC3_EXTINT10_PTC                ((uint16_t)0x0200)            /*!< PC[10] pin */
+#define AFIO_EXTIC3_EXTINT10_PTD                ((uint16_t)0x0300)            /*!< PD[10] pin */
+#define AFIO_EXTIC3_EXTINT10_PTE                ((uint16_t)0x0400)            /*!< PE[10] pin */
+#define AFIO_EXTIC3_EXTINT10_PTF                ((uint16_t)0x0500)            /*!< PF[10] pin */
+#define AFIO_EXTIC3_EXTINT10_PTG                ((uint16_t)0x0600)            /*!< PG[10] pin */
+
+/** EXTI11 configuration */
+#define AFIO_EXTIC3_EXTINT11_PTA                ((uint16_t)0x0000)            /*!< PA[11] pin */
+#define AFIO_EXTIC3_EXTINT11_PTB                ((uint16_t)0x1000)            /*!< PB[11] pin */
+#define AFIO_EXTIC3_EXTINT11_PTC                ((uint16_t)0x2000)            /*!< PC[11] pin */
+#define AFIO_EXTIC3_EXTINT11_PTD                ((uint16_t)0x3000)            /*!< PD[11] pin */
+#define AFIO_EXTIC3_EXTINT11_PTE                ((uint16_t)0x4000)            /*!< PE[11] pin */
+#define AFIO_EXTIC3_EXTINT11_PTF                ((uint16_t)0x5000)            /*!< PF[11] pin */
+#define AFIO_EXTIC3_EXTINT11_PTG                ((uint16_t)0x6000)            /*!< PG[11] pin */
+
+/*****************  Bit definition for AFIO_EXTIC4 register  *****************/
+#define AFIO_EXTIC4_EXTINT12                    ((uint16_t)0x000F)            /*!< EXTI 12 configuration */
+#define AFIO_EXTIC4_EXTINT13                    ((uint16_t)0x00F0)            /*!< EXTI 13 configuration */
+#define AFIO_EXTIC4_EXTINT14                    ((uint16_t)0x0F00)            /*!< EXTI 14 configuration */
+#define AFIO_EXTIC4_EXTINT15                    ((uint16_t)0xF000)            /*!< EXTI 15 configuration */
+
+/** EXTI12 configuration */
+#define AFIO_EXTIC4_EXTINT12_PTA                ((uint16_t)0x0000)            /*!< PA[12] pin */
+#define AFIO_EXTIC4_EXTINT12_PTB                ((uint16_t)0x0001)            /*!< PB[12] pin */
+#define AFIO_EXTIC4_EXTINT12_PTC                ((uint16_t)0x0002)            /*!< PC[12] pin */
+#define AFIO_EXTIC4_EXTINT12_PTD                ((uint16_t)0x0003)            /*!< PD[12] pin */
+#define AFIO_EXTIC4_EXTINT12_PTE                ((uint16_t)0x0004)            /*!< PE[12] pin */
+#define AFIO_EXTIC4_EXTINT12_PTF                ((uint16_t)0x0005)            /*!< PF[12] pin */
+#define AFIO_EXTIC4_EXTINT12_PTG                ((uint16_t)0x0006)            /*!< PG[12] pin */
+
+/** EXTI13 configuration */
+#define AFIO_EXTIC4_EXTINT13_PTA                ((uint16_t)0x0000)            /*!< PA[13] pin */
+#define AFIO_EXTIC4_EXTINT13_PTB                ((uint16_t)0x0010)            /*!< PB[13] pin */
+#define AFIO_EXTIC4_EXTINT13_PTC                ((uint16_t)0x0020)            /*!< PC[13] pin */
+#define AFIO_EXTIC4_EXTINT13_PTD                ((uint16_t)0x0030)            /*!< PD[13] pin */
+#define AFIO_EXTIC4_EXTINT13_PTE                ((uint16_t)0x0040)            /*!< PE[13] pin */
+#define AFIO_EXTIC4_EXTINT13_PTF                ((uint16_t)0x0050)            /*!< PF[13] pin */
+#define AFIO_EXTIC4_EXTINT13_PTG                ((uint16_t)0x0060)            /*!< PG[13] pin */
+
+/** EXTI14 configuration */
+#define AFIO_EXTIC4_EXTINT14_PTA                ((uint16_t)0x0000)            /*!< PA[14] pin */
+#define AFIO_EXTIC4_EXTINT14_PTB                ((uint16_t)0x0100)            /*!< PB[14] pin */
+#define AFIO_EXTIC4_EXTINT14_PTC                ((uint16_t)0x0200)            /*!< PC[14] pin */
+#define AFIO_EXTIC4_EXTINT14_PTD                ((uint16_t)0x0300)            /*!< PD[14] pin */
+#define AFIO_EXTIC4_EXTINT14_PTE                ((uint16_t)0x0400)            /*!< PE[14] pin */
+#define AFIO_EXTIC4_EXTINT14_PTF                ((uint16_t)0x0500)            /*!< PF[14] pin */
+#define AFIO_EXTIC4_EXTINT14_PTG                ((uint16_t)0x0600)            /*!< PG[14] pin */
+
+/** EXTI15 configuration */
+#define AFIO_EXTIC4_EXTINT15_PTA                ((uint16_t)0x0000)            /*!< PA[15] pin */
+#define AFIO_EXTIC4_EXTINT15_PTB                ((uint16_t)0x1000)            /*!< PB[15] pin */
+#define AFIO_EXTIC4_EXTINT15_PTC                ((uint16_t)0x2000)            /*!< PC[15] pin */
+#define AFIO_EXTIC4_EXTINT15_PTD                ((uint16_t)0x3000)            /*!< PD[15] pin */
+#define AFIO_EXTIC4_EXTINT15_PTE                ((uint16_t)0x4000)            /*!< PE[15] pin */
+#define AFIO_EXTIC4_EXTINT15_PTF                ((uint16_t)0x5000)            /*!< PF[15] pin */
+#define AFIO_EXTIC4_EXTINT15_PTG                ((uint16_t)0x6000)            /*!< PG[15] pin */
+
+
+/******************  Bit definition for AFIO_MAP2 register  ******************/
+#define AFIO_MAP2_TMR9_REMAP                    ((uint32_t)0x00000020)        /*!< TMR9 remapping */
+#define AFIO_MAP2_TMR10_REMAP                   ((uint32_t)0x00000040)        /*!< TMR10 remapping */
+#define AFIO_MAP2_TMR11_REMAP                   ((uint32_t)0x00000080)        /*!< TMR11 remapping */
+#define AFIO_MAP2_TMR13_REMAP                   ((uint32_t)0x00000100)        /*!< TMR13 remapping */
+#define AFIO_MAP2_TMR14_REMAP                   ((uint32_t)0x00000200)        /*!< TMR14 remapping */
+#define AFIO_MAP2_XMC_NADV_REMAP                ((uint32_t)0x00000400)        /*!< XMC NADV remapping */
+#define AFIO_MAP2_TMR15_REMAP                   ((uint32_t)0x00000001)        /*!< TMR15 remapping */
+#define AFIO_MAP2_SPI4_REMAP                    ((uint32_t)0x00020000)        /*!< SPI4 remapping */
+#define AFIO_MAP2_I2C3_REMAP                    ((uint32_t)0x00040000)        /*!< I2C3 remapping */
+#define AFIO_MAP2_SDIO2_REMAP_01                ((uint32_t)0x00080000)        /*!< SDIO2 remapping01 */
+#define AFIO_MAP2_SDIO2_REMAP_10                ((uint32_t)0x00100000)        /*!< SDIO2 remapping10 */
+#define AFIO_MAP2_SDIO2_REMAP_11                ((uint32_t)0x00180000)        /*!< SDIO2 remapping11 */
+#define AFIO_MAP2_EXT_FLASH_REMAP               ((uint32_t)0x00200000)        /*!< External FLASH remapping */
+
+/******************  Bit definition for AFIO_MAP3 register  ******************/
+#define AFIO_MAP3_TMR9_GRMP                     ((uint32_t)0x00000002)        /*!< TMR9 Alternate Function mapping  */
+#define AFIO_MAP3_TMR10_GRMP                    ((uint32_t)0x00000020)        /*!< TMR10 Alternate Function mapping  */
+#define AFIO_MAP3_TMR11_GRMP                    ((uint32_t)0x00000200)        /*!< TMR11 Alternate Function mapping  */
+
+/******************  Bit definition for AFIO_MAP4 register  ******************/
+#define AFIO_MAP4_TMR1_GRMP                     ((uint32_t)0x00000001)        /*!< TMR1 Alternate Function mapping */
+#define AFIO_MAP4_TMR2_GRMP_01                  ((uint32_t)0x00000010)        /*!< TMR2 Alternate Function mapping 0001*/
+#define AFIO_MAP4_TMR2_GRMP_10                  ((uint32_t)0x00000020)        /*!< TMR2 Alternate Function mapping 0010*/
+#define AFIO_MAP4_TMR2_GRMP_11                  ((uint32_t)0x00000030)        /*!< TMR2 Alternate Function mapping 0011*/
+#define AFIO_MAP4_TMR3_GRMP_10                  ((uint32_t)0x00000200)        /*!< TMR3 Alternate Function mapping 0010*/
+#define AFIO_MAP4_TMR3_GRMP_11                  ((uint32_t)0x00000300)        /*!< TMR3 Alternate Function mapping 0011*/
+#define AFIO_MAP4_TMR5_GRMP                     ((uint32_t)0x00010000)        /*!< TMR5 Alternate Function mapping : CH1/CH2*/
+#define AFIO_MAP4_TMR5CH4_INTLRE                ((uint32_t)0x00080000)        /*!< TMR5 Channel4 Internal Remap */
+
+/******************  Bit definition for AFIO_MAP5 register  ******************/
+#define AFIO_MAP5_I2C1_GRMP_01                  ((uint32_t)0x00000010)        /*!< I2C1 Alternate Function mapping 0001*/
+#define AFIO_MAP5_I2C1_GRMP_11                  ((uint32_t)0x00000030)        /*!< I2C1 Alternate Function mapping 0011*/
+#define AFIO_MAP5_I2C2_GRMP_01                  ((uint32_t)0x00000100)        /*!< I2C2 Alternate Function mapping 0001*/
+#define AFIO_MAP5_I2C2_GRMP_10                  ((uint32_t)0x00000200)        /*!< I2C2 Alternate Function mapping 0010*/
+#define AFIO_MAP5_I2C2_GRMP_11                  ((uint32_t)0x00000300)        /*!< I2C2 Alternate Function mapping 0011*/
+#define AFIO_MAP5_SPI1_GRMP                     ((uint32_t)0x00010000)        /*!< SPI1 Alternate Function mapping */
+#define AFIO_MAP5_SPI2_GRMP                     ((uint32_t)0x00100000)        /*!< SPI2 Alternate Function mapping */
+
+/******************  Bit definition for AFIO_MAP6 register  ******************/
+#define AFIO_MAP6_CAN1_GRMP                     ((uint32_t)0x00000002)        /*!< CAN1 Alternate Function mapping */
+#define AFIO_MAP6_CAN2_GRMP                     ((uint32_t)0x00000010)        /*!< CAN2 Alternate Function mapping */
+#define AFIO_MAP6_SDIO_GRMP_100                 ((uint32_t)0x00000400)        /*!< SDIO Alternate Function mapping 100 */
+#define AFIO_MAP6_SDIO_GRMP_101                 ((uint32_t)0x00000500)        /*!< SDIO Alternate Function mapping 101 */
+#define AFIO_MAP6_SDIO_GRMP_110                 ((uint32_t)0x00000600)        /*!< SDIO Alternate Function mapping 110 */
+#define AFIO_MAP6_SDIO_GRMP_111                 ((uint32_t)0x00000700)        /*!< SDIO Alternate Function mapping 111 */
+#define AFIO_MAP6_USART1_GRMP                   ((uint32_t)0x00010000)        /*!< USART1 Alternate Function mapping */
+#define AFIO_MAP6_USART3_GRMP                   ((uint32_t)0x01000000)        /*!< USART3 Partial Alternate Function mapping */
+#define AFIO_MAP6_UART4_GRMP                    ((uint32_t)0x10000000)        /*!< UART4 Alternate Function mapping */
+
+/******************  Bit definition for AFIO_MAP7 register  ******************/
+#define AFIO_MAP7_SPIF_GRMP_1000                ((uint32_t)0x00000008)        /*!< EXT_FLASH Alternate Function mapping */ 
+#define AFIO_MAP7_SPIF_GRMP_1001                ((uint32_t)0x00000009)        /*!< EXT_FLASH Alternate Function enable */ 
+#define AFIO_MAP7_ADC1_GRMP_01                  ((uint32_t)0x00000010)        /*!< ADC1 External Trigger Injected Conversion remapping */
+#define AFIO_MAP7_ADC1_GRMP_10                  ((uint32_t)0x00000020)        /*!< ADC1 External Trigger Regular Conversion remapping */
+#define AFIO_MAP7_ADC1_GRMP_11                  ((uint32_t)0x00000030)        /*!< ADC1 External Trigger Regular & Injected Conversion remapping */
+#define AFIO_MAP7_ADC2_GRMP_01                  ((uint32_t)0x00000100)        /*!< ADC2 External Trigger Injected Conversion remapping */
+#define AFIO_MAP7_ADC2_GRMP_10                  ((uint32_t)0x00000200)        /*!< ADC2 External Trigger Regular Conversion remapping */
+#define AFIO_MAP7_ADC2_GRMP_11                  ((uint32_t)0x00000300)        /*!< ADC2 External Trigger Regular & Injected Conversion remapping */
+#define AFIO_MAP7_SWJTAG_GRMP_001               ((uint32_t)0x00010000)        /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define AFIO_MAP7_SWJTAG_GRMP_010               ((uint32_t)0x00020000)        /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAP7_SWJTAG_GRMP_100               ((uint32_t)0x00040000)        /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
+#define AFIO_MAP7_PD01_GRMP                     ((uint32_t)0x00100000)        /*!< PD01 Alternate Function mapping */ 
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                               SystemTick                                   */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************  Bit definition for SysTick_CTRL register  *****************/
+#define  SysTick_CTRL_ENABLE                    ((uint32_t)0x00000001)        /*!< Counter enable */
+#define  SysTick_CTRL_TICKINT                   ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
+#define  SysTick_CTRL_CLKSOURCE                 ((uint32_t)0x00000004)        /*!< Clock source */
+#define  SysTick_CTRL_COUNTFLAG                 ((uint32_t)0x00010000)        /*!< Count Flag */
+
+/*****************  Bit definition for SysTick_LOAD register  *****************/
+#define  SysTick_LOAD_RELOAD                    ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/*****************  Bit definition for SysTick_VAL register  ******************/
+#define  SysTick_VAL_CURRENT                    ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
+
+/*****************  Bit definition for SysTick_CALIB register  ****************/
+#define  SysTick_CALIB_TENMS                    ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
+#define  SysTick_CALIB_SKEW                     ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
+#define  SysTick_CALIB_NOREF                    ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/*                                                                            */
+/*                  Nested Vectored Interrupt Controller                      */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for NVIC_ISER register  *******************/
+#define  NVIC_ISER_SETENA                       ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
+#define  NVIC_ISER_SETENA_0                     ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ISER_SETENA_1                     ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ISER_SETENA_2                     ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ISER_SETENA_3                     ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ISER_SETENA_4                     ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ISER_SETENA_5                     ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ISER_SETENA_6                     ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ISER_SETENA_7                     ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ISER_SETENA_8                     ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ISER_SETENA_9                     ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ISER_SETENA_10                    ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ISER_SETENA_11                    ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ISER_SETENA_12                    ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ISER_SETENA_13                    ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ISER_SETENA_14                    ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ISER_SETENA_15                    ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ISER_SETENA_16                    ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ISER_SETENA_17                    ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ISER_SETENA_18                    ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ISER_SETENA_19                    ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ISER_SETENA_20                    ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ISER_SETENA_21                    ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ISER_SETENA_22                    ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ISER_SETENA_23                    ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ISER_SETENA_24                    ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ISER_SETENA_25                    ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ISER_SETENA_26                    ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ISER_SETENA_27                    ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ISER_SETENA_28                    ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ISER_SETENA_29                    ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ISER_SETENA_30                    ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ISER_SETENA_31                    ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ICER register  *******************/
+#define  NVIC_ICER_CLRENA                       ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
+#define  NVIC_ICER_CLRENA_0                     ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ICER_CLRENA_1                     ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ICER_CLRENA_2                     ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ICER_CLRENA_3                     ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ICER_CLRENA_4                     ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ICER_CLRENA_5                     ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ICER_CLRENA_6                     ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ICER_CLRENA_7                     ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ICER_CLRENA_8                     ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ICER_CLRENA_9                     ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ICER_CLRENA_10                    ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ICER_CLRENA_11                    ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ICER_CLRENA_12                    ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ICER_CLRENA_13                    ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ICER_CLRENA_14                    ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ICER_CLRENA_15                    ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ICER_CLRENA_16                    ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ICER_CLRENA_17                    ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ICER_CLRENA_18                    ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ICER_CLRENA_19                    ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ICER_CLRENA_20                    ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ICER_CLRENA_21                    ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ICER_CLRENA_22                    ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ICER_CLRENA_23                    ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ICER_CLRENA_24                    ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ICER_CLRENA_25                    ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ICER_CLRENA_26                    ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ICER_CLRENA_27                    ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ICER_CLRENA_28                    ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ICER_CLRENA_29                    ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ICER_CLRENA_30                    ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ICER_CLRENA_31                    ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ISPR register  *******************/
+#define  NVIC_ISPR_SETPEND                      ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
+#define  NVIC_ISPR_SETPEND_0                    ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ISPR_SETPEND_1                    ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ISPR_SETPEND_2                    ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ISPR_SETPEND_3                    ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ISPR_SETPEND_4                    ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ISPR_SETPEND_5                    ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ISPR_SETPEND_6                    ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ISPR_SETPEND_7                    ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ISPR_SETPEND_8                    ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ISPR_SETPEND_9                    ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ISPR_SETPEND_10                   ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ISPR_SETPEND_11                   ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ISPR_SETPEND_12                   ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ISPR_SETPEND_13                   ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ISPR_SETPEND_14                   ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ISPR_SETPEND_15                   ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ISPR_SETPEND_16                   ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ISPR_SETPEND_17                   ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ISPR_SETPEND_18                   ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ISPR_SETPEND_19                   ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ISPR_SETPEND_20                   ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ISPR_SETPEND_21                   ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ISPR_SETPEND_22                   ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ISPR_SETPEND_23                   ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ISPR_SETPEND_24                   ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ISPR_SETPEND_25                   ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ISPR_SETPEND_26                   ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ISPR_SETPEND_27                   ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ISPR_SETPEND_28                   ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ISPR_SETPEND_29                   ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ISPR_SETPEND_30                   ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ISPR_SETPEND_31                   ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ICPR register  *******************/
+#define  NVIC_ICPR_CLRPEND                      ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
+#define  NVIC_ICPR_CLRPEND_0                    ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ICPR_CLRPEND_1                    ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ICPR_CLRPEND_2                    ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ICPR_CLRPEND_3                    ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ICPR_CLRPEND_4                    ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ICPR_CLRPEND_5                    ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ICPR_CLRPEND_6                    ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ICPR_CLRPEND_7                    ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ICPR_CLRPEND_8                    ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ICPR_CLRPEND_9                    ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ICPR_CLRPEND_10                   ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ICPR_CLRPEND_11                   ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ICPR_CLRPEND_12                   ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ICPR_CLRPEND_13                   ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ICPR_CLRPEND_14                   ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ICPR_CLRPEND_15                   ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ICPR_CLRPEND_16                   ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ICPR_CLRPEND_17                   ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ICPR_CLRPEND_18                   ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ICPR_CLRPEND_19                   ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ICPR_CLRPEND_20                   ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ICPR_CLRPEND_21                   ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ICPR_CLRPEND_22                   ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ICPR_CLRPEND_23                   ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ICPR_CLRPEND_24                   ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ICPR_CLRPEND_25                   ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ICPR_CLRPEND_26                   ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ICPR_CLRPEND_27                   ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ICPR_CLRPEND_28                   ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ICPR_CLRPEND_29                   ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ICPR_CLRPEND_30                   ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ICPR_CLRPEND_31                   ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_IABR register  *******************/
+#define  NVIC_IABR_ACTIVE                       ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
+#define  NVIC_IABR_ACTIVE_0                     ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_IABR_ACTIVE_1                     ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_IABR_ACTIVE_2                     ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_IABR_ACTIVE_3                     ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_IABR_ACTIVE_4                     ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_IABR_ACTIVE_5                     ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_IABR_ACTIVE_6                     ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_IABR_ACTIVE_7                     ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_IABR_ACTIVE_8                     ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_IABR_ACTIVE_9                     ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_IABR_ACTIVE_10                    ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_IABR_ACTIVE_11                    ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_IABR_ACTIVE_12                    ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_IABR_ACTIVE_13                    ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_IABR_ACTIVE_14                    ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_IABR_ACTIVE_15                    ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_IABR_ACTIVE_16                    ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_IABR_ACTIVE_17                    ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_IABR_ACTIVE_18                    ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_IABR_ACTIVE_19                    ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_IABR_ACTIVE_20                    ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_IABR_ACTIVE_21                    ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_IABR_ACTIVE_22                    ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_IABR_ACTIVE_23                    ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_IABR_ACTIVE_24                    ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_IABR_ACTIVE_25                    ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_IABR_ACTIVE_26                    ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_IABR_ACTIVE_27                    ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_IABR_ACTIVE_28                    ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_IABR_ACTIVE_29                    ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_IABR_ACTIVE_30                    ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_IABR_ACTIVE_31                    ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_PRI0 register  *******************/
+#define  NVIC_IPR0_PRI_0                        ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
+#define  NVIC_IPR0_PRI_1                        ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
+#define  NVIC_IPR0_PRI_2                        ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
+#define  NVIC_IPR0_PRI_3                        ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
+
+/******************  Bit definition for NVIC_PRI1 register  *******************/
+#define  NVIC_IPR1_PRI_4                        ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
+#define  NVIC_IPR1_PRI_5                        ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
+#define  NVIC_IPR1_PRI_6                        ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
+#define  NVIC_IPR1_PRI_7                        ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
+
+/******************  Bit definition for NVIC_PRI2 register  *******************/
+#define  NVIC_IPR2_PRI_8                        ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
+#define  NVIC_IPR2_PRI_9                        ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
+#define  NVIC_IPR2_PRI_10                       ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
+#define  NVIC_IPR2_PRI_11                       ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
+
+/******************  Bit definition for NVIC_PRI3 register  *******************/
+#define  NVIC_IPR3_PRI_12                       ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
+#define  NVIC_IPR3_PRI_13                       ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
+#define  NVIC_IPR3_PRI_14                       ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
+#define  NVIC_IPR3_PRI_15                       ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
+
+/******************  Bit definition for NVIC_PRI4 register  *******************/
+#define  NVIC_IPR4_PRI_16                       ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
+#define  NVIC_IPR4_PRI_17                       ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
+#define  NVIC_IPR4_PRI_18                       ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
+#define  NVIC_IPR4_PRI_19                       ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
+
+/******************  Bit definition for NVIC_PRI5 register  *******************/
+#define  NVIC_IPR5_PRI_20                       ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
+#define  NVIC_IPR5_PRI_21                       ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
+#define  NVIC_IPR5_PRI_22                       ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
+#define  NVIC_IPR5_PRI_23                       ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
+
+/******************  Bit definition for NVIC_PRI6 register  *******************/
+#define  NVIC_IPR6_PRI_24                       ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
+#define  NVIC_IPR6_PRI_25                       ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
+#define  NVIC_IPR6_PRI_26                       ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
+#define  NVIC_IPR6_PRI_27                       ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
+
+/******************  Bit definition for NVIC_PRI7 register  *******************/
+#define  NVIC_IPR7_PRI_28                       ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
+#define  NVIC_IPR7_PRI_29                       ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
+#define  NVIC_IPR7_PRI_30                       ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
+#define  NVIC_IPR7_PRI_31                       ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
+
+/******************  Bit definition for SCB_CPUID register  *******************/
+#define  SCB_CPUID_REVISION                     ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
+#define  SCB_CPUID_PARTNO                       ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
+#define  SCB_CPUID_Constant                     ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
+#define  SCB_CPUID_VARIANT                      ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
+#define  SCB_CPUID_IMPLEMENTER                  ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
+
+/*******************  Bit definition for SCB_ICSR register  *******************/
+#define  SCB_ICSR_VECTACTIVE                    ((uint32_t)0x000001FF)        /*!< Active ISR number field */
+#define  SCB_ICSR_RETTOBASE                     ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define  SCB_ICSR_VECTPENDING                   ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
+#define  SCB_ICSR_ISRPENDING                    ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
+#define  SCB_ICSR_ISRPREEMPT                    ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define  SCB_ICSR_PENDSTCLR                     ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
+#define  SCB_ICSR_PENDSTSET                     ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
+#define  SCB_ICSR_PENDSVCLR                     ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
+#define  SCB_ICSR_PENDSVSET                     ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
+#define  SCB_ICSR_NMIPENDSET                    ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
+
+/*******************  Bit definition for SCB_VTOR register  *******************/
+#define  SCB_VTOR_TBLOFF                        ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
+#define  SCB_VTOR_TBLBASE                       ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
+
+/*******************  Bit definition for SCB_AIRCR register  *******************/
+#define  SCB_AIRCR_VECTRESET                    ((uint32_t)0x00000001)        /*!< System Reset bit */
+#define  SCB_AIRCR_VECTCLRACTIVE                ((uint32_t)0x00000002)        /*!< Clear active vector bit */
+#define  SCB_AIRCR_SYSRESETREQ                  ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
+
+#define  SCB_AIRCR_PRIGROUP                     ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
+#define  SCB_AIRCR_PRIGROUP_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  SCB_AIRCR_PRIGROUP_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  SCB_AIRCR_PRIGROUP_2                   ((uint32_t)0x00000400)        /*!< Bit 2  */
+
+/* prority group configuration */           
+#define  SCB_AIRCR_PRIGROUP0                    ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define  SCB_AIRCR_PRIGROUP1                    ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP2                    ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP3                    ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP4                    ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP5                    ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP6                    ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP7                    ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define  SCB_AIRCR_ENDIANESS                    ((uint32_t)0x00008000)        /*!< Data endianness bit */
+#define  SCB_AIRCR_VECTKEY                      ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/*******************  Bit definition for SCB_SCR register  ********************/
+#define  SCB_SCR_SLEEPONEXIT                    ((uint8_t)0x02)               /*!< Sleep on exit bit */
+#define  SCB_SCR_SLEEPDEEP                      ((uint8_t)0x04)               /*!< Sleep deep bit */
+#define  SCB_SCR_SEVONPEND                      ((uint8_t)0x10)               /*!< Wake up from WFE */
+
+/********************  Bit definition for SCB_CCR register  *******************/
+#define  SCB_CCR_NONBASETHRDENA                 ((uint16_t)0x0001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define  SCB_CCR_USERSETMPEND                   ((uint16_t)0x0002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define  SCB_CCR_UNALIGN_TRP                    ((uint16_t)0x0008)            /*!< Trap for unaligned access */
+#define  SCB_CCR_DIV_0_TRP                      ((uint16_t)0x0010)            /*!< Trap on Divide by 0 */
+#define  SCB_CCR_BFHFNMIGN                      ((uint16_t)0x0100)            /*!< Handlers running at priority -1 and -2 */
+#define  SCB_CCR_STKALIGN                       ((uint16_t)0x0200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/*******************  Bit definition for SCB_SHPR register ********************/
+#define  SCB_SHPR_PRI_N                         ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define  SCB_SHPR_PRI_N1                        ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define  SCB_SHPR_PRI_N2                        ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define  SCB_SHPR_PRI_N3                        ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/******************  Bit definition for SCB_SHCSR register  *******************/
+#define  SCB_SHCSR_MEMFAULTACT                  ((uint32_t)0x00000001)        /*!< MemManage is active */
+#define  SCB_SHCSR_BUSFAULTACT                  ((uint32_t)0x00000002)        /*!< BusFault is active */
+#define  SCB_SHCSR_USGFAULTACT                  ((uint32_t)0x00000008)        /*!< UsageFault is active */
+#define  SCB_SHCSR_SVCALLACT                    ((uint32_t)0x00000080)        /*!< SVCall is active */
+#define  SCB_SHCSR_MONITORACT                   ((uint32_t)0x00000100)        /*!< Monitor is active */
+#define  SCB_SHCSR_PENDSVACT                    ((uint32_t)0x00000400)        /*!< PendSV is active */
+#define  SCB_SHCSR_SYSTICKACT                   ((uint32_t)0x00000800)        /*!< SysTick is active */
+#define  SCB_SHCSR_USGFAULTPENDED               ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
+#define  SCB_SHCSR_MEMFAULTPENDED               ((uint32_t)0x00002000)        /*!< MemManage is pended */
+#define  SCB_SHCSR_BUSFAULTPENDED               ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
+#define  SCB_SHCSR_SVCALLPENDED                 ((uint32_t)0x00008000)        /*!< SVCall is pended */
+#define  SCB_SHCSR_MEMFAULTENA                  ((uint32_t)0x00010000)        /*!< MemManage enable */
+#define  SCB_SHCSR_BUSFAULTENA                  ((uint32_t)0x00020000)        /*!< Bus Fault enable */
+#define  SCB_SHCSR_USGFAULTENA                  ((uint32_t)0x00040000)        /*!< UsageFault enable */
+
+/*******************  Bit definition for SCB_CFSR register  *******************/
+/** MFSR */
+#define  SCB_CFSR_IACCVIOL                      ((uint32_t)0x00000001)        /*!< Instruction access violation */
+#define  SCB_CFSR_DACCVIOL                      ((uint32_t)0x00000002)        /*!< Data access violation */
+#define  SCB_CFSR_MUNSTKERR                     ((uint32_t)0x00000008)        /*!< Unstacking error */
+#define  SCB_CFSR_MSTKERR                       ((uint32_t)0x00000010)        /*!< Stacking error */
+#define  SCB_CFSR_MMARVALID                     ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
+/** BFSR */                                  
+#define  SCB_CFSR_IBUSERR                       ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
+#define  SCB_CFSR_PRECISERR                     ((uint32_t)0x00000200)        /*!< Precise data bus error */
+#define  SCB_CFSR_IMPRECISERR                   ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
+#define  SCB_CFSR_UNSTKERR                      ((uint32_t)0x00000800)        /*!< Unstacking error */
+#define  SCB_CFSR_STKERR                        ((uint32_t)0x00001000)        /*!< Stacking error */
+#define  SCB_CFSR_BFARVALID                     ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
+/** UFSR */                                  
+#define  SCB_CFSR_UNDEFINSTR                    ((uint32_t)0x00010000)        /*!< The processor attempt to execute an undefined instruction */
+#define  SCB_CFSR_INVSTATE                      ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
+#define  SCB_CFSR_INVPC                         ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
+#define  SCB_CFSR_NOCP                          ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
+#define  SCB_CFSR_UNALIGNED                     ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define  SCB_CFSR_DIVBYZERO                     ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/*******************  Bit definition for SCB_HFSR register  *******************/
+#define  SCB_HFSR_VECTTBL                       ((uint32_t)0x00000002)        /*!< Fault occurs because of vector table read on exception processing */
+#define  SCB_HFSR_FORCED                        ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define  SCB_HFSR_DEBUGEVT                      ((uint32_t)0x80000000)        /*!< Fault related to debug */
+
+/*******************  Bit definition for SCB_DFSR register  *******************/
+#define  SCB_DFSR_HALTED                        ((uint8_t)0x01)               /*!< Halt request flag */
+#define  SCB_DFSR_BKPT                          ((uint8_t)0x02)               /*!< BKPT flag */
+#define  SCB_DFSR_DWTTRAP                       ((uint8_t)0x04)               /*!< Data Watchpoint and Trace (DWT) flag */
+#define  SCB_DFSR_VCATCH                        ((uint8_t)0x08)               /*!< Vector catch flag */
+#define  SCB_DFSR_EXTERNAL                      ((uint8_t)0x10)               /*!< External debug request flag */
+
+/*******************  Bit definition for SCB_MMFAR register  ******************/
+#define  SCB_MMFAR_ADDRESS                      ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
+
+/*******************  Bit definition for SCB_BFAR register  *******************/
+#define  SCB_BFAR_ADDRESS                       ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
+
+/*******************  Bit definition for SCB_AFSR register  *******************/
+#define  SCB_AFSR_IMPDEF                        ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for EXTI_INTEN register  *******************/
+#define  EXTI_INTEN_LN0                         ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
+#define  EXTI_INTEN_LN1                         ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
+#define  EXTI_INTEN_LN2                         ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
+#define  EXTI_INTEN_LN3                         ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
+#define  EXTI_INTEN_LN4                         ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
+#define  EXTI_INTEN_LN5                         ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
+#define  EXTI_INTEN_LN6                         ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
+#define  EXTI_INTEN_LN7                         ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
+#define  EXTI_INTEN_LN8                         ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
+#define  EXTI_INTEN_LN9                         ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
+#define  EXTI_INTEN_LN10                        ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_INTEN_LN11                        ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_INTEN_LN12                        ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_INTEN_LN13                        ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_INTEN_LN14                        ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_INTEN_LN15                        ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_INTEN_LN16                        ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_INTEN_LN17                        ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_INTEN_LN18                        ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_INTEN_LN19                        ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+
+/*******************  Bit definition for EXTI_EVTEN register  *******************/
+#define  EXTI_EVTEN_LN0                         ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
+#define  EXTI_EVTEN_LN1                         ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
+#define  EXTI_EVTEN_LN2                         ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
+#define  EXTI_EVTEN_LN3                         ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
+#define  EXTI_EVTEN_LN4                         ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
+#define  EXTI_EVTEN_LN5                         ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
+#define  EXTI_EVTEN_LN6                         ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
+#define  EXTI_EVTEN_LN7                         ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
+#define  EXTI_EVTEN_LN8                         ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
+#define  EXTI_EVTEN_LN9                         ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
+#define  EXTI_EVTEN_LN10                        ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EVTEN_LN11                        ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EVTEN_LN12                        ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EVTEN_LN13                        ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EVTEN_LN14                        ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EVTEN_LN15                        ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EVTEN_LN16                        ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EVTEN_LN17                        ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EVTEN_LN18                        ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EVTEN_LN19                        ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+
+/******************  Bit definition for EXTI_RTRSEL register  *******************/
+#define  EXTI_RTRSEL_LN0                        ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTRSEL_LN1                        ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTRSEL_LN2                        ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTRSEL_LN3                        ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTRSEL_LN4                        ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTRSEL_LN5                        ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTRSEL_LN6                        ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTRSEL_LN7                        ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTRSEL_LN8                        ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTRSEL_LN9                        ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTRSEL_LN10                       ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTRSEL_LN11                       ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTRSEL_LN12                       ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTRSEL_LN13                       ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTRSEL_LN14                       ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTRSEL_LN15                       ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTRSEL_LN16                       ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTRSEL_LN17                       ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTRSEL_LN18                       ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTRSEL_LN19                       ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_FTRSEL register  *******************/
+#define  EXTI_FTRSEL_LN0                        ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTRSEL_LN1                        ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTRSEL_LN2                        ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTRSEL_LN3                        ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTRSEL_LN4                        ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTRSEL_LN5                        ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTRSEL_LN6                        ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTRSEL_LN7                        ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTRSEL_LN8                        ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTRSEL_LN9                        ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTRSEL_LN10                       ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTRSEL_LN11                       ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTRSEL_LN12                       ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTRSEL_LN13                       ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTRSEL_LN14                       ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTRSEL_LN15                       ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTRSEL_LN16                       ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTRSEL_LN17                       ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTRSEL_LN18                       ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTRSEL_LN19                       ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_SWIE register  ******************/
+#define  EXTI_SWIE_LN0                          ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIE_LN1                          ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIE_LN2                          ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIE_LN3                          ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIE_LN4                          ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIE_LN5                          ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIE_LN6                          ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIE_LN7                          ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIE_LN8                          ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIE_LN9                          ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIE_LN10                         ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIE_LN11                         ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIE_LN12                         ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIE_LN13                         ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIE_LN14                         ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIE_LN15                         ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIE_LN16                         ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIE_LN17                         ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIE_LN18                         ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIE_LN19                         ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+
+/*******************  Bit definition for EXTI_PND register  ********************/
+#define  EXTI_PND_LN0                           ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
+#define  EXTI_PND_LN1                           ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
+#define  EXTI_PND_LN2                           ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
+#define  EXTI_PND_LN3                           ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
+#define  EXTI_PND_LN4                           ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
+#define  EXTI_PND_LN5                           ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
+#define  EXTI_PND_LN6                           ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
+#define  EXTI_PND_LN7                           ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
+#define  EXTI_PND_LN8                           ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
+#define  EXTI_PND_LN9                           ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
+#define  EXTI_PND_LN10                          ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
+#define  EXTI_PND_LN11                          ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
+#define  EXTI_PND_LN12                          ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
+#define  EXTI_PND_LN13                          ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
+#define  EXTI_PND_LN14                          ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
+#define  EXTI_PND_LN15                          ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
+#define  EXTI_PND_LN16                          ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
+#define  EXTI_PND_LN17                          ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
+#define  EXTI_PND_LN18                          ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
+#define  EXTI_PND_LN19                          ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISTS register  ********************/
+#define  DMA_ISTS_GIF1                          ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
+#define  DMA_ISTS_TCIF1                         ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
+#define  DMA_ISTS_HTIF1                         ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
+#define  DMA_ISTS_ERRIF1                        ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
+#define  DMA_ISTS_GIF2                          ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
+#define  DMA_ISTS_TCIF2                         ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
+#define  DMA_ISTS_HTIF2                         ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
+#define  DMA_ISTS_ERRIF2                        ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
+#define  DMA_ISTS_GIF3                          ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
+#define  DMA_ISTS_TCIF3                         ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
+#define  DMA_ISTS_HTIF3                         ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
+#define  DMA_ISTS_ERRIF3                        ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
+#define  DMA_ISTS_GIF4                          ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
+#define  DMA_ISTS_TCIF4                         ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
+#define  DMA_ISTS_HTIF4                         ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
+#define  DMA_ISTS_ERRIF4                        ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
+#define  DMA_ISTS_GIF5                          ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
+#define  DMA_ISTS_TCIF5                         ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
+#define  DMA_ISTS_HTIF5                         ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
+#define  DMA_ISTS_ERRIF5                        ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
+#define  DMA_ISTS_GIF6                          ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
+#define  DMA_ISTS_TCIF6                         ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
+#define  DMA_ISTS_HTIF6                         ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
+#define  DMA_ISTS_ERRIF6                        ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
+#define  DMA_ISTS_GIF7                          ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
+#define  DMA_ISTS_TCIF7                         ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
+#define  DMA_ISTS_HTIF7                         ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
+#define  DMA_ISTS_ERRIF7                        ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_ICLR register  *******************/
+#define  DMA_ICLR_CGIF1                          ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */
+#define  DMA_ICLR_CTCIF1                         ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
+#define  DMA_ICLR_CHTIF1                         ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
+#define  DMA_ICLR_CERRIF1                        ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
+#define  DMA_ICLR_CGIF2                          ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
+#define  DMA_ICLR_CTCIF2                         ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
+#define  DMA_ICLR_CHTIF2                         ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
+#define  DMA_ICLR_CERRIF2                        ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
+#define  DMA_ICLR_CGIF3                          ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
+#define  DMA_ICLR_CTCIF3                         ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
+#define  DMA_ICLR_CHTIF3                         ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
+#define  DMA_ICLR_CERRIF3                        ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
+#define  DMA_ICLR_CGIF4                          ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
+#define  DMA_ICLR_CTCIF4                         ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
+#define  DMA_ICLR_CHTIF4                         ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
+#define  DMA_ICLR_CERRIF4                        ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
+#define  DMA_ICLR_CGIF5                          ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
+#define  DMA_ICLR_CTCIF5                         ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
+#define  DMA_ICLR_CHTIF5                         ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
+#define  DMA_ICLR_CERRIF5                        ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
+#define  DMA_ICLR_CGIF6                          ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
+#define  DMA_ICLR_CTCIF6                         ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
+#define  DMA_ICLR_CHTIF6                         ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
+#define  DMA_ICLR_CERRIF6                        ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
+#define  DMA_ICLR_CGIF7                          ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
+#define  DMA_ICLR_CTCIF7                         ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
+#define  DMA_ICLR_CHTIF7                         ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
+#define  DMA_ICLR_CERRIF7                        ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CHCTRL1 register  *******************/
+#define  DMA_CHCTRL1_CHEN                       ((uint16_t)0x0001)            /*!< Channel enable*/
+#define  DMA_CHCTRL1_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CHCTRL1_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CHCTRL1_ERRIE                      ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CHCTRL1_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CHCTRL1_CIRM                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CHCTRL1_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CHCTRL1_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CHCTRL1_PWIDTH                     ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CHCTRL1_PWIDTH_0                   ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CHCTRL1_PWIDTH_1                   ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL1_MWIDTH                     ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CHCTRL1_MWIDTH_0                   ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CHCTRL1_MWIDTH_1                   ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL1_CHPL                       ((uint16_t)0x3000)            /*!< PL[1:0] bits(Channel Priority level) */
+#define  DMA_CHCTRL1_CHPL_0                     ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CHCTRL1_CHPL_1                     ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL1_MEMTOMEM                   ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CHCTRL2 register  *******************/
+#define  DMA_CHCTRL2_CHEN                       ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CHCTRL2_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CHCTRL2_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CHCTRL2_ERRIE                      ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CHCTRL2_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CHCTRL2_CIRM                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CHCTRL2_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CHCTRL2_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CHCTRL2_PWIDTH                     ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CHCTRL2_PWIDTH_0                   ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CHCTRL2_PWIDTH_1                   ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL2_MWIDTH                     ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CHCTRL2_MWIDTH_0                   ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CHCTRL2_MWIDTH_1                   ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL2_CHPL                       ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CHCTRL2_CHPL_0                     ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CHCTRL2_CHPL_1                     ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL2_MEMTOMEM                   ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CHCTRL3 register  *******************/
+#define  DMA_CHCTRL3_CHEN                       ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CHCTRL3_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CHCTRL3_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CHCTRL3_ERRIE                      ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CHCTRL3_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CHCTRL3_CIRM                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CHCTRL3_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CHCTRL3_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CHCTRL3_PWIDTH                     ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CHCTRL3_PWIDTH_0                   ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CHCTRL3_PWIDTH_1                   ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL3_MWIDTH                     ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CHCTRL3_MWIDTH_0                   ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CHCTRL3_MWIDTH_1                   ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL3_CHPL                       ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CHCTRL3_CHPL_0                     ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CHCTRL3_CHPL_1                     ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL3_MEMTOMEM                   ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/********************  Bit definition for DMA_CHCTRL4 register  *******************/
+#define  DMA_CHCTRL4_CHEN                       ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CHCTRL4_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CHCTRL4_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CHCTRL4_ERRIE                      ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CHCTRL4_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CHCTRL4_CIRM                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CHCTRL4_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CHCTRL4_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CHCTRL4_PWIDTH                     ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CHCTRL4_PWIDTH_0                   ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CHCTRL4_PWIDTH_1                   ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL4_MWIDTH                     ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CHCTRL4_MWIDTH_0                   ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CHCTRL4_MWIDTH_1                   ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL4_CHPL                       ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CHCTRL4_CHPL_0                     ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CHCTRL4_CHPL_1                     ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL4_MEMTOMEM                   ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/******************  Bit definition for DMA_CHCTRL5 register  *******************/
+#define  DMA_CHCTRL5_CHEN                       ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CHCTRL5_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CHCTRL5_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CHCTRL5_ERRIE                      ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CHCTRL5_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CHCTRL5_CIRM                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CHCTRL5_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CHCTRL5_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CHCTRL5_PWIDTH                     ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CHCTRL5_PWIDTH_0                   ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CHCTRL5_PWIDTH_1                   ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL5_MWIDTH                     ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CHCTRL5_MWIDTH_0                   ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CHCTRL5_MWIDTH_1                   ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL5_CHPL                       ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CHCTRL5_CHPL_0                     ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CHCTRL5_CHPL_1                     ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL5_MEMTOMEM                   ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
+
+/*******************  Bit definition for DMA_CHCTRL6 register  *******************/
+#define  DMA_CHCTRL6_CHEN                       ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CHCTRL6_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CHCTRL6_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CHCTRL6_ERRIE                      ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CHCTRL6_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CHCTRL6_CIRM                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CHCTRL6_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CHCTRL6_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CHCTRL6_PWIDTH                     ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CHCTRL6_PWIDTH_0                   ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CHCTRL6_PWIDTH_1                   ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL6_MWIDTH                     ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CHCTRL6_MWIDTH_0                   ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CHCTRL6_MWIDTH_1                   ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL6_CHPL                       ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CHCTRL6_CHPL_0                     ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CHCTRL6_CHPL_1                     ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL6_MEMTOMEM                   ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CHCTRL7 register  *******************/
+#define  DMA_CHCTRL7_CHEN                       ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CHCTRL7_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CHCTRL7_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CHCTRL7_ERRIE                      ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CHCTRL7_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CHCTRL7_CIRM                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CHCTRL7_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CHCTRL7_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CHCTRL7_PWIDTH                ,    ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CHCTRL7_PWIDTH_0                   ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CHCTRL7_PWIDTH_1                   ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL7_MWIDTH                     ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CHCTRL7_MWIDTH_0                   ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CHCTRL7_MWIDTH_1                   ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL7_CHPL                       ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CHCTRL7_CHPL_0                     ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CHCTRL7_CHPL_1                     ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CHCTRL7_MEMTOMEM                   ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
+
+/******************  Bit definition for DMA_TCNT1 register  ******************/
+#define  DMA_TCNT1_CNT                          ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_TCNT2 register  ******************/
+#define  DMA_TCNT2_CNT                          ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_TCNT3 register  ******************/
+#define  DMA_TCNT3_CNT                          ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_TCNT4 register  ******************/
+#define  DMA_TCNT4_CNT                          ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_TCNT5 register  ******************/
+#define  DMA_TCNT5_CNT                          ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_TCNT6 register  ******************/
+#define  DMA_TCNT6_CNT                          ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_TCNT7 register  ******************/
+#define  DMA_TCNT7_CNT                          ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CPBA1 register  *******************/
+#define  DMA_CPBA1_PA                           ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPBA2 register  *******************/
+#define  DMA_CPBA2_PA                           ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPBA3 register  *******************/
+#define  DMA_CPBA3_PA                           ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+
+/******************  Bit definition for DMA_CPBA4 register  *******************/
+#define  DMA_CPBA4_PA                           ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPBA5 register  *******************/
+#define  DMA_CPBA5_PA                           ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPBA6 register  *******************/
+#define  DMA_CPBA6_PA                           ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+
+/******************  Bit definition for DMA_CPBA7 register  *******************/
+#define  DMA_CPBA7_PA                           ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CMBA1 register  *******************/
+#define  DMA_CMBA1_MA                           ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMBA2 register  *******************/
+#define  DMA_CMBA2_MA                           ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMBA3 register  *******************/
+#define  DMA_CMBA3_MA                           ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+
+/******************  Bit definition for DMA_CMBA4 register  *******************/
+#define  DMA_CMBA4_MA                           ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMBA5 register  *******************/
+#define  DMA_CMBA5_MA                           ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMBA6 register  *******************/
+#define  DMA_CMBA6_MA                           ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMBA7 register  *******************/
+#define  DMA_CMBA7_MA                           ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for ADC_STS register  ********************/
+#define  ADC_STS_AWD                            ((uint8_t)0x01)               /*!< Analog watchdog flag */
+#define  ADC_STS_EC                             ((uint8_t)0x02)               /*!< End of conversion */
+#define  ADC_STS_JEC                            ((uint8_t)0x04)               /*!< Injected channel end of conversion */
+#define  ADC_STS_JSTR                           ((uint8_t)0x08)               /*!< Injected channel Start flag */
+#define  ADC_STS_RSTR                           ((uint8_t)0x10)               /*!< Regular channel Start flag */
+
+/*******************  Bit definition for ADC_CTRL1 register  ********************/
+#define  ADC_CTRL1_AWDCS                        ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CTRL1_AWDCS_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_CTRL1_AWDCS_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_CTRL1_AWDCS_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_CTRL1_AWDCS_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_CTRL1_AWDCS_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_CTRL1_ECIEN                        ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */
+#define  ADC_CTRL1_AWDIEN                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */
+#define  ADC_CTRL1_JECIEN                       ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */
+#define  ADC_CTRL1_SCN                          ((uint32_t)0x00000100)        /*!< Scan mode */
+#define  ADC_CTRL1_AWDSGE                       ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */
+#define  ADC_CTRL1_JAUT                         ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */
+#define  ADC_CTRL1_RDISEN                       ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */
+#define  ADC_CTRL1_JDISEN                       ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */
+
+#define  ADC_CTRL1_DISN                         ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CTRL1_DISN_0                       ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  ADC_CTRL1_DISN_1                       ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  ADC_CTRL1_DISN_2                       ((uint32_t)0x00008000)        /*!< Bit 2 */
+
+#define  ADC_CTRL1_DUALM                        ((uint32_t)0x000F0000)        /*!< DUALMOD[3:0] bits (Dual mode selection) */
+#define  ADC_CTRL1_DUALM_0                      ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  ADC_CTRL1_DUALM_1                      ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  ADC_CTRL1_DUALM_2                      ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  ADC_CTRL1_DUALM_3                      ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  ADC_CTRL1_JAWDEN                       ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */
+#define  ADC_CTRL1_AWDEN                        ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */
+
+
+/*******************  Bit definition for ADC_CTRL2 register  ********************/
+#define  ADC_CTRL2_ADON                         ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */
+#define  ADC_CTRL2_CON                          ((uint32_t)0x00000002)        /*!< Continuous Conversion */
+#define  ADC_CTRL2_CAL                          ((uint32_t)0x00000004)        /*!< A/D Calibration */
+#define  ADC_CTRL2_RSTCAL                       ((uint32_t)0x00000008)        /*!< Reset Calibration */
+#define  ADC_CTRL2_DMAEN                        ((uint32_t)0x00000100)        /*!< Direct Memory access mode */
+#define  ADC_CTRL2_DALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */
+
+#define  ADC_CTRL2_JEXSEL                       ((uint32_t)0x01007000)        /*!< JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CTRL2_JEXSEL_0                     ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_CTRL2_JEXSEL_1                     ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_CTRL2_JEXSEL_2                     ((uint32_t)0x00004000)        /*!< Bit 2 */
+#define  ADC_CTRL2_JEXSEL_3                     ((uint32_t)0x01000000)        /*!< Bit 3 */
+
+#define  ADC_CTRL2_JEXTREN                      ((uint32_t)0x00008000)        /*!< External Trigger Conversion mode for injected channels */
+
+#define  ADC_CTRL2_EXSEL                        ((uint32_t)0x020E0000)        /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CTRL2_EXSEL_0                      ((uint32_t)0x00020000)        /*!< Bit 0 */
+#define  ADC_CTRL2_EXSEL_1                      ((uint32_t)0x00040000)        /*!< Bit 1 */
+#define  ADC_CTRL2_EXSEL_2                      ((uint32_t)0x00080000)        /*!< Bit 2 */
+#define  ADC_CTRL2_EXSEL_3                      ((uint32_t)0x02000000)        /*!< Bit 3 */
+
+#define  ADC_CTRL2_EXTREN                       ((uint32_t)0x00100000)        /*!< External Trigger Conversion mode for regular channels */
+#define  ADC_CTRL2_JSWSTR                       ((uint32_t)0x00200000)        /*!< Start Conversion of injected channels */
+#define  ADC_CTRL2_SWSTR                        ((uint32_t)0x00400000)        /*!< Start Conversion of regular channels */
+#define  ADC_CTRL2_TSREF                        ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */
+
+/******************  Bit definition for ADC_SMPT1 register  *******************/
+#define  ADC_SMPT1_SMP10                        ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPT1_SMP10_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPT1_SMP10_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPT1_SMP10_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+#define  ADC_SMPT1_SMP11                        ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPT1_SMP11_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPT1_SMP11_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPT1_SMP11_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  ADC_SMPT1_SMP12                        ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPT1_SMP12_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  ADC_SMPT1_SMP12_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
+#define  ADC_SMPT1_SMP12_2                      ((uint32_t)0x00000100)        /*!< Bit 2 */
+
+#define  ADC_SMPT1_SMP13                        ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPT1_SMP13_0                      ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  ADC_SMPT1_SMP13_1                      ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  ADC_SMPT1_SMP13_2                      ((uint32_t)0x00000800)        /*!< Bit 2 */
+
+#define  ADC_SMPT1_SMP14                        ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPT1_SMP14_0                      ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_SMPT1_SMP14_1                      ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_SMPT1_SMP14_2                      ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_SMPT1_SMP15                        ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPT1_SMP15_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPT1_SMP15_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPT1_SMP15_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
+
+#define  ADC_SMPT1_SMP16                        ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPT1_SMP16_0                      ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPT1_SMP16_1                      ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPT1_SMP16_2                      ((uint32_t)0x00100000)        /*!< Bit 2 */
+
+#define  ADC_SMPT1_SMP17                        ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPT1_SMP17_0                      ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPT1_SMP17_1                      ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPT1_SMP17_2                      ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_SMPT2 register  *******************/
+#define  ADC_SMPT2_SMP0                         ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPT2_SMP0_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPT2_SMP0_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPT2_SMP0_2                       ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+#define  ADC_SMPT2_SMP1                         ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPT2_SMP1_0                       ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPT2_SMP1_1                       ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPT2_SMP1_2                       ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  ADC_SMPT2_SMP2                         ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPT2_SMP2_0                       ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  ADC_SMPT2_SMP2_1                       ((uint32_t)0x00000080)        /*!< Bit 1 */
+#define  ADC_SMPT2_SMP2_2                       ((uint32_t)0x00000100)        /*!< Bit 2 */
+
+#define  ADC_SMPT2_SMP3                         ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPT2_SMP3_0                       ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  ADC_SMPT2_SMP3_1                       ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  ADC_SMPT2_SMP3_2                       ((uint32_t)0x00000800)        /*!< Bit 2 */
+
+#define  ADC_SMPT2_SMP4                         ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPT2_SMP4_0                       ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_SMPT2_SMP4_1                       ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_SMPT2_SMP4_2                       ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_SMPT2_SMP5                         ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPT2_SMP5_0                       ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPT2_SMP5_1                       ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPT2_SMP5_2                       ((uint32_t)0x00020000)        /*!< Bit 2 */
+
+#define  ADC_SMPT2_SMP6                         ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPT2_SMP6_0                       ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPT2_SMP6_1                       ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPT2_SMP6_2                       ((uint32_t)0x00100000)        /*!< Bit 2 */
+
+#define  ADC_SMPT2_SMP7                         ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPT2_SMP7_0                       ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPT2_SMP7_1                       ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPT2_SMP7_2                       ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+#define  ADC_SMPT2_SMP8                         ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPT2_SMP8_0                       ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  ADC_SMPT2_SMP8_1                       ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  ADC_SMPT2_SMP8_2                       ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define  ADC_SMPT2_SMP9                         ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPT2_SMP9_0                       ((uint32_t)0x08000000)        /*!< Bit 0 */
+#define  ADC_SMPT2_SMP9_1                       ((uint32_t)0x10000000)        /*!< Bit 1 */
+#define  ADC_SMPT2_SMP9_2                       ((uint32_t)0x20000000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_JOFS1 register  *******************/
+#define  ADC_JOFS1_JOFST1                       ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFS2 register  *******************/
+#define  ADC_JOFS2_JOFST2                       ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFS3 register  *******************/
+#define  ADC_JOFS3_JOFST3                       ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFS4 register  *******************/
+#define  ADC_JOFS4_JOFST4                       ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_WHTR register  ********************/
+#define  ADC_WHTR_AWHT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_WLTR register  ********************/
+#define  ADC_WLTR_AWLT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_RSQ1 register  *******************/
+#define  ADC_RSQ1_SQ13                          ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_RSQ1_SQ13_0                        ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_RSQ1_SQ13_1                        ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_RSQ1_SQ13_2                        ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_RSQ1_SQ13_3                        ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_RSQ1_SQ13_4                        ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_RSQ1_SQ14                          ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_RSQ1_SQ14_0                        ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_RSQ1_SQ14_1                        ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_RSQ1_SQ14_2                        ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_RSQ1_SQ14_3                        ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_RSQ1_SQ14_4                        ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_RSQ1_SQ15                          ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_RSQ1_SQ15_0                        ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_RSQ1_SQ15_1                        ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_RSQ1_SQ15_2                        ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_RSQ1_SQ15_3                        ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_RSQ1_SQ15_4                        ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_RSQ1_SQ16                          ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_RSQ1_SQ16_0                        ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_RSQ1_SQ16_1                        ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_RSQ1_SQ16_2                        ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_RSQ1_SQ16_3                        ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_RSQ1_SQ16_4                        ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_RSQ1_LEN                           ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */
+#define  ADC_RSQ1_LEN_0                         ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_RSQ1_LEN_1                         ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_RSQ1_LEN_2                         ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_RSQ1_LEN_3                         ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+/*******************  Bit definition for ADC_RSQ2 register  *******************/
+#define  ADC_RSQ2_SQ7                           ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_RSQ2_SQ7_0                         ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_RSQ2_SQ7_1                         ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_RSQ2_SQ7_2                         ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_RSQ2_SQ7_3                         ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_RSQ2_SQ7_4                         ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_RSQ2_SQ8                           ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_RSQ2_SQ8_0                         ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_RSQ2_SQ8_1                         ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_RSQ2_SQ8_2                         ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_RSQ2_SQ8_3                         ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_RSQ2_SQ8_4                         ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_RSQ2_SQ9                           ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_RSQ2_SQ9_0                         ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_RSQ2_SQ9_1                         ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_RSQ2_SQ9_2                         ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_RSQ2_SQ9_3                         ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_RSQ2_SQ9_4                         ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_RSQ2_SQ10                          ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_RSQ2_SQ10_0                        ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_RSQ2_SQ10_1                        ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_RSQ2_SQ10_2                        ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_RSQ2_SQ10_3                        ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_RSQ2_SQ10_4                        ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_RSQ2_SQ11                          ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_RSQ2_SQ11_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_RSQ2_SQ11_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_RSQ2_SQ11_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_RSQ2_SQ11_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_RSQ2_SQ11_4                        ((uint32_t)0x01000000)        /*!< Bit 4 */
+
+#define  ADC_RSQ2_SQ12                          ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_RSQ2_SQ12_0                        ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_RSQ2_SQ12_1                        ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_RSQ2_SQ12_2                        ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_RSQ2_SQ12_3                        ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_RSQ2_SQ12_4                        ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_RSQ3 register  *******************/
+#define  ADC_RSQ3_SQ1                           ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_RSQ3_SQ1_0                         ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_RSQ3_SQ1_1                         ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_RSQ3_SQ1_2                         ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_RSQ3_SQ1_3                         ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_RSQ3_SQ1_4                         ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_RSQ3_SQ2                           ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_RSQ3_SQ2_0                         ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_RSQ3_SQ2_1                         ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_RSQ3_SQ2_2                         ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_RSQ3_SQ2_3                         ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_RSQ3_SQ2_4                         ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_RSQ3_SQ3                           ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_RSQ3_SQ3_0                         ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_RSQ3_SQ3_1                         ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_RSQ3_SQ3_2                         ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_RSQ3_SQ3_3                         ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_RSQ3_SQ3_4                         ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_RSQ3_SQ4                           ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_RSQ3_SQ4_0                         ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_RSQ3_SQ4_1                         ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_RSQ3_SQ4_2                         ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_RSQ3_SQ4_3                         ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_RSQ3_SQ4_4                         ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_RSQ3_SQ5                           ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_RSQ3_SQ5_0                         ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_RSQ3_SQ5_1                         ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_RSQ3_SQ5_2                         ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_RSQ3_SQ5_3                         ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_RSQ3_SQ5_4                         ((uint32_t)0x01000000)        /*!< Bit 4 */
+
+#define  ADC_RSQ3_SQ6                           ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_RSQ3_SQ6_0                         ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_RSQ3_SQ6_1                         ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_RSQ3_SQ6_2                         ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_RSQ3_SQ6_3                         ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_RSQ3_SQ6_4                         ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_JSQ register  *******************/
+#define  ADC_JSQ_JSQ1                           ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define  ADC_JSQ_JSQ1_0                         ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_JSQ_JSQ1_1                         ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_JSQ_JSQ1_2                         ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_JSQ_JSQ1_3                         ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_JSQ_JSQ1_4                         ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_JSQ_JSQ2                           ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQ_JSQ2_0                         ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_JSQ_JSQ2_1                         ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_JSQ_JSQ2_2                         ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_JSQ_JSQ2_3                         ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_JSQ_JSQ2_4                         ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_JSQ_JSQ3                           ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQ_JSQ3_0                         ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_JSQ_JSQ3_1                         ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_JSQ_JSQ3_2                         ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_JSQ_JSQ3_3                         ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_JSQ_JSQ3_4                         ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_JSQ_JSQ4                           ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQ_JSQ4_0                         ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_JSQ_JSQ4_1                         ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_JSQ_JSQ4_2                         ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_JSQ_JSQ4_3                         ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_JSQ_JSQ4_4                         ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_JSQ_JLEN                           ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQ_JLEN_0                         ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_JSQ_JLEN_1                         ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+/*******************  Bit definition for ADC_JDOR1 register  *******************/
+#define  ADC_JDOR1_JD                           ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDOR2 register  *******************/
+#define  ADC_JDOR2_JD                           ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDOR3 register  *******************/
+#define  ADC_JDOR3_JD                           ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDOR4 register  *******************/
+#define  ADC_JDOR4_JD                           ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/********************  Bit definition for ADC_RDOR register  ********************/
+#define  ADC_RDOR_D                             ((uint32_t)0x0000FFFF)        /*!< Regular data */
+#define  ADC_RDOR_AD2D                          ((uint32_t)0xFFFF0000)        /*!< ADC2 data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DAC_CTRL register  ********************/
+#define  DAC_CTRL_EN1                           ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
+#define  DAC_CTRL_BF1                           ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
+#define  DAC_CTRL_TEN1                          ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
+
+#define  DAC_CTRL_TGSL1                         ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CTRL_TGSL1_0                       ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  DAC_CTRL_TGSL1_1                       ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  DAC_CTRL_TGSL1_2                       ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  DAC_CTRL_WAVE1                         ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CTRL_WAVE1_0                       ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  DAC_CTRL_WAVE1_1                       ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  DAC_CTRL_MAMS1                         ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CTRL_MAMS1_0                       ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  DAC_CTRL_MAMS1_1                       ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  DAC_CTRL_MAMS1_2                       ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  DAC_CTRL_MAMS1_3                       ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  DAC_CTRL_DMAEN1                        ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
+#define  DAC_CTRL_EN2                           ((uint32_t)0x00010000)        /*!< DAC channel2 enable */
+#define  DAC_CTRL_BF2                           ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */
+#define  DAC_CTRL_TEN2                          ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */
+
+#define  DAC_CTRL_TGSL2                         ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CTRL_TGSL2_0                       ((uint32_t)0x00080000)        /*!< Bit 0 */
+#define  DAC_CTRL_TGSL2_1                       ((uint32_t)0x00100000)        /*!< Bit 1 */
+#define  DAC_CTRL_TGSL2_2                       ((uint32_t)0x00200000)        /*!< Bit 2 */
+
+#define  DAC_CTRL_WAVE2                         ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CTRL_WAVE2_0                       ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  DAC_CTRL_WAVE2_1                       ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  DAC_CTRL_MAMS2                         ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CTRL_MAMS2_0                       ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  DAC_CTRL_MAMS2_1                       ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  DAC_CTRL_MAMS2_2                       ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  DAC_CTRL_MAMS2_3                       ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  DAC_CTRL_DMAEN2                        ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */
+
+/*****************  Bit definition for DAC_SWTRG register  ******************/
+#define  DAC_SWTRG_SWTRG1                       ((uint8_t)0x01)               /*!< DAC channel1 software trigger */
+#define  DAC_SWTRG_SWTRG2                       ((uint8_t)0x02)               /*!< DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_HDR12R1 register  ******************/
+#define  DAC_HDR12R1_D1HDR                      ((uint16_t)0x0FFF)            /*!< DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_HDR12L1register  ******************/
+#define  DAC_HDR12L1_D1HDR                      ((uint16_t)0xFFF0)            /*!< DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_HDR8R1 register  ******************/
+#define  DAC_HDR8R1_D1HDR                       ((uint8_t)0xFF)               /*!< DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_HDR12R2 register  ******************/
+#define  DAC_HDR12R2_D2HDR                      ((uint16_t)0x0FFF)            /*!< DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_HDR12L2 register  ******************/
+#define  DAC_HDR12L2_D2HDR                      ((uint16_t)0xFFF0)            /*!< DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_HDR8R2 register  ******************/
+#define  DAC_HDR8R2_D2HDR                       ((uint8_t)0xFF)               /*!< DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_HDR12RD register  ******************/
+#define  DAC_HDR12RD_D1HDR                      ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
+#define  DAC_HDR12RD_D2HDR                      ((uint32_t)0x0FFF0000)        /*!< DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_HDR12LD register  ******************/
+#define  DAC_HDR12LD_D1HDR                      ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
+#define  DAC_HDR12LD_D2HDR                      ((uint32_t)0xFFF00000)        /*!< DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_HDR8RD register  ******************/
+#define  DAC_HDR8RD_D1HDR                       ((uint16_t)0x00FF)            /*!< DAC channel1 8-bit Right aligned data */
+#define  DAC_HDR8RD_D2HDR                       ((uint16_t)0xFF00)            /*!< DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_ODT1 register  *******************/
+#define  DAC_ODT1_D1ODT                         ((uint16_t)0x0FFF)            /*!< DAC channel1 data output */
+
+/*******************  Bit definition for DAC_ODT2 register  *******************/
+#define  DAC_ODT2_D2ODT                         ((uint16_t)0x0FFF)            /*!< DAC channel2 data output */
+
+/********************  Bit definition for DAC_STS register  ********************/
+#define  DAC_STS_DMAUDR1                        ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
+#define  DAC_STS_DMAUDR2                        ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag */
+
+/*****************************************************************************/
+/*                                                                           */
+/*                               Timers (TMR)                                */
+/*                                                                           */
+/*****************************************************************************/
+/*******************  Bit definition for TMR_CTRL1 register  ********************/
+#define  TMR_CTRL1_CNTEN                        ((uint16_t)0x0001)            /*!< Counter enable */
+#define  TMR_CTRL1_UEVDIS                       ((uint16_t)0x0002)            /*!< Update disable */
+#define  TMR_CTRL1_UVERS                        ((uint16_t)0x0004)            /*!< Update request source */
+#define  TMR_CTRL1_OPMODE                       ((uint16_t)0x0008)            /*!< One pulse mode */
+#define  TMR_CTRL1_DIR                          ((uint16_t)0x0010)            /*!< Direction */
+
+#define  TMR_CTRL1_CMSEL                        ((uint16_t)0x0060)            /*!< CMS[1:0] bits (Center-aligned mode selection) */
+#define  TMR_CTRL1_CMSEL_0                      ((uint16_t)0x0020)            /*!< Bit 0 */
+#define  TMR_CTRL1_CMSEL_1                      ((uint16_t)0x0040)            /*!< Bit 1 */
+
+#define  TMR_CTRL1_ARPEN                        ((uint16_t)0x0080)            /*!< Auto-reload preload enable */
+
+#define  TMR_CTRL1_CLKDIV                       ((uint16_t)0x0300)            /*!< CKD[1:0] bits (clock division) */
+#define  TMR_CTRL1_CLKDIV_0                     ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TMR_CTRL1_CLKDIV_1                     ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  TMR_CTRL1_PMEN                         ((uint16_t)0x0400)            /*!< 32bit counter enable */
+
+/*******************  Bit definition for TMR_CTRL2 register  ********************/
+#define  TMR_CTRL2_CPC                          ((uint16_t)0x0001)            /*!< Capture/Compare Preloaded Control */
+#define  TMR_CTRL2_CUSEL                        ((uint16_t)0x0004)            /*!< Capture/Compare Control Update Selection */
+#define  TMR_CTRL2_CDSEL                        ((uint16_t)0x0008)            /*!< Capture/Compare DMA Selection */
+
+#define  TMR_CTRL2_MMSEL                        ((uint16_t)0x0070)            /*!< MMS[2:0] bits (Master Mode Selection) */
+#define  TMR_CTRL2_MMSEL_0                      ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TMR_CTRL2_MMSEL_1                      ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TMR_CTRL2_MMSEL_2                      ((uint16_t)0x0040)            /*!< Bit 2 */
+
+#define  TMR_CTRL2_TI1SEL                       ((uint16_t)0x0080)            /*!< TI1 Selection */
+#define  TMR_CTRL2_OC1IS                        ((uint16_t)0x0100)            /*!< Output Idle state 1 (OC1 output) */
+#define  TMR_CTRL2_OC1NIS                       ((uint16_t)0x0200)            /*!< Output Idle state 1 (OC1N output) */
+#define  TMR_CTRL2_OC2IS                        ((uint16_t)0x0400)            /*!< Output Idle state 2 (OC2 output) */
+#define  TMR_CTRL2_OC2NIS                       ((uint16_t)0x0800)            /*!< Output Idle state 2 (OC2N output) */
+#define  TMR_CTRL2_OC3IS                        ((uint16_t)0x1000)            /*!< Output Idle state 3 (OC3 output) */
+#define  TMR_CTRL2_OC3NIS                       ((uint16_t)0x2000)            /*!< Output Idle state 3 (OC3N output) */
+#define  TMR_CTRL2_OC4IS                        ((uint16_t)0x4000)            /*!< Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TMR_SMC register  *******************/
+#define  TMR_SMC_SMSEL                          ((uint16_t)0x0007)            /*!< SMS[2:0] bits (Slave mode selection) */
+#define  TMR_SMC_SMSEL_0                        ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TMR_SMC_SMSEL_1                        ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  TMR_SMC_SMSEL_2                        ((uint16_t)0x0004)            /*!< Bit 2 */
+
+#define  TMR_SMC_TRGSEL                         ((uint16_t)0x0070)            /*!< TS[2:0] bits (Trigger selection) */
+#define  TMR_SMC_TRGSEL_0                       ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TMR_SMC_TRGSEL_1                       ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TMR_SMC_TRGSEL_2                       ((uint16_t)0x0040)            /*!< Bit 2 */
+
+#define  TMR_SMC_MSMODE                         ((uint16_t)0x0080)            /*!< Master/slave mode */
+
+#define  TMR_SMC_ETDF                           ((uint16_t)0x0F00)            /*!< ETF[3:0] bits (External trigger filter) */
+#define  TMR_SMC_ETDF_0                         ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TMR_SMC_ETDF_1                         ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  TMR_SMC_ETDF_2                         ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  TMR_SMC_ETDF_3                         ((uint16_t)0x0800)            /*!< Bit 3 */
+
+#define  TMR_SMC_ETD                            ((uint16_t)0x3000)            /*!< ETPS[1:0] bits (External trigger prescaler) */
+#define  TMR_SMC_ETD_0                          ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TMR_SMC_ETD_1                          ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  TMR_SMC_ECLKEN                         ((uint16_t)0x4000)            /*!< External clock enable */
+#define  TMR_SMC_ETRGP                          ((uint16_t)0x8000)            /*!< External trigger polarity */
+
+/*******************  Bit definition for TMR_DIE register  *******************/
+#define  TMR_DIE_UEVIE                          ((uint16_t)0x0001)            /*!< Update interrupt enable */
+#define  TMR_DIE_C1IE                           ((uint16_t)0x0002)            /*!< Capture/Compare 1 interrupt enable */
+#define  TMR_DIE_C2IE                           ((uint16_t)0x0004)            /*!< Capture/Compare 2 interrupt enable */
+#define  TMR_DIE_C3IE                           ((uint16_t)0x0008)            /*!< Capture/Compare 3 interrupt enable */
+#define  TMR_DIE_C4IE                           ((uint16_t)0x0010)            /*!< Capture/Compare 4 interrupt enable */
+#define  TMR_DIE_HALLIE                         ((uint16_t)0x0020)            /*!< COM interrupt enable */
+#define  TMR_DIE_TRGIE                          ((uint16_t)0x0040)            /*!< Trigger interrupt enable */
+#define  TMR_DIE_BRKIE                          ((uint16_t)0x0080)            /*!< Break interrupt enable */
+#define  TMR_DIE_UEVDE                          ((uint16_t)0x0100)            /*!< Update DMA request enable */
+#define  TMR_DIE_C1DE                           ((uint16_t)0x0200)            /*!< Capture/Compare 1 DMA request enable */
+#define  TMR_DIE_C2DE                           ((uint16_t)0x0400)            /*!< Capture/Compare 2 DMA request enable */
+#define  TMR_DIE_C3DE                           ((uint16_t)0x0800)            /*!< Capture/Compare 3 DMA request enable */
+#define  TMR_DIE_C4DE                           ((uint16_t)0x1000)            /*!< Capture/Compare 4 DMA request enable */
+#define  TMR_DIE_HALLDE                         ((uint16_t)0x2000)            /*!< COM DMA request enable */
+#define  TMR_DIE_TRGDE                          ((uint16_t)0x4000)            /*!< Trigger DMA request enable */
+
+/********************  Bit definition for TMR_STS register  ********************/
+#define  TMR_STS_UEVIF                          ((uint16_t)0x0001)            /*!< Update interrupt Flag */
+#define  TMR_STS_C1IF                           ((uint16_t)0x0002)            /*!< Capture/Compare 1 interrupt Flag */
+#define  TMR_STS_C2IF                           ((uint16_t)0x0004)            /*!< Capture/Compare 2 interrupt Flag */
+#define  TMR_STS_C3IF                           ((uint16_t)0x0008)            /*!< Capture/Compare 3 interrupt Flag */
+#define  TMR_STS_C4IF                           ((uint16_t)0x0010)            /*!< Capture/Compare 4 interrupt Flag */
+#define  TMR_STS_HALLIF                         ((uint16_t)0x0020)            /*!< COM interrupt Flag */
+#define  TMR_STS_TRGIF                          ((uint16_t)0x0040)            /*!< Trigger interrupt Flag */
+#define  TMR_STS_BRKIF                          ((uint16_t)0x0080)            /*!< Break interrupt Flag */
+#define  TMR_STS_C1OF                           ((uint16_t)0x0200)            /*!< Capture/Compare 1 Overcapture Flag */
+#define  TMR_STS_C2OF                           ((uint16_t)0x0400)            /*!< Capture/Compare 2 Overcapture Flag */
+#define  TMR_STS_C3OF                           ((uint16_t)0x0800)            /*!< Capture/Compare 3 Overcapture Flag */
+#define  TMR_STS_C4OF                           ((uint16_t)0x1000)            /*!< Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TMR_EVEG register  ********************/
+#define  TMR_EVEG_UEVG                          ((uint8_t)0x01)               /*!< Update Generation */
+#define  TMR_EVEG_C1G                           ((uint8_t)0x02)               /*!< Capture/Compare 1 Generation */
+#define  TMR_EVEG_C2G                           ((uint8_t)0x04)               /*!< Capture/Compare 2 Generation */
+#define  TMR_EVEG_C3G                           ((uint8_t)0x08)               /*!< Capture/Compare 3 Generation */
+#define  TMR_EVEG_C4G                           ((uint8_t)0x10)               /*!< Capture/Compare 4 Generation */
+#define  TMR_EVEG_HALLG                         ((uint8_t)0x20)               /*!< Capture/Compare Control Update Generation */
+#define  TMR_EVEG_TRGG                          ((uint8_t)0x40)               /*!< Trigger Generation */
+#define  TMR_EVEG_BRKG                          ((uint8_t)0x80)               /*!< Break Generation */
+
+/******************  Bit definition for TMR_CCM1 register  *******************/
+#define  TMR_CCM1_C1SEL                         ((uint16_t)0x0003)            /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TMR_CCM1_C1SEL_0                       ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TMR_CCM1_C1SEL_1                       ((uint16_t)0x0002)            /*!< Bit 1 */
+
+#define  TMR_CCM1_OC1FEN                        ((uint16_t)0x0004)            /*!< Output Compare 1 Fast enable */
+#define  TMR_CCM1_OC1PEN                        ((uint16_t)0x0008)            /*!< Output Compare 1 Preload enable */
+
+#define  TMR_CCM1_OC1MODE                       ((uint16_t)0x0070)            /*!< OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TMR_CCM1_OC1MODE_0                     ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TMR_CCM1_OC1MODE_1                     ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TMR_CCM1_OC1MODE_2                     ((uint16_t)0x0040)            /*!< Bit 2 */
+
+#define  TMR_CCM1_C1CDIS                        ((uint16_t)0x0080)            /*!< Output Compare 1Clear Enable */
+
+#define  TMR_CCM1_C2SEL                         ((uint16_t)0x0300)            /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TMR_CCM1_C2SEL_0                       ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TMR_CCM1_C2SEL_1                       ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  TMR_CCM1_OC2FNE                        ((uint16_t)0x0400)            /*!< Output Compare 2 Fast enable */
+#define  TMR_CCM1_OC2PEN                        ((uint16_t)0x0800)            /*!< Output Compare 2 Preload enable */
+
+#define  TMR_CCM1_OC2MODE                       ((uint16_t)0x7000)            /*!< OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TMR_CCM1_OC2MODE_0                     ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TMR_CCM1_OC2MODE_1                     ((uint16_t)0x2000)            /*!< Bit 1 */
+#define  TMR_CCM1_OC2MODE_2                     ((uint16_t)0x4000)            /*!< Bit 2 */
+
+#define  TMR_CCM1_OC2CDIS                       ((uint16_t)0x8000)            /*!< Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TMR_CCM1_IC1DIV                        ((uint16_t)0x000C)            /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TMR_CCM1_IC1DIV_0                      ((uint16_t)0x0004)            /*!< Bit 0 */
+#define  TMR_CCM1_IC1DIV_1                      ((uint16_t)0x0008)            /*!< Bit 1 */
+
+#define  TMR_CCM1_IC1F                          ((uint16_t)0x00F0)            /*!< IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TMR_CCM1_IC1F_0                        ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TMR_CCM1_IC1F_1                        ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TMR_CCM1_IC1F_2                        ((uint16_t)0x0040)            /*!< Bit 2 */
+#define  TMR_CCM1_IC1F_3                        ((uint16_t)0x0080)            /*!< Bit 3 */
+
+#define  TMR_CCM1_IC2DIV                        ((uint16_t)0x0C00)            /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TMR_CCM1_IC2DIV_0                      ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  TMR_CCM1_IC2DIVC_1                     ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  TMR_CCM1_IC2DF                         ((uint16_t)0xF000)            /*!< IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TMR_CCM1_IC2DF_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TMR_CCM1_IC2DF_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+#define  TMR_CCM1_IC2DF_2                       ((uint16_t)0x4000)            /*!< Bit 2 */
+#define  TMR_CCM1_IC2DF_3                       ((uint16_t)0x8000)            /*!< Bit 3 */
+
+/******************  Bit definition for TMR_CCM2 register  *******************/
+#define  TMR_CCM2_C3SEL                         ((uint16_t)0x0003)            /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TMR_CCM2_C3SEL_0                       ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TMR_CCM2_C3SEL_1                       ((uint16_t)0x0002)            /*!< Bit 1 */
+
+#define  TMR_CCM2_OC3FEN                        ((uint16_t)0x0004)            /*!< Output Compare 3 Fast enable */
+#define  TMR_CCM2_OC3PEN                        ((uint16_t)0x0008)            /*!< Output Compare 3 Preload enable */
+
+#define  TMR_CCM2_OC3MODE                       ((uint16_t)0x0070)            /*!< OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TMR_CCM2_OC3MODE_0                     ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TMR_CCM2_OC3MODE_1                     ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TMR_CCM2_OC3MODE_2                     ((uint16_t)0x0040)            /*!< Bit 2 */
+
+#define  TMR_CCM2_OC3CDIS                       ((uint16_t)0x0080)            /*!< Output Compare 3 Clear Enable */
+
+#define  TMR_CCM2_CC4S                          ((uint16_t)0x0300)            /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TMR_CCM2_CC4S_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TMR_CCM2_CC4S_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  TMR_CCM2_OC4FE                         ((uint16_t)0x0400)            /*!< Output Compare 4 Fast enable */
+#define  TMR_CCM2_OC4PE                         ((uint16_t)0x0800)            /*!< Output Compare 4 Preload enable */
+
+#define  TMR_CCM2_OC4MODE                       ((uint16_t)0x7000)            /*!< OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TMR_CCM2_OC4MODE_0                     ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TMR_CCM2_OC4MODE_1                     ((uint16_t)0x2000)            /*!< Bit 1 */
+#define  TMR_CCM2_OC4MODE_2                     ((uint16_t)0x4000)            /*!< Bit 2 */
+
+#define  TMR_CCM2_OC4CDIS                       ((uint16_t)0x8000)            /*!< Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TMR_CCM2_IC3DIV                        ((uint16_t)0x000C)            /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TMR_CCM2_IC3DIV_0                      ((uint16_t)0x0004)            /*!< Bit 0 */
+#define  TMR_CCM2_IC3DIV_1                      ((uint16_t)0x0008)            /*!< Bit 1 */
+
+#define  TMR_CCM2_IC3DF                         ((uint16_t)0x00F0)            /*!< IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TMR_CCM2_IC3DF_0                       ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TMR_CCM2_IC3DF_1                       ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TMR_CCM2_IC3DF_2                       ((uint16_t)0x0040)            /*!< Bit 2 */
+#define  TMR_CCM2_IC3DF_3                       ((uint16_t)0x0080)            /*!< Bit 3 */
+
+#define  TMR_CCM2_IC4DIV                        ((uint16_t)0x0C00)            /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TMR_CCM2_IC4DIV_0                      ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  TMR_CCM2_IC4DIV_1                      ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  TMR_CCM2_IC4DF                         ((uint16_t)0xF000)            /*!< IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TMR_CCM2_IC4DF_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TMR_CCM2_IC4DF_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+#define  TMR_CCM2_IC4DF_2                       ((uint16_t)0x4000)            /*!< Bit 2 */
+#define  TMR_CCM2_IC4DF_3                       ((uint16_t)0x8000)            /*!< Bit 3 */
+
+/*******************  Bit definition for TMR_CCE register  *******************/
+#define  TMR_CCE_C1EN                           ((uint16_t)0x0001)            /*!< Capture/Compare 1 output enable */
+#define  TMR_CCE_C1P                            ((uint16_t)0x0002)            /*!< Capture/Compare 1 output Polarity */
+#define  TMR_CCE_C1NEN                           ((uint16_t)0x0004)            /*!< Capture/Compare 1 Complementary output enable */
+#define  TMR_CCE_C1NP                           ((uint16_t)0x0008)            /*!< Capture/Compare 1 Complementary output Polarity */
+#define  TMR_CCE_C2EN                           ((uint16_t)0x0010)            /*!< Capture/Compare 2 output enable */
+#define  TMR_CCE_C2P                            ((uint16_t)0x0020)            /*!< Capture/Compare 2 output Polarity */
+#define  TMR_CCE_C2NEN                          ((uint16_t)0x0040)            /*!< Capture/Compare 2 Complementary output enable */
+#define  TMR_CCE_C2NP                           ((uint16_t)0x0080)            /*!< Capture/Compare 2 Complementary output Polarity */
+#define  TMR_CCE_C3EN                           ((uint16_t)0x0100)            /*!< Capture/Compare 3 output enable */
+#define  TMR_CCE_C3P                            ((uint16_t)0x0200)            /*!< Capture/Compare 3 output Polarity */
+#define  TMR_CCE_C3NEN                          ((uint16_t)0x0400)            /*!< Capture/Compare 3 Complementary output enable */
+#define  TMR_CCE_C3NP                           ((uint16_t)0x0800)            /*!< Capture/Compare 3 Complementary output Polarity */
+#define  TMR_CCE_C4EN                           ((uint16_t)0x1000)            /*!< Capture/Compare 4 output enable */
+#define  TMR_CCE_C4P                            ((uint16_t)0x2000)            /*!< Capture/Compare 4 output Polarity */
+#define  TMR_CCE_C4NP                           ((uint16_t)0x8000)            /*!< Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TMR_CNT register  ********************/
+#define  TMR_CNT_CNT                            ((uint16_t)0xFFFF)            /*!< Counter Value */
+
+/*******************  Bit definition for TMR_DIV register  ********************/
+#define  TMR_DIV_DIV                            ((uint16_t)0xFFFF)            /*!< Prescaler Value */
+
+/*******************  Bit definition for TMR_AR register  ********************/
+#define  TMR_AR_AR                              ((uint16_t)0xFFFF)            /*!< actual auto-reload Value */
+
+/*******************  Bit definition for TMR_RC register  ********************/
+#define  TMR_RC_RC                              ((uint8_t)0xFF)               /*!< Repetition Counter Value */
+
+/*******************  Bit definition for TMR_CC1 register  *******************/
+#define  TMR_CC1_CC1                            ((uint16_t)0xFFFF)            /*!< Capture/Compare 1 Value */
+
+/*******************  Bit definition for TMR_CC2 register  *******************/
+#define  TMR_CC2_CC2                            ((uint16_t)0xFFFF)            /*!< Capture/Compare 2 Value */
+
+/*******************  Bit definition for TMR_CC3 register  *******************/
+#define  TMR_CC3_CC3                            ((uint16_t)0xFFFF)            /*!< Capture/Compare 3 Value */
+
+/*******************  Bit definition for TMR_CC4 register  *******************/
+#define  TMR_CC4_CC4                            ((uint16_t)0xFFFF)            /*!< Capture/Compare 4 Value */
+
+/*******************  Bit definition for TMR_BRKDT register  *******************/
+#define  TMR_BRKDT_DTGS                         ((uint16_t)0x00FF)            /*!< DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TMR_BRKDT_DTGS_0                       ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TMR_BRKDT_DTGS_1                       ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  TMR_BRKDT_DTGS_2                       ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  TMR_BRKDT_DTGS_3                       ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  TMR_BRKDT_DTGS_4                       ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  TMR_BRKDT_DTGS_5                       ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  TMR_BRKDT_DTGS_6                       ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  TMR_BRKDT_DTGS_7                       ((uint16_t)0x0080)            /*!< Bit 7 */
+
+#define  TMR_BRKDT_LOCKC                        ((uint16_t)0x0300)            /*!< LOCK[1:0] bits (Lock Configuration) */
+#define  TMR_BRKDT_LOCKC_0                      ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TMR_BRKDT_LOCKC_1                      ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  TMR_BRKDT_OSIMI                        ((uint16_t)0x0400)            /*!< Off-State Selection for Idle mode */
+#define  TMR_BRKDT_OSIMR                        ((uint16_t)0x0800)            /*!< Off-State Selection for Run mode */
+#define  TMR_BRKDT_BRKEN                        ((uint16_t)0x1000)            /*!< Break enable */
+#define  TMR_BRKDT_BRKP                         ((uint16_t)0x2000)            /*!< Break Polarity */
+#define  TMR_BRKDT_AOEN                         ((uint16_t)0x4000)            /*!< Automatic Output enable */
+#define  TMR_BRKDT_MOEN                         ((uint16_t)0x8000)            /*!< Main Output enable */
+
+/*******************  Bit definition for TMR_DMAC register  ********************/
+#define  TMR_DMAC_ADDR                          ((uint16_t)0x001F)            /*!< DBA[4:0] bits (DMA Base Address) */
+#define  TMR_DMAC_ADDR_0                        ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TMR_DMAC_ADDR_1                        ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  TMR_DMAC_ADDR_2                        ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  TMR_DMAC_ADDR_3                        ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  TMR_DMAC_ADDR_4                        ((uint16_t)0x0010)            /*!< Bit 4 */
+
+#define  TMR_DMAC_DBLEN                         ((uint16_t)0x1F00)            /*!< DBL[4:0] bits (DMA Burst Length) */
+#define  TMR_DMAC_DBLEN_0                       ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TMR_DMAC_DBLEN_1                       ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  TMR_DMAC_DBLEN_2                       ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  TMR_DMAC_DBLEN_3                       ((uint16_t)0x0800)            /*!< Bit 3 */
+#define  TMR_DMAC_DBLEN_4                       ((uint16_t)0x1000)            /*!< Bit 4 */
+
+/*******************  Bit definition for TMR_DMABA register  *******************/
+#define  TMR_DMABA_DMABA                    ((uint16_t)0xFFFF)            /*!< DMA register for burst accesses */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Real-Time Clock                                */
+/*                                                                            */
+/******************************************************************************/
+#if defined (AT32F415xx)
+/********************  Bits definition for ERTC_TIME register  *******************/
+#define ERTC_TIME_AMPM                          ((uint32_t)0x00400000)
+#define ERTC_TIME_HT                            ((uint32_t)0x00300000)
+#define ERTC_TIME_HT_0                          ((uint32_t)0x00100000)
+#define ERTC_TIME_HT_1                          ((uint32_t)0x00200000)
+#define ERTC_TIME_HU                            ((uint32_t)0x000F0000)
+#define ERTC_TIME_HU_0                          ((uint32_t)0x00010000)
+#define ERTC_TIME_HU_1                          ((uint32_t)0x00020000)
+#define ERTC_TIME_HU_2                          ((uint32_t)0x00040000)
+#define ERTC_TIME_HU_3                          ((uint32_t)0x00080000)
+#define ERTC_TIME_MT                            ((uint32_t)0x00007000)
+#define ERTC_TIME_MT_0                          ((uint32_t)0x00001000)
+#define ERTC_TIME_MT_1                          ((uint32_t)0x00002000)
+#define ERTC_TIME_MT_2                          ((uint32_t)0x00004000)
+#define ERTC_TIME_MU                            ((uint32_t)0x00000F00)
+#define ERTC_TIME_MU_0                          ((uint32_t)0x00000100)
+#define ERTC_TIME_MU_1                          ((uint32_t)0x00000200)
+#define ERTC_TIME_MU_2                          ((uint32_t)0x00000400)
+#define ERTC_TIME_MU_3                          ((uint32_t)0x00000800)
+#define ERTC_TIME_ST                            ((uint32_t)0x00000070)
+#define ERTC_TIME_ST_0                          ((uint32_t)0x00000010)
+#define ERTC_TIME_ST_1                          ((uint32_t)0x00000020)
+#define ERTC_TIME_ST_2                          ((uint32_t)0x00000040)
+#define ERTC_TIME_SU                            ((uint32_t)0x0000000F)
+#define ERTC_TIME_SU_0                          ((uint32_t)0x00000001)
+#define ERTC_TIME_SU_1                          ((uint32_t)0x00000002)
+#define ERTC_TIME_SU_2                          ((uint32_t)0x00000004)
+#define ERTC_TIME_SU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for ERTC_DATE register  *******************/
+#define ERTC_DATE_YT                            ((uint32_t)0x00F00000)
+#define ERTC_DATE_YT_0                          ((uint32_t)0x00100000)
+#define ERTC_DATE_YT_1                          ((uint32_t)0x00200000)
+#define ERTC_DATE_YT_2                          ((uint32_t)0x00400000)
+#define ERTC_DATE_YT_3                          ((uint32_t)0x00800000)
+#define ERTC_DATE_YU                            ((uint32_t)0x000F0000)
+#define ERTC_DATE_YU_0                          ((uint32_t)0x00010000)
+#define ERTC_DATE_YU_1                          ((uint32_t)0x00020000)
+#define ERTC_DATE_YU_2                          ((uint32_t)0x00040000)
+#define ERTC_DATE_YU_3                          ((uint32_t)0x00080000)
+#define ERTC_DATE_WK                            ((uint32_t)0x0000E000)
+#define ERTC_DATE_WK_0                          ((uint32_t)0x00002000)
+#define ERTC_DATE_WK_1                          ((uint32_t)0x00004000)
+#define ERTC_DATE_WK_2                          ((uint32_t)0x00008000)
+#define ERTC_DATE_MT                            ((uint32_t)0x00001000)
+#define ERTC_DATE_MU                            ((uint32_t)0x00000F00)
+#define ERTC_DATE_MU_0                          ((uint32_t)0x00000100)
+#define ERTC_DATE_MU_1                          ((uint32_t)0x00000200)
+#define ERTC_DATE_MU_2                          ((uint32_t)0x00000400)
+#define ERTC_DATE_MU_3                          ((uint32_t)0x00000800)
+#define ERTC_DATE_DT                            ((uint32_t)0x00000030)
+#define ERTC_DATE_DT_0                          ((uint32_t)0x00000010)
+#define ERTC_DATE_DT_1                          ((uint32_t)0x00000020)
+#define ERTC_DATE_DU                            ((uint32_t)0x0000000F)
+#define ERTC_DATE_DU_0                          ((uint32_t)0x00000001)
+#define ERTC_DATE_DU_1                          ((uint32_t)0x00000002)
+#define ERTC_DATE_DU_2                          ((uint32_t)0x00000004)
+#define ERTC_DATE_DU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for ERTC_CTRL register  *******************/
+#define ERTC_CTRL_CALOE                         ((uint32_t)0x00800000)
+#define ERTC_CTRL_OSEL                          ((uint32_t)0x00600000)
+#define ERTC_CTRL_OSEL_0                        ((uint32_t)0x00200000)
+#define ERTC_CTRL_OSEL_1                        ((uint32_t)0x00400000)
+#define ERTC_CTRL_OPOL                          ((uint32_t)0x00100000)
+#define ERTC_CTRL_CALSEL                        ((uint32_t)0x00080000)
+#define ERTC_CTRL_BKP                           ((uint32_t)0x00040000)
+#define ERTC_CTRL_SUB1H                         ((uint32_t)0x00020000)
+#define ERTC_CTRL_ADD1H                         ((uint32_t)0x00010000)
+#define ERTC_CTRL_TSIE                          ((uint32_t)0x00008000)
+#define ERTC_CTRL_WATIE                         ((uint32_t)0x00004000)
+#define ERTC_CTRL_ALBIE                         ((uint32_t)0x00002000)
+#define ERTC_CTRL_ALAIE                         ((uint32_t)0x00001000)
+#define ERTC_CTRL_TSE                           ((uint32_t)0x00000800)
+#define ERTC_CTRL_WATE                          ((uint32_t)0x00000400)
+#define ERTC_CTRL_ALBE                          ((uint32_t)0x00000200)
+#define ERTC_CTRL_ALAE                          ((uint32_t)0x00000100)
+#define ERTC_CTRL_CDCE                          ((uint32_t)0x00000080)
+#define ERTC_CTRL_HFM                           ((uint32_t)0x00000040)
+#define ERTC_CTRL_BYPSHDW                       ((uint32_t)0x00000020)
+#define ERTC_CTRL_RFCKON                        ((uint32_t)0x00000010)
+#define ERTC_CTRL_TSEDGE                        ((uint32_t)0x00000008)
+#define ERTC_CTRL_WACKSEL                       ((uint32_t)0x00000007)
+#define ERTC_CTRL_WACKSEL_0                     ((uint32_t)0x00000001)
+#define ERTC_CTRL_WACKSEL_1                     ((uint32_t)0x00000002)
+#define ERTC_CTRL_WACKSEL_2                     ((uint32_t)0x00000004)
+
+/********************  Bits definition for ERTC_ISTS register  ******************/
+#define ERTC_ISTS_RECALPDF                      ((uint32_t)0x00010000)
+#define ERTC_ISTS_TPF                           ((uint32_t)0x00002000)
+#define ERTC_ISTS_TP2F                          ((uint32_t)0x00004000)
+#define ERTC_ISTS_TSOF                          ((uint32_t)0x00001000)
+#define ERTC_ISTS_TSF                           ((uint32_t)0x00000800)
+#define ERTC_ISTS_WATF                          ((uint32_t)0x00000400)
+#define ERTC_ISTS_ALBF                          ((uint32_t)0x00000200)
+#define ERTC_ISTS_ALAF                          ((uint32_t)0x00000100)
+#define ERTC_ISTS_INITM                         ((uint32_t)0x00000080)
+#define ERTC_ISTS_INITF                         ((uint32_t)0x00000040)
+#define ERTC_ISTS_RSF                           ((uint32_t)0x00000020)
+#define ERTC_ISTS_INITS                         ((uint32_t)0x00000010)
+#define ERTC_ISTS_SFP                           ((uint32_t)0x00000008)
+#define ERTC_ISTS_WATWF                         ((uint32_t)0x00000004)
+#define ERTC_ISTS_ALBWF                         ((uint32_t)0x00000002)
+#define ERTC_ISTS_ALAWF                         ((uint32_t)0x00000001)
+
+/********************  Bits definition for ERTC_PSC register  *****************/
+#define ERTC_PSC_PRDIV_A                        ((uint32_t)0x007F0000)
+#define ERTC_PSC_PRDIV_S                        ((uint32_t)0x00001FFF)
+
+/********************  Bits definition for ERTC_WATR register  *****************/
+#define ERTC_WATR_WAREV                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for ERTC_CAL register  ***************/
+#define ERTC_CAL_DCALS                          ((uint32_t)0x00000080)
+#define ERTC_CAL_DCAL                           ((uint32_t)0x0000001F)
+
+/********************  Bits definition for ERTC_ALA register  ***************/
+#define ERTC_ALA_MASK4                          ((uint32_t)0x80000000)
+#define ERTC_ALA_WKSEL                          ((uint32_t)0x40000000)
+#define ERTC_ALA_DT                             ((uint32_t)0x30000000)
+#define ERTC_ALA_DT_0                           ((uint32_t)0x10000000)
+#define ERTC_ALA_DT_1                           ((uint32_t)0x20000000)
+#define ERTC_ALA_DU                             ((uint32_t)0x0F000000)
+#define ERTC_ALA_DU_0                           ((uint32_t)0x01000000)
+#define ERTC_ALA_DU_1                           ((uint32_t)0x02000000)
+#define ERTC_ALA_DU_2                           ((uint32_t)0x04000000)
+#define ERTC_ALA_DU_3                           ((uint32_t)0x08000000)
+#define ERTC_ALA_MASK3                          ((uint32_t)0x00800000)
+#define ERTC_ALA_AMPM                           ((uint32_t)0x00400000)
+#define ERTC_ALA_HT                             ((uint32_t)0x00300000)
+#define ERTC_ALA_HT_0                           ((uint32_t)0x00100000)
+#define ERTC_ALA_HT_1                           ((uint32_t)0x00200000)
+#define ERTC_ALA_HU                             ((uint32_t)0x000F0000)
+#define ERTC_ALA_HU_0                           ((uint32_t)0x00010000)
+#define ERTC_ALA_HU_1                           ((uint32_t)0x00020000)
+#define ERTC_ALA_HU_2                           ((uint32_t)0x00040000)
+#define ERTC_ALA_HU_3                           ((uint32_t)0x00080000)
+#define ERTC_ALA_MASK2                          ((uint32_t)0x00008000)
+#define ERTC_ALA_MT                             ((uint32_t)0x00007000)
+#define ERTC_ALA_MT_0                           ((uint32_t)0x00001000)
+#define ERTC_ALA_MT_1                           ((uint32_t)0x00002000)
+#define ERTC_ALA_MT_2                           ((uint32_t)0x00004000)
+#define ERTC_ALA_MU                             ((uint32_t)0x00000F00)
+#define ERTC_ALA_MU_0                           ((uint32_t)0x00000100)
+#define ERTC_ALA_MU_1                           ((uint32_t)0x00000200)
+#define ERTC_ALA_MU_2                           ((uint32_t)0x00000400)
+#define ERTC_ALA_MU_3                           ((uint32_t)0x00000800)
+#define ERTC_ALA_MASK1                          ((uint32_t)0x00000080)
+#define ERTC_ALA_ST                             ((uint32_t)0x00000070)
+#define ERTC_ALA_ST_0                           ((uint32_t)0x00000010)
+#define ERTC_ALA_ST_1                           ((uint32_t)0x00000020)
+#define ERTC_ALA_ST_2                           ((uint32_t)0x00000040)
+#define ERTC_ALA_SU                             ((uint32_t)0x0000000F)
+#define ERTC_ALA_SU_0                           ((uint32_t)0x00000001)
+#define ERTC_ALA_SU_1                           ((uint32_t)0x00000002)
+#define ERTC_ALA_SU_2                           ((uint32_t)0x00000004)
+#define ERTC_ALA_SU_3                           ((uint32_t)0x00000008)
+
+/********************  Bits definition for ERTC_ALB register  ***************/
+#define ERTC_ALB_MASK4                          ((uint32_t)0x80000000)
+#define ERTC_ALB_WKSEL                          ((uint32_t)0x40000000)
+#define ERTC_ALB_DT                             ((uint32_t)0x30000000)
+#define ERTC_ALB_DT_0                           ((uint32_t)0x10000000)
+#define ERTC_ALB_DT_1                           ((uint32_t)0x20000000)
+#define ERTC_ALB_DU                             ((uint32_t)0x0F000000)
+#define ERTC_ALB_DU_0                           ((uint32_t)0x01000000)
+#define ERTC_ALB_DU_1                           ((uint32_t)0x02000000)
+#define ERTC_ALB_DU_2                           ((uint32_t)0x04000000)
+#define ERTC_ALB_DU_3                           ((uint32_t)0x08000000)
+#define ERTC_ALB_MASK3                          ((uint32_t)0x00800000)
+#define ERTC_ALB_AMPM                           ((uint32_t)0x00400000)
+#define ERTC_ALB_HT                             ((uint32_t)0x00300000)
+#define ERTC_ALB_HT_0                           ((uint32_t)0x00100000)
+#define ERTC_ALB_HT_1                           ((uint32_t)0x00200000)
+#define ERTC_ALB_HU                             ((uint32_t)0x000F0000)
+#define ERTC_ALB_HU_0                           ((uint32_t)0x00010000)
+#define ERTC_ALB_HU_1                           ((uint32_t)0x00020000)
+#define ERTC_ALB_HU_2                           ((uint32_t)0x00040000)
+#define ERTC_ALB_HU_3                           ((uint32_t)0x00080000)
+#define ERTC_ALB_MASK2                          ((uint32_t)0x00008000)
+#define ERTC_ALB_MT                             ((uint32_t)0x00007000)
+#define ERTC_ALB_MT_0                           ((uint32_t)0x00001000)
+#define ERTC_ALB_MT_1                           ((uint32_t)0x00002000)
+#define ERTC_ALB_MT_2                           ((uint32_t)0x00004000)
+#define ERTC_ALB_MU                             ((uint32_t)0x00000F00)
+#define ERTC_ALB_MU_0                           ((uint32_t)0x00000100)
+#define ERTC_ALB_MU_1                           ((uint32_t)0x00000200)
+#define ERTC_ALB_MU_2                           ((uint32_t)0x00000400)
+#define ERTC_ALB_MU_3                           ((uint32_t)0x00000800)
+#define ERTC_ALB_MASK1                          ((uint32_t)0x00000080)
+#define ERTC_ALB_ST                             ((uint32_t)0x00000070)
+#define ERTC_ALB_ST_0                           ((uint32_t)0x00000010)
+#define ERTC_ALB_ST_1                           ((uint32_t)0x00000020)
+#define ERTC_ALB_ST_2                           ((uint32_t)0x00000040)
+#define ERTC_ALA_SU                             ((uint32_t)0x0000000F)
+#define ERTC_ALA_SU_0                           ((uint32_t)0x00000001)
+#define ERTC_ALA_SU_1                           ((uint32_t)0x00000002)
+#define ERTC_ALA_SU_2                           ((uint32_t)0x00000004)
+#define ERTC_ALA_SU_3                           ((uint32_t)0x00000008)
+
+/********************  Bits definition for ERTC_WPR register  ******************/
+#define ERTC_WPR_KEY                            ((uint32_t)0x000000FF)
+
+/********************  Bits definition for ERTC_SBSR register  ******************/
+#define ERTC_SBSR_SBS                           ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for ERTC_SFCTR register  ***************/
+#define ERTC_SFCTR_SUBSBS                       ((uint32_t)0x00007FFF)
+#define ERTC_SFCTR_ADD1S                        ((uint32_t)0x80000000)
+
+/********************  Bits definition for ERTC_TSTM register  *****************/
+#define ERTC_TSTM_AMPM                          ((uint32_t)0x00400000)
+#define ERTC_TSTM_HT                            ((uint32_t)0x00300000)
+#define ERTC_TSTM_HT_0                          ((uint32_t)0x00100000)
+#define ERTC_TSTM_HT_1                          ((uint32_t)0x00200000)
+#define ERTC_TSTM_HU                            ((uint32_t)0x000F0000)
+#define ERTC_TSTM_HU_0                          ((uint32_t)0x00010000)
+#define ERTC_TSTM_HU_1                          ((uint32_t)0x00020000)
+#define ERTC_TSTM_HU_2                          ((uint32_t)0x00040000)
+#define ERTC_TSTM_HU_3                          ((uint32_t)0x00080000)
+#define ERTC_TSTM_MT                            ((uint32_t)0x00007000)
+#define ERTC_TSTM_MT_0                          ((uint32_t)0x00001000)
+#define ERTC_TSTM_MT_1                          ((uint32_t)0x00002000)
+#define ERTC_TSTM_MT_2                          ((uint32_t)0x00004000)
+#define ERTC_TSTM_MU                            ((uint32_t)0x00000F00)
+#define ERTC_TSTM_MU_0                          ((uint32_t)0x00000100)
+#define ERTC_TSTM_MU_1                          ((uint32_t)0x00000200)
+#define ERTC_TSTM_MU_2                          ((uint32_t)0x00000400)
+#define ERTC_TSTM_MU_3                          ((uint32_t)0x00000800)
+#define ERTC_TSTM_ST                            ((uint32_t)0x00000070)
+#define ERTC_TSTM_ST_0                          ((uint32_t)0x00000010)
+#define ERTC_TSTM_ST_1                          ((uint32_t)0x00000020)
+#define ERTC_TSTM_ST_2                          ((uint32_t)0x00000040)
+#define ERTC_TSTM_SU                            ((uint32_t)0x0000000F)
+#define ERTC_TSTM_SU_0                          ((uint32_t)0x00000001)
+#define ERTC_TSTM_SU_1                          ((uint32_t)0x00000002)
+#define ERTC_TSTM_SU_2                          ((uint32_t)0x00000004)
+#define ERTC_TSTM_SU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for ERTC_TSDT register  *****************/
+#define ERTC_TSDT_WK                            ((uint32_t)0x0000E000)
+#define ERTC_TSDT_WK_0                          ((uint32_t)0x00002000)
+#define ERTC_TSDT_WK_1                          ((uint32_t)0x00004000)
+#define ERTC_TSDT_WK_2                          ((uint32_t)0x00008000)
+#define ERTC_TSDT_MT                            ((uint32_t)0x00001000)
+#define ERTC_TSDT_MU                            ((uint32_t)0x00000F00)
+#define ERTC_TSDT_MU_0                          ((uint32_t)0x00000100)
+#define ERTC_TSDT_MU_1                          ((uint32_t)0x00000200)
+#define ERTC_TSDT_MU_2                          ((uint32_t)0x00000400)
+#define ERTC_TSDT_MU_3                          ((uint32_t)0x00000800)
+#define ERTC_TSDT_DT                            ((uint32_t)0x00000030)
+#define ERTC_TSDT_DT_0                          ((uint32_t)0x00000010)
+#define ERTC_TSDT_DT_1                          ((uint32_t)0x00000020)
+#define ERTC_TSDT_DU                            ((uint32_t)0x0000000F)
+#define ERTC_TSDT_DU_0                          ((uint32_t)0x00000001)
+#define ERTC_TSDT_DU_1                          ((uint32_t)0x00000002)
+#define ERTC_TSDT_DU_2                          ((uint32_t)0x00000004)
+#define ERTC_TSDT_DU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for ERTC_TSSBS register  ****************/
+#define ERTC_TSSBS_SBS                          ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for ERTC_CCR register  *****************/
+#define ERTC_CCR_CALAD                          ((uint32_t)0x00008000)
+#define ERTC_CCR_CAL8                           ((uint32_t)0x00004000)
+#define ERTC_CCR_CAL16                          ((uint32_t)0x00002000)
+#define ERTC_CCR_CALM                           ((uint32_t)0x000001FF)
+#define ERTC_CCR_CALM_0                         ((uint32_t)0x00000001)
+#define ERTC_CCR_CALM_1                         ((uint32_t)0x00000002)
+#define ERTC_CCR_CALM_2                         ((uint32_t)0x00000004)
+#define ERTC_CCR_CALM_3                         ((uint32_t)0x00000008)
+#define ERTC_CCR_CALM_4                         ((uint32_t)0x00000010)
+#define ERTC_CCR_CALM_5                         ((uint32_t)0x00000020)
+#define ERTC_CCR_CALM_6                         ((uint32_t)0x00000040)
+#define ERTC_CCR_CALM_7                         ((uint32_t)0x00000080)
+#define ERTC_CCR_CALM_8                         ((uint32_t)0x00000100)
+
+/********************  Bits definition for ERTC_TPAF register  ****************/
+#define ERTC_TPAF_ALAOUTTYPE                    ((uint32_t)0x00040000)
+#define ERTC_TPAF_TSINSEL                       ((uint32_t)0x00020000)
+#define ERTC_TPAF_TMPINSEL                      ((uint32_t)0x00010000)
+#define ERTC_TPAF_TMPUDIS                       ((uint32_t)0x00008000)
+#define ERTC_TPAF_TMPRCH                        ((uint32_t)0x00006000)
+#define ERTC_TPAF_TMPRCH_0                      ((uint32_t)0x00002000)
+#define ERTC_TPAF_TMPRCH_1                      ((uint32_t)0x00004000)
+#define ERTC_TPAF_TMFLT                         ((uint32_t)0x00001800)
+#define ERTC_TPAF_TMFLT_0                       ((uint32_t)0x00000800)
+#define ERTC_TPAF_TMFLT_1                       ((uint32_t)0x00001000)
+#define ERTC_TPAF_TMFREQ                        ((uint32_t)0x00000700)
+#define ERTC_TPAF_TMFREQ_0                      ((uint32_t)0x00000100)
+#define ERTC_TPAF_TMFREQ_1                      ((uint32_t)0x00000200)
+#define ERTC_TPAF_TMFREQ_2                      ((uint32_t)0x00000400)
+#define ERTC_TPAF_TMTS                          ((uint32_t)0x00000080)
+#define ERTC_TPAF_TM2TRG                        ((uint32_t)0x00000010)
+#define ERTC_TPAF_TM2E                          ((uint32_t)0x00000008) 
+#define ERTC_TPAF_TMIE                          ((uint32_t)0x00000004)
+#define ERTC_TPAF_TM1TRG                        ((uint32_t)0x00000002)
+#define ERTC_TPAF_TM1E                          ((uint32_t)0x00000001)
+
+/********************  Bits definition for ERTC_ALASBS register  *************/
+#define ERTC_ALASBS_MASKSBS                     ((uint32_t)0x0F000000)
+#define ERTC_ALASBS_MASKSBS_0                   ((uint32_t)0x01000000)
+#define ERTC_ALASBS_MASKSBS_1                   ((uint32_t)0x02000000)
+#define ERTC_ALASBS_MASKSBS_2                   ((uint32_t)0x04000000)
+#define ERTC_ALASBS_MASKSBS_3                   ((uint32_t)0x08000000)
+#define ERTC_ALASBS_SBS                         ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for ERTC_ALBSBS register  *************/
+#define ERTC_ALBSBS_MASKSBS                     ((uint32_t)0x0F000000)
+#define ERTC_ALBSBS_MASKSBS_0                   ((uint32_t)0x01000000)
+#define ERTC_ALBSBS_MASKSBS_1                   ((uint32_t)0x02000000)
+#define ERTC_ALBSBS_MASKSBS_2                   ((uint32_t)0x04000000)
+#define ERTC_ALBSBS_MASKSBS_3                   ((uint32_t)0x08000000)
+#define ERTC_ALBSBS_SBS                         ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for ERTC_BKP0DT register  ****************/
+#define ERTC_BKP0DT                             ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP1DT register  ****************/
+#define ERTC_BKP1DT                             ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP2DT register  ****************/
+#define ERTC_BKP2DT                             ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP3DT register  ****************/
+#define ERTC_BKP3DT                             ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP4DT register  ****************/
+#define ERTC_BKP4DT                             ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP5DT register  ****************/
+#define ERTC_BKP5DT                             ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP6DT register  ****************/
+#define ERTC_BKP6DT                             ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP7DT register  ****************/
+#define ERTC_BKP7DT                             ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP8DT register  ****************/
+#define ERTC_BKP8DT                             ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP9DT register  ****************/
+#define ERTC_BKP9DT                             ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP10DT register  ***************/
+#define ERTC_BKP10DT                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP11DT register  ***************/
+#define ERTC_BKP11DT                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP12DT register  ***************/
+#define ERTC_BKP12DT                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP13DT register  ***************/
+#define ERTC_BKP13DT                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP14DT register  ***************/
+#define ERTC_BKP14DT                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP15DT register  ***************/
+#define ERTC_BKP15DT                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP16DT register  ***************/
+#define ERTC_BKP16DT                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP17DT register  ***************/
+#define ERTC_BKP17DT                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP18DT register  ***************/
+#define ERTC_BKP18DT                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for ERTC_BKP19DT register  ***************/
+#define ERTC_BKP19DT                            ((uint32_t)0xFFFFFFFF)
+
+#else
+/*******************  Bit definition for RTC_CTRLH register  ********************/
+#define  RTC_CTRLH_PACEIEN                      ((uint8_t)0x01)               /*!< Second Interrupt Enable */
+#define  RTC_CTRLH_ALAIEN                       ((uint8_t)0x02)               /*!< Alarm Interrupt Enable */
+#define  RTC_CTRLH_OVIEN                        ((uint8_t)0x04)               /*!< OverfloW Interrupt Enable */
+
+/*******************  Bit definition for RTC_CTRLL register  ********************/
+#define  RTC_CTRLL_PACEF                        ((uint8_t)0x01)               /*!< Second Flag */
+#define  RTC_CTRLL_ALAF                         ((uint8_t)0x02)               /*!< Alarm Flag */
+#define  RTC_CTRLL_OVF                          ((uint8_t)0x04)               /*!< OverfloW Flag */
+#define  RTC_CTRLL_RSYNF                        ((uint8_t)0x08)               /*!< Registers Synchronized Flag */
+#define  RTC_CTRLL_CMF                          ((uint8_t)0x10)               /*!< Configuration Flag */
+#define  RTC_CTRLL_RTF                          ((uint8_t)0x20)               /*!< RTC operation OFF */
+
+/*******************  Bit definition for RTC_DIVH register  *******************/
+#define  RTC_DIVH_DIV                           ((uint16_t)0x000F)            /*!< RTC Prescaler Reload Value High */
+
+/*******************  Bit definition for RTC_DIVL register  *******************/
+#define  RTC_DIVL_DIV                           ((uint16_t)0xFFFF)            /*!< RTC Prescaler Reload Value Low */
+
+/*******************  Bit definition for RTC_DIVCNTH register  *******************/
+#define  RTC_DIVCNTH_RTC_DIVCNT                 ((uint16_t)0x000F)            /*!< RTC Clock Divider High */
+
+/*******************  Bit definition for RTC_DIVCNTL register  *******************/
+#define  RTC_DIVCNTL_RTC_DIVCNT                 ((uint16_t)0xFFFF)            /*!< RTC Clock Divider Low */
+
+/*******************  Bit definition for RTC_CNTH register  *******************/
+#define  RTC_CNTH_CNT                           ((uint16_t)0xFFFF)            /*!< RTC Counter High */
+
+/*******************  Bit definition for RTC_CNTL register  *******************/
+#define  RTC_CNTL_CNT                           ((uint16_t)0xFFFF)            /*!< RTC Counter Low */
+
+/*******************  Bit definition for RTC_ALAH register  *******************/
+#define  RTC_ALAH_ALA                           ((uint16_t)0xFFFF)            /*!< RTC Alarm High */
+
+/*******************  Bit definition for RTC_ALAL register  *******************/
+#define  RTC_ALAL_ALA                           ((uint16_t)0xFFFF)            /*!< RTC Alarm Low */
+#endif
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for IWDG_KEY register  ********************/
+#define  IWDG_KEY_KEY                           ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PSC register  ********************/
+#define  IWDG_PSC_PSC                           ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PSC_PSC_0                         ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PSC_PSC_1                         ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PSC_PSC_2                         ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLD register  *******************/
+#define  IWDG_RLD_RLD                           ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_STS register  ********************/
+#define  IWDG_STS_PSCF                          ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_STS_RLDF                          ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CTRL register  ********************/
+#define  WWDG_CTRL_CNTR                         ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CTRL_CNTR0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  WWDG_CTRL_CNTR1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  WWDG_CTRL_CNTR2                        ((uint8_t)0x04)               /*!< Bit 2 */
+#define  WWDG_CTRL_CNTR3                        ((uint8_t)0x08)               /*!< Bit 3 */
+#define  WWDG_CTRL_CNTR4                        ((uint8_t)0x10)               /*!< Bit 4 */
+#define  WWDG_CTRL_CNTR5                        ((uint8_t)0x20)               /*!< Bit 5 */
+#define  WWDG_CTRL_CNTR6                        ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  WWDG_CTRL_EN                           ((uint8_t)0x80)               /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFG register  *******************/
+#define  WWDG_CFG_WCNTR                         ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
+#define  WWDG_CFG_WCNTR0                        ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  WWDG_CFG_WCNTR1                        ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  WWDG_CFG_WCNTR2                        ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  WWDG_CFG_WCNTR3                        ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  WWDG_CFG_WCNTR4                        ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  WWDG_CFG_WCNTR5                        ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  WWDG_CFG_WCNTR6                        ((uint16_t)0x0040)            /*!< Bit 6 */
+
+#define  WWDG_CFG_PSC                           ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFG_PSC0                          ((uint16_t)0x0080)            /*!< Bit 0 */
+#define  WWDG_CFG_PSC1                          ((uint16_t)0x0100)            /*!< Bit 1 */
+
+#define  WWDG_CFG_EWIEN                         ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_STS register  ********************/
+#define  WWDG_STS_EWIF                          ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       eXternal Memory Controller                    		  */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for XMC_BK1CTRL1 register  *******************/
+#define  XMC_BK1CTRL1_EN                        ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  XMC_BK1CTRL1_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  XMC_BK1CTRL1_DEV                       ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  XMC_BK1CTRL1_DEV_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  XMC_BK1CTRL1_DEV_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  XMC_BK1CTRL1_BUSTYPE                   ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  XMC_BK1CTRL1_BUSTYPE_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  XMC_BK1CTRL1_BUSTYPE_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  XMC_BK1CTRL1_NOREN                     ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  XMC_BK1CTRL1_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  XMC_BK1CTRL1_WAITALV                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  XMC_BK1CTRL1_BRSTSPLTEN                ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  XMC_BK1CTRL1_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  XMC_BK1CTRL1_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  XMC_BK1CTRL1_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  XMC_BK1CTRL1_TMGWREN                   ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  XMC_BK1CTRL1_WAITASYNC                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  XMC_BK1CTRL1_BURSTWRSYN                ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for XMC_BK1CTRL2 register  *******************/
+#define  XMC_BK1CTRL2_EN                        ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  XMC_BK1CTRL2_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  XMC_BK1CTRL2_DEV                       ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  XMC_BK1CTRL2_DEV_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  XMC_BK1CTRL2_DEV_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  XMC_BK1CTRL2_BUSTYPE                   ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  XMC_BK1CTRL2_BUSTYPE_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  XMC_BK1CTRL2_BUSTYPE_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  XMC_BK1CTRL2_NOREN                     ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  XMC_BK1CTRL2_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  XMC_BK1CTRL2_WAITALV                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  XMC_BK1CTRL2_BRSTSPLTEN                ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  XMC_BK1CTRL2_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  XMC_BK1CTRL2_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  XMC_BK1CTRL2_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  XMC_BK1CTRL2_TMGWREN                   ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  XMC_BK1CTRL2_WAITASYNC                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  XMC_BK1CTRL2_BURSTWRSYN                ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for XMC_BK1CTRL3 register  *******************/
+#define  XMC_BK1CTRL3_EN                        ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  XMC_BK1CTRL3_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  XMC_BK1CTRL3_DEV                       ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  XMC_BK1CTRL3_DEV_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  XMC_BK1CTRL3_DEV_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  XMC_BK1CTRL3_BUSTYPE                   ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  XMC_BK1CTRL3_BUSTYPE_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  XMC_BK1CTRL3_BUSTYPE_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  XMC_BK1CTRL3_NOREN                     ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  XMC_BK1CTRL3_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  XMC_BK1CTRL3_WAITALV                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit. */
+#define  XMC_BK1CTRL3_BRSTSPLTEN                ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  XMC_BK1CTRL3_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  XMC_BK1CTRL3_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  XMC_BK1CTRL3_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  XMC_BK1CTRL3_TMGWREN                   ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  XMC_BK1CTRL3_WAITASYNC                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  XMC_BK1CTRL3_BURSTWRSYN                ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for XMC_BK1CTRL4 register  *******************/
+#define  XMC_BK1CTRL4_EN                        ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  XMC_BK1CTRL4_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  XMC_BK1CTRL4_DEV                       ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  XMC_BK1CTRL4_DEV_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  XMC_BK1CTRL4_DEV_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  XMC_BK1CTRL4_BUSTYPE                   ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  XMC_BK1CTRL4_BUSTYPE_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  XMC_BK1CTRL4_BUSTYPE_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  XMC_BK1CTRL4_NOREN                     ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  XMC_BK1CTRL4_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  XMC_BK1CTRL4_WAITALV                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  XMC_BK1CTRL4_BRSTSPLTEN                ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  XMC_BK1CTRL4_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  XMC_BK1CTRL4_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  XMC_BK1CTRL4_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  XMC_BK1CTRL4_TMGWREN                   ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  XMC_BK1CTRL4_WAITASYNC                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  XMC_BK1CTRL4_BURSTWRSYN                ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for XMC_BK1TMG1 register  ******************/
+#define  XMC_BK1TMG1_ADROP                      ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  XMC_BK1TMG1_ADROP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  XMC_BK1TMG1_ADROP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  XMC_BK1TMG1_ADROP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  XMC_BK1TMG1_ADROP_3                    ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG1_ADRHLD                     ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  XMC_BK1TMG1_ADRHLD_0                   ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  XMC_BK1TMG1_ADRHLD_1                   ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  XMC_BK1TMG1_ADRHLD_2                   ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  XMC_BK1TMG1_ADRHLD_3                   ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG1_DTOP                       ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  XMC_BK1TMG1_DTOP_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  XMC_BK1TMG1_DTOP_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  XMC_BK1TMG1_DTOP_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  XMC_BK1TMG1_DTOP_3                     ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG1_INTVLOP                    ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  XMC_BK1TMG1_INTVLOP_0                  ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  XMC_BK1TMG1_INTVLOP_1                  ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  XMC_BK1TMG1_INTVLOP_2                  ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  XMC_BK1TMG1_INTVLOP_3                  ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG1_CLKPSC                     ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  XMC_BK1TMG1_CLKPSC_0                   ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  XMC_BK1TMG1_CLKPSC_1                   ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  XMC_BK1TMG1_CLKPSC_2                   ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  XMC_BK1TMG1_CLKPSC_3                   ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG1_DTSTBL                     ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  XMC_BK1TMG1_DTSTBL_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  XMC_BK1TMG1_DTSTBL_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  XMC_BK1TMG1_DTSTBL_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  XMC_BK1TMG1_DTSTBL_3                   ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG1_MODE                       ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  XMC_BK1TMG1_MODE_0                     ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  XMC_BK1TMG1_MODE_1                     ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for XMC_BK1TMG2 register  *******************/
+#define  XMC_BK1TMG2_ADROP                      ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  XMC_BK1TMG2_ADROP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  XMC_BK1TMG2_ADROP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  XMC_BK1TMG2_ADROP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  XMC_BK1TMG2_ADROP_3                    ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG2_ADRHLD                     ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  XMC_BK1TMG2_ADRHLD_0                   ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  XMC_BK1TMG2_ADRHLD_1                   ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  XMC_BK1TMG2_ADRHLD_2                   ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  XMC_BK1TMG2_ADRHLD_3                   ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG2_DTOP                       ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  XMC_BK1TMG2_DTOP_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  XMC_BK1TMG2_DTOP_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  XMC_BK1TMG2_DTOP_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  XMC_BK1TMG2_DTOP_3                     ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG2_INTVLOP                    ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  XMC_BK1TMG2_INTVLOP_0                  ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  XMC_BK1TMG2_INTVLOP_1                  ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  XMC_BK1TMG2_INTVLOP_2                  ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  XMC_BK1TMG2_INTVLOP_3                  ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG2_CLKPSC                     ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  XMC_BK1TMG2_CLKPSC_0                   ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  XMC_BK1TMG2_CLKPSC_1                   ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  XMC_BK1TMG2_CLKPSC_2                   ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  XMC_BK1TMG2_CLKPSC_3                   ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG2_DTSTBL                     ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  XMC_BK1TMG2_DTSTBL_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  XMC_BK1TMG2_DTSTBL_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  XMC_BK1TMG2_DTSTBL_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  XMC_BK1TMG2_DTSTBL_3                   ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG2_MODE                       ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  XMC_BK1TMG2_MODE_0                     ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  XMC_BK1TMG2_MODE_1                     ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/*******************  Bit definition for XMC_BK1TMG3 register  *******************/
+#define  XMC_BK1TMG3_ADROP                      ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  XMC_BK1TMG3_ADROP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  XMC_BK1TMG3_ADROP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  XMC_BK1TMG3_ADROP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  XMC_BK1TMG3_ADROP_3                    ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG3_ADRHLD                     ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  XMC_BK1TMG3_ADRHLD_0                   ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  XMC_BK1TMG3_ADRHLD_1                   ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  XMC_BK1TMG3_ADRHLD_2                   ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  XMC_BK1TMG3_ADRHLD_3                   ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG3_DTOP                       ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  XMC_BK1TMG3_DTOP_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  XMC_BK1TMG3_DTOP_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  XMC_BK1TMG3_DTOP_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  XMC_BK1TMG3_DTOP_3                     ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG3_INTVLOP                    ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  XMC_BK1TMG3_INTVLOP_0                  ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  XMC_BK1TMG3_INTVLOP_1                  ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  XMC_BK1TMG3_INTVLOP_2                  ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  XMC_BK1TMG3_INTVLOP_3                  ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG3_CLKPSC                     ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  XMC_BK1TMG3_CLKPSC_0                   ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  XMC_BK1TMG3_CLKPSC_1                   ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  XMC_BK1TMG3_CLKPSC_2                   ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  XMC_BK1TMG3_CLKPSC_3                   ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG3_DTSTBL                     ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  XMC_BK1TMG3_DTSTBL_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  XMC_BK1TMG3_DTSTBL_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  XMC_BK1TMG3_DTSTBL_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  XMC_BK1TMG3_DTSTBL_3                   ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG3_MODE                       ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  XMC_BK1TMG3_MODE_0                     ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  XMC_BK1TMG3_MODE_1                     ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for XMC_BK1TMG4 register  *******************/
+#define  XMC_BK1TMG4_ADROP                      ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  XMC_BK1TMG4_ADROP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  XMC_BK1TMG4_ADROP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  XMC_BK1TMG4_ADROP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  XMC_BK1TMG4_ADROP_3                    ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG4_ADRHLD                     ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  XMC_BK1TMG4_ADRHLD_0                   ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  XMC_BK1TMG4_ADRHLD_1                   ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  XMC_BK1TMG4_ADRHLD_2                   ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  XMC_BK1TMG4_ADRHLD_3                   ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG4_DTOP                       ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  XMC_BK1TMG4_DTOP_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  XMC_BK1TMG4_DTOP_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  XMC_BK1TMG4_DTOP_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  XMC_BK1TMG4_DTOP_3                     ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG4_INTVLOP                    ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  XMC_BK1TMG4_INTVLOP_0                  ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  XMC_BK1TMG4_INTVLOP_1                  ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  XMC_BK1TMG4_INTVLOP_2                  ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  XMC_BK1TMG4_INTVLOP_3                  ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG4_CLKPSC                     ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  XMC_BK1TMG4_CLKPSC_0                   ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  XMC_BK1TMG4_CLKPSC_1                   ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  XMC_BK1TMG4_CLKPSC_2                   ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  XMC_BK1TMG4_CLKPSC_3                   ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG4_DTSTBL                     ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  XMC_BK1TMG4_DTSTBL_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  XMC_BK1TMG4_DTSTBL_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  XMC_BK1TMG4_DTSTBL_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  XMC_BK1TMG4_DTSTBL_3                   ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMG4_MODE                       ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  XMC_BK1TMG4_MODE_0                     ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  XMC_BK1TMG4_MODE_1                     ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for XMC_BK1TMGWR1 register  ******************/
+#define  XMC_BK1TMGWR1_ADROP                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  XMC_BK1TMGWR1_ADROP_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR1_ADROP_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR1_ADROP_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR1_ADROP_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR1_ADRHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  XMC_BK1TMGWR1_ADRHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR1_ADRHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR1_ADRHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR1_ADRHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR1_DTOP                     ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  XMC_BK1TMGWR1_DTOP_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR1_DTOP_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR1_DTOP_2                   ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR1_DTOP_3                   ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR1_CLKPSC                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  XMC_BK1TMGWR1_CLKPSC_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR1_CLKPSC_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR1_CLKPSC_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR1_CLKPSC_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR1_DTSTBL                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  XMC_BK1TMGWR1_DTSTBL_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR1_DTSTBL_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR1_DTSTBL_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR1_DTSTBL_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR1_MODE                     ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  XMC_BK1TMGWR1_MODE_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR1_MODE_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for XMC_BK1TMGWR2 register  ******************/
+#define  XMC_BK1TMGWR2_ADROP                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  XMC_BK1TMGWR2_ADROP_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR2_ADROP_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR2_ADROP_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR2_ADROP_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR2_ADRHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  XMC_BK1TMGWR2_ADRHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR2_ADRHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR2_ADRHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR2_ADRHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR2_DTOP                     ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  XMC_BK1TMGWR2_DTOP_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR2_DTOP_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR2_DTOP_2                   ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR2_DTOP_3                   ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR2_CLKPSC                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  XMC_BK1TMGWR2_CLKPSC_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR2_CLKPSC_1                 ((uint32_t)0x00200000)        /*!< Bit 1*/
+#define  XMC_BK1TMGWR2_CLKPSC_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR2_CLKPSC_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR2_DTSTBL                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  XMC_BK1TMGWR2_DTSTBL_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR2_DTSTBL_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR2_DTSTBL_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR2_DTSTBL_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR2_MODE                     ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  XMC_BK1TMGWR2_MODE_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR2_MODE_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for XMC_BK1TMGWR3 register  ******************/
+#define  XMC_BK1TMGWR3_ADROP                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  XMC_BK1TMGWR3_ADROP_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR3_ADROP_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR3_ADROP_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR3_ADROP_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR3_ADRHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  XMC_BK1TMGWR3_ADRHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR3_ADRHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR3_ADRHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR3_ADRHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR3_DTOP                     ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  XMC_BK1TMGWR3_DTOP_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR3_DTOP_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR3_DTOP_2                   ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR3_DTOP_3                   ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR3_CLKPSC                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  XMC_BK1TMGWR3_CLKPSC_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR3_CLKPSC_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR3_CLKPSC_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR3_CLKPSC_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR3_DTSTBL                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  XMC_BK1TMGWR3_DTSTBL_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR3_DTSTBL_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR3_DTSTBL_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR3_DTSTBL_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR3_MODE                     ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  XMC_BK1TMGWR3_MODE_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR3_MODE_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for XMC_BK1TMGWR4 register  ******************/
+#define  XMC_BK1TMGWR4_ADROP                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  XMC_BK1TMGWR4_ADROP_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR4_ADROP_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR4_ADROP_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR4_ADROP_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR4_ADRHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  XMC_BK1TMGWR4_ADRHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR4_ADRHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR4_ADRHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR4_ADRHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR4_DTOP                     ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  XMC_BK1TMGWR4_DTOP_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR4_DTOP_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR4_DTOP_2                   ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR4_DTOP_3                   ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR4_CLKPSC                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  XMC_BK1TMGWR4_CLKPSC_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR4_CLKPSC_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR4_CLKPSC_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR4_CLKPSC_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR4_DTSTBL                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  XMC_BK1TMGWR4_DTSTBL_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR4_DTSTBL_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  XMC_BK1TMGWR4_DTSTBL_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  XMC_BK1TMGWR4_DTSTBL_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  XMC_BK1TMGWR4_MODE                     ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  XMC_BK1TMGWR4_MODE_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  XMC_BK1TMGWR4_MODE_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for XMC_BK2CTRL register  *******************/
+#define  XMC_BK2CTRL_WAITEN                     ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
+#define  XMC_BK2CTRL_EN                         ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
+#define  XMC_BK2CTRL_DEV                        ((uint32_t)0x00000008)        /*!< Memory type */
+
+#define  XMC_BK2CTRL_BUSTYPE                    ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define  XMC_BK2CTRL_BUSTYPE_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  XMC_BK2CTRL_BUSTYPE_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  XMC_BK2CTRL_ECCEN                      ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
+
+#define  XMC_BK2CTRL_DLYCR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define  XMC_BK2CTRL_DLYCR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  XMC_BK2CTRL_DLYCR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  XMC_BK2CTRL_DLYCR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+#define  XMC_BK2CTRL_DLYCR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
+
+#define  XMC_BK2CTRL_DLYAR                      ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
+#define  XMC_BK2CTRL_DLYAR_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  XMC_BK2CTRL_DLYAR_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  XMC_BK2CTRL_DLYAR_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */
+#define  XMC_BK2CTRL_DLYAR_3                    ((uint32_t)0x00010000)        /*!< Bit 3 */
+
+#define  XMC_BK2CTRL_ECCPGSIZE                  ((uint32_t)0x000E0000)        /*!< ECCPS[1:0] bits (ECC page size) */
+#define  XMC_BK2CTRL_ECCPGSIZE_0                ((uint32_t)0x00020000)        /*!< Bit 0 */
+#define  XMC_BK2CTRL_ECCPGSIZE_1                ((uint32_t)0x00040000)        /*!< Bit 1 */
+#define  XMC_BK2CTRL_ECCPGSIZE_2                ((uint32_t)0x00080000)        /*!< Bit 2 */
+
+/******************  Bit definition for XMC_BK3CTRL register  *******************/
+#define  XMC_BK3CTRL_WAITEN                     ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
+#define  XMC_BK3CTRL_EN                         ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
+#define  XMC_BK3CTRL_DEV                        ((uint32_t)0x00000008)        /*!< Memory type */
+
+#define  XMC_BK3CTRL_BUSTYPE                    ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define  XMC_BK3CTRL_BUSTYPE_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  XMC_BK3CTRL_BUSTYPE_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  XMC_BK3CTRL_ECCEN                      ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
+
+#define  XMC_BK3CTRL_DLYCR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define  XMC_BK3CTRL_DLYCR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  XMC_BK3CTRL_DLYCR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  XMC_BK3CTRL_DLYCR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+#define  XMC_BK3CTRL_DLYCR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
+
+#define  XMC_BK3CTRL_DLYAR                      ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
+#define  XMC_BK3CTRL_DLYAR_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  XMC_BK3CTRL_DLYAR_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  XMC_BK3CTRL_DLYAR_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */
+#define  XMC_BK3CTRL_DLYAR_3                    ((uint32_t)0x00010000)        /*!< Bit 3 */
+
+#define  XMC_BK3CTRL_ECCPGSIZE                  ((uint32_t)0x000E0000)        /*!< ECCPS[2:0] bits (ECC page size) */
+#define  XMC_BK3CTRL_ECCPGSIZE_0                ((uint32_t)0x00020000)        /*!< Bit 0 */
+#define  XMC_BK3CTRL_ECCPGSIZE_1                ((uint32_t)0x00040000)        /*!< Bit 1 */
+#define  XMC_BK3CTRL_ECCPGSIZE_2                ((uint32_t)0x00080000)        /*!< Bit 2 */
+
+/******************  Bit definition for XMC_BK4CTRL register  *******************/
+#define  XMC_BK4CTRL_WAITEN                     ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
+#define  XMC_BK4CTRL_EN                         ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
+#define  XMC_BK4CTRL_DEV                        ((uint32_t)0x00000008)        /*!< Memory type */
+
+#define  XMC_BK4CTRL_BUSTYPE                    ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define  XMC_BK4CTRL_BUSTYPE_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  XMC_BK4CTRL_BUSTYPE_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  XMC_BK4CTRL_ECCEN                      ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
+
+#define  XMC_BK4CTRL_DLYCR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define  XMC_BK4CTRL_DLYCR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  XMC_BK4CTRL_DLYCR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  XMC_BK4CTRL_DLYCR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+#define  XMC_BK4CTRL_DLYCR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
+
+#define  XMC_BK4CTRL_DLYAR                      ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
+#define  XMC_BK4CTRL_DLYAR_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  XMC_BK4CTRL_DLYAR_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  XMC_BK4CTRL_DLYAR_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */
+#define  XMC_BK4CTRL_DLYAR_3                    ((uint32_t)0x00010000)        /*!< Bit 3 */
+
+#define  XMC_BK4CTRL_ECCPGSIZE                  ((uint32_t)0x000E0000)        /*!< ECCPS[2:0] bits (ECC page size) */
+#define  XMC_BK4CTRL_ECCPGSIZE_0                ((uint32_t)0x00020000)        /*!< Bit 0 */
+#define  XMC_BK4CTRL_ECCPGSIZE_1                ((uint32_t)0x00040000)        /*!< Bit 1 */
+#define  XMC_BK4CTRL_ECCPGSIZE_2                ((uint32_t)0x00080000)        /*!< Bit 2 */
+
+/*******************  Bit definition for XMC_BK2STS register  *******************/
+#define  XMC_BK2STS_IRF                         ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
+#define  XMC_BK2STS_IHLF                        ((uint8_t)0x02)               /*!< Interrupt Level status */
+#define  XMC_BK2STS_IFF                         ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
+#define  XMC_BK2STS_IREN                        ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
+#define  XMC_BK2STS_IHLEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
+#define  XMC_BK2STS_IFEN                        ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
+#define  XMC_BK2STS_FIFOE                       ((uint8_t)0x40)               /*!< FIFO empty */
+
+/*******************  Bit definition for XMC_BK3STS register  *******************/
+#define  XMC_BK3STS_IRF                         ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
+#define  XMC_BK3STS_IHLF                        ((uint8_t)0x02)               /*!< Interrupt Level status */
+#define  XMC_BK3STS_IFF                         ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
+#define  XMC_BK3STS_IREN                        ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
+#define  XMC_BK3STS_IHLEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
+#define  XMC_BK3STS_IFEN                        ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
+#define  XMC_BK3STS_FIFOE                       ((uint8_t)0x40)               /*!< FIFO empty */
+
+/*******************  Bit definition for XMC_BK4STS register  *******************/
+#define  XMC_BK4STS_IRF                         ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
+#define  XMC_BK4STS_IHLF                        ((uint8_t)0x02)               /*!< Interrupt Level status */
+#define  XMC_BK4STS_IFF                         ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
+#define  XMC_BK4STS_IREN                        ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
+#define  XMC_BK4STS_IHLEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
+#define  XMC_BK4STS_IFEN                        ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
+#define  XMC_BK4STS_FIFOE                       ((uint8_t)0x40)               /*!< FIFO empty */
+
+/******************  Bit definition for XMC_BK2TMGMEM register  ******************/
+#define  XMC_BK2TMGMEM_STP                      ((uint32_t)0x000000FF)        /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define  XMC_BK2TMGMEM_STP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  XMC_BK2TMGMEM_STP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  XMC_BK2TMGMEM_STP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  XMC_BK2TMGMEM_STP_3                    ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  XMC_BK2TMGMEM_STP_4                    ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  XMC_BK2TMGMEM_STP_5                    ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  XMC_BK2TMGMEM_STP_6                    ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  XMC_BK2TMGMEM_STP_7                    ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  XMC_BK2TMGMEM_OP                       ((uint32_t)0x0000FF00)        /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define  XMC_BK2TMGMEM_OP_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  XMC_BK2TMGMEM_OP_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  XMC_BK2TMGMEM_OP_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  XMC_BK2TMGMEM_OP_3                     ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  XMC_BK2TMGMEM_OP_4                     ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  XMC_BK2TMGMEM_OP_5                     ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  XMC_BK2TMGMEM_OP_6                     ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  XMC_BK2TMGMEM_OP_7                     ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  XMC_BK2TMGMEM_HLD                      ((uint32_t)0x00FF0000)        /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define  XMC_BK2TMGMEM_HLD_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  XMC_BK2TMGMEM_HLD_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  XMC_BK2TMGMEM_HLD_2                    ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  XMC_BK2TMGMEM_HLD_3                    ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  XMC_BK2TMGMEM_HLD_4                    ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  XMC_BK2TMGMEM_HLD_5                    ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  XMC_BK2TMGMEM_HLD_6                    ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  XMC_BK2TMGMEM_HLD_7                    ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  XMC_BK2TMGMEM_WRSTP                    ((uint32_t)0xFF000000)        /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define  XMC_BK2TMGMEM_WRSTP_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  XMC_BK2TMGMEM_WRSTP_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  XMC_BK2TMGMEM_WRSTP_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  XMC_BK2TMGMEM_WRSTP_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  XMC_BK2TMGMEM_WRSTP_4                  ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  XMC_BK2TMGMEM_WRSTP_5                  ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  XMC_BK2TMGMEM_WRSTP_6                  ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  XMC_BK2TMGMEM_WRSTP_7                  ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for XMC_BK3TMGMEM register  ******************/
+#define  XMC_BK3TMGMEM_STP                      ((uint32_t)0x000000FF)        /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define  XMC_BK3TMGMEM_STP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  XMC_BK3TMGMEM_STP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  XMC_BK3TMGMEM_STP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  XMC_BK3TMGMEM_STP_3                    ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  XMC_BK3TMGMEM_STP_4                    ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  XMC_BK3TMGMEM_STP_5                    ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  XMC_BK3TMGMEM_STP_6                    ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  XMC_BK3TMGMEM_STP_7                    ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  XMC_BK3TMGMEM_OP                       ((uint32_t)0x0000FF00)        /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define  XMC_BK3TMGMEM_OP_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  XMC_BK3TMGMEM_OP_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  XMC_BK3TMGMEM_OP_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  XMC_BK3TMGMEM_OP_3                     ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  XMC_BK3TMGMEM_OP_4                     ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  XMC_BK3TMGMEM_OP_5                     ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  XMC_BK3TMGMEM_OP_6                     ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  XMC_BK3TMGMEM_OP_7                     ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  XMC_BK3TMGMEM_HLD                      ((uint32_t)0x00FF0000)        /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define  XMC_BK3TMGMEM_HLD_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  XMC_BK3TMGMEM_HLD_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  XMC_BK3TMGMEM_HLD_2                    ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  XMC_BK3TMGMEM_HLD_3                    ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  XMC_BK3TMGMEM_HLD_4                    ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  XMC_BK3TMGMEM_HLD_5                    ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  XMC_BK3TMGMEM_HLD_6                    ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  XMC_BK3TMGMEM_HLD_7                    ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  XMC_BK3TMGMEM_WRSTP                    ((uint32_t)0xFF000000)        /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define  XMC_BK3TMGMEM_WRSTP_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  XMC_BK3TMGMEM_WRSTP_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  XMC_BK3TMGMEM_WRSTP_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  XMC_BK3TMGMEM_WRSTP_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  XMC_BK3TMGMEM_WRSTP_4                  ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  XMC_BK3TMGMEM_WRSTP_5                  ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  XMC_BK3TMGMEM_WRSTP_6                  ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  XMC_BK3TMGMEM_WRSTP_7                  ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for XMC_BK4TMGMEM register  ******************/
+#define  XMC_BK4TMGMEM_STP                      ((uint32_t)0x000000FF)        /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define  XMC_BK4TMGMEM_STP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  XMC_BK4TMGMEM_STP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  XMC_BK4TMGMEM_STP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  XMC_BK4TMGMEM_STP_3                    ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  XMC_BK4TMGMEM_STP_4                    ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  XMC_BK4TMGMEM_STP_5                    ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  XMC_BK4TMGMEM_STP_6                    ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  XMC_BK4TMGMEM_STP_7                    ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  XMC_BK4TMGMEM_OP                       ((uint32_t)0x0000FF00)        /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define  XMC_BK4TMGMEM_OP_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  XMC_BK4TMGMEM_OP_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  XMC_BK4TMGMEM_OP_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  XMC_BK4TMGMEM_OP_3                     ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  XMC_BK4TMGMEM_OP_4                     ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  XMC_BK4TMGMEM_OP_5                     ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  XMC_BK4TMGMEM_OP_6                     ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  XMC_BK4TMGMEM_OP_7                     ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  XMC_BK4TMGMEM_HLD                      ((uint32_t)0x00FF0000)        /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define  XMC_BK4TMGMEM_HLD_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  XMC_BK4TMGMEM_HLD_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  XMC_BK4TMGMEM_HLD_2                    ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  XMC_BK4TMGMEM_HLD_3                    ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  XMC_BK4TMGMEM_HLD_4                    ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  XMC_BK4TMGMEM_HLD_5                    ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  XMC_BK4TMGMEM_HLD_6                    ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  XMC_BK4TMGMEM_HLD_7                    ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  XMC_BK4TMGMEM_WRSTP                    ((uint32_t)0xFF000000)        /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define  XMC_BK4TMGMEM_WRSTP_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  XMC_BK4TMGMEM_WRSTP_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  XMC_BK4TMGMEM_WRSTP_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  XMC_BK4TMGMEM_WRSTP_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  XMC_BK4TMGMEM_WRSTP_4                  ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  XMC_BK4TMGMEM_WRSTP_5                  ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  XMC_BK4TMGMEM_WRSTP_6                  ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  XMC_BK4TMGMEM_WRSTP_7                  ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for XMC_BK2TMGATT register  ******************/
+#define  XMC_BK2TMGATT_STP                      ((uint32_t)0x000000FF)        /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define  XMC_BK2TMGATT_STP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  XMC_BK2TMGATT_STP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  XMC_BK2TMGATT_STP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  XMC_BK2TMGATT_STP_3                    ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  XMC_BK2TMGATT_STP_4                    ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  XMC_BK2TMGATT_STP_5                    ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  XMC_BK2TMGATT_STP_6                    ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  XMC_BK2TMGATT_STP_7                    ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  XMC_BK2TMGATT_OP                       ((uint32_t)0x0000FF00)        /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define  XMC_BK2TMGATT_OP_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  XMC_BK2TMGATT_OP_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  XMC_BK2TMGATT_OP_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  XMC_BK2TMGATT_OP_3                     ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  XMC_BK2TMGATT_OP_4                     ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  XMC_BK2TMGATT_OP_5                     ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  XMC_BK2TMGATT_OP_6                     ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  XMC_BK2TMGATT_OP_7                     ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  XMC_BK2TMGATT_HLD                      ((uint32_t)0x00FF0000)        /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define  XMC_BK2TMGATT_HLD_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  XMC_BK2TMGATT_HLD_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  XMC_BK2TMGATT_HLD_2                    ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  XMC_BK2TMGATT_HLD_3                    ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  XMC_BK2TMGATT_HLD_4                    ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  XMC_BK2TMGATT_HLD_5                    ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  XMC_BK2TMGATT_HLD_6                    ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  XMC_BK2TMGATT_HLD_7                    ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  XMC_BK2TMGATT_WRSTP                    ((uint32_t)0xFF000000)        /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define  XMC_BK2TMGATT_WRSTP_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  XMC_BK2TMGATT_WRSTP_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  XMC_BK2TMGATT_WRSTP_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  XMC_BK2TMGATT_WRSTP_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  XMC_BK2TMGATT_WRSTP_4                  ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  XMC_BK2TMGATT_WRSTP_5                  ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  XMC_BK2TMGATT_WRSTP_6                  ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  XMC_BK2TMGATT_WRSTP_7                  ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for XMC_BK3TMGATT register  ******************/
+#define  XMC_BK3TMGATT_STP                      ((uint32_t)0x000000FF)        /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define  XMC_BK3TMGATT_STP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  XMC_BK3TMGATT_STP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  XMC_BK3TMGATT_STP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  XMC_BK3TMGATT_STP_3                    ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  XMC_BK3TMGATT_STP_4                    ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  XMC_BK3TMGATT_STP_5                    ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  XMC_BK3TMGATT_STP_6                    ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  XMC_BK3TMGATT_STP_7                    ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  XMC_BK3TMGATT_OP                       ((uint32_t)0x0000FF00)        /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define  XMC_BK3TMGATT_OP_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  XMC_BK3TMGATT_OP_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  XMC_BK3TMGATT_OP_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  XMC_BK3TMGATT_OP_3                     ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  XMC_BK3TMGATT_OP_4                     ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  XMC_BK3TMGATT_OP_5                     ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  XMC_BK3TMGATT_OP_6                     ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  XMC_BK3TMGATT_OP_7                     ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  XMC_BK3TMGATT_HLD                      ((uint32_t)0x00FF0000)        /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define  XMC_BK3TMGATT_HLD_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  XMC_BK3TMGATT_HLD_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  XMC_BK3TMGATT_HLD_2                    ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  XMC_BK3TMGATT_HLD_3                    ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  XMC_BK3TMGATT_HLD_4                    ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  XMC_BK3TMGATT_HLD_5                    ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  XMC_BK3TMGATT_HLD_6                    ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  XMC_BK3TMGATT_HLD_7                    ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  XMC_BK3TMGATT_WRSTP                    ((uint32_t)0xFF000000)        /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define  XMC_BK3TMGATT_WRSTP_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  XMC_BK3TMGATT_WRSTP_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  XMC_BK3TMGATT_WRSTP_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  XMC_BK3TMGATT_WRSTP_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  XMC_BK3TMGATT_WRSTP_4                  ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  XMC_BK3TMGATT_WRSTP_5                  ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  XMC_BK3TMGATT_WRSTP_6                  ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  XMC_BK3TMGATT_WRSTP_7                  ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for XMC_BK4TMGATT register  ******************/
+#define  XMC_BK4TMGATT_STP                      ((uint32_t)0x000000FF)        /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define  XMC_BK4TMGATT_STP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  XMC_BK4TMGATT_STP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  XMC_BK4TMGATT_STP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  XMC_BK4TMGATT_STP_3                    ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  XMC_BK4TMGATT_STP_4                    ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  XMC_BK4TMGATT_STP_5                    ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  XMC_BK4TMGATT_STP_6                    ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  XMC_BK4TMGATT_STP_7                    ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  XMC_BK4TMGATT_OP                       ((uint32_t)0x0000FF00)        /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define  XMC_BK4TMGATT_OP_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  XMC_BK4TMGATT_OP_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  XMC_BK4TMGATT_OP_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  XMC_BK4TMGATT_OP_3                     ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  XMC_BK4TMGATT_OP_4                     ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  XMC_BK4TMGATT_OP_5                     ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  XMC_BK4TMGATT_OP_6                     ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  XMC_BK4TMGATT_OP_7                     ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  XMC_BK4TMGATT_HLD                      ((uint32_t)0x00FF0000)        /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define  XMC_BK4TMGATT_HLD_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  XMC_BK4TMGATT_HLD_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  XMC_BK4TMGATT_HLD_2                    ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  XMC_BK4TMGATT_HLD_3                    ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  XMC_BK4TMGATT_HLD_4                    ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  XMC_BK4TMGATT_HLD_5                    ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  XMC_BK4TMGATT_HLD_6                    ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  XMC_BK4TMGATT_HLD_7                    ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  XMC_BK4TMGATT_WRSTP                    ((uint32_t)0xFF000000)        /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define  XMC_BK4TMGATT_WRSTP_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  XMC_BK4TMGATT_WRSTP_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  XMC_BK4TMGATT_WRSTP_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  XMC_BK4TMGATT_WRSTP_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  XMC_BK4TMGATT_WRSTP_4                  ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  XMC_BK4TMGATT_WRSTP_5                  ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  XMC_BK4TMGATT_WRSTP_6                  ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  XMC_BK4TMGATT_WRSTP_7                  ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for XMC_BK4TMGIO register  *******************/
+#define  XMC_BK4TMGIO_STP                       ((uint32_t)0x000000FF)        /*!< IOSET4[7:0] bits (I/O 4 setup time) */
+#define  XMC_BK4TMGIO_STP_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  XMC_BK4TMGIO_STP_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  XMC_BK4TMGIO_STP_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  XMC_BK4TMGIO_STP_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  XMC_BK4TMGIO_STP_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  XMC_BK4TMGIO_STP_5                     ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  XMC_BK4TMGIO_STP_6                     ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  XMC_BK4TMGIO_STP_7                     ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  XMC_BK4TMGIO_OP                        ((uint32_t)0x0000FF00)        /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define  XMC_BK4TMGIO_OP_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  XMC_BK4TMGIO_OP_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  XMC_BK4TMGIO_OP_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  XMC_BK4TMGIO_OP_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  XMC_BK4TMGIO_OP_4                      ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  XMC_BK4TMGIO_OP_5                      ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  XMC_BK4TMGIO_OP_6                      ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  XMC_BK4TMGIO_OP_7                      ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  XMC_BK4TMGIO_HLD                       ((uint32_t)0x00FF0000)        /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define  XMC_BK4TMGIO_HLD_0                     ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  XMC_BK4TMGIO_HLD_1                     ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  XMC_BK4TMGIO_HLD_2                     ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  XMC_BK4TMGIO_HLD_3                     ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  XMC_BK4TMGIO_HLD_4                     ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  XMC_BK4TMGIO_HLD_5                     ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  XMC_BK4TMGIO_HLD_6                     ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  XMC_BK4TMGIO_HLD_7                     ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  XMC_BK4TMGIO_WRSTP                     ((uint32_t)0xFF000000)        /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define  XMC_BK4TMGIO_WRSTP_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  XMC_BK4TMGIO_WRSTP_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  XMC_BK4TMGIO_WRSTP_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  XMC_BK4TMGIO_WRSTP_3                   ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  XMC_BK4TMGIO_WRSTP_4                   ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  XMC_BK4TMGIO_WRSTP_5                   ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  XMC_BK4TMGIO_WRSTP_6                   ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  XMC_BK4TMGIO_WRSTP_7                   ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for XMC_BK2ECC register  ******************/
+#define  XMC_BK2ECC_ECC                         ((uint32_t)0xFFFFFFFF)        /*!< ECC result */
+
+/******************  Bit definition for XMC_BK3ECC register  ******************/
+#define  XMC_BK3ECC_ECC                         ((uint32_t)0xFFFFFFFF)        /*!< ECC result */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          SD host Interface                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for SDIO_POWER register  ******************/
+#define  SDIO_POWER_PWRCTRL                     ((uint8_t)0x03)               /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                   ((uint8_t)0x01)               /*!< Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                   ((uint8_t)0x02)               /*!< Bit 1 */
+
+/******************  Bit definition for SDIO_CLKCTRL register  ******************/
+#define  SDIO_CLKCTRL_CLKPSC                    ((uint16_t)0x00FF)            /*!< Clock divide factor */
+#define  SDIO_CLKCTRL_CLKEN                     ((uint16_t)0x0100)            /*!< Clock enable bit */
+#define  SDIO_CLKCTRL_PWRSVG                    ((uint16_t)0x0200)            /*!< Power saving configuration bit */
+#define  SDIO_CLKCTRL_BYPS                      ((uint16_t)0x0400)            /*!< Clock divider bypass enable bit */
+
+#define  SDIO_CLKCTRL_BUSWIDTH                  ((uint16_t)0x1800)            /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                    ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                    ((uint16_t)0x1000)            /*!< Bit 1 */
+
+#define  SDIO_CLKCTRL_CLKEDG                    ((uint16_t)0x2000)            /*!< SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCTRL_FLWCTRLEN                 ((uint16_t)0x4000)            /*!< HW Flow Control enable */
+
+/*******************  Bit definition for SDIO_ARG register  *******************/
+#define  SDIO_ARG_ARG                           ((uint32_t)0xFFFFFFFF)            /*!< Command argument */
+
+/*******************  Bit definition for SDIO_CMD register  *******************/
+#define  SDIO_CMD_CMDIDX                        ((uint16_t)0x003F)            /*!< Command Index */
+
+#define  SDIO_CMD_RSPWT                         ((uint16_t)0x00C0)            /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                    ((uint16_t)0x0040)            /*!<  Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                    ((uint16_t)0x0080)            /*!<  Bit 1 */
+
+#define  SDIO_CMD_INTWT                         ((uint16_t)0x0100)            /*!< CPSM Waits for Interrupt Request */
+#define  SDIO_CMD_PNDWT                         ((uint16_t)0x0200)            /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CMDMEN                        ((uint16_t)0x0400)            /*!< Command path state machine (CPSM) Enable bit */
+#define  SDIO_CMD_SDIOSUSP                      ((uint16_t)0x0800)            /*!< SD I/O suspend command */
+#define  SDIO_CMD_CMPLSGNLEN                    ((uint16_t)0x1000)            /*!< Enable CMD completion */
+#define  SDIO_CMD_INTDIS                        ((uint16_t)0x2000)            /*!< Interrupt Disable */
+#define  SDIO_CMD_ATACMD                        ((uint16_t)0x4000)            /*!< CE-ATA command */
+
+/*****************  Bit definition for SDIO_RSPCMD register  *****************/
+#define  SDIO_RSPCMD_RSPCMD                     ((uint8_t)0x3F)               /*!< Response command index */
+
+/******************  Bit definition for SDIO_RESP0 register  ******************/
+#define  SDIO_RESP0_CARDSTATUS0                 ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RSP1 register  ******************/
+#define  SDIO_RSP1_CARDSTS1                     ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RSP2 register  ******************/
+#define  SDIO_RSP2_CARDSTS2                     ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RSP3 register  ******************/
+#define  SDIO_RSP3_CARDSTS3                     ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RSP4 register  ******************/
+#define  SDIO_RSP4_CARDSTS4                     ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_DTTMR register  *****************/
+#define  SDIO_DTTMR_TIMEOUT                     ((uint32_t)0xFFFFFFFF)        /*!< Data timeout period. */
+
+/******************  Bit definition for SDIO_DTLEN register  *******************/
+#define  SDIO_DTLEN_DTLEN                       ((uint32_t)0x01FFFFFF)        /*!< Data length value */
+
+/******************  Bit definition for SDIO_DTCTRL register  ******************/
+#define  SDIO_DTCTRL_TFREN                      ((uint16_t)0x0001)            /*!< Data transfer enabled bit */
+#define  SDIO_DTCTRL_TFRDIR                     ((uint16_t)0x0002)            /*!< Data transfer direction selection */
+#define  SDIO_DTCTRL_TFRMODE                    ((uint16_t)0x0004)            /*!< Data transfer mode selection */
+#define  SDIO_DTCTRL_DMAEN                      ((uint16_t)0x0008)            /*!< DMA enabled bit */
+
+#define  SDIO_DTCTRL_BLKSIZE                    ((uint16_t)0x00F0)            /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DTCTRL_DBLOCKSIZE_0               ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  SDIO_DTCTRL_DBLOCKSIZE_1               ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  SDIO_DTCTRL_DBLOCKSIZE_2               ((uint16_t)0x0040)            /*!< Bit 2 */
+#define  SDIO_DTCTRL_DBLOCKSIZE_3               ((uint16_t)0x0080)            /*!< Bit 3 */
+
+#define  SDIO_DTCTRL_RDWTSTART                  ((uint16_t)0x0100)            /*!< Read wait start */
+#define  SDIO_DTCTRL_RDWTSTOP                   ((uint16_t)0x0200)            /*!< Read wait stop */
+#define  SDIO_DTCTRL_RDWTMODE                   ((uint16_t)0x0400)            /*!< Read wait mode */
+#define  SDIO_DTCTRL_SDIOEN                     ((uint16_t)0x0800)            /*!< SD I/O enable functions */
+
+/******************  Bit definition for SDIO_DTCNTR register  *****************/
+#define  SDIO_DTCNTR_DTCNT                      ((uint32_t)0x01FFFFFF)        /*!< Data count value */
+
+/******************  Bit definition for SDIO_STS register  ********************/
+#define  SDIO_STS_CMDFAIL                       ((uint32_t)0x00000001)        /*!< Command response received (CRC check failed) */
+#define  SDIO_STS_DTFAIL                        ((uint32_t)0x00000002)        /*!< Data block sent/received (CRC check failed) */
+#define  SDIO_STS_CMDTIMEOUT                    ((uint32_t)0x00000004)        /*!< Command response timeout */
+#define  SDIO_STS_DTTIMEOUT                     ((uint32_t)0x00000008)        /*!< Data timeout */
+#define  SDIO_STS_TXERRU                        ((uint32_t)0x00000010)        /*!< Transmit FIFO underrun error */
+#define  SDIO_STS_RXERRO                        ((uint32_t)0x00000020)        /*!< Received FIFO overrun error */
+#define  SDIO_STS_CMDRSPCMPL                    ((uint32_t)0x00000040)        /*!< Command response received (CRC check passed) */
+#define  SDIO_STS_CMDCMPL                       ((uint32_t)0x00000080)        /*!< Command sent (no response required) */
+#define  SDIO_STS_DTCMPL                        ((uint32_t)0x00000100)        /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define  SDIO_STS_SBITERR                       ((uint32_t)0x00000200)        /*!< Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STS_DTBLKCMPL                     ((uint32_t)0x00000400)        /*!< Data block sent/received (CRC check passed) */
+#define  SDIO_STS_DOCMD                         ((uint32_t)0x00000800)        /*!< Command transfer in progress */
+#define  SDIO_STS_DOTX                          ((uint32_t)0x00001000)        /*!< Data transmit in progress */
+#define  SDIO_STS_DORX                          ((uint32_t)0x00002000)        /*!< Data receive in progress */
+#define  SDIO_STS_TXBUF_H                       ((uint32_t)0x00004000)        /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STS_RXBUF_H                       ((uint32_t)0x00008000)        /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STS_TXBUF_F                       ((uint32_t)0x00010000)        /*!< Transmit FIFO full */
+#define  SDIO_STS_RXBUF_F                       ((uint32_t)0x00020000)        /*!< Receive FIFO full */
+#define  SDIO_STS_TXBUF_E                       ((uint32_t)0x00040000)        /*!< Transmit FIFO empty */
+#define  SDIO_STS_RXBUF_E                       ((uint32_t)0x00080000)        /*!< Receive FIFO empty */
+#define  SDIO_STS_TXBUF                         ((uint32_t)0x00100000)        /*!< Data available in transmit FIFO */
+#define  SDIO_STS_RXBUF                         ((uint32_t)0x00200000)        /*!< Data available in receive FIFO */
+#define  SDIO_STS_SDIOIF                        ((uint32_t)0x00400000)        /*!< SDIO interrupt received */
+#define  SDIO_STS_ATACMPL                       ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received for CMD61 */
+
+/*******************  Bit definition for SDIO_INTCLR register  *******************/
+#define  SDIO_INTCLR_CMDFAIL                    ((uint32_t)0x00000001)        /*!< CCRCFAIL flag clear bit */
+#define  SDIO_INTCLR_DTFAIL                     ((uint32_t)0x00000002)        /*!< DCRCFAIL flag clear bit */
+#define  SDIO_INTCLR_CMDTIMEOUT                 ((uint32_t)0x00000004)        /*!< CTIMEOUT flag clear bit */
+#define  SDIO_INTCLR_DTTIMEOUT                  ((uint32_t)0x00000008)        /*!< DTIMEOUT flag clear bit */
+#define  SDIO_INTCLR_TXERRU                     ((uint32_t)0x00000010)        /*!< TXUNDERR flag clear bit */
+#define  SDIO_INTCLR_RXERRO                     ((uint32_t)0x00000020)        /*!< RXOVERR flag clear bit */
+#define  SDIO_INTCLR_CMDRSPCMPL                 ((uint32_t)0x00000040)        /*!< CMDREND flag clear bit */
+#define  SDIO_INTCLR_CMDCMPL                    ((uint32_t)0x00000080)        /*!< CMDSENT flag clear bit */
+#define  SDIO_INTCLR_DTCMPL                     ((uint32_t)0x00000100)        /*!< DATAEND flag clear bit */
+#define  SDIO_INTCLR_SBITERR                    ((uint32_t)0x00000200)        /*!< STBITERR flag clear bit */
+#define  SDIO_INTCLR_DTBLKCMPL                  ((uint32_t)0x00000400)        /*!< DBCKEND flag clear bit */
+#define  SDIO_INTCLR_SDIOIF                     ((uint32_t)0x00400000)        /*!< SDIOIT flag clear bit */
+#define  SDIO_INTCLR_ATACMPL                    ((uint32_t)0x00800000)        /*!< CEATAEND flag clear bit */
+
+/******************  Bit definition for SDIO_MASK register  *******************/
+#define  SDIO_MASK_CCRCFAILIE                   ((uint32_t)0x00000001)        /*!< Command CRC Fail Interrupt Enable */
+#define  SDIO_INTEN_DTFAIL                      ((uint32_t)0x00000002)        /*!< Data CRC Fail Interrupt Enable */
+#define  SDIO_INTEN_CMDTIMEOUT                  ((uint32_t)0x00000004)        /*!< Command TimeOut Interrupt Enable */
+#define  SDIO_INTEN_DTTIMEOUT                   ((uint32_t)0x00000008)        /*!< Data TimeOut Interrupt Enable */
+#define  SDIO_INTEN_TXERRU                      ((uint32_t)0x00000010)        /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define  SDIO_INTEN_RXERRO                      ((uint32_t)0x00000020)        /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define  SDIO_INTEN_CMDRSPCMPL                  ((uint32_t)0x00000040)        /*!< Command Response Received Interrupt Enable */
+#define  SDIO_INTEN_CMDCMPL                     ((uint32_t)0x00000080)        /*!< Command Sent Interrupt Enable */
+#define  SDIO_INTEN_DTCMPL                      ((uint32_t)0x00000100)        /*!< Data End Interrupt Enable */
+#define  SDIO_INTEN_SBITERR                     ((uint32_t)0x00000200)        /*!< Start Bit Error Interrupt Enable */
+#define  SDIO_INTEN_DTBLKCMPL                   ((uint32_t)0x00000400)        /*!< Data Block End Interrupt Enable */
+#define  SDIO_INTEN_DOCMD                       ((uint32_t)0x00000800)        /*!< Command Acting Interrupt Enable */
+#define  SDIO_INTEN_DOTX                        ((uint32_t)0x00001000)        /*!< Data Transmit Acting Interrupt Enable */
+#define  SDIO_INTEN_DORX                        ((uint32_t)0x00002000)        /*!< Data receive acting interrupt enabled */
+#define  SDIO_INTEN_TXBUF_H                     ((uint32_t)0x00004000)        /*!< Tx FIFO Half Empty interrupt Enable */
+#define  SDIO_INTEN_RXBUF_H                     ((uint32_t)0x00008000)        /*!< Rx FIFO Half Full interrupt Enable */
+#define  SDIO_INTEN_TXBUF_F                     ((uint32_t)0x00010000)        /*!< Tx FIFO Full interrupt Enable */
+#define  SDIO_INTEN_RXBUF_F                     ((uint32_t)0x00020000)        /*!< Rx FIFO Full interrupt Enable */
+#define  SDIO_INTEN_TXBUF_E                     ((uint32_t)0x00040000)        /*!< Tx FIFO Empty interrupt Enable */
+#define  SDIO_INTEN_RXBUF_E                     ((uint32_t)0x00080000)        /*!< Rx FIFO Empty interrupt Enable */
+#define  SDIO_INTEN_TXBUF                       ((uint32_t)0x00100000)        /*!< Data available in Tx FIFO interrupt Enable */
+#define  SDIO_INTEN_RXBUF                       ((uint32_t)0x00200000)        /*!< Data available in Rx FIFO interrupt Enable */
+#define  SDIO_INTEN_SDIOIF                      ((uint32_t)0x00400000)        /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_INTEN_ATACMPL                     ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/*****************  Bit definition for SDIO_BUFCNTR register  *****************/
+#define  SDIO_BUFCNTR_CNT                       ((uint32_t)0x00FFFFFF)        /*!< Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDIO_BUF register  *******************/
+#define  SDIO_BUF_DT                            ((uint32_t)0xFFFFFFFF)        /*!< Receive and transmit BUF data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   USB Device FS                            */
+/*                                                                            */
+/******************************************************************************/
+
+/** Endpoint-specific registers */
+/*******************  Bit definition for USB_EPT0 register  *******************/
+#define  USB_EPT0_EPTADR                        ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EPT0_STS_TX                        ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EPT0_STS_TX_0                      ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EPT0_STS_TX_1                      ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EPT0_DTOG_TX                       ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EPT0_CTFR_TX                       ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EPT0_EPT_SUBTYPE                   ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EPT0_EPT_TYPE                      ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EPT0_EPT_TYPE_0                    ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EPT0_EPT_TYPE_1                    ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EPT0_SETUP                         ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EPT0_STS_RX                        ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EPT0_STS_RX_0                      ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EPT0_STS_RX_1                      ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EPT0_DTOG_RX                       ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EPT0_CTFR_RX                       ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EPT1 register  *******************/
+#define  USB_EPT1_EPTADR                        ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EPT1_STS_TX                        ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EPT1_STS_TX_0                      ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EPT1_STS_TX_1                      ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EPT1_DTOG_TX                       ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EPT1_CTFR_TX                       ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EPT1_EPT_SUBTYPE                   ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EPT1_EPT_TYPE                      ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EPT1_EPT_TYPE_0                    ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EPT1_EPT_TYPE_1                    ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EPT1_SETUP                         ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EPT1_STS_RX                        ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EPT1_STS_RX_0                      ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EPT1_STS_RX_1                      ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EPT1_DTOG_RX                       ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EPT1_CTFR_RX                       ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EPT2 register  *******************/
+#define  USB_EPT2_EPTADR                        ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EPT2_STS_TX                        ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EPT2_STS_TX_0                      ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EPT2_STS_TX_1                      ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EPT2_DTOG_TX                       ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EPT2_CTFR_TX                       ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EPT2_EPT_SUBTYPE                   ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EPT2_EPT_TYPE                      ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EPT2_EPT_TYPE_0                    ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EPT2_EPT_TYPE_1                    ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EPT2_SETUP                         ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EPT2_STS_RX                        ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EPT2_STS_RX_0                      ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EPT2_STS_RX_1                      ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EPT2_DTOG_RX                       ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EPT2_CTFR_RX                       ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EPT3 register  *******************/
+#define  USB_EPT3_EPTADR                        ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EPT3_STS_TX                        ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EPT3_STS_TX_0                      ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EPT3_STS_TX_1                      ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EPT3_DTOG_TX                       ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EPT3_CTFR_TX                       ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EPT3_EPT_SUBTYPE                   ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EPT3_EPT_TYPE                      ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EPT3_EPT_TYPE_0                    ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EPT3_EPT_TYPE_1                    ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EPT3_SETUP                         ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EPT3_STS_RX                        ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EPT3_STS_RX_0                      ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EPT3_STS_RX_1                      ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EPT3_DTOG_RX                       ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EPT3_CTFR_RX                       ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EPT4 register  *******************/
+#define  USB_EPT4_EPTADR                        ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EPT4_STS_TX                        ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EPT4_STS_TX_0                      ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EPT4_STS_TX_1                      ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EPT4_DTOG_TX                       ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EPT4_CTFR_TX                       ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EPT4_EPT_SUBTYPE                   ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EPT4_EPT_TYPE                      ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EPT4_EPT_TYPE_0                    ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EPT4_EPT_TYPE_1                    ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EPT4_SETUP                         ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EPT4_STS_RX                        ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EPT4_STS_RX_0                      ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EPT4_STS_RX_1                      ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EPT4_DTOG_RX                       ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EPT4_CTFR_RX                       ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EPT5 register  *******************/
+#define  USB_EPT5_EPTADR                        ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EPT5_STS_TX                        ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EPT5_STS_TX_0                      ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EPT5_STS_TX_1                      ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EPT5_DTOG_TX                       ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EPT5_CTFR_TX                       ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EPT5_EPT_SUBTYPE                   ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EPT5_EPT_TYPE                      ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EPT5_EPT_TYPE_0                    ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EPT5_EPT_TYPE_1                    ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EPT5_SETUP                         ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EPT5_STS_RX                        ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EPT5_STS_RX_0                      ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EPT5_STS_RX_1                      ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EPT5_DTOG_RX                       ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EPT5_CTFR_RX                       ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EPT6 register  *******************/
+#define  USB_EPT6_EPTADR                        ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EPT6_STS_TX                        ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EPT6_STS_TX_0                      ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EPT6_STS_TX_1                      ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EPT6_DTOG_TX                       ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EPT6_CTFR_TX                       ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EPT6_EPT_SUBTYPE                   ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EPT6_EPT_TYPE                      ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EPT6_EPT_TYPE_0                    ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EPT6_EPT_TYPE_1                    ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EPT6_SETUP                         ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EPT6_STS_RX                        ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EPT6_STS_RX_0                      ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EPT6_STS_RX_1                      ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EPT6_DTOG_RX                       ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EPT6_CTFR_RX                       ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EPT7 register  *******************/
+#define  USB_EPT7_EPTADR                        ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EPT7_STS_TX                        ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EPT7_STS_TX_0                      ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EPT7_STS_TX_1                      ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EPT7_DTOG_TX                       ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EPT7_CTFR_TX                       ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EPT7_EPT_SUBTYPE                   ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EPT7_EPT_TYPE                      ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EPT7_EPT_TYPE_0                    ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EPT7_EPT_TYPE_1                    ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EPT7_SETUP                         ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EPT7_STS_RX                        ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EPT7_STS_RX_0                      ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EPT7_STS_RX_1                      ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EPT7_DTOG_RX                       ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EPT7_CTFR_RX                       ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/** Common registers */
+/*******************  Bit definition for USB_CTRL register  *******************/
+#define  USB_CTRL_FRST                          ((uint16_t)0x0001)            /*!< Force USB Reset */
+#define  USB_CTRL_PDWN                          ((uint16_t)0x0002)            /*!< Power down */
+#define  USB_CTRL_LPWR                          ((uint16_t)0x0004)            /*!< Low-power mode */
+#define  USB_CTRL_FSUSP                         ((uint16_t)0x0008)            /*!< Force suspend */
+#define  USB_CTRL_RESUME                        ((uint16_t)0x0010)            /*!< Resume request */
+#define  USB_CTRL_ESOF_IEN                      ((uint16_t)0x0100)            /*!< Expected Start Of Frame Interrupt Mask */
+#define  USB_CTRL_SOF_IEN                       ((uint16_t)0x0200)            /*!< Start Of Frame Interrupt Mask */
+#define  USB_CTRL_RST_IEN                       ((uint16_t)0x0400)            /*!< RESET Interrupt Mask */
+#define  USB_CTRL_SUSP_IEN                      ((uint16_t)0x0800)            /*!< Suspend mode Interrupt Mask */
+#define  USB_CTRL_WKUP_IEN                      ((uint16_t)0x1000)            /*!< Wakeup Interrupt Mask */
+#define  USB_CTRL_ERR_IEN                       ((uint16_t)0x2000)            /*!< Error Interrupt Mask */
+#define  USB_CTRL_PMOVR_IEN                     ((uint16_t)0x4000)            /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define  USB_CTRL_CTFR_IEN                      ((uint16_t)0x8000)            /*!< Correct Transfer Interrupt Mask */
+
+/*******************  Bit definition for USB_INTSTS register  *******************/
+#define  USB_INTSTS_EPT_ID                      ((uint16_t)0x000F)            /*!< Endpoint Identifier */
+#define  USB_INTSTS_DIR                         ((uint16_t)0x0010)            /*!< Direction of transaction */
+#define  USB_INTSTS_ESOF                        ((uint16_t)0x0100)            /*!< Expected Start Of Frame */
+#define  USB_INTSTS_SOFF                        ((uint16_t)0x0200)            /*!< Start Of Frame */
+#define  USB_INTSTS_RSTF                        ((uint16_t)0x0400)            /*!< USB RESET request */
+#define  USB_INTSTS_SUSPF                       ((uint16_t)0x0800)            /*!< Suspend mode request */
+#define  USB_INTSTS_WKUPF                       ((uint16_t)0x1000)            /*!< Wake up */
+#define  USB_INTSTS_ERRF                        ((uint16_t)0x2000)            /*!< Error */
+#define  USB_INTSTS_PMOVERF                     ((uint16_t)0x4000)            /*!< Packet Memory Area Over / Underrun */
+#define  USB_INTSTS_CTFRF                       ((uint16_t)0x8000)            /*!< Correct Transfer */
+
+/*******************  Bit definition for USB_FRNUM register  ********************/
+#define  USB_FRNUM_FRNUM                        ((uint16_t)0x07FF)            /*!< Frame Number */
+#define  USB_FRNUM_LSOF                         ((uint16_t)0x1800)            /*!< Lost SOF */
+#define  USB_FRNUM_LCK                          ((uint16_t)0x2000)            /*!< Locked */
+#define  USB_FRNUM_DMSTS                        ((uint16_t)0x4000)            /*!< Receive Data - Line Status */
+#define  USB_FRNUM_DPSTS                        ((uint16_t)0x8000)            /*!< Receive Data + Line Status */
+
+/******************  Bit definition for USB_DEVADR register  *******************/
+#define  USB_DEVADR_ADR                         ((uint8_t)0x7F)               /*!< ADD[6:0] bits (Device Address) */
+#define  USB_DEVADR_ADR_B0                      ((uint8_t)0x01)               /*!< Bit 0 */
+#define  USB_DEVADR_ADR_B1                      ((uint8_t)0x02)               /*!< Bit 1 */
+#define  USB_DEVADR_ADR_B2                      ((uint8_t)0x04)               /*!< Bit 2 */
+#define  USB_DEVADR_ADR_B3                      ((uint8_t)0x08)               /*!< Bit 3 */
+#define  USB_DEVADR_ADR_B4                      ((uint8_t)0x10)               /*!< Bit 4 */
+#define  USB_DEVADR_ADR_B5                      ((uint8_t)0x20)               /*!< Bit 5 */
+#define  USB_DEVADR_ADR_B6                      ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  USB_DEVADR_EN                          ((uint8_t)0x80)               /*!< Enable Function */
+
+/******************  Bit definition for USB_BUFTBL register  ******************/
+#define  USB_BUFTBL_ADR                         ((uint16_t)0xFFF8)            /*!< Buffer Table */
+
+/** Buffer descriptor table */
+/*****************  Bit definition for USB_ADR0_TX register  *****************/
+#define  USB_ADR0_TX_ADR0_TX                    ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADR1_TX register  *****************/
+#define  USB_ADR1_TX_ADR1_TX                    ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADR2_TX register  *****************/
+#define  USB_ADR2_TX_ADR2_TX                    ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADR3_TX register  *****************/
+#define  USB_ADR3_TX_ADR3_TX                    ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADR4_TX register  *****************/
+#define  USB_ADR4_TX_ADR4_TX                    ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADR5_TX register  *****************/
+#define  USB_ADR5_TX_ADR5_TX                    ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADR6_TX register  *****************/
+#define  USB_ADR6_TX_ADR6_TX                    ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADR7_TX register  *****************/
+#define  USB_ADR7_TX_ADR7_TX                    ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_CNT0_TX register  ****************/
+#define  USB_CNT0_TX_CNT0_TX                    ((uint16_t)0x03FF)            /*!< Transmission Byte Count 0 */
+
+/*****************  Bit definition for USB_CNT1_TX register  ****************/
+#define  USB_CNT1_TX_CNT1_TX                    ((uint16_t)0x03FF)            /*!< Transmission Byte Count 1 */
+
+/*****************  Bit definition for USB_CNT2_TX register  ****************/
+#define  USB_CNT2_TX_CNT2_TX                    ((uint16_t)0x03FF)            /*!< Transmission Byte Count 2 */
+
+/*****************  Bit definition for USB_CNT3_TX register  ****************/
+#define  USB_CNT3_TX_CNT3_TX                    ((uint16_t)0x03FF)            /*!< Transmission Byte Count 3 */
+
+/*****************  Bit definition for USB_CNT4_TX register  ****************/
+#define  USB_CNT4_TX_CNT4_TX                    ((uint16_t)0x03FF)            /*!< Transmission Byte Count 4 */
+
+/*****************  Bit definition for USB_CNT5_TX register  ****************/
+#define  USB_CNT5_TX_CNT5_TX                    ((uint16_t)0x03FF)            /*!< Transmission Byte Count 5 */
+
+/*****************  Bit definition for USB_CNT6_TX register  ****************/
+#define  USB_CNT6_TX_CNT6_TX                    ((uint16_t)0x03FF)            /*!< Transmission Byte Count 6 */
+
+/*****************  Bit definition for USB_CNT7_TX register  ****************/
+#define  USB_CNT7_TX_CNT7_TX                    ((uint16_t)0x03FF)            /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_CNT0_TX_0 register  ***************/
+#define  USB_CNT0_TX_0_CNT0_TX_0                ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 0 (low) */
+
+/****************  Bit definition for USB_CNT0_TX_1 register  ***************/
+#define  USB_CNT0_TX_1_CNT0_TX_1                ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 0 (high) */
+
+/****************  Bit definition for USB_CNT1_TX_0 register  ***************/
+#define  USB_CNT1_TX_0_CNT1_TX_0                ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 1 (low) */
+
+/****************  Bit definition for USB_CNT1_TX_1 register  ***************/
+#define  USB_CNT1_TX_1_CNT1_TX_1                ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 1 (high) */
+
+/****************  Bit definition for USB_CNT2_TX_0 register  ***************/
+#define  USB_CNT2_TX_0_CNT2_TX_0                ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 2 (low) */
+
+/****************  Bit definition for USB_CNT2_TX_1 register  ***************/
+#define  USB_CNT2_TX_1_CNT2_TX_1                ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 2 (high) */
+
+/****************  Bit definition for USB_CNT3_TX_0 register  ***************/
+#define  USB_CNT3_TX_0_CNT3_TX_0                ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 3 (low) */
+
+/****************  Bit definition for USB_CNT3_TX_1 register  ***************/
+#define  USB_CNT3_TX_1_CNT3_TX_1                ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 3 (high) */
+
+/****************  Bit definition for USB_CNT4_TX_0 register  ***************/
+#define  USB_CNT4_TX_0_CNT4_TX_0                ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 4 (low) */
+
+/****************  Bit definition for USB_CNT4_TX_1 register  ***************/
+#define  USB_CNT4_TX_1_CNT4_TX_1                ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 4 (high) */
+
+/****************  Bit definition for USB_CNT5_TX_0 register  ***************/
+#define  USB_CNT5_TX_0_CNT5_TX_0                ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 5 (low) */
+
+/****************  Bit definition for USB_CNT5_TX_1 register  ***************/
+#define  USB_CNT5_TX_1_CNT5_TX_1                ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 5 (high) */
+
+/****************  Bit definition for USB_CNT6_TX_0 register  ***************/
+#define  USB_CNT6_TX_0_CNT6_TX_0                ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 6 (low) */
+
+/****************  Bit definition for USB_CNT6_TX_1 register  ***************/
+#define  USB_CNT6_TX_1_CNT6_TX_1                ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 6 (high) */
+
+/****************  Bit definition for USB_CNT7_TX_0 register  ***************/
+#define  USB_CNT7_TX_0_CNT7_TX_0                ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 7 (low) */
+
+/****************  Bit definition for USB_CNT7_TX_1 register  ***************/
+#define  USB_CNT7_TX_1_CNT7_TX_1                ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_ADR0_RX register  *****************/
+#define  USB_ADR0_RX_ADR0_RX                    ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADR1_RX register  *****************/
+#define  USB_ADR1_RX_ADR1_RX                    ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADR2_RX register  *****************/
+#define  USB_ADR2_RX_ADR2_RX                    ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADR3_RX register  *****************/
+#define  USB_ADR3_RX_ADR3_RX                    ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADR4_RX register  *****************/
+#define  USB_ADR4_RX_ADR4_RX                    ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADR5_RX register  *****************/
+#define  USB_ADR5_RX_ADR5_RX                    ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADR6_RX register  *****************/
+#define  USB_ADR6_RX_ADR6_RX                    ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADR7_RX register  *****************/
+#define  USB_ADR7_RX_ADR7_RX                    ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_CNT0_RX register  ****************/
+#define  USB_CNT0_RX_CNT0_RX                    ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_CNT0_RX_NUM_BLK                    ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_CNT0_RX_NUM_BLK_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_CNT0_RX_NUM_BLK_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_CNT0_RX_NUM_BLK_2                  ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_CNT0_RX_NUM_BLK_3                  ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_CNT0_RX_NUM_BLK_4                  ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_CNT0_RX_BLKSIZE                    ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_CNT1_RX register  ****************/
+#define  USB_CNT1_RX_CNT1_RX                    ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_CNT1_RX_NUM_BLK                    ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_CNT1_RX_NUM_BLK_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_CNT1_RX_NUM_BLK_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_CNT1_RX_NUM_BLK_2                  ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_CNT1_RX_NUM_BLK_3                  ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_CNT1_RX_NUM_BLK_4                  ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_CNT1_RX_BLKSIZE                    ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_CNT2_RX register  ****************/
+#define  USB_CNT2_RX_CNT2_RX                    ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_CNT2_RX_NUM_BLK                    ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_CNT2_RX_NUM_BLK_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_CNT2_RX_NUM_BLK_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_CNT2_RX_NUM_BLK_2                  ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_CNT2_RX_NUM_BLK_3                  ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_CNT2_RX_NUM_BLK_4                  ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_CNT2_RX_BLKSIZE                    ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_CNT3_RX register  ****************/
+#define  USB_CNT3_RX_CNT0_RX                    ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_CNT3_RX_NUM_BLK                    ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_CNT3_RX_NUM_BLK_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_CNT3_RX_NUM_BLK_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_CNT3_RX_NUM_BLK_2                  ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_CNT3_RX_NUM_BLK_3                  ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_CNT3_RX_NUM_BLK_4                  ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_CNT3_RX_BLKSIZE                    ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_CNT4_RX register  ****************/
+#define  USB_CNT4_RX_CNT0_RX                    ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_CNT4_RX_NUM_BLK                    ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_CNT4_RX_NUM_BLK_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_CNT4_RX_NUM_BLK_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_CNT4_RX_NUM_BLK_2                  ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_CNT4_RX_NUM_BLK_3                  ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_CNT4_RX_NUM_BLK_4                  ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_CNT4_RX_BLKSIZE                    ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_CNT5_RX register  ****************/
+#define  USB_CNT5_RX_CNT0_RX                    ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_CNT5_RX_NUM_BLK                    ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_CNT5_RX_NUM_BLK_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_CNT5_RX_NUM_BLK_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_CNT5_RX_NUM_BLK_2                  ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_CNT5_RX_NUM_BLK_3                  ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_CNT5_RX_NUM_BLK_4                  ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_CNT5_RX_BLKSIZE                    ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_CNT6_RX register  ****************/
+#define  USB_CNT6_RX_CNT0_RX                    ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_CNT6_RX_NUM_BLK                    ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_CNT6_RX_NUM_BLK_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_CNT6_RX_NUM_BLK_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_CNT6_RX_NUM_BLK_2                  ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_CNT6_RX_NUM_BLK_3                  ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_CNT6_RX_NUM_BLK_4                  ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_CNT6_RX_BLKSIZE                    ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_CNT7_RX register  ****************/
+#define  USB_CNT7_RX_CNT0_RX                    ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_CNT7_RX_NUM_BLK                    ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_CNT7_RX_NUM_BLK_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_CNT7_RX_NUM_BLK_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_CNT7_RX_NUM_BLK_2                  ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_CNT7_RX_NUM_BLK_3                  ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_CNT7_RX_NUM_BLK_4                  ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_CNT7_RX_BLKSIZE                    ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_CNT0_RX_0 register  ***************/
+#define  USB_CNT0_RX_0_CNT0_RX_0                ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_CNT0_RX_0_NUM_BLK_0                ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_CNT0_RX_0_NUM_BLK_0_0              ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_CNT0_RX_0_NUM_BLK_0_1              ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_CNT0_RX_0_NUM_BLK_0_2              ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_CNT0_RX_0_NUM_BLK_0_3              ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_CNT0_RX_0_NUM_BLK_0_4              ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_CNT0_RX_0_BLKSIZE_0                ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_CNT0_RX_1 register  ***************/
+#define  USB_CNT0_RX_1_CNT0_RX_1                ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_CNT0_RX_1_NUM_BLK_1                ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_CNT0_RX_1_NUM_BLK_1_0              ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  USB_CNT0_RX_1_NUM_BLK_1_1              ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_CNT0_RX_1_NUM_BLK_1_2              ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_CNT0_RX_1_NUM_BLK_1_3              ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_CNT0_RX_1_NUM_BLK_1_4              ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_CNT0_RX_1_BLKSIZE_1                ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_CNT1_RX_0 register  ***************/
+#define  USB_CNT1_RX_0_CNT1_RX_0                ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_CNT1_RX_0_NUM_BLK_0                ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_CNT1_RX_0_NUM_BLK_0_0              ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_CNT1_RX_0_NUM_BLK_0_1              ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_CNT1_RX_0_NUM_BLK_0_2              ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_CNT1_RX_0_NUM_BLK_0_3              ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_CNT1_RX_0_NUM_BLK_0_4              ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_CNT1_RX_0_BLKSIZE_0                ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_CNT1_RX_1 register  ***************/
+#define  USB_CNT1_RX_1_CNT1_RX_1                ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_CNT1_RX_1_NUM_BLK_1                ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_CNT1_RX_1_NUM_BLK_1_0              ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_CNT1_RX_1_NUM_BLK_1_1              ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_CNT1_RX_1_NUM_BLK_1_2              ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_CNT1_RX_1_NUM_BLK_1_3              ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_CNT1_RX_1_NUM_BLK_1_4              ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_CNT1_RX_1_BLKSIZE_1                ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_CNT2_RX_0 register  ***************/
+#define  USB_CNT2_RX_0_CNT2_RX_0                ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_CNT2_RX_0_NUM_BLK_0                ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_CNT2_RX_0_NUM_BLK_0_0              ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_CNT2_RX_0_NUM_BLK_0_1              ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_CNT2_RX_0_NUM_BLK_0_2              ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_CNT2_RX_0_NUM_BLK_0_3              ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_CNT2_RX_0_NUM_BLK_0_4              ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_CNT2_RX_0_BLKSIZE_0                ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_CNT2_RX_1 register  ***************/
+#define  USB_CNT2_RX_1_CNT2_RX_1                ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_CNT2_RX_1_NUM_BLK_1                ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_CNT2_RX_1_NUM_BLK_1_0              ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_CNT2_RX_1_NUM_BLK_1_1              ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_CNT2_RX_1_NUM_BLK_1_2              ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_CNT2_RX_1_NUM_BLK_1_3              ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_CNT2_RX_1_NUM_BLK_1_4              ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_CNT2_RX_1_BLKSIZE_1                ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_CNT3_RX_0 register  ***************/
+#define  USB_CNT3_RX_0_CNT3_RX_0                ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_CNT3_RX_0_NUM_BLK_0                ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_CNT3_RX_0_NUM_BLK_0_0              ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_CNT3_RX_0_NUM_BLK_0_1              ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_CNT3_RX_0_NUM_BLK_0_2              ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_CNT3_RX_0_NUM_BLK_0_3              ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_CNT3_RX_0_NUM_BLK_0_4              ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_CNT3_RX_0_BLKSIZE_0                ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_CNT3_RX_1 register  ***************/
+#define  USB_CNT3_RX_1_CNT3_RX_1                ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_CNT3_RX_1_NUM_BLK_1                ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_CNT3_RX_1_NUM_BLK_1_0              ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_CNT3_RX_1_NUM_BLK_1_1              ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_CNT3_RX_1_NUM_BLK_1_2              ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_CNT3_RX_1_NUM_BLK_1_3              ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_CNT3_RX_1_NUM_BLK_1_4              ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_CNT3_RX_1_BLKSIZE_1                ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_CNT4_RX_0 register  ***************/
+#define  USB_CNT4_RX_0_CNT4_RX_0                ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_CNT4_RX_0_NUM_BLK_0                ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_CNT4_RX_0_NUM_BLK_0_0              ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_CNT4_RX_0_NUM_BLK_0_1              ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_CNT4_RX_0_NUM_BLK_0_2              ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_CNT4_RX_0_NUM_BLK_0_3              ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_CNT4_RX_0_NUM_BLK_0_4              ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_CNT4_RX_0_BLKSIZE_0                ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_CNT4_RX_1 register  ***************/
+#define  USB_CNT4_RX_1_CNT4_RX_1                ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_CNT4_RX_1_NUM_BLK_1                ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_CNT4_RX_1_NUM_BLK_1_0              ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_CNT4_RX_1_NUM_BLK_1_1              ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_CNT4_RX_1_NUM_BLK_1_2              ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_CNT4_RX_1_NUM_BLK_1_3              ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_CNT4_RX_1_NUM_BLK_1_4              ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_CNT4_RX_1_BLKSIZE_1                ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_CNT5_RX_0 register  ***************/
+#define  USB_CNT5_RX_0_CNT5_RX_0                ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_CNT5_RX_0_NUM_BLK_0                ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_CNT5_RX_0_NUM_BLK_0_0              ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_CNT5_RX_0_NUM_BLK_0_1              ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_CNT5_RX_0_NUM_BLK_0_2              ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_CNT5_RX_0_NUM_BLK_0_3              ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_CNT5_RX_0_NUM_BLK_0_4              ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_CNT5_RX_0_BLKSIZE_0                ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_CNT5_RX_1 register  ***************/
+#define  USB_CNT5_RX_1_CNT5_RX_1                ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_CNT5_RX_1_NUM_BLK_1                ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_CNT5_RX_1_NUM_BLK_1_0              ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_CNT5_RX_1_NUM_BLK_1_1              ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_CNT5_RX_1_NUM_BLK_1_2              ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_CNT5_RX_1_NUM_BLK_1_3              ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_CNT5_RX_1_NUM_BLK_1_4              ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_CNT5_RX_1_BLKSIZE_1                ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_CNT6_RX_0  register  ***************/
+#define  USB_CNT6_RX_0_CNT6_RX_0                ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_CNT6_RX_0_NUM_BLK_0                ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_CNT6_RX_0_NUM_BLK_0_0              ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_CNT6_RX_0_NUM_BLK_0_1              ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_CNT6_RX_0_NUM_BLK_0_2              ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_CNT6_RX_0_NUM_BLK_0_3              ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_CNT6_RX_0_NUM_BLK_0_4              ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_CNT6_RX_0_BLKSIZE_0                ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_CNT6_RX_1 register  ***************/
+#define  USB_CNT6_RX_1_CNT6_RX_1                ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_CNT6_RX_1_NUM_BLK_1                ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_CNT6_RX_1_NUM_BLK_1_0              ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_CNT6_RX_1_NUM_BLK_1_1              ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_CNT6_RX_1_NUM_BLK_1_2              ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_CNT6_RX_1_NUM_BLK_1_3              ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_CNT6_RX_1_NUM_BLK_1_4              ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_CNT6_RX_1_BLKSIZE_1                ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_CNT7_RX_0 register  ****************/
+#define  USB_CNT7_RX_0_CNT7_RX_0                ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_CNT7_RX_0_NUM_BLK_0                ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_CNT7_RX_0_NUM_BLK_0_0              ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_CNT7_RX_0_NUM_BLK_0_1              ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_CNT7_RX_0_NUM_BLK_0_2              ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_CNT7_RX_0_NUM_BLK_0_3              ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_CNT7_RX_0_NUM_BLK_0_4              ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_CNT7_RX_0_BLKSIZE_0                ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/***************  Bit definition for USB_CNT7_RX_1 register  ****************/
+#define  USB_CNT7_RX_1_CNT7_RX_1                ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_CNT7_RX_1_NUM_BLK_1                ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_CNT7_RX_1_NUM_BLK_1_0              ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_CNT7_RX_1_NUM_BLK_1_1              ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_CNT7_RX_1_NUM_BLK_1_2              ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_CNT7_RX_1_NUM_BLK_1_3              ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_CNT7_RX_1_NUM_BLK_1_4              ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_CNT7_RX_1_BLKSIZE_1                ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+
+/** CAN control and status registers */
+/*******************  Bit definition for CAN_MCTRL register  ********************/
+#define  CAN_MCTRL_INRQ                         ((uint16_t)0x0001)            /*!< Initialization Request */
+#define  CAN_MCTRL_SLP                          ((uint16_t)0x0002)            /*!< Sleep Mode Request */
+#define  CAN_MCTRL_TFP                          ((uint16_t)0x0004)            /*!< Transmit FIFO Priority */
+#define  CAN_MCTRL_RFL                          ((uint16_t)0x0008)            /*!< Receive FIFO Locked Mode */
+#define  CAN_MCTRL_NART                         ((uint16_t)0x0010)            /*!< No Automatic Retransmission */
+#define  CAN_MCTRL_AWU                          ((uint16_t)0x0020)            /*!< Automatic Wakeup Mode */
+#define  CAN_MCTRL_ABO                          ((uint16_t)0x0040)            /*!< Automatic Bus-Off Management */
+#define  CAN_MCTRL_TTC                          ((uint16_t)0x0080)            /*!< Time Triggered Communication Mode */
+#define  CAN_MCTRL_RST                          ((uint16_t)0x8000)            /*!< CAN software master reset */
+
+/*******************  Bit definition for CAN_MSTS register  ********************/
+#define  CAN_MSTS_IAK                           ((uint16_t)0x0001)            /*!< Initialization Acknowledge */
+#define  CAN_MSTS_SAK                           ((uint16_t)0x0002)            /*!< Sleep Acknowledge */
+#define  CAN_MSTS_ERIT                          ((uint16_t)0x0004)            /*!< Error Interrupt */
+#define  CAN_MSTS_WKIT                          ((uint16_t)0x0008)            /*!< Wakeup Interrupt */
+#define  CAN_MSTS_SAKIT                         ((uint16_t)0x0010)            /*!< Sleep Acknowledge Interrupt */
+#define  CAN_MSTS_TX                            ((uint16_t)0x0100)            /*!< Transmit Mode */
+#define  CAN_MSTS_RX                            ((uint16_t)0x0200)            /*!< Receive Mode */
+#define  CAN_MSTS_LSAP                          ((uint16_t)0x0400)            /*!< Last Sample Point */
+#define  CAN_MSTS_RXS                           ((uint16_t)0x0800)            /*!< CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSTS register  ********************/
+#define  CAN_TSTS_RQC0                          ((uint32_t)0x00000001)        /*!< Request Completed Mailbox0 */
+#define  CAN_TSTS_TOK0                          ((uint32_t)0x00000002)        /*!< Transmission OK of Mailbox0 */
+#define  CAN_TSTS_ALS0                          ((uint32_t)0x00000004)        /*!< Arbitration Lost for Mailbox0 */
+#define  CAN_TSTS_TER0                          ((uint32_t)0x00000008)        /*!< Transmission Error of Mailbox0 */
+#define  CAN_TSTS_ARQ0                          ((uint32_t)0x00000080)        /*!< Abort Request for Mailbox0 */
+#define  CAN_TSTS_RQC1                          ((uint32_t)0x00000100)        /*!< Request Completed Mailbox1 */
+#define  CAN_TSTS_TOK1                          ((uint32_t)0x00000200)        /*!< Transmission OK of Mailbox1 */
+#define  CAN_TSTS_ALS1                          ((uint32_t)0x00000400)        /*!< Arbitration Lost for Mailbox1 */
+#define  CAN_TSTS_TER1                          ((uint32_t)0x00000800)        /*!< Transmission Error of Mailbox1 */
+#define  CAN_TSTS_ARQ1                          ((uint32_t)0x00008000)        /*!< Abort Request for Mailbox 1 */
+#define  CAN_TSTS_RQC2                          ((uint32_t)0x00010000)        /*!< Request Completed Mailbox2 */
+#define  CAN_TSTS_TOK2                          ((uint32_t)0x00020000)        /*!< Transmission OK of Mailbox 2 */
+#define  CAN_TSTS_ALS2                          ((uint32_t)0x00040000)        /*!< Arbitration Lost for mailbox 2 */
+#define  CAN_TSTS_TER2                          ((uint32_t)0x00080000)        /*!< Transmission Error of Mailbox 2 */
+#define  CAN_TSTS_ARQ2                          ((uint32_t)0x00800000)        /*!< Abort Request for Mailbox 2 */
+#define  CAN_TSTS_NTM                           ((uint32_t)0x03000000)        /*!< Mailbox Code */
+
+#define  CAN_TSTS_TSME                          ((uint32_t)0x1C000000)        /*!< TME[2:0] bits */
+#define  CAN_TSTS_TSME0                         ((uint32_t)0x04000000)        /*!< Transmit Mailbox 0 Empty */
+#define  CAN_TSTS_TSME1                         ((uint32_t)0x08000000)        /*!< Transmit Mailbox 1 Empty */
+#define  CAN_TSTS_TSME2                         ((uint32_t)0x10000000)        /*!< Transmit Mailbox 2 Empty */
+
+#define  CAN_TSTS_LPM                           ((uint32_t)0xE0000000)        /*!< LOW[2:0] bits */
+#define  CAN_TSTS_LPM0                          ((uint32_t)0x20000000)        /*!< Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSTS_LPM1                          ((uint32_t)0x40000000)        /*!< Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSTS_LPM2                          ((uint32_t)0x80000000)        /*!< Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0 register  *******************/
+#define  CAN_RF0_RFP0                           ((uint8_t)0x03)               /*!< FIFO 0 Message Pending */
+#define  CAN_RF0_RFFU0                          ((uint8_t)0x08)               /*!< FIFO 0 Full */
+#define  CAN_RF0_RFOV0                          ((uint8_t)0x10)               /*!< FIFO 0 Overrun */
+#define  CAN_RF0_RRFM0                          ((uint8_t)0x20)               /*!< Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1 register  *******************/
+#define  CAN_RF1_RFP1                           ((uint8_t)0x03)               /*!< FIFO 1 Message Pending */
+#define  CAN_RF1_RFFU1                          ((uint8_t)0x08)               /*!< FIFO 1 Full */
+#define  CAN_RF1_RFOV1                          ((uint8_t)0x10)               /*!< FIFO 1 Overrun */
+#define  CAN_RF1_RRFM1                          ((uint8_t)0x20)               /*!< Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_INTEN register  *******************/
+#define  CAN_INTEN_TSMEIE                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_INTEN_RFPIE0                       ((uint32_t)0x00000002)        /*!< FIFO Message Pending Interrupt Enable */
+#define  CAN_INTEN_RFFUIE0                      ((uint32_t)0x00000004)        /*!< FIFO Full Interrupt Enable */
+#define  CAN_INTEN_RFOVIE0                      ((uint32_t)0x00000008)        /*!< FIFO Overrun Interrupt Enable */
+#define  CAN_INTEN_RFPIE1                       ((uint32_t)0x00000010)        /*!< FIFO Message Pending Interrupt Enable */
+#define  CAN_INTEN_RFFUIE1                      ((uint32_t)0x00000020)        /*!< FIFO Full Interrupt Enable */
+#define  CAN_INTEN_RFOVIE1                      ((uint32_t)0x00000040)        /*!< FIFO Overrun Interrupt Enable */
+#define  CAN_INTEN_ERWIE                        ((uint32_t)0x00000100)        /*!< Error Warning Interrupt Enable */
+#define  CAN_INTEN_ERPIE                        ((uint32_t)0x00000200)        /*!< Error Passive Interrupt Enable */
+#define  CAN_INTEN_BUIE                         ((uint32_t)0x00000400)        /*!< Bus-Off Interrupt Enable */
+#define  CAN_INTEN_ERCIE                        ((uint32_t)0x00000800)        /*!< Last Error Code Interrupt Enable */
+#define  CAN_INTEN_ERIE                         ((uint32_t)0x00008000)        /*!< Error Interrupt Enable */
+#define  CAN_INTEN_WKIE                         ((uint32_t)0x00010000)        /*!< Wakeup Interrupt Enable */
+#define  CAN_INTEN_SAKIE                        ((uint32_t)0x00020000)        /*!< Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESTS register  *******************/
+#define  CAN_ESTS_ERWF                          ((uint32_t)0x00000001)        /*!< Error Warning Flag */
+#define  CAN_ESTS_ERPF                          ((uint32_t)0x00000002)        /*!< Error Passive Flag */
+#define  CAN_ESTS_BFF                           ((uint32_t)0x00000004)        /*!< Bus-Off Flag */
+
+#define  CAN_ESTS_ERC                           ((uint32_t)0x00000070)        /*!< LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESTS_ERC_0                         ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  CAN_ESTS_ERC_1                         ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  CAN_ESTS_ERC_2                         ((uint32_t)0x00000040)        /*!< Bit 2 */
+
+#define  CAN_ESTS_TEC                           ((uint32_t)0x00FF0000)        /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESTS_REC                           ((uint32_t)0xFF000000)        /*!< Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTMG register  ********************/
+#define  CAN_BTMG_BRP                           ((uint32_t)0x000003FF)        /*!< Baud Rate Prescaler */
+#define  CAN_BTMG_BS1                           ((uint32_t)0x000F0000)        /*!< Time Segment 1 */
+#define  CAN_BTMG_BS2                           ((uint32_t)0x00700000)        /*!< Time Segment 2 */
+#define  CAN_BTMG_SJW                           ((uint32_t)0x03000000)        /*!< Resynchronization Jump Width */
+#define  CAN_BTMG_LBK                           ((uint32_t)0x40000000)        /*!< Loop Back Mode (Debug) */
+#define  CAN_BTMG_SIL                           ((uint32_t)0x80000000)        /*!< Silent Mode */
+
+/** Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define  CAN_TMI0_TRQ                           ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
+#define  CAN_TMI0_RTR                           ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_TMI0_IDT                           ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_TMI0_EID                           ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
+#define  CAN_TMI0_SID                           ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0 register  *******************/
+#define  CAN_TDT0_DLC                           ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_TDT0_TMEN                          ((uint32_t)0x00000100)        /*!< Transmit Global Time */
+#define  CAN_TDT0_TS                            ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0 register  *******************/
+#define  CAN_TDL0_D0                            ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_TDL0_D1                            ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_TDL0_D2                            ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_TDL0_D3                            ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0 register  *******************/
+#define  CAN_TDH0_D4                            ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_TDH0_D5                            ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_TDH0_D6                            ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_TDH0_D7                            ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_TMI1 register  *******************/
+#define  CAN_TMI1_TRQ                           ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
+#define  CAN_TMI1_RTR                           ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_TMI1_IDT                           ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_TMI1_EID                           ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
+#define  CAN_TMI1_SID                           ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1 register  ******************/
+#define  CAN_TDT1_DLC                           ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_TDT1_TMEN                          ((uint32_t)0x00000100)        /*!< Transmit Global Time */
+#define  CAN_TDT1_TS                            ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1 register  ******************/
+#define  CAN_TDL1_D0                            ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_TDL1_D1                            ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_TDL1_D2                            ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_TDL1_D3                            ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1 register  ******************/
+#define  CAN_TDH1_D4                            ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_TDH1_D5                            ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_TDH1_D6                            ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_TDH1_D7                            ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_TMI2 register  *******************/
+#define  CAN_TMI2_TRQ                           ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
+#define  CAN_TMI2_RTR                           ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_TMI2_IDT                           ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_TMI2_EID                           ((uint32_t)0x001FFFF8)        /*!< Extended identifier */
+#define  CAN_TMI2_SID                           ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2 register  ******************/
+#define  CAN_TDT2_DLC                           ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_TDT2_TMEN                          ((uint32_t)0x00000100)        /*!< Transmit Global Time */
+#define  CAN_TDT2_TS                            ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2 register  ******************/
+#define  CAN_TDL2_D0                            ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_TDL2_D1                            ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_TDL2_D2                            ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_TDL2_D3                            ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2 register  ******************/
+#define  CAN_TDH2_D4                            ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_TDH2_D5                            ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_TDH2_D6                            ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_TDH2_D7                            ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_RFI0 register  *******************/
+#define  CAN_RFI0_RTR                           ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_RFI0_IDT                           ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_RFI0_EID                           ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
+#define  CAN_RFI0_SID                           ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0 register  ******************/
+#define  CAN_RDT0_DLC                           ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_RDT0_FID                           ((uint32_t)0x0000FF00)        /*!< Filter Match Index */
+#define  CAN_RDT0_TS                            ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0 register  ******************/
+#define  CAN_RDL0_D0                            ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_RDL0_D1                            ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_RDL0_D2                            ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_RDL0_D3                            ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0 register  ******************/
+#define  CAN_RDH0_D4                            ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_RDH0_D5                            ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_RDH0_D6                            ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_RDH0_D7                            ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_RFI1 register  *******************/
+#define  CAN_RFI1_RTR                           ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_RFI1_IDT                           ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_RFI1_EID                           ((uint32_t)0x001FFFF8)        /*!< Extended identifier */
+#define  CAN_RFI1_SID                           ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1 register  ******************/
+#define  CAN_RDT1_DLC                           ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_RDT1_FID                           ((uint32_t)0x0000FF00)        /*!< Filter Match Index */
+#define  CAN_RDT1_TS                            ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1 register  ******************/
+#define  CAN_RDL1_D0                            ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_RDL1_D1                            ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_RDL1_D2                            ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_RDL1_D3                            ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1 register  ******************/
+#define  CAN_RDH1_D4                            ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_RDH1_D5                            ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_RDH1_D6                            ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_RDH1_D7                            ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/** CAN filter registers */
+/*******************  Bit definition for CAN_FM register  ********************/
+#define  CAN_FM_FINT                            ((uint8_t)0x01)               /*!< Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1 register  *******************/
+#define  CAN_FM1_FMS                            ((uint16_t)0x3FFF)            /*!< Filter Mode */
+#define  CAN_FM1_FMS0                           ((uint16_t)0x0001)            /*!< Filter Init Mode bit 0 */
+#define  CAN_FM1_FMS1                           ((uint16_t)0x0002)            /*!< Filter Init Mode bit 1 */
+#define  CAN_FM1_FMS2                           ((uint16_t)0x0004)            /*!< Filter Init Mode bit 2 */
+#define  CAN_FM1_FMS3                           ((uint16_t)0x0008)            /*!< Filter Init Mode bit 3 */
+#define  CAN_FM1_FMS4                           ((uint16_t)0x0010)            /*!< Filter Init Mode bit 4 */
+#define  CAN_FM1_FMS5                           ((uint16_t)0x0020)            /*!< Filter Init Mode bit 5 */
+#define  CAN_FM1_FMS6                           ((uint16_t)0x0040)            /*!< Filter Init Mode bit 6 */
+#define  CAN_FM1_FMS7                           ((uint16_t)0x0080)            /*!< Filter Init Mode bit 7 */
+#define  CAN_FM1_FMS8                           ((uint16_t)0x0100)            /*!< Filter Init Mode bit 8 */
+#define  CAN_FM1_FMS9                           ((uint16_t)0x0200)            /*!< Filter Init Mode bit 9 */
+#define  CAN_FM1_FMS10                          ((uint16_t)0x0400)            /*!< Filter Init Mode bit 10 */
+#define  CAN_FM1_FMS11                          ((uint16_t)0x0800)            /*!< Filter Init Mode bit 11 */
+#define  CAN_FM1_FMS12                          ((uint16_t)0x1000)            /*!< Filter Init Mode bit 12 */
+#define  CAN_FM1_FMS13                          ((uint16_t)0x2000)            /*!< Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1 register  *******************/
+#define  CAN_FS1_FBS                            ((uint16_t)0x3FFF)            /*!< Filter Scale Configuration */
+#define  CAN_FS1_FBS0                           ((uint16_t)0x0001)            /*!< Filter Scale Configuration bit 0 */
+#define  CAN_FS1_FBS1                           ((uint16_t)0x0002)            /*!< Filter Scale Configuration bit 1 */
+#define  CAN_FS1_FBS2                           ((uint16_t)0x0004)            /*!< Filter Scale Configuration bit 2 */
+#define  CAN_FS1_FBS3                           ((uint16_t)0x0008)            /*!< Filter Scale Configuration bit 3 */
+#define  CAN_FS1_FBS4                           ((uint16_t)0x0010)            /*!< Filter Scale Configuration bit 4 */
+#define  CAN_FS1_FBS5                           ((uint16_t)0x0020)            /*!< Filter Scale Configuration bit 5 */
+#define  CAN_FS1_FBS6                           ((uint16_t)0x0040)            /*!< Filter Scale Configuration bit 6 */
+#define  CAN_FS1_FBS7                           ((uint16_t)0x0080)            /*!< Filter Scale Configuration bit 7 */
+#define  CAN_FS1_FBS8                           ((uint16_t)0x0100)            /*!< Filter Scale Configuration bit 8 */
+#define  CAN_FS1_FBS9                           ((uint16_t)0x0200)            /*!< Filter Scale Configuration bit 9 */
+#define  CAN_FS1_FBS10                          ((uint16_t)0x0400)            /*!< Filter Scale Configuration bit 10 */
+#define  CAN_FS1_FBS11                          ((uint16_t)0x0800)            /*!< Filter Scale Configuration bit 11 */
+#define  CAN_FS1_FBS12                          ((uint16_t)0x1000)            /*!< Filter Scale Configuration bit 12 */
+#define  CAN_FS1_FBS13                          ((uint16_t)0x2000)            /*!< Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1 register  *******************/
+#define  CAN_FFA1_FAF                           ((uint16_t)0x3FFF)            /*!< Filter FIFO Assignment */
+#define  CAN_FFA1_FAF0                          ((uint16_t)0x0001)            /*!< Filter FIFO Assignment for Filter 0 */
+#define  CAN_FFA1_FAF1                          ((uint16_t)0x0002)            /*!< Filter FIFO Assignment for Filter 1 */
+#define  CAN_FFA1_FAF2                          ((uint16_t)0x0004)            /*!< Filter FIFO Assignment for Filter 2 */
+#define  CAN_FFA1_FAF3                          ((uint16_t)0x0008)            /*!< Filter FIFO Assignment for Filter 3 */
+#define  CAN_FFA1_FAF4                          ((uint16_t)0x0010)            /*!< Filter FIFO Assignment for Filter 4 */
+#define  CAN_FFA1_FAF5                          ((uint16_t)0x0020)            /*!< Filter FIFO Assignment for Filter 5 */
+#define  CAN_FFA1_FAF6                          ((uint16_t)0x0040)            /*!< Filter FIFO Assignment for Filter 6 */
+#define  CAN_FFA1_FAF7                          ((uint16_t)0x0080)            /*!< Filter FIFO Assignment for Filter 7 */
+#define  CAN_FFA1_FAF8                          ((uint16_t)0x0100)            /*!< Filter FIFO Assignment for Filter 8 */
+#define  CAN_FFA1_FAF9                          ((uint16_t)0x0200)            /*!< Filter FIFO Assignment for Filter 9 */
+#define  CAN_FFA1_FAF10                         ((uint16_t)0x0400)            /*!< Filter FIFO Assignment for Filter 10 */
+#define  CAN_FFA1_FAF11                         ((uint16_t)0x0800)            /*!< Filter FIFO Assignment for Filter 11 */
+#define  CAN_FFA1_FAF12                         ((uint16_t)0x1000)            /*!< Filter FIFO Assignment for Filter 12 */
+#define  CAN_FFA1_FAF13                         ((uint16_t)0x2000)            /*!< Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1 register  *******************/
+#define  CAN_FA1_FEN                            ((uint16_t)0x3FFF)            /*!< Filter Active */
+#define  CAN_FA1_FEN0                           ((uint16_t)0x0001)            /*!< Filter 0 Active */
+#define  CAN_FA1_FEN1                           ((uint16_t)0x0002)            /*!< Filter 1 Active */
+#define  CAN_FA1_FEN2                           ((uint16_t)0x0004)            /*!< Filter 2 Active */
+#define  CAN_FA1_FEN3                           ((uint16_t)0x0008)            /*!< Filter 3 Active */
+#define  CAN_FA1_FEN4                           ((uint16_t)0x0010)            /*!< Filter 4 Active */
+#define  CAN_FA1_FEN5                           ((uint16_t)0x0020)            /*!< Filter 5 Active */
+#define  CAN_FA1_FEN6                           ((uint16_t)0x0040)            /*!< Filter 6 Active */
+#define  CAN_FA1_FEN7                           ((uint16_t)0x0080)            /*!< Filter 7 Active */
+#define  CAN_FA1_FEN8                           ((uint16_t)0x0100)            /*!< Filter 8 Active */
+#define  CAN_FA1_FEN9                           ((uint16_t)0x0200)            /*!< Filter 9 Active */
+#define  CAN_FA1_FEN10                          ((uint16_t)0x0400)            /*!< Filter 10 Active */
+#define  CAN_FA1_FEN11                          ((uint16_t)0x0800)            /*!< Filter 11 Active */
+#define  CAN_FA1_FEN12                          ((uint16_t)0x1000)            /*!< Filter 12 Active */
+#define  CAN_FA1_FEN13                          ((uint16_t)0x2000)            /*!< Filter 13 Active */
+
+/*******************  Bit definition for CAN_FB0R1 register  *******************/
+#define  CAN_FB0R1_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB0R1_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB0R1_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB0R1_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB0R1_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB0R1_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB0R1_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB0R1_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB0R1_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB0R1_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB0R1_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB0R1_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB0R1_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB0R1_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB0R1_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB0R1_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB0R1_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB0R1_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB0R1_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB0R1_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB0R1_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB0R1_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB0R1_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB0R1_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB0R1_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB0R1_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB0R1_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB0R1_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB0R1_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB0R1_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB0R1_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB0R1_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB1R1 register  *******************/
+#define  CAN_FB1R1_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB1R1_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB1R1_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB1R1_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB1R1_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB1R1_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB1R1_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB1R1_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB1R1_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB1R1_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB1R1_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB1R1_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB1R1_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB1R1_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB1R1_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB1R1_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB1R1_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB1R1_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB1R1_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB1R1_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB1R1_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB1R1_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB1R1_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB1R1_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB1R1_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB1R1_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB1R1_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB1R1_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB1R1_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB1R1_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB1R1_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB1R1_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB2R1 register  *******************/
+#define  CAN_FB2R1_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB2R1_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB2R1_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB2R1_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB2R1_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB2R1_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB2R1_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB2R1_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB2R1_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB2R1_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB2R1_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB2R1_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB2R1_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB2R1_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB2R1_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB2R1_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB2R1_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB2R1_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB2R1_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB2R1_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB2R1_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB2R1_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB2R1_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB2R1_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB2R1_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB2R1_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB2R1_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB2R1_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB2R1_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB2R1_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB2R1_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB2R1_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB3R1 register  *******************/
+#define  CAN_FB3R1_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB3R1_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB3R1_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB3R1_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB3R1_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB3R1_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB3R1_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB3R1_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB3R1_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB3R1_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB3R1_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB3R1_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB3R1_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB3R1_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB3R1_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB3R1_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB3R1_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB3R1_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB3R1_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB3R1_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB3R1_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB3R1_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB3R1_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB3R1_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB3R1_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB3R1_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB3R1_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB3R1_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB3R1_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB3R1_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB3R1_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB3R1_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB4R1 register  *******************/
+#define  CAN_FB4R1_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB4R1_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB4R1_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB4R1_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB4R1_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB4R1_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB4R1_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB4R1_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB4R1_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB4R1_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB4R1_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB4R1_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB4R1_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB4R1_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB4R1_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB4R1_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB4R1_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB4R1_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB4R1_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB4R1_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB4R1_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB4R1_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB4R1_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB4R1_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB4R1_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB4R1_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB4R1_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB4R1_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB4R1_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB4R1_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB4R1_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB4R1_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB5R1 register  *******************/
+#define  CAN_FB5R1_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB5R1_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB5R1_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB5R1_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB5R1_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB5R1_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB5R1_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB5R1_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB5R1_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB5R1_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB5R1_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB5R1_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB5R1_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB5R1_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB5R1_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB5R1_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB5R1_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB5R1_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB5R1_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB5R1_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB5R1_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB5R1_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB5R1_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB5R1_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB5R1_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB5R1_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB5R1_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB5R1_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB5R1_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB5R1_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB5R1_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB5R1_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB6R1 register  *******************/
+#define  CAN_FB6R1_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB6R1_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB6R1_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB6R1_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB6R1_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB6R1_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB6R1_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB6R1_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB6R1_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB6R1_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB6R1_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB6R1_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB6R1_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB6R1_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB6R1_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB6R1_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB6R1_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB6R1_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB6R1_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB6R1_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB6R1_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB6R1_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB6R1_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB6R1_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB6R1_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB6R1_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB6R1_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB6R1_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB6R1_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB6R1_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB6R1_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB6R1_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB7R1 register  *******************/
+#define  CAN_FB7R1_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB7R1_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB7R1_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB7R1_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB7R1_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB7R1_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB7R1_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB7R1_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB7R1_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB7R1_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB7R1_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB7R1_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB7R1_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB7R1_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB7R1_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB7R1_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB7R1_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB7R1_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB7R1_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB7R1_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB7R1_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB7R1_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB7R1_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB7R1_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB7R1_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB7R1_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB7R1_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB7R1_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB7R1_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB7R1_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB7R1_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB7R1_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB8R1 register  *******************/
+#define  CAN_FB8R1_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB8R1_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB8R1_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB8R1_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB8R1_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB8R1_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB8R1_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB8R1_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB8R1_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB8R1_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB8R1_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB8R1_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB8R1_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB8R1_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB8R1_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB8R1_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB8R1_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB8R1_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB8R1_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB8R1_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB8R1_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB8R1_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB8R1_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB8R1_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB8R1_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB8R1_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB8R1_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB8R1_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB8R1_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB8R1_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB8R1_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB8R1_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB9R1 register  *******************/
+#define  CAN_FB9R1_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB9R1_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB9R1_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB9R1_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB9R1_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB9R1_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB9R1_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB9R1_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB9R1_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB9R1_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB9R1_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB9R1_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB9R1_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB9R1_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB9R1_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB9R1_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB9R1_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB9R1_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB9R1_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB9R1_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB9R1_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB9R1_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB9R1_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB9R1_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB9R1_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB9R1_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB9R1_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB9R1_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB9R1_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB9R1_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB9R1_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB9R1_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB10R1 register  ******************/
+#define  CAN_FB10R1_FD0                         ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB10R1_FD1                         ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB10R1_FD2                         ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB10R1_FD3                         ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB10R1_FD4                         ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB10R1_FD5                         ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB10R1_FD6                         ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB10R1_FD7                         ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB10R1_FD8                         ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB10R1_FD9                         ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB10R1_FD10                        ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB10R1_FD11                        ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB10R1_FD12                        ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB10R1_FD13                        ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB10R1_FD14                        ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB10R1_FD15                        ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB10R1_FD16                        ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB10R1_FD17                        ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB10R1_FD18                        ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB10R1_FD19                        ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB10R1_FD20                        ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB10R1_FD21                        ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB10R1_FD22                        ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB10R1_FD23                        ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB10R1_FD24                        ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB10R1_FD25                        ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB10R1_FD26                        ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB10R1_FD27                        ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB10R1_FD28                        ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB10R1_FD29                        ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB10R1_FD30                        ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB10R1_FD31                        ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB11R1 register  ******************/
+#define  CAN_FB11R1_FD0                         ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB11R1_FD1                         ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB11R1_FD2                         ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB11R1_FD3                         ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB11R1_FD4                         ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB11R1_FD5                         ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB11R1_FD6                         ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB11R1_FD7                         ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB11R1_FD8                         ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB11R1_FD9                         ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB11R1_FD10                        ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB11R1_FD11                        ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB11R1_FD12                        ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB11R1_FD13                        ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB11R1_FD14                        ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB11R1_FD15                        ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB11R1_FD16                        ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB11R1_FD17                        ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB11R1_FD18                        ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB11R1_FD19                        ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB11R1_FD20                        ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB11R1_FD21                        ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB11R1_FD22                        ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB11R1_FD23                        ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB11R1_FD24                        ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB11R1_FD25                        ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB11R1_FD26                        ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB11R1_FD27                        ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB11R1_FD28                        ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB11R1_FD29                        ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB11R1_FD30                        ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB11R1_FD31                        ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB12R1 register  ******************/
+#define  CAN_FB12R1_FD0                         ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB12R1_FD1                         ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB12R1_FD2                         ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB12R1_FD3                         ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB12R1_FD4                         ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB12R1_FD5                         ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB12R1_FD6                         ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB12R1_FD7                         ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB12R1_FD8                         ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB12R1_FD9                         ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB12R1_FD10                        ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB12R1_FD11                        ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB12R1_FD12                        ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB12R1_FD13                        ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB12R1_FD14                        ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB12R1_FD15                        ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB12R1_FD16                        ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB12R1_FD17                        ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB12R1_FD18                        ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB12R1_FD19                        ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB12R1_FD20                        ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB12R1_FD21                        ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB12R1_FD22                        ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB12R1_FD23                        ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB12R1_FD24                        ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB12R1_FD25                        ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB12R1_FD26                        ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB12R1_FD27                        ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB12R1_FD28                        ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB12R1_FD29                        ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB12R1_FD30                        ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB12R1_FD31                        ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB13R1 register  ******************/
+#define  CAN_FB13R1_FD0                         ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB13R1_FD1                         ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB13R1_FD2                         ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB13R1_FD3                         ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB13R1_FD4                         ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB13R1_FD5                         ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB13R1_FD6                         ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB13R1_FD7                         ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB13R1_FD8                         ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB13R1_FD9                         ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB13R1_FD10                        ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB13R1_FD11                        ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB13R1_FD12                        ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB13R1_FD13                        ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB13R1_FD14                        ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB13R1_FD15                        ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB13R1_FD16                        ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB13R1_FD17                        ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB13R1_FD18                        ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB13R1_FD19                        ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB13R1_FD20                        ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB13R1_FD21                        ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB13R1_FD22                        ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB13R1_FD23                        ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB13R1_FD24                        ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB13R1_FD25                        ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB13R1_FD26                        ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB13R1_FD27                        ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB13R1_FD28                        ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB13R1_FD29                        ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB13R1_FD30                        ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB13R1_FD31                        ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB0R2 register  *******************/
+#define  CAN_FB0R2_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB0R2_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB0R2_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB0R2_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB0R2_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB0R2_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB0R2_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB0R2_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB0R2_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB0R2_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB0R2_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB0R2_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB0R2_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB0R2_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB0R2_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB0R2_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB0R2_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB0R2_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB0R2_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB0R2_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB0R2_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB0R2_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB0R2_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB0R2_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB0R2_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB0R2_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB0R2_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB0R2_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB0R2_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB0R2_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB0R2_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB0R2_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB1R2 register  *******************/
+#define  CAN_FB1R2_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB1R2_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB1R2_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB1R2_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB1R2_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB1R2_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB1R2_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB1R2_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB1R2_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB1R2_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB1R2_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB1R2_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB1R2_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB1R2_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB1R2_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB1R2_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB1R2_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB1R2_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB1R2_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB1R2_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB1R2_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB1R2_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB1R2_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB1R2_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB1R2_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB1R2_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB1R2_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB1R2_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB1R2_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB1R2_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB1R2_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB1R2_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB2R2 register  *******************/
+#define  CAN_FB2R2_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB2R2_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB2R2_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB2R2_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB2R2_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB2R2_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB2R2_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB2R2_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB2R2_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB2R2_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB2R2_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB2R2_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB2R2_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB2R2_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB2R2_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB2R2_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB2R2_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB2R2_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB2R2_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB2R2_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB2R2_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB2R2_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB2R2_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB2R2_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB2R2_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB2R2_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB2R2_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB2R2_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB2R2_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB2R2_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB2R2_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB2R2_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB3R2 register  *******************/
+#define  CAN_FB3R2_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB3R2_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB3R2_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB3R2_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB3R2_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB3R2_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB3R2_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB3R2_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB3R2_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB3R2_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB3R2_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB3R2_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB3R2_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB3R2_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB3R2_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB3R2_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB3R2_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB3R2_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB3R2_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB3R2_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB3R2_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB3R2_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB3R2_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB3R2_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB3R2_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB3R2_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB3R2_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB3R2_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB3R2_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB3R2_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB3R2_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB3R2_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB4R2 register  *******************/
+#define  CAN_FB4R2_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB4R2_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB4R2_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB4R2_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB4R2_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB4R2_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB4R2_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB4R2_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB4R2_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB4R2_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB4R2_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB4R2_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB4R2_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB4R2_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB4R2_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB4R2_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB4R2_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB4R2_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB4R2_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB4R2_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB4R2_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB4R2_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB4R2_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB4R2_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB4R2_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB4R2_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB4R2_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB4R2_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB4R2_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB4R2_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB4R2_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB4R2_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB5R2 register  *******************/
+#define  CAN_FB5R2_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB5R2_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB5R2_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB5R2_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB5R2_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB5R2_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB5R2_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB5R2_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB5R2_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB5R2_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB5R2_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB5R2_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB5R2_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB5R2_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB5R2_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB5R2_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB5R2_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB5R2_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB5R2_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB5R2_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB5R2_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB5R2_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB5R2_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB5R2_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB5R2_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB5R2_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB5R2_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB5R2_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB5R2_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB5R2_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB5R2_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB5R2_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB6R2 register  *******************/
+#define  CAN_FB6R2_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB6R2_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB6R2_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB6R2_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB6R2_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB6R2_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB6R2_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB6R2_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB6R2_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB6R2_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB6R2_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB6R2_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB6R2_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB6R2_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB6R2_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB6R2_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB6R2_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB6R2_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB6R2_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB6R2_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB6R2_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB6R2_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB6R2_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB6R2_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB6R2_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB6R2_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB6R2_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB6R2_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB6R2_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB6R2_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB6R2_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB6R2_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB7R2 register  *******************/
+#define  CAN_FB7R2_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB7R2_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB7R2_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB7R2_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB7R2_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB7R2_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB7R2_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB7R2_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB7R2_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB7R2_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB7R2_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB7R2_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB7R2_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB7R2_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB7R2_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB7R2_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB7R2_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB7R2_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB7R2_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB7R2_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB7R2_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB7R2_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB7R2_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB7R2_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB7R2_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB7R2_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB7R2_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB7R2_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB7R2_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB7R2_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB7R2_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB7R2_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB8R2 register  *******************/
+#define  CAN_FB8R2_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB8R2_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB8R2_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB8R2_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB8R2_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB8R2_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB8R2_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB8R2_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB8R2_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB8R2_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB8R2_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB8R2_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB8R2_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB8R2_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB8R2_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB8R2_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB8R2_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB8R2_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB8R2_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB8R2_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB8R2_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB8R2_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB8R2_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB8R2_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB8R2_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB8R2_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB8R2_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB8R2_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB8R2_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB8R2_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB8R2_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB8R2_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB9R2 register  *******************/
+#define  CAN_FB9R2_FD0                          ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB9R2_FD1                          ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB9R2_FD2                          ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB9R2_FD3                          ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB9R2_FD4                          ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB9R2_FD5                          ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB9R2_FD6                          ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB9R2_FD7                          ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB9R2_FD8                          ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB9R2_FD9                          ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB9R2_FD10                         ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB9R2_FD11                         ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB9R2_FD12                         ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB9R2_FD13                         ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB9R2_FD14                         ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB9R2_FD15                         ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB9R2_FD16                         ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB9R2_FD17                         ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB9R2_FD18                         ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB9R2_FD19                         ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB9R2_FD20                         ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB9R2_FD21                         ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB9R2_FD22                         ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB9R2_FD23                         ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB9R2_FD24                         ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB9R2_FD25                         ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB9R2_FD26                         ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB9R2_FD27                         ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB9R2_FD28                         ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB9R2_FD29                         ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB9R2_FD30                         ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB9R2_FD31                         ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB10R2 register  ******************/
+#define  CAN_FB10R2_FD0                         ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB10R2_FD1                         ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB10R2_FD2                         ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB10R2_FD3                         ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB10R2_FD4                         ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB10R2_FD5                         ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB10R2_FD6                         ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB10R2_FD7                         ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB10R2_FD8                         ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB10R2_FD9                         ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB10R2_FD10                        ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB10R2_FD11                        ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB10R2_FD12                        ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB10R2_FD13                        ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB10R2_FD14                        ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB10R2_FD15                        ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB10R2_FD16                        ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB10R2_FD17                        ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB10R2_FD18                        ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB10R2_FD19                        ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB10R2_FD20                        ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB10R2_FD21                        ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB10R2_FD22                        ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB10R2_FD23                        ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB10R2_FD24                        ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB10R2_FD25                        ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB10R2_FD26                        ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB10R2_FD27                        ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB10R2_FD28                        ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB10R2_FD29                        ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB10R2_FD30                        ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB10R2_FD31                        ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB11R2 register  ******************/
+#define  CAN_FB11R2_FD0                         ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB11R2_FD1                         ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB11R2_FD2                         ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB11R2_FD3                         ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB11R2_FD4                         ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB11R2_FD5                         ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB11R2_FD6                         ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB11R2_FD7                         ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB11R2_FD8                         ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB11R2_FD9                         ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB11R2_FD10                        ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB11R2_FD11                        ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB11R2_FD12                        ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB11R2_FD13                        ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB11R2_FD14                        ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB11R2_FD15                        ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB11R2_FD16                        ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB11R2_FD17                        ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB11R2_FD18                        ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB11R2_FD19                        ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB11R2_FD20                        ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB11R2_FD21                        ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB11R2_FD22                        ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB11R2_FD23                        ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB11R2_FD24                        ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB11R2_FD25                        ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB11R2_FD26                        ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB11R2_FD27                        ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB11R2_FD28                        ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB11R2_FD29                        ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB11R2_FD30                        ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB11R2_FD31                        ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB12R2 register  ******************/
+#define  CAN_FB12R2_FD0                         ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB12R2_FD1                         ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB12R2_FD2                         ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB12R2_FD3                         ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB12R2_FD4                         ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB12R2_FD5                         ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB12R2_FD6                         ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB12R2_FD7                         ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB12R2_FD8                         ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB12R2_FD9                         ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB12R2_FD10                        ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB12R2_FD11                        ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB12R2_FD12                        ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB12R2_FD13                        ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB12R2_FD14                        ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB12R2_FD15                        ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB12R2_FD16                        ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB12R2_FD17                        ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB12R2_FD18                        ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB12R2_FD19                        ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB12R2_FD20                        ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB12R2_FD21                        ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB12R2_FD22                        ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB12R2_FD23                        ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB12R2_FD24                        ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB12R2_FD25                        ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB12R2_FD26                        ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB12R2_FD27                        ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB12R2_FD28                        ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB12R2_FD29                        ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB12R2_FD30                        ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB12R2_FD31                        ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_FB13R2 register  ******************/
+#define  CAN_FB13R2_FD0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_FB13R2_FD1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_FB13R2_FD2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_FB13R2_FD3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_FB13R2_FD4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_FB13R2_FD5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_FB13R2_FD6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_FB13R2_FD7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_FB13R2_FD8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_FB13R2_FD9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_FB13R2_FD10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_FB13R2_FD11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_FB13R2_FD12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_FB13R2_FD13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_FB13R2_FD14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_FB13R2_FD15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_FB13R2_FD16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_FB13R2_FD17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_FB13R2_FD18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_FB13R2_FD19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_FB13R2_FD20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_FB13R2_FD21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_FB13R2_FD22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_FB13R2_FD23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_FB13R2_FD24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_FB13R2_FD25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_FB13R2_FD26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_FB13R2_FD27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_FB13R2_FD28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_FB13R2_FD29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_FB13R2_FD30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_FB13R2_FD31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SPI_CTRL1 register  ********************/
+#define  SPI_CTRL1_CPHA                         ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CTRL1_CPOL                         ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CTRL1_MSTEN                        ((uint16_t)0x0004)            /*!< Master Selection */
+
+#define  SPI_CTRL1_MCLKP                        ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CTRL1_MCLKP_0                      ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CTRL1_MCLKP_1                      ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CTRL1_MCLKP_2                      ((uint16_t)0x0020)            /*!< Bit 2 */
+
+#define  SPI_CTRL1_SPIEN                        ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CTRL1_LSBEN                        ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CTRL1_ISS                          ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CTRL1_SWNSSEN                      ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CTRL1_RONLY                        ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CTRL1_DFF16                        ((uint16_t)0x0800)            /*!< Data Frame Format */
+#define  SPI_CTRL1_CTN                          ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CTRL1_CCE                          ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CTRL1_BDOE                         ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CTRL1_BDMODE                       ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CTRL2 register  ********************/
+#define  SPI_CTRL2_DMAREN                       ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
+#define  SPI_CTRL2_DMATEN                       ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
+#define  SPI_CTRL2_NSSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
+#define  SPI_CTRL2_ERRIE                        ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
+#define  SPI_CTRL2_RNEIE                        ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CTRL2_TEIE                         ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
+#define  SPI_CTRL2_MCLKP_EXT                    ((uint16_t)0x0100)            /*!< BR[3] bits (Baud Rate Control) */
+#define  SPI_CTRL2_MCLKP_3                      ((uint16_t)0x0100)            /*!< Bit 3 */
+
+/********************  Bit definition for SPI_STS register  ********************/
+#define  SPI_STS_RNE                            ((uint8_t)0x01)               /*!< Receive buffer Not Empty */
+#define  SPI_STS_TE                             ((uint8_t)0x02)               /*!< Transmit buffer Empty */
+#define  SPI_STS_I2SCS                          ((uint8_t)0x04)               /*!< Channel side */
+#define  SPI_STS_UDR                            ((uint8_t)0x08)               /*!< Underrun flag */
+#define  SPI_STS_CERR                           ((uint8_t)0x10)               /*!< CRC Error flag */
+#define  SPI_STS_MODF                           ((uint8_t)0x20)               /*!< Mode fault */
+#define  SPI_STS_OVR                            ((uint8_t)0x40)               /*!< Overrun flag */
+#define  SPI_STS_BSY                            ((uint8_t)0x80)               /*!< Busy flag */
+
+/********************  Bit definition for SPI_DT register  ********************/
+#define  SPI_DT_DT                              ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CPOLY register  ******************/
+#define  SPI_CPOLY_CPOLY                        ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RCRC register  ******************/
+#define  SPI_RCRC_RCRC                          ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TCRC register  ******************/
+#define  SPI_TCRC_TCRC                          ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCTRL register  *****************/
+#define  SPI_I2SCTRL_CHLEN                      ((uint16_t)0x0001)            /*!< Channel length (number of bits per audio channel) */
+
+#define  SPI_I2SCTRL_DLEN                       ((uint16_t)0x0006)            /*!< DATLEN[1:0] bits (Data length to be transferred) */
+#define  SPI_I2SCTRL_DLEN_0                     ((uint16_t)0x0002)            /*!< Bit 0 */
+#define  SPI_I2SCTRL_DLEN_1                     ((uint16_t)0x0004)            /*!< Bit 1 */
+
+#define  SPI_I2SCTRL_CPOL                       ((uint16_t)0x0008)            /*!< steady state clock polarity */
+
+#define  SPI_I2SCTRL_I2SAP                      ((uint16_t)0x0030)            /*!< I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCTRL_I2SAP_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  SPI_I2SCTRL_I2SAP_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  SPI_I2SCTRL_PCMSYNCSEL                 ((uint16_t)0x0080)            /*!< PCM frame synchronization */
+
+#define  SPI_I2SCTRL_I2SMOD                     ((uint16_t)0x0300)            /*!< I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCTRL_I2SMOD_0                   ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  SPI_I2SCTRL_I2SMOD_1                   ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  SPI_I2SCTRL_I2SEN                      ((uint16_t)0x0400)            /*!< I2S Enable */
+#define  SPI_I2SCTRL_I2SSEL                     ((uint16_t)0x0800)            /*!< I2S mode selection */
+
+/******************  Bit definition for SPI_I2SCLKP register  *******************/
+#define  SPI_I2SCLKP_I2SDIV                     ((uint16_t)0x0CFF)            /*!< I2S Linear prescaler */
+#define  SPI_I2SCLKP_I2SODD                     ((uint16_t)0x0100)            /*!< Odd factor for the prescaler */
+#define  SPI_I2SCLKP_I2SMCLKOE                  ((uint16_t)0x0200)            /*!< Master Clock Output Enable */
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CTRL1 register  ********************/
+#define  I2C_CTRL1_PEN                          ((uint16_t)0x0001)            /*!< Peripheral Enable */
+#define  I2C_CTRL1_SMBMODE                      ((uint16_t)0x0002)            /*!< SMBus Mode */
+#define  I2C_CTRL1_SMBTYPE                      ((uint16_t)0x0008)            /*!< SMBus Type */
+#define  I2C_CTRL1_ARPEN                        ((uint16_t)0x0010)            /*!< ARP Enable */
+#define  I2C_CTRL1_PECEN                        ((uint16_t)0x0020)            /*!< PEC Enable */
+#define  I2C_CTRL1_GCEN                         ((uint16_t)0x0040)            /*!< General Call Enable */
+#define  I2C_CTRL1_NOCLKSTRETCH                 ((uint16_t)0x0080)            /*!< Clock Stretching Disable (Slave mode) */
+#define  I2C_CTRL1_STARTGEN                     ((uint16_t)0x0100)            /*!< Start Generation */
+#define  I2C_CTRL1_STOPGEN                      ((uint16_t)0x0200)            /*!< Stop Generation */
+#define  I2C_CTRL1_ACKEN                        ((uint16_t)0x0400)            /*!< Acknowledge Enable */
+#define  I2C_CTRL1_POSEN                        ((uint16_t)0x0800)            /*!< Acknowledge/PEC Position (for data reception) */
+#define  I2C_CTRL1_PECTRA                       ((uint16_t)0x1000)            /*!< Packet Error Checking */
+#define  I2C_CTRL1_SMBALERT                     ((uint16_t)0x2000)            /*!< SMBus Alert */
+#define  I2C_CTRL1_SWRESET                      ((uint16_t)0x8000)            /*!< Software Reset */
+
+/*******************  Bit definition for I2C_CTRL2 register  ********************/
+#define  I2C_CTRL2_CLKFREQ                      ((uint16_t)0x003F)            /*!< FREQ[7:0] bits (Peripheral Clock Frequency) */
+#define  I2C_CTRL2_CLKFREQ_B0                   ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  I2C_CTRL2_CLKFREQ_B1                   ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  I2C_CTRL2_CLKFREQ_B2                   ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  I2C_CTRL2_CLKFREQ_B3                   ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  I2C_CTRL2_CLKFREQ_B4                   ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  I2C_CTRL2_CLKFREQ_B5                   ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  I2C_CTRL2_CLKFREQ_B6                   ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  I2C_CTRL2_CLKFREQ_B7                   ((uint16_t)0x0080)            /*!< Bit 7 */
+
+#define  I2C_CTRL2_ERRITEN                      ((uint16_t)0x0100)            /*!< Error Interrupt Enable */
+#define  I2C_CTRL2_EVTITEN                      ((uint16_t)0x0200)            /*!< Event Interrupt Enable */
+#define  I2C_CTRL2_BUFITEN                      ((uint16_t)0x0400)            /*!< Buffer Interrupt Enable */
+#define  I2C_CTRL2_DMAEN                        ((uint16_t)0x0800)            /*!< DMA Requests Enable */
+#define  I2C_CTRL2_DMALAST                      ((uint16_t)0x1000)            /*!< DMA Last Transfer */
+
+/*******************  Bit definition for I2C_OADDR1 register  *******************/
+#define  I2C_OADDR1_ADDR1_7                     ((uint16_t)0x00FE)            /*!< Interface Address */
+#define  I2C_OADDR1_ADDR8_9                     ((uint16_t)0x0300)            /*!< Interface Address */
+
+#define  I2C_OADDR1_ADDR_B0                     ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  I2C_OADDR1_ADDR_B1                     ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  I2C_OADDR1_ADDR_B2                     ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  I2C_OADDR1_ADDR_B3                     ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  I2C_OADDR1_ADDR_B4                     ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  I2C_OADDR1_ADDR_B5                     ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  I2C_OADDR1_ADDR_B6                     ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  I2C_OADDR1_ADDR_B7                     ((uint16_t)0x0080)            /*!< Bit 7 */
+#define  I2C_OADDR1_ADDR_B8                     ((uint16_t)0x0100)            /*!< Bit 8 */
+#define  I2C_OADDR1_ADDR_B9                     ((uint16_t)0x0200)            /*!< Bit 9 */
+
+#define  I2C_OADDR1_ADDRMODE                    ((uint16_t)0x8000)            /*!< Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OADDR2 register  *******************/
+#define  I2C_OADDR2_DUALEN                      ((uint8_t)0x01)               /*!< Dual addressing mode enable */
+#define  I2C_OADDR2_ADDR2                       ((uint8_t)0xFE)               /*!< Interface address */
+
+/********************  Bit definition for I2C_DT register  ********************/
+#define  I2C_DT_DT                              ((uint8_t)0xFF)               /*!< 8-bit Data Register */
+
+/*******************  Bit definition for I2C_STS1 register  ********************/
+#define  I2C_STS1_STARTF                        ((uint16_t)0x0001)            /*!< Start Bit (Master mode) */
+#define  I2C_STS1_ADDRF                         ((uint16_t)0x0002)            /*!< Address sent (master mode)/matched (slave mode) */
+#define  I2C_STS1_BTFF                          ((uint16_t)0x0004)            /*!< Byte Transfer Finished */
+#define  I2C_STS1_ADDR10F                       ((uint16_t)0x0008)            /*!< 10-bit header sent (Master mode) */
+#define  I2C_STS1_STOPF                         ((uint16_t)0x0010)            /*!< Stop detection (Slave mode) */
+#define  I2C_STS1_RDNE                          ((uint16_t)0x0040)            /*!< Data Register not Empty (receivers) */
+#define  I2C_STS1_TDE                           ((uint16_t)0x0080)            /*!< Data Register Empty (transmitters) */
+#define  I2C_STS1_BUSERR                        ((uint16_t)0x0100)            /*!< Bus Error */
+#define  I2C_STS1_ARLOST                        ((uint16_t)0x0200)            /*!< Arbitration Lost (master mode) */
+#define  I2C_STS1_ACKFAIL                       ((uint16_t)0x0400)            /*!< Acknowledge Failure */
+#define  I2C_STS1_OVRUN                         ((uint16_t)0x0800)            /*!< Overrun/Underrun */
+#define  I2C_STS1_PECERR                        ((uint16_t)0x1000)            /*!< PEC Error in reception */
+#define  I2C_STS1_TIMOUT                        ((uint16_t)0x4000)            /*!< Timeout or Tlow Error */
+#define  I2C_STS1_SMBALERTF                     ((uint16_t)0x8000)            /*!< SMBus Alert */
+
+/*******************  Bit definition for I2C_STS2 register  ********************/
+#define  I2C_STS2_MSF                           ((uint16_t)0x0001)            /*!< Master/Slave */
+#define  I2C_STS2_BUSYF                         ((uint16_t)0x0002)            /*!< Bus Busy */
+#define  I2C_STS2_TRF                           ((uint16_t)0x0004)            /*!< Transmitter/Receiver */
+#define  I2C_STS2_GCADDRF                       ((uint16_t)0x0010)            /*!< General Call Address (Slave mode) */
+#define  I2C_STS2_SMBDEFTADDRF                  ((uint16_t)0x0020)            /*!< SMBus Device Default Address (Slave mode) */
+#define  I2C_STS2_SMBHOSTADDRF                  ((uint16_t)0x0040)            /*!< SMBus Host Header (Slave mode) */
+#define  I2C_STS2_DUALF                         ((uint16_t)0x0080)            /*!< Dual Flag (Slave mode) */
+#define  I2C_STS2_PECVAL                        ((uint16_t)0xFF00)            /*!< Packet Error Checking Register */
+
+/*******************  Bit definition for I2C_CLKCTRL register  ********************/
+#define  I2C_CLKCTRL_CLKCTRL                    ((uint16_t)0x0FFF)            /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CLKCTRL_FMDUTY                     ((uint16_t)0x4000)            /*!< Fast Mode Duty Cycle */
+#define  I2C_CLKCTRL_FSMODE                     ((uint16_t)0x8000)            /*!< I2C Master Mode Selection */
+
+/******************  Bit definition for I2C_TMRISE register  *******************/
+#define  I2C_TMRISE_TMRISE                      ((uint8_t)0x3F)               /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/*                                                                            */
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for USART_STS register  *******************/
+#define  USART_STS_PERR                         ((uint16_t)0x0001)            /*!< Parity Error */
+#define  USART_STS_FERR                         ((uint16_t)0x0002)            /*!< Framing Error */
+#define  USART_STS_NERR                         ((uint16_t)0x0004)            /*!< Noise Error Flag */
+#define  USART_STS_ORERR                        ((uint16_t)0x0008)            /*!< OverRun Error */
+#define  USART_STS_IDLEF                        ((uint16_t)0x0010)            /*!< IDLE line detected */
+#define  USART_STS_RDNE                         ((uint16_t)0x0020)            /*!< Read Data Register Not Empty */
+#define  USART_STS_TRAC                         ((uint16_t)0x0040)            /*!< Transmission Complete */
+#define  USART_STS_TDE                          ((uint16_t)0x0080)            /*!< Transmit Data Register Empty */
+#define  USART_STS_LBDF                         ((uint16_t)0x0100)            /*!< LIN Break Detection Flag */
+#define  USART_STS_CTSF                         ((uint16_t)0x0200)            /*!< CTS Flag */
+
+/*******************  Bit definition for USART_DT register  *******************/
+#define  USART_DT_DT                            ((uint16_t)0x01FF)            /*!< Data value */
+
+/******************  Bit definition for USART_BAUDR register  *******************/
+#define  USART_BAUDR_DIV_Decimal                ((uint16_t)0x000F)            /*!< Fraction of USARTDIV */
+#define  USART_BAUDR_DIV_Integer                ((uint16_t)0xFFF0)            /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CTRL1 register  *******************/
+#define  USART_CTRL1_SBRK                       ((uint16_t)0x0001)            /*!< Send Break */
+#define  USART_CTRL1_RECMUTE                    ((uint16_t)0x0002)            /*!< Receiver wakeup */
+#define  USART_CTRL1_REN                        ((uint16_t)0x0004)            /*!< Receiver Enable */
+#define  USART_CTRL1_TEN                        ((uint16_t)0x0008)            /*!< Transmitter Enable */
+#define  USART_CTRL1_IDLEIEN                    ((uint16_t)0x0010)            /*!< IDLE Interrupt Enable */
+#define  USART_CTRL1_RDNEIEN                    ((uint16_t)0x0020)            /*!< RXNE Interrupt Enable */
+#define  USART_CTRL1_TRACIEN                    ((uint16_t)0x0040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CTRL1_TDEIEN                     ((uint16_t)0x0080)            /*!< PE Interrupt Enable */
+#define  USART_CTRL1_PERRIEN                    ((uint16_t)0x0100)            /*!< PE Interrupt Enable */
+#define  USART_CTRL1_PSEL                       ((uint16_t)0x0200)            /*!< Parity Selection */
+#define  USART_CTRL1_PCEN                       ((uint16_t)0x0400)            /*!< Parity Control Enable */
+#define  USART_CTRL1_WUMODE                     ((uint16_t)0x0800)            /*!< Wakeup method */
+#define  USART_CTRL1_LEN                        ((uint16_t)0x1000)            /*!< Word length */
+#define  USART_CTRL1_UEN                        ((uint16_t)0x2000)            /*!< USART Enable */
+#define  USART_CTRL1_OVER8                      ((uint16_t)0x8000)            /*!< USART Oversmapling 8-bits */
+
+/******************  Bit definition for USART_CTRL2 register  *******************/
+#define  USART_CTRL2_ADDR                       ((uint16_t)0x000F)            /*!< Address of the USART node */
+#define  USART_CTRL2_LBDLEN                     ((uint16_t)0x0020)            /*!< LIN Break Detection Length */
+#define  USART_CTRL2_LBDIEN                     ((uint16_t)0x0040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CTRL2_LBCP                       ((uint16_t)0x0100)            /*!< Last Bit Clock pulse */
+#define  USART_CTRL2_CLKPHA                     ((uint16_t)0x0200)            /*!< Clock Phase */
+#define  USART_CTRL2_CLKPOL                     ((uint16_t)0x0400)            /*!< Clock Polarity */
+#define  USART_CTRL2_CLKEN                      ((uint16_t)0x0800)            /*!< Clock Enable */
+
+#define  USART_CTRL2_STOPB                      ((uint16_t)0x3000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CTRL2_STOP_B0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USART_CTRL2_STOP_B1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USART_CTRL2_LINEN                      ((uint16_t)0x4000)            /*!< LIN mode enable */
+
+/******************  Bit definition for USART_CTRL3 register  *******************/
+#define  USART_CTRL3_ERRIEN                     ((uint16_t)0x0001)            /*!< Error Interrupt Enable */
+#define  USART_CTRL3_IRDAEN                     ((uint16_t)0x0002)            /*!< IrDA mode Enable */
+#define  USART_CTRL3_IRDALP                     ((uint16_t)0x0004)            /*!< IrDA Low-Power */
+#define  USART_CTRL3_HALFSEL                    ((uint16_t)0x0008)            /*!< Half-Duplex Selection */
+#define  USART_CTRL3_NACKEN                     ((uint16_t)0x0010)            /*!< Smartcard NACK enable */
+#define  USART_CTRL3_SCMEN                      ((uint16_t)0x0020)            /*!< Smartcard mode enable */
+#define  USART_CTRL3_DMAREN                     ((uint16_t)0x0040)            /*!< DMA Enable Receiver */
+#define  USART_CTRL3_DMATEN                     ((uint16_t)0x0080)            /*!< DMA Enable Transmitter */
+#define  USART_CTRL3_RTSEN                      ((uint16_t)0x0100)            /*!< RTS Enable */
+#define  USART_CTRL3_CTSEN                      ((uint16_t)0x0200)            /*!< CTS Enable */
+#define  USART_CTRL3_CTSIEN                     ((uint16_t)0x0400)            /*!< CTS Interrupt Enable */
+#define  USART_CTRL3_ONEBIT                     ((uint16_t)0x0800)            /*!< One Bit method */
+
+/******************  Bit definition for USART_GTP register  ******************/
+#define  USART_GTP_PSC                          ((uint16_t)0x00FF)            /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTP_PSC_B0                       ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  USART_GTP_PSC_B1                       ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  USART_GTP_PSC_B2                       ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  USART_GTP_PSC_B3                       ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  USART_GTP_PSC_B4                       ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  USART_GTP_PSC_B5                       ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  USART_GTP_PSC_B6                       ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  USART_GTP_PSC_B7                       ((uint16_t)0x0080)            /*!< Bit 7 */
+
+#define  USART_GTP_GTVAL                        ((uint16_t)0xFF00)            /*!< Guard time value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCR register  *****************/
+#define  MCUDBG_IDCR_DEV_ID                     ((uint32_t)0x00000FFF)        /*!< Device Identifier */
+
+#define  MCUDBG_IDCR_REV_ID                     ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define  MCUDBG_IDCR_REV_ID_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  MCUDBG_IDCR_REV_ID_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  MCUDBG_IDCR_REV_ID_2                   ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  MCUDBG_IDCR_REV_ID_3                   ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  MCUDBG_IDCR_REV_ID_4                   ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  MCUDBG_IDCR_REV_ID_5                   ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  MCUDBG_IDCR_REV_ID_6                   ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  MCUDBG_IDCR_REV_ID_7                   ((uint32_t)0x00800000)        /*!< Bit 7 */
+#define  MCUDBG_IDCR_REV_ID_8                   ((uint32_t)0x01000000)        /*!< Bit 8 */
+#define  MCUDBG_IDCR_REV_ID_9                   ((uint32_t)0x02000000)        /*!< Bit 9 */
+#define  MCUDBG_IDCR_REV_ID_10                  ((uint32_t)0x04000000)        /*!< Bit 10 */
+#define  MCUDBG_IDCR_REV_ID_11                  ((uint32_t)0x08000000)        /*!< Bit 11 */
+#define  MCUDBG_IDCR_REV_ID_12                  ((uint32_t)0x10000000)        /*!< Bit 12 */
+#define  MCUDBG_IDCR_REV_ID_13                  ((uint32_t)0x20000000)        /*!< Bit 13 */
+#define  MCUDBG_IDCR_REV_ID_14                  ((uint32_t)0x40000000)        /*!< Bit 14 */
+#define  MCUDBG_IDCR_REV_ID_15                  ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+/******************  Bit definition for DBGMCU_CTRL register  *******************/
+#define  MCUDBG_CTRL_DBG_SLEEP                  ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
+#define  MCUDBG_CTRL_DBG_STOP                   ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
+#define  MCUDBG_CTRL_DBG_STANDBY                ((uint32_t)0x00000004)        /*!< Debug Standby mode */
+#define  MCUDBG_CTRL_TRACE_IOEN                 ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */
+
+#define  MCUDBG_CTRL_TRACE_MODE                 ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define  MCUDBG_CTRL_TRACE_MODE_0               ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  MCUDBG_CTRL_TRACE_MODE_1               ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  MCUDBG_CTRL_DBG_IWDG_STOP              ((uint32_t)0x00000100)        /*!< Debug Independent Watchdog stopped when Core is halted */
+#define  MCUDBG_CTRL_DBG_WWDG_STOP              ((uint32_t)0x00000200)        /*!< Debug Window Watchdog stopped when Core is halted */
+#define  MCUDBG_CTRL_DBG_TMR1_STOP              ((uint32_t)0x00000400)        /*!< TMR1 counter stopped when core is halted */
+#define  MCUDBG_CTRL_DBG_TMR2_STOP              ((uint32_t)0x00000800)        /*!< TMR2 counter stopped when core is halted */
+#define  MCUDBG_CTRL_DBG_TMR3_STOP              ((uint32_t)0x00001000)        /*!< TMR3 counter stopped when core is halted */
+#define  MCUDBG_CTRL_DBG_TMR4_STOP              ((uint32_t)0x00002000)        /*!< TMR4 counter stopped when core is halted */
+#define  MCUDBG_CTRL_DBG_CAN1_STOP              ((uint32_t)0x00004000)        /*!< Debug CAN1 stopped when Core is halted */
+#define  MCUDBG_CTRL_DBG_I2C1_SMBUS_TIMEOUT     ((uint32_t)0x00008000)        /*!< SMBUS timeout mode stopped when Core is halted */
+#define  MCUDBG_CTRL_DBG_I2C2_SMBUS_TIMEOUT     ((uint32_t)0x00010000)        /*!< SMBUS timeout mode stopped when Core is halted */
+#define  MCUDBG_CTRL_DBG_TMR8_STOP              ((uint32_t)0x00020000)        /*!< TMR8 counter stopped when core is halted */
+#define  MCUDBG_CTRL_DBG_TMR5_STOP              ((uint32_t)0x00040000)        /*!< TMR5 counter stopped when core is halted */
+
+
+#define  MCUDBG_CTRL_DBG_TMR9_STOP              ((uint32_t)0x10000000)        /*!< Debug TMR9 stopped when Core is halted */
+#define  MCUDBG_CTRL_DBG_TMR10_STOP             ((uint32_t)0x20000000)        /*!< Debug TMR10 stopped when Core is halted */
+#define  MCUDBG_CTRL_DBG_TMR11_STOP             ((uint32_t)0x40000000)        /*!< Debug TMR11 stopped when Core is halted */
+
+#ifdef AT32F413xx
+#if !defined (AT32FEBKCx_MD)
+#define  MCUDBG_CTRL_DBG_CAN2_STOP              ((uint32_t)0x00200000)        /*!< Debug CAN2 stopped when Core is halted */
+#endif
+#else
+#define  MCUDBG_CTRL_DBG_TMR6_STOP              ((uint32_t)0x00080000)        /*!< TMR6 counter stopped when core is halted */
+#define  MCUDBG_CTRL_DBG_TMR7_STOP              ((uint32_t)0x00100000)        /*!< TMR7 counter stopped when core is halted */
+#define  MCUDBG_CTRL_DBG_TMR15_STOP             ((uint32_t)0x00400000)        /*!< Debug TMR15 stopped when Core is halted */
+#define  MCUDBG_CTRL_DBG_TMR12_STOP             ((uint32_t)0x02000000)        /*!< Debug TMR12 stopped when Core is halted */
+#define  MCUDBG_CTRL_DBG_TMR13_STOP             ((uint32_t)0x04000000)        /*!< Debug TMR13 stopped when Core is halted */
+#define  MCUDBG_CTRL_DBG_TMR14_STOP             ((uint32_t)0x08000000)        /*!< Debug TMR14 stopped when Core is halted */
+#define  MCUDBG_CTRL_DBG_I2C3_SMBUS_TIMEOUT     ((uint32_t)0x80000000)        /*!< SMBUS timeout mode stopped when Core is halted */
+#endif
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FLASH and Option Bytes Registers                      */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                      ((uint8_t)0x07)               /*!< LATENCY[2:0] bits (Latency) */
+#define  FLASH_ACR_LATENCY_0                    ((uint8_t)0x00)               /*!< Bit 0 */
+#define  FLASH_ACR_LATENCY_1                    ((uint8_t)0x01)               /*!< Bit 0 */
+#define  FLASH_ACR_LATENCY_2                    ((uint8_t)0x02)               /*!< Bit 1 */
+#define  FLASH_ACR_LATENCY_3                    ((uint8_t)0x03)               /*!< Bit 1 & Bit 0 */
+#define  FLASH_ACR_LATENCY_4                    ((uint8_t)0x04)               /*!< Bit 2 */
+#define  FLASH_ACR_LATENCY_5                    ((uint8_t)0x05)               /*!< Bit 2 & Bit 0 */
+
+#define  FLASH_ACR_HLFCYA                       ((uint8_t)0x08)               /*!< Flash Half Cycle Access Enable */
+#define  FLASH_ACR_PRFTBE                       ((uint8_t)0x10)               /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                       ((uint8_t)0x20)               /*!< Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_FCKEY register  ******************/
+#define  FLASH_FCKEY_KEY                        ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
+
+/*****************  Bit definition for FLASH_UOBKEY register  ****************/
+#define  FLASH_UOBKEY_KEY                       ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
+
+/******************  Bit definition for FLASH_STS register  *******************/
+#define  FLASH_STS_BSY                          ((uint8_t)0x01)               /*!< Busy */
+#define  FLASH_STS_PRGMFLR                      ((uint8_t)0x04)               /*!< Programming Error */
+#define  FLASH_STS_WRPRTFLR                     ((uint8_t)0x10)               /*!< Write Protection Error */
+#define  FLASH_STS_PRCDN                        ((uint8_t)0x20)               /*!< End of operation */
+
+/*******************  Bit definition for FLASH_CTRL register  *******************/
+#define  FLASH_CTRL_PRGM                        ((uint16_t)0x0001)            /*!< Programming */
+#define  FLASH_CTRL_PGERS                       ((uint16_t)0x0002)            /*!< Page Erase */
+#define  FLASH_CTRL_CHPERS                      ((uint16_t)0x0004)            /*!< Mass Erase */
+#define  FLASH_CTRL_UOBPRGM                     ((uint16_t)0x0010)            /*!< Option Byte Programming */
+#define  FLASH_CTRL_UOBERS                      ((uint16_t)0x0020)            /*!< Option Byte Erase */
+#define  FLASH_CTRL_STRT                        ((uint16_t)0x0040)            /*!< Start */
+#define  FLASH_CTRL_LCK                         ((uint16_t)0x0080)            /*!< Lock */
+#define  FLASH_CTRL_UOBWE                       ((uint16_t)0x0200)            /*!< Option Bytes Write Enable */
+#define  FLASH_CTRL_FLRIE                       ((uint16_t)0x0400)            /*!< Error Interrupt Enable */
+#define  FLASH_CTRL_PRCDNIE                     ((uint16_t)0x1000)            /*!< End of operation interrupt enable */
+#define  FLASH_CTRL_OPTION_BYTE_PRT_DIS_TRIG    ((uint32_t)0x00010000)        /*!< Disable Option Byte Protection */
+
+/*******************  Bit definition for FLASH_ADDR register  *******************/
+#define  FLASH_ADDR_TA                          ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
+
+/******************  Bit definition for FLASH_UOB register  *******************/
+#define  FLASH_UOB_UOBFLR                       ((uint16_t)0x0001)            /*!< Option Byte Error */
+#define  FLASH_UOB_RDPRTEN                      ((uint16_t)0x0002)            /*!< Read protection */
+
+#define  FLASH_UOB_USR                          ((uint16_t)0x03FC)            /*!< User Option Bytes */
+#define  FLASH_UOB_SW_WDG                       ((uint16_t)0x0004)            /*!< WDG_SW */
+#define  FLASH_UOB_nSTP_RST                     ((uint16_t)0x0008)            /*!< nRST_STOP */
+#define  FLASH_UOB_nSTDBY_RST                   ((uint16_t)0x0010)            /*!< nRST_STDBY */
+#define  FLASH_UOB_BTOPT                        ((uint16_t)0x0020)            /*!< BFB2 */
+
+#define  FLASH_UOB_DATA0                        ((uint32_t)0x0003FC00)        /*!< User data 0 */
+#define  FLASH_UOB_DATA1                        ((uint32_t)0x03FC0000)        /*!< User data 1 */
+#define  FLASH_UOB_OPTION_BYTE_PRT_EN           ((uint32_t)0x04000000)        /*!< Option Byte Protection */
+
+/******************  Bit definition for FLASH_WRPRT register  ******************/
+#define  FLASH_WRPRT_WRPRTBMP                   ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
+
+/******************  Bit definition for FSLIB_CDR0 register  ******************/
+#define  FLASH_SLIB_CDR0_BOOT_DIS               ((uint8_t)0x01)               /*!< Boot mode disable in System Memory */
+#define  FLASH_SLIB_CDR0_SYS_SLIB_EN            ((uint8_t)0x04)               /*!< SLIB code enable in System Memory */
+#define  FLASH_SLIB_CDR0_SLIB_EN                ((uint8_t)0x08)               /*!< SLIB code enable in Flash */
+
+/******************  Bit definition for FSLIB_CDR1 register  ******************/
+#define  FLASH_SLIB_START_PAGE                  ((uint32_t)0x000007FF)        /*!< SLIB Start Page */
+#define  FLASH_SLIB_DATA_START_PAGE             ((uint32_t)0x003FF800)        /*!< SLIB Data Start Page */
+#define  FLASH_SLIB_END_PAGE                    ((uint32_t)0xFFC00000)        /*!< SLIB End Page */
+/******************  Bit definition for FSLIB_PSW register  ******************/
+#define  FLASH_SLIB_PSW_PSW                     ((uint32_t)0xFFFFFFFF)        /*!< SLIB password */
+
+/******************  Bit definition for FSLIB_PSWSTS register  ******************/
+#define  FLASH_SLIB_PSWSTS_PSW_ERR              ((uint8_t)0x01)               /*!< SLIB password mismatch */
+#define  FLASH_SLIB_PSWSTS_PSW_OK               ((uint8_t)0x02)               /*!< SLIB password match */
+#define  FLASH_SLIB_UNLOCK                      ((uint8_t)0x04)               /*!< SLIB unlock status */
+#define  FLASH_SLIB_CNT                         ((uint32_t)0x01FF0000)        /*!< SLIB remaining CFG count */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for FLASH_RDPRT register  *******************/
+#define  FLASH_RDPRT_RDPRT                      ((uint32_t)0x000000FF)        /*!< Read protection option byte */
+#define  FLASH_RDPRT_nRDPRT                     ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
+
+/******************  Bit definition for FLASH_USR register  ******************/
+#define  FLASH_USR_USR                          ((uint32_t)0x00FF0000)        /*!< User option byte */
+#define  FLASH_USR_nUSR                         ((uint32_t)0xFF000000)        /*!< User complemented option byte */
+
+/******************  Bit definition for FLASH_DT0 register  *****************/
+#define  FLASH_DT0_DT0                          ((uint32_t)0x000000FF)        /*!< User data storage option byte */
+#define  FLASH_DT0_nDT0                         ((uint32_t)0x0000FF00)        /*!< User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_DT1 register  *****************/
+#define  FLASH_DT1_DT1                          ((uint32_t)0x00FF0000)        /*!< User data storage option byte */
+#define  FLASH_DT1_nDT1                         ((uint32_t)0xFF000000)        /*!< User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_WRPRT0 register  ******************/
+#define  FLASH_WRPRT0_WRPRT0                    ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  FLASH_WRPRT0_nWRPRT0                   ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPRT1 register  ******************/
+#define  FLASH_WRPRT1_WRPRT1                    ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  FLASH_WRPRT1_nWRPRT1                   ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPRT2 register  ******************/
+#define  FLASH_WRPRT2_WRPRT2                    ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  FLASH_WRPRT2_nWRPRT2                   ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPRT3 register  ******************/
+#define  FLASH_WRPRT3_WRPRT3                    ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  FLASH_WRPRT3_nWRPRT3                   ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FSLIB_SET_PSW register ******************/
+#define  FLASH_SLIB_SET_PSW                     ((uint32_t)0xFFFFFFFF)        /*!< SLIB Password */
+
+/****************** Bit definition for FSLIB_SET_RANGE register ******************/
+#define  FLASH_SLIB_SET_START_PAGE              ((uint32_t)0x000007FF)        /*!< SLIB Start Page */
+#define  FLASH_SLIB_SET_DATA_START_PAGE         ((uint32_t)0x003FF800)        /*!< SLIB Data Start Page */
+#define  FLASH_SLIB_SET_END_PAGE                ((uint32_t)0xFFC00000)        /*!< SLIB End Page */
+
+/****************** Bit definition for SLIB_KEYR register ******************/
+#define  FLASH_SLIB_KEYR                        ((uint32_t)0xFFFFFFFF)        /*!< SLIB Unlock Key Register */
+
+#if defined (AT32F407xx)
+/******************************************************************************/
+/*                                                                            */
+/*               Ethernet MAC Registers bits definitions                      */
+/*                                                                            */
+/******************************************************************************/
+/********** Bit definition for Ethernet MAC Control Register register ***********/
+#define ETH_MACCTRL_WDOGD                          ((uint32_t)0x00800000)        /*!< Watchdog disable */
+#define ETH_MACCTRL_JAD                            ((uint32_t)0x00400000)        /*!< Jabber disable */
+
+#define ETH_MACCTRL_FG                             ((uint32_t)0x000E0000)        /*!< Inter-frame gap */
+#define ETH_MACCTRL_FG_96Bit                       ((uint32_t)0x00000000)        /*!< Minimum IFG between frames during transmission is 96Bit */
+#define ETH_MACCTRL_FG_88Bit                       ((uint32_t)0x00020000)        /*!< Minimum IFG between frames during transmission is 88Bit */
+#define ETH_MACCTRL_FG_80Bit                       ((uint32_t)0x00040000)        /*!< Minimum IFG between frames during transmission is 80Bit */
+#define ETH_MACCTRL_FG_72Bit                       ((uint32_t)0x00060000)        /*!< Minimum IFG between frames during transmission is 72Bit */
+#define ETH_MACCTRL_FG_64Bit                       ((uint32_t)0x00080000)        /*!< Minimum IFG between frames during transmission is 64Bit */
+#define ETH_MACCTRL_FG_56Bit                       ((uint32_t)0x000A0000)        /*!< Minimum IFG between frames during transmission is 56Bit */
+#define ETH_MACCTRL_FG_48Bit                       ((uint32_t)0x000C0000)        /*!< Minimum IFG between frames during transmission is 48Bit */
+#define ETH_MACCTRL_FG_40Bit                       ((uint32_t)0x000E0000)        /*!< Minimum IFG between frames during transmission is 40Bit */
+
+#define ETH_MACCTRL_CSD                            ((uint32_t)0x00010000)        /*!< Carrier sense disable (during transmission) */
+#define ETH_MACCTRL_FESM                           ((uint32_t)0x00004000)        /*!< Fast ethernet speed */
+#define ETH_MACCTRL_ROD                            ((uint32_t)0x00002000)        /*!< Receive own disable */
+#define ETH_MACCTRL_LBM                            ((uint32_t)0x00001000)        /*!< loopback mode */
+#define ETH_MACCTRL_DM                             ((uint32_t)0x00000800)        /*!< Duplex mode */
+#define ETH_MACCTRL_IP4CO                          ((uint32_t)0x00000400)        /*!< IP Checksum offload */
+#define ETH_MACCTRL_RD                             ((uint32_t)0x00000200)        /*!< Retry disable */
+#define ETH_MACCTRL_AUPCS                          ((uint32_t)0x00000080)        /*!< Automatic Pad/CRC stripping */
+
+#define ETH_MACCTRL_BOL                            ((uint32_t)0x00000060)        /*!< Back-off limit: random integer number (r) of slot time delays before rescheduling
+                                                                                   a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define ETH_MACCTRL_BOL_10                         ((uint32_t)0x00000000)        /*!< k = min (n, 10) */
+#define ETH_MACCTRL_BOL_8                          ((uint32_t)0x00000020)        /*!< k = min (n, 8) */
+#define ETH_MACCTRL_BOL_4                          ((uint32_t)0x00000040)        /*!< k = min (n, 4) */
+#define ETH_MACCTRL_BOL_1                          ((uint32_t)0x00000060)        /*!< k = min (n, 1) */
+
+#define ETH_MACCTRL_DC                             ((uint32_t)0x00000010)        /*!< Defferal check */
+#define ETH_MACCTRL_TE                             ((uint32_t)0x00000008)        /*!< Transmitter enable */
+#define ETH_MACCTRL_RE                             ((uint32_t)0x00000004)        /*!< Receiver enable */
+
+/************** Bit definition for Ethernet MAC Frame Filter Register ***************/
+#define ETH_MACFRMF_RALL                           ((uint32_t)0x80000000)        /*!< Receive all */
+#define ETH_MACFRMF_HOPF                           ((uint32_t)0x00000400)        /*!< Hash or perfect filter */
+#define ETH_MACFRMF_SADDRF                         ((uint32_t)0x00000200)        /*!< Source address filter enable */
+#define ETH_MACFRMF_SADDRIF                        ((uint32_t)0x00000100)        /*!< SA inverse filtering */
+
+#define ETH_MACFRMF_PCF                            ((uint32_t)0x000000C0)        /*!< Pass control frames: 3 cases */
+#define ETH_MACFRMF_PCF_BlockAll                   ((uint32_t)0x00000040)        /*!< MAC filters all control frames from reaching the application */
+#define ETH_MACFRMF_PCF_ForwardAll                 ((uint32_t)0x00000080)        /*!< MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACFRMF_ForwardPassedAddrFilter        ((uint32_t)0x000000C0)        /*!< MAC forwards control frames that pass the Address Filter. */
+
+#define ETH_MACFRMF_BFD                            ((uint32_t)0x00000020)        /*!< Broadcast frame disable */
+#define ETH_MACFRMF_PALLM                          ((uint32_t)0x00000010)        /*!< Pass all mutlicast */
+#define ETH_MACFRMF_DADDRIF                        ((uint32_t)0x00000008)        /*!< DA Inverse filtering */
+#define ETH_MACFRMF_HM                             ((uint32_t)0x00000004)        /*!< Hash multicast */
+#define ETH_MACFRMF_HU                             ((uint32_t)0x00000002)        /*!< Hash unicast */
+#define ETH_MACFRMF_PM                             ((uint32_t)0x00000001)        /*!< Promiscuous mode */
+
+/************ Bit definition for Ethernet MAC Hash Table High Register *************/
+#define ETH_MACHTH_HTH                             ((uint32_t)0xFFFFFFFF)        /*!< Hash table high */
+
+/************* Bit definition for Ethernet MAC Hash Table Low Register *************/
+#define ETH_MACHTL_HTL                             ((uint32_t)0xFFFFFFFF)        /*!< Hash table low */
+
+/************** Bit definition for Ethernet MAC MII Address Register ***************/
+#define ETH_MACMIIADDR_PA                          ((uint32_t)0x0000F800)        /*!< Physical layer address */
+#define ETH_MACMIIADDR_MII                         ((uint32_t)0x000007C0)        /*!< MII register in the selected PHY */
+
+#define ETH_MACMIIADDR_CLKR                        ((uint32_t)0x0000001C)        /*!< CR clock range: 6 cases */
+#define ETH_MACMIIADDR_CLKR_DIV42                  ((uint32_t)0x00000000)        /*!< HCLK:60-72 MHz; MDC clock= HCLK/42 */
+#define ETH_MACMIIADDR_CLKR_DIV62                  ((uint32_t)0x00000004)        /*!< HCLK:100-150 MHz; MDC clock= HCLK/62 */
+#define ETH_MACMIIADDR_CLKR_DIV16                  ((uint32_t)0x00000008)        /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */
+#define ETH_MACMIIADDR_CLKR_DIV26                  ((uint32_t)0x0000000C)        /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIADDR_CLKR_DIV102                 ((uint32_t)0x00000010)        /*!< HCLK:150-250 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIADDR_CLKR_DIV124                 ((uint32_t)0x00000014)        /*!< HCLK:250-300 MHz; MDC clock= HCLK/124 */
+
+#define ETH_MACMIIADDR_MIIW                        ((uint32_t)0x00000002)        /*!< MII write */
+#define ETH_MACMIIADDR_MIIB                        ((uint32_t)0x00000001)        /*!< MII busy */
+
+/**************** Bit definition for Ethernet MAC MII Data Register ****************/
+#define ETH_MACMIIDT_MIID                          ((uint32_t)0x0000FFFF)        /*!< MII data: read/write data from/to PHY */
+
+/************** Bit definition for Ethernet MAC Flow Control Register **************/
+#define ETH_MACFCTRL_PTM                           ((uint32_t)0xFFFF0000)        /*!< Pause time */
+#define ETH_MACFCTRL_ZQPD                          ((uint32_t)0x00000080)        /*!< Zero-quanta pause disable */
+
+#define ETH_MACFCTRL_PLT                           ((uint32_t)0x00000030)        /*!< Pause low threshold: 4 cases */
+#define ETH_MACFCTRL_PLT_Minus4                    ((uint32_t)0x00000000)        /*!< Pause time minus 4 slot times */
+#define ETH_MACFCTRL_PLT_Minus28                   ((uint32_t)0x00000010)        /*!< Pause time minus 28 slot times */
+#define ETH_MACFCTRL_PLT_Minus144                  ((uint32_t)0x00000020)        /*!< Pause time minus 144 slot times */
+#define ETH_MACFCTRL_PLT_Minus256                  ((uint32_t)0x00000030)        /*!< Pause time minus 256 slot times */
+
+#define ETH_MACFCTRL_UPFD                          ((uint32_t)0x00000008)        /*!< Unicast pause frame detect */
+#define ETH_MACFCTRL_RFCEN                         ((uint32_t)0x00000004)        /*!< Receive flow control enable */
+#define ETH_MACFCTRL_TFCEN                         ((uint32_t)0x00000002)        /*!< Transmit flow control enable */
+#define ETH_MACFCTRL_FCBBPA                        ((uint32_t)0x00000001)        /*!< Flow control busy/backpressure activate */
+
+/************** Bit definition for Ethernet MAC VLAN Tag Register ****************/
+#define ETH_MACVLT_VLTC                            ((uint32_t)0x00010000)        /*!< 12-bit VLAN tag comparison */
+#define ETH_MACVLT_VLTI                            ((uint32_t)0x0000FFFF)        /*!< VLAN tag identifier (for receive frames) */
+
+/****** Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register ******/
+#define ETH_MACRWFF_D                              ((uint32_t)0xFFFFFFFF)        /*!< Wake-up frame filter register data */
+
+/*!< Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/*!< Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
+                              RSVD - Filter1 Command - RSVD - Filter0 Command
+   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/******** Bit definition for Ethernet MAC PMT Control and Status Register **********/
+#define ETH_MACPMTCTRLSTS_WFFPR                    ((uint32_t)0x80000000)        /*!< Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCTRLSTS_GLBU                     ((uint32_t)0x00000200)        /*!< Global Unicast */
+#define ETH_MACPMTCTRLSTS_WFR                      ((uint32_t)0x00000040)        /*!< Wake-Up Frame Received */
+#define ETH_MACPMTCTRLSTS_MPR                      ((uint32_t)0x00000020)        /*!< Magic Packet Received */
+#define ETH_MACPMTCTRLSTS_WFEN                     ((uint32_t)0x00000004)        /*!< Wake-Up Frame Enable */
+#define ETH_MACPMTCTRLSTS_MPEN                     ((uint32_t)0x00000002)        /*!< Magic Packet Enable */
+#define ETH_MACPMTCTRLSTS_PD                       ((uint32_t)0x00000001)        /*!< Power Down */
+
+/**************** Bit definition for Ethernet MAC Status Register ******************/
+#define ETH_MACISTS_TSTS                           ((uint32_t)0x00000200)        /*!< Time stamp trigger status */
+#define ETH_MACISTS_MMCTS                          ((uint32_t)0x00000040)        /*!< MMC transmit status */
+#define ETH_MACISTS_MMCRS                          ((uint32_t)0x00000020)        /*!< MMC receive status */
+#define ETH_MACISTS_MMCS                           ((uint32_t)0x00000010)        /*!< MMC status */
+#define ETH_MACISTS_PMTS                           ((uint32_t)0x00000008)        /*!< PMT status */
+
+/************ Bit definition for Ethernet MAC Interrupt Mask Register **************/
+#define ETH_MACIM_TSTINTM                          ((uint32_t)0x00000200)        /*!< Time stamp trigger interrupt mask */
+#define ETH_MACIM_PMTINTM                          ((uint32_t)0x00000008)        /*!< PMT interrupt mask */
+
+/************ Bit definition for Ethernet MAC Address0 High Register ***************/
+#define ETH_MACA0H_MACADDR0H                       ((uint32_t)0x0000FFFF)        /*!< MAC address0 high */
+
+/************* Bit definition for Ethernet MAC Address0 Low Register ***************/
+#define ETH_MACA0L_MACADDR0L                       ((uint32_t)0xFFFFFFFF)        /*!< MAC address0 low */
+
+/************* Bit definition for Ethernet MAC Address1 High Register **************/
+#define ETH_MACA1H_AEN                             ((uint32_t)0x80000000)        /*!< Address enable */
+#define ETH_MACA1H_SADDR                           ((uint32_t)0x40000000)        /*!< Source address */
+
+#define ETH_MACA1H_MBCTRL                          ((uint32_t)0x3F000000)        /*!< Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define ETH_MACA1H_MBCTRL_HBits15_8                ((uint32_t)0x20000000)        /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA1H_MBCTRL_HBits7_0                 ((uint32_t)0x10000000)        /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA1H_MBCTRL_LBits31_24               ((uint32_t)0x08000000)        /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA1H_MBCTRL_LBits23_16               ((uint32_t)0x04000000)        /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA1H_MBCTRL_LBits15_8                ((uint32_t)0x02000000)        /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA1H_MBCTRL_LBits7_0                 ((uint32_t)0x01000000)        /*!< Mask MAC Address low reg bits [7:0] */
+
+#define ETH_MACA1H_MACADDR1H                       ((uint32_t)0x0000FFFF)        /*!< MAC address1 high */
+/************** Bit definition for Ethernet MAC Address1 Low Register **************/
+
+#define ETH_MACA1L_MACADDR1L                       ((uint32_t)0xFFFFFFFF)        /*!< MAC address1 low */
+
+/************** Bit definition for Ethernet MAC Address2 High Register *************/
+#define ETH_MACA2H_AEN                             ((uint32_t)0x80000000)        /*!< Address enable */
+#define ETH_MACA2H_SADDR                           ((uint32_t)0x40000000)        /*!< Source address */
+
+#define ETH_MACA2H_MBCTRL                          ((uint32_t)0x3F000000)        /*!< Mask byte control */
+#define ETH_MACA2H_MBCTRL_HBits15_8                ((uint32_t)0x20000000)        /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA2H_MBCTRL_HBits7_0                 ((uint32_t)0x10000000)        /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA2H_MBCTRL_LBits31_24               ((uint32_t)0x08000000)        /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA2H_MBCTRL_LBits23_16               ((uint32_t)0x04000000)        /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA2H_MBCTRL_LBits15_8                ((uint32_t)0x02000000)        /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA2H_MBCTRL_LBits7_0                 ((uint32_t)0x01000000)        /*!< Mask MAC Address low reg bits [70] */
+
+#define ETH_MACA2H_MACADDR2H                       ((uint32_t)0x0000FFFF)        /*!< MAC address1 high */
+
+/************** Bit definition for Ethernet MAC Address2 Low Register **************/
+#define ETH_MACA2L_MACADDR2L                       ((uint32_t)0xFFFFFFFF)        /*!< MAC address2 low */
+
+/************** Bit definition for Ethernet MAC Address3 High Register *************/
+#define ETH_MACA3H_AEN                             ((uint32_t)0x80000000)        /*!< Address enable */
+#define ETH_MACA3H_SADDR                           ((uint32_t)0x40000000)        /*!< Source address */
+
+#define ETH_MACA3H_MBCTRL                          ((uint32_t)0x3F000000)        /*!< Mask byte control */
+#define ETH_MACA3H_MBCTRL_HBits15_8                ((uint32_t)0x20000000)        /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA3H_MBCTRL_HBits7_0                 ((uint32_t)0x10000000)        /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA3H_MBCTRL_LBits31_24               ((uint32_t)0x08000000)        /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA3H_MBCTRL_LBits23_16               ((uint32_t)0x04000000)        /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA3H_MBCTRL_LBits15_8                ((uint32_t)0x02000000)        /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA3H_MBCTRL_LBits7_0                 ((uint32_t)0x01000000)        /*!< Mask MAC Address low reg bits [70] */
+
+#define ETH_MACA3H_MACADDR3H                       ((uint32_t)0x0000FFFF)        /*!< MAC address3 high */
+
+/************** Bit definition for Ethernet MAC Address3 Low Register **************/
+#define ETH_MACA3L_MACADDR3L                       ((uint32_t)0xFFFFFFFF)        /*!< MAC address3 low */
+
+/******************************************************************************/
+/*                                                                            */
+/*               Ethernet MMC Registers bits definition                       */
+/*                                                                            */
+/******************************************************************************/
+
+/***************** Bit definition for Ethernet MMC Contol Register *****************/
+#define ETH_MMCCTRL_MCNTF                         ((uint32_t)0x00000008)        /*!< MMC Counter Freeze */
+#define ETH_MMCCTRL_RSTOR                         ((uint32_t)0x00000004)        /*!< Reset on Read */
+#define ETH_MMCCTRL_CSR                           ((uint32_t)0x00000002)        /*!< Counter Stop Rollover */
+#define ETH_MMCCTRL_CNTR                          ((uint32_t)0x00000001)        /*!< Counters Reset */
+
+/*********** Bit definition for Ethernet MMC Receive Interrupt Register ************/
+#define ETH_MMCRI_RGUF                            ((uint32_t)0x00020000)        /*!< Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRI_RFAE                            ((uint32_t)0x00000040)        /*!< Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRI_RFCE                            ((uint32_t)0x00000020)        /*!< Set when Rx crc error counter reaches half the maximum value */
+
+/*********** Bit definition for Ethernet MMC Transmit Interrupt Register ***********/
+#define ETH_MMCTI_TGF                             ((uint32_t)0x00200000)        /*!< Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTI_TGFMSC                          ((uint32_t)0x00008000)        /*!< Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTI_TGFSC                           ((uint32_t)0x00004000)        /*!< Set when Tx good single col counter reaches half the maximum value */
+
+/********* Bit definition for Ethernet MMC Receive Interrupt Mask Register *********/
+#define ETH_MMCRIM_RGUFM                          ((uint32_t)0x00020000)        /*!< Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIM_RFAEM                          ((uint32_t)0x00000040)        /*!< Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIM_RFCEM                          ((uint32_t)0x00000020)        /*!< Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/********* Bit definition for Ethernet MMC Transmit Interrupt Mask Register ********/
+#define ETH_MMCTIM_TGFM                           ((uint32_t)0x00200000)        /*!< Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIM_TGFMSCM                        ((uint32_t)0x00008000)        /*!< Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIM_TGFSCM                         ((uint32_t)0x00004000)        /*!< Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/** Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTFSCC_TGFSCC                       ((uint32_t)0xFFFFFFFF)        /*!< Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/** Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTFMSCC_TGFMSCC                     ((uint32_t)0xFFFFFFFF)        /*!< Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/***** Bit definition for Ethernet MMC Transmitted Good Frames Counter Register ****/
+#define ETH_MMCTFCNT_TGFC                         ((uint32_t)0xFFFFFFFF)        /*!< Number of good frames transmitted. */
+/** Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECNT_RFCEC                      ((uint32_t)0xFFFFFFFF)        /*!< Number of frames received with CRC error. */
+
+/** Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECNT_RFAEC                      ((uint32_t)0xFFFFFFFF)        /*!< Number of frames received with alignment (dribble) error */
+
+/** Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCNT_RGUFC                      ((uint32_t)0xFFFFFFFF)        /*!< Number of good unicast frames received. */
+
+/******************************************************************************/
+/*                                                                            */
+/*               Ethernet PTP Registers bits definition                       */
+/*                                                                            */
+/******************************************************************************/
+
+/************ Bit definition for Ethernet PTP Time Stamp Contol Register ***********/
+#define ETH_PTPTSCTRL_TSARU                       ((uint32_t)0x00000020)        /*!< Addend register update */
+#define ETH_PTPTSCTRL_TSITE                       ((uint32_t)0x00000010)        /*!< Time stamp interrupt trigger enable */
+#define ETH_PTPTSCTRL_TSSTU                       ((uint32_t)0x00000008)        /*!< Time stamp update */
+#define ETH_PTPTSCTRL_TSSTI                       ((uint32_t)0x00000004)        /*!< Time stamp initialize */
+#define ETH_PTPTSCTRL_TSFCU                       ((uint32_t)0x00000002)        /*!< Time stamp fine or coarse update */
+#define ETH_PTPTSCTRL_TSE                         ((uint32_t)0x00000001)        /*!< Time stamp enable */
+
+/********** Bit definition for Ethernet PTP Sub-Second Increment Register **********/
+#define ETH_PTPSSINC_STSINC                       ((uint32_t)0x000000FF)        /*!< System time Sub-second increment value */
+
+/************ Bit definition for Ethernet PTP Time Stamp High Register *************/
+#define ETH_PTPTSH_STS                            ((uint32_t)0xFFFFFFFF)        /*!< System Time second */
+
+/************ Bit definition for Ethernet PTP Time Stamp Low Register **************/
+#define ETH_PTPTSL_STPNS                          ((uint32_t)0x80000000)        /*!< System Time Positive or negative time */
+#define ETH_PTPTSL_STSS                           ((uint32_t)0x7FFFFFFF)        /*!< System Time sub-seconds */
+
+/********* Bit definition for Ethernet PTP Time Stamp High Update Register *********/
+#define ETH_PTPTSHUD_TSUS                         ((uint32_t)0xFFFFFFFF)        /*!< Time stamp update seconds */
+
+/********* Bit definition for Ethernet PTP Time Stamp Low Update Register **********/
+#define ETH_PTPTSLUD_TSUPNS                       ((uint32_t)0x80000000)        /*!< Time stamp update Positive or negative time */
+#define ETH_PTPTSLUD_TSUSS                        ((uint32_t)0x7FFFFFFF)        /*!< Time stamp update sub-seconds */
+
+/*********** Bit definition for Ethernet PTP Time Stamp Addend Register ************/
+#define ETH_PTPTSAD_TSA                           ((uint32_t)0xFFFFFFFF)        /*!< Time stamp addend */
+
+/*********** Bit definition for Ethernet PTP Target Time High Register *************/
+#define ETH_PTPTTH_TTSH                           ((uint32_t)0xFFFFFFFF)        /*!< Target time stamp high */
+
+/************ Bit definition for Ethernet PTP Target Time Low Register *************/
+#define ETH_PTPTTL_TTSL                           ((uint32_t)0xFFFFFFFF)        /*!< Target time stamp low */
+
+/******************************************************************************/
+/*                                                                            */
+/*               Ethernet DMA Registers bits definition                       */
+/*                                                                            */
+/******************************************************************************/
+
+/**************** Bit definition for Ethernet DMA Bus Mode Register ****************/
+#define ETH_DMABM_AAB                          ((uint32_t)0x02000000)        /*!< Address-Aligned beats */
+#define ETH_DMABM_FPBLM                        ((uint32_t)0x01000000)        /*!< 4xPBL mode */
+#define ETH_DMABM_USP                          ((uint32_t)0x00800000)        /*!< Use separate PBL */
+
+#define ETH_DMABM_RDPBL                        ((uint32_t)0x007E0000)        /*!< RxDMA PBL */
+#define ETH_DMABM_RDPBL_1Beat                  ((uint32_t)0x00020000)        /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_DMABM_RDPBL_2Beat                  ((uint32_t)0x00040000)        /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_DMABM_RDPBL_4Beat                  ((uint32_t)0x00080000)        /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABM_RDPBL_8Beat                  ((uint32_t)0x00100000)        /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABM_RDPBL_16Beat                 ((uint32_t)0x00200000)        /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABM_RDPBL_32Beat                 ((uint32_t)0x00400000)        /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABM_RDPBL_4xPBL_4Beat            ((uint32_t)0x01020000)        /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABM_RDPBL_4xPBL_8Beat            ((uint32_t)0x01040000)        /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABM_RDPBL_4xPBL_16Beat           ((uint32_t)0x01080000)        /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABM_RDPBL_4xPBL_32Beat           ((uint32_t)0x01100000)        /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABM_RDPBL_4xPBL_64Beat           ((uint32_t)0x01200000)        /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_DMABM_RDPBL_4xPBL_128Beat          ((uint32_t)0x01400000)        /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
+
+#define ETH_DMABM_FB                           ((uint32_t)0x00010000)        /*!< Fixed Burst */
+
+#define ETH_DMABM_RTPR                         ((uint32_t)0x0000C000)        /*!< Rx Tx priority ratio */
+#define ETH_DMABM_RTPR_1_1                     ((uint32_t)0x00000000)        /*!< Rx Tx priority ratio */
+#define ETH_DMABM_RTPR_2_1                     ((uint32_t)0x00004000)        /*!< Rx Tx priority ratio */
+#define ETH_DMABM_RTPR_3_1                     ((uint32_t)0x00008000)        /*!< Rx Tx priority ratio */
+#define ETH_DMABM_RTPR_4_1                     ((uint32_t)0x0000C000)        /*!< Rx Tx priority ratio */
+
+#define ETH_DMABM_PBL                          ((uint32_t)0x00003F00)        /*!< Programmable burst length */
+#define ETH_DMABM_PBL_1Beat                    ((uint32_t)0x00000100)        /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_DMABM_PBL_2Beat                    ((uint32_t)0x00000200)        /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_DMABM_PBL_4Beat                    ((uint32_t)0x00000400)        /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABM_PBL_8Beat                    ((uint32_t)0x00000800)        /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABM_PBL_16Beat                   ((uint32_t)0x00001000)        /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABM_PBL_32Beat                   ((uint32_t)0x00002000)        /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABM_PBL_4xPBL_4Beat              ((uint32_t)0x01000100)        /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABM_PBL_4xPBL_8Beat              ((uint32_t)0x01000200)        /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABM_PBL_4xPBL_16Beat             ((uint32_t)0x01000400)        /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABM_PBL_4xPBL_32Beat             ((uint32_t)0x01000800)        /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABM_PBL_4xPBL_64Beat             ((uint32_t)0x01001000)        /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_DMABM_PBL_4xPBL_128Beat            ((uint32_t)0x01002000)        /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+
+#define ETH_DMABM_DSL                          ((uint32_t)0x0000007C)        /*!< Descriptor Skip Length */
+#define ETH_DMABM_DA                           ((uint32_t)0x00000002)        /*!< DMA arbitration scheme */
+#define ETH_DMABM_SWRST                        ((uint32_t)0x00000001)        /*!< Software reset */
+
+/********** Bit definition for Ethernet DMA Transmit Poll Demand Register **********/
+#define ETH_DMATPD_TPD                         ((uint32_t)0xFFFFFFFF)        /*!< Transmit poll demand */
+
+/********** Bit definition for Ethernet DMA Receive Poll Demand Register ***********/
+#define ETH_DMARPD_RPD                         ((uint32_t)0xFFFFFFFF)        /*!< Receive poll demand  */
+
+/**** Bit definition for Ethernet DMA Receive Descriptor List Address Register *****/
+#define ETH_DMARDLADDR_SRL                     ((uint32_t)0xFFFFFFFF)        /*!< Start of receive list */
+
+/**** Bit definition for Ethernet DMA Transmit Descriptor List Address Register ****/
+#define ETH_DMATDLADDR_STL                     ((uint32_t)0xFFFFFFFF)        /*!< Start of transmit list */
+
+/***************** Bit definition for Ethernet DMA Status Register *****************/
+#define ETH_DMASTS_TST                          ((uint32_t)0x20000000)        /*!< Time-stamp trigger status */
+#define ETH_DMASTS_PMT                          ((uint32_t)0x10000000)        /*!< PMT status */
+#define ETH_DMASTS_MMC                          ((uint32_t)0x08000000)        /*!< MMC status */
+
+#define ETH_DMASTS_EB                           ((uint32_t)0x03800000)        /*!< Error bits status */
+#define ETH_DMASTS_EB_DescAccess                ((uint32_t)0x02000000)        /*!< Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMASTS_EB_ReadTransf                ((uint32_t)0x01000000)        /*!< Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMASTS_EB_DataTransfTx              ((uint32_t)0x00800000)        /*!< Error bits 0-Rx DMA, 1-Tx DMA */
+
+#define ETH_DMASTS_TP                           ((uint32_t)0x00700000)        /*!< Transmit process state */
+#define ETH_DMASTS_TP_Stopped                   ((uint32_t)0x00000000)        /*!< Stopped - Reset or Stop Tx Command issued  */
+#define ETH_DMASTS_TP_Fetching                  ((uint32_t)0x00100000)        /*!< Running - fetching the Tx descriptor */
+#define ETH_DMASTS_TP_Waiting                   ((uint32_t)0x00200000)        /*!< Running - waiting for status */
+#define ETH_DMASTS_TP_Reading                   ((uint32_t)0x00300000)        /*!< Running - reading the data from host memory */
+#define ETH_DMASTS_TP_Suspended                 ((uint32_t)0x00600000)        /*!< Suspended - Tx Descriptor unavailabe */
+#define ETH_DMASTS_TP_Closing                   ((uint32_t)0x00700000)        /*!< Running - closing Rx descriptor */
+
+#define ETH_DMASTS_RP                           ((uint32_t)0x000E0000)        /*!< Receive process state */
+#define ETH_DMASTS_RP_Stopped                   ((uint32_t)0x00000000)        /*!< Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMASTS_RP_Fetching                  ((uint32_t)0x00020000)        /*!< Running - fetching the Rx descriptor */
+#define ETH_DMASTS_RP_Waiting                   ((uint32_t)0x00060000)        /*!< Running - waiting for packet */
+#define ETH_DMASTS_RP_Suspended                 ((uint32_t)0x00080000)        /*!< Suspended - Rx Descriptor unavailable */
+#define ETH_DMASTS_RP_Closing                   ((uint32_t)0x000A0000)        /*!< Running - closing descriptor */
+#define ETH_DMASTS_RP_Queuing                   ((uint32_t)0x000E0000)        /*!< Running - queuing the recieve frame into host memory */
+
+#define ETH_DMASTS_NIS                          ((uint32_t)0x00010000)        /*!< Normal interrupt summary */
+#define ETH_DMASTS_AIS                          ((uint32_t)0x00008000)        /*!< Abnormal interrupt summary */
+#define ETH_DMASTS_ER                           ((uint32_t)0x00004000)        /*!< Early receive status */
+#define ETH_DMASTS_FBE                          ((uint32_t)0x00002000)        /*!< Fatal bus error status */
+#define ETH_DMASTS_ET                           ((uint32_t)0x00000400)        /*!< Early transmit status */
+#define ETH_DMASTS_RWT                          ((uint32_t)0x00000200)        /*!< Receive watchdog timeout status */
+#define ETH_DMASTS_RPS                          ((uint32_t)0x00000100)        /*!< Receive process stopped status */
+#define ETH_DMASTS_RBU                          ((uint32_t)0x00000080)        /*!< Receive buffer unavailable status */
+#define ETH_DMASTS_RECV                         ((uint32_t)0x00000040)        /*!< Receive status */
+#define ETH_DMASTS_TU                           ((uint32_t)0x00000020)        /*!< Transmit underflow status */
+#define ETH_DMASTS_RO                           ((uint32_t)0x00000010)        /*!< Receive overflow status */
+#define ETH_DMASTS_TJT                          ((uint32_t)0x00000008)        /*!< Transmit jabber timeout status */
+#define ETH_DMASTS_TBU                          ((uint32_t)0x00000004)        /*!< Transmit buffer unavailable status */
+#define ETH_DMASTS_TPS                          ((uint32_t)0x00000002)        /*!< Transmit process stopped status */
+#define ETH_DMASTS_TX                           ((uint32_t)0x00000001)        /*!< Transmit status */
+
+/************* Bit definition for Ethernet DMA Operation Mode Register *************/
+#define ETH_DMAOPM_DTCEFD                       ((uint32_t)0x04000000)        /*!< Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOPM_RSFD                         ((uint32_t)0x02000000)        /*!< Receive store and forward */
+#define ETH_DMAOPM_DFRFD                        ((uint32_t)0x01000000)        /*!< Disable flushing of received frames */
+#define ETH_DMAOPM_TXSF                         ((uint32_t)0x00200000)        /*!< Transmit store and forward */
+#define ETH_DMAOPM_FTXF                         ((uint32_t)0x00100000)        /*!< Flush transmit FIFO */
+
+#define ETH_DMAOPM_TXTC                         ((uint32_t)0x0001C000)        /*!< Transmit threshold control */
+#define ETH_DMAOPM_TXTC_64Bytes                 ((uint32_t)0x00000000)        /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_DMAOPM_TXTC_128Bytes                ((uint32_t)0x00004000)        /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_DMAOPM_TXTC_192Bytes                ((uint32_t)0x00008000)        /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_DMAOPM_TXTC_256Bytes                ((uint32_t)0x0000C000)        /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_DMAOPM_TXTC_40Bytes                 ((uint32_t)0x00010000)        /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_DMAOPM_TXTC_32Bytes                 ((uint32_t)0x00014000)        /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_DMAOPM_TXTC_24Bytes                 ((uint32_t)0x00018000)        /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_DMAOPM_TXTC_16Bytes                 ((uint32_t)0x0001C000)        /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
+
+#define ETH_DMAOPM_STXE                         ((uint32_t)0x00002000)        /*!< Start/stop transmission command */
+#define ETH_DMAOPM_FEF                          ((uint32_t)0x00000080)        /*!< Forward error frames */
+#define ETH_DMAOPM_FUGF                         ((uint32_t)0x00000040)        /*!< Forward undersized good frames */
+
+#define ETH_DMAOPM_RXTC                         ((uint32_t)0x00000018)        /*!< receive threshold control */
+#define ETH_DMAOPM_RXTC_64Bytes                 ((uint32_t)0x00000000)        /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_DMAOPM_RXTC_32Bytes                 ((uint32_t)0x00000008)        /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_DMAOPM_RXTC_96Bytes                 ((uint32_t)0x00000010)        /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_DMAOPM_RXTC_128Bytes                ((uint32_t)0x00000018)        /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
+
+#define ETH_DMAOPM_OPSF                         ((uint32_t)0x00000004)        /*!< operate on second frame */
+#define ETH_DMAOPM_SRXE                         ((uint32_t)0x00000002)        /*!< Start/stop receive */
+
+/************ Bit definition for Ethernet DMA Interrupt Enable Register ************/
+#define ETH_DMAIE_NISE                          ((uint32_t)0x00010000)        /*!< Normal interrupt summary enable */
+#define ETH_DMAIE_AISE                          ((uint32_t)0x00008000)        /*!< Abnormal interrupt summary enable */
+#define ETH_DMAIE_ERIE                          ((uint32_t)0x00004000)        /*!< Early receive interrupt enable */
+#define ETH_DMAIE_FBEIE                         ((uint32_t)0x00002000)        /*!< Fatal bus error interrupt enable */
+#define ETH_DMAIE_ETIE                          ((uint32_t)0x00000400)        /*!< Early transmit interrupt enable */
+#define ETH_DMAIE_RXWTIE                        ((uint32_t)0x00000200)        /*!< Receive watchdog timeout interrupt enable */
+#define ETH_DMAIE_RXPSIE                        ((uint32_t)0x00000100)        /*!< Receive process stopped interrupt enable */
+#define ETH_DMAIE_RXBUIE                        ((uint32_t)0x00000080)        /*!< Receive buffer unavailable interrupt enable */
+#define ETH_DMAIE_RXIE                          ((uint32_t)0x00000040)        /*!< Receive interrupt enable */
+#define ETH_DMAIE_TUIE                          ((uint32_t)0x00000020)        /*!< Transmit Underflow interrupt enable */
+#define ETH_DMAIE_ROIE                          ((uint32_t)0x00000010)        /*!< Receive Overflow interrupt enable */
+#define ETH_DMAIE_TXJTIE                        ((uint32_t)0x00000008)        /*!< Transmit jabber timeout interrupt enable */
+#define ETH_DMAIE_TXBUIE                        ((uint32_t)0x00000004)        /*!< Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIE_TXPSIE                        ((uint32_t)0x00000002)        /*!< Transmit process stopped interrupt enable */
+#define ETH_DMAIE_TXIE                          ((uint32_t)0x00000001)        /*!< Transmit interrupt enable */
+
+/** Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCNT_OFOC                     ((uint32_t)0x10000000)        /*!< Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCNT_MFA                      ((uint32_t)0x0FFE0000)        /*!< Number of frames missed by the application */
+#define ETH_DMAMFBOCNT_OMFC                     ((uint32_t)0x00010000)        /*!< Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCNT_MFC                      ((uint32_t)0x0000FFFF)        /*!< Number of frames missed by the controller */
+
+/** Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACTD_HTDAP                        ((uint32_t)0xFFFFFFFF)        /*!< Host transmit descriptor address pointer */
+
+/** Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACRD_HRDAP                        ((uint32_t)0xFFFFFFFF)        /*!< Host receive descriptor address pointer */
+
+/** Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACTBADDR_HTBAP                    ((uint32_t)0xFFFFFFFF)        /*!< Host transmit buffer address pointer */
+
+/** Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACRBADDR_HRBAP                    ((uint32_t)0xFFFFFFFF)        /*!< Host receive buffer address pointer */
+#endif /* AT32F407xx */
+
+/**
+  * @}
+  */
+
+/**
+ * @}
+ */
+
+#if defined (LIBRARY_VERSION) || defined (USE_STDPERIPH_DRIVER)
+#include "at32f4xx_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+
+#define BIT_SET(REG, BIT)                       ((REG) |= (BIT))
+
+#define BIT_CLEAR(REG, BIT)                     ((REG) &= ~(BIT))
+
+#define BIT_READ(REG, BIT)                      ((REG) & (BIT))
+
+#define REG_CLEAR(REG)                          ((REG) = (0x0))
+
+#define REG_WRITE(REG, VAL)                     ((REG) = (VAL))
+
+#define REG_READ(REG)                           ((REG))
+
+#define REG_CHANGE(REG, CLEARMASK, SETMASK)     REG_WRITE((REG), (((REG_READ(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F4xx_H */
+
+/**
+  * @}
+  */
+
+/**
+* @}
+*/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/inc/at32f4xx_conf.h

@@ -0,0 +1,68 @@
+/**
+ **************************************************************************
+ * File Name    : at32f4xx_conf.h
+ * Description  : at32f4xx configuration file
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F4xx_CONF_H
+#define __AT32F4xx_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
+#include "at32f4xx_acc.h"
+#include "at32f4xx_adc.h"
+#include "at32f4xx_bkp.h"
+#include "at32f4xx_can.h"
+#include "at32f4xx_comp.h"
+#include "at32f4xx_crc.h"
+#include "at32f4xx_dac.h"
+#include "at32f4xx_dbgmcu.h"
+#include "at32f4xx_dma.h"
+#include "at32f4xx_ertc.h"
+#include "at32f4xx_exti.h"
+#include "at32f4xx_flash.h"
+#include "at32f4xx_gpio.h"
+#include "at32f4xx_i2c.h"
+#include "at32f4xx_iwdg.h"
+#include "at32f4xx_pwr.h"
+#include "at32f4xx_rcc.h"
+#include "at32f4xx_rtc.h"
+#include "at32f4xx_sdio.h"
+#include "at32f4xx_spi.h"
+#include "at32f4xx_tim.h"
+#include "at32f4xx_usart.h"
+#include "at32f4xx_wwdg.h"
+#include "at32f4xx_xmc.h"
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports
+  *         the name of the source file and the source line number of the call
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __AT32F4xx_CONF_H */
+
+

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/inc/system_at32f4xx.h

@@ -0,0 +1,88 @@
+/**
+ **************************************************************************
+ * File Name    : system_at32f4xx.h
+ * Description  : CMSIS Cortex-M4 system header file.
+ * Date         : 2018-02-26
+ * Version      : V1.0.4
+ **************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup at32f4xx_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_AT32F4xx_H
+#define __SYSTEM_AT32F4xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup AT32F4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup AT32F4xx_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+/**
+  * @}
+  */
+
+/** @addtogroup AT32F4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup AT32F4xx_System_Exported_Macros
+  * @{
+  */
+#define HSE_STABLE_DELAY             (5000u)
+#define PLL_STABLE_DELAY             (500u)
+/**
+  * @}
+  */
+
+/** @addtogroup AT32F4xx_System_Exported_Functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_AT32F4xx_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/AT32F403AxC_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F403AxC_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F403xC Device with
+**                256KByte FLASH, 96KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/AT32F403AxE_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F403AxE_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F403AxE Device with
+**                512KByte FLASH, 96KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/AT32F403AxG_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F403AxG_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F403xG Device with
+**                1000KByte FLASH, 96KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1000K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/AT32F403xB_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F403xB_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F403xB Device with
+**                128KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20007FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/AT32F403xC_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F403xC_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F403xC Device with
+**                256KByte FLASH, 96KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/AT32F403xE_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F403xE_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F403xE Device with
+**                512KByte FLASH, 96KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/AT32F403xG_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F403xG_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F403xG Device with
+**                1000KByte FLASH, 96KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1000K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/AT32F407xC_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F407xC_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F403xC Device with
+**                256KByte FLASH, 96KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/AT32F407xE_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F407xE_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F407xE Device with
+**                512KByte FLASH, 96KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/AT32F407xG_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F407xG_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F403xG Device with
+**                1000KByte FLASH, 96KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1000K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/AT32F413x8_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F413x8_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F413x8 Device with
+**                64KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20007FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 64K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/AT32F413xB_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F413xB_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F413xB Device with
+**                128KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20007FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/AT32F413xC_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F413xC_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F413xC Device with
+**                256KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20007FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/AT32F415x8_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F415x8_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F415x8 Device with
+**                64KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20007FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 64K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/AT32F415xB_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F415xB_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F415xB Device with
+**                128KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20007FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/AT32F415xC_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : AT32F415xC_FLASH.ld
+**
+**  Abstract    : Linker script for AT32F415xC Device with
+**                256KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek AT32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20007FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/linker/TS32F401xB_FLASH.ld

@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+**  File        : TS32F401xB_FLASH.ld
+**
+**  Abstract    : Linker script for TS32F401xB Device with
+**                128KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : Artery Tek TS32
+**
+**  Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20007FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403acct7.s

@@ -0,0 +1,464 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403acct7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                               */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  0                                   /* Reserved                                */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403accu7.s

@@ -0,0 +1,464 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403accu7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                               */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  0                                   /* Reserved                                */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403acet7.s

@@ -0,0 +1,464 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403acet7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                               */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  0                                   /* Reserved                                */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403aceu7.s

@@ -0,0 +1,464 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403aceu7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                               */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  0                                   /* Reserved                                */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403acgt7.s

@@ -0,0 +1,464 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403acgt7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                               */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  0                                   /* Reserved                                */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403acgu7.s

@@ -0,0 +1,464 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403acgu7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                               */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  0                                   /* Reserved                                */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403arct7.s

@@ -0,0 +1,473 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403arct7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  XMC_IRQHandler                      /* XMC                                     */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  UART8_IRQHandler                    /* UART8                                   */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      XMC_IRQHandler
+   .thumb_set XMC_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403aret7.s

@@ -0,0 +1,473 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403aret7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  XMC_IRQHandler                      /* XMC                                     */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  UART8_IRQHandler                    /* UART8                                   */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      XMC_IRQHandler
+   .thumb_set XMC_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403argt7.s

@@ -0,0 +1,473 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403argt7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  XMC_IRQHandler                      /* XMC                                     */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  UART8_IRQHandler                    /* UART8                                   */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      XMC_IRQHandler
+   .thumb_set XMC_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403avct7.s

@@ -0,0 +1,473 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403avct7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  XMC_IRQHandler                      /* XMC                                     */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  UART8_IRQHandler                    /* UART8                                   */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      XMC_IRQHandler
+   .thumb_set XMC_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403avet7.s

@@ -0,0 +1,473 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403avet7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  XMC_IRQHandler                      /* XMC                                     */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  UART8_IRQHandler                    /* UART8                                   */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      XMC_IRQHandler
+   .thumb_set XMC_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403avgt7.s

@@ -0,0 +1,473 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403avgt7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  XMC_IRQHandler                      /* XMC                                     */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  UART8_IRQHandler                    /* UART8                                   */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      XMC_IRQHandler
+   .thumb_set XMC_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403cx_hd.s

@@ -0,0 +1,409 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403cx_hd.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-08-15
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_HALL_TMR11_IRQHandler      /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_IRQHandler                     /* SPI2                                    */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_HALL_TMR14_IRQHandler      /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_IRQHandler                     /* SPI3                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_HALL_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_HALL_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403cx_md.s

@@ -0,0 +1,409 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403cx_md.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-08-15
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_HALL_TMR11_IRQHandler      /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_IRQHandler                     /* SPI2                                    */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_HALL_TMR14_IRQHandler      /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_IRQHandler                     /* SPI3                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_HALL_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_HALL_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403cx_xl.s

@@ -0,0 +1,409 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403cx_xl.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-08-15
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_HALL_TMR11_IRQHandler      /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_IRQHandler                     /* SPI2                                    */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_HALL_TMR14_IRQHandler      /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_IRQHandler                     /* SPI3                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_HALL_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_HALL_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403rx_hd.s

@@ -0,0 +1,418 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403rx_hd.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-08-15
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_HALL_TMR11_IRQHandler      /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_IRQHandler                     /* SPI2                                    */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_HALL_TMR14_IRQHandler      /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  0                                   /* Reserved                                */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_IRQHandler                     /* SPI3                                    */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_HALL_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_HALL_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403rx_xl.s

@@ -0,0 +1,418 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403rx_xl.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-08-15
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_HALL_TMR11_IRQHandler      /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_IRQHandler                     /* SPI2                                    */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_HALL_TMR14_IRQHandler      /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  0                                   /* Reserved                                */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_IRQHandler                     /* SPI3                                    */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_HALL_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_HALL_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403vx_hd.s

@@ -0,0 +1,425 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403vx_hd.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-08-15
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_HALL_TMR11_IRQHandler      /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_IRQHandler                     /* SPI2                                    */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_HALL_TMR14_IRQHandler      /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  XMC_IRQHandler                      /* XMC                                     */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_IRQHandler                     /* SPI3                                    */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_HALL_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_HALL_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      XMC_IRQHandler
+   .thumb_set XMC_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403vx_xl.s

@@ -0,0 +1,425 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403vx_xl.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-08-15
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_HALL_TMR11_IRQHandler      /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_IRQHandler                     /* SPI2                                    */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_HALL_TMR14_IRQHandler      /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  XMC_IRQHandler                      /* XMC                                     */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_IRQHandler                     /* SPI3                                    */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_HALL_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_HALL_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      XMC_IRQHandler
+   .thumb_set XMC_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403zx_hd.s

@@ -0,0 +1,441 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403zx_hd.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-08-15
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_HALL_TMR11_IRQHandler      /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_IRQHandler                     /* SPI2                                    */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_HALL_TMR14_IRQHandler      /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  XMC_IRQHandler                      /* XMC                                     */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_IRQHandler                     /* SPI3                                    */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  TMR15_BRK_IRQHandler                /* TMR15 Break                             */
+  .word  TMR15_OV_IRQHandler                 /* TMR15 Update                            */
+  .word  TMR15_TRG_HALL_IRQHandler           /* TMR15 Trigger and Commutation           */
+  .word  TMR15_CC_IRQHandler                 /* TMR15 Capture Compare                   */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_HALL_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_HALL_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      XMC_IRQHandler
+   .thumb_set XMC_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      TMR15_BRK_IRQHandler
+   .thumb_set TMR15_BRK_IRQHandler,Default_Handler
+
+   .weak      TMR15_OV_IRQHandler
+   .thumb_set TMR15_OV_IRQHandler,Default_Handler
+
+   .weak      TMR15_TRG_HALL_IRQHandler
+   .thumb_set TMR15_TRG_HALL_IRQHandler,Default_Handler
+
+   .weak      TMR15_CC_IRQHandler
+   .thumb_set TMR15_CC_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f403zx_xl.s

@@ -0,0 +1,441 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f403zx_xl.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-08-15
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_HALL_TMR11_IRQHandler      /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_IRQHandler                     /* SPI2                                    */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_HALL_TMR14_IRQHandler      /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  XMC_IRQHandler                      /* XMC                                     */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_IRQHandler                     /* SPI3                                    */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  TMR15_BRK_IRQHandler                /* TMR15 Break                             */
+  .word  TMR15_OV_IRQHandler                 /* TMR15 Update                            */
+  .word  TMR15_TRG_HALL_IRQHandler           /* TMR15 Trigger and Commutation           */
+  .word  TMR15_CC_IRQHandler                 /* TMR15 Capture Compare                   */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_HALL_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_HALL_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      XMC_IRQHandler
+   .thumb_set XMC_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      TMR15_BRK_IRQHandler
+   .thumb_set TMR15_BRK_IRQHandler,Default_Handler
+
+   .weak      TMR15_OV_IRQHandler
+   .thumb_set TMR15_OV_IRQHandler,Default_Handler
+
+   .weak      TMR15_TRG_HALL_IRQHandler
+   .thumb_set TMR15_TRG_HALL_IRQHandler,Default_Handler
+
+   .weak      TMR15_CC_IRQHandler
+   .thumb_set TMR15_CC_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f407rct7.s

@@ -0,0 +1,481 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f407rct7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  XMC_IRQHandler                      /* XMC                                     */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  UART8_IRQHandler                    /* UART8                                   */
+  .word  ETH_IRQHandler                      /* ETH                                     */
+  .word  ETH_WKUP_IRQHandler                 /* ETH Wakeup                              */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      XMC_IRQHandler
+   .thumb_set XMC_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      ETH_IRQHandler
+   .thumb_set ETH_IRQHandler,Default_Handler
+
+   .weak      ETH_WKUP_IRQHandler
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f407ret7.s

@@ -0,0 +1,481 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f407ret7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  XMC_IRQHandler                      /* XMC                                     */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  UART8_IRQHandler                    /* UART8                                   */
+  .word  ETH_IRQHandler                      /* ETH                                     */
+  .word  ETH_WKUP_IRQHandler                 /* ETH Wakeup                              */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      XMC_IRQHandler
+   .thumb_set XMC_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      ETH_IRQHandler
+   .thumb_set ETH_IRQHandler,Default_Handler
+
+   .weak      ETH_WKUP_IRQHandler
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f407rgt7.s

@@ -0,0 +1,481 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f407rgt7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  XMC_IRQHandler                      /* XMC                                     */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  UART8_IRQHandler                    /* UART8                                   */
+  .word  ETH_IRQHandler                      /* ETH                                     */
+  .word  ETH_WKUP_IRQHandler                 /* ETH Wakeup                              */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      XMC_IRQHandler
+   .thumb_set XMC_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      ETH_IRQHandler
+   .thumb_set ETH_IRQHandler,Default_Handler
+
+   .weak      ETH_WKUP_IRQHandler
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f407vct7.s

@@ -0,0 +1,481 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f407vct7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  XMC_IRQHandler                      /* XMC                                     */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  UART8_IRQHandler                    /* UART8                                   */
+  .word  ETH_IRQHandler                      /* ETH                                     */
+  .word  ETH_WKUP_IRQHandler                 /* ETH Wakeup                              */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      XMC_IRQHandler
+   .thumb_set XMC_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      ETH_IRQHandler
+   .thumb_set ETH_IRQHandler,Default_Handler
+
+   .weak      ETH_WKUP_IRQHandler
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f407vet7.s

@@ -0,0 +1,481 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f407vet7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  XMC_IRQHandler                      /* XMC                                     */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  UART8_IRQHandler                    /* UART8                                   */
+  .word  ETH_IRQHandler                      /* ETH                                     */
+  .word  ETH_WKUP_IRQHandler                 /* ETH Wakeup                              */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      XMC_IRQHandler
+   .thumb_set XMC_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      ETH_IRQHandler
+   .thumb_set ETH_IRQHandler,Default_Handler
+
+   .weak      ETH_WKUP_IRQHandler
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f407vgt7.s

@@ -0,0 +1,481 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f407vgt7.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-10-12
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_COM_TMR11_IRQHandler       /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_I2S2EXT_IRQHandler             /* SPI2 & I2S2EXT                          */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_COM_TMR14_IRQHandler       /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  ADC3_IRQHandler                     /* ADC3                                    */
+  .word  XMC_IRQHandler                      /* XMC                                     */
+  .word  SDIO1_IRQHandler                    /* SDIO1                                   */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  SPI3_I2S3EXT_IRQHandler             /* SPI3 & I2S3EXT                          */
+  .word  UART4_IRQHandler                    /* UART4                                   */
+  .word  UART5_IRQHandler                    /* UART5                                   */
+  .word  TMR6_GLOBAL_IRQHandler              /* TMR6                                    */
+  .word  TMR7_GLOBAL_IRQHandler              /* TMR7                                    */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  SDIO2_IRQHandler                    /* SDIO2                                   */
+  .word  I2C3_EV_IRQHandler                  /* I2C3 Event                              */
+  .word  I2C3_ER_IRQHandler                  /* I2C3 Error                              */
+  .word  SPI4_IRQHandler                     /* SPI4                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+  .word  USART6_IRQHandler                   /* USART6                                  */
+  .word  UART7_IRQHandler                    /* UART7                                   */
+  .word  UART8_IRQHandler                    /* UART8                                   */
+  .word  ETH_IRQHandler                      /* ETH                                     */
+  .word  ETH_WKUP_IRQHandler                 /* ETH Wakeup                              */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_COM_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_I2S2EXT_IRQHandler
+   .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_COM_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      ADC3_IRQHandler
+   .thumb_set ADC3_IRQHandler,Default_Handler
+
+   .weak      XMC_IRQHandler
+   .thumb_set XMC_IRQHandler,Default_Handler
+
+   .weak      SDIO1_IRQHandler
+   .thumb_set SDIO1_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      SPI3_I2S3EXT_IRQHandler
+   .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TMR6_GLOBAL_IRQHandler
+   .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR7_GLOBAL_IRQHandler
+   .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      SDIO2_IRQHandler
+   .thumb_set SDIO2_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler 
+   .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler 
+   .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      ETH_IRQHandler
+   .thumb_set ETH_IRQHandler,Default_Handler
+
+   .weak      ETH_WKUP_IRQHandler
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/

bsp/at32/Libraries/AT32_Std_Driver/CMSIS/AT32/AT32F4xx/src/gcc/startup_at32f413cx_hd.s

@@ -0,0 +1,428 @@
+/**
+  ******************************************************************************
+  * @file      startup_at32f413cx_hd.s
+  * @author    Artery Tek
+  * @version   V1.0.0
+  * @date      2019-08-15
+  * @brief     AT32F4xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM to
+  *                  be used as data memory (optional, to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word  WWDG_IRQHandler                     /* Window Watchdog                         */
+  .word  PVD_IRQHandler                      /* PVD through EXTI Line detect            */
+  .word  TAMPER_IRQHandler                   /* Tamper                                  */
+  .word  RTC_IRQHandler                      /* RTC                                     */
+  .word  FLASH_IRQHandler                    /* Flash                                   */
+  .word  RCC_IRQHandler                      /* RCC                                     */
+  .word  EXTI0_IRQHandler                    /* EXTI Line 0                             */
+  .word  EXTI1_IRQHandler                    /* EXTI Line 1                             */
+  .word  EXTI2_IRQHandler                    /* EXTI Line 2                             */
+  .word  EXTI3_IRQHandler                    /* EXTI Line 3                             */
+  .word  EXTI4_IRQHandler                    /* EXTI Line 4                             */
+  .word  DMA1_Channel1_IRQHandler            /* DMA1 Channel 1                          */
+  .word  DMA1_Channel2_IRQHandler            /* DMA1 Channel 2                          */
+  .word  DMA1_Channel3_IRQHandler            /* DMA1 Channel 3                          */
+  .word  DMA1_Channel4_IRQHandler            /* DMA1 Channel 4                          */
+  .word  DMA1_Channel5_IRQHandler            /* DMA1 Channel 5                          */
+  .word  DMA1_Channel6_IRQHandler            /* DMA1 Channel 6                          */
+  .word  DMA1_Channel7_IRQHandler            /* DMA1 Channel 7                          */
+  .word  ADC1_2_IRQHandler                   /* ADC1 & ADC2                             */
+  .word  USB_HP_CAN1_TX_IRQHandler           /* USB High Priority or CAN1 TX            */
+  .word  USB_LP_CAN1_RX0_IRQHandler          /* USB Low  Priority or CAN1 RX0           */
+  .word  CAN1_RX1_IRQHandler                 /* CAN1 RX1                                */
+  .word  CAN1_SCE_IRQHandler                 /* CAN1 SCE                                */
+  .word  EXTI9_5_IRQHandler                  /* EXTI Line [9:5]                         */
+  .word  TMR1_BRK_TMR9_IRQHandler            /* TMR1 Break and TMR9                     */
+  .word  TMR1_OV_TMR10_IRQHandler            /* TMR1 Update and TMR10                   */
+  .word  TMR1_TRG_HALL_TMR11_IRQHandler      /* TMR1 Trigger and Commutation and TMR11  */
+  .word  TMR1_CC_IRQHandler                  /* TMR1 Capture Compare                    */
+  .word  TMR2_GLOBAL_IRQHandler              /* TMR2                                    */
+  .word  TMR3_GLOBAL_IRQHandler              /* TMR3                                    */
+  .word  TMR4_GLOBAL_IRQHandler              /* TMR4                                    */
+  .word  I2C1_EV_IRQHandler                  /* I2C1 Event                              */
+  .word  I2C1_ER_IRQHandler                  /* I2C1 Error                              */
+  .word  I2C2_EV_IRQHandler                  /* I2C2 Event                              */
+  .word  I2C2_ER_IRQHandler                  /* I2C2 Error                              */
+  .word  SPI1_IRQHandler                     /* SPI1                                    */
+  .word  SPI2_IRQHandler                     /* SPI2                                    */
+  .word  USART1_IRQHandler                   /* USART1                                  */
+  .word  USART2_IRQHandler                   /* USART2                                  */
+  .word  USART3_IRQHandler                   /* USART3                                  */
+  .word  EXTI15_10_IRQHandler                /* EXTI Line [15:10]                       */
+  .word  RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line             */
+  .word  USBWakeUp_IRQHandler                /* USB Wakeup from suspend                 */
+  .word  TMR8_BRK_TMR12_IRQHandler           /* TMR8 Break and TMR12                    */
+  .word  TMR8_OV_TMR13_IRQHandler            /* TMR8 Update and TMR13                   */
+  .word  TMR8_TRG_HALL_TMR14_IRQHandler      /* TMR8 Trigger and Commutation and TMR14  */
+  .word  TMR8_CC_IRQHandler                  /* TMR8 Capture Compare                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  SDIO_IRQHandler                     /* SDIO                                    */
+  .word  TMR5_GLOBAL_IRQHandler              /* TMR5                                    */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  DMA2_Channel1_IRQHandler            /* DMA2 Channel1                           */
+  .word  DMA2_Channel2_IRQHandler            /* DMA2 Channel2                           */
+  .word  DMA2_Channel3_IRQHandler            /* DMA2 Channel3                           */
+  .word  DMA2_Channel4_5_IRQHandler          /* DMA2 Channel4 & Channel5                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  0                                   /* Reserved                                */
+  .word  CAN2_TX_IRQHandler                  /* CAN2 TX                                 */
+  .word  CAN2_RX0_IRQHandler                 /* CAN2 RX0                                */
+  .word  CAN2_RX1_IRQHandler                 /* CAN2 RX1                                */
+  .word  CAN2_SCE_IRQHandler                 /* CAN2 SCE                                */
+  .word  ACC_IRQHandler                      /* ACC                                     */
+  .word  USB_HP_IRQHandler                   /* USB_HP                                  */
+  .word  USB_LP_IRQHandler                   /* USB_LP                                  */
+  .word  DMA2_Channel6_7_IRQHandler          /* DMA2 Channel6 & Channel7                */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMPER_IRQHandler
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_IRQHandler
+   .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel3_IRQHandler
+   .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_IRQHandler
+   .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 
+
+   .weak      DMA1_Channel5_IRQHandler
+   .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel6_IRQHandler
+   .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel7_IRQHandler
+   .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+   .weak      ADC1_2_IRQHandler
+   .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+   .weak      USB_HP_CAN1_TX_IRQHandler
+   .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      USB_LP_CAN1_RX0_IRQHandler
+   .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TMR1_BRK_TMR9_IRQHandler
+   .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+   .weak      TMR1_OV_TMR10_IRQHandler
+   .thumb_set TMR1_OV_TMR10_IRQHandler,Default_Handler
+
+   .weak      TMR1_TRG_HALL_TMR11_IRQHandler
+   .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
+
+   .weak      TMR1_CC_IRQHandler
+   .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+   .weak      TMR2_GLOBAL_IRQHandler
+   .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR3_GLOBAL_IRQHandler
+   .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      TMR4_GLOBAL_IRQHandler
+   .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTCAlarm_IRQHandler
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+   .weak      USBWakeUp_IRQHandler
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+   .weak      TMR8_BRK_TMR12_IRQHandler
+   .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+   .weak      TMR8_OV_TMR13_IRQHandler
+   .thumb_set TMR8_OV_TMR13_IRQHandler,Default_Handler
+
+   .weak      TMR8_TRG_HALL_TMR14_IRQHandler
+   .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler
+
+   .weak      TMR8_CC_IRQHandler
+   .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+   .weak      SDIO_IRQHandler
+   .thumb_set SDIO_IRQHandler,Default_Handler
+
+   .weak      TMR5_GLOBAL_IRQHandler
+   .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel1_IRQHandler
+   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel2_IRQHandler
+   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel3_IRQHandler
+   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel4_5_IRQHandler
+   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler
+   .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler
+   .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      ACC_IRQHandler
+   .thumb_set ACC_IRQHandler,Default_Handler
+
+   .weak      USB_HP_IRQHandler
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+
+   .weak      USB_LP_IRQHandler
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      DMA2_Channel6_7_IRQHandler
+   .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT Artery Tek *****END OF FILE****/