[bsp][renesas] add EK-RA2E2 other device drivers support (#10695)

* [bsp][renesas]add EK-RA2E2 sci_uart support

* [bsp][renesas] add EK-RA2E2 (i2c/spi/adc/pwm/flash/gpio interrupt) support

* [bsp][renesas] comment drv_flash.c and format drv_i2c.c

bsp/renesas/libraries/HAL_Drivers/drivers/config/drv_config.h

@@ -87,6 +87,15 @@ extern "C"
 
 #ifdef SOC_SERIES_R7FA2E2
 #include "ra2e2/uart_config.h"
+
+#ifdef BSP_USING_PWM
+#include "ra2e2/pwm_config.h"
+#endif
+
+#ifdef BSP_USING_ADC
+#include "ra2e2/adc_config.h"
+#endif
+
 #endif /* SOC_SERIES_R7FA2E2 */
 
 #ifdef SOC_SERIES_R7FA2L1

bsp/renesas/libraries/HAL_Drivers/drivers/config/ra2e2/adc_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-17     CYFS         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_ADC0)
+
+struct rt_adc_dev
+{
+    struct rt_adc_ops ops;
+    struct rt_adc_device adc_device;
+};
+
+struct ra_adc_map
+{
+    const char *device_name;
+    const adc_cfg_t *g_cfg;
+    const adc_ctrl_t *g_ctrl;
+    const adc_channel_cfg_t   *g_channel_cfg;
+};
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+

bsp/renesas/libraries/HAL_Drivers/drivers/config/ra2e2/pwm_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2025-08-17     CYFS              first version
+ */
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+#include <drv_config.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum
+{
+#ifdef BSP_USING_PWM4
+    BSP_PWM4_INDEX,
+#endif
+#ifdef BSP_USING_PWM5
+    BSP_PWM5_INDEX,
+#endif
+#ifdef BSP_USING_PWM6
+    BSP_PWM6_INDEX,
+#endif
+#ifdef BSP_USING_PWM7
+    BSP_PWM7_INDEX,
+#endif
+#ifdef BSP_USING_PWM8
+    BSP_PWM8_INDEX,
+#endif
+#ifdef BSP_USING_PWM9
+    BSP_PWM9_INDEX,
+#endif
+    BSP_PWMS_NUM
+};
+
+#define PWM_DRV_INITIALIZER(num)        \
+    {                                   \
+        .name = "pwm"#num ,             \
+        .g_cfg = &g_timer##num##_cfg,   \
+        .g_ctrl = &g_timer##num##_ctrl, \
+        .g_timer = &g_timer##num,       \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/renesas/libraries/HAL_Drivers/drivers/drv_flash.c

@@ -228,7 +228,11 @@ bool calculate_block_num(int no, size_t addr, size_t size, void *erase_addr, voi
     level = rt_hw_interrupt_disable();
     R_FLASH_Reset(&g_flash_ctrl);
 
+#if BSP_FEATURE_FLASH_HP_VERSION
     fal_block_iter(&_onchip_flash_hp0, &calculate_block_num, (void *)addr, (void *)size, &block_num);
+#else
+    fal_block_iter(&_onchip_flash_lp, &calculate_block_num, (void *)addr, (void *)size, &block_num);
+#endif
 
     /* Erase Block */
 #if BSP_FEATURE_FLASH_HP_VERSION
@@ -337,6 +341,16 @@ static int fal_flash_lp_erase(long offset, size_t size)
     return _flash_lp_erase(_onchip_flash_lp.addr + offset, size);
 }
 
+/*
+ * This callback is intentionally left empty.
+ * No action is required on flash events in this application.
+ * If event handling is needed, implement it here.
+ */
+void flash_callback(flash_callback_args_t * p_args)
+{
+
+}
+
 #endif
 
 #endif

bsp/renesas/libraries/HAL_Drivers/drivers/drv_gpio.c

@@ -26,7 +26,7 @@
 
 static rt_base_t ra_pin_get_irqx(rt_uint32_t pin)
 {
-    PIN2IRQX_TABLE(pin)
+    PIN2IRQX_TABLE(pin);
 }
 
 static struct rt_pin_irq_hdr pin_irq_hdr_tab[RA_IRQ_MAX] = {0};

bsp/renesas/libraries/HAL_Drivers/drivers/drv_i2c.c

@@ -23,11 +23,11 @@
 #include <hal_data.h>
 
 #ifndef BIT
-    #define BIT(idx)        (1ul << (idx))
+#define BIT(idx)        (1ul << (idx))
 #endif
 
 #ifndef BITS
-    #define BITS(b,e)       ((((uint32_t)-1)<<(b))&(((uint32_t)-1)>>(31-(e))))
+#define BITS(b,e)       ((((uint32_t)-1)<<(b))&(((uint32_t)-1)>>(31-(e))))
 #endif
 
 #define RA_SCI_EVENT_ABORTED        BIT(0)
@@ -36,6 +36,14 @@
 #define RA_SCI_EVENT_ERROR          BIT(3)
 #define RA_SCI_EVENT_ALL            BITS(0,3)
 
+#ifdef SOC_SERIES_R7FA2E2
+#define R_IIC_MASTER_Open       R_IIC_B_MASTER_Open
+#define R_IIC_MASTER_Write      R_IIC_B_MASTER_Write
+#define R_IIC_MASTER_Read       R_IIC_B_MASTER_Read
+#define R_IIC_MASTER_SlaveAddressSet    R_IIC_B_MASTER_SlaveAddressSet
+#define R_IIC_MASTER_CallbackSet        R_IIC_B_MASTER_CallbackSet
+#endif
+
 struct ra_i2c_handle
 {
     struct rt_i2c_bus_device bus;

bsp/renesas/ra2e2-ek/.config

@@ -107,7 +107,7 @@ CONFIG_SOC_R7FA2E2A7=y
 # end of rt_strnlen options
 # end of klibc options
 
-CONFIG_RT_NAME_MAX=8
+CONFIG_RT_NAME_MAX=16
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
 # CONFIG_RT_USING_NANO is not set
 # CONFIG_RT_USING_SMART is not set
@@ -146,7 +146,7 @@ CONFIG_RT_DEBUGING_CONTEXT=y
 #
 CONFIG_RT_USING_SEMAPHORE=y
 CONFIG_RT_USING_MUTEX=y
-# CONFIG_RT_USING_EVENT is not set
+CONFIG_RT_USING_EVENT=y
 # CONFIG_RT_USING_MAILBOX is not set
 # CONFIG_RT_USING_MESSAGEQUEUE is not set
 # CONFIG_RT_USING_SIGNALS is not set
@@ -1286,6 +1286,10 @@ CONFIG_BSP_USING_UART9=y
 # CONFIG_BSP_UART9_TX_USING_DMA is not set
 CONFIG_BSP_UART9_RX_BUFSIZE=256
 CONFIG_BSP_UART9_TX_BUFSIZE=0
+# CONFIG_BSP_USING_HW_I2C is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_ADC is not set
 # end of On-chip Peripheral Drivers
 
 #

bsp/renesas/ra2e2-ek/README.md

@@ -35,7 +35,7 @@
 | GPIO               | 支持               |                |
 | IIC                | 支持               | 软件           |
 | WDT                | 支持               |                |
-| RTC                | 支持               |                |
+| RTC                | 不支持              |                |
 | ADC                | 支持               |                |
 | SPI                | 支持               |                |
 | FLASH              | 支持               |                |
@@ -172,4 +172,4 @@ RASC 生成的`bsp_linker_info.h`，要么直接删掉，要么根据使用的
 
 ## 贡献代码
 
-如果您对 CPK-RA6M4 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。
+如果您对 EK-RA2E2 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。

bsp/renesas/ra2e2-ek/SConstruct

@@ -44,6 +44,18 @@ Export('SDK_LIB')
 
 rtconfig.BSP_LIBRARY_TYPE = None
 
+def startup_check():
+    import subprocess
+    startup_check_path = os.getcwd() + "/../tools/startup_check.py"
+
+    if os.path.exists(startup_check_path):
+        try:
+            subprocess.call(["python", startup_check_path])
+        except:
+            subprocess.call(["python3", startup_check_path])
+
+RegisterPreBuildingAction(startup_check)
+
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 

bsp/renesas/ra2e2-ek/board/Kconfig

@@ -43,6 +43,67 @@ menu "Hardware Drivers Config"
                     endif
             endif
 
+        menuconfig BSP_USING_HW_I2C
+            bool "Enable hardware I2C BUS"
+            default n
+            select RT_USING_I2C
+            if BSP_USING_HW_I2C
+                config BSP_USING_HW_I2C0
+                    bool "Enable Hardware I2C0 BUS"
+                    default n
+            endif
+
+        menuconfig BSP_USING_SPI
+            bool "Enable hardware SPI BUS"
+            default n
+            select RT_USING_SPI
+            if BSP_USING_SPI
+                config BSP_USING_SPI0
+                    bool "Enable Hardware SPI0 BUS"
+                    default n
+            endif
+
+        menuconfig BSP_USING_PWM
+            bool "Enable PWM"
+            default n
+            select RT_USING_PWM
+            if BSP_USING_PWM
+                config BSP_USING_PWM4
+                    bool "Enable GPT4 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM5
+                    bool "Enable GPT5 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM6
+                    bool "Enable GPT6 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM7
+                    bool "Enable GPT7 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM8
+                    bool "Enable GPT8 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM9
+                    bool "Enable GPT9 (16-Bits) output PWM"
+                    default n
+
+            endif
+        
+        menuconfig BSP_USING_ADC
+            bool "Enable ADC"
+            default n
+            select RT_USING_ADC
+            if BSP_USING_ADC
+                config BSP_USING_ADC0
+                    bool "Enable ADC0"
+                    default n
+            endif
+
     endmenu
 
     menu "Board extended module Drivers"

bsp/renesas/ra2e2-ek/board/ports/fal_cfg.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-20     Sherman      the first version
+ */
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include "hal_data.h"
+#include "rtconfig.h"
+
+extern const struct fal_flash_dev _onchip_flash_lp;
+
+#define FLASH_START_ADDRESS 0x00000000
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE             \
+{                                       \
+    &_onchip_flash_lp,                  \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/** partition table, The chip flash partition is defined in "\script\memory_regions.ld".
+ * The partition start at 0x440 instead of 0 because OFS0, OFS1 and security MPU registers exist.
+ * More details can be found in the RA2E2 Group User Manual: Hardware Figure 6.1.
+ *
+ * The table is used to define flash partition by struct fal_partition in fal_def.h */
+#define FAL_PART_TABLE                                                              \
+{                                                                                   \
+    {FAL_PART_MAGIC_WROD, "app", "onchip_flash_lp", 0x440, 0x0000fbc0, 0},          \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* _FAL_CFG_H_ */
+

bsp/renesas/ra2e2-ek/configuration.xml

@@ -240,9 +240,9 @@
     <symbolicName propertyId="p401.symbolic_name" value="IIC_SDA0"/>
     <symbolicName propertyId="p914.symbolic_name" value="LED2_GREEN"/>
     <pincfg active="true" name="EK-RA2E2.pincfg" selected="true" symbol="g_bsp_pin_cfg">
-      <configSetting altId="i3c0.mode.enabled.free" configurationId="i3c0.mode"/>
-      <configSetting altId="i3c0.scl0.p400" configurationId="i3c0.scl0"/>
-      <configSetting altId="i3c0.sda0.p401" configurationId="i3c0.sda0"/>
+      <configSetting altId="gpt6.mode.gtiocaorgtiocb.free" configurationId="gpt6.mode"/>
+      <configSetting altId="gpt7.mode.gtiocaorgtiocb.free" configurationId="gpt7.mode"/>
+      <configSetting altId="gpt9.mode.gtiocaorgtiocb.free" configurationId="gpt9.mode"/>
       <configSetting altId="jtag_fslash_swd.mode.swd.free" configurationId="jtag_fslash_swd.mode"/>
       <configSetting altId="jtag_fslash_swd.swclk.p300" configurationId="jtag_fslash_swd.swclk"/>
       <configSetting altId="jtag_fslash_swd.swdio.p108" configurationId="jtag_fslash_swd.swdio"/>
@@ -264,10 +264,6 @@
       <configSetting altId="p205.gpio_mode.gpio_mode_in" configurationId="p205.gpio_mode"/>
       <configSetting altId="p300.jtag_fslash_swd.swclk" configurationId="p300"/>
       <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
-      <configSetting altId="p400.i3c0.scl0" configurationId="p400"/>
-      <configSetting altId="p400.gpio_mode.gpio_mode_peripheral" configurationId="p400.gpio_mode"/>
-      <configSetting altId="p401.i3c0.sda0" configurationId="p401"/>
-      <configSetting altId="p401.gpio_mode.gpio_mode_peripheral" configurationId="p401.gpio_mode"/>
       <configSetting altId="p914.output.low" configurationId="p914"/>
       <configSetting altId="p914.gpio_mode.gpio_mode_out.low" configurationId="p914.gpio_mode"/>
       <configSetting altId="sci9.mode.asynchronousuart.free" configurationId="sci9.mode"/>

bsp/renesas/ra2e2-ek/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c

@@ -50,11 +50,15 @@ void Reset_Handler (void)
     SystemInit();
 
     /* Call user application. */
-#ifdef __ARMCC_VERSION
-    main();
-#elif defined(__GNUC__)
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
     extern int entry(void);
     entry();
+#elif defined(__ICCARM__)
+    extern void __low_level_init(void);
+    __low_level_init();
+#else
+    /* Jump to main. */
+    main();
 #endif
 
     while (1)

bsp/renesas/ra2e2-ek/ra_gen/pin_data.c

@@ -36,14 +36,6 @@ const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
         .pin = BSP_IO_PORT_03_PIN_00,
         .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
     },
-    {
-        .pin = BSP_IO_PORT_04_PIN_00,
-        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
-    },
-    {
-        .pin = BSP_IO_PORT_04_PIN_01,
-        .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
-    },
     {
         .pin = BSP_IO_PORT_09_PIN_14,
         .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)

bsp/renesas/ra2e2-ek/rtconfig.h

@@ -63,7 +63,7 @@
 
 /* end of rt_strnlen options */
 /* end of klibc options */
-#define RT_NAME_MAX 8
+#define RT_NAME_MAX 16
 #define RT_CPUS_NR 1
 #define RT_ALIGN_SIZE 8
 #define RT_THREAD_PRIORITY_32
@@ -84,6 +84,7 @@
 
 #define RT_USING_SEMAPHORE
 #define RT_USING_MUTEX
+#define RT_USING_EVENT
 /* end of Inter-Thread communication */
 
 /* Memory Management */