[bsp]1.update es32f0334 libraries.

     2.adapt to the new power management interface.
     3.move es32f0334 folder to essemi folder.

bsp/es32f0334/drivers/drv_pm.c

@@ -1,74 +0,0 @@
-/*
- * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author        Notes
- * 2019-04-08     wangyq        the first version
- * 2019-05-06     Zero-Free     adapt to the new power management interface
- */
-
-#include <rthw.h>
-#include <rtdevice.h>
-#include "board.h"
-#include "drv_pm.h"
-#include <ald_pmu.h>
-
-#ifdef RT_USING_PM
-
-static void _drv_pm_enter(struct rt_pm *pm, uint8_t mode)
-{
-    switch (mode)
-    {
-    case PM_SLEEP_MODE_NONE:
-        break;
-
-    case PM_SLEEP_MODE_IDLE:
-        __WFI();
-        break;
-
-    case PM_SLEEP_MODE_LIGHT:
-        break;
-
-    case PM_SLEEP_MODE_DEEP:
-        pmu_stop2_enter();
-        break;
-
-    case PM_SLEEP_MODE_STANDBY:
-        pmu_standby_enter(PMU_STANDBY_PORT_NONE);
-        break;
-
-    case PM_SLEEP_MODE_SHUTDOWN:
-        break;
-
-    default:
-        RT_ASSERT(0);
-        break;
-    }
-}
-
-static int drv_hw_pm_init(void)
-{
-    static const struct rt_pm_ops _ops =
-    {
-        _drv_pm_enter,
-        RT_NULL,
-        RT_NULL,
-        RT_NULL,
-        RT_NULL
-    };
-
-    rt_uint8_t timer_mask = 0;
-
-    /* initialize timer mask(no need tickless) */
-    // timer_mask = 1UL << PM_SLEEP_MODE_DEEP;
-
-    /* initialize system pm module */
-    rt_system_pm_init(&_ops, timer_mask, RT_NULL);
-
-    return 0;
-}
-INIT_BOARD_EXPORT(drv_hw_pm_init);
-
-#endif

bsp/es32f0334/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf

@@ -1,793 +0,0 @@
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-\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid5861575 TO YOU ON CONDITION THAT YOU ACCEPT ALL OF THE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  TERMS IN THIS LICENCE. BY CLICKING "I AGREE", OR BY INSTALLING OR OTHERWISE USING OR COPYING THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
-YOU INDICATE THAT YOU AGREE TO BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE YOU TO USE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 OF }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  AND YOU MAY NOT INSTALL, USE OR COPY THE }{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 .
-\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93
-CMSIS Deliverables\'94 means the following components: (i) CMSIS-CORE; (ii) CMSIS-DRIVER; (iii) CMSIS-DSP; (iv) CMSIS-PACK; (v) CMSIS-RTOS API; and (vi) CMSIS-SVD . 
-\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx0\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93CMSIS-CORE
-\'94 means the specification defining the application programming interface, naming and coding conventions for the Cortex-M processor cores.
-\par \'94}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 CMSIS-DRIVER}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'94}{\rtlch\fcs1 \af0 \ltrch\fcs0 
-\insrsid11754636 \hich\af37\dbch\af37\loch\f37  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 means the specification defining }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
-\hich\af1\dbch\af37\loch\f1 a generic}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 p}{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 eripheral }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 d}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 river application programming interface, naming and coding conventions}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 .
-\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  \'93CMSIS-DSP\'94
- means the digital signal process (DSP) library specification defining the application programming interface of a DSP library implementation}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15023647 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
-\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx0\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93}{
-\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13240697 \hich\af1\dbch\af37\loch\f1 CMSIS-PACK}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'94}{\rtlch\fcs1 \af0 \ltrch\fcs0 
-\insrsid11754636\charrsid13240697 \hich\af37\dbch\af37\loch\f37  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13240697 \hich\af1\dbch\af37\loch\f1 means the specification defining a software pack file format}{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 , verification utility, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13240697 \hich\af1\dbch\af37\loch\f1 and the associated XML schema file}{\rtlch\fcs1 
-\af0 \ltrch\fcs0 \insrsid11754636\charrsid13240697 .}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 
-\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93CMSIS-RTOS API\'94 means the
- real-time operating system (RTOS) specification defining a generic application programming interface layer for a RTOS system}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15023647 .}{
-\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  
-\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 
-Notwithstanding the foregoing, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4730869 \hich\af1\dbch\af37\loch\f1 the CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{
-\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4730869 \hich\af1\dbch\af37\loch\f1  shall not}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1  include}{\rtlch\fcs1 \af1\afs18 
-\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1  (i) the implementation of other published specification
-\hich\af1\dbch\af37\loch\f1 s }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 referenced }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 in th}{
-\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 e}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 
-; (ii) any enabling technologies that may be necessary to make or use any product or portion thereof that }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4283548 \hich\af1\dbch\af37\loch\f1 complies with the }{\rtlch\fcs1 \af1\afs18 
-\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4283548 \hich\af1\dbch\af37\loch\f1 , but are not themselves expressly set forth in the }{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4283548 \hich\af1\dbch\af37\loch\f1  (e.\hich\af1\dbch\af37\loch\f1 
-g. compiler front ends, code generators, back ends, libraries or other compiler, assembler or linker technologies; validation or debug software or hardware; applications, operating system or driver software; RISC architecture; processor microarchitecture)
-\hich\af1\dbch\af37\loch\f1 ;\hich\af1\dbch\af37\loch\f1  (iii) maskworks and physical layouts of integrated circuit designs; or (iv) RTL or other high}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 
-\hich\af1\dbch\af37\loch\f1  level representations of integrated circuit designs.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
-\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  \'93CMSIS-SVD\'94 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid9306407 means }{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 the specification defining the System View Description (SVD), verification utility, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid11754636\charrsid9306407 and associated XML}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid11754636  schema}{\rtlch\fcs1 \af1\afs18 
-\ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid11754636\charrsid9306407  files. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid9306407 
-\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  \'93Separate Files\'94 means the components in }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid10227990 the CMSIS reference implementation identified}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
- in the Schedule that demonstrate the usage of the CMSIS-CORE, CMSIS-DRIVER, CMSIS-DSP, CMSIS-PACK and CMSIS-RTOS API, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid3618484  for microprocessors 
-or device specific software applications that are for use with microprocessors.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  
-\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {
-\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 1. LICENCE GRANTS.
-\par }\pard \ltrpar\qj \li0\ri0\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 1.1}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES 
-\par 
-\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-transferable }{\rtlch\fcs1 \af1\afs18 
-\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1317547 licence, to use and copy the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS D}{\rtlch\fcs1 \af1\afs18 
-\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 for the purpose of: }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
-\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 
-\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar
-\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 (i) subject to clause 1.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 2}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 , developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products that comply with the }{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 ; and 
-\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1317547 (ii) distributing and having distributed (directly or through your customers and authorised distributors) the CMSIS-D}{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1317547  unmodified, with the products}{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135  you have developed under }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 Clause 1.1 (i) }{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 provided you preserve any copyright notices which are included with the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 . 
-\par }\pard \ltrpar\qj \li0\ri0\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 1.2}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  CONDITIONS ON REDISTRIBUTION}{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
-\par 
-\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 
-\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 
-If you distribute (directly or through your customers and authorised distributors) the products you have created pursuant to Clauses 1.1}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1  
-}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 (i) you agree: (a) not to use ARM\hich\f1 \rquote \loch\f1 s name\hich\af1\dbch\af37\loch\f1 
-, logo or trademarks to market any or all of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1928237 products created under Clause 1.1 (i); }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 (b) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 to }{\rtlch\fcs1 \af1\afs18 
-\ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 pr}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 e}{\rtlch\fcs1 \af1\afs18 
-\ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 serve any copyright notices included in the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 
-\hich\af1\dbch\af37\loch\f1 CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 
-\hich\af1\dbch\af37\loch\f1 ; and (c) to ensure your customers and authorised distributors comply with this Clause 1.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 2}{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1     }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
-\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {
-\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 2. RESTRICTIONS ON USE OF THE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
- CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 .
-\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 
-\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 PERMITTED USERS: The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
-CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 shall be used only by you (either a single individual, or single legal entity) your employees, or by your }{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 on-site }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
-bona fide sub-contractors for whose acts and omissions you hereby agree to be responsible to ARM}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  for}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  to the same extent as }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 you are for }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 your employees, and provided always that such sub-contractors}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 :}{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  (i) are contractually obligated to use the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
-CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 only for your benefit}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
-;}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  and (i}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 i}{\rtlch\fcs1 \af1\afs18 
-\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 ) agree to assign all their work product and any rights they create therein in the supply of such work to you.
-\par COPYRIGHT AND RESERVATION OF RIGHTS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 : The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 
- are owned by ARM or its licensors and are protected by copyright and other intellectual property laws and international treaties. The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{
-\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502  are licensed not sold. Except as expressly licensed herein, you acquire no right, title or interest in the }{\rtlch\fcs1 \af1\afs18 
-\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 
- or any intellectual property therein. In no event shall the licences granted herein be construed as granting you, expressly or by implication, estoppels or otherwise, a licence to use any ARM technology except the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
-\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {
-\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 3}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . SUPPORT.
-\par ARM is not obligated to support the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables but}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  may do so entirely at ARM's discretion. 
-\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 4}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 NO }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 WARRANT}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 Y.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
-\par YOU AGREE THAT THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES ARE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
- LICENSED "AS IS", AND THAT ARM EXPRESSLY DISCLAIMS ALL REPRESENTATIONS, WARRANTIES, CONDITIONS OR OTHER TERMS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION THE IMPLIED WARR
-ANTIES OF NON-INFRINGEMENT, SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  THE CMSIS DELIVERABLES MAY CONTAIN ERRORS.  }{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
-\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 5}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . LIMITATION OF LIABILITY.
-\par THE MAXIMUM LIABILITY OF ARM TO YOU IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN CONTRACT}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ,}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  TORT OR OTHERWISE UNDER OR IN CONNECTION WITH THE SUBJECT MATTER OF THIS LICENCE SHALL NOT EXCEED }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 THE GREATER OF (I) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
-THE TOTAL OF SUMS PAID BY YOU TO ARM (IF ANY) FOR THIS LICENCE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  AND (II) US$10.00}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636   THE LIMITATIONS, EXCLUSIONS AND DISCLAIMERS IN THIS LICEN
-CE SHALL APPLY TO THE MAXIMUM EXTENT ALLOWED BY APPLICABLE LAW.
-\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 6
-}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid13830602 \hich\af1\dbch\af37\loch\f1 . THIRD PARTY RIGHTS.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13830602 
-\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid13830602 \hich\af1\dbch\af37\loch\f1 
-The Separate Files are delivered subject to and your use is governed by their own separate licence agreements. This Licence does not apply to such Separate Files and the\hich\af1\dbch\af37\loch\f1 \hich\f1 y are not included in the term \'93}{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid13830602 
-\loch\af1\dbch\af37\hich\f1 \'94\loch\f1 \hich\f1  under this Licence. You agree to comply with all terms and conditions imposed on you in respect of such Separate Files including those identified in the Schedule (\'93\loch\f1 \hich\f1 Third Party Terms
-\'94\loch\f1 ).  
-\par \hich\af1\dbch\af37\loch\f1 ARM HEREBY DISCLA\hich\af1\dbch\af37\loch\f1 \hich\f1 
-IMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS INCLUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY \'93\loch\f1 \hich\f1 
-OTHER CODE\'94\loch\f1 ), AND THE USE OF\hich\af1\dbch\af37\loch\f1  \hich\af1\dbch\af37\loch\f1 
-ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF SATISFACTORY QUALITY OR FITNESS FOR A PARTICULAR PURPOSE.
-\par \hich\af1\dbch\af37\loch\f1 NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, \hich\af1\dbch\af37\loch\f1 
-INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EX
-\hich\af1\dbch\af37\loch\f1 E\hich\af1\dbch\af37\loch\f1 RCISE OF ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS LICENCE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE FILES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {
-\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 7}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . U.S. GOVERNMENT END USERS.
-\par US Government Restrictions: Use, duplication, reproduction, release, modification, disclosure or transfer of this commercial product and accompanying documentation is restricted in accordance with the terms of this Licence.
-\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 8}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . TERM AND TERMINATION.
-\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 8.1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
-This Licence shall remain in force until terminated }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 in accordance with the terms of Clause 8.2 or Clause 8.3 below}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
-\par 8.2 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
-Without prejudice to any of its other rights if you are in breach of any of the terms and conditions of this Licence then ARM may terminate this Licence immediately upon giving written notice to you}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid7630822 .  You may terminate this Licence at any time. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
-\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 
-8.3 This Licence shall immediately terminate and shall be unavailable to you if you or any party affiliated to you asserts any patents against ARM, ARM affiliates, third parties who have a valid licence fro\hich\af1\dbch\af37\loch\f1 
-m ARM for the CMSIS Deliverables, or any customers or distributors of any of them based upon a claim that your (or your affiliate) patent is Necessary to implement the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
-\hich\af1\dbch\af37\loch\f1 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 . In this Licence}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
-\hich\af1\dbch\af37\loch\f1 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1  (i) "affiliate" means any entity controlling, contr\hich\af1\dbch\af37\loch\f1 
-olled by or under common control with a party (in fact or in law, via voting securities, management control or otherwise) and "affiliated" shall be construed accordingly; (ii) "assert" means to allege infringement in legal or administrative proceedings, o
-\hich\af1\dbch\af37\loch\f1 r\hich\af1\dbch\af37\loch\f1  proceedings before any other competent trade, arbitral or international authority; }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 and }{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 \hich\f1 (iii) \'93\loch\f1 \hich\f1 Necessary\'94\loch\f1 
- means with respect to any claims of any patent, those claims which, without the appropriate permission of the patent owner, will be infringed when imp\hich\af1\dbch\af37\loch\f1 lementing the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1  Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 
-because no alternative, commercially reasonable, non-infringing way of implementing the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1  Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 is known.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid5900444 \hich\af1\dbch\af37\loch\f1  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
-\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {
-\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 8.4 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid7630822 Upon termination of this Licence,}{
-\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636  you shall stop }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 
-using the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 
- and destroy all copies of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396  in your possession. The provisions of clauses 5, 6, 7, 8 and 9 shall survive termination of this Licence.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636   
-\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 9}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . GENERAL.
-\par This Licence is governed by English Law. Except where ARM agrees otherwise in a written contract signed by you and ARM, this is the only agreement between you and ARM relating to the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 
- and it may only be modified by written agreement between you and ARM. Except as expressly agreed in writing, this Licence may not be modified by purchase orders, ad
-vertising or other representation by any person. If any clause or sentence in this Licence is held by a court of law to be illegal or unenforceable the remaining provisions of this Licence shall not be affected thereby. The failure by ARM to enforce any o
-f the provisions of this Licence, unless waived in writing, shall not constitute a waiver of ARM's rights to enforce such provision or any other provision of this Licence in the future.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636   This Licence may not be assigned without the prior written consent of ARM.
-\par }\pard \ltrpar\qc \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {
-\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \page SCHEDULE
-\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {
-\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 Separate Files
-\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 The }{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 package }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 also }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 includes the components}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636  contained in the following directories}{\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 
-\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (a)\tab}}\pard \ltrpar
-\qj \fi-360\li720\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\ls16\adjustright\rin0\lin720\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 
-\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 
-\hich\af1\dbch\af37\loch\f1 DSP_Lib}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1  -  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 
-DSP Library sources and examples}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ; 
-\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (b)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 
-\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 
-\hich\af1\dbch\af37\loch\f1 Include}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1  - Header files; 
-\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (c)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 
-\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 
-\hich\af1\dbch\af37\loch\f1 Lib}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1  - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 
-DSP Library build for various toolchains}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ; 
-\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (d)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 
-\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 
-\hich\af1\dbch\af37\loch\f1 RTOS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1  - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 
-Header file template for CMSIS-RTOS implementation}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ; and 
-\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (e)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 .}{\rtlch\fcs1 \af1\afs18 
-\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /Device - T}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid14488502 \hich\af1\dbch\af37\loch\f1 emplate files and implementations for Cortex-M class processors}{
-\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 . 
-\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
-\par \hich\af1\dbch\af37\loch\f1 All of the above components (a\hich\f1 \endash \loch\f1  e) are licensed to you under the terms of the BSD licence, which is incorp\hich\af1\dbch\af37\loch\f1 orated within or alongside the above components.  
-\par }\pard \ltrpar\qj \li284\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin284\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1   }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 
-\f1\fs18\insrsid11754636\charrsid13975144 \hich\af1\dbch\af37\loch\f1 (f)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1    }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13975144 
-\hich\af1\dbch\af37\loch\f1 ./CMSIS/Driver \hich\f1 \endash \loch\f1  CMSIS-Driver header files}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
-\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13975144 \hich\af1\dbch\af37\loch\f1   (g)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1  }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 
-\hich\af37\dbch\af37\loch\f37  }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ./CMSIS/Pack \hich\f1 \endash \loch\f1  Example Device Family Pack}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636\charrsid13975144 
-
-\par }\pard\plain \ltrpar\s32\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \rtlch\fcs1 \af0\afs21\alang1025 \ltrch\fcs0 \f39\fs21\lang2057\langfe1033\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1 
-\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
-\par The above components (f \endash  g) are licensed to you under the terms of the zlib licence, which is incorporated within or alongside the above components.
-\par 
-\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid14488502        }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 
-\par 
-\par 
-\par }\pard\plain \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 
-\fs22\lang2057\langfe1033\loch\af37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid2958685 \hich\af1\dbch\af37\loch\f1 ARM contract reference LEC-PRE-00489}{\rtlch\fcs1 \af1\afs18 
-\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 - v3.0}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid2958685 
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bsp/es32f0334/libraries/CMSIS/Include/SConscript

@@ -1,11 +0,0 @@
-Import('ES32_SDK_ROOT')
-
-from building import *
-
-cwd = GetCurrentDir()
-src = Glob('*.c')
-include_path  = [cwd]
-
-group = DefineGroup('CMSIS2', src, depend = [''], CPPPATH = include_path)
-
-Return('group')

bsp/es32f0334/libraries/CMSIS/Include/core_cm3.h

@@ -1,1763 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M3
-  @{
- */
-
-/*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM3_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (0x03U)                                      /*!< Cortex-M Core */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
-  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
-  #define __STATIC_INLINE  static inline
-
-#else
-  #error Unknown compiler
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "core_cmInstr.h"                /* Core Instruction Access */
-#include "core_cmFunc.h"                 /* Core Function Access */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM3_REV
-    #define __CM3_REV               0x0200U
-    #warning "__CM3_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M3 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[24U];
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[24U];
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[24U];
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[24U];
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[56U];
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED5[644U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-        uint32_t RESERVED0[5U];
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if (__CM3_REV < 0x0201U)                   /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-#else
-        uint32_t RESERVED1[1U];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[6U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable External Interrupt
-  \details Enables a device-specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Disable External Interrupt
-  \details Disables a device-specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
-  \param [in]      IRQn  Interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of an external interrupt.
-  \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of an external interrupt.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in NVIC and returns the active bit.
-  \param [in]      IRQn  Interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of an interrupt.
-  \note    The priority cannot be set for every core interrupt.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) < 0)
-  {
-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of an interrupt.
-           The interrupt number can be positive to specify an external (device specific) interrupt,
-           or negative to specify an internal (core) interrupt.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) < 0)
-  {
-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

bsp/es32f0334/libraries/CMSIS/Include/core_cm4.h

@@ -1,1937 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4.h
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M4
-  @{
- */
-
-/*  CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM4_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (0x04U)                                      /*!< Cortex-M Core */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
-  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
-  #define __STATIC_INLINE  static inline
-
-#else
-  #error Unknown compiler
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #if (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#endif
-
-#include "core_cmInstr.h"                /* Core Instruction Access */
-#include "core_cmFunc.h"                 /* Core Function Access */
-#include "core_cmSimd.h"                 /* Compiler specific SIMD Intrinsics */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM4_REV
-    #define __CM4_REV               0x0000U
-    #warning "__CM4_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[24U];
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[24U];
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[24U];
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[24U];
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[56U];
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED5[644U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-        uint32_t RESERVED0[5U];
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[6U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-#if (__FPU_PRESENT == 1U)
-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable External Interrupt
-  \details Enables a device-specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Disable External Interrupt
-  \details Disables a device-specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
-  \param [in]      IRQn  Interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of an external interrupt.
-  \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of an external interrupt.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in NVIC and returns the active bit.
-  \param [in]      IRQn  Interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of an interrupt.
-  \note    The priority cannot be set for every core interrupt.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) < 0)
-  {
-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of an interrupt.
-           The interrupt number can be positive to specify an external (device specific) interrupt,
-           or negative to specify an internal (core) interrupt.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) < 0)
-  {
-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

bsp/es32f0334/libraries/CMSIS/Include/core_cm7.h

@@ -1,2512 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm7.h
- * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM7_H_GENERIC
-#define __CORE_CM7_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M7
-  @{
- */
-
-/*  CMSIS CM7 definitions */
-#define __CM7_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */
-#define __CM7_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */
-#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM7_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (0x07U)                                      /*!< Cortex-M Core */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
-  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
-  #define __STATIC_INLINE  static inline
-
-#else
-  #error Unknown compiler
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #if (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#endif
-
-#include "core_cmInstr.h"                /* Core Instruction Access */
-#include "core_cmFunc.h"                 /* Core Function Access */
-#include "core_cmSimd.h"                 /* Compiler specific SIMD Intrinsics */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM7_H_DEPENDANT
-#define __CORE_CM7_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM7_REV
-    #define __CM7_REV               0x0000U
-    #warning "__CM7_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __ICACHE_PRESENT
-    #define __ICACHE_PRESENT          0U
-    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __DCACHE_PRESENT
-    #define __DCACHE_PRESENT          0U
-    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __DTCM_PRESENT
-    #define __DTCM_PRESENT            0U
-    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M7 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[24U];
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[24U];
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[24U];
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[24U];
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[56U];
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED5[644U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
-  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
-  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
-  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-        uint32_t RESERVED3[93U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
-        uint32_t RESERVED4[15U];
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
-        uint32_t RESERVED5[1U];
-  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
-        uint32_t RESERVED6[1U];
-  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
-  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
-  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
-  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
-  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
-  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
-  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
-  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
-        uint32_t RESERVED7[6U];
-  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
-  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
-  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
-  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
-  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
-
-#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
-
-#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
-
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
-
-#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
-#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
-
-#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
-#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[6U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-        uint32_t RESERVED3[981U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/* Media and FP Feature Register 2 Definitions */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-#if (__FPU_PRESENT == 1U)
-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable External Interrupt
-  \details Enables a device-specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Disable External Interrupt
-  \details Disables a device-specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
-  \param [in]      IRQn  Interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of an external interrupt.
-  \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of an external interrupt.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in NVIC and returns the active bit.
-  \param [in]      IRQn  Interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of an interrupt.
-  \note    The priority cannot be set for every core interrupt.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) < 0)
-  {
-    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of an interrupt.
-           The interrupt number can be positive to specify an external (device specific) interrupt,
-           or negative to specify an internal (core) interrupt.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) < 0)
-  {
-    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-  uint32_t mvfr0;
-
-  mvfr0 = SCB->MVFR0;
-  if        ((mvfr0 & 0x00000FF0UL) == 0x220UL)
-  {
-    return 2UL;           /* Double + Single precision FPU */
-  }
-  else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)
-  {
-    return 1UL;           /* Single precision FPU */
-  }
-  else
-  {
-    return 0UL;           /* No FPU */
-  }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################  Cache functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_CacheFunctions Cache Functions
-  \brief    Functions that configure Instruction and Data cache.
-  @{
- */
-
-/* Cache Size ID Register Macros */
-#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
-#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
-
-
-/**
-  \brief   Enable I-Cache
-  \details Turns on I-Cache
-  */
-__STATIC_INLINE void SCB_EnableICache (void)
-{
-  #if (__ICACHE_PRESENT == 1U)
-    __DSB();
-    __ISB();
-    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
-    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Disable I-Cache
-  \details Turns off I-Cache
-  */
-__STATIC_INLINE void SCB_DisableICache (void)
-{
-  #if (__ICACHE_PRESENT == 1U)
-    __DSB();
-    __ISB();
-    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
-    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Invalidate I-Cache
-  \details Invalidates I-Cache
-  */
-__STATIC_INLINE void SCB_InvalidateICache (void)
-{
-  #if (__ICACHE_PRESENT == 1U)
-    __DSB();
-    __ISB();
-    SCB->ICIALLU = 0UL;
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Enable D-Cache
-  \details Turns on D-Cache
-  */
-__STATIC_INLINE void SCB_EnableDCache (void)
-{
-  #if (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-                                            /* invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-      do {
-        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
-                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
-        #if defined ( __CC_ARM )
-          __schedule_barrier();
-        #endif
-      } while (ways--);
-    } while(sets--);
-    __DSB();
-
-    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Disable D-Cache
-  \details Turns off D-Cache
-  */
-__STATIC_INLINE void SCB_DisableDCache (void)
-{
-  #if (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
-
-                                            /* clean & invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-      do {
-        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
-                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
-        #if defined ( __CC_ARM )
-          __schedule_barrier();
-        #endif
-      } while (ways--);
-    } while(sets--);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Invalidate D-Cache
-  \details Invalidates D-Cache
-  */
-__STATIC_INLINE void SCB_InvalidateDCache (void)
-{
-  #if (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-                                            /* invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-      do {
-        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
-                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
-        #if defined ( __CC_ARM )
-          __schedule_barrier();
-        #endif
-      } while (ways--);
-    } while(sets--);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Clean D-Cache
-  \details Cleans D-Cache
-  */
-__STATIC_INLINE void SCB_CleanDCache (void)
-{
-  #if (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-                                            /* clean D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-      do {
-        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
-                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
-        #if defined ( __CC_ARM )
-          __schedule_barrier();
-        #endif
-      } while (ways--);
-    } while(sets--);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Clean & Invalidate D-Cache
-  \details Cleans and Invalidates D-Cache
-  */
-__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
-{
-  #if (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-                                            /* clean & invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-      do {
-        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
-                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
-        #if defined ( __CC_ARM )
-          __schedule_barrier();
-        #endif
-      } while (ways--);
-    } while(sets--);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   D-Cache Invalidate by address
-  \details Invalidates D-Cache for the given address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
-  #if (__DCACHE_PRESENT == 1U)
-     int32_t op_size = dsize;
-    uint32_t op_addr = (uint32_t)addr;
-     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
-    __DSB();
-
-    while (op_size > 0) {
-      SCB->DCIMVAC = op_addr;
-      op_addr += linesize;
-      op_size -= linesize;
-    }
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   D-Cache Clean by address
-  \details Cleans D-Cache for the given address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
-  #if (__DCACHE_PRESENT == 1)
-     int32_t op_size = dsize;
-    uint32_t op_addr = (uint32_t) addr;
-     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
-    __DSB();
-
-    while (op_size > 0) {
-      SCB->DCCMVAC = op_addr;
-      op_addr += linesize;
-      op_size -= linesize;
-    }
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   D-Cache Clean and Invalidate by address
-  \details Cleans and invalidates D_Cache for the given address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
-  #if (__DCACHE_PRESENT == 1U)
-     int32_t op_size = dsize;
-    uint32_t op_addr = (uint32_t) addr;
-     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
-    __DSB();
-
-    while (op_size > 0) {
-      SCB->DCCIMVAC = op_addr;
-      op_addr += linesize;
-      op_size -= linesize;
-    }
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/*@} end of CMSIS_Core_CacheFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

bsp/es32f0334/libraries/CMSIS/RTOS/Template/cmsis_os.h

@@ -1,707 +0,0 @@
-/* ----------------------------------------------------------------------
- * $Date:        5. February 2013
- * $Revision:    V1.02
- *
- * Project:      CMSIS-RTOS API
- * Title:        cmsis_os.h template header file
- *
- * Version 0.02
- *    Initial Proposal Phase
- * Version 0.03
- *    osKernelStart added, optional feature: main started as thread
- *    osSemaphores have standard behavior
- *    osTimerCreate does not start the timer, added osTimerStart
- *    osThreadPass is renamed to osThreadYield
- * Version 1.01
- *    Support for C++ interface
- *     - const attribute removed from the osXxxxDef_t typedef's
- *     - const attribute added to the osXxxxDef macros
- *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
- *    Added: osKernelInitialize
- * Version 1.02
- *    Control functions for short timeouts in microsecond resolution:
- *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
- *    Removed: osSignalGet 
- *----------------------------------------------------------------------------
- *
- * Copyright (c) 2013 ARM LIMITED
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *  - Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *  - Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *  - Neither the name of ARM  nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without
- *    specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *---------------------------------------------------------------------------*/
- 
- 
-#ifndef _CMSIS_OS_H
-#define _CMSIS_OS_H
- 
-/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version.
-#define osCMSIS           0x10002      ///< API version (main [31:16] .sub [15:0])
- 
-/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
-#define osCMSIS_KERNEL    0x10000	   ///< RTOS identification and version (main [31:16] .sub [15:0])
- 
-/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
-#define osKernelSystemId "KERNEL V1.00"   ///< RTOS identification string
- 
-/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS.
-#define osFeature_MainThread   1       ///< main thread      1=main can be thread, 0=not available
-#define osFeature_Pool         1       ///< Memory Pools:    1=available, 0=not available
-#define osFeature_MailQ        1       ///< Mail Queues:     1=available, 0=not available
-#define osFeature_MessageQ     1       ///< Message Queues:  1=available, 0=not available
-#define osFeature_Signals      8       ///< maximum number of Signal Flags available per thread
-#define osFeature_Semaphore    30      ///< maximum count for \ref osSemaphoreCreate function
-#define osFeature_Wait         1       ///< osWait function: 1=available, 0=not available
-#define osFeature_SysTick      1       ///< osKernelSysTick functions: 1=available, 0=not available
- 
-#include <stdint.h>
-#include <stddef.h>
- 
-#ifdef  __cplusplus
-extern "C"
-{
-#endif
- 
- 
-// ==== Enumeration, structures, defines ====
- 
-/// Priority used for thread control.
-/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS.
-typedef enum  {
-  osPriorityIdle          = -3,          ///< priority: idle (lowest)
-  osPriorityLow           = -2,          ///< priority: low
-  osPriorityBelowNormal   = -1,          ///< priority: below normal
-  osPriorityNormal        =  0,          ///< priority: normal (default)
-  osPriorityAboveNormal   = +1,          ///< priority: above normal
-  osPriorityHigh          = +2,          ///< priority: high
-  osPriorityRealtime      = +3,          ///< priority: realtime (highest)
-  osPriorityError         =  0x84        ///< system cannot determine priority or thread has illegal priority
-} osPriority;
- 
-/// Timeout value.
-/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS.
-#define osWaitForever     0xFFFFFFFF     ///< wait forever timeout value
- 
-/// Status code values returned by CMSIS-RTOS functions.
-/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS.
-typedef enum  {
-  osOK                    =     0,       ///< function completed; no error or event occurred.
-  osEventSignal           =  0x08,       ///< function completed; signal event occurred.
-  osEventMessage          =  0x10,       ///< function completed; message event occurred.
-  osEventMail             =  0x20,       ///< function completed; mail event occurred.
-  osEventTimeout          =  0x40,       ///< function completed; timeout occurred.
-  osErrorParameter        =  0x80,       ///< parameter error: a mandatory parameter was missing or specified an incorrect object.
-  osErrorResource         =  0x81,       ///< resource not available: a specified resource was not available.
-  osErrorTimeoutResource  =  0xC1,       ///< resource not available within given time: a specified resource was not available within the timeout period.
-  osErrorISR              =  0x82,       ///< not allowed in ISR context: the function cannot be called from interrupt service routines.
-  osErrorISRRecursive     =  0x83,       ///< function called multiple times from ISR with same object.
-  osErrorPriority         =  0x84,       ///< system cannot determine priority or thread has illegal priority.
-  osErrorNoMemory         =  0x85,       ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.
-  osErrorValue            =  0x86,       ///< value of a parameter is out of range.
-  osErrorOS               =  0xFF,       ///< unspecified RTOS error: run-time error but no other error message fits.
-  os_status_reserved      =  0x7FFFFFFF  ///< prevent from enum down-size compiler optimization.
-} osStatus;
- 
- 
-/// Timer type value for the timer definition.
-/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
-typedef enum  {
-  osTimerOnce             =     0,       ///< one-shot timer
-  osTimerPeriodic         =     1        ///< repeating timer
-} os_timer_type;
- 
-/// Entry point of a thread.
-/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
-typedef void (*os_pthread) (void const *argument);
- 
-/// Entry point of a timer call back function.
-/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
-typedef void (*os_ptimer) (void const *argument);
- 
-// >>> the following data type definitions may shall adapted towards a specific RTOS
- 
-/// Thread ID identifies the thread (pointer to a thread control block).
-/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS.
-typedef struct os_thread_cb *osThreadId;
- 
-/// Timer ID identifies the timer (pointer to a timer control block).
-/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS.
-typedef struct os_timer_cb *osTimerId;
- 
-/// Mutex ID identifies the mutex (pointer to a mutex control block).
-/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS.
-typedef struct os_mutex_cb *osMutexId;
- 
-/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
-/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS.
-typedef struct os_semaphore_cb *osSemaphoreId;
- 
-/// Pool ID identifies the memory pool (pointer to a memory pool control block).
-/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS.
-typedef struct os_pool_cb *osPoolId;
- 
-/// Message ID identifies the message queue (pointer to a message queue control block).
-/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS.
-typedef struct os_messageQ_cb *osMessageQId;
- 
-/// Mail ID identifies the mail queue (pointer to a mail queue control block).
-/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS.
-typedef struct os_mailQ_cb *osMailQId;
- 
- 
-/// Thread Definition structure contains startup information of a thread.
-/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
-typedef struct os_thread_def  {
-  os_pthread               pthread;    ///< start address of thread function
-  osPriority             tpriority;    ///< initial thread priority
-  uint32_t               instances;    ///< maximum number of instances of that thread function
-  uint32_t               stacksize;    ///< stack size requirements in bytes; 0 is default stack size
-} osThreadDef_t;
- 
-/// Timer Definition structure contains timer parameters.
-/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
-typedef struct os_timer_def  {
-  os_ptimer                 ptimer;    ///< start address of a timer function
-} osTimerDef_t;
- 
-/// Mutex Definition structure contains setup information for a mutex.
-/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
-typedef struct os_mutex_def  {
-  uint32_t                   dummy;    ///< dummy value.
-} osMutexDef_t;
- 
-/// Semaphore Definition structure contains setup information for a semaphore.
-/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
-typedef struct os_semaphore_def  {
-  uint32_t                   dummy;    ///< dummy value.
-} osSemaphoreDef_t;
- 
-/// Definition structure for memory block allocation.
-/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
-typedef struct os_pool_def  {
-  uint32_t                 pool_sz;    ///< number of items (elements) in the pool
-  uint32_t                 item_sz;    ///< size of an item
-  void                       *pool;    ///< pointer to memory for pool
-} osPoolDef_t;
- 
-/// Definition structure for message queue.
-/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
-typedef struct os_messageQ_def  {
-  uint32_t                queue_sz;    ///< number of elements in the queue
-  uint32_t                 item_sz;    ///< size of an item
-  void                       *pool;    ///< memory array for messages
-} osMessageQDef_t;
- 
-/// Definition structure for mail queue.
-/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
-typedef struct os_mailQ_def  {
-  uint32_t                queue_sz;    ///< number of elements in the queue
-  uint32_t                 item_sz;    ///< size of an item
-  void                       *pool;    ///< memory array for mail
-} osMailQDef_t;
- 
-/// Event structure contains detailed information about an event.
-/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
-///       However the struct may be extended at the end.
-typedef struct  {
-  osStatus                 status;     ///< status code: event or error information
-  union  {
-    uint32_t                    v;     ///< message as 32-bit value
-    void                       *p;     ///< message or mail as void pointer
-    int32_t               signals;     ///< signal flags
-  } value;                             ///< event value
-  union  {
-    osMailQId             mail_id;     ///< mail id obtained by \ref osMailCreate
-    osMessageQId       message_id;     ///< message id obtained by \ref osMessageCreate
-  } def;                               ///< event definition
-} osEvent;
- 
- 
-//  ==== Kernel Control Functions ====
- 
-/// Initialize the RTOS Kernel for creating objects.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS.
-osStatus osKernelInitialize (void);
- 
-/// Start the RTOS Kernel.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
-osStatus osKernelStart (void);
- 
-/// Check if the RTOS kernel is already started.
-/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
-/// \return 0 RTOS is not started, 1 RTOS is started.
-int32_t osKernelRunning(void);
- 
-#if (defined (osFeature_SysTick)  &&  (osFeature_SysTick != 0))     // System Timer available
- 
-/// Get the RTOS kernel system timer counter 
-/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
-/// \return RTOS kernel system timer as 32-bit value 
-uint32_t osKernelSysTick (void);
- 
-/// The RTOS kernel system timer frequency in Hz
-/// \note Reflects the system timer setting and is typically defined in a configuration file.
-#define osKernelSysTickFrequency 100000000
- 
-/// Convert a microseconds value to a RTOS kernel system timer value.
-/// \param         microsec     time value in microseconds.
-/// \return time value normalized to the \ref osKernelSysTickFrequency
-#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
- 
-#endif    // System Timer available
- 
-//  ==== Thread Management ====
- 
-/// Create a Thread Definition with function, priority, and stack requirements.
-/// \param         name         name of the thread function.
-/// \param         priority     initial priority of the thread function.
-/// \param         instances    number of possible thread instances.
-/// \param         stacksz      stack size (in bytes) requirements for the thread function.
-/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
-///       macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal)  // object is external
-#define osThreadDef(name, priority, instances, stacksz)  \
-extern const osThreadDef_t os_thread_def_##name
-#else                            // define the object
-#define osThreadDef(name, priority, instances, stacksz)  \
-const osThreadDef_t os_thread_def_##name = \
-{ (name), (priority), (instances), (stacksz)  }
-#endif
- 
-/// Access a Thread definition.
-/// \param         name          name of the thread definition object.
-/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
-///       macro body is implementation specific in every CMSIS-RTOS.
-#define osThread(name)  \
-&os_thread_def_##name
- 
-/// Create a thread and add it to Active Threads and set it to state READY.
-/// \param[in]     thread_def    thread definition referenced with \ref osThread.
-/// \param[in]     argument      pointer that is passed to the thread function as start argument.
-/// \return thread ID for reference by other functions or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
-osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
- 
-/// Return the thread ID of the current running thread.
-/// \return thread ID for reference by other functions or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
-osThreadId osThreadGetId (void);
- 
-/// Terminate execution of a thread and remove it from Active Threads.
-/// \param[in]     thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
-osStatus osThreadTerminate (osThreadId thread_id);
- 
-/// Pass control to next thread that is in state \b READY.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
-osStatus osThreadYield (void);
- 
-/// Change priority of an active thread.
-/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \param[in]     priority      new priority value for the thread function.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
-osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
- 
-/// Get current priority of an active thread.
-/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \return current priority value of the thread function.
-/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
-osPriority osThreadGetPriority (osThreadId thread_id);
- 
- 
-//  ==== Generic Wait Functions ====
- 
-/// Wait for Timeout (Time Delay).
-/// \param[in]     millisec      time delay value
-/// \return status code that indicates the execution status of the function.
-osStatus osDelay (uint32_t millisec);
- 
-#if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0))     // Generic Wait available
- 
-/// Wait for Signal, Message, Mail, or Timeout.
-/// \param[in] millisec          timeout value or 0 in case of no time-out
-/// \return event that contains signal, message, or mail information or error code.
-/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
-osEvent osWait (uint32_t millisec);
- 
-#endif  // Generic Wait available
- 
- 
-//  ==== Timer Management Functions ====
-/// Define a Timer object.
-/// \param         name          name of the timer object.
-/// \param         function      name of the timer call back function.
-/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
-///       macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal)  // object is external
-#define osTimerDef(name, function)  \
-extern const osTimerDef_t os_timer_def_##name
-#else                            // define the object
-#define osTimerDef(name, function)  \
-const osTimerDef_t os_timer_def_##name = \
-{ (function) }
-#endif
- 
-/// Access a Timer definition.
-/// \param         name          name of the timer object.
-/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
-///       macro body is implementation specific in every CMSIS-RTOS.
-#define osTimer(name) \
-&os_timer_def_##name
- 
-/// Create a timer.
-/// \param[in]     timer_def     timer object referenced with \ref osTimer.
-/// \param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
-/// \param[in]     argument      argument to the timer call back function.
-/// \return timer ID for reference by other functions or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
-osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
- 
-/// Start or restart a timer.
-/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
-/// \param[in]     millisec      time delay value of the timer.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
-osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
- 
-/// Stop the timer.
-/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
-osStatus osTimerStop (osTimerId timer_id);
- 
-/// Delete a timer that was created by \ref osTimerCreate.
-/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS.
-osStatus osTimerDelete (osTimerId timer_id);
- 
- 
-//  ==== Signal Management ====
- 
-/// Set the specified Signal Flags of an active thread.
-/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \param[in]     signals       specifies the signal flags of the thread that should be set.
-/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
-/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
-int32_t osSignalSet (osThreadId thread_id, int32_t signals);
- 
-/// Clear the specified Signal Flags of an active thread.
-/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
-/// \param[in]     signals       specifies the signal flags of the thread that shall be cleared.
-/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
-/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
-int32_t osSignalClear (osThreadId thread_id, int32_t signals);
- 
-/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
-/// \param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.
-/// \param[in]     millisec      timeout value or 0 in case of no time-out.
-/// \return event flag information or error code.
-/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
-osEvent osSignalWait (int32_t signals, uint32_t millisec);
- 
- 
-//  ==== Mutex Management ====
- 
-/// Define a Mutex.
-/// \param         name          name of the mutex object.
-/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
-///       macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal)  // object is external
-#define osMutexDef(name)  \
-extern const osMutexDef_t os_mutex_def_##name
-#else                            // define the object
-#define osMutexDef(name)  \
-const osMutexDef_t os_mutex_def_##name = { 0 }
-#endif
- 
-/// Access a Mutex definition.
-/// \param         name          name of the mutex object.
-/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
-///       macro body is implementation specific in every CMSIS-RTOS.
-#define osMutex(name)  \
-&os_mutex_def_##name
- 
-/// Create and Initialize a Mutex object.
-/// \param[in]     mutex_def     mutex definition referenced with \ref osMutex.
-/// \return mutex ID for reference by other functions or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
-osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
- 
-/// Wait until a Mutex becomes available.
-/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
-/// \param[in]     millisec      timeout value or 0 in case of no time-out.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
-osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
- 
-/// Release a Mutex that was obtained by \ref osMutexWait.
-/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
-osStatus osMutexRelease (osMutexId mutex_id);
- 
-/// Delete a Mutex that was created by \ref osMutexCreate.
-/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS.
-osStatus osMutexDelete (osMutexId mutex_id);
- 
- 
-//  ==== Semaphore Management Functions ====
- 
-#if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))     // Semaphore available
- 
-/// Define a Semaphore object.
-/// \param         name          name of the semaphore object.
-/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
-///       macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal)  // object is external
-#define osSemaphoreDef(name)  \
-extern const osSemaphoreDef_t os_semaphore_def_##name
-#else                            // define the object
-#define osSemaphoreDef(name)  \
-const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
-#endif
- 
-/// Access a Semaphore definition.
-/// \param         name          name of the semaphore object.
-/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
-///       macro body is implementation specific in every CMSIS-RTOS.
-#define osSemaphore(name)  \
-&os_semaphore_def_##name
- 
-/// Create and Initialize a Semaphore object used for managing resources.
-/// \param[in]     semaphore_def semaphore definition referenced with \ref osSemaphore.
-/// \param[in]     count         number of available resources.
-/// \return semaphore ID for reference by other functions or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
-osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
- 
-/// Wait until a Semaphore token becomes available.
-/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
-/// \param[in]     millisec      timeout value or 0 in case of no time-out.
-/// \return number of available tokens, or -1 in case of incorrect parameters.
-/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
-int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
- 
-/// Release a Semaphore token.
-/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
-osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
- 
-/// Delete a Semaphore that was created by \ref osSemaphoreCreate.
-/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
-osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
- 
-#endif     // Semaphore available
- 
- 
-//  ==== Memory Pool Management Functions ====
- 
-#if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0))  // Memory Pool Management available
- 
-/// \brief Define a Memory Pool.
-/// \param         name          name of the memory pool.
-/// \param         no            maximum number of blocks (objects) in the memory pool.
-/// \param         type          data type of a single block (object).
-/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
-///       macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal)  // object is external
-#define osPoolDef(name, no, type)   \
-extern const osPoolDef_t os_pool_def_##name
-#else                            // define the object
-#define osPoolDef(name, no, type)   \
-const osPoolDef_t os_pool_def_##name = \
-{ (no), sizeof(type), NULL }
-#endif
- 
-/// \brief Access a Memory Pool definition.
-/// \param         name          name of the memory pool
-/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
-///       macro body is implementation specific in every CMSIS-RTOS.
-#define osPool(name) \
-&os_pool_def_##name
- 
-/// Create and Initialize a memory pool.
-/// \param[in]     pool_def      memory pool definition referenced with \ref osPool.
-/// \return memory pool ID for reference by other functions or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
-osPoolId osPoolCreate (const osPoolDef_t *pool_def);
- 
-/// Allocate a memory block from a memory pool.
-/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
-/// \return address of the allocated memory block or NULL in case of no memory available.
-/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
-void *osPoolAlloc (osPoolId pool_id);
- 
-/// Allocate a memory block from a memory pool and set memory block to zero.
-/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
-/// \return address of the allocated memory block or NULL in case of no memory available.
-/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
-void *osPoolCAlloc (osPoolId pool_id);
- 
-/// Return an allocated memory block back to a specific memory pool.
-/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
-/// \param[in]     block         address of the allocated memory block that is returned to the memory pool.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
-osStatus osPoolFree (osPoolId pool_id, void *block);
- 
-#endif   // Memory Pool Management available
- 
- 
-//  ==== Message Queue Management Functions ====
- 
-#if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0))     // Message Queues available
- 
-/// \brief Create a Message Queue Definition.
-/// \param         name          name of the queue.
-/// \param         queue_sz      maximum number of messages in the queue.
-/// \param         type          data type of a single message element (for debugger).
-/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
-///       macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal)  // object is external
-#define osMessageQDef(name, queue_sz, type)   \
-extern const osMessageQDef_t os_messageQ_def_##name
-#else                            // define the object
-#define osMessageQDef(name, queue_sz, type)   \
-const osMessageQDef_t os_messageQ_def_##name = \
-{ (queue_sz), sizeof (type)  }
-#endif
- 
-/// \brief Access a Message Queue Definition.
-/// \param         name          name of the queue
-/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
-///       macro body is implementation specific in every CMSIS-RTOS.
-#define osMessageQ(name) \
-&os_messageQ_def_##name
- 
-/// Create and Initialize a Message Queue.
-/// \param[in]     queue_def     queue definition referenced with \ref osMessageQ.
-/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
-/// \return message queue ID for reference by other functions or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
-osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
- 
-/// Put a Message to a Queue.
-/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
-/// \param[in]     info          message information.
-/// \param[in]     millisec      timeout value or 0 in case of no time-out.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
-osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
- 
-/// Get a Message or Wait for a Message from a Queue.
-/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
-/// \param[in]     millisec      timeout value or 0 in case of no time-out.
-/// \return event information that includes status code.
-/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
-osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
- 
-#endif     // Message Queues available
- 
- 
-//  ==== Mail Queue Management Functions ====
- 
-#if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))     // Mail Queues available
- 
-/// \brief Create a Mail Queue Definition.
-/// \param         name          name of the queue
-/// \param         queue_sz      maximum number of messages in queue
-/// \param         type          data type of a single message element
-/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
-///       macro body is implementation specific in every CMSIS-RTOS.
-#if defined (osObjectsExternal)  // object is external
-#define osMailQDef(name, queue_sz, type) \
-extern const osMailQDef_t os_mailQ_def_##name
-#else                            // define the object
-#define osMailQDef(name, queue_sz, type) \
-const osMailQDef_t os_mailQ_def_##name =  \
-{ (queue_sz), sizeof (type) }
-#endif
- 
-/// \brief Access a Mail Queue Definition.
-/// \param         name          name of the queue
-/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
-///       macro body is implementation specific in every CMSIS-RTOS.
-#define osMailQ(name)  \
-&os_mailQ_def_##name
- 
-/// Create and Initialize mail queue.
-/// \param[in]     queue_def     reference to the mail queue definition obtain with \ref osMailQ
-/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
-/// \return mail queue ID for reference by other functions or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
-osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
- 
-/// Allocate a memory block from a mail.
-/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
-/// \param[in]     millisec      timeout value or 0 in case of no time-out
-/// \return pointer to memory block that can be filled with mail or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
-void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
- 
-/// Allocate a memory block from a mail and set memory block to zero.
-/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
-/// \param[in]     millisec      timeout value or 0 in case of no time-out
-/// \return pointer to memory block that can be filled with mail or NULL in case of error.
-/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
-void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
- 
-/// Put a mail to a queue.
-/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
-/// \param[in]     mail          memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
-osStatus osMailPut (osMailQId queue_id, void *mail);
- 
-/// Get a mail from a queue.
-/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
-/// \param[in]     millisec      timeout value or 0 in case of no time-out
-/// \return event that contains mail information or error code.
-/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
-osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
- 
-/// Free a memory block from a mail.
-/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
-/// \param[in]     mail          pointer to the memory block that was obtained with \ref osMailGet.
-/// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
-osStatus osMailFree (osMailQId queue_id, void *mail);
- 
-#endif  // Mail Queues available
- 
- 
-#ifdef  __cplusplus
-}
-#endif
- 
-#endif  // _CMSIS_OS_H

bsp/es32f0334/libraries/CMSIS/index.html

@@ -1,14 +0,0 @@
-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
-<html xmlns="http://www.w3.org/1999/xhtml">
-<head>
-<title>Redirect to the CMSIS main page after 0 seconds</title>
-<meta http-equiv="refresh" content="0; URL=Documentation/General/html/index.html">
-<meta name="keywords" content="automatic redirection">
-</head>
-
-<body>
-
-If the automatic redirection is failing, click <a href="Documentation/General/html/index.html">open CMSIS Documentation</a>.
-
-</body>
-</html>

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_acmp.h

@@ -1,356 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_acmp.h
-  * @brief   Header file of ACMP module driver.
-  *
-  * @version V1.0
-  * @date    13 Dec 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#ifndef __ALD_ACMP_H__
-#define __ALD_ACMP_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup ACMP
-  * @{
-  */
-
-/** @defgroup ACMP_Public_Types ACMP Public Types
-  * @{
-  */
-
-/**
-  * @brief Acmp interrupt
-  */
-typedef enum {
-	ACMP_IT_EDGE   = (1U << 0),	/**< Edge interrupt bit */
-	ACMP_IT_WARMUP = (1U << 1),	/**< Warm up interrupt bit */
-} acmp_it_t;
-
-/**
-  * @brief Acmp interrupt
-  */
-typedef enum {
-	ACMP_FLAG_EDGE   = (1U << 0),	/**< Edge interrupt flag */
-	ACMP_FLAG_WARMUP = (1U << 1),	/**< Warm up interrupt flag */	
-} acmp_flag_t;
-
-/**
-  * @brief Acmp interrupt flag
-  */
-typedef enum {
-	ACMP_STATUS_EDGE    = (1U << 0),	/**< Edge interrupt flag */
-	ACMP_STATUS_WARMUP  = (1U << 1),	/**< Warm up interrupt flag */
-} acmp_status_t;
-
-/**
-  * @brief Acmp positive input
-  */
-typedef enum {
-	ACMP_POS_CH0 = 0,	/**< Channel 0 as positive input */
-	ACMP_POS_CH1 = 1,	/**< Channel 1 as positive input */
-	ACMP_POS_CH2 = 2,	/**< Channel 2 as positive input */
-	ACMP_POS_CH3 = 3,	/**< Channel 3 as positive input */
-	ACMP_POS_CH4 = 4,	/**< Channel 4 as positive input */
-	ACMP_POS_CH5 = 5,	/**< Channel 5 as positive input */
-	ACMP_POS_CH6 = 6,	/**< Channel 6 as positive input */
-	ACMP_POS_CH7 = 7,	/**< Channel 7 as positive input */
-} acmp_pos_input_t;
-
-/**
-  * @brief Acmp negative input
-  */
-typedef enum {
-	ACMP_NEG_CH0      = 0, 	/**< Channel 0 as negative input */
-	ACMP_NEG_CH1      = 1, 	/**< Channel 1 as negative input */
-	ACMP_NEG_CH2      = 2, 	/**< Channel 2 as negative input */
-	ACMP_NEG_CH3      = 3, 	/**< Channel 3 as negative input */
-	ACMP_NEG_CH4      = 4, 	/**< Channel 4 as negative input */
-	ACMP_NEG_CH5      = 5, 	/**< Channel 5 as negative input */
-	ACMP_NEG_CH6      = 6, 	/**< Channel 6 as negative input */
-	ACMP_NEG_CH7      = 7, 	/**< Channel 7 as negative input */
-	ACMP_NEG_1V25     = 8, 	/**< 1.25v as negative input */
-	ACMP_NEG_2V5      = 9, 	/**< 2.5v as negative input */
-	ACMP_NEG_VDD      = 10,	/**< VDD as negative input */
-	ACMP_NEG_CAP      = 11,	/**< Capacitive as negative input */
-	ACMP_NEG_DAC0_CH0 = 12,	/**< DAC0 channel 0 as negative input */
-	ACMP_NEG_DAC0_CH1 = 13,	/**< DAC0 channel 1 as negative input */
-} acmp_neg_input_t;
-
-/**
-  * @brief Acmp mode
-  */
-typedef enum {
-	ACMP_ULTRA_LOW_POWER = 0,	/**< Ultra low power mode */
-	ACMP_LOW_POWER       = 1,	/**< Low power mode */
-	ACMP_MIDDLE_POWER    = 2,	/**< Middle power mode */
-	ACMP_HIGH_POWER      = 3,	/**< High power mode */
-} acmp_mode_t;
-
-/**
-  * @brief Acmp warm-up time
-  */
-typedef enum {
-	ACMP_4_PCLK   = 0,	/**< 4 hfperclk cycles */
-	ACMP_8_PCLK   = 1,	/**< 4 hfperclk cycles */
-	ACMP_16_PCLK  = 2,	/**< 4 hfperclk cycles */
-	ACMP_32_PCLK  = 3,	/**< 4 hfperclk cycles */
-	ACMP_64_PCLK  = 4,	/**< 4 hfperclk cycles */
-	ACMP_128_PCLK = 5,	/**< 4 hfperclk cycles */
-	ACMP_256_PCLK = 6,	/**< 4 hfperclk cycles */
-	ACMP_512_PCLK = 7,	/**< 4 hfperclk cycles */
-} acmp_warm_time_t;
-
-/**
-  * @brief Acmp hysteresis level
-  */
-typedef enum {
-	ACMP_HYST_0  = 0,	/**< No hysteresis */
-	ACMP_HYST_15 = 1,	/**< 15mV hysteresis */
-	ACMP_HYST_22 = 2,	/**< 22mV hysteresis */
-	ACMP_HYST_29 = 3,	/**< 29mV hysteresis */
-	ACMP_HYST_36 = 4,	/**< 36mV hysteresis */
-	ACMP_HYST_43 = 5,	/**< 43mV hysteresis */
-	ACMP_HYST_50 = 6,	/**< 50mV hysteresis */
-	ACMP_HYST_57 = 7,	/**< 57mV hysteresis */
-} acmp_hystsel_t;
-
-/**
-  * @brief Acmp inactive state
-  */
-typedef enum {
-	ACMP_INACTVAL_LOW  = 0,	/**< The inactive value is 0 */
-	ACMP_INACTVAL_HIGH = 1,	/**< The inactive value is 1 */
-} acmp_inactval_t;
-
-/**
-  * @brief which edges set up interrupt
-  */
-typedef enum {
-	ACMP_EDGE_NONE = 0,	/**< Disable EDGE interrupt */
-	ACMP_EDGE_FALL = 1,	/**< Falling edges set EDGE interrupt */
-	ACMP_EDGE_RISE = 2,	/**< rise edges set EDGE interrupt */
-	ACMP_EDGE_ALL  = 3,	/**< Falling edges and rise edges set EDGE interrupt */
-} acmp_edge_t;
-
-/**
-  * @brief Acmp output function
-  */
-typedef enum {
-	ACMP_OUT_DISABLE = 0,	/**< Disable acmp output */
-	ACMP_OUT_ENABLE  = 1,	/**< Enable acmp output */
-} acmp_out_func_t;
-
-/**
-  * @brief Acmp warm-up interrupt function
-  */
-typedef enum {
-	ACMP_WARM_DISABLE = 0,	/**< Disable acmp warm-up interrupt */
-	ACMP_WARM_ENABLE  = 1,	/**< Enable acmp warm-up interrupt */
-} acmp_warm_it_func;
-
-/**
-  * @brief Acmp gpio output invert
-  */
-typedef enum {
-	ACMP_GPIO_NO_INV = 0,	/**< Acmp output to gpio is not inverted */
-	ACMP_GPIO_INV    = 1,	/**< Acmp output to gpio is inverted */
-} acmp_invert_t;
-
-/**
-  * @brief The location of the acmp i/o pin
-  */
-typedef enum {
-	ACMP_LOCATION_O = 0,	/**< Location 0 */
-	ACMP_LOCATION_1 = 1,	/**< Location 1 */
-	ACMP_LOCATION_2 = 2,	/**< Location 2 */
-} acmp_location_t;
-
-/**
-  * @brief Acmp output config structure definition
-  */
-typedef struct {
-	acmp_out_func_t out_func;	/**< Acmp output function */
-	acmp_invert_t gpio_inv;   	/**< If invert gpio output */
-	acmp_location_t location;	/**< The location of acmp I/0 pin */
-} acmp_output_config_t;
-
-/**
-  * @brief Acmp init structure definition
-  */
-typedef struct {
-	acmp_mode_t mode;           	/**< Acmp operation mode */
-	acmp_warm_time_t warm_time; 	/**< Acmp warm up time */
-	acmp_hystsel_t hystsel;     	/**< Acmp hysteresis level */
-	acmp_warm_it_func warm_func;	/**< Acmp warm-up interrupt enable/disable */
-	acmp_pos_input_t pos_port;  	/**< Acmp positive port select */
-	acmp_neg_input_t neg_port;  	/**< Acmp negative port select */
-	acmp_inactval_t inactval;   	/**< Acmp inavtive output value */
-	acmp_edge_t edge;           	/** Select edges to set interrupt flag */
-	uint8_t vdd_level;          	/** Select scaling factor for CDD reference level, MAX is 63 */
-} acmp_init_t;
-
-/**
-  * @brief  ACMP Handle Structure definition
-  */
-typedef struct acmp_handle_s {
-	ACMP_TypeDef *perh;	/**< Register base address */
-	acmp_init_t init;  	/**< ACMP required parameters */
-	lock_state_t lock; 	/**< Locking object */
-
-	void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg);	/**< Acmp warm-up complete callback */
-	void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg);  	/**< Acmp edge trigger callback */
-} acmp_handle_t;
-/**
-  * @}
-  */
-
-/** @defgroup ACMP_Public_Macros ACMP Public Macros
-  * @{
-  */
-#define ACMP_ENABLE(handle) 	(SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
-#define ACMP_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup ACMP_Private_Macros   ACMP Private Macros
-  * @{
-  */
-#define IS_ACMP_TYPE(x) 		(((x) == ACMP0) || \
-				         ((x) == ACMP1))
-#define IS_ACMP_MODE_TYPE(x)		(((x) == ACMP_ULTRA_LOW_POWER) || \
-					 ((x) == ACMP_LOW_POWER)       || \
-					 ((x) == ACMP_MIDDLE_POWER)    || \
-					 ((x) == ACMP_HIGH_POWER))
-#define IS_ACMP_IT_TYPE(x) 		(((x) == ACMP_IT_EDGE)  || \
-				         ((x) == ACMP_IT_WARMUP))
-#define IS_ACMP_FLAG_TYPE(x) 		(((x) == ACMP_FLAG_EDGE)  || \
-				         ((x) == ACMP_FLAG_WARMUP))
-#define IS_ACMP_STATUS_TYPE(x) 	        (((x) == ACMP_STATUS_EDGE)  || \
-				         ((x) == ACMP_STATUS_WARMUP))
-#define IS_ACMP_POS_INPUT_TYPE(x) 	(((x) == ACMP_POS_CH0) || \
-				         ((x) == ACMP_POS_CH1) || \
-				         ((x) == ACMP_POS_CH2) || \
-				         ((x) == ACMP_POS_CH3) || \
-				         ((x) == ACMP_POS_CH4) || \
-				         ((x) == ACMP_POS_CH5) || \
-				         ((x) == ACMP_POS_CH6) || \
-				         ((x) == ACMP_POS_CH7))
-#define IS_ACMP_NEG_INPUT_TYPE(x) 	(((x) == ACMP_NEG_CH0)      || \
-				         ((x) == ACMP_NEG_CH1)      || \
-				         ((x) == ACMP_NEG_CH2)      || \
-				         ((x) == ACMP_NEG_CH3)      || \
-				         ((x) == ACMP_NEG_CH4)      || \
-				         ((x) == ACMP_NEG_CH5)      || \
-				         ((x) == ACMP_NEG_CH6)      || \
-				         ((x) == ACMP_NEG_CH7)      || \
-				         ((x) == ACMP_NEG_1V25)     || \
-				         ((x) == ACMP_NEG_2V5)      || \
-				         ((x) == ACMP_NEG_VDD)      || \
-				         ((x) == ACMP_NEG_CAP)      || \
-				         ((x) == ACMP_NEG_DAC0_CH0) || \
-				         ((x) == ACMP_NEG_DAC0_CH1))
-#define IS_ACMP_WARM_UP_TIME_TYPE(x)    (((x) == ACMP_4_PCLK)   || \
-				         ((x) == ACMP_8_PCLK)   || \
-				         ((x) == ACMP_16_PCLK)  || \
-				         ((x) == ACMP_32_PCLK)  || \
-				         ((x) == ACMP_64_PCLK)  || \
-				         ((x) == ACMP_128_PCLK) || \
-				         ((x) == ACMP_256_PCLK) || \
-				         ((x) == ACMP_512_PCLK))
-#define IS_ACMP_HYSTSEL_TYPE(x)         (((x) == ACMP_HYST_0)  || \
-				         ((x) == ACMP_HYST_15) || \
-				         ((x) == ACMP_HYST_22) || \
-				         ((x) == ACMP_HYST_29) || \
-				         ((x) == ACMP_HYST_36) || \
-				         ((x) == ACMP_HYST_43) || \
-				         ((x) == ACMP_HYST_50) || \
-				         ((x) == ACMP_HYST_57))
-#define IS_ACMP_INACTVAL_TYPE(x) 	(((x) == ACMP_INACTVAL_LOW) || \
-				         ((x) == ACMP_INACTVAL_HIGH))
-#define IS_ACMP_EDGE_TYPE(x) 	        (((x) == ACMP_EDGE_NONE) || \
-					 ((x) == ACMP_EDGE_FALL) || \
-				         ((x) == ACMP_EDGE_RISE) || \
-					 ((x) == ACMP_EDGE_ALL))
-#define IS_ACMP_OUT_FUNC_TYPE(x)	(((x) == ACMP_OUT_DISABLE) || \
-					 ((x) == ACMP_OUT_ENABLE))
-#define IS_ACMP_INVERT_TYPE(x)		(((x) == ACMP_GPIO_NO_INV) || \
-					 ((x) == ACMP_GPIO_INV))
-#define IS_ACMP_LOCATION_TYPE(x)	(((x) == ACMP_LOCATION_O) || \
-					 ((x) == ACMP_LOCATION_1) || \
-					 ((x) == ACMP_LOCATION_2))
-#define IS_ACMP_WARM_FUNC_TYPE(x)	(((x) == ACMP_WARM_DISABLE) || \
-					 ((x) == ACMP_WARM_ENABLE))
-/**
-  * @}
-  */
-
-/** @addtogroup ACMP_Public_Functions
-  * @{
-  */
-
-/** @addtogroup ACMP_Public_Functions_Group1
-  * @{
-  */
-ald_status_t acmp_init(acmp_handle_t *hperh);
-
-/**
-  * @}
-  */
-
-/** @addtogroup ACMP_Public_Functions_Group2
-  * @{
-  */
-ald_status_t acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state);
-ald_status_t acmp_set_interrupt_mask(acmp_handle_t *hperh, acmp_it_t it);
-it_status_t acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t it);
-ald_status_t acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t it);
-flag_status_t acmp_get_status(acmp_handle_t *hperh, acmp_status_t flag);
-
-/**
-  * @}
-  */
-
-/** @addtogroup ACMP_Public_Functions_Group3
-  * @{
-  */
-void acmp_irq_handle(acmp_handle_t *hperh);
-ald_status_t acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config);
-uint8_t acmp_out_result(acmp_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
- extern "C" }
-#endif
-
-#endif

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_adc.h

@@ -1,557 +0,0 @@
-/**
-  ******************************************************************************
- * @file    ald_adc.h
- * @brief   Header file of ADC Module library.
- *
- * @version V1.0
- * @date    15 Dec 2017
- * @author  AE Team
- * @note
- *
- * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
- *
- ******************************************************************************
- */
-
-#ifndef __ALD_ADC_H__
-#define __ALD_ADC_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-#include "ald_pis.h"
-#include "ald_timer.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup ADC
-  * @{
-  */
-
-/** @defgroup ADC_Pubulic_Types ADC Pubulic Types
-  * @{
-  */
-
-/**
-  * @brief ADC  State structures definition
-  */
-typedef enum {
-	ADC_STATE_RESET         = 0x0,    	/**< ADC not yet initialized or disabled */
-	ADC_STATE_READY         = 0x1,    	/**< ADC peripheral ready for use */
-	ADC_STATE_BUSY_INTERNAL = 0x2,    	/**< ADC is busy to internal process */
-	ADC_STATE_TIMEOUT       = 0x4,    	/**< TimeOut occurrence */
-	ADC_STATE_ERROR         = 0x10,   	/**< Internal error occurrence */
-	ADC_STATE_NM_BUSY       = 0x100,  	/**< Conversion on group normal is ongoing or can occur */
-	ADC_STATE_NM_EOC        = 0x200,  	/**< Conversion data available on group normal */
-	ADC_STATE_IST_BUSY      = 0x1000, 	/**< Conversion on group insert is ongoing or can occur */
-	ADC_STATE_IST_EOC       = 0x2000, 	/**< Conversion data available on group insert */
-	ADC_STATE_AWD           = 0x10000,	/**< Out-of-window occurrence of analog watchdog */
-} adc_state_t;
-
-/**
-  *@brief ADC Error Code
-  */
-typedef enum {
-	ADC_ERROR_NONE     = 0x0,	/**< No error */
-	ADC_ERROR_INTERNAL = 0x1,	/**< ADC IP internal error*/
-	ADC_ERROR_OVR      = 0x2,	/**< Overrun error */
-	ADC_ERROR_DMA      = 0x4, 	/**< DMA transfer error */
-} adc_error_t;
-
-/**
-  *@brief ADC data alignment
-  */
-typedef enum {
-	ADC_DATAALIGN_RIGHT = 0x0,	/**< ADC data alignment right */
-	ADC_DATAALIGN_LEFT  = 0x1,	/**< ADC data alignment left */
-} adc_align_t;
-
-/**
-  *@brief ADC scan mode
-  */
-typedef enum {
-	ADC_SCAN_DISABLE = 0x0,	/**< ADC scan disable */
-	ADC_SCAN_ENABLE  = 0x1,	/**< ADC scan enable */
-} adc_scan_t;
-
-/**
-  *@brief ADC config  hannal trigger the EOC IT mode
-  */
-typedef enum {
-	ADC_NCHESEL_MODE_ALL = 0x0,	/**< ADC set RCHE after convert sequence finish */
-	ADC_NCHESEL_MODE_ONE = 0x1,	/**< ADC set RCHE after one convert finish */
-} adc_nchesel_t;
-
-/**
-  *@brief  ADC channels
-  */
-typedef enum {
-	ADC_CHANNEL_0  = 0x0, 	/**< ADC channel 0 */
-	ADC_CHANNEL_1  = 0x1, 	/**< ADC channel 1 */
-	ADC_CHANNEL_2  = 0x2, 	/**< ADC channel 2 */
-	ADC_CHANNEL_3  = 0x3, 	/**< ADC channel 3 */
-	ADC_CHANNEL_4  = 0x4, 	/**< ADC channel 4 */
-	ADC_CHANNEL_5  = 0x5, 	/**< ADC channel 5 */
-	ADC_CHANNEL_6  = 0x6, 	/**< ADC channel 6 */
-	ADC_CHANNEL_7  = 0x7, 	/**< ADC channel 7 */
-	ADC_CHANNEL_8  = 0x8, 	/**< ADC channel 8 */
-	ADC_CHANNEL_9  = 0x9, 	/**< ADC channel 9 */
-	ADC_CHANNEL_10 = 0xA, 	/**< ADC channel 10 */
-	ADC_CHANNEL_11 = 0xB, 	/**< ADC channel 11 */
-	ADC_CHANNEL_12 = 0xC, 	/**< ADC channel 12 */
-	ADC_CHANNEL_13 = 0xD, 	/**< ADC channel 13 */
-	ADC_CHANNEL_14 = 0xE, 	/**< ADC channel 14 */
-	ADC_CHANNEL_15 = 0xF, 	/**< ADC channel 15 */
-	ADC_CHANNEL_16 = 0x10,	/**< ADC channel 16 */
-	ADC_CHANNEL_17 = 0x11,	/**< ADC channel 17 */
-	ADC_CHANNEL_18 = 0x12,	/**< ADC channel 18 */
-	ADC_CHANNEL_19 = 0x13,	/**< ADC channel 19 */
-} adc_channel_t;
-
-/**
-  *@brief  ADC sampling times
-  */
-typedef enum {
-	ADC_SAMPLETIME_1  = 0x0,	/**< ADC sampling times 1 clk */
-	ADC_SAMPLETIME_2  = 0x1,	/**< ADC sampling times 2 clk */
-	ADC_SAMPLETIME_4  = 0x2,	/**< ADC sampling times 4 clk */
-	ADC_SAMPLETIME_15 = 0x3,	/**< ADC sampling times 15 clk */
-} adc_samp_t;
-
-/**
-  *@brief   ADC rank into normal group
-  */
-typedef enum {
-	ADC_NC_RANK_1  = 0x1, 	/**< ADC normal channel rank 1 */
-	ADC_NC_RANK_2  = 0x2, 	/**< ADC normal channel rank 2 */
-	ADC_NC_RANK_3  = 0x3, 	/**< ADC normal channel rank 3 */
-	ADC_NC_RANK_4  = 0x4, 	/**< ADC normal channel rank 4 */
-	ADC_NC_RANK_5  = 0x5, 	/**< ADC normal channel rank 5 */
-	ADC_NC_RANK_6  = 0x6, 	/**< ADC normal channel rank 6 */
-	ADC_NC_RANK_7  = 0x7, 	/**< ADC normal channel rank 7 */
-	ADC_NC_RANK_8  = 0x8, 	/**< ADC normal channel rank 8 */
-	ADC_NC_RANK_9  = 0x9, 	/**< ADC normal channel rank 9 */
-	ADC_NC_RANK_10 = 0xA, 	/**< ADC normal channel rank 10 */
-	ADC_NC_RANK_11 = 0xB, 	/**< ADC normal channel rank 11 */
-	ADC_NC_RANK_12 = 0xC, 	/**< ADC normal channel rank 12 */
-	ADC_NC_RANK_13 = 0xD, 	/**< ADC normal channel rank 13 */
-	ADC_NC_RANK_14 = 0xE, 	/**< ADC normal channel rank 14 */
-	ADC_NC_RANK_15 = 0xF, 	/**< ADC normal channel rank 15 */
-	ADC_NC_RANK_16 = 0x10,	/**< ADC normal channel rank 16 */
-} adc_nc_rank_t;
-
-/**
-  * @brief ADC rank into insert group
-  */
-typedef enum {
-	ADC_IH_RANK_1 = 0x1,	/**< ADC insert channel rank 1 */
-	ADC_IH_RANK_2 = 0x2,	/**< ADC insert channel rank 2 */
-	ADC_IH_RANK_3 = 0x3,	/**< ADC insert channel rank 3 */
-	ADC_IH_RANK_4 = 0x4,	/**< ADC insert channel rank 4 */
-} adc_ih_rank_t;
-
-/**
-  * @brief ADC analog watchdog mode
-  */
-typedef enum {
-	ADC_ANAWTD_NONE       = 0x0,     	/**< No watch dog */
-	ADC_ANAWTD_SING_NM    = 0x800200,	/**< One normal channel watch dog */
-	ADC_ANAWTD_SING_IST   = 0x400200,	/**< One inset channel Injec watch dog */
-	ADC_ANAWTD_SING_NMIST = 0xC00200,	/**< One normal and inset channel watch dog */
-	ADC_ANAWTD_ALL_NM     = 0x800000,	/**< All normal channel watch dog */
-	ADC_ANAWTD_ALL_IST    = 0x400000,	/**< All inset channel watch dog */
-	ADC_ANAWTD_ALL_NMIST  = 0xC00000,	/**< All normal and inset channel watch dog */
-} adc_ana_wtd_t;
-
-/**
-  * @brief ADC Event type
-  */
-typedef enum {
-	ADC_AWD_EVENT = (1U << 0),	/**< ADC analog watch dog event */
-} adc_event_type_t;
-
-/**
-  * @brief ADC interrupts definition
-  */
-typedef enum {
-	ADC_IT_NH  = (1U << 5), 	/**< ADC it normal */
-	ADC_IT_AWD = (1U << 6), 	/**< ADC it awd */
-	ADC_IT_IH  = (1U << 7), 	/**< ADC it insert */
-	ADC_IT_OVR = (1U << 26),	/**< ADC it overring */
-} adc_it_t;
-
-/**
-  * @brief ADC flags definition
-  */
-typedef enum {
-	ADC_FLAG_AWD = (1U << 0),	/**<ADC flag awd */
-	ADC_FLAG_NH  = (1U << 1),	/**<ADC flag normal mode */
-	ADC_FLAG_IH  = (1U << 2),	/**<ADC flag inset mode */
-	ADC_FLAG_OVR = (1U << 3),	/**<ADC flag ovr */
-	ADC_FLAG_NHS = (1U << 8),	/**<ADC flag normal start */
-	ADC_FLAG_IHS = (1U << 9),	/**<ADC flag inset start */
-} adc_flag_t;
-
-/**
-  * @brief ADC CLD DIV definition
-  */
-typedef enum {
-	ADC_CKDIV_1   = 0x0,	/**< ADC CLK DIV 1 */
-	ADC_CKDIV_2   = 0x1,	/**< ADC CLK DIV 2 */
-	ADC_CKDIV_4   = 0x2,	/**< ADC CLK DIV 4 */
-	ADC_CKDIV_8   = 0x3,	/**< ADC CLK DIV 8 */
-	ADC_CKDIV_16  = 0x4,	/**< ADC CLK DIV 16 */
-	ADC_CKDIV_32  = 0x5,	/**< ADC CLK DIV 32 */
-	ADC_CKDIV_64  = 0x6,	/**< ADC CLK DIV 64 */
-	ADC_CKDIV_128 = 0x7,	/**< ADC CLK DIV 128 */
-} adc_clk_div_t;
-
-/**
-  * @brief ADC negative reference voltage definition
-  */
-typedef enum {
-	ADC_NEG_REF_VSS   = 0x0,	/**< ADC negative regerence voltage vss */
-	ADC_NEG_REF_VREFN = 0x1,	/**< ADC negative regerence voltage vrefn */
-} adc_neg_ref_t;
-
-/**
-  * @brief ADC positive reference voltage definition
-  */
-typedef enum {
-	ADC_POS_REF_VDD        = 0x0,	/**< ADC posotove reference is VDD */
-	ADC_POS_REF_2V         = 0x1,	/**< ADC posotove reference is internal 2V */
-	ADC_POS_REF_VREEFP     = 0x2,	/**< ADC posotove reference is VREEFP */
-	ADC_POS_REF_VREEFP_BUF = 0x3,	/**< ADC posotove reference is VREEFP BUFFER */
-} adc_pos_ref_t;
-
-/**
-  * @brief ADC numbers of normal conversion channals
-  */
-typedef enum {
-	ADC_NM_NBR_1  = 0x0,	/**< ADC number of normal conversion 1 */
-	ADC_NM_NBR_2  = 0x1,	/**< ADC number of normal conversion 2 */
-	ADC_NM_NBR_3  = 0x2,	/**< ADC number of normal conversion 3 */
-	ADC_NM_NBR_4  = 0x3,	/**< ADC number of normal conversion 4 */
-	ADC_NM_NBR_5  = 0x4,	/**< ADC number of normal conversion 5 */
-	ADC_NM_NBR_6  = 0x5,	/**< ADC number of normal conversion 6 */
-	ADC_NM_NBR_7  = 0x6,	/**< ADC number of normal conversion 7 */
-	ADC_NM_NBR_8  = 0x7,	/**< ADC number of normal conversion 8 */
-	ADC_NM_NBR_9  = 0x8,	/**< ADC number of normal conversion 9 */
-	ADC_NM_NBR_10 = 0x9,	/**< ADC number of normal conversion 10 */
-	ADC_NM_NBR_11 = 0xA,	/**< ADC number of normal conversion 11 */
-	ADC_NM_NBR_12 = 0xB,	/**< ADC number of normal conversion 12 */
-	ADC_NM_NBR_13 = 0xC,	/**< ADC number of normal conversion 13 */
-	ADC_NM_NBR_14 = 0xD,	/**< ADC number of normal conversion 14 */
-	ADC_NM_NBR_15 = 0xE,	/**< ADC number of normal conversion 15 */
-	ADC_NM_NBR_16 = 0xF,	/**< ADC number of normal conversion 16 */
-} adc_nm_nbr_t;
-
-/**
-  * @brief ADC numbers of insert conversion channals
-  */
-typedef enum {
-	ADC_IST_NBR_1 = 0x0,	/**< ADC number of insert conversion 1 */
-	ADC_IST_NBR_2 = 0x1,	/**< ADC number of insert conversion 2 */
-	ADC_IST_NBR_3 = 0x2,	/**< ADC number of insert conversion 3 */
-	ADC_IST_NBR_4 = 0x3,	/**< ADC number of insert conversion 4 */
-} adc_ist_nbr_t;
-
-/**
-  * @brief ADC numbers of channals in discontinuous conversion mode
-  */
-typedef enum {
-	ADC_DISC_NBR_1 = 0x0,	/**< ADC number of discontinuous conversion 1 */
-	ADC_DISC_NBR_2 = 0x1,	/**< ADC number of discontinuous conversion 2 */
-	ADC_DISC_NBR_3 = 0x2,	/**< ADC number of discontinuous conversion 3 */
-	ADC_DISC_NBR_4 = 0x3,	/**< ADC number of discontinuous conversion 4 */
-	ADC_DISC_NBR_5 = 0x4,	/**< ADC number of discontinuous conversion 5 */
-	ADC_DISC_NBR_6 = 0x5,	/**< ADC number of discontinuous conversion 6 */
-	ADC_DISC_NBR_7 = 0x6,	/**< ADC number of discontinuous conversion 7 */
-	ADC_DISC_NBR_8 = 0x7,	/**< ADC number of discontinuous conversion 8 */
-} adc_disc_nbr_t;
-
-/**
-  * @brief ADC resolution of conversion
-  */
-typedef enum {
-	ADC_CONV_RES_6  = 0x0,	/**< ADC resolution of conversion 6 */
-	ADC_CONV_RES_8  = 0x1,	/**< ADC resolution of conversion 8 */
-	ADC_CONV_RES_10 = 0x2,	/**< ADC resolution of conversion 10 */
-	ADC_CONV_RES_12 = 0x3,	/**< ADC resolution of conversion 12 */
-} adc_conv_res_t;
-
-/**
-  * @brief ADC trigger conversion mode
-  */
-typedef enum {
-	ADC_TRIG_SOFT     = 0x0,	/**< ADC tirgger conversion soft */
-	ADC_TRIG_PIS      = 0x1,	/**< ADC tirgger conversion pis */
-	ADC_TRIG_PIS_SOFT = 0x2,	/**< ADC tirgger conversion all */
-} adc_trig_mode_t;
-
-/**
-  * @brief  Structure definition of ADC and normal group initialization
-  */
-typedef struct {
-	adc_align_t data_align;		/**< Specifies ADC data alignment */
-	adc_scan_t scan_mode;         	/**< Choose scan mode enable or not */
-	type_func_t cont_mode;       	/**< Choose continuous mode enable or not */
-	adc_nm_nbr_t conv_nbr;  	/**< Number of normal ranks will be converted */
-	type_func_t disc_mode;    	/**< Discontinuous mode enable or not */
-	adc_disc_nbr_t disc_nbr;	/**< Number of discontinuous conversions channel */
-	adc_conv_res_t conv_res;   	/**< The precision of conversion */
-	adc_clk_div_t clk_div;		/**< ADCCLK divider */
-	adc_nchesel_t nche_mode;	/**< Trigger the NCHE FALG mode */
-	adc_neg_ref_t neg_ref;    	/**< The negative reference voltage*/
-	adc_pos_ref_t pos_ref;    	/**< The positive reference voltage*/
-} adc_init_t;
-
-/**
-  * @brief  Structure definition of ADC channel for normal group
-  */
-typedef struct {
-	adc_channel_t channel;        	/**< The channel to configure into ADC normal group */
-	adc_nc_rank_t rank;       	/**< The rank in the normal group sequencer */
-	adc_samp_t sampling_time;	/**< Sampling time value to be set */
-} adc_channel_conf_t;
-
-/**
-  * @brief  ADC Configuration analog watchdog definition
-  */
-typedef struct {
-	adc_ana_wtd_t watchdog_mode;		/**< Configures the ADC analog watchdog mode*/
-	adc_channel_t channel;			/**< Selects which ADC channel to monitor by analog watchdog */
-	type_func_t it_mode;             	/**< Whether the analog watchdog is configured in interrupt */
-	uint32_t high_threshold;     	 	/**< The ADC analog watchdog High threshold value. */
-	uint32_t low_threshold;      	 	/**< The ADC analog watchdog Low threshold value. */
-} adc_analog_wdg_conf_t;
-
-/**
-  * @brief  ADC Configuration insert Channel structure definition
-  */
-typedef struct {
-	adc_channel_t channel;	/**< Selection of ADC channel to configure */
-	adc_ih_rank_t rank;	/**< Rank in the insert group sequencer */
-	adc_samp_t samp_time;	/**< Sampling time value for selected channel */
-	uint32_t offset;	/**< The offset about converted data */
-	adc_ist_nbr_t nbr;	/**< The number of insert ranks */
-	type_func_t disc_mode;	/**< insert sequence's Discontinuous function */
-	type_func_t auto_inj;	/**< insert sequence's auto function */
-} adc_ih_conf_t;
-
-/**
-  * @brief  ADC handle Structure definition
-  */
-typedef struct adc_handle_s {
-	ADC_TypeDef *perh;			/**< Register base address */
-	adc_init_t init;			/**< ADC required parameters */
-#ifdef ALD_DMA
-	dma_handle_t hdma;			/**< Pointer DMA Handler */
-	pis_handle_t hpis;			/**< Pointer PIS Handler for connect adc and dma */
-#endif
-	lock_state_t lock;			/**< ADC locking object */
-	adc_state_t state;			/**< ADC communication state  */
-	adc_error_t error_code;			/**< ADC Error code */
-	pis_handle_t reg_pis_handle;		/**< PIS for connect normal channel and trigger */
-	pis_handle_t inj_pis_handle;		/**< PIS for connect insert channel and trigger */
-	adc_trig_mode_t nm_trig_mode;		/**< ADC normal channel trigger mode */
-	adc_trig_mode_t ist_trig_mode;		/**< ADC insert channel trigger mode */
-
-	void (*adc_reg_cplt_cbk)( struct adc_handle_s *arg);  	/**< Regluar Conversion complete callback */
-	void (*adc_inj_cplt_cbk)( struct adc_handle_s *arg);  	/**< insert Conversion complete callback */
-	void (*adc_out_of_win_cbk)( struct adc_handle_s *arg);	/**< Level out of window callback */
-	void (*adc_error_cbk)(struct adc_handle_s *arg);      	/**< adc error callback */
-	void (*adc_ovr_cbk)(struct adc_handle_s *arg);	      	/**< adc ovr callback */
-} adc_handle_t;
-
-/**
-  * @brief Timer trigger adc config structure definition
-  */
-typedef struct {
-	uint32_t time;						/**< Timer period time uint: us */	
-	uint16_t size;						/**< Adc convert times */	
-	uint16_t *buf;						/**< Convert data buffer */	
-	adc_neg_ref_t n_ref;					/**< The negative reference voltage for adc*/
-	adc_pos_ref_t p_ref;					/**< The positive reference voltage for adc*/
-	adc_channel_t adc_ch;					/**< Adc channel */	
-	uint8_t dma_ch;						/**< Dma channel */	
-	TIMER_TypeDef *p_timer;					/**< Adc peripheral */	
-	ADC_TypeDef *p_adc;					/**< Dma peripheral */	
-	void (*adc_cplt_cbk)( struct adc_handle_s *arg);	/**< Conversion complete callback */
-	
-	/* private variable */
-	lock_state_t lock;		/**< Locking object */
-	pis_handle_t lh_pis;		/**< Handle of PIS module */
-	dma_handle_t lh_dma;		/**< Handle of DMA module */
-	timer_handle_t lh_timer;	/**< Handle of TIMER module */
-	adc_handle_t lh_adc;		/**< Handle of ADC module */
-	adc_channel_conf_t lnm_config;	/**< Struct for chanel configure */
-} adc_timer_config_t;
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Public_Macros ADC Public Macros
-  * @{
-  */
-#define ADC_ENABLE(handle) 			(SET_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK))
-#define ADC_DISABLE(handle) 			(CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK))
-#define ADC_NH_TRIG_BY_SOFT(handle)		(SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK))
-#define ADC_IH_TRIG_BY_SOFT(handle)		(SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK))
-#define ADC_RESET_HANDLE_STATE(handle)		((handle)->state = ADC_STATE_RESET)
-#define ADC_VREF_OUT_ENABLE(handle)		(SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))
-#define ADC_VREF_OUT_DISABLE(handle)		(CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Private_Macros ADC Private Macros
-  * @{
-  */
-#define IS_ADC_IH_RANK_TYPE(x)			((x) <= ADC_IH_RANK_4)
-#define IS_ADC_NC_RANK_TYPE(x)			((x) <= ADC_NC_RANK_16)
-#define IS_ADC_SAMPLING_TIMES_TYPE(x)		(((x) == ADC_SAMPLETIME_1) || \
-                                                 ((x) == ADC_SAMPLETIME_2) || \
-					         ((x) == ADC_SAMPLETIME_4) || \
-					         ((x) == ADC_SAMPLETIME_15))
-#define IS_ADC_CHANNELS_TYPE(x)			((x) <= ADC_CHANNEL_19)
-#define IS_ADC_SCAN_MODE_TYPE(x)		(((x) == ADC_SCAN_DISABLE) || \
-                                                 ((x) ==  ADC_SCAN_ENABLE) )
-#define IS_ADC_DATA_ALIGN_TYPE(x)		(((x) == ADC_DATAALIGN_RIGHT) || \
-                                                 ((x) == ADC_DATAALIGN_LEFT))
-#define IS_ADC_ANALOG_WTD_MODE_TYPE(x)  	(((x) == ADC_ANAWTD_NONE)       || \
-						 ((x) == ADC_ANAWTD_SING_NM)    || \
-						 ((x) == ADC_ANAWTD_SING_IST)   || \
-						 ((x) == ADC_ANAWTD_SING_NMIST) || \
-						 ((x) == ADC_ANAWTD_ALL_NM)     || \
-						 ((x) == ADC_ANAWTD_ALL_IST)    || \
-						 ((x) == ADC_ANAWTD_ALL_NMIST))
-#define IS_ADC_IT_TYPE(x)			(((x) == ADC_IT_NH) || \
-						 ((x) == ADC_IT_AWD)  || \
-						 ((x) == ADC_IT_IH) ||  \
-						 ((x) == ADC_IT_OVR ))
-#define IS_ADC_FLAGS_TYPE(x)			(((x) == ADC_FLAG_AWD)   || \
-						 ((x) == ADC_FLAG_NH)  || \
-						 ((x) == ADC_FLAG_IH)  || \
-						 ((x) == ADC_FLAG_OVR)   || \
-						 ((x) == ADC_FLAG_NHS) || \
-						 ((x) == ADC_FLAG_IHS))
-#define IS_ADC_CLK_DIV_TYPE(x)			(((x) == ADC_CKDIV_1)   || \
-						 ((x) == ADC_CKDIV_2)   || \
-						 ((x) == ADC_CKDIV_4)   || \
-						 ((x) == ADC_CKDIV_8)   || \
-						 ((x) == ADC_CKDIV_16)  || \
-						 ((x) == ADC_CKDIV_32)  || \
-						 ((x) == ADC_CKDIV_64)  || \
-						 ((x) == ADC_CKDIV_128))
-#define IS_ADC_NEG_REF_VOLTAGE_TYPE(x)		(((x) == ADC_NEG_REF_VSS ) || \
-                                                 ((x) == ADC_NEG_REF_VREFN ))
-#define IS_POS_REF_VOLTAGE_TYPE(x)		(((x) == ADC_POS_REF_VDD)    || \
-						 ((x) == ADC_POS_REF_2V)     || \
-						 ((x) == ADC_POS_REF_VREEFP) || \
-						 ((x) == ADC_POS_REF_VREEFP_BUF))
-#define IS_ADC_NBR_OF_NM_TYPE(x)		((x) <= ADC_NM_NBR_16)
-#define IS_ADC_NBR_OF_IST_TYPE(x)		((x) <= ADC_IST_NBR_4)
-#define IS_ADC_DISC_NBR_TYPE(x)			((x) <= ADC_DISC_NBR_8)
-#define IS_ADC_CONV_RES_TYPE(x)			(((x) == ADC_CONV_RES_12) || \
-                                                 ((x) == ADC_CONV_RES_6)  || \
-						 ((x) == ADC_CONV_RES_8)  || \
-						 ((x) == ADC_CONV_RES_10))
-#define IS_ADC_TRIG_MODE_TYPE(x)		(((x) == ADC_TRIG_SOFT) || \
-                                                 ((x) == ADC_TRIG_PIS)  || \
-                                                 ((x) == ADC_TRIG_PIS_SOFT))
-#define IS_ADC_TYPE(x) 				(((x) == ADC0) || \
-						 ((x) == ADC1))
-#define IS_ADC_NCHESEL_MODE_TYPE(x)		(((x) == ADC_NCHESEL_MODE_ALL) || \
-						 ((x) == ADC_NCHESEL_MODE_ONE))
-#define IS_ADC_EVENT_TYPE(x)			((x) == ADC_AWD_EVENT)
-#define IS_ADC_IST_OFFSET_TYPE(x)		((x) <= 0xfff)
-#define IS_HTR_TYPE(x)				((x) <= 0xfff)
-#define IS_LTR_TYPE(x)				((x) <= 0xfff)
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Public_Functions
-  * @{
-  */
-
-/** @addtogroup ADC_Public_Functions_Group1
-  * @{
-  */
-ald_status_t adc_init(adc_handle_t *hperh);
-ald_status_t adc_reset(adc_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Public_Functions_Group2
-  * @{
-  */
-ald_status_t adc_normal_start(adc_handle_t *hperh);
-ald_status_t adc_normal_stop(adc_handle_t *hperh);
-ald_status_t adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout);
-ald_status_t adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout);
-ald_status_t adc_normal_start_by_it(adc_handle_t *hperh);
-ald_status_t adc_normal_stop_by_it(adc_handle_t *hperh);
-#ifdef ALD_DMA
-ald_status_t adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel);
-ald_status_t adc_stop_by_dma(adc_handle_t *hperh);
-ald_status_t adc_timer_trigger_adc_by_dma(adc_timer_config_t *config);
-#endif
-uint32_t adc_normal_get_value(adc_handle_t *hperh);
-ald_status_t adc_insert_start(adc_handle_t *hperh);
-ald_status_t adc_insert_stop(adc_handle_t *hperh);
-ald_status_t adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout);
-ald_status_t adc_insert_start_by_it(adc_handle_t *hperh);
-ald_status_t adc_insert_stop_by_it(adc_handle_t *hperh);
-uint32_t adc_insert_get_value(adc_handle_t *hperh, adc_ih_rank_t ih_rank);
-void adc_irq_handler(adc_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Public_Functions_Group3
-  * @{
-  */
-ald_status_t adc_normal_channel_config(adc_handle_t *hperh, adc_channel_conf_t *config);
-ald_status_t adc_insert_channel_config(adc_handle_t *hperh, adc_ih_conf_t *config);
-ald_status_t adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config);
-void adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state);
-it_status_t adc_get_it_status(adc_handle_t *hperh, adc_it_t it);
-flag_status_t adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag);
-void adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag);
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Public_Functions_Group4
-  * @{
-  */
-uint32_t adc_get_state(adc_handle_t *hperh);
-uint32_t adc_get_error(adc_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
- extern "C" }
-#endif
-
-#endif /* __ALD_ADC_H */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_bkpc.h

@@ -1,184 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_bkpc.h
-  * @brief   Header file of BKPC module driver.
-  *
-  * @version V1.0
-  * @date    15 Dec 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  ********************************************************************************
-  */
-
-#ifndef __ALD_BKPC_H__
-#define __ALD_BKPC_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup BKPC
-  * @{
-  */
-
-/** @defgroup BKPC_Public_Macros BKPC Public Macros
-  * @{
-  */
-#define BKPC_LOCK()		(WRITE_REG(BKPC->PROT, 0))
-#define BKPC_UNLOCK()		(WRITE_REG(BKPC->PROT, 0x9669AA55))
-#define BKPC_LRC_ENABLE()			\
-do {						\
-	BKPC_UNLOCK();				\
-	SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);	\
-	BKPC_LOCK();				\
-} while (0)
-#define BKPC_LRC_DISABLE()			\
-do {						\
-	BKPC_UNLOCK();				\
-	CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);	\
-	BKPC_LOCK();				\
-} while (0)
-#define BKPC_LOSM_ENABLE()			\
-do {						\
-	BKPC_UNLOCK();				\
-	SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);	\
-	BKPC_LOCK();				\
-} while (0)
-#define BKPC_LOSM_DISABLE()			\
-do {						\
-	BKPC_UNLOCK();				\
-	CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\
-	BKPC_LOCK();				\
-} while (0)
-#define BKPC_LOSC_ENABLE()			\
-do {						\
-	BKPC_UNLOCK();				\
-	SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);	\
-	BKPC_LOCK();				\
-} while (0)
-#define BKPC_LOSC_DISABLE()			\
-do {						\
-	BKPC_UNLOCK();				\
-	CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\
-	BKPC_LOCK();				\
-} while (0)
-/**
-  * @}
-  */
-
-/** @defgroup BKPC_Public_Types BKPC Public Types
-  * @{
-  */
-/**
-  * @brief BKPC ldo output select
-  */
-typedef enum {
-	BKPC_LDO_OUTPUT_1_6 = 0x0,	/**< 1.6V */
-	BKPC_LDO_OUTPUT_1_3 = 0x1,	/**< 1.3V */
-	BKPC_LDO_OUTPUT_1_4 = 0x2,	/**< 1.4V */
-	BKPC_LDO_OUTPUT_1_5 = 0x4,	/**< 1.5V */
-} bkpc_ldo_output_t;
-
-/**
-  * @brief BKPC BOR voltage select
-  */
-typedef enum {
-	BKPC_BOR_VOL_1_7  = 0x0,	/**< 1.7V */
-	BKPC_BOR_VOL_2_0  = 0x1,	/**< 2.0V */
-	BKPC_BOR_VOL_2_1  = 0x2,	/**< 2.1V */
-	BKPC_BOR_VOL_2_2  = 0x3,	/**< 2.2V */
-	BKPC_BOR_VOL_2_3  = 0x4,	/**< 2.3V */
-	BKPC_BOR_VOL_2_4  = 0x5,	/**< 2.4V */
-	BKPC_BOR_VOL_2_5  = 0x6,	/**< 2.5V */
-	BKPC_BOR_VOL_2_6  = 0x7,	/**< 2.6V */
-	BKPC_BOR_VOL_2_8  = 0x8,	/**< 2.8V */
-	BKPC_BOR_VOL_3_0  = 0x9,	/**< 3.0V */
-	BKPC_BOR_VOL_3_1  = 0xA,	/**< 3.1V */
-	BKPC_BOR_VOL_3_3  = 0xB,	/**< 3.3V */
-	BKPC_BOR_VOL_3_6  = 0xC,	/**< 3.6V */
-	BKPC_BOR_VOL_3_7  = 0xD,	/**< 3.7V */
-	BKPC_BOR_VOL_4_0  = 0xE,	/**< 4.0V */
-	BKPC_BOR_VOL_4_3  = 0xF,	/**< 4.3V */
-} bkpc_bor_vol_t;
-
-/**
-  * @}
-  */
-
-/**
-  * @defgroup BKPC_Private_Macros BKPC Private Macros
-  * @{
-  */
-#define IS_BKPC_LDO_OUTPUT(x)	(((x) == BKPC_LDO_OUTPUT_1_6) || \
-                                 ((x) == BKPC_LDO_OUTPUT_1_3) || \
-                                 ((x) == BKPC_LDO_OUTPUT_1_4) || \
-                                 ((x) == BKPC_LDO_OUTPUT_1_5))
-#define IS_BKPC_BOR_VOL(x)	(((x) == BKPC_BOR_VOL_1_7) || \
-                                 ((x) == BKPC_BOR_VOL_2_0) || \
-                                 ((x) == BKPC_BOR_VOL_2_1) || \
-                                 ((x) == BKPC_BOR_VOL_2_2) || \
-                                 ((x) == BKPC_BOR_VOL_2_3) || \
-                                 ((x) == BKPC_BOR_VOL_2_4) || \
-                                 ((x) == BKPC_BOR_VOL_2_5) || \
-                                 ((x) == BKPC_BOR_VOL_2_6) || \
-                                 ((x) == BKPC_BOR_VOL_2_8) || \
-                                 ((x) == BKPC_BOR_VOL_3_0) || \
-                                 ((x) == BKPC_BOR_VOL_3_1) || \
-                                 ((x) == BKPC_BOR_VOL_3_3) || \
-                                 ((x) == BKPC_BOR_VOL_3_6) || \
-                                 ((x) == BKPC_BOR_VOL_3_7) || \
-                                 ((x) == BKPC_BOR_VOL_4_0) || \
-                                 ((x) == BKPC_BOR_VOL_4_3))
-#define IS_BKPC_RAM_IDX(x)	((x) < 32)
-/**
-  * @}
-  */
-
-/** @addtogroup BKPC_Public_Functions
-  * @{
-  */
-/** @addtogroup BKPC_Public_Functions_Group1
-  * @{
-  */
-/* control functions */
-extern void bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state);
-extern void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state);
-/**
-  * @}
-  */
-/** @addtogroup BKPC_Public_Functions_Group2
-  * @{
-  */
-/* IO operation functions */
-extern void bkpc_write_ram(uint8_t idx, uint32_t value);
-extern uint32_t bkpc_read_ram(uint8_t idx);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_BKPC_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_cmu.h

@@ -1,615 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_cmu.h
-  * @brief   Header file of CMU module driver.
-  *
-  * @version V1.0
-  * @date    22 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  ********************************************************************************
-  */
-
-#ifndef __ALD_CMU_H__
-#define __ALD_CMU_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_syscfg.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup CMU
-  * @{
-  */
-
-/** @defgroup CMU_Public_Macros CMU Public Macros
-  * @{
-  */
-#define CMU_LOSC_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LOSC_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LRC_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LRC_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_ULRC_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_ULRC_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-
-/* Low power mode control */
-#define CMU_LP_LRC_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LP_LRC_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LP_LOSC_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LP_LOSC_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LP_HRC_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LP_HRC_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LP_HOSC_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LP_HOSC_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-/**
-  * @}
-  */
-
-
-/** @defgroup CMU_Public_Types CMU Public Types
-  * @{
-  */
-/**
-  * @brief CMU state structure definition
-  */
-typedef	enum {
-	CMU_CLOCK_HRC  = 0x1,	/**< HRC */
-	CMU_CLOCK_LRC  = 0x2,	/**< LRC */
-	CMU_CLOCK_LOSC = 0x3,	/**< LOSC */
-	CMU_CLOCK_PLL1 = 0x4,	/**< PLL1 */
-	CMU_CLOCK_HOSC = 0x5,	/**< HOSC */
-} cmu_clock_t;
-
-/**
-  * @brief PLL1 output clock
-  */
-typedef enum {
-	CMU_PLL1_OUTPUT_32M = 0x0,	/**< x8  (32MHz) */
-	CMU_PLL1_OUTPUT_48M = 0x1,	/**< x12 (48MHz) */
-} cmu_pll1_output_t;
-
-/**
-  * @brief PLL1 referance clock
-  */
-typedef enum {
-	CMU_PLL1_INPUT_HRC_6  = 0x0,	/**< HRC  / 6 */
-	CMU_PLL1_INPUT_PLL2   = 0x1,	/**< PLL2 */
-	CMU_PLL1_INPUT_HOSC   = 0x2,	/**< HOSC / 1 */
-	CMU_PLL1_INPUT_HOSC_2 = 0x3,	/**< HOSC / 2 */
-	CMU_PLL1_INPUT_HOSC_3 = 0x4,	/**< HOSC / 3 */
-	CMU_PLL1_INPUT_HOSC_4 = 0x5,	/**< HOSC / 4 */
-	CMU_PLL1_INPUT_HOSC_5 = 0x6,	/**< HOSC / 5 */
-	CMU_PLL1_INPUT_HOSC_6 = 0x7,	/**< HOSC / 6 */
-} cmu_pll1_input_t;
-
-/**
-  * @brief HOSC range
-  */
-typedef enum {
-	CMU_HOSC_2M  = 0x0,
-	CMU_HOSC_4M  = 0x1,
-	CMU_HOSC_8M  = 0x2,
-	CMU_HOSC_16M = 0x3,
-	CMU_HOSC_24M = 0x4,
-} cmu_hosc_range_t;
-
-/**
-  * @brief Auto-calibrate input
-  */
-typedef enum {
-	CMU_AUTO_CALIB_INPUT_LOSE = 0x0,
-	CMU_AUTO_CALIB_INPUT_HOSE = 0x1,
-} cmu_auto_calib_input_t;
-
-/**
-  * @brief Auto-calibrate output
-  */
-typedef enum {
-	CMU_AUTO_CALIB_OUTPUT_24M = 0x0,
-	CMU_AUTO_CALIB_OUTPUT_2M  = 0x1,
-} cmu_auto_calib_output_t;
-
-/**
-  * @brief Frequency division select bit
-  */
-typedef enum {
-	CMU_DIV_1    = 0x0,		/**< Division by 1 */
-	CMU_DIV_2    = 0x1,		/**< Division by 2 */
-	CMU_DIV_4    = 0x2,		/**< Division by 4 */
-	CMU_DIV_8    = 0x3,		/**< Division by 8 */
-	CMU_DIV_16   = 0x4,		/**< Division by 16 */
-	CMU_DIV_32   = 0x5,		/**< Division by 32 */
-	CMU_DIV_64   = 0x6,		/**< Division by 64 */
-	CMU_DIV_128  = 0x7,		/**< Division by 128 */
-	CMU_DIV_256  = 0x8,		/**< Division by 256 */
-	CMU_DIV_512  = 0x9,		/**< Division by 512 */
-	CMU_DIV_1024 = 0xA,		/**< Division by 1024 */
-	CMU_DIV_2048 = 0xB,		/**< Division by 2048 */
-	CMU_DIV_4096 = 0xC,		/**< Division by 4096 */
-} cmu_div_t;
-
-/**
-  * @brief Bus type
-  */
-typedef enum {
-	CMU_HCLK_1 = 0x0,		/**< AHB1 bus */
-	CMU_SYS    = 0x1,		/**< SYS bus */
-	CMU_PCLK_1 = 0x2,		/**< APB1 bus */
-	CMU_PCLK_2 = 0x3,		/**< APB2 bus */
-} cmu_bus_t;
-
-/**
-  * @brief Output high clock select
-  */
-typedef enum {
-	CMU_OUTPUT_HIGH_SEL_HOSC   = 0x0,	/**< Select HOSC */
-	CMU_OUTPUT_HIGH_SEL_LOSC   = 0x1,	/**< Select LOSC */
-	CMU_OUTPUT_HIGH_SEL_HRC    = 0x2,	/**< Select HRC */
-	CMU_OUTPUT_HIGH_SEL_LRC    = 0x3,	/**< Select LRC */
-	CMU_OUTPUT_HIGH_SEL_HOSM   = 0x4,	/**< Select HOSM */
-	CMU_OUTPUT_HIGH_SEL_PLL1   = 0x5,	/**< Select PLL1 */
-	CMU_OUTPUT_HIGH_SEL_PLL2   = 0x6,	/**< Select PLL2 */
-	CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7,	/**< Select SYSCLK */
-} cmu_output_high_sel_t;
-
-/**
-  * @brief Output frequency division
-  */
-typedef enum {
-	CMU_OUTPUT_DIV_1   = 0x0,	/**< Division by 1 */
-	CMU_OUTPUT_DIV_2   = 0x1,	/**< Division by 2 */
-	CMU_OUTPUT_DIV_4   = 0x2,	/**< Division by 4 */
-	CMU_OUTPUT_DIV_8   = 0x3,	/**< Division by 8 */
-	CMU_OUTPUT_DIV_16  = 0x4,	/**< Division by 16 */
-	CMU_OUTPUT_DIV_32  = 0x5,	/**< Division by 32 */
-	CMU_OUTPUT_DIV_64  = 0x6,	/**< Division by 64 */
-	CMU_OUTPUT_DIV_128 = 0x7,	/**< Division by 128 */
-} cmu_output_high_div_t;
-
-/**
-  * @brief Output low clock select
-  */
-typedef enum {
-	CMU_OUTPUT_LOW_SEL_LOSC = 0x0,	/**< Select LOSC */
-	CMU_OUTPUT_LOW_SEL_LRC  = 0x1,	/**< Select LRC */
-	CMU_OUTPUT_LOW_SEL_LOSM = 0x2,	/**< Select LOSM */
-	CMU_OUTPUT_LOW_SEL_BUZZ = 0x3,	/**< Select BUZZ */
-	CMU_OUTPUT_LOW_SEL_ULRC = 0x4,	/**< Select ULRC */
-} cmu_output_low_sel_t;
-
-/**
-  * @brief BUZZ frequency division
-  */
-typedef enum {
-	CMU_BUZZ_DIV_2   = 0x0,		/**< Division by 2 */
-	CMU_BUZZ_DIV_4   = 0x1,		/**< Division by 4 */
-	CMU_BUZZ_DIV_8   = 0x2,		/**< Division by 8 */
-	CMU_BUZZ_DIV_16  = 0x3,		/**< Division by 16 */
-	CMU_BUZZ_DIV_32  = 0x4,		/**< Division by 32 */
-	CMU_BUZZ_DIV_64  = 0x5,		/**< Division by 64 */
-	CMU_BUZZ_DIV_128 = 0x6,		/**< Division by 128 */
-	CMU_BUZZ_DIV_256 = 0x7,		/**< Division by 256 */
-} cmu_buzz_div_t;
-
-/**
-  * @brief Low power peripheral clock select
-  */
-typedef enum {
-	CMU_LP_PERH_CLOCK_SEL_PCLK2   = 0x0,	/**< Select PCLK2 */
-	CMU_LP_PERH_CLOCK_SEL_PLL1    = 0x1,	/**< Select PLL1 */
-	CMU_LP_PERH_CLOCK_SEL_PLL2    = 0x2,	/**< Select PLL2 */
-	CMU_LP_PERH_CLOCK_SEL_HRC     = 0x3,	/**< Select HRC */
-	CMU_LP_PERH_CLOCK_SEL_HOSC    = 0x4,	/**< Select HOSC */
-	CMU_LP_PERH_CLOCK_SEL_LRC     = 0x5,	/**< Select LRC */
-	CMU_LP_PERH_CLOCK_SEL_LOSC    = 0x6,	/**< Select LOSC */
-	CMU_LP_PERH_CLOCK_SEL_ULRC    = 0x7,	/**< Select ULRC */
-	CMU_LP_PERH_CLOCK_SEL_HRC_1M  = 0x8,	/**< Select HRC down to 1MHz */
-	CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9,	/**< Select HOSC down to 1MHz  */
-	CMU_LP_PERH_CLOCK_SEL_LOSM    = 0xA,	/**< Select LOSM */
-	CMU_LP_PERH_CLOCK_SEL_HOSM    = 0xB,	/**< Select HOSM */
-} cmu_lp_perh_clock_sel_t;
-
-/**
-  * @brief LCD clock select
-  */
-typedef enum {
-	CMU_LCD_SEL_LOSM    = 0x0,	/**< Select LOSM */
-	CMU_LCD_SEL_LOSC    = 0x1,	/**< Select LOSC */
-	CMU_LCD_SEL_LRC     = 0x2,	/**< Select LRC */
-	CMU_LCD_SEL_ULRC    = 0x3,	/**< Select ULRC */
-	CMU_LCD_SEL_HRC_1M  = 0x4,	/**< Select HRC down to 1MHz */
-	CMU_LCD_SEL_HOSC_1M = 0x5,	/**< Select HOSC down to 1MHz */
-} cmu_lcd_clock_sel_t;
-
-/**
-  * @brief Peripheral clock enable/disable
-  */
-typedef enum {
-	CMU_PERH_GPIO    = (1U << 0),			/**< GPIO */
-	CMU_PERH_CRC     = (1U << 1),			/**< CRC */
-	CMU_PERH_CALC    = (1U << 2),			/**< CALC */
-	CMU_PERH_CRYPT   = (1U << 3),			/**< CRYPT */
-	CMU_PERH_TRNG    = (1U << 4),			/**< TRNG */
-	CMU_PERH_PIS     = (1U << 5),			/**< PIS */
-	CMU_PERH_TIM0    = (1U << 0)  | (1U << 27),	/**< TIM0 */
-	CMU_PERH_TIM1    = (1U << 1)  | (1U << 27),	/**< TIM1 */
-	CMU_PERH_TIM2    = (1U << 2)  | (1U << 27),	/**< TIM2 */
-	CMU_PERH_TIM3    = (1U << 3)  | (1U << 27),	/**< TIM3 */
-	CMU_PERH_TIM4    = (1U << 4)  | (1U << 27),	/**< TIM4 */
-	CMU_PERH_TIM5    = (1U << 5)  | (1U << 27),	/**< TIM5 */
-	CMU_PERH_TIM6    = (1U << 6)  | (1U << 27),	/**< TIM6 */
-	CMU_PERH_TIM7    = (1U << 7)  | (1U << 27),	/**< TIM7 */
-	CMU_PERH_UART0   = (1U << 8)  | (1U << 27),	/**< UART0 */
-	CMU_PERH_UART1   = (1U << 9)  | (1U << 27),	/**< UART1 */
-	CMU_PERH_UART2   = (1U << 10) | (1U << 27),	/**< UART2 */
-	CMU_PERH_UART3   = (1U << 11) | (1U << 27),	/**< UART3 */
-	CMU_PERH_USART0  = (1U << 12) | (1U << 27),	/**< USART0 */
-	CMU_PERH_USART1  = (1U << 13) | (1U << 27),	/**< USART1 */
-	CMU_PERH_SPI0    = (1U << 16) | (1U << 27),	/**< SPI0 */
-	CMU_PERH_SPI1    = (1U << 17) | (1U << 27),	/**< SPI1 */
-	CMU_PERH_SPI2    = (1U << 18) | (1U << 27),	/**< SPI2 */
-	CMU_PERH_I2C0    = (1U << 20) | (1U << 27),	/**< I2C0 */
-	CMU_PERH_I2C1    = (1U << 21) | (1U << 27),	/**< I2C1 */
-	CMU_PERH_CAN     = (1U << 24) | (1U << 27),	/**< CAN */
-	CMU_PERH_LPTIM0  = (1U << 0)  | (1U << 28),	/**< LPTIM0 */
-	CMU_PERH_LPUART0 = (1U << 2)  | (1U << 28),	/**< LPUART0 */
-	CMU_PERH_ADC0    = (1U << 4)  | (1U << 28),	/**< ADC0 */
-	CMU_PERH_ADC1    = (1U << 5)  | (1U << 28),	/**< ADC1 */
-	CMU_PERH_ACMP0   = (1U << 6)  | (1U << 28),	/**< ACMP0 */
-	CMU_PERH_ACMP1   = (1U << 7)  | (1U << 28),	/**< ACMP1 */
-	CMU_PERH_OPAMP   = (1U << 8)  | (1U << 28),	/**< OPAMP */
-	CMU_PERH_DAC0    = (1U << 9)  | (1U << 28),	/**< DAC0 */
-	CMU_PERH_WWDT    = (1U << 12) | (1U << 28),	/**< WWDT */
-	CMU_PERH_LCD     = (1U << 13) | (1U << 28),	/**< LCD */
-	CMU_PERH_IWDT    = (1U << 14) | (1U << 28),	/**< IWDT */
-	CMU_PERH_RTC     = (1U << 15) | (1U << 28),	/**< RTC */
-	CMU_PERH_TEMP    = (1U << 16) | (1U << 28),	/**< TEMP */
-	CMU_PERH_BKPC    = (1U << 17) | (1U << 28),	/**< BKPC */
-	CMU_PERH_BKRPAM  = (1U << 18) | (1U << 28),	/**< BKPRAM */
-	CMU_PERH_DBGC    = (1U << 19) | (1U << 28),	/**< DBGC */
-	CMU_PERH_ALL     = (0x7FFFFFFF),		/**< ALL */
-} cmu_perh_t;
-
-/**
-  * @brief CMU interrupt type
-  */
-typedef enum {
-	CMU_LOSC_STOP    = 0x0,	/**< LOSC STOP INTERRUPT */
-	CMU_HOSC_STOP    = 0x1,	/**< HOSC STOP INTERRUPT */
-	CMU_PLL1_UNLOCK  = 0x2,	/**< PLL1 UNLOCK INTERRUPT */
-	CMU_LOSC_START   = 0x3,	/**< LOSC START INTERRUPT */
-	CMU_HOSC_START   = 0x4,	/**< HOSC START INTERRUPT */
-} cmu_security_t;
-
-/**
-  * @brief CMU clock state type
-  */
-typedef enum {
-	CMU_CLOCK_STATE_HOSCACT = (1U << 0),	/**< HOSC active */
-	CMU_CLOCK_STATE_LOSCACT = (1U << 1),	/**< LOSC active */
-	CMU_CLOCK_STATE_HRCACT  = (1U << 2),	/**< HRC active */
-	CMU_CLOCK_STATE_LRCACT  = (1U << 3),	/**< LRC active */
-	CMU_CLOCK_STATE_ULRCACT = (1U << 4),	/**< ULRC active */
-	CMU_CLOCK_STATE_PLLACT  = (1U << 8),	/**< PLL active */
-	CMU_CLOCK_STATE_HOSCRDY = (1U << 16),	/**< HOSC ready */
-	CMU_CLOCK_STATE_LOSCRDY = (1U << 17),	/**< LOSC ready */
-	CMU_CLOCK_STATE_HRCRDY  = (1U << 18),	/**< HRC ready */
-	CMU_CLOCK_STATE_LRCRDY  = (1U << 19),	/**< LRC ready */
-	CMU_CLOCK_STATE_PLLRDY  = (1U << 24),	/**< PLL ready */
-} cmu_clock_state_t;
-/**
-  * @}
-  */
-
-/**
-  * @defgroup CMU_Private_Macros CMU Private Macros
-  * @{
-  */
-#define IS_CMU_CLOCK(x)		(((x) == CMU_CLOCK_HRC)  || \
-                                 ((x) == CMU_CLOCK_LRC)  || \
-                                 ((x) == CMU_CLOCK_LOSC) || \
-                                 ((x) == CMU_CLOCK_PLL1) || \
-                                 ((x) == CMU_CLOCK_HOSC))
-#define IS_CMU_PLL1_OUTPUT(x)	(((x) == CMU_PLL1_OUTPUT_32M) || \
-                                 ((x) == CMU_PLL1_OUTPUT_48M))
-#define IS_CMU_PLL1_INPUT(x)	(((x) == CMU_PLL1_INPUT_HRC_6)  || \
-                                 ((x) == CMU_PLL1_INPUT_PLL2)   || \
-                                 ((x) == CMU_PLL1_INPUT_HOSC)   || \
-                                 ((x) == CMU_PLL1_INPUT_HOSC_2) || \
-                                 ((x) == CMU_PLL1_INPUT_HOSC_3) || \
-                                 ((x) == CMU_PLL1_INPUT_HOSC_4) || \
-                                 ((x) == CMU_PLL1_INPUT_HOSC_5) || \
-                                 ((x) == CMU_PLL1_INPUT_HOSC_6))
-#define IS_CMU_HOSC_RANGE(x)	(((x) == CMU_HOSC_2M)  || \
-                                 ((x) == CMU_HOSC_4M)  || \
-                                 ((x) == CMU_HOSC_8M)  || \
-                                 ((x) == CMU_HOSC_16M) || \
-                                 ((x) == CMU_HOSC_24M))
-#define IS_CMU_DIV(x)		(((x) == CMU_DIV_1)    || \
-                                 ((x) == CMU_DIV_2)    || \
-                                 ((x) == CMU_DIV_4)    || \
-                                 ((x) == CMU_DIV_8)    || \
-                                 ((x) == CMU_DIV_16)   || \
-                                 ((x) == CMU_DIV_32)   || \
-                                 ((x) == CMU_DIV_64)   || \
-                                 ((x) == CMU_DIV_128)  || \
-                                 ((x) == CMU_DIV_256)  || \
-                                 ((x) == CMU_DIV_512)  || \
-                                 ((x) == CMU_DIV_1024) || \
-                                 ((x) == CMU_DIV_2048) || \
-                                 ((x) == CMU_DIV_4096))
-#define IS_CMU_BUS(x)		(((x) == CMU_HCLK_1) || \
-                                 ((x) == CMU_SYS)    || \
-                                 ((x) == CMU_PCLK_1) || \
-                                 ((x) == CMU_PCLK_2))
-#define IS_CMU_OUTPUT_HIGH_SEL(x)	(((x) == CMU_OUTPUT_HIGH_SEL_HOSC) || \
-                                         ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \
-                                         ((x) == CMU_OUTPUT_HIGH_SEL_HRC)  || \
-                                         ((x) == CMU_OUTPUT_HIGH_SEL_LRC)  || \
-                                         ((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \
-                                         ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \
-                                         ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \
-                                         ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK))
-#define IS_CMU_OUTPUT_HIGH_DIV(x)	(((x) == CMU_OUTPUT_DIV_1)  || \
-                                         ((x) == CMU_OUTPUT_DIV_2)  || \
-                                         ((x) == CMU_OUTPUT_DIV_4)  || \
-                                         ((x) == CMU_OUTPUT_DIV_8)  || \
-                                         ((x) == CMU_OUTPUT_DIV_16) || \
-                                         ((x) == CMU_OUTPUT_DIV_32) || \
-                                         ((x) == CMU_OUTPUT_DIV_64) || \
-                                         ((x) == CMU_OUTPUT_DIV_128))
-#define IS_CMU_OUTPUT_LOW_SEL(x)	(((x) == CMU_OUTPUT_LOW_SEL_LOSC) || \
-                                         ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \
-                                         ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \
-                                         ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \
-                                         ((x) == CMU_OUTPUT_LOW_SEL_ULRC))
-#define IS_CMU_AUTO_CALIB_INPUT(x)	(((x) == CMU_AUTO_CALIB_INPUT_LOSE) || \
-                                         ((x) == CMU_AUTO_CALIB_INPUT_HOSE))
-#define IS_CMU_AUTO_CALIB_OUTPUT(x)	(((x) == CMU_AUTO_CALIB_OUTPUT_24M) || \
-                                         ((x) == CMU_AUTO_CALIB_OUTPUT_2M))
-#define IS_CMU_BUZZ_DIV(x)	(((x) == CMU_BUZZ_DIV_2)   || \
-                                 ((x) == CMU_BUZZ_DIV_4)   || \
-                                 ((x) == CMU_BUZZ_DIV_8)   || \
-                                 ((x) == CMU_BUZZ_DIV_16)  || \
-                                 ((x) == CMU_BUZZ_DIV_32)  || \
-                                 ((x) == CMU_BUZZ_DIV_64)  || \
-                                 ((x) == CMU_BUZZ_DIV_128) || \
-                                 ((x) == CMU_BUZZ_DIV_256))
-#define IS_CMU_LP_PERH_CLOCK_SEL(x)	(((x) == CMU_LP_PERH_CLOCK_SEL_PCLK2)   || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1)    || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2)    || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_HRC)     || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC)    || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_LRC)     || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_LOSC)    || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_ULRC)    || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M)  || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM)    || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM))
-#define IS_CMU_LCD_CLOCK_SEL(x)	(((x) == CMU_LCD_SEL_LOSM)   || \
-                                 ((x) == CMU_LCD_SEL_LOSC)   || \
-                                 ((x) == CMU_LCD_SEL_LRC)    || \
-                                 ((x) == CMU_LCD_SEL_ULRC)   || \
-                                 ((x) == CMU_LCD_SEL_HRC_1M) || \
-                                 ((x) == CMU_LCD_SEL_HOSC_1M))
-#define IS_CMU_PERH(x)		(((x) == CMU_PERH_GPIO)    || \
-                                 ((x) == CMU_PERH_CRC)     || \
-                                 ((x) == CMU_PERH_CALC)    || \
-                                 ((x) == CMU_PERH_CRYPT)   || \
-                                 ((x) == CMU_PERH_TRNG)    || \
-                                 ((x) == CMU_PERH_PIS)     || \
-                                 ((x) == CMU_PERH_TIM0)    || \
-                                 ((x) == CMU_PERH_TIM1)    || \
-                                 ((x) == CMU_PERH_TIM2)    || \
-                                 ((x) == CMU_PERH_TIM3)    || \
-                                 ((x) == CMU_PERH_TIM4)    || \
-                                 ((x) == CMU_PERH_TIM5)    || \
-                                 ((x) == CMU_PERH_TIM6)    || \
-                                 ((x) == CMU_PERH_TIM7)    || \
-                                 ((x) == CMU_PERH_UART0)   || \
-                                 ((x) == CMU_PERH_UART1)   || \
-                                 ((x) == CMU_PERH_UART2)   || \
-                                 ((x) == CMU_PERH_UART3)   || \
-                                 ((x) == CMU_PERH_USART0)  || \
-                                 ((x) == CMU_PERH_USART1)  || \
-                                 ((x) == CMU_PERH_SPI0)    || \
-                                 ((x) == CMU_PERH_SPI1)    || \
-                                 ((x) == CMU_PERH_SPI2)    || \
-                                 ((x) == CMU_PERH_I2C0)    || \
-                                 ((x) == CMU_PERH_I2C1)    || \
-                                 ((x) == CMU_PERH_CAN)     || \
-                                 ((x) == CMU_PERH_LPTIM0)  || \
-                                 ((x) == CMU_PERH_LPUART0) || \
-                                 ((x) == CMU_PERH_ADC0)    || \
-                                 ((x) == CMU_PERH_ADC1)    || \
-                                 ((x) == CMU_PERH_ACMP0)   || \
-                                 ((x) == CMU_PERH_ACMP1)   || \
-                                 ((x) == CMU_PERH_OPAMP)   || \
-                                 ((x) == CMU_PERH_DAC0)    || \
-                                 ((x) == CMU_PERH_WWDT)    || \
-                                 ((x) == CMU_PERH_LCD)     || \
-                                 ((x) == CMU_PERH_IWDT)    || \
-                                 ((x) == CMU_PERH_RTC)     || \
-                                 ((x) == CMU_PERH_TEMP)    || \
-                                 ((x) == CMU_PERH_BKPC)    || \
-                                 ((x) == CMU_PERH_BKRPAM ) || \
-                                 ((x) == CMU_PERH_DBGC)    || \
-                                 ((x) == CMU_PERH_ALL))
-#define IS_CMU_CLOCK_STATE(x)	(((x) == CMU_CLOCK_STATE_HOSCACT) || \
-                                 ((x) == CMU_CLOCK_STATE_LOSCACT) || \
-				 ((x) == CMU_CLOCK_STATE_HRCACT) || \
-				 ((x) == CMU_CLOCK_STATE_LRCACT) || \
-				 ((x) == CMU_CLOCK_STATE_ULRCACT) || \
-				 ((x) == CMU_CLOCK_STATE_PLLACT) || \
-				 ((x) == CMU_CLOCK_STATE_HOSCRDY) || \
-				 ((x) == CMU_CLOCK_STATE_LOSCRDY) || \
-				 ((x) == CMU_CLOCK_STATE_HRCRDY) || \
-				 ((x) == CMU_CLOCK_STATE_LRCRDY) || \
-				 ((x) == CMU_CLOCK_STATE_PLLRDY))
-/**
-  * @}
-  */
-
-/** @addtogroup CMU_Public_Functions
-  * @{
-  */
-/** @addtogroup CMU_Public_Functions_Group1
-  * @{
-  */
-/* System clock configure */
-ald_status_t cmu_clock_config_default(void);
-ald_status_t cmu_clock_config(cmu_clock_t clk, uint32_t clock);
-void cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output);
-uint32_t cmu_get_clock(void);
-int32_t cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output_t freq);
-/**
-  * @}
-  */
-
-/** @addtogroup CMU_Public_Functions_Group2
-  * @{
-  */
-/* BUS division control */
-void cmu_div_config(cmu_bus_t bus, cmu_div_t div);
-uint32_t cmu_get_hclk1_clock(void);
-uint32_t cmu_get_sys_clock(void);
-uint32_t cmu_get_pclk1_clock(void);
-uint32_t cmu_get_pclk2_clock(void);
-/**
-  * @}
-  */
-
-/** @addtogroup CMU_Public_Functions_Group3
-  * @{
-  */
-/* Clock safe configure */
-void cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status);
-void cmu_losc_safe_config(type_func_t status);
-void cmu_pll_safe_config(type_func_t status);
-flag_status_t cmu_get_clock_state(cmu_clock_state_t sr);
-void cmu_irq_cbk(cmu_security_t se);
-/**
-  * @}
-  */
-
-/** @addtogroup CMU_Public_Functions_Group4
-  * @{
-  */
-/* Clock output configure */
-void cmu_output_high_clock_config(cmu_output_high_sel_t sel,
-		cmu_output_high_div_t div, type_func_t status);
-void cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status);
-/**
-  * @}
-  */
-
-/** @addtogroup CMU_Public_Functions_Group5
-  * @{
-  */
-/* Peripheral Clock configure */
-void cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status);
-void cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock);
-void cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock);
-void cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock);
-void cmu_perh_clock_config(cmu_perh_t perh, type_func_t status);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_CMU_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crc.h

@@ -1,191 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_crc.h
-  * @brief   Header file of CRC module driver.
-  *
-  * @version V1.0
-  * @date    6 Dec 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#ifndef __ALD_CRC_H__
-#define __ALD_CRC_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup CRC
-  * @{
-  */
-
-/** @defgroup CRC_Public_Types CRC Public Types
-  * @{
-  */
-
-/**
-  * @brief CRC mode
-  */
-typedef enum {
-	CRC_MODE_CCITT = 0,	/**< Ccitt */
-	CRC_MODE_8     = 1,	/**< Crc8 */
-	CRC_MODE_16    = 2,	/**< Crc16 */
-	CRC_MODE_32    = 3,	/**< Crc32 */
-} crc_mode_t;
-
-/**
-  * @brief CRC input length
-  */
-typedef enum {
-	CRC_LEN_AUTO    = 0,	/**< Auto */
-	CRC_DATASIZE_8  = 1,	/**< Byte */
-	CRC_DATASIZE_16 = 2,	/**< Half word */
-	CRC_DATASIZE_32 = 3,	/**< Word */
-} crc_datasize_t;
-
-/**
-  * @brief CRC whether write error or no
-  */
-typedef enum {
-	CRC_WERR_NO  = 0,	/**< No error */
-	CRC_WERR_ERR = 1,	/**< Error */
-} crc_werr_t;
-
-/**
-  * @brief CRC state structures definition
-  */
-typedef enum {
-	CRC_STATE_RESET = 0x0,	/**< Peripheral is not initialized */
-	CRC_STATE_READY = 0x1,	/**< Peripheral Initialized and ready for use */
-	CRC_STATE_BUSY  = 0x2,	/**< An internal process is ongoing */
-	CRC_STATE_ERROR = 0x4,	/**< Error */
-} crc_state_t;
-
-/**
-  * @brief CRC init structure definition
-  */
-typedef struct {
-	crc_mode_t mode;	/**< CRC mode */
-	type_func_t data_rev;	/**< CRC data reverse or no */
-	type_func_t data_inv;	/**< CRC data inverse or no */
-	type_func_t chs_rev; 	/**< CRC check sum reverse or no */
-	type_func_t chs_inv; 	/**< CRC check sum inverse or no */
-	uint32_t seed;		/**< CRC seed */
-} crc_init_t;
-
-/**
-  * @brief  CRC Handle Structure definition
-  */
-typedef struct crc_handle_s {
-	CRC_TypeDef *perh;	/**< Register base address */
-	crc_init_t init;  	/**< CRC required parameters */
-	uint8_t *cal_buf; 	/**< The pointer of preparing buffer */
-	uint32_t *cal_res;	/**< The pointer of result */
-#ifdef ALD_DMA
-	dma_handle_t hdma;	/**< CRC DMA handle parameters */
-#endif
-	lock_state_t lock;	/**< Locking object */
-	crc_state_t state;	/**< CRC operation state */
-
-	void (*cal_cplt_cbk)(struct crc_handle_s *arg);	/**< Calculate completed callback */
-	void (*err_cplt_cbk)(struct crc_handle_s *arg);	/**< Calculate error callback */
-} crc_handle_t;
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Public_Macros CRC Public Macros
-  * @{
-  */
-#define CRC_ENABLE(handle)		(SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
-#define CRC_DISABLE(handle)		(CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
-#define CRC_RESET(handle)		(SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK))
-#define CRC_DMA_ENABLE(handle) 		(SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
-#define CRC_DMA_DISABLE(handle) 	(CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
-#define CRC_CLEAR_ERROR_FLAG(handle)	(SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Private_Macros   CRC Private Macros
-  * @{
-  */
-#define IS_CRC(x) 	((x) == CRC)
-#define IS_CRC_MODE(x) 	(((x) == CRC_MODE_CCITT) || \
-			 ((x) == CRC_MODE_8)     || \
-			 ((x) == CRC_MODE_16)    || \
-			 ((x) == CRC_MODE_32))
-/**
-  * @}
-  */
-
-/** @addtogroup CRC_Public_Functions
-  * @{
-  */
-
-/** @addtogroup CRC_Public_Functions_Group1
-  * @{
-  */
-ald_status_t crc_init(crc_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup CRC_Public_Functions_Group2
-  * @{
-  */
-uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size);
-/**
-  * @}
-  */
-
-#ifdef ALD_DMA
-/** @addtogroup CRC_Public_Functions_Group3
-  * @{
-  */
-ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
-ald_status_t crc_dma_pause(crc_handle_t *hperh);
-ald_status_t crc_dma_resume(crc_handle_t *hperh);
-ald_status_t crc_dma_stop(crc_handle_t *hperh);
-/**
-  * @}
-  */
-#endif
-/** @addtogroup CRC_Public_Functions_Group4
-  * @{
-  */
-crc_state_t crc_get_state(crc_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_CRC_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crypt.h

@@ -1,255 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_crypt.h
-  * @brief   Header file of CRYPT module driver.
-  *
-  * @version V1.0
-  * @date    7 Dec 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#ifndef __ALD_CRYPT_H__
-#define __ALD_CRYPT_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup CRYPT
-  * @{
-  */
-
-/** @defgroup CRYPT_Public_Types CRYPT Public Types
-  * @{
-  */
-
-/**
-  * @brief CRYPT encrypt or decrypt select
-  */
-typedef enum {
-	CRYPT_DECRYPT = 0,	/**< Decrypt */
-	CRYPT_ENCRYPT = 1,	/**< Encrypt */
-} crypt_encs_t;
-
-/**
-  * @brief CRYPT mode select
-  */
-typedef enum {
-	CRYPT_MODE_ECB = 0,	/**< ECB */
-	CRYPT_MODE_CBC = 1,	/**< CBC */
-	CRYPT_MODE_CTR = 2,	/**< CTR */
-} crypt_mode_t;
-
-/**
-  * @brief CRYPT data type
-  */
-typedef enum {
-	CRYPT_DATA_CHANGE_NO = 0,	/**< No exchange */
-	CRYPT_DATA_CHANGE_16 = 1,	/**< 16bit exchange */
-	CRYPT_DATA_CHANGE_8  = 2,	/**< 8bit exchange */
-	CRYPT_DATA_CHANGE_1  = 3,	/**< 1bit exchange */
-} crypt_datatype_t;
-
-/**
-  * @brief CRYPT interrupt
-  */
-typedef enum {
-	CRYPT_IT_IT = 0x80,	/**< Interrupt */
-} crypt_it_t;
-
-/**
-  * @brief CRYPT interrupt flag
-  */
-typedef enum {
-	CRYPT_FLAG_AESIF = 0x1,  	/**< Aes flag */
-	CRYPT_FLAG_DONE  = 0x100,	/**< Complete flag */
-} crypt_flag_t;
-
-/**
-  * @brief CRYPT state structures definition
-  */
-typedef enum {
-	CRYPT_STATE_RESET = 0x0,	/**< Peripheral is not initialized */
-	CRYPT_STATE_READY = 0x1,	/**< Peripheral Initialized and ready for use */
-	CRYPT_STATE_BUSY  = 0x2,	/**< An internal process is ongoing */
-	CRYPT_STATE_ERROR = 0x4,	/**< Error */
-} crypt_state_t;
-
-/**
-  * @brief CRYPT data type
-  */
-typedef enum {
-	DATA_32_BIT = 0,	/**< 32 bit data,don't swap */
-	DATA_16_BIT = 1,	/**< 16 bit data,swap */
-	DATA_8_BIT  = 2,	/**< 8 bit data,swap */
-	DATA_1_BIT  = 3,	/**< 1 bit data, swap */
-} crypt_data_t;
-
-/**
-  * @brief CRYPT init structure definition
-  */
-typedef struct {
-	crypt_mode_t mode;    	/**< Crypt mode */
-	crypt_data_t type;    	/**< Data type select */
-} crypt_init_t;
-
-/**
-  * @brief  CRYPT Handle Structure definition
-  */
-typedef struct crypt_handle_s {
-	CRYPT_TypeDef *perh;	/**< Register base address */
-	crypt_init_t init;  	/**< CRYPT required parameters */
-#ifdef ALD_DMA
-	dma_handle_t hdma_m2p;	/**< CRYPT DMA handle parameters memory to crypt module */
-	dma_handle_t hdma_p2m;	/**< CRYPT DMA handle parameters crypt module to memory */
-#endif
-	uint8_t *plain_text; 	/**< Pointer to plain text */
-	uint8_t *cipher_text;	/**< Pointer to cipher text */
-	uint32_t size;       	/**< The size of crypt data buf */
-	uint32_t count;      	/**< The count of crypt data buf */
-	uint32_t step;       	/**< The step of once crypt 4(aes) */
-	uint32_t dir;        	/**< ENCRYPT or DECRYPT */
-	uint32_t iv[4];     	/**< The iv of crypt */
-	uint32_t key[4];     	/**< The key of crypt */
-	lock_state_t lock;   	/**< Locking object */
-	crypt_state_t state; 	/**< CRYPT operation state */
-
-	void (*crypt_cplt_cbk)(struct crypt_handle_s *arg);	/**< Crypt completed callback */
-	void (*err_cplt_cbk)(struct crypt_handle_s *arg);  	/**< Crypt error callback */
-} crypt_handle_t;
-/**
-  * @}
-  */
-
-/** @defgroup CRYPT_Public_Macros CRYPT Public Macros
-  * @{
-  */
-#define CRYPT_GO(handle) 		(SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK))
-#define CRYPT_FIFOEN_ENABLE(handle) 	(SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
-#define CRYPT_FIFOEN_DISABLE(handle) 	(CLEAR_BIT(handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
-#define CRYPT_IVEN_ENABLE(handle) 	(SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
-#define CRYPT_IVEN_DISABLE(handle) 	(CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
-#define CRYPT_IE_ENABLE(handle)		(SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
-#define CRYPT_IE_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
-#define CRYPT_DMA_ENABLE(handle)	(SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
-#define CRYPT_DMA_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
-#define CRYPT_SETDIR(handle, dir)	do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS);	\
-					   (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0)
-#define CRYPT_WRITE_FIFO(handle, data)  ((handle)->perh->FIFO = (data))
-#define CRYPT_READ_FIFO(handle)		((handle)->perh->FIFO)
-/**
-  * @}
-  */
-
-/** @defgroup CRYPT_Private_Macros   CRYPT Private Macros
-  * @{
-  */
-#define IS_CRYPT(x)		((x) == CRYPT)
-#define IS_CRYPT_MODE(x) 	(((x) == CRYPT_MODE_ECB) ||   \
-				 ((x) == CRYPT_MODE_CBC) ||   \
-				 ((x) == CRYPT_MODE_CTR))
-#define IS_CRYPT_IT(x)		((x) == CRYPT_IT_IT)
-#define IS_CRYPT_FLAG(x) 	(((x) == CRYPT_FLAG_AESIF) || \
-				 ((x) == CRYPT_FLAG_DONE))
-#define IS_CRYPT_IV_LEN(x)	(((x) == IV_2_LEN) || \
-				 ((x) == IV_4_LEN))
-/**
-  * @}
-  */
-
-/** @addtogroup CRYPT_Public_Functions
-  * @{
-  */
-
-/** @addtogroup CRYPT_Public_Functions_Group1
-  * @{
-  */
-ald_status_t crypt_init(crypt_handle_t *hperh);
-ald_status_t crypt_write_key(crypt_handle_t *hperh, uint32_t *key);
-ald_status_t crypt_read_key(crypt_handle_t *hperh, uint32_t *key);
-ald_status_t crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv);
-ald_status_t crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv);
-/**
-  * @}
-  */
-
-/** @addtogroup CRYPT_Public_Functions_Group2
-  * @{
-  */
-ald_status_t crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size);
-ald_status_t crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size);
-ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag);
-ald_status_t crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size);
-ald_status_t crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size);
-#ifdef ALD_DMA
-ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text,
-             uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
-ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text,
-               uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
-#endif
-/**
-  * @}
-  */
-
-/** @addtogroup CRYPT_Public_Functions_Group3
-  * @{
-  */
-#ifdef ALD_DMA
-ald_status_t crypt_dma_pause(crypt_handle_t *hperh);
-ald_status_t crypt_dma_resume(crypt_handle_t *hperh);
-ald_status_t crypt_dma_stop(crypt_handle_t *hperh);
-#endif
-void crypt_irq_handle(crypt_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup CRYPT_Public_Functions_Group4
-  * @{
-  */
-void crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state);
-flag_status_t crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag);
-void crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag);
-it_status_t crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it);
-/**
-  * @}
-  */
-
-/** @addtogroup CRYPT_Public_Functions_Group5
-  * @{
-  */
-crypt_state_t crypt_get_state(crypt_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dbgc.h

@@ -1,156 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_dbgc.h
-  * @brief   DEBUGCON module driver.
-  *
-  * @version V1.0
-  * @date    04 Jun 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#ifndef __ALD_DBGC_H__
-#define __ALD_DBGC_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup DBGC DBGC
-  * @brief DBGC module driver
-  * @{
-  */
-
-
-
-/** @defgroup DBGC_Public_Types DBGC Public Types
-  * @{
-  */
-/**
-  * @brief Debug mode select
-  */
-typedef enum {
-	DEBC_MODE_SLEEP   = (1u << 0),	/**< Sleep mode */
-	DEBC_MODE_STOP1   = (1u << 1),	/**< STOP1 mode */
-	DEBC_MODE_STOP2   = (1u << 2),	/**< STOP2 mode */
-	DEBC_MODE_STANDBY = (1u << 3),	/**< Standby mode */
-} dbgc_mode_t;
-
-/**
-  * @brief Debug peripheral select
-  */
-typedef enum {
-	DEBC_PERH_TIMER0  = (1u << 0),			/**< AD16C4T0 */
-	DEBC_PERH_TIMER1  = (1u << 1),			/**< BS16T0 */
-	DEBC_PERH_TIMER2  = (1u << 2),			/**< GP16C2T0 */
-	DEBC_PERH_TIMER3  = (1u << 3),			/**< GP16C2T1 */
-	DEBC_PERH_TIMER4  = (1u << 4),			/**< BS16T1 */
-	DEBC_PERH_TIMER5  = (1u << 5),			/**< BS16T2 */
-	DEBC_PERH_TIMER6  = (1u << 6),			/**< GP16C4T0 */
-	DEBC_PERH_TIMER7  = (1u << 7),			/**< BS16T3 */
-	DEBC_PERH_I2C0    = (1u << 8),			/**< I2C0 SMBUS */
-	DEBC_PERH_I2C1    = (1u << 9),			/**< I2C1 SMBUS */
-	DEBC_PERH_CAN     = (1u << 12),			/**< CAN */
-	DEBC_PERH_LPTIM0  = (1u << 0)  | (1u << 16),	/**< LPTIM0 */
-	DEBC_PERH_IWDT    = (1u << 8)  | (1u << 16),	/**< IWDT */
-	DEBC_PERH_WWDT    = (1u << 9)  | (1u << 16),	/**< WWDT */
-	DEBC_PERH_RTC     = (1u << 10) | (1u << 16),	/**< RTC */
-} dbgc_perh_t;
-/**
-  * @}
-  */
-
-/** @defgroup DBGC_Public_Functions DBGC Public Functions
-  * @{
-  */
-/**
-  * @brief  Gets version.
-  * @retval Version
-  */
-__INLINE uint32_t dbgc_get_rev_id(void)
-{
-	return (DBGC->IDCODE >> 16);
-}
-
-/**
-  * @brief  Gets core id.
-  * @retval Core id
-  */
-__INLINE uint32_t dbgc_get_core_id(void)
-{
-	return (DBGC->IDCODE >> 12) & 0xF;
-}
-
-/**
-  * @brief  Gets device id
-  * @retval device id
-  */
-__INLINE uint32_t dbgc_get_device_id(void)
-{
-	return DBGC->IDCODE & 0xFFF;
-}
-
-/**
-  * @brief  Configures low power debug mode
-  * @param  mode: The mode of low power.
-  * @param  state: ENABLE/DISABLE
-  * @retval None
-  */
-__INLINE void dbgc_mode_config(dbgc_mode_t mode, type_func_t state)
-{
-	if (state)
-		SET_BIT(DBGC->CR, mode);
-	else
-		CLEAR_BIT(DBGC->CR, mode);
-}
-
-/**
-  * @brief  Configures peripheral debug mode
-  * @param  perh: The peripheral.
-  * @param  state: ENABLE/DISABLE
-  * @retval None
-  */
-__INLINE void dbgc_perh_config(dbgc_perh_t perh, type_func_t state)
-{
-	if ((perh >> 16) & 0x1) {
-		if (state)
-			SET_BIT(DBGC->APB2FZ, perh);
-		else
-			CLEAR_BIT(DBGC->APB2FZ, perh);
-	}
-	else {
-		if (state)
-			SET_BIT(DBGC->APB1FZ, perh);
-		else
-			CLEAR_BIT(DBGC->APB1FZ, perh);
-	}
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dma.h

@@ -1,377 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_dma.h
-  * @brief   DMA module Library.
-  *
-  * @version V1.0
-  * @date    09 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#ifndef __ALD_DMA_H__
-#define __ALD_DMA_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup DMA
-  * @{
-  */
-
-/**
-  * @defgroup DMA_Public_Macros DMA Public Macros
-  * @{
-  */
-#define DMA_CH_COUNT	6
-#define DMA_ERR		31
-/**
-  * @}
-  */
-
-/**
-  * @defgroup DMA_Public_Types DMA Public Types
-  * @{
-  */
-
-/**
-  * @brief Input source to DMA channel
-  */
-typedef enum {
-	DMA_MSEL_NONE    = 0x0,		/**< NONE */
-	DMA_MSEL_GPIO    = 0x1,		/**< GPIO */
-	DMA_MSEL_CRYPT   = 0x2,		/**< CRYPT */
-	DMA_MSEL_ACMP    = 0x3,		/**< ACMP */
-	DMA_MSEL_DAC0    = 0x4,		/**< DAC0 */
-	DMA_MSEL_ADC0    = 0x6,		/**< ADC0 */
-	DMA_MSEL_CRC     = 0x7,		/**< CRC */
-	DMA_MSEL_UART0   = 0x8,		/**< UART0 */
-	DMA_MSEL_UART1   = 0x9,		/**< UART1 */
-	DMA_MSEL_UART2   = 0xA,		/**< UART2 */
-	DMA_MSEL_UART3   = 0xB,		/**< UART3 */
-	DMA_MSEL_USART0  = 0xC,		/**< USART0 */
-	DMA_MSEL_USART1  = 0xD,		/**< USART1 */
-	DMA_MSEL_SPI0    = 0xE,		/**< SPI0 */
-	DMA_MSEL_SPI1    = 0xF,		/**< SPI1 */
-	DMA_MSEL_I2C0    = 0x10,	/**< I2C0 */
-	DMA_MSEL_I2C1    = 0x11,	/**< I2C1 */
-	DMA_MSEL_TIMER0  = 0x12,	/**< TIMER0 */
-	DMA_MSEL_TIMER1  = 0x13,	/**< TIMER1 */
-	DMA_MSEL_TIMER2  = 0x14,	/**< TIMER2 */
-	DMA_MSEL_TIMER3  = 0x15,	/**< TIMER3 */
-	DMA_MSEL_RTC     = 0x16,	/**< RTC */
-	DMA_MSEL_LPTIM0  = 0x17,	/**< LPTIM0 */
-	DMA_MSEL_LPUART0 = 0x18,	/**< LPUART0 */
-	DMA_MSEL_DMA     = 0x19,	/**< DMA */
-	DMA_MSEL_SPI2    = 0x1A,	/**< SPI2 */
-	DMA_MSEL_TIMER4  = 0x1B,	/**< TIMER4 */
-	DMA_MSEL_TIMER5  = 0x1C,	/**< TIMER5 */
-	DMA_MSEL_TIMER6  = 0x1D,	/**< TIMER6 */
-	DMA_MSEL_TIMER7  = 0x1E,	/**< TIMER7 */
-	DMA_MSEL_ADC1    = 0x1F,	/**< ADC1 */
-	DMA_MSEL_PIS     = 0x20,	/**< PIS */
-	DMA_MSEL_TRNG    = 0x21,	/**< TRNG */
-} dma_msel_t;
-
-/**
-  * @brief Input signal to DMA channel
-  */
-typedef enum {
-	DMA_MSIGSEL_NONE           = 0x0,	/**< NONE */
-	DMA_MSIGSEL_EXTI_0         = 0x0,	/**< External interrupt 0 */
-	DMA_MSIGSEL_EXTI_1         = 0x1,	/**< External interrupt 1 */
-	DMA_MSIGSEL_EXTI_2         = 0x2,	/**< External interrupt 2 */
-	DMA_MSIGSEL_EXTI_3         = 0x3,	/**< External interrupt 3 */
-	DMA_MSIGSEL_EXTI_4         = 0x4,	/**< External interrupt 4 */
-	DMA_MSIGSEL_EXTI_5         = 0x5,	/**< External interrupt 5 */
-	DMA_MSIGSEL_EXTI_6         = 0x6,	/**< External interrupt 6 */
-	DMA_MSIGSEL_EXTI_7         = 0x7,	/**< External interrupt 7 */
-	DMA_MSIGSEL_EXTI_8         = 0x8,	/**< External interrupt 8 */
-	DMA_MSIGSEL_EXTI_9         = 0x9,	/**< External interrupt 9 */
-	DMA_MSIGSEL_EXTI_10        = 0xA,	/**< External interrupt 10 */
-	DMA_MSIGSEL_EXTI_11        = 0xB,	/**< External interrupt 11 */
-	DMA_MSIGSEL_EXTI_12        = 0xC,	/**< External interrupt 12 */
-	DMA_MSIGSEL_EXTI_13        = 0xD,	/**< External interrupt 13 */
-	DMA_MSIGSEL_EXTI_14        = 0xE,	/**< External interrupt 14 */
-	DMA_MSIGSEL_EXTI_15        = 0xF,	/**< External interrupt 15 */
-	DMA_MSIGSEL_CRYPT_WRITE    = 0x0,	/**< CRYPT write mode */
-	DMA_MSIGSEL_CRYPT_READ     = 0x1,	/**< CRYPT read mode */
-	DMA_MSIGSEL_CALC_WRITE     = 0x0,	/**< CALC write mode */
-	DMA_MSIGSEL_CALC_READ      = 0x1,	/**< CALC read mode */
-	DMA_MSIGSEL_DAC0_CH0       = 0x0,	/**< DAC0 channel 0 complete */
-	DMA_MSIGSEL_DAC0_CH1       = 0x1,	/**< DAC0 channel 1 complete */
-	DMA_MSIGSEL_ADC       	   = 0x0,	/**< ADC mode */
-	DMA_MSIGSEL_UART_TXEMPTY   = 0x0,	/**< UART transmit */
-	DMA_MSIGSEL_UART_RNR       = 0x1,	/**< UART receive */
-	DMA_MSIGSEL_USART_RNR      = 0x0,	/**< USART reveive */
-	DMA_MSIGSEL_USART_TXEMPTY  = 0x1,	/**< USART transmit */
-	DMA_MSIGSEL_SPI_RNR        = 0x0,	/**< SPI receive */
-	DMA_MSIGSEL_SPI_TXEMPTY    = 0x1,	/**< SPI transmit */
-	DMA_MSIGSEL_I2C_RNR        = 0x0,	/**< I2C receive */
-	DMA_MSIGSEL_I2C_TXEMPTY    = 0x1,	/**< I2C transmit */
-	DMA_MSIGSEL_TIMER_CH1      = 0x0,	/**< TIM channal 1 */
-	DMA_MSIGSEL_TIMER_CH2      = 0x1,	/**< TIM channal 2 */
-	DMA_MSIGSEL_TIMER_CH3      = 0x2,	/**< TIM channal 3 */
-	DMA_MSIGSEL_TIMER_CH4      = 0x3,	/**< TIM channal 4 */
-	DMA_MSIGSEL_TIMER_TRI      = 0x4,	/**< TIM trigger */
-	DMA_MSIGSEL_TIMER_COMP     = 0x5,	/**< TIM compare */
-	DMA_MSIGSEL_TIMER_UPDATE   = 0x6,	/**< TIM update */
-	DMA_MSIGSEL_LPUART_RNR     = 0x0,	/**< LPUART receive */
-	DMA_MSIGSEL_LPUART_TXEMPTY = 0x1,	/**< LPUART transmit */
-	DMA_MSIGSEL_PIS_CH0        = 0x0,	/**< PIS channal 0 */
-	DMA_MSIGSEL_PIS_CH1        = 0x1,	/**< PIS channal 1 */
-	DMA_MSIGSEL_PIS_CH2        = 0x2,	/**< PIS channal 2 */
-	DMA_MSIGSEL_PIS_CH3        = 0x3,	/**< PIS channal 3 */
-	DMA_MSIGSEL_PIS_CH4        = 0x4,	/**< PIS channal 4 */
-	DMA_MSIGSEL_PIS_CH5        = 0x5,	/**< PIS channal 5 */
-	DMA_MSIGSEL_PIS_CH6        = 0x6,	/**< PIS channal 6 */
-	DMA_MSIGSEL_PIS_CH7        = 0x7,	/**< PIS channal 7 */
-	DMA_MSIGSEL_PIS_CH8        = 0x8,	/**< PIS channal 8 */
-	DMA_MSIGSEL_PIS_CH9        = 0x9,	/**< PIS channal 9 */
-	DMA_MSIGSEL_PIS_CH10       = 0xA,	/**< PIS channal 10 */
-	DMA_MSIGSEL_PIS_CH11       = 0xB,	/**< PIS channal 11 */
-	DMA_MSIGSEL_PIS_CH12       = 0xC,	/**< PIS channal 12 */
-	DMA_MSIGSEL_PIS_CH13       = 0xD,	/**< PIS channal 13 */
-	DMA_MSIGSEL_PIS_CH14       = 0xE,	/**< PIS channal 14 */
-	DMA_MSIGSEL_PIS_CH15       = 0xF,	/**< PIS channal 15 */
-} dma_msigsel_t;
-
-/**
-  * @brief DMA Descriptor control type
-  */
-typedef union {
-	struct {
-		uint32_t cycle_ctrl    :3;	/**< DMA operating mode @ref dma_cycle_ctrl_t */
-		uint32_t next_useburst :1;	/**< Uses the alternate data structure when complete a DMA cycle */
-		uint32_t n_minus_1     :10;	/**< Represent the total number of DMA transfers that DMA cycle contains. */
-		uint32_t R_power       :4;	/**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
-		uint32_t src_prot_ctrl :3;	/**< Control the state of HPROT when reads the source data. */
-		uint32_t dst_prot_ctrl :3;	/**< Control the state of HPROT when writes the destination data */
-		uint32_t src_size      :2;	/**< Source data size @ref dma_data_size_t */
-		uint32_t src_inc       :2;	/**< Control the source address increment. @ref dma_data_inc_t */
-		uint32_t dst_size      :2;	/**< Destination data size. @ref dma_data_size_t */
-		uint32_t dst_inc       :2;	/**< Destination address increment. @ref dma_data_inc_t */
-	};
-	uint32_t word;
-} dma_ctrl_t;
-
-/**
-  * @brief Channel control data structure
-  */
-typedef struct {
-	void *src;		/**< Source data end pointer */
-	void *dst;		/**< Destination data end pointer */
-	dma_ctrl_t ctrl;	/**< Control data configuration @ref dma_ctrl_t */
-	uint32_t use;		/**< Reserve for user */
-} dma_descriptor_t;
-
-/**
-  * @brief data increment
-  */
-typedef enum {
-	DMA_DATA_INC_BYTE     = 0x0,	/**< Address increment by byte */
-	DMA_DATA_INC_HALFWORD = 0x1,	/**< Address increment by halfword */
-	DMA_DATA_INC_WORD     = 0x2,	/**< Address increment by word */
-	DMA_DATA_INC_NONE     = 0x3,	/**< No increment */
-} dma_data_inc_t;
-
-/**
-  * @brief Data size
-  */
-typedef enum {
-	DMA_DATA_SIZE_BYTE     = 0x0,	/**< Byte */
-	DMA_DATA_SIZE_HALFWORD = 0x1,	/**< Halfword */
-	DMA_DATA_SIZE_WORD     = 0x2,	/**< Word */
-} dma_data_size_t;
-
-/**
-  * @brief The operating mode of the DMA cycle
-  */
-typedef enum {
-	DMA_CYCLE_CTRL_NONE               = 0x0,	/**< Stop */
-	DMA_CYCLE_CTRL_BASIC              = 0x1,	/**< Basic */
-	DMA_CYCLE_CTRL_AUTO               = 0x2,	/**< Auto-request */
-	DMA_CYCLE_CTRL_PINGPONG           = 0x3,	/**< Ping-pong */
-	DMA_CYCLE_CTRL_MEM_SCATTER_GATHER = 0x4,	/**< Memory scatter/gather */
-	DMA_CYCLE_CTRL_PER_SCATTER_GATHER = 0x6,	/**< Peripheral scatter/gather */
-} dma_cycle_ctrl_t;
-
-/**
-  * @brief Control how many DMA transfers can occur
-  *        before the controller re-arbitrates
-  */
-typedef enum {
-	DMA_R_POWER_1    = 0x0,		/**< Arbitrates after each DMA transfer */
-	DMA_R_POWER_2    = 0x1,		/**< Arbitrates after 2 DMA transfer */
-	DMA_R_POWER_4    = 0x2,		/**< Arbitrates after 4 DMA transfer */
-	DMA_R_POWER_8    = 0x3,		/**< Arbitrates after 8 DMA transfer */
-	DMA_R_POWER_16   = 0x4,		/**< Arbitrates after 16 DMA transfer */
-	DMA_R_POWER_32   = 0x5,		/**< Arbitrates after 32 DMA transfer */
-	DMA_R_POWER_64   = 0x6,		/**< Arbitrates after 64 DMA transfer */
-	DMA_R_POWER_128  = 0x7,		/**< Arbitrates after 128 DMA transfer */
-	DMA_R_POWER_256  = 0x8,		/**< Arbitrates after 256 DMA transfer */
-	DMA_R_POWER_512  = 0x9,		/**< Arbitrates after 512 DMA transfer */
-	DMA_R_POWER_1024 = 0xA,		/**< Arbitrates after 1024 DMA transfer */
-} dma_arbiter_config_t;
-
-/**
-  * @brief Callback function pointer and param
-  */
-typedef struct {
-	void (*cplt_cbk)(void *arg);	/**< DMA transfers complete callback */
-	void (*err_cbk)(void* arg);	/**< DMA occurs error callback */
-	void *cplt_arg;			/**< The parameter of cplt_cbk() */
-	void *err_arg;			/**< The parameter of err_cbk() */
-} dma_call_back_t;
-
-/**
-  * @brief DMA channal configure structure
-  */
-typedef struct {
-	void *src;			/**< Source data begin pointer */
-	void *dst;			/**< Destination data begin pointer */
-	uint16_t size;			/**< The total number of DMA transfers that DMA cycle contains */
-	dma_data_size_t data_width;	/**< Data width, @ref dma_data_size_t */
-	dma_data_inc_t src_inc;		/**< Source increment type. @ref dma_data_inc_t */
-	dma_data_inc_t dst_inc;		/**< Destination increment type. @ref dma_data_inc_t */
-	dma_arbiter_config_t R_power;	/**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
-	type_func_t primary;		/**< Use primary descriptor or alternate descriptor */
-	type_func_t burst;		/**< Uses the alternate data structure when complete a DMA cycle */
-	type_func_t high_prio;		/**< High priority or default priority */
-	type_func_t iterrupt;		/**< Enable/disable interrupt */
-	dma_msel_t msel;		/**< Input source to DMA channel @ref dma_msel_t */
-	dma_msigsel_t msigsel;		/**< Input signal to DMA channel @ref dma_msigsel_t */
-	uint8_t channel;		/**< Channel index */
-} dma_config_t;
-
-/**
-  * @brief DMA handle structure definition
-  */
-typedef struct {
-	DMA_TypeDef *perh;		/**< DMA registers base address */
-	dma_config_t config;		/**< Channel configure structure. @ref dma_config_t */
-	void (*cplt_cbk)(void *arg);	/**< DMA transfers complete callback */
-	void (*err_cbk)(void *arg);	/**< DMA bus occurs error callback */
-	void *cplt_arg;			/**< The parameter of cplt_cbk() */
-	void *err_arg;			/**< The parameter of err_cbk() */
-} dma_handle_t;
-/**
-  * @}
-  */
-
-/**
-  * @defgroup DMA_Private_Macros DMA Private Macros
-  * @{
-  */
-#define IS_DMA_MSEL_TYPE(x)	((x) <= DMA_MSEL_TRNG)
-#define IS_DMA_MSIGSEL_TYPE(x)	((x) <= 0xF)
-#define IS_DMA_DATAINC_TYPE(x)  (((x) == DMA_DATA_INC_BYTE)     || \
-                                 ((x) == DMA_DATA_INC_HALFWORD) || \
-                                 ((x) == DMA_DATA_INC_WORD)     || \
-                                 ((x) == DMA_DATA_INC_NONE))
-#define IS_DMA_DATASIZE_TYPE(x)  (((x) == DMA_DATA_SIZE_BYTE)     || \
-                                  ((x) == DMA_DATA_SIZE_HALFWORD) || \
-                                  ((x) == DMA_DATA_SIZE_WORD))
-#define IS_CYCLECTRL_TYPE(x)  (((x) == DMA_CYCLE_CTRL_NONE)               || \
-                               ((x) == DMA_CYCLE_CTRL_BASIC)              || \
-                               ((x) == DMA_CYCLE_CTRL_AUTO)               || \
-                               ((x) == DMA_CYCLE_CTRL_PINGPONG)           || \
-                               ((x) == DMA_CYCLE_CTRL_MEM_SCATTER_GATHER) || \
-                               ((x) == DMA_CYCLE_CTRL_PER_SCATTER_GATHER))
-#define IS_DMA_ARBITERCONFIG_TYPE(x)  (((x) == DMA_R_POWER_1)   || \
-                                       ((x) == DMA_R_POWER_2)   || \
-                                       ((x) == DMA_R_POWER_4)   || \
-                                       ((x) == DMA_R_POWER_8)   || \
-                                       ((x) == DMA_R_POWER_16)  || \
-                                       ((x) == DMA_R_POWER_32)  || \
-                                       ((x) == DMA_R_POWER_64)  || \
-                                       ((x) == DMA_R_POWER_128) || \
-                                       ((x) == DMA_R_POWER_256) || \
-                                       ((x) == DMA_R_POWER_512) || \
-                                       ((x) == DMA_R_POWER_1024))
-#define IS_DMA(x)		((x) == DMA0)
-#define IS_DMA_CHANNEL(x)	((x) <= 5)
-#define IS_DMA_DATA_SIZE(x)	((x) <= 1024)
-#define IS_DMA_IT_TYPE(x)	(((x) <= 5) || ((x) == 31))
-/**
-  * @}
-  */
-
-/**
-  * @addtogroup DMA_Public_Functions
-  * @{
-  */
-
-/** @addtogroup DMA_Public_Functions_Group1
-  * @{
-  */
-/* Initialization functions */
-extern void dma_reset(DMA_TypeDef *DMAx);
-extern void dma_init(DMA_TypeDef *DMAx);
-extern void dma_config_struct(dma_config_t *p);
-/**
-  * @}
-  */
-
-
-/** @addtogroup DMA_Public_Functions_Group2
-  * @{
-  */
-/* Configure DMA channel functions */
-extern void dma_config_auto(dma_handle_t *hperh);
-extern void dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size);
-extern void dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst,
-                                        uint16_t size, uint8_t channel, void (*cbk)(void *arg));
-extern void dma_config_basic(dma_handle_t *hperh);
-extern void dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size);
-extern void dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel,
-                                 dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg));
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Public_Functions_Group3
-  * @{
-  */
-/* DMA control functions */
-extern void dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state);
-extern void dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state);
-extern it_status_t dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel);
-extern flag_status_t dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel);
-extern void dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel);
-void dma0_irq_cbk(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/*__ALD_DMA_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_gpio.h

@@ -1,277 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_gpio.h
-  * @brief   Header file of GPIO module driver
-  *
-  * @version V1.0
-  * @date    07 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#ifndef __ALD_GPIO_H__
-#define __ALD_GPIO_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup GPIO
-  * @{
-  */
-
-/**
-  * @defgroup GPIO_Public_Macros GPIO Public Macros
-  * @{
-  */
-#define GPIO_PIN_0	(1U << 0)
-#define GPIO_PIN_1	(1U << 1)
-#define GPIO_PIN_2	(1U << 2)
-#define GPIO_PIN_3	(1U << 3)
-#define GPIO_PIN_4	(1U << 4)
-#define GPIO_PIN_5	(1U << 5)
-#define GPIO_PIN_6	(1U << 6)
-#define GPIO_PIN_7	(1U << 7)
-#define GPIO_PIN_8	(1U << 8)
-#define GPIO_PIN_9	(1U << 9)
-#define GPIO_PIN_10	(1U << 10)
-#define GPIO_PIN_11	(1U << 11)
-#define GPIO_PIN_12	(1U << 12)
-#define GPIO_PIN_13	(1U << 13)
-#define GPIO_PIN_14	(1U << 14)
-#define GPIO_PIN_15	(1U << 15)
-#define GPIO_PIN_ALL	(0xFFFF)
-/**
-  * @}
-  */
-
-/**
-  * @defgroup GPIO_Public_Types GPIO Public Types
-  * @{
-  */
-
-/**
-  * @brief GPIO mode
-  */
-typedef enum {
-	GPIO_MODE_CLOSE  = 0x0,	/**< Digital close  Analog open */
-	GPIO_MODE_INPUT  = 0x1,	/**< Input */
-	GPIO_MODE_OUTPUT = 0x2,	/**< Output */
-} gpio_mode_t;
-
-/**
-  * @brief GPIO open-drain or push-pull
-  */
-typedef enum {
-	GPIO_PUSH_PULL   = 0x0,	/**< Push-Pull */
-	GPIO_OPEN_DRAIN  = 0x2,	/**< Open-Drain */
-	GPIO_OPEN_SOURCE = 0x3,	/**< Open-Source */
-} gpio_odos_t;
-
-/**
-  * @brief GPIO push-up or push-down
-  */
-typedef enum {
-	GPIO_FLOATING     = 0x0,/**< Floating */
-	GPIO_PUSH_UP      = 0x1,/**< Push-Up */
-	GPIO_PUSH_DOWN    = 0x2,/**< Push-Down */
-	GPIO_PUSH_UP_DOWN = 0x3,/**< Push-Up and Push-Down */
-} gpio_push_t;
-
-/**
-  * @brief GPIO output drive
-  */
-typedef enum {
-	GPIO_OUT_DRIVE_NORMAL = 0x0,	/**< Normal current flow */
-	GPIO_OUT_DRIVE_STRONG = 0x1,	/**< Strong current flow */
-} gpio_out_drive_t;
-
-/**
-  * @brief GPIO filter
-  */
-typedef enum {
-	GPIO_FILTER_DISABLE = 0x0,	/**< Disable filter */
-	GPIO_FILTER_ENABLE  = 0x1,	/**< Enable filter */
-} gpio_filter_t;
-
-/**
-  * @brief GPIO type
-  */
-typedef enum {
-	GPIO_TYPE_CMOS = 0x0,	/**< CMOS Type */
-	GPIO_TYPE_TTL  = 0x1,	/**< TTL Type */
-} gpio_type_t;
-
-/**
-  * @brief GPIO functions
-  */
-typedef enum {
-	GPIO_FUNC_0 = 0,	/**< function #0 */
-	GPIO_FUNC_1 = 1,	/**< function #1 */
-	GPIO_FUNC_2 = 2,	/**< function #2 */
-	GPIO_FUNC_3 = 3,	/**< function #3 */
-	GPIO_FUNC_4 = 4,	/**< function #4 */
-	GPIO_FUNC_5 = 5,	/**< function #5 */
-	GPIO_FUNC_6 = 6,	/**< function #6 */
-	GPIO_FUNC_7 = 7,	/**< function #7 */
-} gpio_func_t;
-
-
-/**
-  * @brief GPIO Init Structure definition
-  */
-typedef struct {
-	gpio_mode_t mode;	/**< Specifies the operating mode for the selected pins.
-				     This parameter can be any value of @ref gpio_mode_t */
-	gpio_odos_t odos;	/**< Specifies the Open-Drain or Push-Pull for the selected pins.
-				     This parameter can be a value of @ref gpio_odos_t */
-	gpio_push_t pupd;	/**< Specifies the Pull-up or Pull-Down for the selected pins.
-				     This parameter can be a value of @ref gpio_push_t */
-	gpio_out_drive_t odrv;	/**< Specifies the output driver for the selected pins.
-				     This parameter can be a value of @ref gpio_out_drive_t */
-	gpio_filter_t flt;	/**< Specifies the input filter for the selected pins.
-				     This parameter can be a value of @ref gpio_filter_t */
-	gpio_type_t type;	/**< Specifies the type for the selected pins.
-				     This parameter can be a value of @ref gpio_type_t */
-	gpio_func_t func;	/**< Specifies the function for the selected pins.
-				     This parameter can be a value of @ref gpio_func_t */
-} gpio_init_t;
-
-/**
-  * @brief EXTI trigger style
-  */
-typedef enum {
-	EXTI_TRIGGER_RISING_EDGE   = 0,	/**< Rising edge trigger */
-	EXTI_TRIGGER_TRAILING_EDGE = 1,	/**< Trailing edge trigger */
-	EXTI_TRIGGER_BOTH_EDGE     = 2,	/**< Rising and trailing edge trigger */
-} exti_trigger_style_t;
-
-/**
-  * @brief EXTI filter clock select
-  */
-typedef enum {
-	EXTI_FILTER_CLOCK_10K = 0,	/**< cks = 10KHz */
-	EXTI_FILTER_CLOCK_32K = 1,	/**< cks = 32KHz */
-} exti_filter_clock_t;
-
-/**
-  * @brief EXTI Init Structure definition
-  */
-typedef struct {
-	type_func_t filter;		/**< Enable filter. */
-	exti_filter_clock_t cks;	/**< Filter clock select. */
-	uint8_t filter_time;		/**< Filter duration */
-} exti_init_t;
-/**
-  * @}
-  */
-
-/**
-  * @defgroup GPIO_Private_Macros GPIO Private Macros
-  * @{
-  */
-#define PIN_MASK	0xFFFF
-#define UNLOCK_KEY	0x55AA
-
-#define IS_GPIO_PIN(x)	((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0))
-#define IS_GPIO_PORT(GPIOx)	((GPIOx == GPIOA) || \
-				 (GPIOx == GPIOB) || \
-				 (GPIOx == GPIOC) || \
-				 (GPIOx == GPIOD) || \
-				 (GPIOx == GPIOE) || \
-				 (GPIOx == GPIOF) || \
-				 (GPIOx == GPIOG) || \
-				 (GPIOx == GPIOH))
-#define IS_GPIO_MODE(x)		(((x) == GPIO_MODE_CLOSE) || \
-                                 ((x) == GPIO_MODE_INPUT) || \
-                                 ((x) == GPIO_MODE_OUTPUT))
-#define IS_GPIO_ODOS(x)		(((x) == GPIO_PUSH_PULL)  || \
-                                 ((x) == GPIO_OPEN_DRAIN) || \
-                                 ((x) == GPIO_OPEN_SOURCE))
-#define IS_GPIO_PUPD(x)		(((x) == GPIO_FLOATING)  || \
-                                 ((x) == GPIO_PUSH_UP)   || \
-                                 ((x) == GPIO_PUSH_DOWN) || \
-                                 ((x) == GPIO_PUSH_UP_DOWN))
-#define IS_GPIO_ODRV(x)		(((x) == GPIO_OUT_DRIVE_NORMAL) || \
-                                 ((x) == GPIO_OUT_DRIVE_STRONG))
-#define IS_GPIO_FLT(x)		(((x) == GPIO_FILTER_DISABLE) || \
-                                 ((x) == GPIO_FILTER_ENABLE))
-#define IS_GPIO_TYPE(x)		(((x) == GPIO_TYPE_TTL) || \
-                                 ((x) == GPIO_TYPE_CMOS))
-#define IS_TRIGGER_STYLE(x)	(((x) == EXTI_TRIGGER_RISING_EDGE)   || \
-                                 ((x) == EXTI_TRIGGER_TRAILING_EDGE) || \
-                                 ((x) == EXTI_TRIGGER_BOTH_EDGE))
-#define IS_EXTI_FLTCKS_TYPE(x)	(((x) == EXTI_FILTER_CLOCK_10K) || \
-                                 ((x) == EXTI_FILTER_CLOCK_32K))
-#define IS_GPIO_FUNC(x)		((x) <= 7)
-/**
-  * @}
-  */
-
-/** @addtogroup GPIO_Public_Functions
-  * @{
-  */
-
-/** @addtogroup GPIO_Public_Functions_Group1
-  * @{
-  */
-void gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init);
-void gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin);
-void gpio_func_default(GPIO_TypeDef *GPIOx);
-void gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init);
-/**
-  * @}
-  */
-
-/** @addtogroup GPIO_Public_Functions_Group2
-  * @{
-  */
-uint8_t gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
-void gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val);
-void gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
-void gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin);
-void gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
-uint16_t gpio_read_port(GPIO_TypeDef *GPIOx);
-void gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val);
-/**
-  * @}
-  */
-
-/** @addtogroup GPIO_Public_Functions_Group3
-  * @{
-  */
-void gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status);
-flag_status_t gpio_exti_get_flag_status(uint16_t pin);
-void gpio_exti_clear_flag_status(uint16_t pin);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_GPIO_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_i2c.h

@@ -1,513 +0,0 @@
-/**
- *********************************************************************************
- *
- * @file    ald_i2c.h
- * @brief   Header file of I2C driver
- *
- * @version V1.0
- * @date    15 Nov 2017
- * @author  AE Team
- * @note
- *
- * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
- *
- ********************************************************************************
- */
-
-#ifndef __ALD_I2C_H__
-#define __ALD_I2C_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-#include "ald_cmu.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup I2C
-  * @{
-  */
-
-/** @defgroup I2C_Public_Types I2C Public Types
-  * @{
-  */
-/**
-  * @brief I2C Error Code
-  */
-typedef enum {
-	I2C_ERROR_NONE    = 0x0, 	/**< No error */
-	I2C_ERROR_BERR    = 0x1, 	/**< Berr error */
-	I2C_ERROR_ARLO    = 0x2, 	/**< Arlo error */
-	I2C_ERROR_AF      = 0x4, 	/**< Af error */
-	I2C_ERROR_OVR     = 0x8, 	/**< Ovr error */
-	I2C_ERROR_DMA     = 0x10,	/**< Dma error */
-	I2C_ERROR_TIMEOUT = 0x20,	/**< Timeout error */
-} i2c_error_t;
-
-/**
-  * @brief I2C state structure definition
-  */
-typedef enum {
-	I2C_STATE_RESET   = 0x0, 	/**< Peripheral is not yet Initialized */
-	I2C_STATE_READY   = 0x1,	/**< Peripheral Initialized and ready for use */
-	I2C_STATE_BUSY    = 0x2,	/**< An internal process is ongoing */
-	I2C_STATE_BUSY_TX = 0x3,	/**< Data Transmission process is ongoing */
-	I2C_STATE_BUSY_RX = 0x4,	/**< Data Reception process is ongoing */
-	I2C_STATE_TIMEOUT = 0x5,	/**< timeout state */
-	I2C_STATE_ERROR   = 0x6,	/**< Error */
-} i2c_state_t;
-
-/**
-  * @brief I2C Duty Cycle
-  */
-typedef enum {
-	I2C_DUTYCYCLE_2    = 0x0,   	/**< duty cycle is 2 */
-	I2C_DUTYCYCLE_16_9 = 0x4000,	/**< duty cycle is 16/9 */
-} i2c_duty_t;
-
-/**
-  * @brief I2C Addressing Mode
-  */
-typedef enum {
-	I2C_ADDR_7BIT  = 0x1,	/**< 7 bit address */
-	I2C_ADDR_10BIT = 0x2,	/**< 10 bit address */
-} i2c_addr_t;
-
-/**
-  * @brief I2C Dual Addressing Mode
-  */
-typedef enum {
-	I2C_DUALADDR_DISABLE = 0x0,	/**< dual address is disable */
-	I2C_DUALADDR_ENABLE  = 0x1,	/**< dual address is enable */
-} i2c_dual_addr_t;
-
-/**
-  * @brief I2C General Call Addressing mode
-  */
-typedef enum {
-	I2C_GENERALCALL_DISABLE = 0x0, 	/**< feneral call address is disable */
-	I2C_GENERALCALL_ENABLE  = 0x40,	/**< feneral call address is enable */
-} i2c_general_addr_t;
-
-/**
-  * @brief I2C Nostretch Mode
-  */
-typedef enum {
-	I2C_NOSTRETCH_DISABLE = 0x0, 	/**< Nostretch disable */
-	I2C_NOSTRETCH_ENABLE  = 0x80,	/**< Nostretch enable */
-} i2c_nostretch_t;
-
-/**
-  * @brief I2C Memory Address Size
-  */
-typedef enum {
-	I2C_MEMADD_SIZE_8BIT  = 0x1,	/**< 8 bit memory address size */
-	I2C_MEMADD_SIZE_16BIT = 0x10	/**< 10 bit memory address size */
-} i2c_addr_size_t;
-
-/**
-  * @brief I2C Flag Definition
-  */
-typedef enum {
-	I2C_FLAG_SB         = (1U << 0),
-	I2C_FLAG_ADDR       = (1U << 1),
-	I2C_FLAG_BTF        = (1U << 2),
-	I2C_FLAG_ADD10      = (1U << 3),
-	I2C_FLAG_STOPF      = (1U << 4),
-	I2C_FLAG_RXNE       = (1U << 6),
-	I2C_FLAG_TXE        = (1U << 7),
-	I2C_FLAG_BERR       = (1U << 8),
-	I2C_FLAG_ARLO       = (1U << 9),
-	I2C_FLAG_AF         = (1U << 10),
-	I2C_FLAG_OVR        = (1U << 11),
-	I2C_FLAG_PECERR     = (1U << 12),
-	I2C_FLAG_TIMEOUT    = (1U << 14),
-	I2C_FLAG_SMBALERT   = (1U << 15),
-	I2C_FLAG_MSL        = (1U << 16),
-	I2C_FLAG_BUSY       = (1U << 17),
-	I2C_FLAG_TRA        = (1U << 18),
-	I2C_FLAG_GENCALL    = (1U << 20),
-	I2C_FLAG_SMBDEFAULT = (1U << 21),
-	I2C_FLAG_SMBHOST    = (1U << 22),
-	I2C_FLAG_DUALF      = (1U << 23),
-} i2c_flag_t;
-
-/**
-  * @brief I2C mode structure definition
-  */
-typedef enum
-{
-	I2C_MODE_NONE   = 0x0, 	/**< No I2C communication on going */
-	I2C_MODE_MASTER = 0x10,	/**< I2C communication is in Master mode */
-	I2C_MODE_SLAVE  = 0x20,	/**< I2C communication is in Slave mode */
-	I2C_MODE_MEM    = 0x40,	/**< I2C communication is in Memory mode */
-} i2c_mode_t;
-
-/**
-  * @brief I2C Clock
-  */
-typedef enum {
-	I2C_STANDARD_MODE_MAX_CLK = 100000,	/**< Standard mode clock */
-	I2C_FAST_MODE_MAX_CLK     = 400000,	/**< Fast mode clock */
-} i2c_clock_t;
-
-/**
-  * @brief Interrupt Configuration Definition
-  */
-typedef enum {
-	I2C_IT_BUF = (1U << 10),	/**< Buffer interrupt */
-	I2C_IT_EVT = (1U << 9), 	/**< Event interrupt */
-	I2C_IT_ERR = (1U << 8), 	/**< Error interrupt */
-} i2c_interrupt_t;
-
-/**
-  * @brief I2C CON1 Register
-  */
-typedef enum {
-	I2C_CON1_PEN    = (1U << 0), 	/**< PEN BIT */
-	I2C_CON1_PMOD   = (1U << 1), 	/**< PMOD BIT */
-	I2C_CON1_SMBMOD = (1U << 3), 	/**< SMBMOD  BIT */
-	I2C_CON1_ARPEN  = (1U << 4), 	/**< ARPEN BIT */
-	I2C_CON1_PECEN  = (1U << 5), 	/**< PECEN BIT */
-	I2C_CON1_GCEN   = (1U << 6), 	/**< GCEN  BIT */
-	I2C_CON1_DISCS  = (1U << 7), 	/**< DISCS BIT */
-	I2C_CON1_START  = (1U << 8), 	/**< START BIT */
-	I2C_CON1_STOP   = (1U << 9), 	/**< STOP BIT */
-	I2C_CON1_ACKEN  = (1U << 10),	/**< ACKEN  BIT */
-	I2C_CON1_POSAP  = (1U << 11),	/**< POSAP BIT */
-	I2C_CON1_TRPEC  = (1U << 12),	/**< TRPEC  BIT */
-	I2C_CON1_ALARM  = (1U << 13),	/**< ALARM BIT */
-	I2C_CON1_SRST   = (1U << 15),	/**< SRST BIT */
-} i2c_con1_t;
-
-/**
-  * @brief I2C CON2 Register
-  */
-typedef enum {
-	I2C_CON2_CLKF    =  0x3F,     	/**< CLKF BITS */
-	I2C_CON2_CLKF_0  = (1U << 0), 	/**< CLKF_0 BIT */
-	I2C_CON2_CLKF_1  = (1U << 1), 	/**< CLKF_1 BIT */
-	I2C_CON2_CLKF_2  = (1U << 2), 	/**< CLKF_2 BIT */
-	I2C_CON2_CLKF_3  = (1U << 3), 	/**< CLKF_3 BIT */
-	I2C_CON2_CLKF_4  = (1U << 4), 	/**< CLKF_4 BIT */
-	I2C_CON2_CLKF_5  = (1U << 5), 	/**< CLKF_5 BIT */
-	I2C_CON2_ERRIE   = (1U << 8), 	/**< ERRIE BIT */
-	I2C_CON2_EVTIE   = (1U << 9), 	/**< EVTIE BIT */
-	I2C_CON2_BUFIE   = (1U << 10),	/**< BUFIE BIT */
-	I2C_CON2_DMAEN   = (1U << 11),	/**< DMAEN BIT */
-	I2C_CON2_LDMA    = (1U << 12),	/**< LDMA BIT */
-} i2c_con2_t;
-
-/**
-  * @brief I2C ADDR1 Register
-  */
-typedef enum {
-	I2C_ADDR1_ADDH0   = (1U << 0), 	/**< ADDH0 BIT */
-	I2C_ADDR1_ADDH1   = (1U << 1), 	/**< ADDH1 BIT */
-	I2C_ADDR1_ADDH2   = (1U << 2), 	/**< ADDH2 BIT */
-	I2C_ADDR1_ADDH3   = (1U << 3), 	/**< ADDH3 BIT */
-	I2C_ADDR1_ADDH4   = (1U << 4), 	/**< ADDH4 BIT */
-	I2C_ADDR1_ADDH5   = (1U << 5), 	/**< ADDH5 BIT */
-	I2C_ADDR1_ADDH6   = (1U << 6), 	/**< ADDH6 BIT */
-	I2C_ADDR1_ADDH7   = (1U << 7), 	/**< ADDH7 BIT */
-	I2C_ADDR1_ADDH8   = (1U << 8), /**< ADDH8 BIT */
-	I2C_ADDR1_ADDH9   = (1U << 9),	/**< ADDH9 BIT */
-	I2C_ADDR1_ADDTYPE = (1U << 15),	/**< ADDTYPE BIT */
-} i2c_addr1_t;
-
-/**
-  * @brief I2C ADDR2 Register
-  */
-typedef enum {
-	I2C_ADDR2_DUALEN = (1U << 0),	/**< DUALEN BIT */
-	I2C_ADDR2_ADD    = (1U << 1),	/**< ADD BIT */
-} i2c_addr2_t;
-
-/**
-  * @brief I2C STAT1 Register
-  */
-typedef enum {
-	I2C_STAT1_SB        = (1U << 0), 	/**< SB BIT */
-	I2C_STAT1_ADDR      = (1U << 1), 	/**< ADDR  BIT */
-	I2C_STAT1_BTC       = (1U << 2), 	/**< BTC BIT */
-	I2C_STAT1_SENDADD10 = (1U << 3), 	/**< SENDADD10 BIT */
-	I2C_STAT1_DETSTP    = (1U << 4), 	/**< DETSTP BIT */
-	I2C_STAT1_RXBNE     = (1U << 6), 	/**< RXBNE BIT */
-	I2C_STAT1_TXBE      = (1U << 7), 	/**< TXBE BIT */
-	I2C_STAT1_BUSERR    = (1U << 8), 	/**< BUSERR BIT */
-	I2C_STAT1_LARB      = (1U << 9), 	/**< LARB BIT */
-	I2C_STAT1_ACKERR    = (1U << 10),	/**< ACKERR BIT */
-	I2C_STAT1_ROUERR    = (1U << 11),	/**< ROUERR BIT */
-	I2C_STAT1_PECERR    = (1U << 12),	/**< PECERR BIT */
-	I2C_STAT1_SMBTO     = (1U << 14),	/**< SMBTO BIT */
-	I2C_STAT1_SMBALARM  = (1U << 15),	/**< SMBALARM BIT */
-} i2c_stat1_t;
-
-/**
-  * @brief I2C STAT2 Register
-  */
-typedef enum {
-	I2C_STAT2_MASTER = (1U << 0),	/**< MASTER BIT */
-	I2C_STAT2_BSYF   = (1U << 1),	/**< BSYF  BIT */
-	I2C_STAT2_TRF    = (1U << 2),	/**< TRF BIT */
-	I2C_STAT2_RXGCF  = (1U << 4),	/**< RXGCF BIT */
-	I2C_STAT2_SMBDEF = (1U << 5),	/**< SMBDEF BIT */
-	I2C_STAT2_SMBHH  = (1U << 6),	/**< SMBHH BIT */
-	I2C_STAT2_DUALF  = (1U << 7),	/**< DMF BIT */
-	I2C_STAT2_PECV   = (1U << 8),	/**< PECV BIT */
-} i2c_stat2_t;
-
-/**
-  * @brief I2C CKCFG Register
-  */
-typedef enum {
-	I2C_CKCFG_CLKSET =  0xFFF,    	/**< CLKSET BITS */
-	I2C_CKCFG_DUTY   = (1U << 14),	/**< DUTY BIT */
-	I2C_CKCFG_CLKMOD = (1U << 15),	/**< CLKMOD BIT */
-} i2c_ckcfg_t;
-
-/**
-  * @brief I2C RT Register
-  */
-typedef enum {
-	I2C_RT_RISET = 0x3F,	/**< RISET BITS */
-} i2c_trise_t;
-
-/**
- * @brief I2C Configuration Structure definition
- */
-typedef struct {
-	uint32_t clk_speed;                	/**< Specifies the clock frequency */
-	i2c_duty_t duty;			/**< Specifies the I2C fast mode duty cycle */
-	uint32_t own_addr1;               	/**< Specifies the first device own address */
-	i2c_addr_t addr_mode;			/**< Specifies addressing mode */
-	i2c_dual_addr_t dual_addr;		/**< Specifies if dual addressing mode is selected */
-	uint32_t own_addr2;               	/**< Specifies the second device own address */
-	i2c_general_addr_t general_call;	/**< Specifies if general call mode is selected */
-	i2c_nostretch_t no_stretch;     	/**< Specifies if nostretch mode is selected */
-} i2c_init_t;
-
-/**
-  * @brief  I2C handle Structure definition
-  */
-typedef struct i2c_handle_s {
-	I2C_TypeDef *perh;       	/**< I2C registers base address */
-	i2c_init_t init;         	/**< I2C communication parameters */
-	uint8_t *p_buff;         	/**< Pointer to I2C transfer buffer */
-	uint16_t xfer_size;      	/**< I2C transfer size */
-	__IO uint16_t xfer_count;	/**< I2C transfer counter */
-#ifdef ALD_DMA
-	dma_handle_t hdmatx;		/**< I2C Tx DMA handle parameters */
-	dma_handle_t hdmarx;		/**< I2C Rx DMA handle parameters */
-#endif
-	lock_state_t lock;       	/**< I2C locking object */
-	__IO i2c_state_t state;  	/**< I2C communication state */
-	__IO i2c_mode_t mode;    	/**< I2C communication mode */
-	__IO uint32_t error_code;	/**< I2C Error code */
-
-	void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg);	/**< Master Tx completed callback */
-	void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg);	/**< Master Rx completed callback */
-	void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); 	/**< Slave Tx completed callback */
-	void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); 	/**< Slave Rx completed callback */
-	void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg);   	/**< Tx to Memory completed callback */
-	void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg);   	/**< Rx from Memory completed callback */
-	void (*error_callback)(struct i2c_handle_s *arg);    	/**< Error callback */
-} i2c_handle_t;
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Public_Macro I2C Public Macros
-  * @{
-  */
-#define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET)
-#define I2C_CLEAR_ADDRFLAG(x)		\
-do {					\
-	__IO uint32_t tmpreg;		\
-	tmpreg = (x)->perh->STAT1;	\
-	tmpreg = (x)->perh->STAT2;	\
-	UNUSED(tmpreg);			\
-} while (0)
-#define __I2C_CLEAR_STOPFLAG(x)					\
-do {								\
-	__IO uint32_t tmpreg;					\
-	tmpreg = (x)->perh->STAT1;				\
-	tmpreg = SET_BIT((x)->perh->CON1, I2C_CON1_PEN);	\
-	UNUSED(tmpreg);						\
-} while (0)
-#define I2C_ENABLE(x)  (SET_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK))
-#define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Private_Macro I2C Private Macros
-  * @{
-  */
-#define IS_I2C_TYPE(x)						(((x) == I2C0) || \
-								 ((x) == I2C1))
-#define IS_I2C_ADDRESSING_MODE(x)				(((x) == I2C_ADDR_7BIT) || \
-								 ((x) == I2C_ADDR_10BIT))
-#define IS_I2C_DUAL_ADDRESS(x)					(((x) == I2C_DUALADDR_DISABLE) || \
-								 ((x) == I2C_DUALADDR_ENABLE))
-#define IS_I2C_GENERAL_CALL(x)					(((x) == I2C_GENERALCALL_DISABLE) || \
-								 ((x) == I2C_GENERALCALL_ENABLE))
-#define IS_I2C_MEMADD_size(x)					(((x) == I2C_MEMADD_SIZE_8BIT) || \
-								 ((x) == I2C_MEMADD_SIZE_16BIT))
-#define IS_I2C_NO_STRETCH(x)					(((x) == I2C_NOSTRETCH_DISABLE) || \
-								 ((x) == I2C_NOSTRETCH_ENABLE))
-#define IS_I2C_OWN_ADDRESS1(x)					(((x) & (uint32_t)(0xFFFFFC00)) == 0)
-#define IS_I2C_OWN_ADDRESS2(x)					(((x) & (uint32_t)(0xFFFFFF01)) == 0)
-#define IS_I2C_CLOCK_SPEED(x)					(((x) > 0) && ((x) <= I2C_FAST_MODE_MAX_CLK))
-#define IS_I2C_DUTY_CYCLE(x)					(((x) == I2C_DUTYCYCLE_2) || \
-								 ((x) == I2C_DUTYCYCLE_16_9))
-#define IS_I2C_IT_TYPE(x)					(((x) == I2C_IT_BUF) || \
-								 ((x) == I2C_IT_EVT) || \
-								 ((x) == I2C_IT_ERR))
-#define IS_I2C_FLAG(x)						(((x) == I2C_FLAG_SB)         || \
-								 ((x) == I2C_FLAG_ADDR)       || \
-								 ((x) == I2C_FLAG_BTF)        || \
-								 ((x) == I2C_FLAG_ADD10)      || \
-								 ((x) == I2C_FLAG_STOPF)      || \
-								 ((x) == I2C_FLAG_RXNE)       || \
-								 ((x) == I2C_FLAG_TXE)        || \
-								 ((x) == I2C_FLAG_BERR)       || \
-								 ((x) == I2C_FLAG_ARLO)       || \
-								 ((x) == I2C_FLAG_AF)         || \
-								 ((x) == I2C_FLAG_OVR)        || \
-								 ((x) == I2C_FLAG_PECERR)     || \
-								 ((x) == I2C_FLAG_TIMEOUT)    || \
-								 ((x) == I2C_FLAG_SMBALERT)   || \
-								 ((x) == I2C_FLAG_MSL)        || \
-								 ((x) == I2C_FLAG_BUSY)       || \
-								 ((x) == I2C_FLAG_TRA)        || \
-								 ((x) == I2C_FLAG_GENCALL)    || \
-								 ((x) == I2C_FLAG_SMBDEFAULT) || \
-								 ((x) == I2C_FLAG_SMBHOST)    || \
-								 ((x) == I2C_FLAG_DUALF))
-
-#define I2C_FREQ_RANGE(x)					((x) / 1000000)
-#define I2C_RISE_TIME(x, u)					(((u) <= I2C_STANDARD_MODE_MAX_CLK) ? ((x) + 1) :\
-        ((((x) * 300) / 1000) + 1))
-#define I2C_SPEED_STANDARD(x, y)				(((((x) / ((y) << 1)) & I2C_CKCFG_CLKSET) < 4) ? 4:\
-	((x) / ((y) << 1)))
-#define I2C_SPEED_FAST(x, y, z)					(((z) == I2C_DUTYCYCLE_2) ? ((x) / ((y) * 3)) :\
-        (((x) / ((y) * 25)) | I2C_DUTYCYCLE_16_9))
-#define I2C_SPEED(x, y, z)					(((y) <= 100000) ? (I2C_SPEED_STANDARD((x), (y))) :\
-	((I2C_SPEED_FAST((x), (y), (z)) & I2C_CKCFG_CLKSET) == 0) ? 1 : \
-        ((I2C_SPEED_FAST((x), (y), (z))) | I2C_CKCFG_CLKMOD))
-#define I2C_MEM_ADD_MSB(x)					((uint8_t)((uint16_t)(((uint16_t)((x) &\
-        (uint16_t)(0xFF00))) >> 8)))
-#define I2C_MEM_ADD_LSB(x)					((uint8_t)((uint16_t)((x) & (uint16_t)(0x00FF))))
-#define I2C_7BIT_ADD_WRITE(x)					((uint8_t)((x) & (~I2C_ADDR1_ADDH0)))
-#define I2C_7BIT_ADD_READ(x)					((uint8_t)((x) | I2C_ADDR1_ADDH0))
-#define I2C_10BIT_ADDRESS(x)					((uint8_t)((uint16_t)((x) & (uint16_t)(0x00FF))))
-#define I2C_10BIT_HEADER_WRITE(x)				((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\
-        (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
-#define I2C_10BIT_HEADER_READ(x)				((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\
-       (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Public_Functions
-  * @{
-  */
-
-/** @addtogroup I2C_Public_Functions_Group1
-  * @{
-  */
-ald_status_t i2c_init(i2c_handle_t *hperh);
-ald_status_t i2c_reset(i2c_handle_t *hperh);
-
-/**
- * @}
- */
-
-/** @addtogroup I2C_Public_Functions_Group2
- * @{
- */
- /** Blocking mode: Polling */
-ald_status_t i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr,
-                                 uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr,
-                                uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                           i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                          i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout);
-
- /** Non-Blocking mode: Interrupt */
-ald_status_t i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size);
-ald_status_t i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size);
-ald_status_t i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size);
-ald_status_t i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size);
-ald_status_t i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                              i2c_addr_size_t add_size, uint8_t *buf, uint16_t size);
-ald_status_t i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                             i2c_addr_size_t add_size, uint8_t *buf, uint16_t size);
-
-#ifdef ALD_DMA
- /** Non-Blocking mode: DMA */
-ald_status_t i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr,
-                                     uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr,
-                                    uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size,
-                                 uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                                i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel);
-#endif
-/**
- * @}
- */
-
-/** @addtogroup I2C_Public_Functions_Group3
-  * @{
-  */
-i2c_state_t i2c_get_state(i2c_handle_t *hperh);
-uint32_t    i2c_get_error(i2c_handle_t *hperh);
-flag_status_t i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag);
-flag_status_t i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it);
-void i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag);
-/**
- * @}
- */
-
-/** @addtogroup I2C_Public_Functions_Group4
- * @{
- */
-void i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state);
-void i2c_ev_irq_handler(i2c_handle_t *hperh);
-void i2c_er_irq_handler(i2c_handle_t *hperh);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
-  * @}
-  */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_I2C_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lcd.h

@@ -1,496 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_lcd.h
-  * @brief   Header file of LCD module driver.
-  *
-  * @version V1.0
-  * @date    29 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  ********************************************************************************
-  */
-
-#ifndef __ALD_LCD_H__
-#define __ALD_LCD_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_cmu.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup LCD
-  * @{
-  */
-
-/** @defgroup LCD_Public_Types LCD Public Types
-  * @{
-  */
-/**
-  * @brief Lcd vlcd voltage type
-  */
-typedef enum {
-	LCD_VCHPS_3V2 = 0,	/**< 3.2V */
-	LCD_VCHPS_3V8 = 1,	/**< 3.8V */
-	LCD_VCHPS_4V8 = 2,	/**< 4.8V */
-	LCD_VCHPS_5V4 = 3,	/**< 5.4V */
-} lcd_vchps_t;
-
-/**
-  * @brief Lcd function type
-  */
-typedef enum {
-	LCD_FUNC_DISABLE = 0,	/**< Lcd's function disable */
-	LCD_FUNC_ENABLE  = 1,	/**< Lcd's function enable */
-} lcd_func_t;
-
-/**
-  * @brief Lcd voltage type
-  */
-typedef enum {
-	LCD_VSEL_VDD  = 0,	/**< VDD */
-	LCD_VSEL_CP   = 1,	/**< Charge pump output */
-	LCD_VSEL_VLCD = 2,	/**< VLCD input */
-} lcd_vsel_t;
-
-/**
-  * @brief Lcd resistance select bit
-  */
-typedef enum {
-	LCD_RES_1MOHM = 0,	/**< 1M ohm */
-	LCD_RES_2MOHM = 1,	/**< 2M ohm */
-	LCD_RES_3MOHM = 2,	/**< 3M ohm */
-} lcd_res_t;
-
-/**
-  * @brief Lcd bias selector
-  */
-typedef enum {
-	LCD_BIAS_1_4 = 0,	/**< 1/4 bias */
-	LCD_BIAS_1_2 = 2,	/**< 1/2 bias */
-	LCD_BIAS_1_3 = 3,	/**< 1/3 bias */
-} lcd_bias_t;
-
-/**
-  * @brief Lcd duty
-  */
-typedef enum {
-	LCD_DUTY_STATIC = 0,	/**< Static duty (COM0) */
-	LCD_DUTY_1_2    = 1,	/**< 1/2 duty (COM0~COM1) */
-	LCD_DUTY_1_3    = 2,	/**< 1/3 duty (COM0~COM2) */
-	LCD_DUTY_1_4    = 3,	/**< 1/4 duty (COM0~COM3) */
-	LCD_DUTY_1_6    = 4,	/**< 1/6 duty (COM0~COM5) */
-	LCD_DUTY_1_8    = 5,	/**< 1/8 duty (COM0~COM7) */
-} lcd_duty_t;
-
-/**
-  * @brief Lcd prescaler
-  */
-typedef enum {
-	LCD_PRS_1     = 0, 	/**< CLKPRS = LCDCLK / 1 */
-	LCD_PRS_2     = 1, 	/**< CLKPRS = LCDCLK / 2 */
-	LCD_PRS_4     = 2, 	/**< CLKPRS = LCDCLK / 4 */
-	LCD_PRS_8     = 3, 	/**< CLKPRS = LCDCLK / 8 */
-	LCD_PRS_16    = 4, 	/**< CLKPRS = LCDCLK / 16 */
-	LCD_PRS_32    = 5, 	/**< CLKPRS = LCDCLK / 32 */
-	LCD_PRS_64    = 6, 	/**< CLKPRS = LCDCLK / 64 */
-	LCD_PRS_128   = 7, 	/**< CLKPRS = LCDCLK / 128 */
-	LCD_PRS_256   = 8, 	/**< CLKPRS = LCDCLK / 256 */
-	LCD_PRS_512   = 9, 	/**< CLKPRS = LCDCLK / 512 */
-	LCD_PRS_1024  = 10,	/**< CLKPRS = LCDCLK / 1024 */
-	LCD_PRS_2048  = 11,	/**< CLKPRS = LCDCLK / 2048 */
-	LCD_PRS_4096  = 12,	/**< CLKPRS = LCDCLK / 4096 */
-	LCD_PRS_8192  = 13,	/**< CLKPRS = LCDCLK / 8192 */
-	LCD_PRS_16384 = 14,	/**< CLKPRS = LCDCLK / 16384 */
-	LCD_PRS_32768 = 15,	/**< CLKPRS = LCDCLK / 32768 */
-} lcd_prs_t;
-
-/**
-  * @brief Lcd divider
-  */
-typedef enum {
-	LCD_DIV_16 = 0, 	/**< DIVCLK = CLKPRS / 16 */
-	LCD_DIV_17 = 1, 	/**< DIVCLK = CLKPRS / 17 */
-	LCD_DIV_18 = 2, 	/**< DIVCLK = CLKPRS / 18 */
-	LCD_DIV_19 = 3, 	/**< DIVCLK = CLKPRS / 19 */
-	LCD_DIV_20 = 4, 	/**< DIVCLK = CLKPRS / 20 */
-	LCD_DIV_21 = 5, 	/**< DIVCLK = CLKPRS / 21 */
-	LCD_DIV_22 = 6, 	/**< DIVCLK = CLKPRS / 22 */
-	LCD_DIV_23 = 7, 	/**< DIVCLK = CLKPRS / 23 */
-	LCD_DIV_24 = 8, 	/**< DIVCLK = CLKPRS / 24 */
-	LCD_DIV_25 = 9, 	/**< DIVCLK = CLKPRS / 25 */
-	LCD_DIV_26 = 10,	/**< DIVCLK = CLKPRS / 26 */
-	LCD_DIV_27 = 11,	/**< DIVCLK = CLKPRS / 27 */
-	LCD_DIV_28 = 12,	/**< DIVCLK = CLKPRS / 28 */
-	LCD_DIV_29 = 13,	/**< DIVCLK = CLKPRS / 29 */
-	LCD_DIV_30 = 14,	/**< DIVCLK = CLKPRS / 30 */
-	LCD_DIV_31 = 15,	/**< DIVCLK = CLKPRS / 31 */
-} lcd_div_t;
-
-/**
-  * @brief Lcd blink mode
-  */
-typedef enum {
-	LCD_BLINK_OFF           = 0,	/**< Blink disabled */
-	LCD_BLINK_SEG0_COM0     = 1,	/**< Blink enabled on SEG0, COM0 */
-	LCD_BLINK_SEG0_COMX2    = 2,	/**< Blink enabled on SEG0, COMx2 */
-	LCD_BLINK_ALLSEG_ALLCOM = 3,	/**< Blink enabled on all SEG and all COM */
-} lcd_blink_t;
-
-/**
-  * @brief Lcd blink frequency
-  */
-typedef enum {
-	LCD_BLFRQ_8    = 0,	/**< DIVCLK / 8 */
-	LCD_BLFRQ_16   = 1,	/**< DIVCLK / 16 */
-	LCD_BLFRQ_32   = 2,	/**< DIVCLK / 32 */
-	LCD_BLFRQ_64   = 3,	/**< DIVCLK / 64 */
-	LCD_BLFRQ_128  = 4,	/**< DIVCLK / 128 */
-	LCD_BLFRQ_256  = 5,	/**< DIVCLK / 256 */
-	LCD_BLFRQ_512  = 6,	/**< DIVCLK / 512 */
-	LCD_BLFRQ_1024 = 7,	/**< DIVCLK / 1024 */
-} lcd_blfrq_t;
-
-/**
-  * @brief Lcd dead time
-  */
-typedef enum {
-	LCD_DEAD_TIME_NONE     = 0,	/**< No dead time */
-	LCD_DEAD_TIME_1_DIVCLK = 1,	/**< Dead time is 1 divclk */
-	LCD_DEAD_TIME_2_DIVCLK = 2,	/**< Dead time is 2 divclk */
-	LCD_DEAD_TIME_3_DIVCLK = 3,	/**< Dead time is 3 divclk */
-	LCD_DEAD_TIME_4_DIVCLK = 4,	/**< Dead time is 4 divclk */
-	LCD_DEAD_TIME_5_DIVCLK = 5,	/**< Dead time is 5 divclk */
-	LCD_DEAD_TIME_6_DIVCLK = 6,	/**< Dead time is 6 divclk */
-	LCD_DEAD_TIME_7_DIVCLK = 7,	/**< Dead time is 7 divclk */
-} lcd_dead_t;
-
-/**
-  * @brief Lcd pulse keep time
-  */
-typedef enum {
-	LCD_PON_NONE     = 0,	/**< No pulse keep time */
-	LCD_PON_1_PRSCLK = 1,	/**< Pulse keep 1 prsclk */
-	LCD_PON_2_PRSCLK = 2,	/**< Pulse keep 2 prsclk */
-	LCD_PON_3_PRSCLK = 3,	/**< Pulse keep 3 prsclk */
-	LCD_PON_4_PRSCLK = 4,	/**< Pulse keep 4 prsclk */
-	LCD_PON_5_PRSCLK = 5,	/**< Pulse keep 5 prsclk */
-	LCD_PON_6_PRSCLK = 6,	/**< Pulse keep 6 prsclk */
-	LCD_PON_7_PRSCLK = 7,	/**< Pulse keep 7 prsclk */
-} lcd_pluse_on_t;
-
-/**
-  * @brief Lcd vgs select
-  */
-typedef enum {
-	LCD_VGS_0  = 0, 	/**< Grey level display voltage is 30/45 vlcd */
-	LCD_VGS_1  = 1, 	/**< Grey level display voltage is 31/45 vlcd */
-	LCD_VGS_2  = 2, 	/**< Grey level display voltage is 32/45 vlcd */
-	LCD_VGS_3  = 3, 	/**< Grey level display voltage is 33/45 vlcd */
-	LCD_VGS_4  = 4, 	/**< Grey level display voltage is 34/45 vlcd */
-	LCD_VGS_5  = 5, 	/**< Grey level display voltage is 35/45 vlcd */
-	LCD_VGS_6  = 6, 	/**< Grey level display voltage is 36/45 vlcd */
-	LCD_VGS_7  = 7, 	/**< Grey level display voltage is 37/45 vlcd */
-	LCD_VGS_8  = 8, 	/**< Grey level display voltage is 38/45 vlcd */
-	LCD_VGS_9  = 9, 	/**< Grey level display voltage is 39/45 vlcd */
-	LCD_VGS_10 = 10,	/**< Grey level display voltage is 40/45 vlcd */
-	LCD_VGS_11 = 11,	/**< Grey level display voltage is 41/45 vlcd */
-	LCD_VGS_12 = 12,	/**< Grey level display voltage is 42/45 vlcd */
-	LCD_VGS_13 = 13,	/**< Grey level display voltage is 43/45 vlcd */
-	LCD_VGS_14 = 14,	/**< Grey level display voltage is 44/45 vlcd */
-	LCD_VGS_15 = 15,	/**< Grey level display voltage is equal to vlcd */
-} lcd_vgs_t;
-
-/**
-  * @brief Lcd wave choose
-  */
-typedef enum {
-	LCD_WAVE_A = 0,	/**< Wave type is A */
-	LCD_WAVE_B = 1,	/**< Wave type is B */
-} lcd_wfs_t;
-
-/**
-  * @brief Lcd status select bit
-  */
-typedef enum {
-	LCD_STATUS_RDY   = (1U << 0),	/**< VLCD voltage state flag */
-	LCD_STATUS_ENS   = (1U << 1),	/**< LCD Enable state flag*/
-	LCD_STATUS_UDR   = (1U << 2),	/**< Update display request state flag */
-	LCD_STATUS_FCRSF = (1U << 3),	/**< LCD frame control sync flag */
-	LCD_STATUS_ALL   = 0xFFFFFFF,	/**< All flag */
-} lcd_status_t;
-
-/**
-  * @brief Lcd interrupt type
-  */
-typedef enum {
-	LCD_IT_SOF = (1U << 0),	/**< Start of frame interrupt enable */
-	LCD_IT_UDD = (1U << 1),	/**< Update display done interrupt enable*/
-} lcd_it_t;
-
-/**
-  * @brief Lcd interrupt flag
-  */
-typedef enum {
-	LCD_FLAG_SOF = (1U << 0), /**< Start of frame interrupt enable flag*/
-	LCD_FLAG_UDD = (1U << 1), /**< Update display done interrupt enable flag*/
-} lcd_flag_t;
-
-/**
-  * @brief Lcd interrupt type
-  */
-typedef enum {
-	SEG_0_TO_31  = 0,	/**< Segment 0 to 31 to be set */
-	SEG_32_TO_59 = 1,	/**< Segment 32 to 59 to be set */
-} lcd_seg_t;
-
-/**
-  * @brief Lcd configure
-  */
-typedef struct
-{
-	lcd_vsel_t lcd_vsel;      	/**< Lcd power choose */
-	lcd_vchps_t lcd_vchps;    	/**< Charge pump voltage choose */
-	lcd_func_t lcd_vbufld;    	/**< Low drive mode function */
-	lcd_func_t lcd_vbufhd;    	/**< High drive mode function */
-	uint32_t lcd_dsld;        	/**< Low drive mode level */
-	uint32_t lcd_dshd;        	/**< High drive mode level */
-	lcd_res_t lcd_resld;      	/**< Low dirve mode resistance choose */
-	lcd_res_t lcd_reshd;      	/**< High dirve mode resistance choose */
-	lcd_bias_t lcd_bias;      	/**< LCD bias */
-	lcd_duty_t lcd_duty;      	/**< LCD duty */
-	lcd_wfs_t lcd_wfs;        	/**< Wave choose */
-	lcd_prs_t lcd_prs;        	/**< Lcd clock prs */
-	lcd_div_t lcd_div;        	/**< Lcd div */
-	lcd_dead_t lcd_dead;      	/**< Lcd dead time */
-	lcd_pluse_on_t lcd_pon;   	/**< Lcd pluse on time */
-	lcd_vgs_t lcd_vgs;        	/**< Lcd gray level display voltage */
-	cmu_lcd_clock_sel_t clock;	/**< Lcd clock choose */
-} lcd_init_t;
-
-/**
-  * @brief  Lcd handle Structure definition
-  */
-typedef struct lcd_handle_s {
-	LCD_TypeDef *perh;	/**< LCD registers base address */
-	lcd_init_t init;  	/**< LCD initialize parameters */
-	lock_state_t lock;	/**< Locking object */
-
-	void (*display_cplt_cbk)(struct lcd_handle_s *arg);	/**< Display completed callback */
-	void (*frame_start_cbk)(struct lcd_handle_s *arg); 	/**< Frame start callback */
-} lcd_handle_t;
-
-/**
-  * @}
-  */
-
-/** @defgroup LCD_Public_Macro LCD Public Macros
-  * @{
-  */
-#define LCD_HD_ENABLE(x)	(SET_BIT((x)->perh->FCR, LCD_FCR_HD_MSK))
-#define LCD_HD_DISABLE(x)	(CLEAR_BIT((x)->perh->FCR, LCD_FCR_HD_MSK))
-/**
-  * @}
-  */
-
-/**
-  * @defgroup LCD_Private_Macros LCD Private Macros
-  * @{
-  */
-#define IS_LCD_PERH_TYPE(x)	((x) == LCD)
-#define IS_LCD_VCHPS_TYPE(x)    (((x) == LCD_VCHPS_3V2) || \
-				 ((x) == LCD_VCHPS_3V8) || \
-				 ((x) == LCD_VCHPS_4V8) || \
-				 ((x) == LCD_VCHPS_5V4))
-#define IS_LCD_VSEL_TYPE(x)     (((x) == LCD_VSEL_VDD) || \
-				 ((x) == LCD_VSEL_CP)  || \
-				 ((x) == LCD_VSEL_VLCD))
-#define IS_LCD_FUNC_TYPE(x)	(((x) == LCD_FUNC_DISABLE) || \
-				 ((x) == LCD_FUNC_ENABLE))
-#define IS_LCD_LEVEL_TYPE(x)	(((x) > 0) | ((x) <= 0xF))
-#define IS_LCD_RES_TYPE(x)      (((x) == LCD_RES_1MOHM) || \
-				 ((x) == LCD_RES_2MOHM) || \
-				 ((x) == LCD_RES_3MOHM))
-#define IS_LCD_BIAS_TYPE(x)     (((x) == LCD_BIAS_1_4) || \
-				 ((x) == LCD_BIAS_1_2) || \
-				 ((x) == LCD_BIAS_1_3))
-#define IS_LCD_DUTY_TYPE(x)     (((x) == LCD_DUTY_STATIC) || \
-				 ((x) == LCD_DUTY_1_2)    || \
-				 ((x) == LCD_DUTY_1_3)    || \
-				 ((x) == LCD_DUTY_1_4)    || \
-				 ((x) == LCD_DUTY_1_6)    || \
-				 ((x) == LCD_DUTY_1_8))
-#define IS_LCD_WFS_TYPE(x)	(((x) == LCD_WAVE_A) || \
-				 ((x) == LCD_WAVE_B))
-#define IS_LCD_PRS_TYPE(x)      (((x) == LCD_PRS_1)     || \
-				 ((x) == LCD_PRS_2)     || \
-				 ((x) == LCD_PRS_4)     || \
-				 ((x) == LCD_PRS_8)     || \
-				 ((x) == LCD_PRS_16)    || \
-				 ((x) == LCD_PRS_32)    || \
-				 ((x) == LCD_PRS_64)    || \
-				 ((x) == LCD_PRS_128)   || \
-				 ((x) == LCD_PRS_256)   || \
-				 ((x) == LCD_PRS_512)   || \
-				 ((x) == LCD_PRS_1024)  || \
-				 ((x) == LCD_PRS_2048)  || \
-				 ((x) == LCD_PRS_4096)  || \
-				 ((x) == LCD_PRS_8192)  || \
-				 ((x) == LCD_PRS_16384) || \
-				 ((x) == LCD_PRS_32768))
-#define IS_LCD_DIV_TYPE(x)      (((x) == LCD_DIV_16) || \
-				 ((x) == LCD_DIV_17) || \
-				 ((x) == LCD_DIV_18) || \
-				 ((x) == LCD_DIV_19) || \
-				 ((x) == LCD_DIV_20) || \
-				 ((x) == LCD_DIV_21) || \
-				 ((x) == LCD_DIV_22) || \
-				 ((x) == LCD_DIV_23) || \
-				 ((x) == LCD_DIV_24) || \
-				 ((x) == LCD_DIV_25) || \
-				 ((x) == LCD_DIV_26) || \
-				 ((x) == LCD_DIV_27) || \
-				 ((x) == LCD_DIV_28) || \
-				 ((x) == LCD_DIV_29) || \
-				 ((x) == LCD_DIV_30) || \
-				 ((x) == LCD_DIV_31))
-#define IS_LCD_BLINK_MODE(x)    (((x) == LCD_BLINK_OFF)        || \
-				 ((x) == LCD_BLINK_SEG0_COM0)  || \
-				 ((x) == LCD_BLINK_SEG0_COMX2) || \
-				 ((x) == LCD_BLINK_ALLSEG_ALLCOM))
-#define IS_LCD_BLFRQ_TYPE(x)    (((x) == LCD_BLFRQ_8)   || \
-				 ((x) == LCD_BLFRQ_16)  || \
-				 ((x) == LCD_BLFRQ_32)  || \
-				 ((x) == LCD_BLFRQ_64)  || \
-				 ((x) == LCD_BLFRQ_128) || \
-				 ((x) == LCD_BLFRQ_256) || \
-				 ((x) == LCD_BLFRQ_512) || \
-				 ((x) == LCD_BLFRQ_1024))
-#define IS_LCD_STATUS_TYPE(x) 	(((x) == LCD_STATUS_RDY)   || \
-                                 ((x) == LCD_STATUS_ENS)   || \
-                                 ((x) == LCD_STATUS_UDR)   || \
-				 ((x) == LCD_STATUS_FCRSF) || \
-                                 ((x) == LCD_STATUS_ALL))
-#define IS_LCD_CLEARFLAG_TYPE(x)(((x) == LCD_FLAG_SOF) || \
-                                 ((x) == LCD_FLAG_UDD) || \
-                                 ((x) == LCD_STATUS_ALL))
-#define IS_LCD_IT_TYPE(x)      	(((x) == LCD_IT_SOF) || \
-                                 ((x) == LCD_IT_UDD))
-#define IS_LCD_FLAG_TYPE(x)	(((x) == LCD_FLAG_SOF) || \
-				 ((x) == LCD_FLAG_UDD))
-#define IS_LCD_SEG_TYPE(x)	(((x) == SEG_0_TO_31) || \
-				 ((x) == SEG_32_TO_59))
-#define IS_LCD_DEAD_TYPE(x)	(((x) == LCD_DEAD_TIME_NONE)     || \
-				 ((x) == LCD_DEAD_TIME_1_DIVCLK) || \
-				 ((x) == LCD_DEAD_TIME_2_DIVCLK) || \
-				 ((x) == LCD_DEAD_TIME_3_DIVCLK) || \
-				 ((x) == LCD_DEAD_TIME_4_DIVCLK) || \
-				 ((x) == LCD_DEAD_TIME_5_DIVCLK) || \
-				 ((x) == LCD_DEAD_TIME_6_DIVCLK) || \
-				 ((x) == LCD_DEAD_TIME_7_DIVCLK))
-#define IS_LCD_PON_TYPE(x)	(((x) == LCD_PON_NONE)     || \
-				 ((x) == LCD_PON_1_PRSCLK) || \
-				 ((x) == LCD_PON_2_PRSCLK) || \
-				 ((x) == LCD_PON_3_PRSCLK) || \
-				 ((x) == LCD_PON_4_PRSCLK) || \
-				 ((x) == LCD_PON_5_PRSCLK) || \
-				 ((x) == LCD_PON_6_PRSCLK) || \
-				 ((x) == LCD_PON_7_PRSCLK))
-#define IS_LCD_VGS_TYPE(x)	(((x) == LCD_VGS_0)  || \
-				 ((x) == LCD_VGS_1)  || \
-				 ((x) == LCD_VGS_2)  || \
-				 ((x) == LCD_VGS_3)  || \
-				 ((x) == LCD_VGS_4)  || \
-				 ((x) == LCD_VGS_5)  || \
-				 ((x) == LCD_VGS_6)  || \
-				 ((x) == LCD_VGS_7)  || \
-				 ((x) == LCD_VGS_8)  || \
-				 ((x) == LCD_VGS_9)  || \
-				 ((x) == LCD_VGS_10) || \
-				 ((x) == LCD_VGS_11) || \
-				 ((x) == LCD_VGS_12) || \
-				 ((x) == LCD_VGS_13) || \
-				 ((x) == LCD_VGS_14) || \
-				 ((x) == LCD_VGS_15))
-#define IS_LCD_BUFFER_TYPE(x)	((x) <= 15)
-
-/**
-  * @}
-  */
-
-/** @addtogroup LCD_Public_Functions
-  * @{
-  */
-
-/**
-  * @addtogroup LCD_Public_Functions_Group1
-  * @{
-  */
-/* Initialization and enable functions */
-ald_status_t lcd_init(lcd_handle_t *hperh);
-ald_status_t lcd_cmd(lcd_handle_t *hperh, type_func_t state);
-/**
-  * @}
-  */
-
-/**
-  * @addtogroup LCD_Public_Functions_Group2
-  * @{
-  */
-/* Config output and blink function */
-ald_status_t lcd_blink_config(lcd_handle_t *hperh, lcd_blink_t blink_mode, lcd_blfrq_t blink_freq);
-ald_status_t lcd_write(lcd_handle_t *hperh, uint8_t buf, uint32_t buf_data);
-ald_status_t lcd_write_seg(lcd_handle_t *hperh, lcd_seg_t seg, uint32_t seg_data);
-/**
-  * @}
-  */
-
-/**
-  * @addtogroup LCD_Public_Functions_Group3
-  * @{
-  */
-/* Query lcd status function */
-uint32_t lcd_get_status(lcd_handle_t *hperh, lcd_status_t lcd_flag);
-/**
-  * @}
-  */
-
-/**
-  * @addtogroup LCD_Public_Functions_Group4
-  * @{
-  */
-/* Interrupt function */
-ald_status_t lcd_interrupt_config(lcd_handle_t *hperh, lcd_it_t it, type_func_t state);
-flag_status_t lcd_get_it_status(lcd_handle_t *hperh, lcd_it_t it);
-it_status_t lcd_get_flag_status(lcd_handle_t *hperh, lcd_flag_t flag);
-ald_status_t lcd_clear_flag_status(lcd_handle_t *hperh, lcd_flag_t flag);
-void lcd_irq_handler(lcd_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_LCD_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lptim.h

@@ -1,358 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_lptim.c
-  * @brief   LPTIM module driver.
-  *	     This is the common part of the LPTIM initialization
-  *
-  * @version V1.0
-  * @date    09 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#ifndef __ALD_LPTIM_H__
-#define __ALD_LPTIM_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_cmu.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup LPTIM
-  * @{
-  */
-
-/** @defgroup LPTIM_Public_Types LPTIM Public Types
-  * @{
-  */
-
-/**
-  * @brief LPTIM clock select
-  */
-typedef enum {
-	LPTIM_CKSEL_INTERNAL = 0,	/**< Select internal clock */
-	LPTIM_CKSEL_EXTERNAL = 1,	/**< Select external clock */
-} lptim_cksel_t;
-
-/**
-  * @brief LPTIM clock pol
-  */
-typedef enum {
-	LPTIM_CKPOL_RISING  = 0,	/**< using rising edge */
-	LPTIM_CKPOL_FALLING = 1,	/**< using falling edge */
-} lptim_ckpol_t;
-
-/**
-  * @brief LPTIM clock fliter
-  */
-typedef enum {
-	LPTIM_CKFLT_0 = 0,	/**< not clock filter */
-	LPTIM_CKFLT_2 = 1,	/**< 2 cycle filter */
-	LPTIM_CKFLT_4 = 2,	/**< 4 cycle filter */
-	LPTIM_CKFLT_8 = 3,	/**< 8 cycle filter */
-} lptim_ckflt_t;
-
-/**
-  * @brief LPTIM trigger fliter
-  */
-typedef enum {
-	LPTIM_TRGFLT_0 = 0,	/**< not clock filter */
-	LPTIM_TRGFLT_2 = 1,	/**< 2 cycle filter */
-	LPTIM_TRGFLT_4 = 2,	/**< 4 cycle filter */
-	LPTIM_TRGFLT_8 = 3,	/**< 8 cycle filter */
-} lptim_trgflt_t;
-
-/**
-  * @brief LPTIM prescaler
-  */
-typedef enum {
-	LPTIM_PRESC_1   = 0,	/**< No prescaler is used */
-	LPTIM_PRESC_2   = 1,	/**< Clock is divided by 2 */
-	LPTIM_PRESC_4   = 2,	/**< Clock is divided by 4 */
-	LPTIM_PRESC_8   = 3,	/**< Clock is divided by 8 */
-	LPTIM_PRESC_16  = 4,	/**< Clock is divided by 16 */
-	LPTIM_PRESC_32  = 5,	/**< Clock is divided by 32 */
-	LPTIM_PRESC_64  = 6,	/**< Clock is divided by 64 */
-	LPTIM_PRESC_128 = 7,	/**< Clock is divided by 128 */
-} lptim_presc_t;
-
-/**
-  * @brief LPTIM trig select
-  */
-typedef enum {
-	LPTIM_TRIGSEL_EXT0 = 0,	/**< Trigger select external channel 0 */
-	LPTIM_TRIGSEL_EXT1 = 1,	/**< Trigger select external channel 1 */
-	LPTIM_TRIGSEL_EXT2 = 2,	/**< Trigger select external channel 2 */
-	LPTIM_TRIGSEL_EXT3 = 3,	/**< Trigger select external channel 3 */
-	LPTIM_TRIGSEL_EXT4 = 4,	/**< Trigger select external channel 4 */
-	LPTIM_TRIGSEL_EXT5 = 5,	/**< Trigger select external channel 5 */
-	LPTIM_TRIGSEL_EXT6 = 6,	/**< Trigger select external channel 6 */
-	LPTIM_TRIGSEL_EXT7 = 7,	/**< Trigger select external channel 7 */
-} lptim_trigsel_t;
-
-/**
-  * @brief LPTIM start mode select
-  */
-typedef enum {
-	LPTIM_MODE_SINGLE     = 0,	/**< Start single mode */
-	LPTIM_MODE_CONTINUOUS = 1,	/**< Start continuous mode */
-} lptim_mode_t;
-
-/**
-  * @brief LPTIM trig en
-  */
-typedef enum {
-	LPTIM_TRIGEN_SW      = 0,	/**< software trigger */
-	LPTIM_TRIGEN_RISING  = 1,	/**< rising edge trigger */
-	LPTIM_TRIGEN_FALLING = 2,	/**< falling edge trigger */
-	LPTIM_TRIGEN_BOTH    = 3,	/**< rising and falling edge trigger */
-} lptim_trigen_t;
-
-/**
-  * @brief LPTIM wave
-  */
-typedef enum {
-	LPTIM_WAVE_NONE   = 0,	/**< Output close */
-	LPTIM_WAVE_TOGGLE = 1,	/**< Output toggle */
-	LPTIM_WAVE_PULSE  = 2,	/**< Output pulse */
-	LPTIM_WAVE_PWM    = 3,	/**< Output PWM */
-} lptim_wave_t;
-
-/**
-  * @brief LPTIM interrupt
-  */
-typedef enum {
-	LPTIM_IT_CMPMAT  = 1,	/**< Compare interrupt bit */
-	LPTIM_IT_ARRMAT  = 2,	/**< Update interrupt bit */
-	LPTIM_IT_EXTTRIG = 4,	/**< external trigger interrupt bit */
-} lptim_it_t;
-
-/**
-  * @brief LPTIM Interrupt flag
-  */
-typedef enum {
-	LPTIM_FLAG_CMPMAT  = 1,	/**< Compare interrupt flag */
-	LPTIM_FLAG_ARRMAT  = 2,	/**< Update interrupt flag */
-	LPTIM_FLAG_EXTTRIG = 4,	/**< Update interrupt flag */
-} lptim_flag_t;
-
-/**
-  * @brief LPTIM state structures definition
-  */
-typedef enum {
-	LPTIM_STATE_RESET   = 0x00,	/**< Peripheral not yet initialized or disabled */
-	LPTIM_STATE_READY   = 0x01,	/**< Peripheral Initialized and ready for use */
-	LPTIM_STATE_BUSY    = 0x02,	/**< An internal process is ongoing */
-	LPTIM_STATE_TIMEOUT = 0x03,	/**< Timeout state */
-	LPTIM_STATE_ERROR   = 0x04,	/**< Reception process is ongoing */
-} lptim_state_t;
-
-/**
-  * @brief LPTIM Init Structure definition
-  */
-typedef struct {
-	lptim_presc_t psc;		/**< Specifies the prescaler value */
-	uint16_t arr;			/**< Specifies the update value */
-	uint16_t cmp;			/**< Specifies the compare value */
-	cmu_lp_perh_clock_sel_t clock;	/**< Specifies the clock choose */
-	lptim_mode_t mode;		/**< Specifies the start mode */
-} lptim_init_t;
-
-/**
-  * @brief LPTIM trigger Structure definition
-  */
-typedef struct {
-	lptim_trigen_t mode;	/**< Specifies the trigger mode */
-	lptim_trigsel_t sel;	/**< Specifies the trigger source select */
-} lptim_trigger_init_t;
-
-/**
-  * @brief LPTIM trigger Structure definition
-  */
-typedef struct {
-	lptim_cksel_t sel;	/**< Specifies the clock select */
-	lptim_ckpol_t polarity;	/**< Specifies the clock polarity */
-} lptim_clock_source_init_t;
-
-/**
-  * @brief  LPTIM Handle Structure definition
-  */
-typedef struct lptim_handle_s {
-	LPTIM_TypeDef *perh;	/**< Register base address */
-	lptim_init_t init;	/**< LPTIM Time required parameters */
-	lock_state_t lock;	/**< Locking object */
-	lptim_state_t state;	/**< LPTIM operation state */
-
-	void (*trig_cbk)(struct lptim_handle_s *arg);	/**< Trigger callback */
-	void (*update_cbk)(struct lptim_handle_s *arg);	/**< Update callback */
-	void (*cmp_cbk)(struct lptim_handle_s *arg);	/**< Compare callback */
-} lptim_handle_t;
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Public_Macros LPTIM Public Macros
-  * @{
-  */
-#define LPTIM_ENABLE(x)			(SET_BIT((x)->perh->CON1, LP16T_CON1_ENABLE_MSK))
-#define LPTIM_DISABLE(x)		(CLEAR_BIT((x)->perh->CON1, LP16T_CON1_ENABLE_MSK))
-#define LPTIM_CNTSTART(x)		(SET_BIT((x)->perh->CON1, LP16T_CON1_CNTSTRT_MSK))
-#define LPTIM_SNGSTART(x)		(SET_BIT((x)->perh->CON1, LP16T_CON1_SNGSTRT_MSK))
-#define LPTIM_UPDATE_ENABLE(x)		(SET_BIT((x)->perh->UPDATE, LP16T_UPDATE_UDIS_MSK))
-#define LPTIM_UPDATE_DISABLE(x)		(CLEAR_BIT((x)->perh->UPDATE, LP16T_UPDATE_UDIS_MSK))
-#define LPTIM_PRELOAD_IMM(x)		(SET_BIT((x)->perh->CR0, LP16T_CON0_PRELOAD_MSK))
-#define LPTIM_PRELOAD_WAIT(x)		(CLEAR_BIT((x)->perh->CR0, LP16T_CON0_PRELOAD_MSK))
-#define LPTIM_WAVEPOL_NORMAL(x)		(MODIFY_REG((x)->perh->CR0, LP16T_CON0_WAVE_MSK, 0 << LP16T_CON0_WAVE_POSS))
-#define LPTIM_WAVEPOL_INVERSE(x)	(MODIFY_REG((x)->perh->CR0, LP16T_CON0_WAVE_MSK, 1 << LP16T_CON0_WAVE_POSS))
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Private_Macros   LPTIM Private Macros
-  * @{
-  */
-#define IS_LPTIM(x)		((x) == LPTIM0)
-#define IS_LPTIM_CKSEL(x)	(((x) == LPTIM_CKSEL_INTERNAL) || \
-                                 ((x) == LPTIM_CKSEL_EXTERNAL))
-#define IS_LPTIM_CKPOL(x)	(((x) == LPTIM_CKPOL_RISING) || \
-                                 ((x) == LPTIM_CKPOL_FALLING))
-#define IS_LPTIM_MODE(x)	(((x) == LPTIM_MODE_SINGLE) || \
-                                 ((x) == LPTIM_MODE_CONTINUOUS))
-#define IS_LPTIM_CKFLT(x)	(((x) == LPTIM_CKFLT_0) || \
-                                 ((x) == LPTIM_CKFLT_2) || \
-                                 ((x) == LPTIM_CKFLT_4) || \
-                                 ((x) == LPTIM_CKFLT_8))
-#define IS_LPTIM_TRGFLT(x)	(((x) == LPTIM_TRGFLT_0) || \
-                                 ((x) == LPTIM_TRGFLT_2) || \
-                                 ((x) == LPTIM_TRGFLT_4) || \
-                                 ((x) == LPTIM_TRGFLT_8))
-#define IS_LPTIM_PRESC(x)	(((x) == LPTIM_PRESC_1)  || \
-                                 ((x) == LPTIM_PRESC_2)  || \
-                                 ((x) == LPTIM_PRESC_4)  || \
-                                 ((x) == LPTIM_PRESC_8)  || \
-                                 ((x) == LPTIM_PRESC_16) || \
-                                 ((x) == LPTIM_PRESC_32) || \
-                                 ((x) == LPTIM_PRESC_64) || \
-                                 ((x) == LPTIM_PRESC_128))
-#define IS_LPTIM_TRIGSEL(x)	(((x) == LPTIM_TRIGSEL_EXT0) || \
-                                 ((x) == LPTIM_TRIGSEL_EXT1) || \
-                                 ((x) == LPTIM_TRIGSEL_EXT2) || \
-                                 ((x) == LPTIM_TRIGSEL_EXT3) || \
-                                 ((x) == LPTIM_TRIGSEL_EXT4) || \
-                                 ((x) == LPTIM_TRIGSEL_EXT5) || \
-                                 ((x) == LPTIM_TRIGSEL_EXT6) || \
-                                 ((x) == LPTIM_TRIGSEL_EXT7))
-#define IS_LPTIM_TRIGEN(x)	(((x) == LPTIM_TRIGEN_SW)      || \
-                                 ((x) == LPTIM_TRIGEN_RISING)  || \
-                                 ((x) == LPTIM_TRIGEN_FALLING) || \
-                                 ((x) == LPTIM_TRIGEN_BOTH))
-#define IS_LPTIM_IT(x)		(((x) == LPTIM_IT_CMPMAT) || \
-                                 ((x) == LPTIM_IT_ARRMAT) || \
-                                 ((x) == LPTIM_IT_EXTTRIG))
-#define IS_LPTIM_FLAG(x)	(((x) == LPTIM_FLAG_CMPMAT) || \
-                                 ((x) == LPTIM_FLAG_ARRMAT) || \
-                                 ((x) == LPTIM_FLAG_EXTTRIG))
-/**
-  * @}
-  */
-
-/** @addtogroup LPTIM_Public_Functions
-  * @{
-  */
-
-/** @addtogroup LPTIM_Public_Functions_Group1
-  * @{
-  */
-void lptim_reset(lptim_handle_t *hperh);
-void lptim_trigger_config(lptim_handle_t *hperh, lptim_trigger_init_t *config);
-void lptim_clock_source_config(lptim_handle_t *hperh, lptim_clock_source_init_t *config);
-void lptim_trigger_filter_config(lptim_handle_t *hperh, lptim_trgflt_t flt);
-void lptim_clock_filter_config(lptim_handle_t *hperh, lptim_ckflt_t flt);
-/**
-  * @}
-  */
-
-/** @addtogroup LPTIM_Public_Functions_Group2
-  * @{
-  */
-ald_status_t lptim_toggle_init(lptim_handle_t *hperh);
-void lptim_toggle_start(lptim_handle_t *hperh);
-void lptim_toggle_stop(lptim_handle_t *hperh);
-void lptim_toggle_start_by_it(lptim_handle_t *hperh);
-void lptim_toggle_stop_by_it(lptim_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup LPTIM_Public_Functions_Group3
-  * @{
-  */
-ald_status_t lptim_pulse_init(lptim_handle_t *hperh);
-void lptim_pulse_start(lptim_handle_t *hperh);
-void lptim_pulse_stop(lptim_handle_t *hperh);
-void lptim_pulse_start_by_it(lptim_handle_t *hperh);
-void lptim_pulse_stop_by_it(lptim_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup LPTIM_Public_Functions_Group4
-  * @{
-  */
-ald_status_t lptim_pwm_init(lptim_handle_t *hperh);
-void lptim_pwm_start(lptim_handle_t *hperh);
-void lptim_pwm_stop(lptim_handle_t *hperh);
-void lptim_pwm_start_by_it(lptim_handle_t *hperh);
-void lptim_pwm_stop_by_it(lptim_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup LPTIM_Public_Functions_Group5
-  * @{
-  */
-void lptim_irq_handle(lptim_handle_t *hperh);
-void lptim_interrupt_config(lptim_handle_t *hperh, lptim_it_t it, type_func_t state);
-it_status_t lptim_get_it_status(lptim_handle_t *hperh, lptim_it_t it);
-flag_status_t lptim_get_flag_status(lptim_handle_t *hperh, lptim_flag_t flag);
-void lptim_clear_flag_status(lptim_handle_t *hperh, lptim_flag_t flag);
-/**
-  * @}
-  */
-
-/** @addtogroup LPTIM_Public_Functions_Group6
-  * @{
-  */
-lptim_state_t lptim_get_state(lptim_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_LPTIM_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lpuart.h

@@ -1,468 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_lpuart.h
-  * @brief   Header file of Low Power UART module library.
-  *
-  * @version V1.0
-  * @date    30 May 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#ifndef __ALD_LPUART_H__
-#define __ALD_LPUART_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-#include "ald_cmu.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup LPUART
-  * @{
-  */
-
-/**
-  * @defgroup LPUART_Public_Macros LPUART Public Macros
-  * @{
-  */
-
-/**
-  * @defgroup LPUART_Public_Macros1 LPUART FIFO Reset
-  * @{
-  */
-#define LPUART_FIFO_TX_RESET(hperh)	(SET_BIT((hperh)->perh->FIFOCON, LPUART_FIFOCON_TXRESET_MSK))
-#define LPUART_FIFO_RX_RESET(hperh)	(SET_BIT((hperh)->perh->FIFOCON, LPUART_FIFOCON_RXRESET_MSK))
-/**
-  * @}
-  */
-/**
-  * @defgroup LPUART_Public_Macros2 LPUART RS485 RX Enable
-  * @{
-  */
-#define LPUART_RS485_RX_DISABLE(hperh)	(SET_BIT((hperh)->perh->FIFOCON, LPUART_FIFOCON_NMPMRXDIS_MSK))
-#define LPUART_RS485_RX_ENABLE(hperh)	(CLEAR_BIT((hperh)->perh->FIFOCON, LPUART_FIFOCON_NMPMRXDIS_MSK))
-/**
-  * @}
-  */
-/**
-  * @defgroup LPUART_Public_Macros4 LPUART LoopMode Enable
-  * @{
-  */
-#define LPUART_LPBMOD_ENABLE(hperh)	(SET_BIT((hperh)->perh->CON0, LPUART_CON0_LPBMOD_MSK))
-#define LPUART_LPBMOD_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_LPBMOD_MSK))
-/**
-  * @}
-  */
-/**
-  * @defgroup LPUART_Public_Macros5 LPUART IrDA TX Enable
-  * @{
-  */
-#define LPUART_IRTX_ENABLE(hperh)	(SET_BIT((hperh)->perh->CON1, LPUART_CON1_IRTXE_MSK))
-#define LPUART_IRTX_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->CON1, LPUART_CON1_IRTXE_MSK))
-/**
-  * @}
-  */
-/**
-  * @defgroup LPUART_Public_Macros6 LPUART IRWIDTH Enable
-  * @{
-  */
-#define LPUART_IRWIDTH_DISABLE(hperh)	(SET_BIT((hperh)->perh->CON1, LPUART_CON1_IRWIDTH_MSK))
-#define LPUART_IRWIDTH_ENABLE(hperh)	(CLEAR_BIT((hperh)->perh->CON1, LPUART_CON1_IRWIDTH_MSK))
-/**
-  * @}
-  */
-/**
-  * @defgroup LPUART_Public_Macros7 LPUART CTS/RTS Enable
-  * @{
-  */
-#define LPUART_CTS_ENABLE(hperh)	(SET_BIT((hperh)->perh->CON0, LPUART_CON0_ATCTSE_MSK))
-#define LPUART_CTS_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_ATCTSE_MSK))
-#define LPUART_RTS_ENABLE(hperh)	(SET_BIT((hperh)->perh->CON0, LPUART_CON0_ATRTSE_MSK))
-#define LPUART_RTS_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_ATRTSE_MSK))
-/**
-  * @}
-  */
-/**
-  * @defgroup LPUART_Public_Macros8 LPUART CTS/RTS Polarity
-  * @{
-  */
-#define LPUART_CTS_POL_LOW(hperh)	(SET_BIT((hperh)->perh->CON0, LPUART_CON0_CTSPOL_MSK))
-#define LPUART_CTS_POL_HIGH(hperh)	(CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_CTSPOL_MSK))
-#define LPUART_RTS_POL_LOW(hperh)	(SET_BIT((hperh)->perh->CON0, LPUART_CON0_RTSPOL_MSK))
-#define LPUART_RTS_POL_HIGH(hperh)	(CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_RTSPOL_MSK))
-/**
-  * @}
-  */
-/**
-  * @defgroup LPUART_Public_Macros10 LPUART Update Enable
-  * @{
-  */
-#define LPUART_UPDATE_ENABLE(hperh)	(CLEAR_BIT((hperh)->perh->UPDATE, LPUART_UPDATE_UDIS_MSK))
-#define LPUART_UPDATE_DISABLE(hperh)	(SET_BIT((hperh)->perh->UPDATE, LPUART_UPDATE_UDIS_MSK))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_Public_Types LPUART Public Types
-  * @{
-  */
-/**
-  * @brief LPUART Word Length
-  */
-typedef enum {
-	LPUART_WORD_LENGTH_5B = 0x0,	/**< 5-bits */
-	LPUART_WORD_LENGTH_6B = 0x1,	/**< 6-bits */
-	LPUART_WORD_LENGTH_7B = 0x2,	/**< 7-bits */
-	LPUART_WORD_LENGTH_8B = 0x3,	/**< 8-bits */
-	LPUART_WORD_LENGTH_9B = 0x4,	/**< 9-bits */
-} lpuart_word_length_t;
-
-/**
-  * @brief LPUART Stop Bits
-  */
-typedef enum {
-	LPUART_STOP_BITS_1 = 0x0,	/**< 1-bits */
-	LPUART_STOP_BITS_2 = 0x1,	/**< 2-bits */
-} lpuart_stop_bits_t;
-
-/**
-  * @brief LPUART Parity
-  */
-typedef enum {
-	LPUART_PARITY_NONE = 0x0,	/**< Not parity */
-	LPUART_PARITY_ODD  = 0x1,	/**< Odd parity */
-	LPUART_PARITY_EVEN = 0x3,	/**< Even parity */
-} lpuart_parity_t;
-
-/**
-  * @brief LPUART Mode
-  */
-typedef enum {
-	LPUART_MODE_UART  = 0x0,	/**< UART */
-	LPUART_MODE_IrDA  = 0x2,	/**< IrDA */
-	LPUART_MODE_RS485 = 0x3,	/**< RS485 */
-} lpuart_mode_t;
-
-/**
-  * @brief LPUART Hardware Flow Control
-  */
-typedef enum {
-	LPUART_HW_FLOW_CTL_NONE    = 0x0,	/**< None */
-	LPUART_HW_FLOW_CTL_RTS     = 0x1,	/**< RTS */
-	LPUART_HW_FLOW_CTL_CTS     = 0x2,	/**< CTS */
-	LPUART_HW_FLOW_CTL_RTS_CTS = 0x3,	/**< RTS & CTS */
-} lpuart_hw_flow_ctl_t;
-
-/**
-  * @brief ALD LPUART State
-  */
-typedef enum {
-	LPUART_STATE_RESET      = 0x00,	/**< Peripheral is not initialized */
-	LPUART_STATE_READY      = 0x01,	/**< Peripheral Initialized and ready for use */
-	LPUART_STATE_BUSY       = 0x02,	/**< an internal process is ongoing */
-	LPUART_STATE_BUSY_TX    = 0x11,	/**< Data Transmission process is ongoing */
-	LPUART_STATE_BUSY_RX    = 0x21,	/**< Data Reception process is ongoing */
-	LPUART_STATE_BUSY_TX_RX = 0x31,	/**< Data Transmission Reception process is ongoing */
-	LPUART_STATE_TIMEOUT    = 0x03,	/**< Timeout state */
-	LPUART_STATE_ERROR      = 0x04,	/**< Error */
-} lpuart_state_t;
-
-/**
-  * @brief LPUART Error Codes
-  */
-typedef enum {
-	LPUART_ERROR_NONE = ((uint32_t)0x00),	/**< No error */
-	LPUART_ERROR_PE   = ((uint32_t)0x01),	/**< Parity error */
-	LPUART_ERROR_NE   = ((uint32_t)0x02),	/**< Noise error */
-	LPUART_ERROR_FE   = ((uint32_t)0x04),	/**< frame error */
-	LPUART_ERROR_ORE  = ((uint32_t)0x08),	/**< Overrun error */
-	LPUART_ERROR_DMA  = ((uint32_t)0x10),	/**< DMA transfer error */
-} lpuart_error_t;
-
-/**
-  * @brief LPUART Init structure definition
-  */
-typedef struct {
-	uint32_t baud;				/**< Specifies the lpuart communication baud rate */
-	lpuart_word_length_t word_length;	/**< Specifies the number of data bits transmitted or received in a frame */
-	lpuart_stop_bits_t stop_bits;		/**< Specifies the number of stop bits transmitted */
-	lpuart_parity_t parity;			/**< Specifies the parity mode */
-	lpuart_mode_t mode;			/**< Specifies uart mode */
-	lpuart_hw_flow_ctl_t fctl;		/**< Specifies wether the hardware flow control mode is enabled or disabled */
-	cmu_lp_perh_clock_sel_t clock;		/**< Specifies clock, only support LOSC and LRC */
-} lpuart_init_t;
-
-/**
-  * @brief  LPUART handle structure definition
-  */
-typedef struct lpuart_handle_s {
-	LPUART_TypeDef *perh;		/**< LPUART registers base address */
-	lpuart_init_t init;		/**< LPUART communication parameters */
-	uint8_t *tx_buf;		/**< Pointer to LPUART Tx transfer Buffer */
-	uint16_t tx_size;		/**< LPUART Tx Transfer size */
-	uint16_t tx_count;		/**< LPUART Tx Transfer Counter */
-	uint8_t *rx_buf;		/**< Pointer to LPUART Rx transfer Buffer */
-	uint16_t rx_size;		/**< LPUART Rx Transfer size */
-	uint16_t rx_count;		/**< LPUART Rx Transfer Counter */
-#ifdef ALD_DMA
-	dma_handle_t hdmatx;		/**< LPUART Tx DMA Handle parameters */
-	dma_handle_t hdmarx;		/**< LPUART Rx DMA Handle parameters */
-#endif
-	lock_state_t lock;            	/**< Locking object */
-	lpuart_state_t state;		/**< LPUART communication state */
-	lpuart_error_t err_code;	/**< LPUART Error code */
-
-	void (*tx_cplt_cbk)(struct lpuart_handle_s *arg);	/**< Tx completed callback */
-	void (*rx_cplt_cbk)(struct lpuart_handle_s *arg);	/**< Rx completed callback */
-	void (*error_cbk)(struct lpuart_handle_s *arg);		/**< error callback */
-} lpuart_handle_t;
-
-/**
-  * @brief LPUART RS485 Configure Structure definition
-  */
-typedef struct {
-	type_func_t RS485_NMM;		/**< Normal Point Mode */
-	type_func_t RS485_AAD;		/**< Auto-Address Detect */
-	type_func_t RS485_AUD;		/**< Auto-Direction Mode */
-	type_func_t RS485_ADD_DET;	/**< Eable/Disable Address Detect */
-	uint8_t RS485_ADDCMP;		/**< Address for compare */
-} lpuart_rs485_config_t;
-
-/**
-  * @brief LPUART DMA Requests
-  */
-typedef enum {
-	LPUART_DMA_REQ_TX = 0x0,	/**< TX dma */
-	LPUART_DMA_REQ_RX = 0x1,	/**< RX dma */
-} lpuart_dma_req_t;
-
-/**
-  * @brief LPUART RXFIFO size
-  */
-typedef enum {
-	LPUART_RXFIFO_1BYTE  = 0x0,	/**< 1-Byte */
-	LPUART_RXFIFO_4BYTE  = 0x1,	/**< 4-Bytes */
-	LPUART_RXFIFO_8BYTE  = 0x2,	/**< 8-Bytes */
-	LPUART_RXFIFO_14BYTE = 0x3,	/**< 14-Bytes */
-} lpuart_rxfifo_t;
-
-/**
-  * @brief LPUART Interrupts Types
-  */
-typedef enum {
-	LPUART_IT_RBR    = (1U << 0),	/**< RBR */
-	LPUART_IT_TBEMP  = (1U << 1),	/**< TBEMP */
-	LPUART_IT_CTSDET = (1U << 2),	/**< CTSDET */
-	LPUART_IT_RXTO   = (1U << 3),	/**< RXTO */
-	LPUART_IT_RXOV   = (1U << 4),	/**< RXOV */
-	LPUART_IT_TXOV   = (1U << 5),	/**< TXOV */
-	LPUART_IT_CTSWK  = (1U << 7),	/**< CTSWK */
-	LPUART_IT_DATWK  = (1U << 8),	/**< DATWK */
-	LPUART_IT_PERR   = (1U << 9),	/**< PERR */
-	LPUART_IT_FERR   = (1U << 10),	/**< FERR */
-	LPUART_IT_BRKERR = (1U << 11),	/**< BRKERR */
-	LPUART_IT_ADET   = (1U << 12),	/**< ADET */
-	LPUART_IT_TC     = (1U << 15),	/**< TC */
-} lpuart_it_t;
-
-/**
-  * @brief LPUART Flags Types
-  */
-typedef enum {
-	LPUART_IF_RBR    = (1U << 0),	/**< RBR */
-	LPUART_IF_TBEMP  = (1U << 1),	/**< TBEMP */
-	LPUART_IF_CTSDET = (1U << 2),	/**< CTSDET */
-	LPUART_IF_RXTO   = (1U << 3),	/**< RXTO */
-	LPUART_IF_RXOV   = (1U << 4),	/**< RXOV */
-	LPUART_IF_TXOV   = (1U << 5),	/**< TXOV */
-	LPUART_IF_CTSWK  = (1U << 7),	/**< CTSWK */
-	LPUART_IF_DATWK  = (1U << 8),	/**< DATWK */
-	LPUART_IF_PERR   = (1U << 9),	/**< PERR */
-	LPUART_IF_FERR   = (1U << 10),	/**< FERR */
-	LPUART_IF_BRKERR = (1U << 11),	/**< BRKERR */
-	LPUART_IF_ADET   = (1U << 12),	/**< ADET */
-	LPUART_IF_TC     = (1U << 15),	/**< TC */
-} lpuart_flag_t;
-
-/**
-  * @brief LPUART Status Types
-  */
-typedef enum {
-	LPUART_STAT_RXEMP   = (1U << 6),	/**< RX FIFO empty */
-	LPUART_STAT_RXFULL  = (1U << 7),	/**< RX FIFO full */
-	LPUART_STAT_TXEMP   = (1U << 14),	/**< TX FIFO empty */
-	LPUART_STAT_TXFULL  = (1U << 15),	/**< TX FIFO full */
-	LPUART_STAT_TXIDLE  = (1U << 16),	/**< TX idle */
-	LPUART_STAT_CTSSTAT = (1U << 17),	/**< CTS status */
-	LPUART_STAT_RTSSTAT = (1U << 18),	/**< RTS status */
-} lpuart_status_t;
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_Private_Macros   LPUART Private Macros
-  * @{
-  */
-#define IS_LPUART(x)  ((x) == LPUART0)
-#define IS_LPUART_DATA(x) ((x) <= 0x1FF)
-#define IS_LPUART_BAUDRATE(x) (((x) > 0) && ((x) <= 115200))
-#define IS_LPUART_WORD_LENGTH(x)  (((x) == LPUART_WORD_LENGTH_5B) || \
-                                   ((x) == LPUART_WORD_LENGTH_6B) || \
-                                   ((x) == LPUART_WORD_LENGTH_7B) || \
-                                   ((x) == LPUART_WORD_LENGTH_8B) || \
-                                   ((x) == LPUART_WORD_LENGTH_9B))
-#define IS_LPUART_STOPBITS(x)  (((x) == LPUART_STOP_BITS_1) || \
-                                ((x) == LPUART_STOP_BITS_2))
-#define IS_LPUART_PARITY(x)  (((x) == LPUART_PARITY_NONE)  || \
-                              ((x) == LPUART_PARITY_ODD) || \
-                              ((x) == LPUART_PARITY_EVEN))
-#define IS_LPUART_MODE(x)  (((x) == LPUART_MODE_UART) || \
-                            ((x) == LPUART_MODE_IrDA) || \
-                            ((x) == LPUART_MODE_RS485))
-#define IS_LPUART_HARDWARE_FLOW_CONTROL(x)\
-                              (((x) == LPUART_HW_FLOW_CTL_NONE) || \
-                               ((x) == LPUART_HW_FLOW_CTL_RTS)  || \
-                               ((x) == LPUART_HW_FLOW_CTL_CTS)  || \
-                               ((x) == LPUART_HW_FLOW_CTL_RTS_CTS))
-#define IS_LPUART_DMAREQ(x)  (((x) == LPUART_DMA_REQ_TX) || ((x) == LPUART_DMA_REQ_RX))
-#define IS_LPUART_RXFIFO(x)  (((x) == LPUART_RXFIFO_1BYTE) || \
-                              ((x) == LPUART_RXFIFO_4BYTE) || \
-                              ((x) == LPUART_RXFIFO_8BYTE) || \
-                              ((x) == LPUART_RXFIFO_14BYTE))
-#define IS_LPUART_IT(x)	(((x) == LPUART_IT_RBR)    || \
-                         ((x) == LPUART_IT_TBEMP)  || \
-                         ((x) == LPUART_IT_CTSDET) || \
-                         ((x) == LPUART_IT_RXTO)   || \
-                         ((x) == LPUART_IT_RXOV)   || \
-                         ((x) == LPUART_IT_TXOV)   || \
-                         ((x) == LPUART_IT_CTSWK)  || \
-                         ((x) == LPUART_IT_DATWK)  || \
-                         ((x) == LPUART_IT_PERR)   || \
-                         ((x) == LPUART_IT_FERR)   || \
-                         ((x) == LPUART_IT_BRKERR) || \
-                         ((x) == LPUART_IT_ADET)   || \
-                         ((x) == LPUART_IT_TC))
-#define IS_LPUART_IF(x)	(((x) == LPUART_IF_RBR)    || \
-                         ((x) == LPUART_IF_TBEMP)  || \
-                         ((x) == LPUART_IF_CTSDET) || \
-                         ((x) == LPUART_IF_RXTO)   || \
-                         ((x) == LPUART_IF_RXOV)   || \
-                         ((x) == LPUART_IF_TXOV)   || \
-                         ((x) == LPUART_IF_CTSWK)  || \
-                         ((x) == LPUART_IF_DATWK)  || \
-                         ((x) == LPUART_IF_PERR)   || \
-                         ((x) == LPUART_IF_FERR)   || \
-                         ((x) == LPUART_IF_BRKERR) || \
-                         ((x) == LPUART_IF_ADET)   || \
-                         ((x) == LPUART_IF_TC))
-#define IS_LPUART_STAT(x)	(((x) == LPUART_STAT_RXEMP)   || \
-                                 ((x) == LPUART_STAT_RXFULL)  || \
-                                 ((x) == LPUART_STAT_TXEMP)   || \
-                                 ((x) == LPUART_STAT_TXFULL)  || \
-                                 ((x) == LPUART_STAT_TXIDLE)  || \
-                                 ((x) == LPUART_STAT_CTSSTAT) || \
-                                 ((x) == LPUART_STAT_RTSSTAT))
-
-#define LPUART_STATE_TX_MASK	(1 << 4)
-#define LPUART_STATE_RX_MASK	(1 << 5)
-/**
-  * @}
-  */
-
-/** @addtogroup LPUART_Public_Functions
-  * @{
-  */
-
-/** @addtogroup LPUART_Public_Functions_Group1
-  * @{
-  */
-/* Initialization functions */
-void lpuart_init(lpuart_handle_t *hperh);
-void lpuart_reset(lpuart_handle_t *hperh);
-void lpuart_rs485_config(lpuart_handle_t *hperh, lpuart_rs485_config_t *config);
-/**
-  * @}
-  */
-
-/** @addtogroup LPUART_Public_Functions_Group2
-  * @{
-  */
-/* IO operation functions */
-ald_status_t lpuart_send(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t lpuart_recv(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t lpuart_send_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size);
-ald_status_t lpuart_recv_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size);
-#ifdef ALD_DMA
-ald_status_t lpuart_send_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t lpuart_recv_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t lpuart_dma_pause(lpuart_handle_t *hperh);
-ald_status_t lpuart_dma_resume(lpuart_handle_t *hperh);
-ald_status_t lpuart_dma_stop(lpuart_handle_t *hperh);
-#endif
-void lpuart_irq_handle(lpuart_handle_t *hperh);
-
-/**
-  * @}
-  */
-
-/** @addtogroup LPUART_Public_Functions_Group3
-  * @{
-  */
-/* Peripheral Control functions */
-void lpuart_interrupt_config(lpuart_handle_t *hperh, lpuart_it_t it, type_func_t status);
-void lpuart_tx_interval_config(lpuart_handle_t *hperh, uint8_t val);
-void lpuart_dma_req_config(lpuart_handle_t *hperh, lpuart_dma_req_t req, type_func_t status);
-void lpuart_rx_fifo_it_config(lpuart_handle_t *hperh, lpuart_rxfifo_t config);
-void lpuart_rx_fifo_rts_config(lpuart_handle_t *hperh, lpuart_rxfifo_t config);
-ald_status_t lpuart_rs485_send_addr(lpuart_handle_t *hperh, uint16_t addr, uint32_t timeout);
-flag_status_t lpuart_get_status(lpuart_handle_t *hperh, lpuart_status_t flag);
-flag_status_t lpuart_get_flag_status(lpuart_handle_t *hperh, lpuart_flag_t flag);
-void lpuart_clear_flag_status(lpuart_handle_t *hperh, lpuart_flag_t flag);
-it_status_t lpuart_get_it_status(lpuart_handle_t *hperh, lpuart_it_t it);
-/**
-  * @}
-  */
-
-/** @addtogroup LPUART_Public_Functions_Group4
-  * @{
-  */
-/* Peripheral State and Errors functions */
-lpuart_state_t lpuart_get_state(lpuart_handle_t *hperh);
-uint32_t lpuart_get_error(lpuart_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_LPUART_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pis.h

@@ -1,614 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_pis.h
-  * @brief   Header file of PIS driver.
-  *
-  * @version V1.0
-  * @date    27 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#ifndef __ALD_PIS_H__
-#define __ALD_PIS_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup PIS
-  * @{
-  */
-
-/** @defgroup PIS_Public_Types PIS Public Types
-  * @{
-  */
-
-/**
-  * @brief Producer entry
-  */
-typedef enum {
-	PIS_NON               = 0x0,	/**< No async */
-	PIS_GPIO_PIN0         = 0x10,	/**< Pin0, level,support async */
-	PIS_GPIO_PIN1         = 0x11,	/**< Pin1, level,support async */
-	PIS_GPIO_PIN2         = 0x12,	/**< Pin2, level,support async */
-	PIS_GPIO_PIN3         = 0x13,	/**< Pin3, level,support async */
-	PIS_GPIO_PIN4         = 0x14,	/**< Pin4, level,support async */
-	PIS_GPIO_PIN5         = 0x15,	/**< Pin5, level,support async */
-	PIS_GPIO_PIN6         = 0x16,	/**< Pin6, level,support async */
-	PIS_GPIO_PIN7         = 0x17,	/**< Pin7, level,support async */
-	PIS_GPIO_PIN8         = 0x18,	/**< Pin8, level,support async */
-	PIS_GPIO_PIN9         = 0x19,	/**< Pin9, level,support async */
-	PIS_GPIO_PIN10        = 0x1a,	/**< Pin10, level,support async */
-	PIS_GPIO_PIN11        = 0x1b,	/**< Pin11, level,support async */
-	PIS_GPIO_PIN12        = 0x1c,	/**< Pin12, level,support async */
-	PIS_GPIO_PIN13        = 0x1d,	/**< Pin13, level,support async */
-	PIS_GPIO_PIN14        = 0x1e,	/**< Pin14, level,support async */
-	PIS_GPIO_PIN15        = 0x1f,	/**< Pin15, level,support async */
-	PIS_ACMP_OUT0         = 0x30,	/**< Acmp0 output, level,support async */
-	PIS_ACMP_OUT1         = 0x31,	/**< Acmp1 output, level,support async */
-	PIS_DAC0_CH0          = 0x40,	/**< Dac0 channel 0, pclk2 pulse,support async */
-	PIS_DAC0_CH1          = 0x41,	/**< Dac0 channel 1, pclk2 pulse,support async */
-	PIS_ADC0_INJECT       = 0x60,	/**< Adc0 inject, pclk2 pulse,support async */
-	PIS_ADC0_REGULAT      = 0x61,	/**< Adc0 regulat, pclk2 pulse,support async */
-	PIS_ADC0_WINDOW       = 0x62,	/**< Adc0 window, no have */
-	PIS_LVD               = 0x70,	/**< Lvd, level,support async */
-	PIS_UART0_ASY_SEND    = 0x80,	/**< Uart0 asy send, pulse,support async */
-	PIS_UART0_ASY_RECV    = 0x81,	/**< Uart0 asy recv, pulse,support async */
-	PIS_UART0_IRDAOUT     = 0x82,	/**< Uart0 irdaout, level,support async */
-	PIS_UART0_RTSOUT      = 0x83,	/**< Uart0 rtsout, level,support async */
-	PIS_UART0_TXOUT       = 0x84,	/**< Uart0 txout, level,support async */
-	PIS_UART0_SYN_SEND    = 0x85,	/**< Uart0 syn send, pulse,support async */
-	PIS_UART0_SYN_RECV    = 0x86,	/**< Uart0 syn recv, pulse,support async */
-	PIS_UART1_ASY_SEND    = 0x90,	/**< Uart1 asy send, pulse,support async */
-	PIS_UART1_ASY_RECV    = 0x91,	/**< Uart1 asy recv, pulse,support async */
-	PIS_UART1_IRDA        = 0x92,	/**< Uart1 irdaout, level,support async */
-	PIS_UART1_RTS         = 0x93,	/**< Uart1 rtsout, level,support async */
-	PIS_UART1_TXOUT       = 0x94,	/**< Uart1 txout, level,support async */
-	PIS_UART1_SYN_SEND    = 0x95,	/**< Uart1 syn send, pulse,support async */
-	PIS_UART1_SYN_RECV    = 0x96,	/**< Uart1 syn recv, pulse,support async */
-	PIS_UART2_ASY_SEND    = 0xa0,	/**< Uart2 asy send, pulse,support async */
-	PIS_UART2_ASY_RECV    = 0xa1,	/**< Uart2 asy recv, pulse,support async */
-	PIS_UART2_IRDA        = 0xa2,	/**< Uart2 irdaout, level,support async */
-	PIS_UART2_RTS         = 0xa3,	/**< Uart2 rtsout, level,support async */
-	PIS_UART2_TXOUT       = 0xa4,	/**< Uart2 txout, level,support async */
-	PIS_UART2_SYN_SEND    = 0xa5,	/**< Uart2 syn send, pulse,support async */
-	PIS_UART2_SYN_RECV    = 0xa6,	/**< Uart2 syn recv, pulse,support async */
-	PIS_UART3_ASY_SEND    = 0xb1,	/**< Uart3 asy send, pulse,support async */
-	PIS_UART3_ASY_RECV    = 0xb2,	/**< Uart3 asy recv, pulse,support async */
-	PIS_UART3_IRDA        = 0xb3,	/**< Uart3 irdaout, level,support async */
-	PIS_UART3_RTS         = 0xb4,	/**< Uart3 rtsout, level,support async */
-	PIS_UART3_TXOUT       = 0xb5,	/**< Uart3 txout, level,support async */
-	PIS_UART3_SYN_SEND    = 0xb6,	/**< Uart3 syn send, pulse,support async */
-	PIS_UART3_SYN_RECV    = 0xb7,	/**< Uart3 syn recv, pulse,support async */
-	PIS_EUART0_RECV       = 0xc0,	/**< Euart0 recv, plck1 pulse */
-	PIS_EUART0_SEND       = 0xc1,	/**< Euart0 send, plck1 pulse */
-	PIS_EUART0_TXOUT      = 0xc2,	/**< Euart0 txout, plck1 level */
-	PIS_EUART1_RECV       = 0xd0,	/**< Euart1 recv, plck1 pulse */
-	PIS_EUART1_SEND       = 0xd1,	/**< Euart1 send, plck1 pulse */
-	PIS_EUART1_TXOUT      = 0xd2,	/**< Euart1 txout, plck1 level */
-	PIS_SPI0_RECV         = 0xe0,	/**< Spi0 recv, plck1 pulse */
-	PIS_SPI0_SEND         = 0xe1,	/**< Spi0 send, plck1 pulse */
-	PIS_SPI0_NE           = 0xe2,	/**< Spi0 ne, plck1 level */
-	PIS_SPI1_RECV         = 0xf0,	/**< Spi1 recv, plck1 pulse */
-	PIS_SPI1_SEND         = 0xf1,	/**< Spi1 send, plck1 pulse */
-	PIS_SPI1_NE           = 0xf2,	/**< Spi1 ne, plck1 level */
-	PIS_I2C0_RECV         = 0x100,	/**< I2c0 recv, plck1 level */
-	PIS_I2C0_SEND         = 0x101,	/**< I2c0 send, plck1 level */
-	PIS_I2C1_RECV         = 0x110,	/**< I2c1 recv, plck1 level */
-	PIS_I2C1_SEND         = 0x111,	/**< I2c1 send, plck1 level */
-	PIS_TIMER0_UPDATA     = 0x120,	/**< Timer0 updata, plck1 pulse */
-	PIS_TIMER0_TRIG       = 0x121,	/**< Timer0 trig, plck1 pulse */
-	PIS_TIMER0_INPUT      = 0x122,	/**< Timer0 input, plck1 pulse */
-	PIS_TIMER0_OUTPUT     = 0x123,	/**< Timer0 output, plck1 pulse */
-	PIS_TIMER1_UPDATA     = 0x130,	/**< Timer1 updata, plck1 pulse */
-	PIS_TIMER1_TRIG       = 0x131,	/**< Timer1 trig, plck1 pulse */
-	PIS_TIMER1_INPUT      = 0x132,	/**< Timer1 input, plck1 pulse */
-	PIS_TIMER1_OUTPUT     = 0x133,	/**< Timer1 output, plck1 pulse */
-	PIS_TIMER2_UPDATA     = 0x140,	/**< Timer2 updata, plck1 pulse */
-	PIS_TIMER2_TRIG       = 0x141,	/**< Timer2 trig, plck1 pulse */
-	PIS_TIMER2_INPUT      = 0x142,	/**< Timer2 input, plck1 pulse */
-	PIS_TIMER2_OUTPUT     = 0x143,	/**< Timer2 output, plck1 pulse */
-	PIS_TIMER3_UPDATA     = 0x150,	/**< Timer0 updata, plck1 pulse */
-	PIS_TIMER3_TRIG       = 0x151,	/**< Timer0 trig, plck1 pulse */
-	PIS_TIMER3_INPUT      = 0x152,	/**< Timer0 input, plck1 pulse */
-	PIS_TIMER3_OUTPUT     = 0x153,	/**< Timer0 output, plck1 pulse */
-	PIS_RTC_CLOCK         = 0x160,	/**< Rtc clock, pulse,support async */
-	PIS_RTC_ALARM         = 0x161,	/**< Rtc alarm, pulse,support async */
-	PIS_LPTIM0_SYN_UPDATA = 0x170,	/**< Lptimer0 syn updata, pulse,support async */
-	PIS_LPTIM0_ASY_UPDATA = 0x171,	/**< Lptimer0 asy updata, pulse,support async */
-	PIS_LPUART0_ASY_RECV  = 0x180,	/**< Lpuart0 asy recv, pulse,support async */
-	PIS_LPUART0_ASY_SEND  = 0x181,	/**< Lpuart0 asy send, pulse,support async */
-	PIS_LPUART0_SYN_RECV  = 0x182,	/**< Lpuart0 syn recv, pulse,support async */
-	PIS_LPUART0_SYN_SEND  = 0x183,	/**< Lpuart0 syn recv, pulse,support async */
-	PIS_DMA               = 0x190,	/**< Dma, pulse,support async */
-	PIS_ADC1_INJECT       = 0x1a0,	/**< Adc1 inject, pclk2 pulse,support async */
-	PIS_ADC1_REGULAT      = 0x1a1,	/**< Adc1 regulat, pclk2 pulse,support async */
-	PIS_ADC1_WINDOW       = 0x1a2,	/**< Adc1 window, no have */
-} pis_src_t;
-
-/**
-  * @brief Consumer entry
-  */
-typedef enum {
-	PIS_CH0_TIMER0_BRKIN  = 0x4000,	/**< Timer0 brkin */
-	PIS_CH0_SPI1_CLK      = 0xF010,	/**< Spi1 clk */
-	PIS_CH0_LPTIM0_EXT0   = 0x0030,	/**< Lptimer0 ext0 */
-	PIS_CH0_ADC1_NORMAL   = 0x0030,	/**< Adc1 normal */
-	PIS_CH1_TIMER0_CH1IN  = 0x0001,	/**< Timer0 ch1in */
-	PIS_CH1_TIMER2_CH1IN  = 0x0101,	/**< Timer2 ch1in */
-	PIS_CH1_TIMER3_CH1IN  = 0x8101,	/**< Timer3 ch1in */
-	PIS_CH1_LPTIM0_EXT1   = 0x0031,	/**< Lptime0 ext1 */
-	PIS_CH1_UART0_RX_IRDA = 0x0011,	/**< Uart0 rx irda */
-	PIS_CH1_ADC1_INSERT   = 0x0031,	/**< Adc1 insert */
-	PIS_CH2_TIMER0_CH2IN  = 0x1002,	/**< Timer0 ch2in */
-	PIS_CH2_TIMER2_CH2IN  = 0x1102,	/**< Timer2 ch2in */
-	PIS_CH2_TIMER3_CH2IN  = 0x9102,	/**< Timer3 ch2in */
-	PIS_CH2_LPTIM0_EXT2   = 0x0032,	/**< Lptime0 ext2 */
-	PIS_CH2_UART1_RX_IRDA = 0x1012,	/**< Uart1 rx irda */
-	PIS_CH3_TIMER0_CH3IN  = 0x2003,	/**< Timer0 ch3in */
-	PIS_CH3_LPTIM0_EXT3   = 0x0033,	/**< Lptime0 ext3 */
-	PIS_CH3_UART2_RX_IRDA = 0x2013,	/**< Uart2 rx irda */
-	PIS_CH4_TIMER0_CH4IN  = 0x0004,	/**< Timer0 ch4in */
-	PIS_CH4_TIMER0_ITR0   = 0x0034,	/**< Timer0 itr0 */
-	PIS_CH4_TIMER2_ITR0   = 0x0034,	/**< Timer2 itr0 */
-	PIS_CH4_TIMER3_ITR0   = 0x0034,	/**< Timer3 itr0 */
-	PIS_CH4_LPTIM0_EXT4   = 0x4034,	/**< Lptime0 ext4 */
-	PIS_CH4_UART3_RX_IRDA = 0x3014,	/**< Uart3 rx irda */
-	PIS_CH5_SPI0_RX       = 0xC015,	/**< Spi0 rx */
-	PIS_CH5_LPTIM0_EXT5   = 0x0035,	/**< Lptime0 ext5 */
-	PIS_CH5_EUART0_RX     = 0x6015,	/**< Euart0 rx */
-	PIS_CH5_TIMER0_ITR1   = 0x0035,	/**< Timer0 itr1 */
-	PIS_CH5_TIMER2_ITR1   = 0x0035,	/**< Timer2 itr1 */
-	PIS_CH5_TIMER3_ITR1   = 0x0035,	/**< Timer3 itr1 */
-	PIS_CH6_SPI0_CLK      = 0xD016,	/**< Spi0 clk */
-	PIS_CH6_ADC0_NORMAL   = 0x0036,	/**< Adc0 normal */
-	PIS_CH6_LPTIM0_EXT6   = 0x0036,	/**< Lptime0 ext6 */
-	PIS_CH6_EUART1_RX     = 0x7016,	/**< Euart1 rx */
-	PIS_CH6_TIMER0_ITR2   = 0x0036,	/**< Timer0 itr2 */
-	PIS_CH6_TIMER2_ITR2   = 0x0036,	/**< Timer2 itr2 */
-	PIS_CH6_TIMER3_ITR2   = 0x0036,	/**< Timer3 itr2 */
-	PIS_CH6_DAC_CH1       = 0x0036,	/**< Dac channel 1 */
-	PIS_CH7_SPI1_RX       = 0xE017,	/**< Spi1 rx */
-	PIS_CH7_ADC0_INSERT   = 0x0037,	/**< Adc0 insert */
-	PIS_CH7_LPTIM0_EXT7   = 0x0037,	/**< Lptime0 ext7 */
-	PIS_CH7_DMA           = 0x0037,	/**< Dma */
-	PIS_CH7_TIMER0_ITR3   = 0x0037,	/**< Timer0 itr3 */
-	PIS_CH7_TIMER2_ITR3   = 0x0037,	/**< Timer2 itr3 */
-	PIS_CH7_TIMER3_ITR3   = 0x0037,	/**< Timer3 itr3 */
-	PIS_CH7_LPUART_RX     = 0x8017,	/**< Lpuart rx */
-	PIS_CH7_DAC_CH0       = 0x0037,	/**< Dac channel 0 */
-} pis_trig_t;
-
-/**
-  * @brief Clock select
-  */
-typedef enum {
-	PIS_CLK_PCLK1 = 0,	/**< Pclock1 */
-	PIS_CLK_PCLK2 = 1,	/**< Pclock2 */
-	PIS_CLK_SYS   = 2,	/**< Sys clock */
-	PIS_CLK_LP    = 3,	/**< Low power clock */
-} pis_clock_t;
-
-/**
-  * @brief Level select
-  */
-typedef enum {
-	PIS_EDGE_NONE    = 0,	/**< None edge */
-	PIS_EDGE_UP      = 1,	/**< Up edge */
-	PIS_EDGE_DOWN    = 2,	/**< Down edge */
-	PIS_EDGE_UP_DOWN = 3,	/**< Up and down edge */
-} pis_edge_t;
-
-/**
-  * @brief Output style
-  */
-typedef enum {
-	PIS_OUT_LEVEL = 0,	/**< Level */
-	PIS_OUT_PULSE = 1,	/**< Pulse */
-} pis_output_t;
-/**
-  * @brief Sync select
-  */
-typedef enum {
-	PIS_SYN_DIRECT      = 0,	/**< Direct */
-	PIS_SYN_ASY_PCLK1   = 1,	/**< Asy pclk1 */
-	PIS_SYN_ASY_PCLK2   = 2,	/**< Asy pclk2 */
-	PIS_SYN_ASY_PCLK    = 3,	/**< Asy pclk */
-	PIS_SYN_PCLK2_PCLK1 = 4,	/**< Pclk2 to pclk1 */
-	PIS_SYN_PCLK1_PCLK2 = 5,	/**< Pclk1 to pclk2 */
-	PIS_SYN_PCLK12_SYS  = 6,	/**< Pclk1 or pclk2 to sysclk */
-} pis_syncsel_t;
-
-/**
-  * @brief Pis channel
-  */
-typedef enum {
-	PIS_CH_0 = 0,	/**< Channel 0 */
-	PIS_CH_1 = 1,	/**< Channel 1 */
-	PIS_CH_2 = 2,	/**< Channel 2 */
-	PIS_CH_3 = 3,	/**< Channel 3 */
-	PIS_CH_4 = 4,	/**< Channel 4 */
-	PIS_CH_5 = 5,	/**< Channel 5 */
-	PIS_CH_6 = 6,	/**< Channel 6 */
-	PIS_CH_7 = 7,	/**< Channel 7 */
-} pis_ch_t;
-
-/**
-  * @brief Pis output channel
-  */
-typedef enum {
-	PIS_OUT_CH_0 = 0,	/**< Channel 0 */
-	PIS_OUT_CH_1 = 1,	/**< Channel 1 */
-	PIS_OUT_CH_2 = 2,	/**< Channel 2 */
-	PIS_OUT_CH_3 = 3,	/**< Channel 3 */
-} pis_out_ch_t;
-
-/**
-  * @brief Indirect value,no care of it.
-  */
-typedef enum {
-	PIS_CON_0    = 0,	/**< Con 0 */
-	PIS_CON_1    = 1,	/**< Con 1 */
-	PIS_CON_NONE = 2,	/**< None */
-} pis_con_t;
-
-/**
-  * @brief Indirect value,no care of it.
-  */
-typedef union {
-	struct {
-		uint8_t ch    :4;	/**< Channel */
-		uint8_t con   :4;	/**< Contorl */
-		uint8_t shift :8;	/**< Shift */
-	};
-	uint16_t HalfWord;
-} pis_divide_t;
-
-/**
-  * @brief PIS state structures definition
-  */
-typedef enum {
-	PIS_STATE_RESET   = 0x00,	/**< Peripheral is not initialized */
-	PIS_STATE_READY   = 0x01,	/**< Peripheral Initialized and ready for use */
-	PIS_STATE_BUSY    = 0x02,	/**< An internal process is ongoing */
-	PIS_STATE_TIMEOUT = 0x03,	/**< Timeout state */
-	PIS_STATE_ERROR   = 0x04,	/**< Error */
-} pis_state_t;
-
-/**
-  * @brief PIS modulate target
-  */
-typedef enum {
-	PIS_UART0_TX   = 0,	/**< Modulate uart0 tx */
-	PIS_UART1_TX   = 1,	/**< Modulate uart1 tx */
-	PIS_UART2_TX   = 2,	/**< Modulate uart2 tx */
-	PIS_UART3_TX   = 3,	/**< Modulate uart3 tx */
-	PIS_LPUART0_TX = 4,	/**< Modulate lpuart0 tx */
-} pis_modu_targ_t;
-
-/**
-  * @brief PIS modulate level
-  */
-typedef enum {
-	PIS_LOW_LEVEL  = 0,	/**< Modulate low level */
-	PIS_HIGH_LEVEL = 1,	/**< Modulate high level */
-} pis_modu_level_t;
-
-/**
-  * @brief PIS modulate source
-  */
-typedef enum {
-	PIS_SRC_NONE   = 0,	/**< Stop modulate */
-	PIS_SRC_TIMER0 = 1,	/**< Modulate source is TIMER0 */
-	PIS_SRC_TIMER1 = 2,	/**< Modulate source is TIMER1 */
-	PIS_SRC_TIMER2 = 3,	/**< Modulate source is TIMER2 */
-	PIS_SRC_TIMER3 = 4,	/**< Modulate source is TIMER3 */
-	PIS_SRC_TIMER6 = 5,	/**< Modulate source is TIMER6 */
-	PIS_SRC_TIMER7 = 6,	/**< Modulate source is TIMER7 */
-	PIS_SRC_LPTIM0 = 7,	/**< Modulate source is LPTIM0 */
-	PIS_SRC_BUZ    = 8,	/**< Modulate source is buz */
-} pis_modu_src_t;
-
-/**
-  * @brief PIS modulate channel
-  */
-typedef enum {
-	PIS_TIMER_CH1 = 0,	/**< Src is TIMERx and choose channel 1 */
-	PIS_TIMER_CH2 = 1,	/**< Src is TIMERx and choose channel 2 */
-	PIS_TIMER_CH3 = 2,	/**< Src is TIMERx and choose channel 3 */
-	PIS_TIMER_CH4 = 3,	/**< Src is TIMERx and choose channel 4 */
-} pis_modu_channel_t;
-
-/**
-  * @brief PIS init structure definition
-  */
-typedef struct {
-	pis_src_t producer_src;		/**< Producer entry */
-	pis_clock_t producer_clk;	/**< Producer module clock */
-	pis_edge_t producer_edge;	/**< Producer module pin output edge */
-	pis_trig_t consumer_trig;	/**< Consumer entry */
-	pis_clock_t consumer_clk;	/**< Consumer clock */
-} pis_init_t;
-
-/**
-  * @brief PIS modulate config structure definition
-  */
-typedef struct {
-	pis_modu_targ_t target;		/**< Modulate target */
-	pis_modu_level_t level;		/**< Modulate level */
-	pis_modu_src_t src;		/**< Modulate src */
-	pis_modu_channel_t channel;	/**< Modulate channel */
-} pis_modulate_config_t;
-
-/**
-  * @brief  PIS Handle Structure definition
-  */
-typedef struct pis_handle_s {
-	PIS_TypeDef *perh;		/**< Register base address */
-	pis_init_t init;		/**< PIS required parameters */
-	pis_ch_t consumer_ch;		/**< Indirect value, no care of it */
-	pis_con_t consumer_con;		/**< Indirect value, no care of it */
-	uint8_t consumer_pos;	        /**< Indirect value, no care of it */
-	uint32_t check_info;		/**< When destroy a handle ,user need check whether is right that ready to destroy */
-	lock_state_t lock;		/**< Locking object */
-	pis_state_t state;		/**< PIS operation state */
-} pis_handle_t;
-/**
-  * @}
-  */
-
-
-/** @defgroup PIS_Private_Macros PIS Private Macros
-  * @{
-  */
-#define IS_PIS(x) 		(((x) == PIS))
-#define IS_PIS_SRC(x) 		(((x) == PIS_NON)               || \
-				 ((x) == PIS_GPIO_PIN0)         || \
-				 ((x) == PIS_GPIO_PIN1)         || \
-				 ((x) == PIS_GPIO_PIN2)         || \
-				 ((x) == PIS_GPIO_PIN3)         || \
-				 ((x) == PIS_GPIO_PIN4)         || \
-				 ((x) == PIS_GPIO_PIN5)         || \
-				 ((x) == PIS_GPIO_PIN6)         || \
-				 ((x) == PIS_GPIO_PIN7)         || \
-				 ((x) == PIS_GPIO_PIN8)         || \
-				 ((x) == PIS_GPIO_PIN9)         || \
-				 ((x) == PIS_GPIO_PIN10)        || \
-				 ((x) == PIS_GPIO_PIN11)        || \
-				 ((x) == PIS_GPIO_PIN12)        || \
-				 ((x) == PIS_GPIO_PIN13)        || \
-				 ((x) == PIS_GPIO_PIN14)        || \
-				 ((x) == PIS_GPIO_PIN15)        || \
-				 ((x) == PIS_ACMP_OUT0)         || \
-				 ((x) == PIS_ACMP_OUT1)         || \
-				 ((x) == PIS_DAC0_CH1)          || \
-				 ((x) == PIS_ACMP_OUT1)         || \
-				 ((x) == PIS_ADC0_INJECT)       || \
-				 ((x) == PIS_ADC0_REGULAT)      || \
-				 ((x) == PIS_ADC0_WINDOW)       || \
-				 ((x) == PIS_LVD)               || \
-				 ((x) == PIS_UART0_ASY_SEND)    || \
-				 ((x) == PIS_UART0_ASY_RECV)    || \
-				 ((x) == PIS_UART0_IRDAOUT)     || \
-				 ((x) == PIS_UART0_RTSOUT)      || \
-				 ((x) == PIS_UART0_TXOUT)       || \
-				 ((x) == PIS_UART0_SYN_SEND)    || \
-				 ((x) == PIS_UART0_SYN_RECV)    || \
-				 ((x) == PIS_UART1_ASY_SEND)    || \
-				 ((x) == PIS_UART1_ASY_RECV)    || \
-				 ((x) == PIS_UART1_IRDA)        || \
-				 ((x) == PIS_UART1_RTS)         || \
-				 ((x) == PIS_UART1_TXOUT)       || \
-				 ((x) == PIS_UART1_SYN_SEND)    || \
-				 ((x) == PIS_UART1_SYN_RECV)    || \
-				 ((x) == PIS_UART2_ASY_SEND)    || \
-				 ((x) == PIS_UART2_ASY_RECV)    || \
-				 ((x) == PIS_UART2_IRDA)        || \
-				 ((x) == PIS_UART2_RTS)         || \
-				 ((x) == PIS_UART2_TXOUT)       || \
-				 ((x) == PIS_UART2_SYN_SEND)    || \
-				 ((x) == PIS_UART2_SYN_RECV)    || \
-				 ((x) == PIS_UART3_ASY_SEND)    || \
-				 ((x) == PIS_UART3_ASY_RECV)    || \
-				 ((x) == PIS_UART3_IRDA)        || \
-				 ((x) == PIS_UART3_RTS)         || \
-				 ((x) == PIS_UART3_TXOUT)       || \
-				 ((x) == PIS_UART3_SYN_SEND)    || \
-				 ((x) == PIS_UART3_SYN_RECV)    || \
-				 ((x) == PIS_EUART0_RECV)       || \
-				 ((x) == PIS_EUART0_SEND)       || \
-				 ((x) == PIS_EUART0_TXOUT)      || \
-				 ((x) == PIS_EUART1_RECV)       || \
-				 ((x) == PIS_EUART1_SEND)       || \
-				 ((x) == PIS_EUART1_TXOUT)      || \
-				 ((x) == PIS_SPI0_RECV)         || \
-				 ((x) == PIS_SPI0_SEND)         || \
-				 ((x) == PIS_SPI0_NE)           || \
-				 ((x) == PIS_SPI1_RECV)         || \
-				 ((x) == PIS_SPI1_SEND)         || \
-				 ((x) == PIS_SPI1_NE)           || \
-				 ((x) == PIS_I2C0_RECV)         || \
-				 ((x) == PIS_I2C0_SEND)         || \
-				 ((x) == PIS_I2C1_RECV)         || \
-				 ((x) == PIS_I2C1_SEND)         || \
-				 ((x) == PIS_TIMER0_UPDATA)       || \
-				 ((x) == PIS_TIMER0_TRIG)         || \
-				 ((x) == PIS_TIMER0_INPUT)        || \
-				 ((x) == PIS_TIMER0_OUTPUT)       || \
-				 ((x) == PIS_TIMER1_UPDATA)       || \
-				 ((x) == PIS_TIMER1_TRIG)         || \
-				 ((x) == PIS_TIMER1_INPUT)        || \
-				 ((x) == PIS_TIMER1_OUTPUT)       || \
-				 ((x) == PIS_TIMER2_UPDATA)       || \
-				 ((x) == PIS_TIMER2_TRIG)         || \
-				 ((x) == PIS_TIMER2_INPUT)        || \
-				 ((x) == PIS_TIMER2_OUTPUT)       || \
-				 ((x) == PIS_TIMER3_UPDATA)       || \
-				 ((x) == PIS_TIMER3_TRIG)         || \
-				 ((x) == PIS_TIMER3_INPUT)        || \
-				 ((x) == PIS_TIMER3_OUTPUT)       || \
-				 ((x) == PIS_RTC_CLOCK)         || \
-				 ((x) == PIS_RTC_ALARM)         || \
-				 ((x) == PIS_LPTIM0_SYN_UPDATA) || \
-				 ((x) == PIS_LPTIM0_ASY_UPDATA) || \
-				 ((x) == PIS_LPUART0_ASY_RECV)  || \
-				 ((x) == PIS_LPUART0_ASY_SEND)  || \
-				 ((x) == PIS_LPUART0_SYN_RECV)  || \
-				 ((x) == PIS_LPUART0_SYN_SEND)  || \
-				 ((x) == PIS_DMA)               || \
-				 ((x) == PIS_ADC1_INJECT)       || \
-				 ((x) == PIS_ADC1_REGULAT)      || \
-				 ((x) == PIS_ADC1_WINDOW))
-#define IS_PIS_TRIG(x) 		(((x) == PIS_CH0_TIMER0_BRKIN)    || \
-				 ((x) == PIS_CH0_SPI1_CLK)      || \
-				 ((x) == PIS_CH0_LPTIM0_EXT0)   || \
-				 ((x) == PIS_CH0_ADC1_NORMAL)   || \
-				 ((x) == PIS_CH1_TIMER0_CH1IN)    || \
-				 ((x) == PIS_CH1_TIMER2_CH1IN)    || \
-				 ((x) == PIS_CH1_TIMER3_CH1IN)    || \
-				 ((x) == PIS_CH1_UART0_RX_IRDA) || \
-				 ((x) == PIS_CH1_LPTIM0_EXT1)   || \
-				 ((x) == PIS_CH1_ADC1_INSERT)   || \
-				 ((x) == PIS_CH2_TIMER0_CH2IN)    || \
-				 ((x) == PIS_CH2_TIMER2_CH2IN)    || \
-				 ((x) == PIS_CH2_TIMER3_CH2IN)    || \
-				 ((x) == PIS_CH2_LPTIM0_EXT2)   || \
-				 ((x) == PIS_CH2_UART1_RX_IRDA) || \
-				 ((x) == PIS_CH3_TIMER0_CH3IN)    || \
-				 ((x) == PIS_CH3_LPTIM0_EXT3)   || \
-				 ((x) == PIS_CH3_UART2_RX_IRDA) || \
-				 ((x) == PIS_CH4_TIMER0_CH4IN)    || \
-				 ((x) == PIS_CH4_TIMER0_ITR0)     || \
-				 ((x) == PIS_CH4_TIMER2_ITR0)     || \
-				 ((x) == PIS_CH4_TIMER3_ITR0)     || \
-				 ((x) == PIS_CH4_LPTIM0_EXT4)   || \
-				 ((x) == PIS_CH4_UART3_RX_IRDA) || \
-				 ((x) == PIS_CH5_SPI0_RX)       || \
-				 ((x) == PIS_CH5_LPTIM0_EXT5)   || \
-				 ((x) == PIS_CH5_EUART0_RX)     || \
-				 ((x) == PIS_CH5_TIMER0_ITR1)     || \
-				 ((x) == PIS_CH5_TIMER2_ITR1)     || \
-				 ((x) == PIS_CH5_TIMER3_ITR1)     || \
-				 ((x) == PIS_CH6_SPI0_CLK)      || \
-				 ((x) == PIS_CH6_ADC0_NORMAL)   || \
-				 ((x) == PIS_CH6_LPTIM0_EXT6)   || \
-				 ((x) == PIS_CH6_EUART1_RX)     || \
-				 ((x) == PIS_CH6_TIMER0_ITR2)     || \
-				 ((x) == PIS_CH6_TIMER2_ITR2)     || \
-				 ((x) == PIS_CH6_TIMER3_ITR2)     || \
-				 ((x) == PIS_CH6_DAC_CH1)       || \
-				 ((x) == PIS_CH7_SPI1_RX)       || \
-				 ((x) == PIS_CH7_ADC0_INSERT)   || \
-				 ((x) == PIS_CH7_LPTIM0_EXT7)   || \
-				 ((x) == PIS_CH7_DMA)           || \
-				 ((x) == PIS_CH7_TIMER0_ITR3)     || \
-				 ((x) == PIS_CH7_TIMER2_ITR3)     || \
-				 ((x) == PIS_CH7_TIMER3_ITR3)     || \
-				 ((x) == PIS_CH7_DAC_CH0)       || \
-				 ((x) == PIS_CH7_LPUART_RX))
-#define IS_PIS_CLOCK(x) 	(((x) == PIS_CLK_PCLK1)  || \
-				 ((x) == PIS_CLK_PCLK2)  || \
-				 ((x) == PIS_CLK_SYS) || \
-				 ((x) == PIS_CLK_LP))
-#define IS_PIS_EDGE(x) 		(((x) == PIS_EDGE_NONE) || \
-				 ((x) == PIS_EDGE_UP)   || \
-				 ((x) == PIS_EDGE_DOWN) || \
-				 ((x) == PIS_EDGE_UP_DOWN))
-#define IS_PIS_OUTPUT(x) 	(((x) == PIS_OUT_LEVEL) || \
-				 ((x) == PIS_OUT_PULSE))
-#define IS_PIS_OUPUT_CH(x)	(((x) == PIS_OUT_CH_0) || \
-				 ((x) == PIS_OUT_CH_1) || \
-				 ((x) == PIS_OUT_CH_2) || \
-				 ((x) == PIS_OUT_CH_3))
-#define IS_PIS_MODU_TARGET(x)	(((x) == PIS_UART0_TX) || \
-				 ((x) == PIS_UART1_TX) || \
-				 ((x) == PIS_UART2_TX) || \
-				 ((x) == PIS_UART3_TX) || \
-				 ((x) == PIS_LPUART0_TX))
-#define IS_PIS_MODU_LEVEL(x)	(((x) == PIS_LOW_LEVEL) || \
-				 ((x) == PIS_HIGH_LEVEL))
-#define IS_PIS_MODU_SRC(x)	(((x) == PIS_SRC_NONE)   || \
-				 ((x) == PIS_SRC_TIMER0)   || \
-				 ((x) == PIS_SRC_TIMER1)   || \
-				 ((x) == PIS_SRC_TIMER2)   || \
-				 ((x) == PIS_SRC_TIMER3)   || \
-				 ((x) == PIS_SRC_TIMER6)   || \
-				 ((x) == PIS_SRC_TIMER7)   || \
-				 ((x) == PIS_SRC_LPTIM0) || \
-				 ((x) == PIS_SRC_BUZ))
-#define IS_PIS_MODU_CHANNEL(x)	(((x) == PIS_TIMER_CH1) || \
-				 ((x) == PIS_TIMER_CH2) || \
-				 ((x) == PIS_TIMER_CH3) || \
-				 ((x) == PIS_TIMER_CH4))
-/**
-  * @}
-  */
-
-/** @addtogroup PIS_Public_Functions
-  * @{
-  */
-
-/** @addtogroup PIS_Public_Functions_Group1
-  * @{
-  */
-ald_status_t pis_create(pis_handle_t *hperh);
-ald_status_t pis_destroy(pis_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup PIS_Public_Functions_Group2
-  * @{
-  */
-ald_status_t pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch);
-ald_status_t pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch);
-/**
-  * @}
-  */
-
-/** @addtogroup PIS_Public_Functions_Group3
-  * @{
-  */
-pis_state_t pis_get_state(pis_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup PIS_Public_Functions_Group4
-  * @{
-  */
-ald_status_t pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_PIS_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pmu.h

@@ -1,275 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_pmu.h
-  * @brief   Header file of PMU module driver.
-  *
-  * @version V1.0
-  * @date    04 Dec 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  ********************************************************************************
-  */
-
-#ifndef __ALD_PMU_H__
-#define __ALD_PMU_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_syscfg.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup PMU
-  * @{
-  */
-
-/** @defgroup PMU_Public_Macros PMU Public Macros
-  * @{
-  */
-#define PMU_SRAM0_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define PMU_SRAM0_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\
-	SYSCFG_LOCK();					\
-} while (0)
-#define PMU_SRAM1_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define PMU_SRAM1_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\
-	SYSCFG_LOCK();					\
-} while (0)
-#define PMU_BXCAN_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define PMU_BXCAN_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-
-#define PMU_LPSTOP_ENABLE()			\
-do {						\
-	SYSCFG_UNLOCK();			\
-	SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);	\
-	SYSCFG_LOCK();				\
-} while (0)
-#define PMU_LPSTOP_DISABLE()			\
-do {						\
-	SYSCFG_UNLOCK();			\
-	CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);	\
-	SYSCFG_LOCK();				\
-} while (0)
-#define PMU_MTSTOP_ENABLE()			\
-do {						\
-	SYSCFG_UNLOCK();			\
-	SET_BIT(PMU->CR, PMU_CR_MTSTOP_MSK);	\
-	SYSCFG_LOCK();				\
-} while (0)
-#define PMU_MTSTOP_DISABLE()			\
-do {						\
-	SYSCFG_UNLOCK();			\
-	CLEAR_BIT(PMU->CR, PMU_CR_MTSTOP_MSK);	\
-	SYSCFG_LOCK();				\
-} while (0)
-
-#define PMU_GET_LVD_STATUS()	(READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS))
-/**
-  * @}
-  */
-
-
-/** @defgroup PMU_Public_Types PMU Public Types
-  * @{
-  */
-/**
-  * @brief Standby wakeup port select
-  */
-typedef enum {
-	PMU_STANDBY_PORT_SEL_PA0 = 0x0,	/**< PA0 */
-	PMU_STANDBY_PORT_SEL_PA1 = 0x1,	/**< PA1 */
-	PMU_STANDBY_PORT_SEL_PA2 = 0x2,	/**< PA2 */
-	PMU_STANDBY_PORT_SEL_PA3 = 0x3,	/**< PA3 */
-	PMU_STANDBY_PORT_SEL_PA4 = 0x4,	/**< PA4 */
-	PMU_STANDBY_PORT_SEL_PA5 = 0x5,	/**< PA5 */
-	PMU_STANDBY_PORT_SEL_PA6 = 0x6,	/**< PA6 */
-	PMU_STANDBY_PORT_SEL_PA7 = 0x7,	/**< PA7 */
-	PMU_STANDBY_PORT_NONE    = 0xF,	/**< NONE */
-} pmu_standby_wakeup_sel_t;
-
-/**
-  * @brief Low power mode
-  */
-typedef enum {
-	PMU_LP_STOP1   = 0x0,	/**< Stop1 */
-	PMU_LP_STOP2   = 0x1,	/**< Stop2 */
-	PMU_LP_STANDBY = 0x2,	/**< Standby */
-} pmu_lp_mode_t;
-
-typedef enum {
-	PMU_SR_WUF      = (1U << 0),
-	PMU_SR_STANDBYF = (1U << 1),
-} pmu_status_t;
-
-/**
-  * @brief LVD voltage select
-  */
-typedef enum {
-	PMU_LVD_VOL_SEL_2_0 = 0x0,	/**< 2.0V ~ 2.05V */
-	PMU_LVD_VOL_SEL_2_1 = 0x1,	/**< 2.1V ~ 2.15V */
-	PMU_LVD_VOL_SEL_2_2 = 0x2,	/**< 2.2V ~ 2.25V */
-	PMU_LVD_VOL_SEL_2_4 = 0x3,	/**< 2.4V ~ 2.45V */
-	PMU_LVD_VOL_SEL_2_6 = 0x4,	/**< 2.6V ~ 2.65V */
-	PMU_LVD_VOL_SEL_2_8 = 0x5,	/**< 2.8V ~ 2.85V */
-	PMU_LVD_VOL_SEL_3_0 = 0x6,	/**< 3.0V ~ 3.05V */
-	PMU_LVD_VOL_SEL_3_6 = 0x7,	/**< 3.6V ~ 3.65V */
-	PMU_LVD_VOL_SEL_4_0 = 0x8,	/**< 4.0V ~ 4.05V */
-	PMU_LVD_VOL_SEL_4_6 = 0x9,	/**< 4.6V ~ 4.65V */
-	PMU_LVD_VOL_SEL_2_3 = 0xA,	/**< 2.3V ~ 2.35V */
-	PMU_LVD_VOL_SEL_EXT = 0xF,	/**< Select external input. It must be 1.2V */
-} pmu_lvd_voltage_sel_t;
-
-/**
-  * @brief LVD trigger mode
-  */
-typedef enum {
-	PMU_LVD_TRIGGER_RISING_EDGE    = 0x0,	/**< Rising edge */
-	PMU_LVD_TRIGGER_FALLING_EDGE   = 0x1,	/**< Falling edge */
-	PMU_LVD_TRIGGER_HIGH_LEVEL     = 0x2,	/**< High level */
-	PMU_LVD_TRIGGER_LOW_LEVEL      = 0x3,	/**< Low level */
-	PMU_LVD_TRIGGER_RISING_FALLING = 0x4,	/**< Rising and falling edge */
-} pmu_lvd_trigger_mode_t;
-
-/**
-  * @brief LDO output voltage selest in low power mode
-  */
-typedef enum {
-	PMU_LDO_LPMODE_OUTPUT_1_5 = 0x0,	/**< 1.5V */
-	PMU_LDO_LPMODE_OUTPUT_1_4 = 0x1,	/**< 1.4V */
-	PMU_LDO_LPMODE_OUTPUT_1_3 = 0x2,	/**< 1.3V */
-	PMU_LDO_LPMODE_OUTPUT_1_2 = 0x4,	/**< 1.2V */
-} pmu_ldo_lpmode_output_t;
-/**
-  * @}
-  */
-
-/**
-  * @defgroup PMU_Private_Macros PMU Private Macros
-  * @{
-  */
-#define IS_PMU_STANDBY_PORT_SEL(x)	(((x) == PMU_STANDBY_PORT_SEL_PA0) || \
-                                         ((x) == PMU_STANDBY_PORT_SEL_PA1) || \
-                                         ((x) == PMU_STANDBY_PORT_SEL_PA2) || \
-                                         ((x) == PMU_STANDBY_PORT_SEL_PA3) || \
-                                         ((x) == PMU_STANDBY_PORT_SEL_PA4) || \
-                                         ((x) == PMU_STANDBY_PORT_SEL_PA5) || \
-                                         ((x) == PMU_STANDBY_PORT_SEL_PA6) || \
-                                         ((x) == PMU_STANDBY_PORT_SEL_PA7) || \
-                                         ((x) == PMU_STANDBY_PORT_NONE))
-#define IS_PMU_LP_MODE(x)		(((x) == PMU_LP_STOP1) || \
-                                         ((x) == PMU_LP_STOP2) || \
-                                         ((x) == PMU_LP_STANDBY))
-#define IS_PMU_STATUS(x)		(((x) == PMU_SR_WUF) || \
-                                         ((x) == PMU_SR_STANDBYF))
-#define IS_PMU_LVD_VOL_SEL(x)		(((x) == PMU_LVD_VOL_SEL_2_0) || \
-                                         ((x) == PMU_LVD_VOL_SEL_2_1) || \
-                                         ((x) == PMU_LVD_VOL_SEL_2_2) || \
-                                         ((x) == PMU_LVD_VOL_SEL_2_4) || \
-                                         ((x) == PMU_LVD_VOL_SEL_2_6) || \
-                                         ((x) == PMU_LVD_VOL_SEL_2_8) || \
-                                         ((x) == PMU_LVD_VOL_SEL_3_0) || \
-                                         ((x) == PMU_LVD_VOL_SEL_3_6) || \
-                                         ((x) == PMU_LVD_VOL_SEL_4_0) || \
-                                         ((x) == PMU_LVD_VOL_SEL_4_6) || \
-                                         ((x) == PMU_LVD_VOL_SEL_2_3) || \
-                                         ((x) == PMU_LVD_VOL_SEL_EXT))
-#define IS_PMU_LVD_TRIGGER_MODE(x)	(((x) == PMU_LVD_TRIGGER_RISING_EDGE)  || \
-                                         ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \
-                                         ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL)   || \
-                                         ((x) == PMU_LVD_TRIGGER_LOW_LEVEL)    || \
-                                         ((x) == PMU_LVD_TRIGGER_RISING_FALLING))
-#define IS_PMU_LDO_LPMODE_OUTPUT(x)	(((x) == PMU_LDO_LPMODE_OUTPUT_1_5) || \
-                                         ((x) == PMU_LDO_LPMODE_OUTPUT_1_4) || \
-                                         ((x) == PMU_LDO_LPMODE_OUTPUT_1_3) || \
-                                         ((x) == PMU_LDO_LPMODE_OUTPUT_1_2))
-/**
-  * @}
-  */
-
-/** @addtogroup PMU_Public_Functions
-  * @{
-  */
-/** @addtogroup PMU_Public_Functions_Group1
-  * @{
-  */
-/* Low power mode select */
-__STATIC_INLINE__ void __sleep()
-{
-	__WFI();
-}
-
-__STATIC_INLINE__ void __sleep_deep()
-{
-	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-	__WFI();
-}
-
-void pmu_stop1_enter(void);
-void pmu_stop2_enter(void);
-void pmu_standby_enter(pmu_standby_wakeup_sel_t port);
-void pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state);
-flag_status_t pmu_get_status(pmu_status_t sr);
-void pmu_clear_status(pmu_status_t sr);
-/**
-  * @}
-  */
-/** @addtogroup PMU_Public_Functions_Group2
-  * @{
-  */
-/* LVD configure */
-void pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state);
-void lvd_irq_cbk(void);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_PMU_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rmu.h

@@ -1,261 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_rmu.h
-  * @brief   Header file of RMU module driver.
-  *
-  * @version V1.0
-  * @date    04 Dec 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  ********************************************************************************
-  */
-
-#ifndef __ALD_RMU_H__
-#define __ALD_RMU_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup RMU
-  * @{
-  */
-
-/** @defgroup RMU_Public_Types RMU Public Types
-  * @{
-  */
-/**
-  * @brief RMU BOR fliter
-  */
-typedef enum {
-	RMU_BORFLT_1 = 0x1,	/**< 1 cycle  */
-	RMU_BORFLT_2 = 0x2,	/**< 2 cycles */
-	RMU_BORFLT_3 = 0x3,	/**< 3 cycles */
-	RMU_BORFLT_4 = 0x4,	/**< 4 cycles */
-	RMU_BORFLT_5 = 0x5,	/**< 5 cycles */
-	RMU_BORFLT_6 = 0x6,	/**< 6 cycles */
-	RMU_BORFLT_7 = 0x7,	/**< 7 cycles */
-} rmu_bor_filter_t;
-
-/**
-  * @brief RMU BOR voltage
-  */
-typedef enum {
-	RMU_VOL_1_7 = 0x0,	/**< 1.7V */
-	RMU_VOL_2_0 = 0x1,	/**< 2.0V */
-	RMU_VOL_2_1 = 0x2,	/**< 2.1V */
-	RMU_VOL_2_2 = 0x3,	/**< 2.2V */
-	RMU_VOL_2_3 = 0x4,	/**< 2.3V */
-	RMU_VOL_2_4 = 0x5,	/**< 2.4V */
-	RMU_VOL_2_5 = 0x6,	/**< 2.5V */
-	RMU_VOL_2_6 = 0x7,	/**< 2.6V */
-	RMU_VOL_2_8 = 0x8,	/**< 2.8V */
-	RMU_VOL_3_0 = 0x9,	/**< 3.0V */
-	RMU_VOL_3_1 = 0xA,	/**< 3.1V */
-	RMU_VOL_3_3 = 0xB,	/**< 3.3V */
-	RMU_VOL_3_6 = 0xC,	/**< 3.6V */
-	RMU_VOL_3_7 = 0xD,	/**< 3.7V */
-	RMU_VOL_4_0 = 0xE,	/**< 4.0V */
-	RMU_VOL_4_3 = 0xF,	/**< 4.3V */
-} rmu_bor_vol_t;
-
-/**
-  * @brief RMU reset status
-  */
-typedef enum {
-	RMU_RST_POR    = (1U << 0),	/**< POR */
-	RMU_RST_WAKEUP = (1U << 1),	/**< WAKEUP */
-	RMU_RST_BOR    = (1U << 2),	/**< BOR */
-	RMU_RST_NMRST  = (1U << 3),	/**< NMRST */
-	RMU_RST_IWDT   = (1U << 4),	/**< IWDT */
-	RMU_RST_WWDT   = (1U << 5),	/**< WWDT */
-	RMU_RST_LOCKUP = (1U << 6),	/**< LOCKUP */
-	RMU_RST_CHIP   = (1U << 7),	/**< CHIP */
-	RMU_RST_MCU    = (1U << 8),	/**< MCU */
-	RMU_RST_CPU    = (1U << 9),	/**< CPU */
-	RMU_RST_CFG    = (1U << 10),	/**< CFG */
-	RMU_RST_CFGERR = (1U << 16),	/**< CFG Error */
-} rmu_state_t;
-
-/**
-  * @brief RMU periperal select bit
-  */
-typedef enum {
-	RMU_PERH_GPIO    = (1U << 0),			/**< AHB1: GPIO */
-	RMU_PERH_CRC     = (1U << 1),			/**< AHB1: CRC */
-	RMU_PERH_CALC    = (1U << 2),			/**< AHB1: CALC */
-	RMU_PERH_CRYPT   = (1U << 3),			/**< AHB1: CRYPT */
-	RMU_PERH_TRNG    = (1U << 4),			/**< AHB1: TRNG */
-	RMU_PERH_PIS     = (1U << 5),			/**< AHB1: PIS */
-	RMU_PERH_CHIP    = (1U << 0)  | (1U << 27),	/**< AHB2: CHIP */
-	RMU_PERH_CPU     = (1U << 1)  | (1U << 27),	/**< AHB2: CPU */
-	RMU_PERH_TIM0    = (1U << 0)  | (1U << 28),	/**< APB1: TIM0 */
-	RMU_PERH_TIM1    = (1U << 1)  | (1U << 28),	/**< APB1: TIM1 */
-	RMU_PERH_TIM2    = (1U << 2)  | (1U << 28),	/**< APB1: TIM2 */
-	RMU_PERH_TIM3    = (1U << 3)  | (1U << 28),	/**< APB1: TIM3 */
-	RMU_PERH_TIM4    = (1U << 4)  | (1U << 28),	/**< APB1: TIM4 */
-	RMU_PERH_TIM5    = (1U << 5)  | (1U << 28),	/**< APB1: TIM5 */
-	RMU_PERH_TIM6    = (1U << 6)  | (1U << 28),	/**< APB1: TIM6 */
-	RMU_PERH_TIM7    = (1U << 7)  | (1U << 28),	/**< APB1: TIM7 */
-	RMU_PERH_UART0   = (1U << 8)  | (1U << 28),	/**< APB1: UART0 */
-	RMU_PERH_UART1   = (1U << 9)  | (1U << 28),	/**< APB1: UART1 */
-	RMU_PERH_UART2   = (1U << 10) | (1U << 28),	/**< APB1: UART2 */
-	RMU_PERH_UART3   = (1U << 11) | (1U << 28),	/**< APB1: UART3 */
-	RMU_PERH_USART0  = (1U << 12) | (1U << 28),	/**< APB1: EUART0 */
-	RMU_PERH_USART1  = (1U << 13) | (1U << 28),	/**< APB1: EUART1 */
-	RMU_PERH_SPI0    = (1U << 16) | (1U << 28),	/**< APB1: SPI0 */
-	RMU_PERH_SPI1    = (1U << 17) | (1U << 28),	/**< APB1: SPI1 */
-	RMU_PERH_SPI2    = (1U << 18) | (1U << 28),	/**< APB1: SPI2 */
-	RMU_PERH_I2C0    = (1U << 20) | (1U << 28),	/**< APB1: I2C0 */
-	RMU_PERH_I2C1    = (1U << 21) | (1U << 28),	/**< APB1: I2C1 */
-	RMU_PERH_CAN0    = (1U << 24) | (1U << 28),	/**< APB1: CAN0 */
-	RMU_PERH_LPTIM0  = (1U << 0)  | (1U << 29),	/**< APB2: LPTIM0 */
-	RMU_PERH_LPUART0 = (1U << 2)  | (1U << 29),	/**< APB2: LPUART */
-	RMU_PERH_ADC0    = (1U << 4)  | (1U << 29),	/**< APB2: ADC0 */
-	RMU_PERH_ADC1    = (1U << 5)  | (1U << 29),	/**< APB2: ADC1 */
-	RMU_PERH_ACMP0   = (1U << 6)  | (1U << 29),	/**< APB2: ACMP0 */
-	RMU_PERH_ACMP1   = (1U << 7)  | (1U << 29),	/**< APB2: ACMP1 */
-	RMU_PERH_OPAMP   = (1U << 8)  | (1U << 29),	/**< APB2: OPAMP */
-	RMU_PERH_DAC0    = (1U << 9)  | (1U << 29),	/**< APB2: DAC0 */
-	RMU_PERH_WWDT    = (1U << 12) | (1U << 29),	/**< APB2: WWDT */
-	RMU_PERH_LCD     = (1U << 13) | (1U << 29),	/**< APB2: LCD */
-	RMU_PERH_IWDT    = (1U << 14) | (1U << 29),	/**< APB2: IWDT */
-	RMU_PERH_RTC     = (1U << 15) | (1U << 29),	/**< APB2: RTC */
-	RMU_PERH_TEMP    = (1U << 16) | (1U << 29),	/**< APB2: TEMP */
-	RMU_PERH_BKPC    = (1U << 17) | (1U << 29),	/**< APB2: BKPC */
-	RMU_PERH_BKPRAM  = (1U << 18) | (1U << 29),	/**< APB2: BKPRAM */
-} rmu_peripheral_t;
-/**
-  * @}
-  */
-
-/**
-  * @defgroup RMU_Private_Macros RMU Private Macros
-  * @{
-  */
-#define IS_RMU_BORFLT(x)	(((x) == RMU_BORFLT_1) || \
-                                 ((x) == RMU_BORFLT_2) || \
-                                 ((x) == RMU_BORFLT_3) || \
-                                 ((x) == RMU_BORFLT_4) || \
-                                 ((x) == RMU_BORFLT_5) || \
-                                 ((x) == RMU_BORFLT_6) || \
-                                 ((x) == RMU_BORFLT_7))
-#define IS_RMU_BORVOL(x)	(((x) == RMU_VOL_1_7) || \
-                                 ((x) == RMU_VOL_2_0) || \
-                                 ((x) == RMU_VOL_2_1) || \
-                                 ((x) == RMU_VOL_2_2) || \
-                                 ((x) == RMU_VOL_2_3) || \
-                                 ((x) == RMU_VOL_2_4) || \
-                                 ((x) == RMU_VOL_2_5) || \
-                                 ((x) == RMU_VOL_2_6) || \
-                                 ((x) == RMU_VOL_2_8) || \
-                                 ((x) == RMU_VOL_3_0) || \
-                                 ((x) == RMU_VOL_3_1) || \
-                                 ((x) == RMU_VOL_3_3) || \
-                                 ((x) == RMU_VOL_3_6) || \
-                                 ((x) == RMU_VOL_3_7) || \
-                                 ((x) == RMU_VOL_4_0) || \
-                                 ((x) == RMU_VOL_4_3))
-#define IS_RMU_STATE(x)		(((x) == RMU_RST_POR)    || \
-                                 ((x) == RMU_RST_WAKEUP) || \
-                                 ((x) == RMU_RST_BOR)    || \
-                                 ((x) == RMU_RST_NMRST)  || \
-                                 ((x) == RMU_RST_IWDT)   || \
-                                 ((x) == RMU_RST_WWDT)   || \
-                                 ((x) == RMU_RST_LOCKUP) || \
-                                 ((x) == RMU_RST_CHIP)   || \
-                                 ((x) == RMU_RST_MCU)    || \
-                                 ((x) == RMU_RST_CPU)    || \
-                                 ((x) == RMU_RST_CFG)    || \
-                                 ((x) == RMU_RST_CFGERR))
-#define IS_RMU_STATE_CLEAR(x)	(((x) == RMU_RST_POR)    || \
-                                 ((x) == RMU_RST_WAKEUP) || \
-                                 ((x) == RMU_RST_BOR)    || \
-                                 ((x) == RMU_RST_NMRST)  || \
-                                 ((x) == RMU_RST_IWDT)   || \
-                                 ((x) == RMU_RST_WWDT)   || \
-                                 ((x) == RMU_RST_LOCKUP) || \
-                                 ((x) == RMU_RST_CHIP)   || \
-                                 ((x) == RMU_RST_MCU)    || \
-                                 ((x) == RMU_RST_CPU)    || \
-                                 ((x) == RMU_RST_CFG))
-#define IS_RMU_PERH(x)		(((x) == RMU_PERH_GPIO)    || \
-                                 ((x) == RMU_PERH_CRC)     || \
-                                 ((x) == RMU_PERH_CALC)    || \
-                                 ((x) == RMU_PERH_CRYPT)   || \
-                                 ((x) == RMU_PERH_TRNG)    || \
-                                 ((x) == RMU_PERH_PIS)     || \
-                                 ((x) == RMU_PERH_CHIP)    || \
-                                 ((x) == RMU_PERH_CPU)     || \
-                                 ((x) == RMU_PERH_TIM0)    || \
-                                 ((x) == RMU_PERH_TIM1)    || \
-                                 ((x) == RMU_PERH_TIM2)    || \
-                                 ((x) == RMU_PERH_TIM3)    || \
-                                 ((x) == RMU_PERH_TIM4)    || \
-                                 ((x) == RMU_PERH_TIM5)    || \
-                                 ((x) == RMU_PERH_TIM6)    || \
-                                 ((x) == RMU_PERH_TIM7)    || \
-                                 ((x) == RMU_PERH_UART0)   || \
-                                 ((x) == RMU_PERH_UART1)   || \
-                                 ((x) == RMU_PERH_UART2)   || \
-                                 ((x) == RMU_PERH_UART3)   || \
-                                 ((x) == RMU_PERH_USART0)  || \
-                                 ((x) == RMU_PERH_USART1)  || \
-                                 ((x) == RMU_PERH_SPI0)    || \
-                                 ((x) == RMU_PERH_SPI1)    || \
-                                 ((x) == RMU_PERH_SPI2)    || \
-                                 ((x) == RMU_PERH_I2C0)    || \
-                                 ((x) == RMU_PERH_I2C1)    || \
-                                 ((x) == RMU_PERH_CAN0)    || \
-                                 ((x) == RMU_PERH_LPTIM0)  || \
-                                 ((x) == RMU_PERH_LPUART0) || \
-                                 ((x) == RMU_PERH_ADC0)    || \
-                                 ((x) == RMU_PERH_ADC1)    || \
-                                 ((x) == RMU_PERH_ACMP0)   || \
-                                 ((x) == RMU_PERH_ACMP1)   || \
-                                 ((x) == RMU_PERH_OPAMP)   || \
-                                 ((x) == RMU_PERH_DAC0)    || \
-                                 ((x) == RMU_PERH_WWDT)    || \
-                                 ((x) == RMU_PERH_LCD)     || \
-                                 ((x) == RMU_PERH_IWDT)    || \
-                                 ((x) == RMU_PERH_RTC)     || \
-                                 ((x) == RMU_PERH_TEMP)    || \
-                                 ((x) == RMU_PERH_BKPC)    || \
-                                 ((x) == RMU_PERH_BKPRAM))
-/**
-  * @}
-  */
-
-/** @addtogroup RMU_Public_Functions
-  * @{
-  */
-void rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state);
-flag_status_t rmu_get_reset_status(rmu_state_t state);
-void rmu_clear_reset_status(rmu_state_t state);
-void rmu_reset_periperal(rmu_peripheral_t perh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_RMU_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rtc.h

@@ -1,669 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ald_rtc.h
-  * @brief   Header file of RTC Module driver.
-  *
-  * @version V1.0
-  * @date    16 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *******************************************************************************
-  */
-
-#ifndef __ALD_RTC_H__
-#define __ALD_RTC_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup RTC
-  * @{
-  */
-
-/** @defgroup RTC_Public_Types RTC Public Types
-  * @{
-  */
-
-/**
-  * @brief Hours format
-  */
-typedef enum {
-	RTC_HOUR_FORMAT_24 = 0x0,	/**< 24-hours format */
-	RTC_HOUR_FORMAT_12 = 0x1,	/**< 12-hours format */
-} rtc_hour_format_t;
-
-/**
-  * @brief Output mode
-  */
-typedef enum {
-	RTC_OUTPUT_DISABLE = 0x0,	/**< Disable output */
-	RTC_OUTPUT_ALARM_A = 0x1,	/**< Output alarm_a signal */
-	RTC_OUTPUT_ALARM_B = 0x2,	/**< Output alarm_b signal */
-	RTC_OUTPUT_WAKEUP  = 0x3,	/**< Output wakeup signal */
-} rtc_output_select_t;
-
-/**
-  * @brief Output polarity
-  */
-typedef enum {
-	RTC_OUTPUT_POLARITY_HIGH = 0x0,	/**< Polarity is high */
-	RTC_OUTPUT_POLARITY_LOW  = 0x0,	/**< Polarity is low */
-} rtc_output_polarity_t;
-
-/**
-  * @brief Initialization structure
-  */
-typedef struct {
-	rtc_hour_format_t hour_format;		/**< Hours format */
-	uint32_t asynch_pre_div;		/**< Asynchronous predivider value */
-	uint32_t synch_pre_div;			/**< Synchronous predivider value */
-	rtc_output_select_t output;		/**< Output signal type */
-	rtc_output_polarity_t output_polarity;	/**< Output polarity */
-} rtc_init_t;
-
-/**
-  * @brief Source select
-  */
-typedef enum {
-	RTC_SOURCE_LOSC        = 0x0,	/**< LOSC */
-	RTC_SOURCE_LRC         = 0x1,	/**< LRC */
-	RTC_SOURCE_HRC_DIV_1M  = 0x2,	/**< HRC divide to 1MHz */
-	RTC_SOURCE_HOSC_DIV_1M = 0x3,	/**< HOSC divide to 1MHz */
-} rtc_source_sel_t;
-
-/**
-  * @brief Time structure
-  */
-typedef struct {
-	uint8_t hour;		/**< Hours */
-	uint8_t minute;		/**< Minutes */
-	uint8_t second;		/**< Seconds */
-	uint16_t sub_sec;	/**< Sub-seconds */
-} rtc_time_t;
-
-/**
-  * @brief Date structure
-  */
-typedef struct {
-	uint8_t week;	/**< Weeks */
-	uint8_t day;	/**< days */
-	uint8_t month;	/**< months */
-	uint8_t year;	/**< years */
-} rtc_date_t;
-
-/**
-  * @brief Data format
-  */
-typedef enum {
-	RTC_FORMAT_DEC = 0,
-	RTC_FORMAT_BCD = 1,
-} rtc_format_t;
-
-/**
-  * @brief Index of alarm
-  */
-typedef enum {
-	RTC_ALARM_A = 0x0,	/**< Alarm-A */
-	RTC_ALARM_B = 0x1,	/**< Alarm-B */
-} rtc_alarm_idx_t;
-
-/**
-  * @brief Alarm mask
-  */
-typedef enum {
-	RTC_ALARM_MASK_NONE     = 0x0,		/**< Mask is disable */
-	RTC_ALARM_MASK_WEEK_DAY = (1U << 30),	/**< Mask week or day */
-	RTC_ALARM_MASK_HOUR     = (1U << 23),	/**< Mask hour */
-	RTC_ALARM_MASK_MINUTE   = (1U << 15),	/**< Mask minute */
-	RTC_ALARM_MASK_SECOND   = (1U << 7),	/**< Mask second */
-	RTC_ALARM_MASK_ALL      = 0x40808080,	/**< Mask all */
-} rtc_alarm_mask_t;
-
-/**
-  * @brief Alarm sub-second mask
-  */
-typedef enum {
-	RTC_ALARM_SS_MASK_NONE  = 0xF,	/**< Mask is disable */
-	RTC_ALARM_SS_MASK_14_1  = 0x1,	/**< Mask bit(1-14) */
-	RTC_ALARM_SS_MASK_14_2  = 0x2,	/**< Mask bit(2-14) */
-	RTC_ALARM_SS_MASK_14_3  = 0x3,	/**< Mask bit(3-14) */
-	RTC_ALARM_SS_MASK_14_4  = 0x4,	/**< Mask bit(4-14) */
-	RTC_ALARM_SS_MASK_14_5  = 0x5,	/**< Mask bit(5-14) */
-	RTC_ALARM_SS_MASK_14_6  = 0x6,	/**< Mask bit(6-14) */
-	RTC_ALARM_SS_MASK_14_7  = 0x7,	/**< Mask bit(7-14) */
-	RTC_ALARM_SS_MASK_14_8  = 0x8,	/**< Mask bit(8-14) */
-	RTC_ALARM_SS_MASK_14_9  = 0x9,	/**< Mask bit(9-14) */
-	RTC_ALARM_SS_MASK_14_10 = 0xA,	/**< Mask bit(10-14) */
-	RTC_ALARM_SS_MASK_14_11 = 0xB,	/**< Mask bit(11-14) */
-	RTC_ALARM_SS_MASK_14_12 = 0xC,	/**< Mask bit(12-14) */
-	RTC_ALARM_SS_MASK_14_13 = 0xD,	/**< Mask bit(13-14) */
-	RTC_ALARM_SS_MASK_14    = 0xE,	/**< Mask bit14 */
-	RTC_ALARM_SS_MASK_ALL   = 0x0,	/**< Mask bit(0-14) */
-} rtc_sub_second_mask_t;
-
-/**
-  * @brief Alarm select week or day */
-typedef enum {
-	RTC_SELECT_DAY  = 0x0,	/**< Alarm select day */
-	RTC_SELECT_WEEK = 0x1,	/**< Alarm select week */
-} rtc_week_day_sel_t;
-
-/**
-  * @brief Alarm structure
-  */
-typedef struct {
-	rtc_alarm_idx_t idx;		/**< Index of alarm */
-	rtc_time_t time;		/**< Time structure */
-	uint32_t mask;			/**< Alarm mask */
-	rtc_sub_second_mask_t ss_mask;	/**< Alarm sub-second mask */
-	rtc_week_day_sel_t sel;		/**< Select week or day */
-
-	union {
-		uint8_t week;		/**< Alarm select week */
-		uint8_t day;		/**< Alarm select day */
-	};
-} rtc_alarm_t;
-
-/**
-  * @brief Time stamp signel select
-  */
-typedef enum {
-	RTC_TS_SIGNAL_SEL_TAMPER0 = 0,	/**< Select tamper0 */
-	RTC_TS_SIGNAL_SEL_TAMPER1 = 1,	/**< Select tamper1 */
-} rtc_ts_signal_sel_t;
-
-/**
-  * @brief Time stamp trigger style
-  */
-typedef enum {
-	RTC_TS_RISING_EDGE  = 0,	/**< Rising edge */
-	RTC_TS_FALLING_EDGE = 1,	/**< Falling edge */
-} rtc_ts_trigger_style_t;
-
-/**
-  * @brief Index of tamper
-  */
-typedef enum {
-	RTC_TAMPER_0 = 0,	/**< Tamper0 */
-	RTC_TAMPER_1 = 1,	/**< Tamper1 */
-} rtc_tamper_idx_t;
-
-/**
-  * @brief Tamper trigger type
-  */
-typedef enum {
-	RTC_TAMPER_TRIGGER_LOW  = 0,	/**< High trigger */
-	RTC_TAMPER_TRIGGER_HIGH = 1,	/**< Low trigger */
-} rtc_tamper_trigger_t;
-
-/**
-  * @brief Tamper sampling frequency
-  */
-typedef enum {
-	RTC_TAMPER_SAMPLING_FREQ_32768 = 0,	/**< RTCCLK / 32768 */
-	RTC_TAMPER_SAMPLING_FREQ_16384 = 1,	/**< RTCCLK / 16384 */
-	RTC_TAMPER_SAMPLING_FREQ_8192  = 2,	/**< RTCCLK / 8192 */
-	RTC_TAMPER_SAMPLING_FREQ_4096  = 3,	/**< RTCCLK / 4096 */
-	RTC_TAMPER_SAMPLING_FREQ_2048  = 4,	/**< RTCCLK / 2048 */
-	RTC_TAMPER_SAMPLING_FREQ_1024  = 5,	/**< RTCCLK / 1024 */
-	RTC_TAMPER_SAMPLING_FREQ_512   = 6,	/**< RTCCLK / 512 */
-	RTC_TAMPER_SAMPLING_FREQ_256   = 7,	/**< RTCCLK / 256 */
-} rtc_tamper_sampling_freq_t;
-
-/**
-  * @brief Tamper filter time
-  */
-typedef enum {
-	RTC_TAMPER_DURATION_1 = 0,	/**< Duration 1 sampling */
-	RTC_TAMPER_DURATION_2 = 1,	/**< Duration 2 sampling */
-	RTC_TAMPER_DURATION_4 = 2,	/**< Duration 4 sampling */
-	RTC_TAMPER_DURATION_8 = 3,	/**< Duration 8 sampling */
-} rtc_tamper_duration_t;
-
-/**
-  * @brief Tamper structure
-  */
-typedef struct {
-	rtc_tamper_idx_t idx;			/**< Index of tamper */
-	rtc_tamper_trigger_t trig;		/**< Trigger type */
-	rtc_tamper_sampling_freq_t freq;	/**< Sampling frequency */
-	rtc_tamper_duration_t dur;		/**< Filter time */
-	type_func_t ts;				/**< Enable/Disable trigger time stamp event */
-} rtc_tamper_t;
-
-/**
-  * @brief Wake-up clock
-  */
-typedef enum {
-	RTC_WAKEUP_CLOCK_DIV_16   = 0,	/**< RTCCLK / 16 */
-	RTC_WAKEUP_CLOCK_DIV_8    = 1,	/**< RTCCLK / 8 */
-	RTC_WAKEUP_CLOCK_DIV_4    = 2,	/**< RTCCLK / 4 */
-	RTC_WAKEUP_CLOCK_DIV_2    = 3,	/**< RTCCLK / 2 */
-	RTC_WAKEUP_CLOCK_1HZ      = 4,	/**< 1Hz */
-	RTC_WAKEUP_CLOCK_1HZ_PULS = 6,	/**< 1Hz and WUT + 65536 */
-} rtc_wakeup_clock_t;
-
-/**
-  * @brief RTC clock output type
-  */
-typedef enum {
-	RTC_CLOCK_OUTPUT_32768 = 0,	/**< 32768Hz */
-	RTC_CLOCK_OUTPUT_1024  = 1,	/**< 1024Hz */
-	RTC_CLOCK_OUTPUT_32    = 2,	/**< 32Hz */
-	RTC_CLOCK_OUTPUT_1     = 3,	/**< 1Hz */
-	RTC_CLOCK_OUTPUT_CAL_1 = 4,	/**< 1Hz after calibration */
-	RTC_CLOCK_OUTPUT_EXA_1 = 5,	/**< Exact 1Hz */
-} rtc_clock_output_t;
-
-/**
-  * @ Calibration frequency
-  */
-typedef enum {
-	RTC_CALI_FREQ_10_SEC = 0,	/**< Calibrate every 10 seconds */
-	RTC_CALI_FREQ_20_SEC = 1,	/**< Calibrate every 20 seconds */
-	RTC_CALI_FREQ_1_MIN  = 2,	/**< Calibrate every 1 minute */
-	RTC_CALI_FREQ_2_MIN  = 3,	/**< Calibrate every 2 minutes */
-	RTC_CALI_FREQ_5_MIN  = 4,	/**< Calibrate every 5 minutes */
-	RTC_CALI_FREQ_10_MIN = 5,	/**< Calibrate every 10 minutes */
-	RTC_CALI_FREQ_20_MIN = 6,	/**< Calibrate every 20 minutes */
-	RTC_CALI_FREQ_1_SEC  = 7,	/**< Calibrate every 1 second */
-} rtc_cali_freq_t;
-
-/**
-  * @brief Temperature compensate type
-  */
-typedef enum {
-	RTC_CALI_TC_NONE          = 0,	/**< Temperature compensate disable */
-	RTC_CALI_TC_AUTO_BY_HW    = 1,	/**< Temperature compensate by hardware */
-	RTC_CALI_TC_AUTO_BY_SF    = 2,	/**< Temperature compensate by software */
-	RTC_CALI_TC_AUTO_BY_HW_SF = 3,	/**< Temperature compensate by hardware, trigger by software */
-} rtc_cali_tc_t;
-
-/**
-  * @ Calculate frequency
-  */
-typedef enum {
-	RTC_CALI_CALC_FREQ_10_SEC = 0,	/**< Calculate every 10 seconds */
-	RTC_CALI_CALC_FREQ_20_SEC = 1,	/**< Calculate every 20 seconds */
-	RTC_CALI_CALC_FREQ_1_MIN  = 2,	/**< Calculate every 1 minute */
-	RTC_CALI_CALC_FREQ_2_MIN  = 3,	/**< Calculate every 2 minutes */
-	RTC_CALI_CALC_FREQ_5_MIN  = 4,	/**< Calculate every 5 minutes */
-	RTC_CALI_CALC_FREQ_10_MIN = 5,	/**< Calculate every 10 minutes */
-	RTC_CALI_CALC_FREQ_20_MIN = 6,	/**< Calculate every 20 minutes */
-	RTC_CALI_CALC_FREQ_1_HOUR = 7,	/**< Calculate every 1 hour */
-} rtc_cali_calc_freq_t;
-
-/**
-  * @brief Calibration algorithm
-  */
-typedef enum {
-	RTC_CALI_CALC_4 = 0,	/**< 4-polynomial */
-	RTC_CALI_CALC_2 = 1,	/**< 2-parabola */
-} rtc_cali_calc_t;
-
-/**
-  * @brief Calibration structure
-  */
-typedef struct {
-	rtc_cali_freq_t cali_freq;	/**< calibrate frequency */
-	rtc_cali_tc_t tc;		/**< Temperature compensate type */
-	rtc_cali_calc_freq_t calc_freq;	/**< Calculate frequency */
-	rtc_cali_calc_t calc;		/**< algorithm */
-	type_func_t acc;		/**< Enable/Disable decimal accumulate */
-} rtc_cali_t;
-
-/**
-  * @brief Interrupt type
-  */
-typedef enum {
-	RTC_IT_SEC  = (1U << 0),	/**< Second */
-	RTC_IT_MIN  = (1U << 1),	/**< Minute */
-	RTC_IT_HR   = (1U << 2),	/**< Hour */
-	RTC_IT_DAY  = (1U << 3),	/**< Day */
-	RTC_IT_MON  = (1U << 4),	/**< Month */
-	RTC_IT_YR   = (1U << 5),	/**< Year */
-	RTC_IT_ALMA = (1U << 8),	/**< Alarm-A */
-	RTC_IT_ALMB = (1U << 9),	/**< Alarm-B */
-	RTC_IT_TS   = (1U << 10),	/**< Time stamp */
-	RTC_IT_TSOV = (1U << 11),	/**< Time stamp overflow */
-	RTC_IT_TP0  = (1U << 12),	/**< Tamper-0 */
-	RTC_IT_TP1  = (1U << 13),	/**< Tamper-1 */
-	RTC_IT_RSC  = (1U << 16),	/**< Synchronous complete */
-	RTC_IT_SFC  = (1U << 17),	/**< Shift complete */
-	RTC_IT_WU   = (1U << 18),	/**< Wake-up */
-	RTC_IT_TCC  = (1U << 24),	/**< Temperature compensate complete */
-	RTC_IT_TCE  = (1U << 25),	/**< Temperature compensate error */
-} rtc_it_t;
-
-/**
-  * @brief Interrupt flag
-  */
-typedef enum {
-	RTC_IF_SEC  = (1U << 0),	/**< Second */
-	RTC_IF_MIN  = (1U << 1),	/**< Minute */
-	RTC_IF_HR   = (1U << 2),	/**< Hour */
-	RTC_IF_DAY  = (1U << 3),	/**< Day */
-	RTC_IF_MON  = (1U << 4),	/**< Month */
-	RTC_IF_YR   = (1U << 5),	/**< Year */
-	RTC_IF_ALMA = (1U << 8),	/**< Alarm-A */
-	RTC_IF_ALMB = (1U << 9),	/**< Alarm-B */
-	RTC_IF_TS   = (1U << 10),	/**< Time stamp */
-	RTC_IF_TSOV = (1U << 11),	/**< Time stamp overflow */
-	RTC_IF_TP0  = (1U << 12),	/**< Tamper-0 */
-	RTC_IF_TP1  = (1U << 13),	/**< Tamper-1 */
-	RTC_IF_RSC  = (1U << 16),	/**< Synchronous complete */
-	RTC_IF_SFC  = (1U << 17),	/**< Shift complete */
-	RTC_IF_WU   = (1U << 18),	/**< Wake-up */
-	RTC_IF_TCC  = (1U << 24),	/**< Temperature compensate complete */
-	RTC_IF_TCE  = (1U << 25),	/**< Temperature compensate error */
-} rtc_flag_t;
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Public_Macro RTC Public Macros
-  * @{
-  */
-#define RTC_UNLOCK()		(WRITE_REG(RTC->WPR, 0x55AAAA55))
-#define RTC_LOCK()		(WRITE_REG(RTC->WPR, 0x0))
-#define RTC_BY_PASS_ENABLE()			\
-do {						\
-	RTC_UNLOCK();				\
-	SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK);	\
-	RTC_LOCK();				\
-} while (0)
-#define RTC_BY_PASS_DISABLE()			\
-do {						\
-	RTC_UNLOCK();				\
-	CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK);	\
-	RTC_LOCK();				\
-} while (0)
-#define RTC_SUMMER_TIME_ENABLE()		\
-do {						\
-	RTC_UNLOCK();				\
-	SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK);	\
-	RTC_LOCK();				\
-} while (0)
-#define RTC_SUMMER_TIME_DISABLE()		\
-do {						\
-	RTC_UNLOCK();				\
-	CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK);	\
-	RTC_LOCK();				\
-} while (0)
-#define RTC_WINTER_TIME_ENABLE()		\
-do {						\
-	RTC_UNLOCK();				\
-	SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK);	\
-	RTC_LOCK();				\
-} while (0)
-#define RTC_WINTER_TIME_DISABLE()		\
-do {						\
-	RTC_UNLOCK();				\
-	CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK);	\
-	RTC_LOCK();				\
-} while (0)
-/**
- * @}
- */
-
-/** @defgroup CAN_Private_Macros CAN Private Macros
-  * @{
-  */
-#define RTC_CALI_UNLOCK()	(WRITE_REG(RTC->CALWPR, 0x699655AA))
-#define RTC_CALI_LOCK()		(WRITE_REG(RTC->CALWPR, 0x0))
-#define ALARM_MASK_ALL		0x40808080
-#define RTC_TIMEOUT_VALUE	100
-
-#define IS_SHIFT_SUB_SS(x)	((x) < (1U << 15))
-#define IS_RTC_HOUR_FORMAT(x)	(((x) == RTC_HOUR_FORMAT_24) || \
-                                 ((x) == RTC_HOUR_FORMAT_12))
-#define IS_RTC_OUTPUT_SEL(x)	(((x) == RTC_OUTPUT_DISABLE) || \
-                                 ((x) == RTC_OUTPUT_ALARM_A) || \
-                                 ((x) == RTC_OUTPUT_ALARM_B) || \
-                                 ((x) == RTC_OUTPUT_WAKEUP))
-#define IS_RTC_OUTPUT_POLARITY(x)	(((x) == RTC_OUTPUT_POLARITY_HIGH) || \
-                                         ((x) == RTC_OUTPUT_POLARITY_LOW))
-#define IS_RTC_SOURCE_SEL(x)	(((x) == RTC_SOURCE_LOSC)        || \
-                                 ((x) == RTC_SOURCE_LRC)         || \
-                                 ((x) == RTC_SOURCE_HRC_DIV_1M ) || \
-                                 ((x) == RTC_SOURCE_HOSC_DIV_1M))
-#define IS_RTC_ALARM(x)		(((x) == RTC_ALARM_A) || \
-                                 ((x) == RTC_ALARM_B))
-#define IS_RTC_ALARM_SEL(x)	(((x) == RTC_SELECT_DAY) || \
-                                 ((x) == RTC_SELECT_WEEK))
-#define IS_RTC_ALARM_MASK(x)	(((x) == RTC_ALARM_MASK_NONE)     || \
-                                 ((x) == RTC_ALARM_MASK_WEEK_DAY) || \
-                                 ((x) == RTC_ALARM_MASK_HOUR)     || \
-                                 ((x) == RTC_ALARM_MASK_MINUTE)   || \
-                                 ((x) == RTC_ALARM_MASK_SECOND)   || \
-                                 ((x) == RTC_ALARM_MASK_ALL))
-#define IS_RTC_ALARM_SS_MASK(x)	(((x) == RTC_ALARM_SS_MASK_NONE)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_1)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_2)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_3)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_4)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_5)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_6)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_7)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_8)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_9)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_10) || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_11) || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_12) || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_13) || \
-                                 ((x) == RTC_ALARM_SS_MASK_14)    || \
-                                 ((x) == RTC_ALARM_SS_MASK_ALL))
-#define IS_RTC_TS_SIGNAL(x)	(((x) == RTC_TS_SIGNAL_SEL_TAMPER0) || \
-                                 ((x) == RTC_TS_SIGNAL_SEL_TAMPER1))
-#define IS_RTC_TS_STYLE(x)	(((x) == RTC_TS_RISING_EDGE) || \
-                                 ((x) == RTC_TS_FALLING_EDGE))
-#define IS_RTC_FORMAT(x)	(((x) == RTC_FORMAT_DEC) || \
-                                 ((x) == RTC_FORMAT_BCD))
-#define IS_RTC_TAMPER(x)	(((x) == RTC_TAMPER_0) || \
-                                 ((x) == RTC_TAMPER_1))
-#define IS_RTC_TAMPER_TRIGGER(x)	(((x) == RTC_TAMPER_TRIGGER_LOW) || \
-                                         ((x) == RTC_TAMPER_TRIGGER_HIGH))
-#define IS_RTC_TAMPER_SAMPLING_FREQ(x)	(((x) == RTC_TAMPER_SAMPLING_FREQ_32768) || \
-                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \
-                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_8192)  || \
-                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_4096)  || \
-                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_2048)  || \
-                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_1024)  || \
-                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_512)   || \
-                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_256))
-#define IS_RTC_TAMPER_DURATION(x)	(((x) == RTC_TAMPER_DURATION_1) || \
-                                         ((x) == RTC_TAMPER_DURATION_2) || \
-                                         ((x) == RTC_TAMPER_DURATION_4) || \
-                                         ((x) == RTC_TAMPER_DURATION_8))
-#define IS_RTC_WAKEUP_CLOCK(x)	(((x) == RTC_WAKEUP_CLOCK_DIV_16) || \
-                                 ((x) == RTC_WAKEUP_CLOCK_DIV_8)  || \
-                                 ((x) == RTC_WAKEUP_CLOCK_DIV_4)  || \
-                                 ((x) == RTC_WAKEUP_CLOCK_DIV_2)  || \
-                                 ((x) == RTC_WAKEUP_CLOCK_1HZ)    || \
-                                 ((x) == RTC_WAKEUP_CLOCK_1HZ_PULS))
-#define IS_RTC_CLOCK_OUTPUT(x)	(((x) == RTC_CLOCK_OUTPUT_32768) || \
-                                 ((x) == RTC_CLOCK_OUTPUT_1024)  || \
-                                 ((x) == RTC_CLOCK_OUTPUT_32)    || \
-                                 ((x) == RTC_CLOCK_OUTPUT_1)     || \
-                                 ((x) == RTC_CLOCK_OUTPUT_CAL_1) || \
-                                 ((x) == RTC_CLOCK_OUTPUT_EXA_1))
-#define IS_RTC_CALI_FREQ(x)	(((x) == RTC_CALI_FREQ_10_SEC) || \
-                                 ((x) == RTC_CALI_FREQ_20_SEC) || \
-                                 ((x) == RTC_CALI_FREQ_1_MIN)  || \
-                                 ((x) == RTC_CALI_FREQ_2_MIN)  || \
-                                 ((x) == RTC_CALI_FREQ_5_MIN)  || \
-                                 ((x) == RTC_CALI_FREQ_10_MIN) || \
-                                 ((x) == RTC_CALI_FREQ_20_MIN) || \
-                                 ((x) == RTC_CALI_FREQ_1_SEC))
-#define IS_RTC_CALI_TC(x)	(((x) == RTC_CALI_TC_NONE)       || \
-                                 ((x) == RTC_CALI_TC_AUTO_BY_HW) || \
-                                 ((x) == RTC_CALI_TC_AUTO_BY_SF) || \
-                                 ((x) == RTC_CALI_TC_AUTO_BY_HW_SF))
-#define IS_RTC_CALC_FREQ(x)	(((x) == RTC_CALI_CALC_FREQ_10_SEC) || \
-                                 ((x) == RTC_CALI_CALC_FREQ_20_SEC) || \
-                                 ((x) == RTC_CALI_CALC_FREQ_1_MIN)  || \
-                                 ((x) == RTC_CALI_CALC_FREQ_2_MIN)  || \
-                                 ((x) == RTC_CALI_CALC_FREQ_5_MIN)  || \
-                                 ((x) == RTC_CALI_CALC_FREQ_10_MIN) || \
-                                 ((x) == RTC_CALI_CALC_FREQ_20_MIN) || \
-                                 ((x) == RTC_CALI_CALC_FREQ_1_HOUR))
-#define IS_RTC_CALI_CALC(x)	(((x) == RTC_CALI_CALC_4) || \
-                                 ((x) == RTC_CALI_CALC_2))
-#define IS_RTC_IT(x)		(((x) == RTC_IT_SEC)  || \
-                                 ((x) == RTC_IT_MIN)  || \
-                                 ((x) == RTC_IT_HR)   || \
-                                 ((x) == RTC_IT_DAY)  || \
-                                 ((x) == RTC_IT_MON)  || \
-                                 ((x) == RTC_IT_YR)   || \
-                                 ((x) == RTC_IT_ALMA) || \
-                                 ((x) == RTC_IT_ALMB) || \
-                                 ((x) == RTC_IT_TS)   || \
-                                 ((x) == RTC_IT_TSOV) || \
-                                 ((x) == RTC_IT_TP0)  || \
-                                 ((x) == RTC_IT_TP1)  || \
-                                 ((x) == RTC_IT_RSC)  || \
-                                 ((x) == RTC_IT_SFC)  || \
-                                 ((x) == RTC_IT_WU)   || \
-                                 ((x) == RTC_IT_TCC)  || \
-                                 ((x) == RTC_IT_TCE))
-#define IS_RTC_IF(x)		(((x) == RTC_IF_SEC)  || \
-                                 ((x) == RTC_IF_MIN)  || \
-                                 ((x) == RTC_IF_HR)   || \
-                                 ((x) == RTC_IF_DAY)  || \
-                                 ((x) == RTC_IF_MON)  || \
-                                 ((x) == RTC_IF_YR)   || \
-                                 ((x) == RTC_IF_ALMA) || \
-                                 ((x) == RTC_IF_ALMB) || \
-                                 ((x) == RTC_IF_TS)   || \
-                                 ((x) == RTC_IF_TSOV) || \
-                                 ((x) == RTC_IF_TP0)  || \
-                                 ((x) == RTC_IF_TP1)  || \
-                                 ((x) == RTC_IF_RSC)  || \
-                                 ((x) == RTC_IF_SFC)  || \
-                                 ((x) == RTC_IF_WU)   || \
-                                 ((x) == RTC_IF_TCC)  || \
-                                 ((x) == RTC_IF_TCE))
-#define IS_RTC_SECOND(x)	((x) < 60)
-#define IS_RTC_MINUTE(x)	((x) < 60)
-#define IS_RTC_HOUR(x)		((x) < 24)
-#define IS_RTC_DAY(x)		(((x) > 0) && ((x) < 32))
-#define IS_RTC_MONTH(x)		(((x) > 0) && ((x) < 13))
-#define IS_RTC_YEAR(x)		((x) < 100)
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Public_Functions
-  * @{
-  */
-
-/** @addtogroup RTC_Public_Functions_Group1
-  *  @{
-  */
-/* Initialization functions */
-void rtc_reset(void);
-void rtc_init(rtc_init_t *init);
-void rtc_source_selcet(rtc_source_sel_t sel);
-/**
-  * @}
-  */
-/** @addtogroup RTC_Public_Functions_Group2
-  * @{
-  */
-/* Time and date operation functions */
-ald_status_t rtc_set_time(rtc_time_t *time, rtc_format_t format);
-ald_status_t rtc_set_date(rtc_date_t *date, rtc_format_t format);
-void rtc_get_time(rtc_time_t *time, rtc_format_t format);
-void rtc_get_date(rtc_date_t *date, rtc_format_t format);
-int32_t rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format);
-/**
-  * @}
-  */
-/** @addtogroup RTC_Public_Functions_Group3
-  * @{
-  */
-/* Alarm functions */
-void rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format);
-void rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format);
-/**
-  * @}
-  */
-/** @addtogroup RTC_Public_Functions_Group4
-  * @{
-  */
-/* Time stamp functions */
-void rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style);
-void rtc_cancel_time_stamp(void);
-void rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format);
-/**
-  * @}
-  */
-/** @addtogroup RTC_Public_Functions_Group5
-  * @{
-  */
-/* Tamper functions */
-void rtc_set_tamper(rtc_tamper_t *tamper);
-void rtc_cancel_tamper(rtc_tamper_idx_t idx);
-/**
-  * @}
-  */
-/** @addtogroup RTC_Public_Functions_Group6
-  * @{
-  */
-/* Wakeup functions */
-void rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value);
-void rtc_cancel_wakeup(void);
-uint16_t rtc_get_wakeup_timer_value(void);
-/**
-  * @}
-  */
-/** @addtogroup RTC_Public_Functions_Group7
-  * @{
-  */
-/* Clock output functions */
-ald_status_t rtc_set_clock_output(rtc_clock_output_t clock);
-void rtc_cancel_clock_output(void);
-/**
-  * @}
-  */
-/** @addtogroup RTC_Public_Functions_Group8
-  * @{
-  */
-/* Control functions */
-void rtc_interrupt_config(rtc_it_t it, type_func_t state);
-void rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state);
-ald_status_t rtc_set_shift(type_func_t add_1s, uint16_t sub_ss);
-void rtc_set_cali(rtc_cali_t *config);
-void rtc_cancel_cali(void);
-ald_status_t rtc_get_cali_status(void);
-void rtc_write_temp(uint16_t temp);
-it_status_t rtc_get_it_status(rtc_it_t it);
-flag_status_t rtc_get_flag_status(rtc_flag_t flag);
-void rtc_clear_flag_status(rtc_flag_t flag);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-#endif

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_smartcard.h

@@ -1,274 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_usart.h
-  * @brief   Header file of SMARTCARD driver module.
-  *
-  * @version V1.0
-  * @date    25 Apr 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#ifndef __ALD_SMARTCARD_H__
-#define __ALD_SMARTCARD_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-#include "ald_usart.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup SMARTCARD
-  * @{
-  */
-
-/** @defgroup SMARTCARD_Public_Constants  SMARTCARD Public constants
-  * @{
-  */
-
-/**
-  * @brief SMARTCARD error codes
-  */
-typedef enum {
-	SMARTCARD_ERROR_NONE = ((uint32_t)0x00),	/**< No error */
-	SMARTCARD_ERROR_PE   = ((uint32_t)0x01),	/**< Parity error */
-	SMARTCARD_ERROR_NE   = ((uint32_t)0x02),	/**< Noise error */
-	SMARTCARD_ERROR_FE   = ((uint32_t)0x04),	/**< frame error */
-	SMARTCARD_ERROR_ORE  = ((uint32_t)0x08),	/**< Overrun error */
-	SMARTCARD_ERROR_DMA  = ((uint32_t)0x10),	/**< DMA transfer error */
-} smartcard_error_t;
-
-/**
-  * @brief SMARTCARD Prescaler
-  */
-typedef enum {
-	SMARTCARD_PRESCALER_SYSCLK_DIV2  = ((uint32_t)0x1),	/**< SYSCLK divided by 2 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV4  = ((uint32_t)0x2),	/**< SYSCLK divided by 4 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV6  = ((uint32_t)0x3),	/**< SYSCLK divided by 6 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV8  = ((uint32_t)0x4),	/**< SYSCLK divided by 8 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5),	/**< SYSCLK divided by 10 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6),	/**< SYSCLK divided by 12 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7),	/**< SYSCLK divided by 14 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8),	/**< SYSCLK divided by 16 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9),	/**< SYSCLK divided by 18 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xA),	/**< SYSCLK divided by 20 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xB),	/**< SYSCLK divided by 22 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xC),	/**< SYSCLK divided by 24 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xD),	/**< SYSCLK divided by 26 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xE),	/**< SYSCLK divided by 28 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xF),	/**< SYSCLK divided by 30 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10),	/**< SYSCLK divided by 32 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11),	/**< SYSCLK divided by 34 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12),	/**< SYSCLK divided by 36 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13),	/**< SYSCLK divided by 38 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14),	/**< SYSCLK divided by 40 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15),	/**< SYSCLK divided by 42 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16),	/**< SYSCLK divided by 44 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17),	/**< SYSCLK divided by 46 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18),	/**< SYSCLK divided by 48 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19),	/**< SYSCLK divided by 50 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1A),	/**< SYSCLK divided by 52 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1B),	/**< SYSCLK divided by 54 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1C),	/**< SYSCLK divided by 56 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1D),	/**< SYSCLK divided by 58 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1E),	/**< SYSCLK divided by 60 */
-	SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1F),	/**< SYSCLK divided by 62 */
-} smartcard_prescaler_t;
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Public_Types SMARTCARD Public Types
-  * @{
-  */
-
-/**
-  * @brief SMARTCARD Init Structure definition
-  */
-typedef struct {
-	uint32_t baud;			/**< This member configures the SmartCard communication baud rate. */
-	usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */
-	usart_stop_bits_t stop_bits;	/**< Specifies the number of stop bits transmitted. */
-	usart_parity_t parity;		/**< Specifies the parity mode.
-						@note When parity is enabled, the computed parity is inserted
-                                                      at the MSB position of the transmitted data (9th bit when
-                                                      the word length is set to 9 data bits; 8th bit when the
-                                                      word length is set to 8 data bits).*/
-	usart_mode_t mode;		/**< Specifies whether the Receive or Transmit mode is enabled or disabled. */
-	usart_cpol_t polarity;		/**< Specifies the steady state of the serial clock. */
-	usart_cpha_t phase;		/**< Specifies the clock transition on which the bit capture is made.*/
-	usart_last_bit_t last_bit;	/**< Specifies whether the clock pulse corresponding to the last transmitted
-					     data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                                             This parameter can be a value of @ref usart_last_bit_t */
-	smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock
-					     to provide the smartcard clock. The value given in the register (5 significant bits)
-					     is multiplied by 2 to give the division factor of the source clock frequency. */
-	uint32_t guard_time;		/**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
-	type_func_t nack;		/**< Specifies the SmartCard NACK Transmission state. */
-} smartcard_init_t;
-
-/**
-  * @brief ALD state structures definition
-  */
-typedef enum {
-	SMARTCARD_STATE_RESET      = 0x00,	/**< Peripheral is not yet Initialized */
-	SMARTCARD_STATE_READY      = 0x01,	/**< Peripheral Initialized and ready for use */
-	SMARTCARD_STATE_BUSY       = 0x02,	/**< an internal process is ongoing */
-	SMARTCARD_STATE_BUSY_TX    = 0x11,	/**< Data Transmission process is ongoing */
-	SMARTCARD_STATE_BUSY_RX    = 0x21,	/**< Data Reception process is ongoing */
-	SMARTCARD_STATE_BUSY_TX_RX = 0x31,	/**< Data Transmission and Reception process is ongoing */
-	SMARTCARD_STATE_TIMEOUT    = 0x03,	/**< Timeout state */
-	SMARTCARD_STATE_ERROR      = 0x04	/**< Error */
-} smartcard_state_t;
-
-
-/**
-  * @brief  SMARTCARD handle structure definition
-  */
-typedef struct smartcard_handle_s {
-	USART_TypeDef *perh;		/**< USART registers base address */
-	smartcard_init_t init;		/**< SmartCard communication parameters */
-	uint8_t *tx_buf;		/**< Pointer to SmartCard Tx transfer Buffer */
-	uint16_t tx_size;		/**< SmartCard Tx Transfer size */
-	uint16_t tx_count;		/**< SmartCard Tx Transfer Counter */
-	uint8_t *rx_buf;		/**< Pointer to SmartCard Rx transfer Buffer */
-	uint16_t rx_size;		/**< SmartCard Rx Transfer size */
-	uint16_t rx_count;		/**< SmartCard Rx Transfer Counter */
-#ifdef ALD_DMA
-	dma_handle_t hdmatx;		/**< SmartCard Tx DMA Handle parameters */
-	dma_handle_t hdmarx;		/**< SmartCard Rx DMA Handle parameters */
-#endif
-	lock_state_t lock;		/**< Locking object */
-	smartcard_state_t state;	/**< SmartCard communication state */
-	uint32_t  err_code;		/**< SmartCard Error code */
-
-	void (*tx_cplt_cbk)(struct smartcard_handle_s *arg);	/**< Tx completed callback */
-	void (*rx_cplt_cbk)(struct smartcard_handle_s *arg);	/**< Rx completed callback */
-	void (*error_cbk)(struct smartcard_handle_s *arg);	/**< error callback */
-} smartcard_handle_t;
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Public_Macros SMARTCARD Public Macros
-  * @{
-  */
-
-/** @defgroup SMARTCARD_Public_Macros_1 SMARTCARD handle reset
-  * @{
-  */
-#define SMARTCARD_RESET_HANDLE_STATE(handle) ((handle)->state = SMARTCARD_STATE_RESET)
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Public_Macros_2 SMARTCARD flush data
-  * @{
-  */
-#define SMARTCARD_FLUSH_DRREGISTER(handle) ((handle)->perh->DATA)
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Public_Macros_3 SMARTCARD enable
-  * @{
-  */
-#define SMARTCARD_ENABLE(handle)	(SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Public_Macros_4 SMARTCARD disable
-  * @{
-  */
-#define SMARTCARD_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
-  * @{
-  */
-
-#define IS_SMARTCARD_PRESCALER(x)   (((x) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \
-				     ((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62))
-/**
-  * @}
-  */
-
-/** @addtogroup SMARTCARD_Public_Functions
-  * @{
-  */
-
-/** @addtogroup SMARTCARD_Public_Functions_Group1
-  * @{
-  */
-/* Initialization functions */
-ald_status_t smartcard_init(smartcard_handle_t *hperh);
-ald_status_t smartcard_reset(smartcard_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup SMARTCARD_Public_Functions_Group2
-  * @{
-  */
-/* IO operation functions */
-ald_status_t smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size);
-ald_status_t smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size);
-#ifdef ALD_DMA
-ald_status_t smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-#endif
-void smartcard_irq_handle(smartcard_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup SMARTCARD_Public_Functions_Group3
-  * @{
-  */
-/* Peripheral State and Errors functions functions */
-smartcard_state_t smartcard_get_state(smartcard_handle_t *hperh);
-uint32_t smartcard_get_error(smartcard_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_SMARTCARD_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_spi.h

@@ -1,362 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_spi.c
-  * @brief   Header file of SPI module driver.
-  *
-  * @version V1.0
-  * @date    13 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#ifndef __ALD_SPI_H__
-#define __ALD_SPI_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup SPI
-  * @{
-  */
-
-/** @defgroup SPI_Public_Types SPI Public Types
-  * @{
-  */
-
-/**
-  * @brief clock phase
-  */
-typedef enum {
-	SPI_CPHA_FIRST  = 0,	/**< Transiting data in the first edge */
-	SPI_CPHA_SECOND = 1,	/**< Transiting data in the seconde edge */
-} spi_cpha_t;
-
-/**
-  * @brief clock polarity
-  */
-typedef enum {
-	SPI_CPOL_LOW  = 0,	/**< Polarity hold low when spi-bus is idle */
-	SPI_CPOL_HIGH = 1,	/**< Polarity hold high when spi-bus is idle */
-} spi_cpol_t;
-
-/**
-  * @brief master selection
-  */
-typedef enum {
-	SPI_MODE_SLAVER = 0,	/**< Slave mode */
-	SPI_MODE_MASTER = 1,	/**< Master mode */
-} spi_mode_t;
-
-/**
-  * @brief baud rate control
-  */
-typedef enum {
-	SPI_BAUD_2   = 0,	/**< fpclk/2 */
-	SPI_BAUD_4   = 1,	/**< fpclk/4 */
-	SPI_BAUD_8   = 2,	/**< fpclk/8 */
-	SPI_BAUD_16  = 3,	/**< fpclk/16 */
-	SPI_BAUD_32  = 4,	/**< fpclk/32 */
-	SPI_BAUD_64  = 5,	/**< fpclk/64 */
-	SPI_BAUD_128 = 6,	/**< fpclk/128 */
-	SPI_BAUD_256 = 7,	/**< fpclk/256 */
-} spi_baud_t;
-
-/**
-  * @brief frame format
-  */
-typedef enum {
-	SPI_FIRSTBIT_MSB = 0,	/**< MSB transmitted first */
-	SPI_FIRSTBIT_LSB = 1,	/**< LSB transmitted first */
-} spi_firstbit_t;
-
-/**
-  * @brief data frame format
-  */
-typedef enum {
-	SPI_DATA_SIZE_8  = 0,	/**< 8-bit data frame format is selected for transmission/reception */
-	SPI_DATA_SIZE_16 = 1,	/**< 16-bit data frame format is selected for transmission/reception */
-} spi_datasize_t;
-
-/**
-  * @brief interrupt control
-  */
-typedef enum {
-	SPI_IT_ERR   = (1U << 5),	/**< error interrupt */
-	SPI_IT_RXBNE = (1U << 6),	/**< rx buffer not empty interrupt */
-	SPI_IT_TXBE  = (1U << 7),	/**< tx buffer empty interrupt */
-} spi_it_t;
-
-/**
-  * @brief interrupt flag
-  */
-typedef enum {
-	SPI_IF_RXBNE  = (1U << 0),	/**< receive buffer not empty */
-	SPI_IF_TXBE   = (1U << 1),	/**< transmit buffer empty */
-	SPI_IF_CRCERR = (1U << 4),	/**< crc error flag */
-	SPI_IF_MODF   = (1U << 5),	/**< mode fault */
-	SPI_IF_OVE    = (1U << 6),	/**< overrun flag */
-	SPI_IF_BUSY   = (1U << 7),	/**< busy flag */
-} spi_flag_t;
-
-/**
-  * @brief SPI error status
-  */
-typedef enum {
-	SPI_ERROR_NONE = 0,	/**< none */
-	SPI_ERROR_MODF = 1,	/**< mode fault */
-	SPI_ERROR_CRC  = 2,	/**< crc error */
-	SPI_ERROR_OVE  = 4,	/**< overrun error */
-	SPI_ERROR_DMA  = 8,	/**< dma error  */
-	SPI_ERROR_FLAG = 0x10,	/**< interrupt flag error */
-} spi_error_t;
-
-
-
-/**
-  * @brief SPI state structures definition
-  */
-typedef enum {
-	SPI_STATE_RESET      = 0x00,	/**< Peripheral is not initialized */
-	SPI_STATE_READY      = 0x01,	/**< Peripheral Initialized and ready for use */
-	SPI_STATE_BUSY       = 0x02,	/**< an internal process is ongoing */
-	SPI_STATE_BUSY_TX    = 0x11,	/**< transmit is ongoing */
-	SPI_STATE_BUSY_RX    = 0x21,	/**< receive is ongoing */
-	SPI_STATE_BUSY_TX_RX = 0x31,	/**< transmit and receive are ongoing */
-	SPI_STATE_TIMEOUT    = 0x03,	/**< Timeout state */
-	SPI_STATE_ERROR      = 0x04,	/**< Error */
-} spi_state_t;
-
-
-/**
-  * @brief SPI direction definition
-  */
-typedef enum {
-	SPI_DIRECTION_2LINES        = 0,	/**< 2 lines */
-	SPI_DIRECTION_2LINES_RXONLY = 1,	/**< 2 lines only rx */
-	SPI_DIRECTION_1LINE         = 2,	/**< 1 line */
-	SPI_DIRECTION_1LINE_RX      = 3,	/**< 1 line only rx */
-} spi_direction_t;
-
-/**
-  * @brief SPI dma request definition
-  */
-typedef enum {
-	SPI_DMA_REQ_TX = 0,	/**< TX dma request */
-	SPI_DMA_REQ_RX = 1,	/**< RX dma request */
-} spi_dma_req_t;
-
-/**
-  * @brief SPI TXE/RXNE status definition
-  */
-typedef enum {
-	SPI_SR_TXBE       = 0,	/**< SR.TXE set */
-	SPI_SR_RXBNE      = 1,	/**< SR.RXNE set */
-	SPI_SR_TXBE_RXBNE = 2,	/**< SR.TXE and SR.RXNE set */
-} spi_sr_status_t;
-
-/**
-  * @brief SPI init structure definition
-  */
-typedef struct {
-	spi_mode_t mode;		/**< SPI mode */
-	spi_direction_t dir;		/**< SPI direction */
-	spi_datasize_t data_size;	/**< SPI data size */
-	spi_baud_t baud;			/**< SPI baudrate prescaler */
-	spi_cpha_t phase;		/**< SPI clock phase */
-	spi_cpol_t polarity;		/**< SPI clock polarity */
-	spi_firstbit_t first_bit;	/**< SPI first bit */
-	type_func_t ss_en;		/**< SPI ssm enable or disable */
-	type_func_t crc_calc;		/**< SPI crc calculation */
-	uint16_t crc_poly;		/**< SPI crc polynomial */
-} spi_init_t;
-
-/**
-  * @brief  SPI handle structure definition
-  */
-typedef struct spi_handle_s {
-	SPI_TypeDef *perh;	/**< SPI registers base address */
-	spi_init_t init;	/**< SPI communication parameters */
-	uint8_t *tx_buf;	/**< Pointer to SPI Tx transfer buffer */
-	uint16_t tx_size;	/**< SPI Tx transfer size */
-	uint16_t tx_count;	/**< SPI Tx transfer counter */
-	uint8_t *rx_buf;	/**< Pointer to SPI Rx transfer buffer */
-	uint16_t rx_size;	/**< SPI Rx Transfer size */
-	uint16_t rx_count;	/**< SPI Rx Transfer Counter */
-#ifdef ALD_DMA
-	dma_handle_t hdmatx;	/**< SPI Tx DMA handle parameters */
-	dma_handle_t hdmarx;	/**< SPI Rx DMA handle parameters */
-#endif
-	lock_state_t lock;	/**< Locking object */
-	spi_state_t state;	/**< SPI communication state */
-	uint32_t err_code;	/**< SPI error code */
-
-	void (*tx_cplt_cbk)(struct spi_handle_s *arg);		/**< Tx completed callback */
-	void (*rx_cplt_cbk)(struct spi_handle_s *arg);		/**< Rx completed callback */
-	void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg);	/**< Tx & Rx completed callback */
-	void (*err_cbk)(struct spi_handle_s *arg);		/**< error callback */
-} spi_handle_t;
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Public_Macros SPI Public Macros
-  * @{
-  */
-#define SPI_RESET_HANDLE_STATE(x)	((x)->state = SPI_STATE_RESET)
-#define SPI_ENABLE(x)			((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS))
-#define SPI_DISABLE(x)			((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS))
-#define SPI_CRC_RESET(x)					\
-do {								\
-	CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK);		\
-	SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK);		\
-} while (0)
-#define SPI_CRCNEXT_ENABLE(x)	(SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
-#define SPI_CRCNEXT_DISABLE(x)	(CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
-#define SPI_RXONLY_ENABLE(x)	(SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
-#define SPI_RXONLY_DISABLE(x)	(CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
-#define SPI_1LINE_TX(x)		(SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
-#define SPI_1LINE_RX(x)		(CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
-#define SPI_SSI_HIGH(x)		(SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
-#define SPI_SSI_LOW(x)		(CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
-#define SPI_SSOE_ENABLE(x)	(SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
-#define SPI_SSOE_DISABLE(x)	(CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Private_Macros   SPI Private Macros
-  * @{
-  */
-#define IS_SPI(x)	(((x) == SPI0) || \
-                         ((x) == SPI1) || \
-                         ((x) == SPI2))
-#define IS_SPI_CPHA(x)	(((x) == SPI_CPHA_FIRST) || \
-                         ((x) == SPI_CPHA_SECOND))
-#define IS_SPI_CPOL(x)	(((x) == SPI_CPOL_LOW) || \
-                         ((x) == SPI_CPOL_HIGH))
-#define IS_SPI_MODE(x)	(((x) == SPI_MODE_SLAVER) || \
-                         ((x) == SPI_MODE_MASTER))
-#define IS_SPI_BAUD(x)	(((x) == SPI_BAUD_2)   || \
-                         ((x) == SPI_BAUD_4)   || \
-                         ((x) == SPI_BAUD_8)   || \
-                         ((x) == SPI_BAUD_16)  || \
-                         ((x) == SPI_BAUD_32)  || \
-                         ((x) == SPI_BAUD_64)  || \
-                         ((x) == SPI_BAUD_128) || \
-                         ((x) == SPI_BAUD_256))
-#define IS_SPI_DATASIZE(x)	(((x) == SPI_DATA_SIZE_8) || \
-                                 ((x) == SPI_DATA_SIZE_16))
-#define IS_SPI_BIDOE(x)		(((x) == SPI_BID_RX) || \
-                                 ((x) == SPI_BID_TX))
-#define IS_SPI_BIDMODE(x)	(((x) == SPI_BIDMODE_DUAL) || \
-                                 ((x) == SPI_BIDMODE_SOLE))
-#define IS_SPI_DIRECTION(x)	(((x) == SPI_DIRECTION_2LINES)         || \
-                                 ((x) == SPI_DIRECTION_2LINES_RXONLY)  || \
-                                 ((x) == SPI_DIRECTION_1LINE)          || \
-				 ((x) == SPI_DIRECTION_1LINE_RX))
-#define IS_SPI_DMA_REQ(x)	(((x) == SPI_DMA_REQ_TX) || \
-                                 ((x) == SPI_DMA_REQ_RX))
-#define IS_SPI_SR_STATUS(x)	(((x) == SPI_SR_TXBE)  || \
-                                 ((x) == SPI_SR_RXBNE) || \
-                                 ((x) == SPI_SR_TXBE_RXBNE))
-#define IS_SPI_IT(x)	(((x) == SPI_IT_ERR)   || \
-                         ((x) == SPI_IT_RXBNE) || \
-                         ((x) == SPI_IT_TXBE))
-#define IS_SPI_IF(x)	(((x) == SPI_IF_RXBNE)  || \
-                         ((x) == SPI_IF_TXBE)   || \
-                         ((x) == SPI_IF_CRCERR) || \
-                         ((x) == SPI_IF_MODF)   || \
-                         ((x) == SPI_IF_OVE)    || \
-                         ((x) == SPI_IF_BUSY))
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Public_Functions
-  * @{
-  */
-
-/** @addtogroup SPI_Public_Functions_Group1
-  * @{
-  */
-
-ald_status_t spi_init(spi_handle_t *hperh);
-void spi_reset(spi_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Public_Functions_Group2
-  * @{
-  */
-int32_t spi_send_byte_fast(spi_handle_t *hperh, uint8_t data);
-uint8_t spi_recv_byte_fast(spi_handle_t *hperh);
-ald_status_t spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout);
-ald_status_t spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size);
-ald_status_t spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size);
-ald_status_t spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size);
-#ifdef ALD_DMA
-ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel);
-ald_status_t spi_dma_pause(spi_handle_t *hperh);
-ald_status_t spi_dma_resume(spi_handle_t *hperh);
-ald_status_t spi_dma_stop(spi_handle_t *hperh);
-#endif
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Public_Functions_Group3
-  * @{
-  */
-void spi_irq_handle(spi_handle_t *hperh);
-void spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state);
-void spi_speed_config(spi_handle_t *hperh, spi_baud_t speed);
-void spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state);
-it_status_t spi_get_it_status(spi_handle_t *hperh, spi_it_t it);
-flag_status_t spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag);
-void spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag);
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Public_Functions_Group4
-  * @{
-  */
-spi_state_t spi_get_state(spi_handle_t *hperh);
-uint32_t spi_get_error(spi_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-#endif

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_temp.h

@@ -1,199 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_temp.h
-  * @brief   Header file of TEMP module driver.
-  *
-  * @version V1.0
-  * @date    15 Dec 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  ********************************************************************************
-  */
-
-#ifndef __ALD_TEMP_H__
-#define __ALD_TEMP_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup TEMP
-  * @{
-  */
-
-/** @defgroup TEMP_Public_Macros TEMP Public Macros
-  * @{
-  */
-#define TEMP_LOCK()		(WRITE_REG(TEMP->WPR, 0x0))
-#define TEMP_UNLOCK()		(WRITE_REG(TEMP->WPR, 0xA55A9669))
-#define TEMP_ENABLE()				\
-do {						\
-	TEMP_UNLOCK();				\
-	SET_BIT(TEMP->CR, TEMP_CR_EN_MSK);	\
-	TEMP_LOCK();				\
-} while (0)
-#define TEMP_DISABLE()				\
-do {						\
-	TEMP_UNLOCK();				\
-	CLEAR_BIT(TEMP->CR, TEMP_CR_EN_MSK);	\
-	TEMP_LOCK();				\
-} while (0)
-#define TEMP_REQ_ENABLE()			\
-do {						\
-	TEMP_UNLOCK();				\
-	SET_BIT(TEMP->CR, TEMP_CR_REQEN_MSK);	\
-	TEMP_LOCK();				\
-} while (0)
-#define TEMP_REQ_DISABLE()			\
-do {						\
-	TEMP_UNLOCK();				\
-	CLEAR_BIT(TEMP->CR, TEMP_CR_REQEN_MSK);	\
-	TEMP_LOCK();				\
-} while (0)
-#define TEMP_CTN_ENABLE()			\
-do {						\
-	TEMP_UNLOCK();				\
-	SET_BIT(TEMP->CR, TEMP_CR_CTN_MSK);	\
-	TEMP_LOCK();				\
-} while (0)
-#define TEMP_CTN_DISABLE()			\
-do {						\
-	TEMP_UNLOCK();				\
-	CLEAR_BIT(TEMP->CR, TEMP_CR_CTN_MSK);	\
-	TEMP_LOCK();				\
-} while (0)
-#define TEMP_RESET()				\
-do {						\
-	TEMP_UNLOCK();				\
-	SET_BIT(TEMP->CR, TEMP_CR_RST_MSK);	\
-	TEMP_LOCK();				\
-} while (0)
-/**
-  * @}
-  */
-
-/** @defgroup TEMP_Public_Types TEMP Public Types
-  * @{
-  */
-/**
-  * @brief Temperature update time
-  */
-typedef enum {
-	TEMP_UPDATE_CYCLE_3 = 0x3,	/**< 3 Cycles */
-	TEMP_UPDATE_CYCLE_4 = 0x4,	/**< 4 Cycles */
-	TEMP_UPDATE_CYCLE_5 = 0x5,	/**< 5 Cycles */
-	TEMP_UPDATE_CYCLE_6 = 0x6,	/**< 6 Cycles */
-	TEMP_UPDATE_CYCLE_7 = 0x7,	/**< 7 Cycles */
-} temp_update_cycle_t;
-
-/**
-  * @brief Temperature output mode
-  */
-typedef enum {
-	TEMP_OUTPUT_MODE_200  = 0x0,	/**< 200 cycles update one temperature */
-	TEMP_OUTPUT_MODE_400  = 0x1,	/**< 400 cycles update one temperature */
-	TEMP_OUTPUT_MODE_800  = 0x2,	/**< 800 cycles update one temperature */
-	TEMP_OUTPUT_MODE_1600 = 0x3,	/**< 1600 cycles update one temperature */
-	TEMP_OUTPUT_MODE_3200 = 0x4,	/**< 3200 cycles update one temperature */
-} temp_output_mode_t;
-
-/**
-  * @brief Source select
-  */
-typedef enum {
-	TEMP_SOURCE_LOSC        = 0x0,	/**< LOSC */
-	TEMP_SOURCE_LRC         = 0x1,	/**< LRC */
-	TEMP_SOURCE_HRC_DIV_1M  = 0x2,	/**< HRC divide to 1MHz */
-	TEMP_SOURCE_HOSC_DIV_1M = 0x3,	/**< HOSC divide to 1MHz */
-} temp_source_sel_t;
-
-
-/**
-  * @brief TEMP init structure definition
-  */
-typedef struct {
-	temp_update_cycle_t cycle;	/**< Temperature update time */
-	temp_output_mode_t mode;	/**< Temperature output mode */
-	uint8_t ctn;			/**< Continue mode */
-	uint8_t psc;			/**< Perscaler */
-} temp_init_t;
-
-/**
-  * @brief Define callback function type
-  */
-typedef void (*temp_cbk)(uint16_t value, ald_status_t status);
-/**
-  * @}
-  */
-
-/**
-  * @defgroup TEMP_Private_Macros TEMP Private Macros
-  * @{
-  */
-#define IS_TEMP_UPDATE_CYCLE(x)	(((x) == TEMP_UPDATE_CYCLE_3) || \
-                                 ((x) == TEMP_UPDATE_CYCLE_4) || \
-                                 ((x) == TEMP_UPDATE_CYCLE_5) || \
-                                 ((x) == TEMP_UPDATE_CYCLE_6) || \
-                                 ((x) == TEMP_UPDATE_CYCLE_7))
-#define IS_TEMP_OUTPUT_MODE(x)	(((x) == TEMP_OUTPUT_MODE_200)  || \
-                                 ((x) == TEMP_OUTPUT_MODE_400)  || \
-                                 ((x) == TEMP_OUTPUT_MODE_800)  || \
-                                 ((x) == TEMP_OUTPUT_MODE_1600) || \
-                                 ((x) == TEMP_OUTPUT_MODE_3200))
-#define IS_TEMP_SOURCE_SEL(x)	(((x) == TEMP_SOURCE_LOSC)        || \
-                                 ((x) == TEMP_SOURCE_LRC)         || \
-                                 ((x) == TEMP_SOURCE_HRC_DIV_1M ) || \
-                                 ((x) == TEMP_SOURCE_HOSC_DIV_1M))
-/**
-  * @}
-  */
-
-/** @addtogroup TEMP_Public_Functions
-  * @{
-  */
-/** @addtogroup TEMP_Public_Functions_Group1
-  * @{
-  */
-/* Initialization functions */
-extern void temp_init(temp_init_t *init);
-extern void temp_source_selcet(temp_source_sel_t sel);
-/**
-  * @}
-  */
-/** @addtogroup TEMP_Public_Functions_Group2
-  * @{
-  */
-/* Control functions */
-extern ald_status_t temp_get_value(uint16_t *temp);
-extern void temp_get_value_by_it(temp_cbk cbk);
-void temp_irq_handle(void);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_TEMP_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_timer.h

@@ -1,1086 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_timer.h
-  * @brief   TIMER module driver.
-  *	     This is the common part of the TIMER initialization
-  *
-  * @version V1.0
-  * @date    06 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#ifndef __ALD_TIMER_H__
-#define __ALD_TIMER_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup TIMER
-  * @{
-  */
-
-/** @defgroup TIMER_Public_Types TIMER Public Types
-  * @{
-  */
-
-/**
-  * @brief TIMER counter mode
-  */
-typedef enum {
-	TIMER_CNT_MODE_UP      = 0,	/**< Counter mode up */
-	TIMER_CNT_MODE_DOWN    = 1,	/**< Counter mode down */
-	TIMER_CNT_MODE_CENTER1 = 2,	/**< Counter mode center1 */
-	TIMER_CNT_MODE_CENTER2 = 3,	/**< Counter mode center2 */
-	TIMER_CNT_MODE_CENTER3 = 4,	/**< Counter mode center3 */
-} timer_cnt_mode_t;
-
-/**
-  * @brief TIMER clock division
-  */
-typedef enum {
-	TIMER_CLOCK_DIV1 = 0,	/**< No prescaler is used */
-	TIMER_CLOCK_DIV2 = 1,	/** Clock is divided by 2 */
-	TIMER_CLOCK_DIV4 = 2,	/** Clock is divided by 4 */
-} timer_clock_division_t;
-
-/**
-  * @brief TIMER output compare and PWM modes
-  */
-typedef enum {
-	TIMER_OC_MODE_TIMERING       = 0,	/**< Output compare mode is timering */
-	TIMER_OC_MODE_ACTIVE         = 1,	/**< Output compare mode is active */
-	TIMER_OC_MODE_INACTIVE       = 2,	/**< Output compare mode is inactive */
-	TIMER_OC_MODE_TOGGLE         = 3,	/**< Output compare mode is toggle */
-	TIMER_OC_MODE_FORCE_INACTIVE = 4,	/**< Output compare mode is force inactive */
-	TIMER_OC_MODE_FORCE_ACTIVE   = 5,	/**< Output compare mode is force active */
-	TIMER_OC_MODE_PWM1           = 6,	/**< Output compare mode is pwm1 */
-	TIMER_OC_MODE_PWM2           = 7,	/**< Output compare mode is pwm2 */
-} timer_oc_mode_t;
-
-/**
-  * @brief TIMER output compare polarity
-  */
-typedef enum {
-	TIMER_OC_POLARITY_HIGH = 0,	/**< Output compare polarity is high */
-	TIMER_OC_POLARITY_LOW  = 1,	/**< Output compare polarity is low */
-} timer_oc_polarity_t;
-
-/**
-  * @brief TIMER complementary output compare polarity
-  */
-typedef enum {
-	TIMER_OCN_POLARITY_HIGH = 0,	/**< Complementary output compare polarity is high */
-	TIMER_OCN_POLARITY_LOW  = 1,	/**< Complementary output compare polarity is low */
-} timer_ocn_polarity_t;
-
-/**
-  * @brief TIMER output compare idle state
-  */
-typedef enum {
-	TIMER_OC_IDLE_RESET = 0,	/**< Output compare idle state is reset */
-	TIMER_OC_IDLE_SET   = 1,	/**< Output compare idle state is set */
-} timer_oc_idle_t;
-
-/**
-  * @brief TIMER complementary output compare idle state
-  */
-typedef enum {
-	TIMER_OCN_IDLE_RESET = 0,	/**< Complementary output compare idle state is reset */
-	TIMER_OCN_IDLE_SET   = 1,	/**< Complementary output compare idle state is set */
-} timer_ocn_idle_t;
-
-/**
-  * @brief TIMER channel
-  */
-typedef enum {
-	TIMER_CHANNEL_1   = 0,		/**< Channel 1 */
-	TIMER_CHANNEL_2   = 1,		/**< Channel 2 */
-	TIMER_CHANNEL_3   = 2,		/**< Channel 3 */
-	TIMER_CHANNEL_4   = 4,		/**< Channel 4 */
-	TIMER_CHANNEL_ALL = 0xF,	/**< All channel */
-} timer_channel_t;
-
-/**
-  * @brief TIMER one pulse mode
-  */
-typedef enum {
-	TIMER_OP_MODE_REPEAT = 0,	/**< Repetitive */
-	TIMER_OP_MODE_SINGLE = 1,	/**< single */
-} timer_op_mode_t;
-
-/**
-  * @brief TIMER one pulse output channel
-  */
-typedef enum {
-	TIMER_OP_OUTPUT_CHANNEL_1 = 0,	/**< One pulse output channal 1 */
-	TIMER_OP_OUTPUT_CHANNEL_2 = 1,	/**< One pulse output channal 2 */
-} timer_op_output_channel_t;
-
-/**
-  * @brief  TIMER time base configuration structure definition
-  */
-typedef struct {
-	uint32_t prescaler;		/**< Specifies the prescaler value used to divide the TIMER clock. */
-	timer_cnt_mode_t mode;		/**< Specifies the counter mode. */
-	uint32_t period;		/**< Specifies the period value to be loaded into ARR at the next update event. */
-	timer_clock_division_t clk_div;	/**< Specifies the clock division.*/
-	uint32_t re_cnt;		/**< Specifies the repetition counter value. */
-} timer_base_init_t;
-
-/**
-  * @brief  TIMER output compare configuration structure definition
-  */
-typedef struct {
-	timer_oc_mode_t oc_mode;		/**< Specifies the TIMER mode. */
-	uint32_t pulse;				/**< Specifies the pulse value to be loaded into the Capture Compare Register. */
-	timer_oc_polarity_t oc_polarity;	/**< Specifies the output polarity. */
-	timer_ocn_polarity_t ocn_polarity;	/**< Specifies the complementary output polarity. */
-	type_func_t oc_fast_en;			/**< Specifies the Fast mode state. */
-	timer_oc_idle_t oc_idle;		/**< Specifies the TIMER Output Compare pin state during Idle state. */
-	timer_ocn_idle_t ocn_idle;		/**< Specifies the TIMER Output Compare pin state during Idle state. */
-} timer_oc_init_t;
-
-/**
-  * @brief State structures definition
-  */
-typedef enum {
-	TIMER_STATE_RESET     = 0x00,	/**< Peripheral not yet initialized or disabled */
-	TIMER_STATE_READY     = 0x01,	/**< Peripheral Initialized and ready for use */
-	TIMER_STATE_BUSY      = 0x02,	/**< An internal process is ongoing */
-	TIMER_STATE_TIMEREOUT = 0x03,	/**< Timeout state */
-	TIMER_STATE_ERROR     = 0x04,	/**< Reception process is ongoing */
-} timer_state_t;
-
-/**
-  * @brief Active channel structures definition
-  */
-typedef enum {
-	TIMER_ACTIVE_CHANNEL_1       = 0x01,	/**< The active channel is 1 */
-	TIMER_ACTIVE_CHANNEL_2       = 0x02,	/**< The active channel is 2 */
-	TIMER_ACTIVE_CHANNEL_3       = 0x04,	/**< The active channel is 3 */
-	TIMER_ACTIVE_CHANNEL_4       = 0x08,	/**< The active channel is 4 */
-	TIMER_ACTIVE_CHANNEL_CLEARED = 0x00,	/**< All active channels cleared */
-} timer_active_channel_t;
-
-/**
-  * @brief  TIMER time base handle structure definition
-  */
-typedef struct timer_handle_s {
-	TIMER_TypeDef *perh;		/**< Register base address */
-	timer_base_init_t init;		/**< TIMER Time Base required parameters */
-	timer_active_channel_t ch;	/**< Active channel */
-	lock_state_t lock;		/**< Locking object */
-	timer_state_t state;		/**< TIMER operation state */
-
-	void (*period_elapse_cbk)(struct timer_handle_s *arg);		/**< Period elapse callback */
-	void (*delay_elapse_cbk)(struct timer_handle_s *arg);		/**< Delay_elapse callback */
-	void (*capture_cbk)(struct timer_handle_s *arg);		/**< Capture callback */
-	void (*pwm_pulse_finish_cbk)(struct timer_handle_s *arg);	/**< PWM_pulse_finish callback */
-	void (*trigger_cbk)(struct timer_handle_s *arg);		/**< Trigger callback */
-	void (*break_cbk)(struct timer_handle_s *arg);			/**< Break callback */
-	void (*com_cbk)(struct timer_handle_s *arg);			/**< commutation callback */
-	void (*error_cbk)(struct timer_handle_s *arg);			/**< Error callback */
-} timer_handle_t;
-
-
-/**
-  * @brief TIMER encoder mode
-  */
-typedef enum {
-	TIMER_ENC_MODE_TI1  = 1,	/**< encoder mode 1 */
-	TIMER_ENC_MODE_TI2  = 2,	/**< encoder mode 2 */
-	TIMER_ENC_MODE_TI12 = 3,	/**< encoder mode 3 */
-} timer_encoder_mode_t;
-
-/**
-  * @brief TIMER input capture polarity
-  */
-typedef enum {
-	TIMER_IC_POLARITY_RISE = 0,	/**< Input capture polarity rising */
-	TIMER_IC_POLARITY_FALL = 1,	/**< Input capture polarity falling */
-	TIMER_IC_POLARITY_BOTH = 3,	/**< Input capture polarity rising and falling */
-} timer_ic_polarity_t;
-
-/**
-  *@brief TIMER input capture selection
-  */
-typedef enum {
-	TIMER_IC_SEL_DIRECT   = 1,	/**< IC1 -- TI1 */
-	TIMER_IC_SEL_INDIRECT = 2,	/**< IC1 -- TI2 */
-	TIMER_IC_SEL_TRC      = 3,	/**< IC1 -- TRC */
-} timer_ic_select_t;
-
-/**
-  * @brief TIMER input capture prescaler
-  */
-typedef enum {
-	TIMER_IC_PSC_DIV1 = 0,	/**< Capture performed once every 1 events */
-	TIMER_IC_PSC_DIV2 = 1,	/**< Capture performed once every 2 events */
-	TIMER_IC_PSC_DIV4 = 2,	/**< Capture performed once every 4 events */
-	TIMER_IC_PSC_DIV8 = 3,	/**< Capture performed once every 4 events */
-} timer_ic_prescaler_t;
-
-/**
-  * @brief TIMER encoder configuration structure definition
-  */
-typedef struct {
-	timer_encoder_mode_t mode;		/**< Specifies the encoder mode */
-	timer_ic_polarity_t ic1_polarity;	/**< Specifies the active edge of the input signal */
-	timer_ic_select_t ic1_sel;		/**< Specifies the input */
-	timer_ic_prescaler_t ic1_psc;		/**< Specifies the Input Capture Prescaler */
-	uint32_t ic1_filter;			/**< Specifies the input capture filter */
-	timer_ic_polarity_t ic2_polarity;	/**< Specifies the active edge of the input signal */
-	timer_ic_select_t ic2_sel;		/**< Specifies the input */
-	timer_ic_prescaler_t ic2_psc;		/**< Specifies the Input Capture Prescaler */
-	uint32_t ic2_filter;			/**< Specifies the input capture filter */
-} timer_encoder_init_t;
-
-/**
-  * @brief  TIMER input capture configuration structure definition
-  */
-typedef struct {
-	timer_ic_polarity_t polarity;	/**< Specifies the active edge of the input signal */
-	timer_ic_select_t sel;		/**< Specifies the input */
-	timer_ic_prescaler_t psc;	/**< Specifies the Input Capture Prescaler */
-	uint32_t filter;		/**< Specifies the input capture filter */
-} timer_ic_init_t;
-
-/**
-  * @brief  TIMER one pulse mode configuration structure definition
-  */
-typedef struct {
-	timer_oc_mode_t mode;			/**< Specifies the TIMER mode */
-	uint16_t pulse;				/**< Specifies the pulse value */
-	timer_oc_polarity_t oc_polarity;	/**< Specifies the output polarity */
-	timer_ocn_polarity_t ocn_polarity;	/**< Specifies the complementary output polarity */
-	timer_oc_idle_t oc_idle;		/**< Specifies the TIMER Output Compare pin state during Idle state */
-	timer_ocn_idle_t ocn_idle;		/**< Specifies the TIMER Output Compare pin state during Idle state */
-	timer_ic_polarity_t polarity;		/**< Specifies the active edge of the input signal */
-	timer_ic_select_t sel;			/**< Specifies the input */
-	uint32_t filter;			/**< Specifies the input capture filter */
-} timer_one_pulse_init_t;
-
-/** @brief TIMER clear input source
-  */
-typedef enum {
-	TIMER_INPUT_NONE  = 0,	/**< Clear input none */
-	TIMER_INPUT_ETR   = 1,	/**< Clear input etr */
-} timer_clear_input_source_t;
-
-/** @brief TIMER clear input polarity
-  */
-typedef enum {
-	TIMER_POLARITY_NO_INV = 0,	/**< Polarity for ETRx pin */
-	TIMER_POLARITY_INV    = 1,	/**< Polarity for ETRx pin */
-} timer_clear_input_polarity_t;
-
-/** @brief TIMER clear input polarity
-  */
-typedef enum {
-	TIMER_ETR_PSC_DIV1 = 0,	/**< No prescaler is used */
-	TIMER_ETR_PSC_DIV2 = 1,	/**< ETR input source is divided by 2 */
-	TIMER_ETR_PSC_DIV4 = 2,	/**< ETR input source is divided by 4 */
-	TIMER_ETR_PSC_DIV8 = 3,	/**< ETR input source is divided by 8 */
-} timer_etr_psc_t;
-
-/**
-  * @brief  TIMER clear input configuration handle structure definition
-  */
-typedef struct {
-	type_func_t state;			/**< TIMER clear Input state */
-	timer_clear_input_source_t source;	/**< TIMER clear Input sources */
-	timer_clear_input_polarity_t polarity;	/**< TIMER Clear Input polarity */
-	timer_etr_psc_t psc;			/**< TIMER Clear Input prescaler */
-	uint32_t filter;			/**< TIMER Clear Input filter */
-} timer_clear_input_config_t;
-
-/** @brief TIMER clock source
-  */
-typedef enum {
-	TIMER_SRC_ETRMODE2 = 0,	/**< Clock source is etr mode2 */
-	TIMER_SRC_INTER    = 1,	/**< Clock source is etr internal */
-	TIMER_SRC_ITR0     = 2,	/**< Clock source is etr itr0 */
-	TIMER_SRC_ITR1     = 3,	/**< Clock source is etr itr1 */
-	TIMER_SRC_ITR2     = 4,	/**< Clock source is etr itr2 */
-	TIMER_SRC_ITR3     = 5,	/**< Clock source is etr itr3 */
-	TIMER_SRC_TI1ED    = 6,	/**< Clock source is etr ti1ed */
-	TIMER_SRC_TI1      = 7,	/**< Clock source is etr ti1 */
-	TIMER_SRC_TI2      = 8,	/**< Clock source is etr ti2 */
-	TIMER_SRC_ETRMODE1 = 9,	/**< Clock source is etr mode1 */
-} timer_clock_source_t;
-
-/** @brief TIMER clock polarity
-  */
-typedef enum {
-	TIMER_CLK_POLARITY_INV    = 1,	/**< Polarity for ETRx clock sources */
-	TIMER_CLK_POLARITY_NO_INV = 0,	/**< Polarity for ETRx clock sources */
-	TIMER_CLK_POLARITY_RISE   = 0,	/**< Polarity for TIx clock sources */
-	TIMER_CLK_POLARITY_FALL   = 1,	/**< Polarity for TIx clock sources */
-	TIMER_CLK_POLARITY_BOTH   = 3,	/**< Polarity for TIx clock sources */
-} timer_clock_polarity_t;
-
-/**
-  * @brief  TIMER clock config structure definition
-  */
-typedef struct {
-	timer_clock_source_t source;		/**< TIMER clock sources */
-	timer_clock_polarity_t polarity;	/**< TIMER clock polarity */
-	timer_etr_psc_t psc;			/**< TIMER clock prescaler */
-	uint32_t filter;			/**< TIMER clock filter */
-} timer_clock_config_t;
-
-/**
-  * @brief TIMER slave mode
-  */
-typedef enum {
-	TIMER_MODE_DISABLE   = 0,	/**< Slave mode is disable */
-	TIMER_MODE_ENC1      = 1,	/**< Slave mode is encoder1 */
-	TIMER_MODE_ENC2      = 2,	/**< Slave mode is encoder2 */
-	TIMER_MODE_ENC3      = 3,	/**< Slave mode is encoder3 */
-	TIMER_MODE_RESET     = 4,	/**< Slave mode is reset */
-	TIMER_MODE_GATED     = 5,	/**< Slave mode is gated */
-	TIMER_MODE_TRIG      = 6,	/**< Slave mode is trigger */
-	TIMER_MODE_EXTERNAL1 = 7,	/**< Slave mode is external1 */
-} timer_slave_mode_t;
-
-/**
-  * @brief TIMER ts definition
-  */
-typedef enum {
-	TIMER_TS_ITR0    = 0,	/**< ITR0 */
-	TIMER_TS_ITR1    = 1,	/**< ITR1 */
-	TIMER_TS_ITR2    = 2,	/**< ITR2 */
-	TIMER_TS_ITR3    = 3,	/**< ITR3 */
-	TIMER_TS_TI1F_ED = 4,	/**< TI1F_ED */
-	TIMER_TS_TI1FP1  = 5,	/**< TI1FP1 */
-	TIMER_TS_TI2FP2  = 6,	/**< TI2FP2 */
-	TIMER_TS_ETRF    = 7,	/**< ETRF */
-} timer_ts_t;
-
-/**
-  * @brief  TIMER slave configuration structure definition
-  */
-typedef struct {
-	timer_slave_mode_t mode;		/**< Slave mode selection */
-	timer_ts_t input;			/**< Input Trigger source */
-	timer_clock_polarity_t polarity;	/**< Input Trigger polarity */
-	timer_etr_psc_t psc;		/**< Input trigger prescaler */
-	uint32_t filter;		/**< Input trigger filter */
-} timer_slave_config_t;
-
-/**
-  * @brief  TIMER hall sensor configuretion structure definition
-  */
-typedef struct {
-	timer_ic_polarity_t polarity;	/**< Specifies the active edge of the input signal */
-	timer_ic_prescaler_t psc;		/**< Specifies the Input Capture Prescaler */
-	uint32_t filter;		/**< Specifies the input capture filter [0x0, 0xF] */
-	uint32_t delay;			/**< Specifies the pulse value to be loaded into the register [0x0, 0xFFFF] */
-} timer_hall_sensor_init_t;
-
-/**
-  * @brief TIMER lock level
-  */
-typedef enum {
-	TIMER_LOCK_LEVEL_OFF = 0,	/**< Lock off */
-	TIMER_LOCK_LEVEL_1   = 1,	/**< Lock level 1 */
-	TIMER_LOCK_LEVEL_2   = 2,	/**< Lock level 2 */
-	TIMER_LOCK_LEVEL_3   = 3,	/**< Lock level 3 */
-} timer_lock_level_t;
-
-/**
-  * @brief TIMER break polarity
-  */
-typedef enum {
-	TIMER_BREAK_POLARITY_LOW  = 0,	/**< LOW */
-	TIMER_BREAK_POLARITY_HIGH = 1,	/**< HIGH */
-} timer_break_polarity_t;
-
-/**
-  * @brief  TIMER break and dead time configuretion structure definition
-  */
-typedef struct {
-	type_func_t off_run;		/**< Enalbe/Disable off state in run mode */
-	type_func_t off_idle;		/**< Enalbe/Disable off state in idle mode */
-	timer_lock_level_t lock_level;	/**< Lock level */
-	uint32_t dead_time;		/**< Dead time, [0x0, 0xFF] */
-	type_func_t break_state;	/**< Break state */
-	timer_break_polarity_t polarity;	/**< Break input polarity */
-	type_func_t auto_out;		/**< Enalbe/Disable automatic output */
-} timer_break_dead_time_t;
-
-/**
-  * @brief  TIMER commutation event channel configuretion structure definition
-  */
-typedef struct {
-	type_func_t en;		/**< Enalbe/Disable the channel */
-	type_func_t n_en;	/**< Enalbe/Disable the complementary channel */
-	timer_oc_mode_t mode;	/**< Mode of the channel */
-} timer_channel_config_t;
-
-/**
-  * @brief  TIMER commutation event configuretion structure definition
-  */
-typedef struct {
-	timer_channel_config_t ch[3];	/**< Configure of channel */
-} timer_com_channel_config_t;
-
-/**
-  * @brief TIMER master mode selection
-  */
-typedef enum {
-	TIMER_TRGO_RESET  = 0,	/**< RESET */
-	TIMER_TRGO_ENABLE = 1,	/**< ENABLE */
-	TIMER_TRGO_UPDATE = 2,	/**< UPDATE */
-	TIMER_TRGO_OC1    = 3,	/**< OC1 */
-	TIMER_TRGO_OC1REF = 4,	/**< OC1REF */
-	TIMER_TRGO_OC2REF = 5,	/**< OC2REF */
-	TIMER_TRGO_OC3REF = 6,	/**< OC3REF */
-	TIMER_TRGO_OC4REF = 7,	/**< OC4REF */
-} timer_master_mode_sel_t;
-
-/**
-  * @brief  TIMER master configuretion structure definition
-  */
-typedef struct {
-	timer_master_mode_sel_t sel;	/**< Specifies the active edge of the input signal */
-	type_func_t master_en;		/**< Master/Slave mode selection */
-} timer_master_config_t;
-
-/**
-  * @brief Specifies the event source
-  */
-typedef enum {
-	TIMER_SRC_UPDATE = (1U << 0),	/**< Event source is update */
-	TIMER_SRC_CC1    = (1U << 1),	/**< Event source is channel1 */
-	TIMER_SRC_CC2    = (1U << 2),	/**< Event source is channel2 */
-	TIMER_SRC_CC3    = (1U << 3),	/**< Event source is channel3 */
-	TIMER_SRC_CC4    = (1U << 4),	/**< Event source is channel4 */
-	TIMER_SRC_COM    = (1U << 5),	/**< Event source is compare */
-	TIMER_SRC_TRIG   = (1U << 6),	/**< Event source is trigger */
-	TIMER_SRC_BREAK  = (1U << 7),	/**< Event source is break */
-} timer_event_source_t;
-
-/**
-  * @brief TIMER interrupt definition
-  */
-typedef enum {
-	TIMER_IT_UPDATE  = (1U << 0),	/**< Update interrupt bit */
-	TIMER_IT_CC1     = (1U << 1),	/**< Channel1 interrupt bit */
-	TIMER_IT_CC2     = (1U << 2),	/**< Channel2 interrupt bit */
-	TIMER_IT_CC3     = (1U << 3),	/**< Channel3 interrupt bit */
-	TIMER_IT_CC4     = (1U << 4),	/**< Channel4 interrupt bit */
-	TIMER_IT_COM     = (1U << 5),	/**< compare interrupt bit */
-	TIMER_IT_TRIGGER = (1U << 6),	/**< Trigger interrupt bit */
-	TIMER_IT_BREAK   = (1U << 7),	/**< Break interrupt bit */
-} timer_it_t;
-
-/**
-  * @brief TIMER DMA request
-  */
-typedef enum {
-	TIMER_DMA_UPDATE  = (1U << 8),	/**< DMA request from update */
-	TIMER_DMA_CC1     = (1U << 9),	/**< DMA request from channel1 */
-	TIMER_DMA_CC2     = (1U << 10),	/**< DMA request from channel2 */
-	TIMER_DMA_CC3     = (1U << 11),	/**< DMA request from channel3 */
-	TIMER_DMA_CC4     = (1U << 12),	/**< DMA request from channel4 */
-	TIMER_DMA_COM     = (1U << 13),	/**< DMA request from compare */
-	TIMER_DMA_TRIGGER = (1U << 14),	/**< DMA request from trigger */
-} timer_dma_req_t;
-
-/**
-  * @brief TIMER flag definition
-  */
-typedef enum {
-	TIMER_FLAG_UPDATE  = (1U << 0),	/**< Update interrupt flag */
-	TIMER_FLAG_CC1     = (1U << 1),	/**< Channel1 interrupt flag */
-	TIMER_FLAG_CC2     = (1U << 2),	/**< Channel2 interrupt flag */
-	TIMER_FLAG_CC3     = (1U << 3),	/**< Channel3 interrupt flag */
-	TIMER_FLAG_CC4     = (1U << 4),	/**< Channel4 interrupt flag */
-	TIMER_FLAG_COM     = (1U << 5),	/**< Compare interrupt flag */
-	TIMER_FLAG_TRIGGER = (1U << 6),	/**< Trigger interrupt flag */
-	TIMER_FLAG_BREAK   = (1U << 7),	/**< Break interrupt flag */
-	TIMER_FLAG_CC1OF   = (1U << 9),	/**< Channel1 override state flag */
-	TIMER_FLAG_CC2OF   = (1U << 10),	/**< Channel2 override state flag */
-	TIMER_FLAG_CC3OF   = (1U << 11),	/**< Channel3 override state flag */
-	TIMER_FLAG_CC4OF   = (1U << 12),	/**< Channel4 override state flag */
-} timer_flag_t;
-/**
-  * @}
-  */
-
-/** @defgroup TIMER_Public_Macros   TIMER Public Macros
-  * @{
-  */
-#define CCER_CCxE_MASK		((1U << 0) | (1U << 4) | (1U << 8) | (1U << 12))
-#define CCER_CCxNE_MASK		((1U << 2) | (1U << 6) | (1U << 10))
-
-/**
-  * @brief  Reset TIMER handle state
-  */
-#define TIMER_RESET_HANDLE_STATE(hperh)	((hperh)->state = TIMER_STATE_RESET)
-
-/**
-  * @brief  Enable the TIMER peripheral.
- */
-#define TIMER_ENABLE(hperh)	(SET_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK))
-
-/**
-  * @brief  Enable the TIMER main output.
-  */
-#define TIMER_MOE_ENABLE(hperh)	(SET_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK))
-
-/**
-  * @brief  Disable the TIMER peripheral.
-  */
-#define TIMER_DISABLE(hperh)                                              \
-do {                                                                    \
-	if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0)		\
-           && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0))		\
-		CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK);	\
-} while (0)
-
-/**
-  * @brief  Disable the TIMER main output.
-  * @note The Main Output Enable of a timer instance is disabled only if
-  *       all the CCx and CCxN channels have been disabled
-  */
-#define TIMER_MOE_DISABLE(hperh)						\
-do {                                                                    \
-	if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0)		\
-           && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0))		\
-		CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK);	\
-} while (0)
-
-/**
-  * @brief  Sets the TIMER autoreload register value on runtime without calling
-  *         another time any Init function.
-  */
-#define TIMER_SET_AUTORELOAD(handle, AUTORELOAD)	\
-do {						\
-	(handle)->perh->AR    = (AUTORELOAD);	\
-	(handle)->init.period = (AUTORELOAD);	\
-} while (0)
-
-/**
-  * @brief  Gets the TIMER autoreload register value on runtime
-  */
-#define TIMER_GET_AUTORELOAD(handle)	((handle)->perh->AR)
-
-/**
-  * @brief  Gets the TIMER count register value on runtime
-  */
-#define TIMER_GET_CNT(handle)	((handle)->perh->COUNT)
-
-/**
-  * @brief  Gets the TIMER count direction value on runtime
-  */
-#define TIMER_GET_DIR(handle)	(READ_BITS((handle)->perh->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS))
-
-/**
-  * @brief  CCx DMA request sent when CCx event occurs
-  */
-#define TIMER_CCx_DMA_REQ_CCx(handle)	(CLEAR_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK))
-
-/**
-  * @brief  CCx DMA request sent when update event occurs
-  */
-#define TIMER_CCx_DMA_REQ_UPDATE(handle)	(SET_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK))
-
-/**
-  * @brief  Enable channel
-  * @param  handle: TIMER handle
-  * @param  ch: Must be one of this:
-  *           TIMER_CHANNEL_1
-  *           TIMER_CHANNEL_2
-  *           TIMER_CHANNEL_3
-  *           TIMER_CHANNEL_4
-  */
-#define TIMER_CCx_ENABLE(handle, ch)	(((ch) == TIMER_CHANNEL_4) ? \
-(SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2))))))
-
-/**
-  * @brief  Disable channel
-  * @param  handle: TIMER handle
-  * @param  ch: Must be one of this:
-  *           TIMER_CHANNEL_1
-  *           TIMER_CHANNEL_2
-  *           TIMER_CHANNEL_3
-  *           TIMER_CHANNEL_4
-  */
-#define TIMER_CCx_DISABLE(handle, ch)	(((ch) == TIMER_CHANNEL_4) ? \
-(CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2))))
-
-/**
-  * @brief  Enable complementary channel
-  * @param  handle: TIMER handle
-  * @param  ch: Must be one of this:
-  *           TIMER_CHANNEL_1
-  *           TIMER_CHANNEL_2
-  *           TIMER_CHANNEL_3
-  */
-#define TIMER_CCxN_ENABLE(handle, ch)	((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2)))
-
-/**
-  * @brief  Disable complementary channel
-  * @param  handle: TIMER handle
-  * @param  ch: Must be one of this:
-  *           TIMER_CHANNEL_1
-  *           TIMER_CHANNEL_2
-  *           TIMER_CHANNEL_3
-  */
-#define TIMER_CCxN_DISABLE(handle, ch)	((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2)))
-/**
-  * @}
-  */
-
-/** @defgroup TIMER_Private_Macros TIMER Private Macros
-  * @{
-  */
-#define IS_TIMER_INSTANCE(x)	(((x) == TIMER0) || \
-                                 ((x) == TIMER1) || \
-                                 ((x) == TIMER2) || \
-                                 ((x) == TIMER3) || \
-                                 ((x) == TIMER4) || \
-                                 ((x) == TIMER5) || \
-                                 ((x) == TIMER6) || \
-                                 ((x) == TIMER7))
-#define IS_ADTIMER_INSTANCE(x)	((x) == TIMER0)
-#define IS_TIMER_XOR_INSTANCE(x)	(((x) == TIMER0) || ((x) == TIMER6))
-#define IS_TIMER_COM_EVENT_INSTANCE(x)	(((x) == TIMER0) || \
-                                         ((x) == TIMER2) || \
-                                         ((x) == TIMER3))
-#define IS_TIMER_CC2_INSTANCE(x)	(((x) == TIMER0) || \
-                                 ((x) == TIMER2) || \
-                                 ((x) == TIMER3) || \
-                                 ((x) == TIMER6))
-#define IS_TIMER_CC4_INSTANCE(x)	(((x) == TIMER0) || \
-                                 ((x) == TIMER6))
-#define IS_TIMER_BREAK_INSTANCE(x) (((x) == TIMER0) || \
-                                  ((x) == TIMER2) || \
-                                  ((x) == TIMER3))
-#define IS_TIMER_PWM_INPUT_INSTANCE(x, y)	((((x) == TIMER0)           && \
-					 (((y) == TIMER_CHANNEL_1)  || \
-					 ((y) == TIMER_CHANNEL_2))) || \
-					 (((x) == TIMER2)           && \
-					 (((y) == TIMER_CHANNEL_1)  || \
-					 ((y) == TIMER_CHANNEL_2))) || \
-					 (((x) == TIMER3)           && \
-					 (((y) == TIMER_CHANNEL_1)  || \
-					 ((y) == TIMER_CHANNEL_2))) || \
-					 (((x) == TIMER6)           && \
-					 (((y) == TIMER_CHANNEL_1)  || \
-					 ((y) == TIMER_CHANNEL_2))))
-#define IS_TIMER_CCX_INSTANCE(x, y)	((((x) == TIMER0)           && \
-					 (((y) == TIMER_CHANNEL_1)  || \
-					 ((y) == TIMER_CHANNEL_2)   || \
-					 ((y) == TIMER_CHANNEL_3)   || \
-					 ((y) == TIMER_CHANNEL_4))) || \
-					 (((x) == TIMER2)           && \
-					 (((y) == TIMER_CHANNEL_1)  || \
-					 ((y) == TIMER_CHANNEL_2))) || \
-					 (((x) == TIMER3)           && \
-					 (((y) == TIMER_CHANNEL_1)  || \
-					 ((y) == TIMER_CHANNEL_2))) || \
-					 (((x) == TIMER6)           && \
-					 (((y) == TIMER_CHANNEL_1)  || \
-					 ((y) == TIMER_CHANNEL_2)   || \
-					 ((y) == TIMER_CHANNEL_3)   || \
-					 ((y) == TIMER_CHANNEL_4))))
-#define IS_TIMER_CCXN_INSTANCE(x, y)	((((x) == TIMER0)          || \
-					 ((x) == TIMER2)           || \
-					 ((x) == TIMER3))          && \
-                                         (((y) == TIMER_CHANNEL_1) || \
-                                         ((y) == TIMER_CHANNEL_2)  || \
-                                         ((y) == TIMER_CHANNEL_3)  || \
-                                         ((y) == TIMER_CHANNEL_4)))
-#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x)	(((x) == TIMER0) || \
-                                                 ((x) == TIMER2) || \
-                                                 ((x) == TIMER3))
-#define IS_TIMER_CLOCK_DIVISION_INSTANCE(x)	IS_TIMER_CC2_INSTANCE(x)
-#define IS_TIMER_COUNTER_MODE(x)		(((x) == TIMER_CNT_MODE_UP)      || \
-                                         ((x) == TIMER_CNT_MODE_DOWN)    || \
-                                         ((x) == TIMER_CNT_MODE_CENTER1) || \
-                                         ((x) == TIMER_CNT_MODE_CENTER2) || \
-                                         ((x) == TIMER_CNT_MODE_CENTER3))
-#define IS_TIMER_CLOCK_DIVISION(x) 	(((x) == TIMER_CLOCK_DIV1) || \
-                                         ((x) == TIMER_CLOCK_DIV2) || \
-                                         ((x) == TIMER_CLOCK_DIV4))
-#define IS_TIMER_PWM_MODE(x)		(((x) == TIMER_OC_MODE_PWM1) || \
-                                         ((x) == TIMER_OC_MODE_PWM2))
-#define IS_TIMER_OC_MODE(x) 		(((x) == TIMER_OC_MODE_TIMERING)         || \
-                                         ((x) == TIMER_OC_MODE_ACTIVE)         || \
-                                         ((x) == TIMER_OC_MODE_INACTIVE)       || \
-                                         ((x) == TIMER_OC_MODE_TOGGLE)         || \
-                                         ((x) == TIMER_OC_MODE_FORCE_ACTIVE)   || \
-                                         ((x) == TIMER_OC_MODE_FORCE_INACTIVE) || \
-                                         ((x) == TIMER_OC_MODE_PWM1) || \
-                                         ((x) == TIMER_OC_MODE_PWM2))
-#define IS_TIMER_OC_POLARITY(x) 		(((x) == TIMER_OC_POLARITY_HIGH) || \
-                                         ((x) == TIMER_OC_POLARITY_LOW))
-#define IS_TIMER_OCN_POLARITY(x) 		(((x) == TIMER_OCN_POLARITY_HIGH) || \
-                                         ((x) == TIMER_OCN_POLARITY_LOW))
-#define IS_TIMER_OCIDLE_STATE(x) 		(((x) == TIMER_OC_IDLE_RESET) || \
-                                         ((x) == TIMER_OC_IDLE_SET))
-#define IS_TIMER_OCNIDLE_STATE(x) 	(((x) == TIMER_OCN_IDLE_RESET) || \
-                                         ((x) == TIMER_OCN_IDLE_SET))
-#define IS_TIMER_CHANNELS(x)		(((x) == TIMER_CHANNEL_1) || \
-                                         ((x) == TIMER_CHANNEL_2) || \
-                                         ((x) == TIMER_CHANNEL_3) || \
-                                         ((x) == TIMER_CHANNEL_4) || \
-                                         ((x) == TIMER_CHANNEL_ALL))
-#define IS_TIMER_OP_MODE(x) 		(((x) == TIMER_OP_MODE_REPEAT) || \
-                                         ((x) == TIMER_OP_MODE_SINGLE))
-#define IS_TIMER_OP_OUTPUT_CH(x) 		(((x) == TIMER_OP_OUTPUT_CHANNEL_1) || \
-                                         ((x) == TIMER_OP_OUTPUT_CHANNEL_2))
-#define IS_TIMER_ENCODER_MODE(x) 		(((x) == TIMER_ENC_MODE_TI1) || \
-                                         ((x) == TIMER_ENC_MODE_TI2) || \
-                                         ((x) == TIMER_ENC_MODE_TI12))
-#define IS_TIMER_IC_POLARITY(x) 		(((x) == TIMER_IC_POLARITY_RISE)  || \
-                                         ((x) == TIMER_IC_POLARITY_FALL) || \
-                                         ((x) == TIMER_IC_POLARITY_BOTH))
-#define IS_TIMER_IC_SELECT(x) 		(((x) == TIMER_IC_SEL_DIRECT)   || \
-                                         ((x) == TIMER_IC_SEL_INDIRECT) || \
-                                         ((x) == TIMER_IC_SEL_TRC))
-#define IS_TIMER_IC_PSC(x) 		(((x) == TIMER_IC_PSC_DIV1) || \
-                                         ((x) == TIMER_IC_PSC_DIV2) || \
-                                         ((x) == TIMER_IC_PSC_DIV4) || \
-                                         ((x) == TIMER_IC_PSC_DIV8))
-#define IS_TIMER_IC_FILTER(x) 		((x) <= 0xF)
-#define IS_TIMER_DEAD_TIMERE(x) 		((x) <= 0xFF)
-#define IS_TIMER_CLEAR_INPUT_SOURCE(x) 	(((x) == TIMER_INPUT_NONE) || \
-                                         ((x) == TIMER_INPUT_ETR))
-#define IS_TIMER_CLEAR_INPUT_POLARITY(x) 	(((x) == TIMER_POLARITY_NO_INV) || \
-                                         ((x) == TIMER_POLARITY_INV))
-#define IS_TIMER_ETR_PSC(x) 		(((x) == TIMER_ETR_PSC_DIV1) || \
-                                         ((x) == TIMER_ETR_PSC_DIV2) || \
-                                         ((x) == TIMER_ETR_PSC_DIV4) || \
-                                         ((x) == TIMER_ETR_PSC_DIV8))
-#define IS_TIMER_CLOCK_SOURCE(x) 		(((x) == TIMER_SRC_ETRMODE2) || \
-                                         ((x) == TIMER_SRC_INTER) || \
-                                         ((x) == TIMER_SRC_ITR0)     || \
-                                         ((x) == TIMER_SRC_ITR1)     || \
-                                         ((x) == TIMER_SRC_ITR2)     || \
-                                         ((x) == TIMER_SRC_ITR3)     || \
-                                         ((x) == TIMER_SRC_TI1ED)    || \
-                                         ((x) == TIMER_SRC_TI1)      || \
-                                         ((x) == TIMER_SRC_TI2)      || \
-                                         ((x) == TIMER_SRC_ETRMODE1))
-#define IS_TIMER_CLOCK_POLARITY(x) 	(((x) == TIMER_CLK_POLARITY_INV)    || \
-                                         ((x) == TIMER_CLK_POLARITY_NO_INV) || \
-                                         ((x) == TIMER_CLK_POLARITY_RISE)      || \
-                                         ((x) == TIMER_CLK_POLARITY_FALL)     || \
-                                         ((x) == TIMER_CLK_POLARITY_BOTH))
-#define IS_TIMER_SLAVE_MODE(x)	(((x) == TIMER_MODE_DISABLE)  || \
-                                 ((x) == TIMER_MODE_ENC1) || \
-                                 ((x) == TIMER_MODE_ENC2) || \
-                                 ((x) == TIMER_MODE_ENC3) || \
-                                 ((x) == TIMER_MODE_RESET)    || \
-                                 ((x) == TIMER_MODE_GATED)    || \
-                                 ((x) == TIMER_MODE_TRIG)  || \
-                                 ((x) == TIMER_MODE_EXTERNAL1))
-#define IS_TIMER_EVENT_SOURCE(x)	(((x) == TIMER_SRC_UPDATE)  || \
-                                 ((x) == TIMER_SRC_CC1)     || \
-                                 ((x) == TIMER_SRC_CC2)     || \
-                                 ((x) == TIMER_SRC_CC3)     || \
-                                 ((x) == TIMER_SRC_CC4)     || \
-                                 ((x) == TIMER_SRC_COM)     || \
-                                 ((x) == TIMER_SRC_TRIG) || \
-                                 ((x) == TIMER_SRC_BREAK))
-#define IS_TIMER_TS(x)		(((x) == TIMER_TS_ITR0)    || \
-                                 ((x) == TIMER_TS_ITR1)    || \
-                                 ((x) == TIMER_TS_ITR2)    || \
-                                 ((x) == TIMER_TS_ITR3)    || \
-                                 ((x) == TIMER_TS_TI1F_ED) || \
-                                 ((x) == TIMER_TS_TI1FP1)  || \
-                                 ((x) == TIMER_TS_TI2FP2)  || \
-                                 ((x) == TIMER_TS_ETRF))
-#define IS_TIMER_CLOCK_LEVEL(x)	(((x) == TIMER_LOCK_LEVEL_OFF) || \
-                                 ((x) == TIMER_LOCK_LEVEL_1)   || \
-                                 ((x) == TIMER_LOCK_LEVEL_2)   || \
-                                 ((x) == TIMER_LOCK_LEVEL_3))
-#define IS_TIMER_BREAK_POLARITY(x)	(((x) == TIMER_BREAK_POLARITY_LOW) || \
-                                         ((x) == TIMER_BREAK_POLARITY_HIGH))
-#define IS_TIMER_MASTER_MODE_SEL(x)	(((x) == TIMER_TRGO_RESET)  || \
-                                         ((x) == TIMER_TRGO_ENABLE) || \
-                                         ((x) == TIMER_TRGO_UPDATE) || \
-                                         ((x) == TIMER_TRGO_OC1)    || \
-                                         ((x) == TIMER_TRGO_OC1REF) || \
-                                         ((x) == TIMER_TRGO_OC2REF) || \
-                                         ((x) == TIMER_TRGO_OC3REF) || \
-                                         ((x) == TIMER_TRGO_OC4REF))
-#define IS_TIMER_IT(x)	(((x) == TIMER_IT_UPDATE)  || \
-                         ((x) == TIMER_IT_CC1)     || \
-                         ((x) == TIMER_IT_CC2)     || \
-                         ((x) == TIMER_IT_CC3)     || \
-                         ((x) == TIMER_IT_CC4)     || \
-                         ((x) == TIMER_IT_COM)     || \
-                         ((x) == TIMER_IT_TRIGGER) || \
-                         ((x) == TIMER_IT_BREAK))
-#define IS_TIMER_DMA_REQ(x)	(((x) == TIMER_DMA_UPDATE) || \
-                                 ((x) == TIMER_DMA_CC1)    || \
-                                 ((x) == TIMER_DMA_CC2)    || \
-                                 ((x) == TIMER_DMA_CC3)    || \
-                                 ((x) == TIMER_DMA_CC4)    || \
-                                 ((x) == TIMER_DMA_COM)    || \
-                                 ((x) == TIMER_DMA_TRIGGER))
-#define IS_TIMER_FLAG(x)	(((x) == TIMER_FLAG_UPDATE)  || \
-                         ((x) == TIMER_FLAG_CC1)     || \
-                         ((x) == TIMER_FLAG_CC2)     || \
-                         ((x) == TIMER_FLAG_CC3)     || \
-                         ((x) == TIMER_FLAG_CC4)     || \
-                         ((x) == TIMER_FLAG_COM)     || \
-                         ((x) == TIMER_FLAG_TRIGGER) || \
-                         ((x) == TIMER_FLAG_BREAK)   || \
-                         ((x) == TIMER_FLAG_CC1OF)   || \
-                         ((x) == TIMER_FLAG_CC2OF)   || \
-                         ((x) == TIMER_FLAG_CC3OF)   || \
-                         ((x) == TIMER_FLAG_CC4OF))
-/**
-  * @}
-  */
-
-/** @addtogroup TIMER_Public_Functions
-  * @{
-  */
-/** @addtogroup TIMER_Public_Functions_Group1
-  * @{
-  */
-/* Time Base functions */
-ald_status_t timer_base_init(timer_handle_t *hperh);
-void timer_base_reset(timer_handle_t *hperh);
-void timer_base_start(timer_handle_t *hperh);
-void timer_base_stop(timer_handle_t *hperh);
-void timer_base_start_by_it(timer_handle_t *hperh);
-void timer_base_stop_by_it(timer_handle_t *hperh);
-#ifdef ALD_DMA
-ald_status_t timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma,
-                                  uint16_t *buf, uint32_t len, uint8_t dma_ch);
-void timer_base_stop_by_dma(timer_handle_t *hperh);
-#endif
-/**
-  * @}
-  */
-
-/** @addtogroup TIMER_Public_Functions_Group2
-  * @{
-  */
-/* Timer Output Compare functions */
-ald_status_t timer_oc_init(timer_handle_t *hperh);
-void timer_oc_start(timer_handle_t *hperh, timer_channel_t ch);
-void timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch);
-void timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
-void timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
-#ifdef ALD_DMA
-ald_status_t timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
-                      dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch);
-void timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
-#endif
-/**
-  * @}
-  */
-
-/** @addtogroup TIMER_Public_Functions_Group3
-  * @{
-  */
-/* Timer PWM functions */
-ald_status_t timer_pwm_init(timer_handle_t *hperh);
-void timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch);
-void timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch);
-void timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
-void timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
-void timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq);
-void timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty);
-void timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch);
-#ifdef ALD_DMA
-ald_status_t timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
-                      dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch);
-void timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
-#endif
-/**
-  * @}
-  */
-
-/** @addtogroup TIMER_Public_Functions_Group4
-  * @{
-  */
-/* Timer Input Capture functions */
-ald_status_t timer_ic_init(timer_handle_t *hperh);
-void timer_ic_start(timer_handle_t *hperh, timer_channel_t ch);
-void timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch);
-void timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
-void timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
-#ifdef ALD_DMA
-ald_status_t timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
-                      dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch);
-void timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
-#endif
-/**
-  * @}
-  */
-
-/** @addtogroup TIMER_Public_Functions_Group5
-  * @{
-  */
-/* Timer One Pulse functions */
-ald_status_t timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode);
-void timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch);
-void timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch);
-void timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch);
-void timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMER_Public_Functions_Group6
-  * @{
-  */
-/* Timer encoder functions */
-ald_status_t timer_encoder_init(timer_handle_t *hperh,  timer_encoder_init_t *config);
-void timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch);
-void timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch);
-void timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
-void timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
-#ifdef ALD_DMA
-ald_status_t timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
-                           dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1,
-			   uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2);
-void timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
-#endif
-/**
-  * @}
-  */
-
-/** @addtogroup TIMER_Public_Functions_Group7
-  * @{
-  */
-/* Timer hall sensor functions */
-ald_status_t timer_hall_sensor_init(timer_handle_t *hperh,  timer_hall_sensor_init_t *config);
-void timer_hall_sensor_start(timer_handle_t *hperh);
-void timer_hall_sensor_stop(timer_handle_t *hperh);
-void timer_hall_sensor_start_by_it(timer_handle_t *hperh);
-void timer_hall_sensor_stop_by_it(timer_handle_t *hperh);
-#ifdef ALD_DMA
-ald_status_t timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma,
-		                       uint16_t *buf, uint32_t len, uint8_t dma_ch);
-void timer_hall_sensor_stop_by_dma(timer_handle_t *hperh);
-#endif
-/**
-  * @}
-  */
-
-/** @addtogroup TIMER_Public_Functions_Group8
-  * @{
-  */
-/* Timer complementary output compare functions */
-void timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch);
-void timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch);
-void timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
-void timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
-#ifdef ALD_DMA
-ald_status_t timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma,
-		          timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch);
-void timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
-#endif
-/**
-  * @}
-  */
-
-/** @addtogroup TIMER_Public_Functions_Group9
-  * @{
-  */
-/* Timer complementary PWM functions */
-void timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch);
-void timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch);
-void timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
-void timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
-#ifdef ALD_DMA
-ald_status_t timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma,
-		          timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch);
-void timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
-#endif
-/**
-  * @}
-  */
-
-/** @addtogroup TIMER_Public_Functions_Group10
-  * @{
-  */
-/* Timer complementary one pulse functions */
-void timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch);
-void timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch);
-void timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
-void timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMER_Public_Functions_Group11
-  * @{
-  */
-/* Control functions */
-ald_status_t timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t* config, timer_channel_t ch);
-ald_status_t timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t* config, timer_channel_t ch);
-ald_status_t timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config,
-                                                   timer_channel_t ch_out,  timer_channel_t ch_in);
-ald_status_t timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch);
-ald_status_t timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config);
-ald_status_t timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select);
-ald_status_t timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config);
-ald_status_t timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config);
-ald_status_t timer_generate_event(timer_handle_t *hperh, timer_event_source_t event);
-uint32_t timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch);
-void timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch);
-void timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config);
-void timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi);
-void timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi);
-void timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config);
-void timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config);
-void timer_irq_handle(timer_handle_t *hperh);
-void timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state);
-void timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state);
-it_status_t timer_get_it_status(timer_handle_t *hperh, timer_it_t it);
-flag_status_t timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag);
-void timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag);
-/**
-  * @}
-  */
-
-/** @addtogroup TIMER_Public_Functions_Group12
-  * @{
-  */
-/* State functions */
-timer_state_t timer_get_state(timer_handle_t *hperh);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_TIMER_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_trng.h

@@ -1,176 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_trng.h
-  * @brief   Header file of TRNG module driver.
-  *
-  * @version V1.0
-  * @date    04 Dec 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  ********************************************************************************
-  */
-
-#ifndef __ALD_TRNG_H__
-#define __ALD_TRNG_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup TRNG
-  * @{
-  */
-
-/** @defgroup TRNG_Public_Macros TRNG Public Macros
-  * @{
-  */
-#define TRNG_ENABLE()		(SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
-#define TRNG_DISABLE()		(CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
-#define TRNG_ADJM_ENABLE()	(SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
-#define TRNG_ADJM_DISABLE()	(CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup TRNG_Public_Types TRNG Public Types
-  * @{
-  */
-/**
-  * @brief Data width
-  */
-typedef enum {
-	TRNG_DSEL_1B  = 0x0,	/**< 1-bit */
-	TRNG_DSEL_8B  = 0x1,	/**< 8-bit */
-	TRNG_DSEL_16B = 0x2,	/**< 16-bit */
-	TRNG_DSEL_32B = 0x3,	/**< 32-bit */
-} trng_data_width_t;
-
-/**
-  * @brief seed type
-  */
-typedef enum {
-	TRNG_SEED_TYPE_0    = 0x0,	/**< Using 0 as seed */
-	TRNG_SEED_TYPE_1    = 0x1,	/**< Using 1 as seed */
-	TRNG_SEED_TYPE_LAST = 0x2,	/**< Using last seed */
-	TRNG_SEED_TYPE_SEED = 0x3,	/**< Using value of register */
-} trng_seed_type_t;
-
-/**
-  * @brief TRNG init structure definition
-  */
-typedef struct {
-	trng_data_width_t data_width;	/**< The width of data */
-	trng_seed_type_t seed_type;	/**< The seed type */
-	uint32_t seed;			/**< The value of seed */
-	uint16_t t_start;		/**< T(start) = T(hclk) * (t_start + 1), T(start) > 1ms */
-	uint8_t adjc;			/**< Adjust parameter */
-	uint8_t posten;
-} trng_init_t;
-
-/**
-  * @brief State type
-  */
-typedef enum {
-	TRNG_STATUS_START = (1U << 0),	/**< Start state */
-	TRNG_STATUS_DAVLD = (1U << 1),	/**< Data valid state */
-	TRNG_STATUS_SERR  = (1U << 2),	/**< Error state */
-} trng_status_t;
-
-/**
-  * @brief Interrupt type
-  */
-typedef enum {
-	TRNG_IT_START = (1U << 0),	/**< Start */
-	TRNG_IT_DAVLD = (1U << 1),	/**< Data valid */
-	TRNG_IT_SERR  = (1U << 2),	/**< Error */
-} trng_it_t;
-
-/**
-  * @brief Interrupt flag type
-  */
-typedef enum {
-	TRNG_IF_START = (1U << 0),	/**< Start */
-	TRNG_IF_DAVLD = (1U << 1),	/**< Data valid */
-	TRNG_IF_SERR  = (1U << 2),	/**< Error */
-} trng_flag_t;
-/**
-  * @}
-  */
-
-/**
-  * @defgroup TRNG_Private_Macros TRNG Private Macros
-  * @{
-  */
-#define IS_TRNG_DATA_WIDTH(x)	(((x) == TRNG_DSEL_1B)  || \
-                                 ((x) == TRNG_DSEL_8B)  || \
-                                 ((x) == TRNG_DSEL_16B) || \
-                                 ((x) == TRNG_DSEL_32B))
-#define IS_TRNG_SEED_TYPE(x)	(((x) == TRNG_SEED_TYPE_0)    || \
-                                 ((x) == TRNG_SEED_TYPE_1)    || \
-                                 ((x) == TRNG_SEED_TYPE_LAST) || \
-                                 ((x) == TRNG_SEED_TYPE_SEED))
-#define IS_TRNG_STATUS(x)	(((x) == TRNG_STATUS_START)  || \
-                                 ((x) == TRNG_STATUS_DAVLD)  || \
-                                 ((x) == TRNG_STATUS_SERR))
-#define IS_TRNG_IT(x)	(((x) == TRNG_IT_START)  || \
-                         ((x) == TRNG_IT_DAVLD)  || \
-                         ((x) == TRNG_IT_SERR))
-#define IS_TRNG_FLAG(x)	(((x) == TRNG_IF_START)  || \
-                         ((x) == TRNG_IF_DAVLD)  || \
-                         ((x) == TRNG_IF_SERR))
-#define IS_TRNG_ADJC(x)	((x) < 4)
-/**
-  * @}
-  */
-
-/** @addtogroup TRNG_Public_Functions
-  * @{
-  */
-/** @addtogroup TRNG_Public_Functions_Group1
-  * @{
-  */
-/* Initialization functions */
-extern void trng_init(trng_init_t *init);
-/**
-  * @}
-  */
-/** @addtogroup TRNG_Public_Functions_Group2
-  * @{
-  */
-/* Control functions */
-extern uint32_t trng_get_result(void);
-extern void trng_interrupt_config(trng_it_t it, type_func_t state);
-extern flag_status_t trng_get_status(trng_status_t status);
-extern it_status_t trng_get_it_status(trng_it_t it);
-extern flag_status_t trng_get_flag_status(trng_flag_t flag);
-extern void trng_clear_flag_status(trng_flag_t flag);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_TRNG_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_uart.h

@@ -1,461 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_uart.h
-  * @brief   Header file of UART module library.
-  *
-  * @version V1.0
-  * @date    21 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#ifndef __ALD_UART_H__
-#define __ALD_UART_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup UART
-  * @{
-  */
-
-/**
-  * @defgroup UART_Public_Macros UART Public Macros
-  * @{
-  */
-#define UART_RX_ENABLE(hperh)		(SET_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK))
-#define UART_RX_DISABLE(hperh)		(CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK))
-#define UART_BRR_WRITE_ENABLE(hperh)	(SET_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK))
-#define UART_BRR_WRITE_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK))
-#define UART_RX_TIMEOUT_ENABLE(hperh)	(SET_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK))
-#define UART_RX_TIMEOUT_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK))
-#define UART_MSB_FIRST_ENABLE(hperh)	(SET_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK))
-#define UART_MSB_FIRST_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK))
-#define UART_DATA_INV_ENABLE(hperh)	(SET_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK))
-#define UART_DATA_INV_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK))
-#define UART_RX_INV_ENABLE(hperh)	(SET_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK))
-#define UART_RX_INV_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK))
-#define UART_TX_INV_ENABLE(hperh)	(SET_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK))
-#define UART_TX_INV_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK))
-#define UART_TX_RX_SWAP_ENABLE(hperh)	(SET_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK))
-#define UART_TX_RX_SWAP_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK))
-#define UART_HDSEL_ENABLE(hperh)	(SET_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK))
-#define UART_HDSEL_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK))
-#define UART_FIFO_TX_RESET(hperh)	(SET_BIT((hperh)->perh->FCR, UART_FCR_TFRST_MSK))
-#define UART_FIFO_RX_RESET(hperh)	(SET_BIT((hperh)->perh->FCR, UART_FCR_RFRST_MSK))
-#define UART_LPBMOD_ENABLE(hperh)	(SET_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK))
-#define UART_LPBMOD_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK))
-#define UART_AUTOBR_ENABLE(hperh)	(SET_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK))
-#define UART_AUTOBR_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK))
-#define UART_AUTOBR_RESTART(hperh)	(SET_BIT((hperh)->perh->MCR, UART_MCR_ABRRS_MSK))
-#define UART_GET_BRR_VALUE(hperh)	(READ_REG((hperh)->perh->BRR))
-#define UART_SET_TIMEOUT_VALUE(x, y)	(MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS))
-/**
-  * @}
-  */
-
-/** @defgroup UART_Public_Types UART Public Types
-  * @{
-  */
-/**
-  * @brief UART word length
-  */
-typedef enum {
-	UART_WORD_LENGTH_5B = 0x0,	/**< 5-bits */
-	UART_WORD_LENGTH_6B = 0x1,	/**< 6-bits */
-	UART_WORD_LENGTH_7B = 0x2,	/**< 7-bits */
-	UART_WORD_LENGTH_8B = 0x3,	/**< 8-bits */
-} uart_word_length_t;
-
-/**
-  * @brief UART stop bits
-  */
-typedef enum {
-	UART_STOP_BITS_1   = 0x0,		/**< 1-bits */
-	UART_STOP_BITS_2   = 0x1,		/**< 2-bits */
-	UART_STOP_BITS_0_5 = 0x0,		/**< 0.5-bits, using smartcard mode */
-	UART_STOP_BITS_1_5 = 0x1,		/**< 1.5-bits, using smartcard mode */
-} uart_stop_bits_t;
-
-/**
-  * @brief UART parity
-  */
-typedef enum {
-	UART_PARITY_NONE = 0x0,		/**< Not parity */
-	UART_PARITY_ODD  = 0x1,		/**< Odd parity */
-	UART_PARITY_EVEN = 0x3,		/**< Even parity */
-} uart_parity_t;
-
-/**
-  * @brief UART mode
-  */
-typedef enum {
-	UART_MODE_UART  = 0x0,		/**< UART */
-	UART_MODE_LIN   = 0x1,		/**< LIN */
-	UART_MODE_IrDA  = 0x2,		/**< IrDA */
-	UART_MODE_RS485 = 0x3,		/**< RS485 */
-	UART_MODE_HDSEL = 0x4,		/**< Single-wire half-duplex */
-} uart_mode_t;
-
-/**
-  * @brief UART hardware flow control
-  */
-typedef enum {
-	UART_HW_FLOW_CTL_DISABLE = 0x0,	/**< Auto-flow-control disable */
-	UART_HW_FLOW_CTL_ENABLE  = 0x1,	/**< Auto-flow-control enable */
-} uart_hw_flow_ctl_t;
-
-/**
-  * @brief ALD UART state
-  */
-typedef enum {
-	UART_STATE_RESET      = 0x00,	/**< Peripheral is not initialized */
-	UART_STATE_READY      = 0x01,	/**< Peripheral Initialized and ready for use */
-	UART_STATE_BUSY       = 0x02,	/**< an internal process is ongoing */
-	UART_STATE_BUSY_TX    = 0x11,	/**< Data Transmission process is ongoing */
-	UART_STATE_BUSY_RX    = 0x21,	/**< Data Reception process is ongoing */
-	UART_STATE_BUSY_TX_RX = 0x31,	/**< Data Transmission Reception process is ongoing */
-	UART_STATE_TIMEOUT    = 0x03,	/**< Timeout state */
-	UART_STATE_ERROR      = 0x04,	/**< Error */
-} uart_state_t;
-
-/**
-  * @brief UART error codes
-  */
-typedef enum {
-	UART_ERROR_NONE = ((uint32_t)0x00),	/**< No error */
-	UART_ERROR_PE   = ((uint32_t)0x01),	/**< Parity error */
-	UART_ERROR_NE   = ((uint32_t)0x02),	/**< Noise error */
-	UART_ERROR_FE   = ((uint32_t)0x04),	/**< frame error */
-	UART_ERROR_ORE  = ((uint32_t)0x08),	/**< Overrun error */
-	UART_ERROR_DMA  = ((uint32_t)0x10),	/**< DMA transfer error */
-} uart_error_t;
-
-/**
-  * @brief UART init structure definition
-  */
-typedef struct {
-	uint32_t baud;			/**< Specifies the uart communication baud rate */
-	uart_word_length_t word_length;	/**< Specifies the number of data bits transmitted or received in a frame */
-	uart_stop_bits_t stop_bits;	/**< Specifies the number of stop bits transmitted */
-	uart_parity_t parity;		/**< Specifies the parity mode */
-	uart_mode_t mode;		/**< Specifies uart mode */
-	uart_hw_flow_ctl_t fctl;	/**< Specifies wether the hardware flow control mode is enabled or disabled */
-} uart_init_t;
-
-/**
-  * @brief  UART handle structure definition
-  */
-typedef struct uart_handle_s {
-	UART_TypeDef *perh;	/**< UART registers base address */
-	uart_init_t init;	/**< UART communication parameters */
-	uint8_t *tx_buf;	/**< Pointer to UART Tx transfer Buffer */
-	uint16_t tx_size;	/**< UART Tx Transfer size */
-	uint16_t tx_count;	/**< UART Tx Transfer Counter */
-	uint8_t *rx_buf;	/**< Pointer to UART Rx transfer Buffer */
-	uint16_t rx_size;	/**< UART Rx Transfer size */
-	uint16_t rx_count;	/**< UART Rx Transfer Counter */
-#ifdef ALD_DMA
-	dma_handle_t hdmatx;	/**< UART Tx DMA Handle parameters */
-	dma_handle_t hdmarx;	/**< UART Rx DMA Handle parameters */
-#endif
-	lock_state_t lock;	/**< Locking object */
-	uart_state_t state;	/**< UART communication state */
-	uart_error_t err_code;	/**< UART Error code */
-
-	void (*tx_cplt_cbk)(struct uart_handle_s *arg);	/**< Tx completed callback */
-	void (*rx_cplt_cbk)(struct uart_handle_s *arg);	/**< Rx completed callback */
-	void (*error_cbk)(struct uart_handle_s *arg);	/**< error callback */
-} uart_handle_t;
-
-/**
-  * @brief UART RS485 configure structure definition
-  */
-typedef struct {
-	type_func_t normal;	/**< Normal mode */
-	type_func_t dir;	/**< Auto-direction mode */
-	type_func_t invert;	/**< Address detection invert */
-	uint8_t addr;		/**< Address for compare */
-} uart_rs485_config_t;
-
-/**
-  * @brief LIN detection break length
-  */
-typedef enum {
-	LIN_BREAK_LEN_10B = 0x0,	/**< 10-bit break */
-	LIN_BREAK_LEN_11B = 0x1,	/**< 11-bit break */
-} uart_lin_break_len_t;
-
-/**
-  * @brief UART TXFIFO size
-  */
-typedef enum {
-	UART_TXFIFO_EMPTY = 0x0,	/**< Empty */
-	UART_TXFIFO_2BYTE = 0x1,	/**< 2-Bytes */
-	UART_TXFIFO_4BYTE = 0x2,	/**< 4-Bytes */
-	UART_TXFIFO_8BYTE = 0x3,	/**< 8-Bytes */
-} uart_txfifo_t;
-
-/**
-  * @brief UART RXFIFO size
-  */
-typedef enum {
-	UART_RXFIFO_1BYTE  = 0x0,	/**< 1-Byte */
-	UART_RXFIFO_4BYTE  = 0x1,	/**< 4-Bytes */
-	UART_RXFIFO_8BYTE  = 0x2,	/**< 8-Bytes */
-	UART_RXFIFO_14BYTE = 0x3,	/**< 14-Bytes */
-} uart_rxfifo_t;
-
-/**
-  * @brief UART auto-baud mode
-  */
-typedef enum {
-	UART_ABRMOD_1_TO_0 = 0x0,	/**< Detect bit0:1, bit1:0 */
-	UART_ABRMOD_1      = 0x1,	/**< Detect bit0:1 */
-	UART_ABRMOD_0_TO_1 = 0x2,	/**< Detect bit0:0, bit1:1 */
-} uart_auto_baud_mode_t;
-
-/**
-  * @brief UART status types
-  */
-typedef enum {
-	UART_STATUS_DR   = (1U << 0),	/**< Data ready */
-	UART_STATUS_OE   = (1U << 1),	/**< Overrun error */
-	UART_STATUS_PE   = (1U << 2),	/**< Parity error */
-	UART_STATUS_FE   = (1U << 3),	/**< Framing error */
-	UART_STATUS_BI   = (1U << 4),	/**< Break interrupt */
-	UART_STATUS_TBEM = (1U << 5),	/**< Transmit buffer empty */
-	UART_STATUS_TEM  = (1U << 6),	/**< Transmitter empty */
-	UART_STATUS_RFE  = (1U << 7),	/**< Reveiver FIFO data error */
-	UART_STATUS_BUSY = (1U << 8),	/**< UART busy */
-	UART_STATUS_TFNF = (1U << 9),	/**< Transmit FIFO not full */
-	UART_STATUS_TFEM = (1U << 10),	/**< Transmit FIFO not empty */
-	UART_STATUS_RFNE = (1U << 11),	/**< Receive FIFO not empty */
-	UART_STATUS_RFF  = (1U << 12),	/**< Receive FIFO full */
-	UART_STATUS_DCTS = (1U << 14),	/**< Delta clear to send */
-	UART_STATUS_CTS  = (1U << 15),	/**< Clear to send */
-} uart_status_t;
-
-/**
-  * @brief UART interrupt types
-  */
-typedef enum {
-	UART_IT_RXRD  = (1U << 0),	/**< Receive data available */
-	UART_IT_TXS   = (1U << 1),	/**< Tx empty status */
-	UART_IT_RXS   = (1U << 2),	/**< Rx line status */
-	UART_IT_MDS   = (1U << 3),	/**< Modem status */
-	UART_IT_RTO   = (1U << 4),	/**< Receiver timeout */
-	UART_IT_BZ    = (1U << 5),	/**< Busy status */
-	UART_IT_ABE   = (1U << 6),	/**< Auto-baud rate detection end */
-	UART_IT_ABTO  = (1U << 7),	/**< Auto-baud rate detection timeout */
-	UART_IT_LINBK = (1U << 8),	/**< Lin break detection */
-	UART_IT_TC    = (1U << 9),	/**< Transmission complete */
-	UART_IT_EOB   = (1U << 10),	/**< End of block */
-	UART_IT_CM    = (1U << 11),	/**< Character match */
-} uart_it_t;
-
-/**
-  * @brief UART flags types
-  */
-typedef enum {
-	UART_IF_RXRD  = (1U << 0),	/**<  Receive data available */
-	UART_IF_TXS   = (1U << 1),	/**<  Tx empty status */
-	UART_IF_RXS   = (1U << 2),	/**<  Rx line status */
-	UART_IF_MDS   = (1U << 3),	/**<  Modem status */
-	UART_IF_RTO   = (1U << 4),	/**<  Receiver timeout */
-	UART_IF_BZ    = (1U << 5),	/**<  Busy status */
-	UART_IF_ABE   = (1U << 6),	/**<  Auto-baud rate detection end */
-	UART_IF_ABTO  = (1U << 7),	/**<  Auto-baud rate detection timeout */
-	UART_IF_LINBK = (1U << 8),	/**<  Lin break detection */
-	UART_IF_TC    = (1U << 9),	/**<  Transmission complete */
-	UART_IF_EOB   = (1U << 10),	/**<  End of block */
-	UART_IF_CM    = (1U << 11),	/**<  Character match */
-} uart_flag_t;
-/**
-  * @}
-  */
-
-/** @defgroup UART_Private_Macros   UART Private Macros
-  * @{
-  */
-#define IS_UART_ALL(x)	(((x) == UART0) || \
-                         ((x) == UART1) || \
-                         ((x) == UART2) || \
-                         ((x) == UART3))
-#define IS_UART_WORD_LENGTH(x)	(((x) == UART_WORD_LENGTH_5B) || \
-                                 ((x) == UART_WORD_LENGTH_6B) || \
-                                 ((x) == UART_WORD_LENGTH_7B) || \
-                                 ((x) == UART_WORD_LENGTH_8B))
-#define IS_UART_STOPBITS(x)	(((x) == UART_STOP_BITS_1)   || \
-                                 ((x) == UART_STOP_BITS_2)   || \
-                                 ((x) == UART_STOP_BITS_0_5) || \
-                                 ((x) == UART_STOP_BITS_1_5))
-#define IS_UART_PARITY(x)	(((x) == UART_PARITY_NONE)  || \
-                                 ((x) == UART_PARITY_ODD) || \
-                                 ((x) == UART_PARITY_EVEN))
-#define IS_UART_MODE(x)		(((x) == UART_MODE_UART) || \
-                                 ((x) == UART_MODE_LIN)  || \
-                                 ((x) == UART_MODE_IrDA) || \
-                                 ((x) == UART_MODE_RS485) || \
-                                 ((x) == UART_MODE_HDSEL))
-#define IS_UART_HARDWARE_FLOW_CONTROL(x) \
-                                (((x) == UART_HW_FLOW_CTL_DISABLE) || \
-                                 ((x) == UART_HW_FLOW_CTL_ENABLE))
-#define IS_UART_LIN_BREAK_LEN(x)	(((x) == LIN_BREAK_LEN_10B) || \
-                                         ((x) == LIN_BREAK_LEN_11B))
-#define IS_UART_TXFIFO_TYPE(x)	(((x) == UART_TXFIFO_EMPTY) || \
-                                 ((x) == UART_TXFIFO_2BYTE) || \
-                                 ((x) == UART_TXFIFO_4BYTE) || \
-                                 ((x) == UART_TXFIFO_8BYTE))
-#define IS_UART_RXFIFO_TYPE(x)	(((x) == UART_RXFIFO_1BYTE) || \
-                                 ((x) == UART_RXFIFO_4BYTE) || \
-                                 ((x) == UART_RXFIFO_8BYTE) || \
-                                 ((x) == UART_RXFIFO_14BYTE))
-#define IS_UART_AUTO_BAUD_MODE(x)	(((x) == UART_ABRMOD_1_TO_0) || \
-                                         ((x) == UART_ABRMOD_1)      || \
-                                         ((x) == UART_ABRMOD_0_TO_1))
-#define IS_UART_STATUS(x)	(((x) == UART_STATUS_DR)   || \
-                                 ((x) == UART_STATUS_OE)   || \
-                                 ((x) == UART_STATUS_PE)   || \
-                                 ((x) == UART_STATUS_FE)   || \
-                                 ((x) == UART_STATUS_BI)   || \
-                                 ((x) == UART_STATUS_TBEM) || \
-                                 ((x) == UART_STATUS_TEM)  || \
-                                 ((x) == UART_STATUS_RFE)  || \
-                                 ((x) == UART_STATUS_BUSY) || \
-                                 ((x) == UART_STATUS_TFNF) || \
-                                 ((x) == UART_STATUS_TFEM) || \
-                                 ((x) == UART_STATUS_RFNE) || \
-                                 ((x) == UART_STATUS_RFF)  || \
-                                 ((x) == UART_STATUS_DCTS) || \
-                                 ((x) == UART_STATUS_CTS))
-#define IS_UART_IT(x)		(((x) == UART_IT_RXRD)  || \
-                                 ((x) == UART_IT_TXS)   || \
-                                 ((x) == UART_IT_RXS)   || \
-                                 ((x) == UART_IT_MDS)   || \
-                                 ((x) == UART_IT_RTO)   || \
-                                 ((x) == UART_IT_BZ)    || \
-                                 ((x) == UART_IT_ABE)   || \
-                                 ((x) == UART_IT_ABTO)  || \
-                                 ((x) == UART_IT_LINBK) || \
-                                 ((x) == UART_IT_TC)    || \
-                                 ((x) == UART_IT_EOB)   || \
-                                 ((x) == UART_IT_CM))
-#define IS_UART_IF(x)		(((x) == UART_IF_RXRD)  || \
-                                 ((x) == UART_IF_TXS)   || \
-                                 ((x) == UART_IF_RXS)   || \
-                                 ((x) == UART_IF_MDS)   || \
-                                 ((x) == UART_IF_RTO)   || \
-                                 ((x) == UART_IF_BZ)    || \
-                                 ((x) == UART_IF_ABE)   || \
-                                 ((x) == UART_IF_ABTO)  || \
-                                 ((x) == UART_IF_LINBK) || \
-                                 ((x) == UART_IF_TC)    || \
-                                 ((x) == UART_IF_EOB)   || \
-                                 ((x) == UART_IF_CM))
-#define IS_UART_BAUDRATE(x)	(((x) > 0) && ((x) < 0x44AA21))
-#define IS_UART_DATA(x)		((x) <= 0x1FF)
-
-#define UART_STATE_TX_MASK	(1U << 4)
-#define UART_STATE_RX_MASK	(1U << 5)
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Public_Functions
-  * @{
-  */
-
-/** @addtogroup UART_Public_Functions_Group1
-  * @{
-  */
-/* Initialization functions */
-void uart_init(uart_handle_t *hperh);
-void uart_reset(uart_handle_t *hperh);
-void uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config);
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Public_Functions_Group2
-  * @{
-  */
-/* IO operation functions */
-ald_status_t uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size);
-ald_status_t uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size);
-#ifdef ALD_DMA
-ald_status_t uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t uart_dma_pause(uart_handle_t *hperh);
-ald_status_t uart_dma_resume(uart_handle_t *hperh);
-ald_status_t uart_dma_stop(uart_handle_t *hperh);
-#endif
-void uart_irq_handle(uart_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Public_Functions_Group3
-  * @{
-  */
-/* Peripheral Control functions */
-void uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state);
-void uart_dma_req_config(uart_handle_t *hperh, type_func_t state);
-void uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level);
-void uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level);
-void uart_lin_send_break(uart_handle_t *hperh);
-void uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len);
-void uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode);
-ald_status_t uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout);
-it_status_t uart_get_it_status(uart_handle_t *hperh, uart_it_t it);
-flag_status_t uart_get_status(uart_handle_t *hperh, uart_status_t status);
-flag_status_t uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag);
-flag_status_t uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag);
-void uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag);
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Public_Functions_Group4
-  * @{
-  */
-/* Peripheral State and Errors functions */
-uart_state_t uart_get_state(uart_handle_t *hperh);
-uint32_t uart_get_error(uart_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_UART_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_usart.h

@@ -1,561 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_usart.h
-  * @brief   Header file of USART module library.
-  *
-  * @version V1.0
-  * @date    16 Apr 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#ifndef __ALD_USART_H__
-#define __ALD_USART_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup USART
-  * @{
-  */
-
-/** @defgroup USART_Public_Types USART Public Types
-  * @{
-  */
-
-/**
-  * @brief usart_word_length
-  */
-typedef enum {
-	USART_WORD_LENGTH_8B = 0x0,	/**< Word length is 8-bits */
-	USART_WORD_LENGTH_9B = 0x1,	/**< Word length is 9-bits */
-} usart_word_length_t;
-
-/**
-  * @brief usart_stop_bits
-  */
-typedef enum {
-	USART_STOP_BITS_1   = 0x0,	/**< Stop bits is 1-bits */
-	USART_STOP_BITS_0_5 = 0x1,	/**< Stop bits is 0.5-bits */
-	USART_STOP_BITS_2   = 0x2,	/**< Stop bits is 2-bits */
-	USART_STOP_BITS_1_5 = 0x3,	/**< Stop bits is 1.5-bits */
-} usart_stop_bits_t;
-
-/**
-  * @brief usart_parity
-  */
-typedef enum {
-	USART_PARITY_NONE = 0x0,	/**< Not parity */
-	USART_PARITY_EVEN = 0x2,	/**< Even parity */
-	USART_PARITY_ODD  = 0x3,	/**< Odd parity */
-} usart_parity_t;
-
-/**
-  * @brief usart_mode
-  */
-typedef enum {
-	USART_MODE_RX    = 0x1,		/**< TX mode */
-	USART_MODE_TX    = 0x2,		/**< RX mode */
-	USART_MODE_TX_RX = 0x3,		/**< TX & RX mode */
-} usart_mode_t;
-
-/**
-  * @brief usart_hardware_flow_control
-  */
-typedef enum {
-	USART_HW_FLOW_CTL_NONE    = 0x0,	/**< Not flow control */
-	USART_HW_FLOW_CTL_RTS     = 0x1,	/**< RTS flow control */
-	USART_HW_FLOW_CTL_CTS     = 0x2,	/**< CTS flow control */
-	USART_HW_FLOW_CTL_RTS_CTS = 0x3,	/**< RTS & CTS flow control */
-} usart_hw_flow_ctl_t;
-
-/**
-  * @brief usart_clock
-  */
-typedef enum {
-	USART_CLOCK_DISABLE = 0x0,	/**< Disable clock output */
-	USART_CLOCK_ENABLE  = 0x1,	/**< Enable clock output */
-} usart_clock_t;
-
-/**
-  * @brief usart_clock_polarity
-  */
-typedef enum {
-	USART_CPOL_LOW  = 0x0,		/**< Clock polarity low */
-	USART_CPOL_HIGH = 0x1,		/**< Clock polarity high */
-} usart_cpol_t;
-
-/**
-  * @brief usart_clock_phase
-  */
-typedef enum {
-	USART_CPHA_1EDGE = 0x0,		/**< Clock phase first edge */
-	USART_CPHA_2EDGE = 0x1,		/**< Clock phase second edge */
-} usart_cpha_t;
-
-/**
-  * @brief usart_last_bit
-  */
-typedef enum {
-	USART_LAST_BIT_DISABLE = 0x0,	/**< Disable last bit clock output */
-	USART_LAST_BIT_ENABLE  = 0x1,	/**< Enable last bit clock output */
-} usart_last_bit_t;
-
-/**
-  * @brief usart state structures definition
-  */
-typedef enum {
-	USART_STATE_RESET      = 0x00,	/**< Peripheral is not initialized */
-	USART_STATE_READY      = 0x01,	/**< Peripheral Initialized and ready for use */
-	USART_STATE_BUSY       = 0x02,	/**< an internal process is ongoing */
-	USART_STATE_BUSY_TX    = 0x11,	/**< Data Transmission process is ongoing */
-	USART_STATE_BUSY_RX    = 0x21,	/**< Data Reception process is ongoing */
-	USART_STATE_BUSY_TX_RX = 0x31,	/**< Data Transmission Reception process is ongoing */
-	USART_STATE_TIMEOUT    = 0x03,	/**< Timeout state */
-	USART_STATE_ERROR      = 0x04,	/**< Error */
-} usart_state_t;
-
-/**
-  * @brief usart error codes
-  */
-typedef enum {
-	USART_ERROR_NONE = ((uint32_t)0x00),	/**< No error */
-	USART_ERROR_PE   = ((uint32_t)0x01),	/**< Parity error */
-	USART_ERROR_NE   = ((uint32_t)0x02),	/**< Noise error */
-	USART_ERROR_FE   = ((uint32_t)0x04),	/**< frame error */
-	USART_ERROR_ORE  = ((uint32_t)0x08),	/**< Overrun error */
-	USART_ERROR_DMA  = ((uint32_t)0x10),	/**< DMA transfer error */
-} usart_error_t;
-
-
-/**
-  * @brief usart init structure definition
-  */
-typedef struct {
-	uint32_t baud;			/**< This member configures the Usart communication baud rate. */
-	usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */
-	usart_stop_bits_t stop_bits;	/**< Specifies the number of stop bits transmitted. */
-	usart_parity_t parity;		/**< Specifies the parity mode.
-					     @note When parity is enabled, the computed parity is inserted
- 						   at the MSB position of the transmitted data (9th bit when
- 						   the word length is set to 9 data bits; 8th bit when the
-						   word length is set to 8 data bits). */
-	usart_mode_t mode;		/**< Specifies wether the Receive or Transmit mode is enabled or disabled. */
-	usart_hw_flow_ctl_t fctl;	/**< Specifies wether the hardware flow control mode is enabled or disabled. */
-	type_func_t over_sampling;	/**< Specifies whether the Over sampling 8 is enabled or disabled. */
-} usart_init_t;
-
-/**
-  * @brief  USART handle structure definition
-  */
-typedef struct usart_handle_s {
-	USART_TypeDef *perh;	/**< USART registers base address */
-	usart_init_t init;	/**< USART communication parameters */
-	uint8_t *tx_buf;	/**< Pointer to USART Tx transfer buffer */
-	uint16_t tx_size;	/**< USART Tx transfer size */
-	uint16_t tx_count;	/**< USART Tx transfer counter */
-	uint8_t *rx_buf;	/**< Pointer to USART Rx transfer buffer */
-	uint16_t rx_size;	/**< USART Rx Transfer size */
-	uint16_t rx_count;	/**< USART Rx Transfer Counter */
-#ifdef ALD_DMA
-	dma_handle_t hdmatx;	/**< USART Tx DMA handle parameters */
-	dma_handle_t hdmarx;	/**< USART Rx DMA handle parameters */
-#endif
-	lock_state_t lock;	/**< Locking object */
-	usart_state_t state;	/**< USART communication state */
-	uint32_t err_code;	/**< USART error code */
-
-	void (*tx_cplt_cbk)(struct usart_handle_s *arg);	/**< Tx completed callback */
-	void (*rx_cplt_cbk)(struct usart_handle_s *arg);	/**< Rx completed callback */
-	void (*tx_rx_cplt_cbk)(struct usart_handle_s *arg);	/**< Tx & Rx completed callback */
-	void (*error_cbk)(struct usart_handle_s *arg);		/**< error callback */
-} usart_handle_t;
-
-
-/**
-  * @brief USART clock init structure definition
-  */
-typedef struct {
-	usart_clock_t clk;		/**< Pecifies whether the USART clock is enable or disable. */
-	usart_cpol_t polarity;		/**< Specifies the steady state of the serial clock. */
-	usart_cpha_t phase;		/**< Specifies the clock transition on which the bit capture is made. */
-	usart_last_bit_t last_bit;	/**< Specifies whether the clock pulse corresponding to the last transmitted
-				             data bit (MSB) has to be output on the SCLK pin in synchronous mode. */
-} usart_clock_init_t;
-
-
-/**
-  * @brief usart_dma_request
-  */
-typedef enum {
-	USART_DMA_REQ_TX = (1U << 7),	/**< TX dma bit */
-	USART_DMA_REQ_RX = (1U << 6),	/**< RX dma bit */
-} usart_dma_req_t;
-
-/**
-  * @brief usart_wakeup_methods
-  */
-typedef enum {
-	USART_WAKEUP_IDLE = 0x0,	/**< Wake up the machine when bus-line is idle */
-	USART_WAKEUP_ADDR = 0x1,	/**< Wake up the machine when match the address */
-} usart_wakeup_t;
-
-/**
-  * @brief usart_IrDA_low_power
-  */
-typedef enum {
-	USART_IrDA_MODE_NORMAL    = 0x0,		/**< Normal IrDA mode */
-	USART_IrDA_MODE_LOW_POWER = 0x1,		/**< Low-power IrDA mode */
-} usart_IrDA_mode_t;
-
-/**
-  * @brief USART interrupts definition
-  */
-typedef enum {
-	USART_IT_PE   = ((1U << 8) | (1U << 16)),	/**< Parity error */
-	USART_IT_TXE  = ((1U << 7) | (1U << 16)),	/**< Tx empty */
-	USART_IT_TC   = ((1U << 6) | (1U << 16)),	/**< Tx complete */
-	USART_IT_RXNE = ((1U << 5) | (1U << 16)),	/**< Rx not empty */
-	USART_IT_IDLE = ((1U << 4) | (1U << 16)),	/**< Idle */
-	USART_IT_CTS  = ((1U << 10)| (1U << 18)),	/**< CTS */
-	USART_IT_ERR  = ((1U << 0) | (1U << 18)),	/**< Error */
-	USART_IT_ORE  = (1U << 3),			/**< Overrun error */
-	USART_IT_NE   = (1U << 2),			/**< Noise error */
-	USART_IT_FE   = (1U << 0),			/**< Frame error */
-} usart_it_t;
-
-/**
-  * @brief USART flags
-  */
-typedef enum {
-	USART_FLAG_CTS  = (1U << 9),	/**< CTS */
-	USART_FLAG_TXE  = (1U << 7),	/**< Tx empty */
-	USART_FLAG_TC   = (1U << 6),	/**< Tx complete */
-	USART_FLAG_RXNE = (1U << 5),	/**< Rx not empty */
-	USART_FLAG_IDLE = (1U << 4),	/**< Idle */
-	USART_FLAG_ORE  = (1U << 3),	/**< Overrun error */
-	USART_FLAG_NE   = (1U << 2),	/**< Noise error */
-	USART_FLAG_FE   = (1U << 1),	/**< Frame error */
-	USART_FLAG_PE   = (1U << 0),	/**< Parity error */
-} usart_flag_t;
-
-/**
-  * @}
-  */
-
-
-/** @defgroup USART_Public_Macros USART Public Macros
-  * @{
-  */
-
-/** @defgroup USART_Public_Macros_1 USART handle reset
-  * @{
-  */
-#define USART_RESET_HANDLE_STATE(handle) ((handle)->state = USART_STATE_RESET)
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Macros_2 USART clear PE flag
-  * @{
-  */
-#define USART_CLEAR_PEFLAG(handle)	\
-do {					\
-	__IO uint32_t tmpreg;		\
-	tmpreg = (handle)->perh->STAT;	\
-	tmpreg = (handle)->perh->DATA;	\
-	UNUSED(tmpreg);			\
-} while (0)
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Macros_3 USART clear FE flag
-  * @{
-  */
-#define USART_CLEAR_FEFLAG(handle) USART_CLEAR_PEFLAG(handle)
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Macros_4 USART clear NE flag
-  * @{
-  */
-#define USART_CLEAR_NEFLAG(handle) USART_CLEAR_PEFLAG(handle)
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Macros_5 USART clear ORE flag
-  * @{
-  */
-#define USART_CLEAR_OREFLAG(handle) USART_CLEAR_PEFLAG(handle)
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Macros_6 USART clear IDLE flag
-  * @{
-  */
-#define USART_CLEAR_IDLEFLAG(handle) USART_CLEAR_PEFLAG(handle)
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Macros_7 USART enable CTS flow control
-  * @{
-  */
-#define USART_HWCONTROL_CTS_ENABLE(handle)	\
-	(SET_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Macros_8 USART disable CTS flow control
-  * @{
-  */
-#define USART_HWCONTROL_CTS_DISABLE(handle)	\
-	(CLEAR_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Macros_9 USART enable RTS flow control
-  * @{
-  */
-#define USART_HWCONTROL_RTS_ENABLE(handle)	\
-	(SET_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Macros_10 USART disable RTS flow control
-  * @{
-  */
-#define USART_HWCONTROL_RTS_DISABLE(handle)	\
-	(CLEAR_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Macros_11 USART enable
-  * @{
-  */
-#define USART_ENABLE(handle)	(SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Macros_12 USART disable
-  * @{
-  */
-#define USART_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK))
- /**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Private_Macros   USART Private Macros
-  * @{
-  */
-
-#define IS_USART(x) (((x) == USART0) || ((x) == USART1))
-#define IS_USART_WORD_LENGTH(x) (((x) == USART_WORD_LENGTH_8B) || \
-                                 ((x) == USART_WORD_LENGTH_9B))
-#define IS_USART_STOPBITS(x) (((x) == USART_STOP_BITS_1) ||   \
-                              ((x) == USART_STOP_BITS_0_5) || \
-                              ((x) == USART_STOP_BITS_2) ||   \
-                              ((x) == USART_STOP_BITS_1_5))
-#define IS_USART_PARITY(x) (((x) == USART_PARITY_NONE) ||   \
-                            ((x) == USART_PARITY_EVEN) || \
-                            ((x) == USART_PARITY_ODD))
-#define IS_USART_MODE(x) (((x) == USART_MODE_RX) || \
-			  ((x) == USART_MODE_TX) || \
-			  ((x) == USART_MODE_TX_RX))
-#define IS_USART_HARDWARE_FLOW_CONTROL(x)\
-                              (((x) == USART_HW_FLOW_CTL_NONE) || \
-                               ((x) == USART_HW_FLOW_CTL_RTS)  || \
-                               ((x) == USART_HW_FLOW_CTL_CTS)  || \
-                               ((x) == USART_HW_FLOW_CTL_RTS_CTS))
-#define IS_USART_CLOCK(x) (((x) == USART_CLOCK_DISABLE) || \
-                           ((x) == USART_CLOCK_ENABLE))
-#define IS_USART_CPOL(x) (((x) == USART_CPOL_LOW) || ((x) == USART_CPOL_HIGH))
-#define IS_USART_CPHA(x) (((x) == USART_CPHA_1EDGE) || ((x) == USART_CPHA_2EDGE))
-#define IS_USART_LASTBIT(x) (((x) == USART_LAST_BIT_DISABLE) || \
-                             ((x) == USART_LAST_BIT_ENABLE))
-#define IS_USART_DMAREQ(x) (((x) == USART_DMA_REQ_TX) || \
-                            ((x) == USART_DMA_REQ_RX))
-#define IS_USART_WAKEUP(x) (((x) == USART_WAKEUP_IDLE) || \
-                            ((x) == USART_WAKEUP_ADDR))
-#define IS_USART_IRDA_MODE(x) (((x) == USART_IrDA_MODE_NORMAL) || \
-                               ((x) == USART_IrDA_MODE_LOW_POWER))
-#define IS_USART_CONFIG_IT(x) (((x) == USART_IT_PE) || ((x) == USART_IT_TXE)   || \
-                               ((x) == USART_IT_TC) || ((x) == USART_IT_RXNE)  || \
-                               ((x) == USART_IT_IDLE) || \
-                               ((x) == USART_IT_CTS) || ((x) == USART_IT_ERR))
-#define IS_USART_GET_IT(x) (((x) == USART_IT_PE) || ((x) == USART_IT_TXE)   || \
-                            ((x) == USART_IT_TC) || ((x) == USART_IT_RXNE)  || \
-                            ((x) == USART_IT_IDLE) || \
-                            ((x) == USART_IT_CTS) || ((x) == USART_IT_ORE)  || \
-                            ((x) == USART_IT_NE) || ((x) == USART_IT_FE)    || \
-                            ((x) == USART_IT_ERR))
-#define IS_USART_CLEAR_IT(x) (((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \
-                               ((x) == USART_IT_CTS))
-
-#define IS_USART_FLAG(x) (((x) == USART_FLAG_PE) || ((x) == USART_FLAG_TXE)   || \
-                          ((x) == USART_FLAG_TC) || ((x) == USART_FLAG_RXNE)  || \
-                          ((x) == USART_FLAG_IDLE) || \
-                          ((x) == USART_FLAG_CTS) || ((x) == USART_FLAG_ORE)  || \
-                          ((x) == USART_FLAG_NE) || ((x) == USART_FLAG_FE))
-#define IS_USART_CLEAR_FLAG(x) (((x) == USART_FLAG_CTS) || \
-                                ((x) == USART_FLAG_TC)  || \
-                                ((x) == USART_FLAG_RXNE))
-#define IS_USART_BAUDRATE(x)	(((x) > 0) && ((x) < 0x0044AA21))
-#define IS_USART_ADDRESS(x)	((x) <= 0xF)
-#define IS_USART_DATA(x)	((x) <= 0x1FF)
-#define DUMMY_DATA		0xFFFF
-#define USART_STATE_TX_MASK	(1 << 4)
-#define USART_STATE_RX_MASK	(1 << 5)
-
-/**
-  * @}
-  */
-
-/** @addtogroup USART_Public_Functions
-  * @{
-  */
-
-/** @addtogroup USART_Public_Functions_Group1
-  * @{
-  */
-/* Initialization functions */
-void usart_reset(usart_handle_t *hperh);
-ald_status_t usart_init(usart_handle_t *hperh);
-ald_status_t usart_half_duplex_init(usart_handle_t *hperh);
-ald_status_t usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usart_wakeup_t wakeup);
-ald_status_t usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init);
-/**
-  * @}
-  */
-
-/** @addtogroup USART_Public_Functions_Group2
-  * @{
-  */
-
-/** @addtogroup USART_Public_Functions_Group2_1
-  * @{
-  */
-/* Asynchronization IO operation functions */
-ald_status_t usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size);
-ald_status_t usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size);
-ald_status_t usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size);
-#ifdef ALD_DMA
-ald_status_t usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-#endif
-/**
-  * @}
-  */
-
-/** @addtogroup USART_Public_Functions_Group2_2
-  * @{
-  */
-/* Synchronization IO operation functions */
-ald_status_t usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout);
-ald_status_t usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size);
-ald_status_t usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size);
-ald_status_t usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf,  uint16_t size);
-#ifdef ALD_DMA
-ald_status_t usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel);
-ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf,
-                    uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel);
-#endif
-/**
-  * @}
-  */
-
-/** @addtogroup USART_Public_Functions_Group2_3
-  * @{
-  */
-/* Utilities functions */
-#ifdef ALD_DMA
-ald_status_t usart_dma_pause(usart_handle_t *hperh);
-ald_status_t usart_dma_resume(usart_handle_t *hperh);
-ald_status_t usart_dma_stop(usart_handle_t *hperh);
-#endif
-void usart_irq_handle(usart_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup USART_Public_Functions_Group3
-  * @{
-  */
-/* Peripheral control functions */
-ald_status_t usart_multi_processor_enter_mute_mode(usart_handle_t *hperh);
-ald_status_t usart_multi_processor_exit_mute_mode(usart_handle_t *hperh);
-ald_status_t usart_half_duplex_enable_send(usart_handle_t *hperh);
-ald_status_t usart_half_duplex_enable_recv(usart_handle_t *hperh);
-void usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_t state);
-void usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t state);
-flag_status_t usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag);
-void usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag);
-it_status_t usart_get_it_status(usart_handle_t *hperh, usart_it_t it);
-/**
-  * @}
-  */
-
-/** @addtogroup USART_Public_Functions_Group4
-  * @{
-  */
-
-/* Peripheral state and error functions */
-usart_state_t usart_get_state(usart_handle_t *hperh);
-uint32_t usart_get_error(usart_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_USART_H__ */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_acmp.c

@@ -1,326 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_acmp.c
-  * @brief   ACMP module driver.
-  *
-  * @version V1.0
-  * @date    13 Dec 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#include "ald_acmp.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup ACMP ACMP
-  * @brief ACMP module driver
-  * @{
-  */
-#ifdef ALD_ACMP
-
-/** @defgroup ACMP_Public_Functions ACMP Public Functions
-  * @{
-  */
-
-/** @defgroup ACMP_Public_Functions_Group1 Initialization functions
-  * @brief Initialization and Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  Initializes the ACMP mode according to the specified parameters in
-  *         the acmp_init_t and create the associated handle.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t acmp_init(acmp_handle_t *hperh)
-{
-	uint32_t tmp = 0;
-
-	if (hperh == NULL)
-		return ERROR;
-
-	if (hperh->init.vdd_level > 63)
-		return ERROR;
-
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-	assert_param(IS_ACMP_MODE_TYPE(hperh->init.mode));
-	assert_param(IS_ACMP_WARM_UP_TIME_TYPE(hperh->init.warm_time));
-	assert_param(IS_ACMP_HYSTSEL_TYPE(hperh->init.hystsel));
-	assert_param(IS_ACMP_WARM_FUNC_TYPE(hperh->init.warm_func));
-	assert_param(IS_ACMP_POS_INPUT_TYPE(hperh->init.pos_port));
-	assert_param(IS_ACMP_NEG_INPUT_TYPE(hperh->init.neg_port));
-	assert_param(IS_ACMP_INACTVAL_TYPE(hperh->init.inactval));
-	assert_param(IS_ACMP_EDGE_TYPE(hperh->init.edge));
-
-	__LOCK(hperh);
-
-	tmp = hperh->perh->CON;
-
-	tmp |= ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) |
-		(hperh->init.inactval << ACMP_CON_INACTV_POS));
-
-	hperh->perh->CON = tmp;
-
-	tmp = hperh->perh->INPUTSEL;
-
-	tmp |= ((hperh->init.pos_port << ACMP_INPUTSEL_PSEL_POSS) | (hperh->init.neg_port << ACMP_INPUTSEL_NSEL_POSS) |
-		(hperh->init.vdd_level << ACMP_INPUTSEL_VDDLVL_POSS));
-
-	hperh->perh->INPUTSEL = tmp;
-
-	if (hperh->init.warm_func == ACMP_WARM_DISABLE)
-		CLEAR_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK);
-	else
-		SET_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK);
-
-	switch (hperh->init.edge) {
-	case ACMP_EDGE_NONE:
-		CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
-		CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
-		break;
-
-	case ACMP_EDGE_FALL:
-		SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
-		CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
-		break;
-
-	case ACMP_EDGE_RISE:
-		CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
-		SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
-		break;
-
-	case ACMP_EDGE_ALL:
-		SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
-		SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
-		break;
-
-	default:
-		break;
-	}
-
-	SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK);
-
-	while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0);
-
-	__UNLOCK(hperh);
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup ACMP_Public_Functions_Group2 Interrupt operation functions
-  * @brief ACMP Interrupt operation functions
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified ACMP interrupts.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @param  it: Specifies the ACMP interrupt sources to be enabled or disabled.
-  *         This parameter can be one of the @ref acmp_it_t.
-  * @param  state: New status
-  *           - ENABLE
-  *           - DISABLE
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state)
-{
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-	assert_param(IS_ACMP_IT_TYPE(it));
-	assert_param(IS_FUNC_STATE(state));
-
-	__LOCK(hperh);
-
-	if (state)
-		hperh->perh->IES |= it;
-	else
-		hperh->perh->IEC |= it;
-
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Checks whether the specified ACMP interrupt has occurred or not.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @param  flag: Specifies the ACMP interrupt source to check.
-  *         This parameter can be one of the @ref acmp_it_t.
-  * @retval it_status_t
-  *           - SET
-  *           - RESET
-  */
-it_status_t acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
-{
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-	assert_param(IS_ACMP_FLAG_TYPE(flag));
-
-	if (hperh->perh->RIF & flag) {
-		__UNLOCK(hperh);
-		return SET;
-	}
-
-	return RESET;
-}
-
-/** @brief  Clear the specified ACMP it flags.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @param  flag: specifies the it flag.
-  *         This parameter can be one of the @ref acmp_it_t.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
-{
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-	assert_param(IS_ACMP_FLAG_TYPE(flag));
-
-	__LOCK(hperh);
-	hperh->perh->IFC |= flag;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/** @brief  Set the specified acmp it flags.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified acmp module.
-  * @param  it: specifies the  it flag.
-  *         This parameter can be one of the @ref acmp_it_t.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t acmp_set_it_mask(acmp_handle_t *hperh, acmp_it_t it)
-{
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-	assert_param(IS_ACMP_IT_TYPE(it));
-
-	__LOCK(hperh);
-	hperh->perh->IFM |= it;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/** @brief  Check whether the specified ACMP flag is set or not.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @param  status: specifies the status to check.
-  *         This parameter can be one of the @ref acmp_status_t.
-  * @retval flag_status_t
-  *           - SET
-  *           - RESET
-  */
-flag_status_t acmp_get_status(acmp_handle_t *hperh, acmp_status_t status)
-{
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-	assert_param(IS_ACMP_STATUS_TYPE(status));
-
-	if (hperh->perh->STAT & status) {
-		__UNLOCK(hperh);
-		return SET;
-	}
-
-	return RESET;
-}
-/**
-  * @}
-  */
-
-/** @defgroup ACMP_Public_Functions_Group3 Output value functions
-  * @brief ACMP Output value functions
-  * @{
-  */
-
-/**
-  * @brief  This function handles ACMP interrupt request.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @retval None
-  */
-void acmp_irq_handle(acmp_handle_t *hperh)
-{
-	if (acmp_get_flag_status(hperh, ACMP_FLAG_WARMUP) == SET) {
-		if (hperh->acmp_warmup_cplt_cbk)
-			hperh->acmp_warmup_cplt_cbk(hperh);
-		acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP);
-	}
-
-	if (acmp_get_flag_status(hperh, ACMP_FLAG_EDGE) == SET) {
-		if (hperh->acmp_edge_cplt_cbk)
-			hperh->acmp_edge_cplt_cbk(hperh);
-		acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE);
-	}
-
-	return;
-}
-
-/**
-  * @brief  This function config acmp output.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @param  config: Pointer to a acmp_output_config_t structure that contains
-  *         the configutation information for acmp output.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config)
-{
-	if (hperh == NULL)
-		return ERROR;
-
-	if (config == NULL)
-		return ERROR;
-
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-	assert_param(IS_ACMP_INVERT_TYPE(config->gpio_inv));
-	assert_param(IS_ACMP_LOCATION_TYPE(config->location));
-	assert_param(IS_ACMP_OUT_FUNC_TYPE(config->out_func));
-
-	__LOCK(hperh);
-	hperh->perh->PORT = config->location;
-	hperh->perh->CON |= (config->gpio_inv << ACMP_CON_OUTINV_POS);
-	hperh->perh->PORT = config->out_func;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  This function output acmp result.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @retval output value.
-  */
-uint8_t acmp_out_result(acmp_handle_t *hperh)
-{
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-
-	return (READ_BIT(hperh->perh->STAT, ACMP_STAT_OUT_MSK) >> ACMP_STAT_OUT_POS);
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* ALD_ACMP */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_adc.c

@@ -1,1291 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ald_adc.c
-  * @brief   This file provides firmware functions to manage the following
-  *          functionalities of the Analog to Digital Convertor (ADC)
-  *          peripheral:
-  *           + Initialization functions
-  *             ++ Initialization and Configuration of ADC
-  *           + Operation functions
-  *             ++ Start, stop, get result of conversions of normal
-  *                group, using 3 possible modes: polling, interruption or DMA.
-  *           + Control functions
-  *             ++ Channels configuration on normal group
-  *             ++ Channels configuration on insert group
-  *             ++ Analog Watchdog configuration
-  *           + State functions
-  *             ++ ADC state machine management
-  *             ++ Interrupts and flags management
-  *
-  * @version V1.0
-  * @date    15 Dec 2017
-  * @author  AE Team.
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-
-#include "ald_cmu.h"
-#include "ald_adc.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup ADC ADC
-  * @brief ADC module driver
-  * @{
-  */
-
-#ifdef ALD_ADC
-
-/** @addtogroup ADC_Private_Functions
-  * @{
-  */
-#ifdef ALD_DMA
-static void adc_dma_normal_conv_cplt(void *arg);
-static void adc_dma_error(void *arg);
-#endif
-/**
-  * @}
-  */
-
-
-/** @defgroup ADC_Public_Functions ADC Public Functions
-  * @{
-  */
-
-/** @defgroup ADC_Public_Functions_Group1 Initialization functions
-  * @brief    Initialization and Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  Initializes the ADC peripheral and normal group according to
-  *         parameters specified in structure "adc_handle_t".
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t adc_init(adc_handle_t *hperh)
-{
-	ald_status_t tmp_status = OK;
-
-	if (hperh == NULL)
-		return ERROR;
-
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	assert_param(IS_ADC_DATA_ALIGN_TYPE(hperh->init.data_align));
-	assert_param(IS_ADC_SCAN_MODE_TYPE(hperh->init.scan_mode));
-	assert_param(IS_ADC_CLK_DIV_TYPE(hperh->init.clk_div));
-	assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.neg_ref));
-	assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.pos_ref));
-	assert_param(IS_ADC_CONV_RES_TYPE(hperh->init.conv_res));
-	assert_param(IS_ADC_NBR_OF_NM_TYPE(hperh->init.conv_nbr));
-	assert_param(IS_ADC_DISC_NBR_TYPE(hperh->init.disc_nbr));
-	assert_param(IS_FUNC_STATE(hperh->init.cont_mode));
-	assert_param(IS_FUNC_STATE(hperh->init.disc_mode));
-	assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_mode));
-	assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->nm_trig_mode));
-
-	if (hperh->state ==  ADC_STATE_RESET ) {
-		hperh->error_code = ADC_ERROR_NONE;
-		hperh->lock 	  = UNLOCK;
-	}
-
-	ADC_DISABLE(hperh);
-	hperh->state = ADC_STATE_BUSY_INTERNAL;
-	MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.data_align << ADC_CON1_ALIGN_POS);
-	MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.cont_mode << ADC_CON1_CM_POS);
-	MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan_mode << ADC_CON0_SCANEN_POS);
-	MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.conv_res << ADC_CON0_RSEL_POSS);
-
-	/* Enable discontinuous mode only if continuous mode is enabled */
-	if (hperh->init.disc_mode == ENABLE) {
-		if (hperh->init.cont_mode == ENABLE) {
-			SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK);
-			MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nbr << ADC_CON0_ETRGN_POSS);
-			MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.conv_nbr << ADC_CHSL_NSL_POSS);
-		}
-		else {
-			hperh->state 	  |= ADC_STATE_ERROR;
-			hperh->error_code |= ADC_ERROR_INTERNAL;
-			tmp_status 	   = ERROR;
-		}
-	}
-	else {
-		CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK);
-	}
-
-	if (hperh->init.scan_mode == ADC_SCAN_ENABLE)
-		MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.conv_nbr << ADC_CHSL_NSL_POSS);
-
-	if (hperh->init.cont_mode == ENABLE)
-		MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.conv_nbr << ADC_CHSL_NSL_POSS);
-
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS);
-	/* if the ADC CLK less than 1MHZ,PWRMOD should be Enable*/
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.clk_div << ADC_CCR_CKDIV_POSS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.neg_ref << ADC_CCR_VRNSEL_POS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.pos_ref << ADC_CCR_VRPSEL_POSS);
-	MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_mode << ADC_CON1_NCHESEL_POS);
-
-	if (hperh->nm_trig_mode != ADC_TRIG_SOFT)
-		pis_create(&hperh->reg_pis_handle);
-
-	if (tmp_status == OK) {
-		hperh->error_code = ADC_ERROR_NONE;
-		hperh->state 	 |= ADC_STATE_READY;
-		hperh->state 	 &= ~(ADC_STATE_ERROR | ADC_STATE_NM_BUSY
-				      | ADC_STATE_IST_BUSY | ADC_STATE_BUSY_INTERNAL);
-	}
-
-	adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE);
-	return tmp_status;
-}
-
-/**
-  * @brief  Deinitialize the ADC peripheral registers to their default reset
-  *         values.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t adc_reset(adc_handle_t *hperh)
-{
-	if (hperh == NULL)
-		return ERROR;
-
-	assert_param(IS_ADC_TYPE(hperh->perh));
-
-	ADC_DISABLE(hperh);
-
-	adc_clear_flag_status(hperh, ADC_FLAG_AWD);
-	adc_clear_flag_status(hperh, ADC_FLAG_NH);
-	adc_clear_flag_status(hperh, ADC_FLAG_IH);
-	adc_clear_flag_status(hperh, ADC_FLAG_OVR);
-	adc_clear_flag_status(hperh, ADC_FLAG_NHS);
-	adc_clear_flag_status(hperh, ADC_FLAG_IHS);
-
-	WRITE_REG(hperh->perh->CON0, 0x0);
-	WRITE_REG(hperh->perh->CON1, 0x0);
-	WRITE_REG(hperh->perh->CCR, 0x0);
-	WRITE_REG(hperh->perh->WDTH, 0xFFF);
-	WRITE_REG(hperh->perh->WDTL, 0x0);
-	WRITE_REG(hperh->perh->ICHOFF[0], 0x0);
-	WRITE_REG(hperh->perh->ICHOFF[1], 0x0);
-	WRITE_REG(hperh->perh->ICHOFF[2], 0x0);
-	WRITE_REG(hperh->perh->ICHOFF[3], 0x0);
-	WRITE_REG(hperh->perh->ICHS, 0x0);
-	WRITE_REG(hperh->perh->NCHS1, 0x0);
-	WRITE_REG(hperh->perh->NCHS2, 0x0);
-	WRITE_REG(hperh->perh->NCHS3, 0x0);
-	WRITE_REG(hperh->perh->NCHS4, 0x0);
-	WRITE_REG(hperh->perh->SMPT1, 0x0);
-	WRITE_REG(hperh->perh->SMPT2, 0x0);
-	WRITE_REG(hperh->perh->CHSL, 0x0);
-
-	if (hperh->nm_trig_mode != ADC_TRIG_SOFT)
-		pis_destroy(&hperh->reg_pis_handle);
-
-	if (hperh->ist_trig_mode != ADC_TRIG_SOFT)
-		pis_destroy(&hperh->inj_pis_handle);
-
-	hperh->state      = ADC_STATE_RESET;
-	hperh->error_code = ADC_ERROR_NONE;
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Public_Functions_Group2 IO operation functions
- *  @brief    Input and Output operation functions
- *  @{
- */
-
-/**
-  * @brief  Enables ADC, starts conversion of normal group.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t adc_normal_start(adc_handle_t *hperh)
-{
-	if (hperh == NULL)
-		return ERROR;
-
-	assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->nm_trig_mode));
-	assert_param(IS_ADC_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-	ADC_ENABLE(hperh);
-	hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC);
-	hperh->state |= ADC_STATE_NM_BUSY;
-	__UNLOCK(hperh);
-	adc_clear_flag_status(hperh, ADC_FLAG_NH);
-
-	if (hperh->nm_trig_mode == ADC_TRIG_SOFT)
-		SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK);
-
-	return OK;
-}
-
-/**
-  * @brief  Stop ADC conversion of normal group (and insert channels in
-  *         case of auto_injection mode), disable ADC peripheral.
-  * @note:  ADC peripheral disable is forcing stop of potential
-  *         conversion on insert group. If insert group is under use, it
-  *         should be preliminarily stopped using adc_insert_stop function.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t adc_normal_stop(adc_handle_t *hperh)
-{
-	assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->nm_trig_mode));
-	assert_param(IS_ADC_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-
-	ADC_DISABLE(hperh);
-	hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_NM_EOC);
-	hperh->state |=  ADC_STATE_READY;
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Wait for normal group conversion to be completed.
-  * @note   This function cannot be used in a particular setup: ADC configured  in DMA mode.
-  *         In this case, DMA resets the flag EOC and polling cannot be performed on each conversion.
-  * @note   When use this function,you should be pay attention to the hperh->init.reocs_mode,
-  *         if it is ADC_REOCS_MODE_ALL, it means the function will wait all normal rank conversion  finished.
-  *         if it is ADC_REOCS_MODE_ONE, it means the funcion will wait every normal rank conversion finished.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @param  timeout: Timeout value in millisecond.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout)
-{
-	uint32_t tickstart = 0;
-
-	assert_param(IS_ADC_TYPE(hperh->perh));
-
-	tickstart = __get_tick();
-	while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK))) {
-		if (timeout != ALD_MAX_DELAY ) {
-			if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) {
-				hperh->state |= ADC_STATE_TIMEOUT;
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-		}
-	}
-
-	adc_clear_flag_status(hperh, ADC_FLAG_NHS);
-	adc_clear_flag_status(hperh, ADC_FLAG_NH);
-
-	hperh->state |= ADC_STATE_NM_EOC;
-
-	if ((hperh->nm_trig_mode == ADC_TRIG_SOFT)
-		       && (hperh->init.cont_mode == DISABLE)
-	               && (hperh->init.scan_mode == ADC_SCAN_DISABLE)) {
-		hperh->state &= ~ADC_STATE_NM_BUSY;
-
-		if ((hperh->state & ADC_STATE_IST_BUSY) == 0)
-			hperh->state |= ADC_STATE_READY;
-	}
-	return OK;
-}
-
-/**
-  * @brief  Poll for conversion event.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @param  event_type: the ADC event type.
-  *          This parameter can be one of the following values:
-  *            ADC_awd_event: ADC Analog watchdog event.
-  * @param  timeout: Timeout value in millisecond.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout)
-{
-	uint32_t tickstart = 0;
-
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	assert_param(IS_ADC_EVENT_TYPE(event_type));
-
-	tickstart = __get_tick();
-
-	while (adc_get_flag_status(hperh, (adc_flag_t)event_type) == RESET) {
-		if (timeout != ALD_MAX_DELAY ) {
-			if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) {
-				hperh->state |= ADC_STATE_TIMEOUT;
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-		}
-	}
-
-	hperh->state |= ADC_STATE_AWD;
-	return OK;
-}
-
-/**
-  * @brief  Enables ADC, starts conversion of normal group with interruption.
-  *         Interruptions enabled in this function:
-  *          - REOC (end of conversion of normal group)
-  *         Each of these interruptions has its dedicated callback function.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t adc_normal_start_by_it(adc_handle_t *hperh)
-{
-	assert_param(IS_ADC_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-	ADC_ENABLE(hperh);
-	hperh->state 	 &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC);
-	hperh->state 	 |= ADC_STATE_NM_BUSY;
-	hperh->error_code = ADC_ERROR_NONE;
-
-	if (READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)) {
-		hperh->state &= ~(ADC_STATE_IST_EOC);
-		hperh->state |= ADC_STATE_IST_BUSY;
-	}
-
-	__UNLOCK(hperh);
-	adc_clear_flag_status(hperh, ADC_FLAG_NH);
-	adc_interrupt_config(hperh, ADC_IT_NH, ENABLE);
-
-	if (hperh->nm_trig_mode == ADC_TRIG_SOFT)
-		SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK);
-
-	return OK;
-}
-
-/**
-  * @brief  Stop ADC conversion of normal group (and insert group in
-  *         case of auto_injection mode), disable interrution of
-  *         end-of-conversion, disable ADC peripheral.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t adc_normal_stop_by_it(adc_handle_t *hperh)
-{
-	assert_param(IS_ADC_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-	ADC_DISABLE(hperh);
-	adc_interrupt_config(hperh, ADC_IT_NH, DISABLE);
-	hperh->state |= ADC_STATE_READY;
-	hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY);
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  Enables ADC, starts conversion of normal group and transfers result
-  *         through DMA.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @param  buf: The destination Buffer address.
-  * @param  size: The length of data to be transferred from ADC peripheral to memory.
-  * @param  channel: The DMA channel
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel)
-{
-	if ((hperh == NULL) || (buf == NULL) || (size == 0) || (channel > 5))
-		return ERROR;
-
-	assert_param(IS_ADC_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-	ADC_ENABLE(hperh);
-	hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC);
-	hperh->state |= ADC_STATE_NM_BUSY;
-
-	if (READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)) {
-		hperh->state &= ~(ADC_STATE_IST_EOC);
-		hperh->state |= ADC_STATE_IST_BUSY;
-	}
-
-	if ((hperh->state & ADC_STATE_IST_BUSY) != 0) {
-		hperh->state      &= ~(ADC_STATE_ERROR);
-		hperh->error_code &= ~(ADC_ERROR_OVR | ADC_ERROR_DMA);
-	}
-	else {
-		hperh->state     &= ~(ADC_STATE_ERROR);
-		hperh->error_code = ADC_ERROR_NONE;
-	}
-	__UNLOCK(hperh);
-
-	if (hperh->hdma.perh == NULL)
-		hperh->hdma.perh = DMA0;
-
-	hperh->hdma.cplt_cbk = adc_dma_normal_conv_cplt;
-	hperh->hdma.cplt_arg = hperh;
-	hperh->hdma.err_cbk  = adc_dma_error;
-	hperh->hdma.err_arg  = hperh;
-
-	dma_config_struct(&hperh->hdma.config);
-	hperh->hdma.config.src        = (void *)&hperh->perh->NCHDR;
-	hperh->hdma.config.dst        = (void *)buf;
-	hperh->hdma.config.size       = size;
-	hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD;
-	hperh->hdma.config.src_inc    = DMA_DATA_INC_NONE;
-	hperh->hdma.config.dst_inc    = DMA_DATA_INC_HALFWORD;
-	hperh->hdma.config.msel       = DMA_MSEL_ADC0;
-	hperh->hdma.config.msigsel    = DMA_MSIGSEL_ADC;
-	hperh->hdma.config.channel    = channel;
-	dma_config_basic(&hperh->hdma);
-
-	hperh->hpis.init.producer_src  = PIS_ADC1_REGULAT;
-	hperh->hpis.init.producer_clk  = PIS_CLK_PCLK2;
-	hperh->hpis.init.producer_edge = PIS_EDGE_NONE;
-	hperh->hpis.init.consumer_trig = PIS_CH7_DAC_CH0;
-	hperh->hpis.init.consumer_clk  = PIS_CLK_PCLK1;
- 	pis_create(&hperh->hpis);
-
-	if (hperh->nm_trig_mode == ADC_TRIG_SOFT)
-		SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK);
-
-	return OK;
-}
-
-/**
-  * @brief  Stop ADC conversion of normal group (and insert group in
-  *         case of auto_insert mode), disable ADC DMA transfer, disable
-  *         ADC peripheral.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t adc_stop_dma(adc_handle_t *hperh)
-{
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	__LOCK(hperh);
-
-	ADC_DISABLE(hperh);
-	pis_destroy(&hperh->hpis);
-	hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY);
-	hperh->state |= ADC_STATE_READY;
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  DMA transfer complete callback.
-  * @param  arg: argument of the call back.
-  * @retval None
-  */
-static void adc_dma_timer_trigger_cplt(void *arg)
-{
-	adc_timer_config_t *hperh = (adc_timer_config_t *)arg;
-
-	ADC_DISABLE(&hperh->lh_adc);
-	timer_base_stop(&hperh->lh_timer);
-	
-	__UNLOCK(hperh);
-	if (hperh->lh_adc.adc_reg_cplt_cbk != NULL)
-		hperh->lh_adc.adc_reg_cplt_cbk(&hperh->lh_adc);
-
-}
-
-
-/**
-  * @brief  Config Timer trigger adc function
-  * @param  config: Pointer to a adc_timer_config_t structure that
-  *         contains the configuration information for the specified function.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t adc_timer_trigger_adc_by_dma(adc_timer_config_t *config)
-{
-	__LOCK(config);
-
-	config->lh_pis.perh               = PIS;
-	config->lh_pis.init.producer_clk  = PIS_CLK_PCLK1;
-	config->lh_pis.init.producer_edge = PIS_EDGE_NONE;
-	config->lh_pis.init.consumer_clk  = PIS_CLK_PCLK1;
-	
-	if (config->p_timer == TIMER0)
-		config->lh_pis.init.producer_src  = PIS_TIMER0_UPDATA;
-	else if (config->p_timer == TIMER1)
-		config->lh_pis.init.producer_src  = PIS_TIMER1_UPDATA;
-	else if (config->p_timer == TIMER2)
-		config->lh_pis.init.producer_src  = PIS_TIMER2_UPDATA;
-	else if (config->p_timer == TIMER3)
-		config->lh_pis.init.producer_src  = PIS_TIMER3_UPDATA;
-	else
-		return ERROR;
-	
-	if (config->p_adc == ADC0)
-		config->lh_pis.init.consumer_trig = PIS_CH6_ADC0_NORMAL;
-	else if (config->p_adc == ADC1)
-		config->lh_pis.init.consumer_trig = PIS_CH0_ADC1_NORMAL;
-	else
-		return ERROR;
-
-	pis_create(&config->lh_pis);
-	
-	/* Initialize TIMER0 */
-	config->lh_timer.perh           = config->p_timer;
-	config->lh_timer.init.prescaler = 0;
-	config->lh_timer.init.mode      = TIMER_CNT_MODE_UP;
-	config->lh_timer.init.period    = ((cmu_get_pclk1_clock() / 1000000) * config->time);
-	config->lh_timer.init.clk_div   = TIMER_CLOCK_DIV1;
-	config->lh_timer.init.re_cnt    = 0;
-	timer_base_init(&config->lh_timer);
-
-	config->lh_adc.perh               = config->p_adc;
-	config->lh_adc.init.data_align    = ADC_DATAALIGN_RIGHT;
-	config->lh_adc.init.scan_mode     = ADC_SCAN_DISABLE;
-	config->lh_adc.init.cont_mode     = DISABLE;
-	config->lh_adc.init.conv_nbr      = ADC_NM_NBR_1;
-	config->lh_adc.init.disc_mode     = DISABLE;
-	config->lh_adc.init.disc_nbr      = ADC_DISC_NBR_1;
-	config->lh_adc.init.conv_res      = ADC_CONV_RES_12;
-	config->lh_adc.init.clk_div       = ADC_CKDIV_16;
-	config->lh_adc.init.nche_mode     = ADC_NCHESEL_MODE_ONE;
-	config->lh_adc.init.neg_ref       = config->n_ref;
-	config->lh_adc.init.pos_ref       = config->p_ref;
-	config->lh_adc.adc_reg_cplt_cbk   = config->adc_cplt_cbk;
-	config->lh_adc.adc_inj_cplt_cbk   = NULL;
-	config->lh_adc.adc_out_of_win_cbk = NULL;
-	config->lh_adc.adc_error_cbk      = NULL;
-	config->lh_adc.adc_ovr_cbk        = NULL;
-	adc_init(&config->lh_adc);
-
-	config->lnm_config.channel       = config->adc_ch;
-	config->lnm_config.rank          = ADC_NC_RANK_1;
-	config->lnm_config.sampling_time = ADC_SAMPLETIME_1;
- 	adc_normal_channel_config(&config->lh_adc, &config->lnm_config);
-	
-	config->lh_dma.cplt_cbk = adc_dma_timer_trigger_cplt;
-	config->lh_dma.cplt_arg = config;
-	config->lh_dma.err_cbk  = adc_dma_error;
-	config->lh_dma.err_arg  = &config->lh_adc;
-
-	dma_config_struct(&config->lh_dma.config);
-	config->lh_dma.perh              = DMA0;
-	config->lh_dma.config.src        = (void *)&config->lh_adc.perh->NCHDR;
-	config->lh_dma.config.dst        = (void *)config->buf;
-	config->lh_dma.config.size       = config->size;
-	config->lh_dma.config.data_width = DMA_DATA_SIZE_HALFWORD;
-	config->lh_dma.config.src_inc    = DMA_DATA_INC_NONE;
-	config->lh_dma.config.dst_inc    = DMA_DATA_INC_HALFWORD;
-	config->lh_dma.config.msel       = config->p_adc == ADC0? DMA_MSEL_ADC0 : DMA_MSEL_ADC1;
-	config->lh_dma.config.msigsel    = DMA_MSIGSEL_ADC;
-	config->lh_dma.config.channel    = config->dma_ch;
-	dma_config_basic(&config->lh_dma);
-	
-	ADC_ENABLE(&config->lh_adc);
-	timer_base_start(&config->lh_timer);
-
-	return OK;
-}
-#endif
-
-/**
-  * @brief  Get ADC normal group conversion result.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @retval ADC group normal conversion data
-  */
-uint32_t adc_normal_get_value(adc_handle_t *hperh)
-{
-	assert_param(IS_ADC_TYPE(hperh->perh));
-
-	hperh->state &= ~ADC_STATE_NM_EOC;
-	return hperh->perh->NCHDR;
-}
-
-/**
-  * @brief  Enables ADC, starts conversion of insert group.
-  *         Interruptions enabled in this function: None.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t adc_insert_start(adc_handle_t *hperh)
-{
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode));
-
-	__LOCK(hperh);
-	ADC_ENABLE(hperh);
-	hperh->state &= ~(ADC_STATE_READY | ADC_STATE_IST_EOC);
-	hperh->state |= ADC_STATE_IST_BUSY;
-
-	if ((hperh->state & ADC_STATE_NM_BUSY) == 0)
-		hperh->error_code = ADC_ERROR_NONE;
-
-	__UNLOCK(hperh);
-	adc_clear_flag_status(hperh, ADC_FLAG_IH);
-
-	if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) {
-		if (hperh->ist_trig_mode == ADC_TRIG_SOFT)
-			SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK);
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  Stop conversion of insert channels. Disable ADC peripheral if
-  *         no normal conversion is on going.
-  * @note   If ADC must be disabled and if conversion is on going on
-  *         normal group, function adc_normal_stop must be used to stop both
-  *         insert and normal groups, and disable the ADC.
-  * @note   If insert group mode auto-injection is enabled,
-  *         function adc_normal_stop must be used.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t adc_insert_stop(adc_handle_t *hperh)
-{
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode));
-
-	__LOCK(hperh);
-
-	if (((hperh->state & ADC_STATE_NM_BUSY) == 0)
-				&& (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))) {
-		ADC_DISABLE(hperh);
-		hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY | ADC_STATE_IST_EOC);
-		hperh->state |= ADC_STATE_READY;
-	}
-	else {
-		hperh->state |= ADC_STATE_ERROR;
-		__UNLOCK(hperh);
-		return ERROR;
-	}
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Wait for insert group conversion to be completed.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @param  timeout: Timeout value in millisecond.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout)
-{
-	uint32_t tickstart;
-
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode));
-
-	tickstart = __get_tick();
-
-	while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_ICHE_MSK))) {
-		if (timeout != ALD_MAX_DELAY) {
-			if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) {
-				hperh->state |= ADC_STATE_TIMEOUT;
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-		}
-	}
-
-	adc_clear_flag_status(hperh, ADC_FLAG_IHS);
-	adc_clear_flag_status(hperh, ADC_FLAG_IH);
-	adc_clear_flag_status(hperh, ADC_FLAG_NH);
-
-	hperh->state |= ADC_STATE_IST_EOC;
-
-	if (hperh->ist_trig_mode == ADC_TRIG_SOFT ) {
-		hperh->state &= ~(ADC_STATE_IST_BUSY);
-		if ((hperh->state & ADC_STATE_NM_BUSY) == 0)
-			hperh->state |= ADC_STATE_READY;
-	}
-
-	hperh->state &= ~(ADC_STATE_TIMEOUT);
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Enables ADC, starts conversion of insert group with interruption.
-  *          - JEOC (end of conversion of insert group)
-  *         Each of these interruptions has its dedicated callback function.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @retval Status, see @ref ald_status_t..
-  */
-ald_status_t adc_insert_start_by_it(adc_handle_t *hperh)
-{
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode));
-
-	__LOCK(hperh);
-	ADC_ENABLE(hperh);
-	hperh->state &= ~(ADC_STATE_READY | ADC_STATE_IST_EOC);
-	hperh->state |= ADC_STATE_IST_BUSY;
-
-	if ((hperh->state & ADC_STATE_NM_BUSY) == 0)
-		hperh->error_code = ADC_ERROR_NONE;
-
-	__UNLOCK(hperh);
-	adc_clear_flag_status(hperh, ADC_FLAG_IH);
-	adc_interrupt_config(hperh, ADC_IT_IH, ENABLE);
-
-	if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) {
-		if (hperh->ist_trig_mode == ADC_TRIG_SOFT)
-			SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK);
-	}
-	return OK;
-}
-
-/**
-  * @brief  Stop conversion of insert channels, disable interruption of
-  *         end-of-conversion. Disable ADC peripheral if no normal conversion
-  *         is on going.
-  * @note   If ADC must be disabled and if conversion is on going on
-  *         normal group, function adc_normal_stop must be used to stop both
-  *         insert and normal groups, and disable the ADC.
-  * @note   If insert group mode auto-injection is enabled,
-  *         function adc_normal_stop must be used.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @retval None
-  */
-ald_status_t adc_insert_stop_by_it(adc_handle_t *hperh)
-{
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode));
-
-	__LOCK(hperh);
-
-	if (((hperh->state & ADC_STATE_NM_BUSY) == 0)
-				&& (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))) {
-		ADC_DISABLE(hperh);
-		adc_interrupt_config(hperh, ADC_IT_IH, DISABLE);
-		hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY);
-		hperh->state |= ADC_STATE_READY;
-	}
-	else {
-		adc_interrupt_config(hperh, ADC_IT_IH, DISABLE);
-		hperh->state |= ADC_STATE_ERROR;
-		__UNLOCK(hperh);
-		return ERROR;
-	}
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Get ADC insert group conversion result.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @param  ih_rank: the converted ADC insert rank.
-  *          This parameter can be one of the following values:
-  *            @arg ADC_INJ_RANK_1: insert Channel1 selected
-  *            @arg ADC_INJ_RANK_2: insert Channel2 selected
-  *            @arg ADC_INJ_RANK_3: insert Channel3 selected
-  *            @arg ADC_INJ_RANK_4: insert Channel4 selected
-  * @retval ADC group insert conversion data
-  */
-uint32_t adc_insert_get_value(adc_handle_t *hperh, adc_ih_rank_t ih_rank)
-{
-	uint32_t tmp;
-
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	assert_param(IS_ADC_IH_RANK_TYPE(ih_rank));
-
-	switch (ih_rank) {
-	case ADC_IH_RANK_1:
-		tmp = hperh->perh->ICHDR[0];
-		break;
-	case ADC_IH_RANK_2:
-		tmp = hperh->perh->ICHDR[1];
-		break;
-	case ADC_IH_RANK_3:
-		tmp = hperh->perh->ICHDR[2];
-		break;
-	case ADC_IH_RANK_4:
-		tmp = hperh->perh->ICHDR[3];
-		break;
-	default:
-		break;
-	}
-
-	return tmp;
-}
-
-/**
-  * @brief  Handles ADC interrupt request
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @retval None
-  */
-void adc_irq_handler(adc_handle_t *hperh)
-{
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode));
-	assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->nm_trig_mode));
-
-	if (adc_get_it_status(hperh, ADC_IT_NH) && adc_get_flag_status(hperh, ADC_FLAG_NH)) {
-		if ((hperh->state & ADC_STATE_ERROR) == 0)
-			hperh->state |= ADC_STATE_NM_EOC;
-
-		if ((hperh->nm_trig_mode == ADC_TRIG_SOFT)
-			         && (hperh->init.cont_mode == DISABLE)) {
-			adc_interrupt_config(hperh, ADC_IT_NH, DISABLE);
-			hperh->state &= ~(ADC_STATE_NM_BUSY);
-
-			if ((hperh->state & ADC_STATE_IST_BUSY) == 0)
-				hperh->state |= ADC_STATE_READY;
-		}
-
-		if (hperh->adc_reg_cplt_cbk != NULL)
-			hperh->adc_reg_cplt_cbk(hperh);
-
-		adc_clear_flag_status(hperh, ADC_FLAG_NHS);
-		adc_clear_flag_status(hperh, ADC_FLAG_NH);
-	}
-
-	if (adc_get_it_status(hperh, ADC_IT_IH) && adc_get_flag_status(hperh, ADC_FLAG_IH)) {
-		if ((hperh->state & ADC_STATE_ERROR) == 0)
-			hperh->state |= ADC_STATE_IST_EOC;
-
-		if ((hperh->ist_trig_mode == ADC_TRIG_SOFT)
-			   || ((!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))
-		           && (hperh->nm_trig_mode == ADC_TRIG_SOFT)
-			   && (hperh->init.cont_mode == DISABLE))) {
-			adc_interrupt_config(hperh, ADC_IT_IH, DISABLE);
-			hperh->state &= ~(ADC_STATE_IST_BUSY);
-
-			if ((hperh->state & ADC_STATE_NM_BUSY) == 0)
-				hperh->state |= ADC_STATE_READY;
-		}
-		if (hperh->adc_inj_cplt_cbk != NULL)
-			hperh->adc_inj_cplt_cbk(hperh);
-
-		adc_clear_flag_status(hperh, ADC_FLAG_IHS);
-		adc_clear_flag_status(hperh, ADC_FLAG_IH);
-	}
-
-	if (adc_get_it_status(hperh, ADC_IT_AWD) && adc_get_flag_status(hperh, ADC_FLAG_AWD)) {
-		hperh->state |= ADC_STATE_AWD;
-
-		if (hperh->adc_out_of_win_cbk != NULL)
-			hperh->adc_out_of_win_cbk(hperh);
-
-		adc_clear_flag_status(hperh, ADC_FLAG_AWD);
-	}
-
-	if (adc_get_it_status(hperh, ADC_IT_OVR) && adc_get_flag_status(hperh, ADC_FLAG_OVR)) {
-		adc_clear_flag_status(hperh, ADC_FLAG_OVR);
-		hperh->error_code |= ADC_ERROR_OVR;
-		hperh->state      |= ADC_STATE_ERROR;
-
-		if (hperh->adc_ovr_cbk != NULL)
-			hperh->adc_ovr_cbk(hperh);
-	}
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Public_Functions_Group3 Peripheral Control functions
- *  @brief    Peripheral Control functions
- *  @{
- */
-
-/**
-  * @brief  Configures the the selected channel to be linked to the normal
-  *         group.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @param  config: Structure of ADC channel for normal group.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t adc_normal_channel_config(adc_handle_t *hperh, adc_channel_conf_t *config)
-{
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	assert_param(IS_ADC_CHANNELS_TYPE(config->channel));
-	assert_param(IS_ADC_NC_RANK_TYPE(config->rank));
-	assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->sampling_time));
-
-	__LOCK(hperh);
-
-	if (config->rank <= ADC_NC_RANK_4 ) {
-		hperh->perh->NCHS1 &= ~(0x1f <<  ((config->rank - 1) << 3));
-		hperh->perh->NCHS1 |= (config->channel << ((config->rank - 1) << 3));
-	}
-	else if (config->rank <= ADC_NC_RANK_8) {
-		hperh->perh->NCHS2 &= ~(0x1f <<  ((config->rank - 5) << 3));
-		hperh->perh->NCHS2 |= (config->channel << ((config->rank - 5) << 3));
-	}
-	else if (config->rank <= ADC_NC_RANK_12) {
-		hperh->perh->NCHS3 &= ~(0x1f <<  ((config->rank - 9) << 3));
-		hperh->perh->NCHS3 |= (config->channel << ((config->rank - 9) << 3));
-	}
-	else {
-		hperh->perh->NCHS4 &= ~(0x1f <<  ((config->rank - 13) << 3));
-		hperh->perh->NCHS4 |= (config->channel << ((config->rank - 13) << 3));
-	}
-
-	if (config->channel <= 15) {
-		hperh->perh->SMPT1 &=  ~(0x03 << (config->channel << 1));
-		hperh->perh->SMPT1 |= config->sampling_time << (config->channel << 1);
-	}
-	else {
-		hperh->perh->SMPT2 &=  ~(0x03 << ((config->channel - 16) << 1));
-		hperh->perh->SMPT2 |= config->sampling_time << ((config->channel - 16) << 1);
-	}
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Configures the the selected channel to be linked to the insert
-  *         group.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @param  config: Structure of ADC channel for insert group.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t adc_insert_channel_config(adc_handle_t *hperh, adc_ih_conf_t *config)
-{
-	uint8_t tmp1, tmp2;
-	ald_status_t tmp_status = OK;
-
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	assert_param(IS_ADC_CHANNELS_TYPE(config->channel));
-	assert_param(IS_ADC_IH_RANK_TYPE(config->rank));
-	assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp_time));
-	assert_param(IS_ADC_IST_OFFSET_TYPE(config->offset));
-	assert_param(IS_ADC_NBR_OF_IST_TYPE(config->nbr));
-	assert_param(IS_FUNC_STATE(config->disc_mode));
-	assert_param(IS_FUNC_STATE(config->auto_inj));
-	assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode));
-
-	__LOCK(hperh);
-
-	if (hperh->init.scan_mode == ADC_SCAN_DISABLE) {
-		switch (config->rank) {
-		case ADC_IH_RANK_1:
-			MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS1_MSK, config->channel << ADC_ICHS_IS1_POSS);
-			break;
-		case ADC_IH_RANK_2:
-			MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS2_MSK, config->channel << ADC_ICHS_IS1_POSS);
-			break;
-		case ADC_IH_RANK_3:
-			MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS3_MSK, config->channel << ADC_ICHS_IS1_POSS);
-			break;
-		case ADC_IH_RANK_4:
-			MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS4_MSK, config->channel << ADC_ICHS_IS1_POSS);
-			break;
-		default:
-			hperh->state      |= ADC_STATE_ERROR;
-			hperh->error_code |= ADC_ERROR_INTERNAL;
-			tmp_status         = ERROR;
-			break;
-		}
-	}
-	else {
-		MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nbr << ADC_CHSL_ISL_POSS);
-		tmp1 = config->rank ;
-		tmp2 = config->nbr;
-
-		if (tmp1 <= tmp2) {
-			hperh->perh->ICHS &= ~(0x1f << ((tmp1 - 1) << 3));
-			hperh->perh->ICHS |= config->channel
-			                                  << ((tmp1 - 1) << 3);
-		}
-		else {
-			hperh->perh->ICHS &= ~(0x1f << ((tmp1 - 1) << 3));
-		}
-	}
-
-	if (config->auto_inj == ENABLE) {
-		if (hperh->ist_trig_mode == ADC_TRIG_SOFT) {
-			SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK);
-		}
-		else {
-			hperh->state      |= ADC_STATE_ERROR;
-			hperh->error_code |= ADC_ERROR_INTERNAL;
-			tmp_status         = ERROR;
-		}
-	}
-
-	if (config->disc_mode == ENABLE) {
-		if (config->auto_inj == DISABLE) {
-			MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nbr << ADC_CHSL_ISL_POSS);
-			SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK);
-		}
-		else {
-			hperh->state      |= ADC_STATE_ERROR;
-			hperh->error_code |= ADC_ERROR_INTERNAL;
-			tmp_status         = ERROR;
-		}
-	}
-
-	if (config->channel <= 15) {
-		hperh->perh->SMPT1 &=  ~(0x03 << (config->channel << 1));
-		hperh->perh->SMPT1 |= config->samp_time << (config->channel << 1);
-	}
-	else {
-		hperh->perh->SMPT2 &=  ~(0x03 << ((config->channel - 16) << 1));
-		hperh->perh->SMPT2 |= config->samp_time << ((config->channel - 16) << 1);
-	}
-
-	switch (config->rank) {
-	case ADC_IH_RANK_1:
-		hperh->perh->ICHOFF[0] = config->offset;
-		break;
-	case ADC_IH_RANK_2:
-		hperh->perh->ICHOFF[1] = config->offset;
-		break;
-	case ADC_IH_RANK_3:
-		hperh->perh->ICHOFF[2] = config->offset;
-		break;
-	case ADC_IH_RANK_4:
-		hperh->perh->ICHOFF[3] = config->offset;
-		break;
-	default:
-		break;
-	}
-
-	if (hperh->ist_trig_mode != ADC_TRIG_SOFT)
-		pis_create(&hperh->inj_pis_handle);
-
-	__UNLOCK(hperh);
-	return tmp_status;
-}
-
-/**
-  * @brief  Configures the analog watchdog.
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @param  config: Structure of ADC analog watchdog configuration
-  * @retval ALD status
-  */
-ald_status_t adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config)
-{
-
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	assert_param(IS_ADC_ANALOG_WTD_MODE_TYPE(config->watchdog_mode));
-	assert_param(IS_FUNC_STATE(config->it_mode));
-	assert_param(IS_HTR_TYPE(config->high_threshold));
-	assert_param(IS_LTR_TYPE(config->low_threshold));
-
-	__LOCK(hperh);
-
-	if ((config->watchdog_mode == ADC_ANAWTD_SING_NM)
-		|| (config->watchdog_mode == ADC_ANAWTD_SING_IST)
-	        || (config->watchdog_mode == ADC_ANAWTD_SING_NMIST))
-		assert_param(IS_ADC_CHANNELS_TYPE(config->channel));
-
-	if (config->it_mode == DISABLE)
-		adc_interrupt_config(hperh, ADC_IT_AWD, DISABLE);
-	else
-		adc_interrupt_config(hperh, ADC_IT_AWD, ENABLE);
-
-	CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHWDTEN_MSK);
-	CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHWDEN_MSK);
-	CLEAR_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK);
-	hperh->perh->CON0 |= config->watchdog_mode;
-
-	if (READ_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK))
-		MODIFY_REG(hperh->perh->CON0, ADC_CON0_AWDCH_MSK, config->channel << ADC_CON0_AWDCH_POSS);
-
-	WRITE_REG(hperh->perh->WDTL, config->low_threshold);
-	WRITE_REG(hperh->perh->WDTH, config->high_threshold);
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Enables or disables the specified ADC interrupts.
-  * @param  hperh: Pointer to a adc_handle_t structure.
-  * @param  it: Specifies the ADC interrupt sources to be enabled or disabled.
-  *         This parameter can be one of the @ref adc_it_t.
-  * @param  state: New status
-  *           - ENABLE
-  *           - DISABLE
-  * @retval None
-  */
-void adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state)
-{
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	assert_param(IS_ADC_IT_TYPE(it));
-	assert_param(IS_FUNC_STATE(state));
-
-	if (state == ENABLE)
-		SET_BIT(hperh->perh->CON0, it);
-	else
-		CLEAR_BIT(hperh->perh->CON0, it);
-
-	return;
-}
-
-/**
-  * @brief  Checks whether the specified ADC interrupt has occurred or not.
-  * @param  hperh: Pointer to a adc_handle_t structure.
-  * @param  it: Specifies the ADC interrupt source to check.
-  *         This parameter can be one of the @ref adc_it_t.
-  * @retval Status
-  *           - SET
-  *           - RESET
-  */
-it_status_t adc_get_it_status(adc_handle_t *hperh, adc_it_t it)
-{
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	assert_param(IS_ADC_IT_TYPE(it));
-
-	if (READ_BIT(hperh->perh->CON0, it))
-		return SET;
-
-	return RESET;
-}
-
-/** @brief  Check whether the specified ADC flag is set or not.
-  * @param  hperh: Pointer to a adc_handle_t structure.
-  * @param  flag: specifies the flag to check.
-  *         This parameter can be one of the @ref adc_flag_t.
-  * @retval Status
-  *           - SET
-  *           - RESET
-  */
-flag_status_t adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag)
-{
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	assert_param(IS_ADC_FLAGS_TYPE(flag));
-
-	if (READ_BIT(hperh->perh->STAT, flag))
-		return SET;
-
-	return RESET;
-}
-
-/** @brief  Clear the specified ADC pending flags.
-  * @param  hperh: Pointer to a adc_handle_t structure.
-  * @param  flag: specifies the flag to check.
-  *         This parameter can be one of the @ref adc_flag_t.
-  * @retval None
-  */
-void adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag)
-{
-	assert_param(IS_ADC_TYPE(hperh->perh));
-	assert_param(IS_ADC_FLAGS_TYPE(flag));
-
-	WRITE_REG(hperh->perh->CLR, flag);
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Public_Functions_Group4 Peripheral State functions
- *  @brief    Peripheral State functions
- *  @{
- */
-
-/**
-  * @brief  return the ADC state
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @retval state
-  */
-uint32_t adc_get_state(adc_handle_t *hperh)
-{
-	return hperh->state;
-}
-
-/**
-  * @brief  Return the ADC error code
-  * @param  hperh: Pointer to a adc_handle_t structure that contains
-  *         the configuration information for the specified ADC module.
-  * @retval ADC Error Code
-  */
-uint32_t adc_get_error(adc_handle_t *hperh)
-{
-	return hperh->error_code;
-}
-
-/**
-  *@}
-  */
-
-/**
-  *@}
-  */
-
-/** @defgroup ADC_Private_Functions ADC Private Functions
-  * @{
-  */
-
-#ifdef ALD_DMA
-/**
-  * @brief  DMA transfer complete callback.
-  * @param  arg: argument of the call back.
-  * @retval None
-  */
-static void adc_dma_normal_conv_cplt(void *arg)
-{
-	adc_handle_t *hperh = (adc_handle_t *)arg;
-
-	if (hperh->adc_reg_cplt_cbk != NULL)
-		hperh->adc_reg_cplt_cbk(hperh);
-
-}
-
-/**
-  * @brief  DMA error callback
-  * @param  arg: argument of the call back.
-  * @retval None
-  */
-static void adc_dma_error(void *arg)
-{
-	adc_handle_t *hperh = (adc_handle_t *)arg;
-	hperh->state       |= ADC_STATE_ERROR;
-	hperh->error_code  |= ADC_ERROR_DMA;
-
-	if (hperh->adc_error_cbk != NULL)
-		hperh->adc_error_cbk(hperh);
-}
-#endif
-/**
-  *@}
-  */
-
-#endif /* ALD_ADC */
-
-/**
-  *@}
-  */
-
-/**
-  *@}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_cmu.c

@@ -1,1065 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_cmu.c
-  * @brief   CMU module driver.
-  *
-  * @version V1.0
-  * @date    22 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  * @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-     *** System clock configure ***
-     =================================
-     [..]
-       (+) If you don't change system clock, you can using cmu_clock_config_default() API.
-           It will select HRC as system clock. The system clock is 24MHz.
-       (+) If you want to change system clock, you can using cmu_clock_config() API.
-           You can select one of the following as system clock:
-             @ref CMU_CLOCK_HRC   2MHz or 24MHz
-             @ref CMU_CLOCK_LRC   32768Hz
-             @ref CMU_CLOCK_LOSC  32768Hz
-             @ref CMU_CLOCK_PLL1  32MHz, 48MHz or (32768*1024)Hz
-             @ref CMU_CLOCK_HOSC  1MHz -- 24MHz
-       (+) If you select CMU_CLOCK_PLL1 as system clock, it must config the PLL1
-           using cmu_pll1_config() API. The input of clock must be 4MHz or PLL2.
-       (+) If you get current clock, you can using cmu_get_clock() API.
-
-     *** BUS division control ***
-     ===================================
-
-     PLCK            sys_clk                     hclk1
-     -------DIV_SYS-----------+------DIV_AHB1------------Peripheral(GPIO, CRC, ... etc.)
-                              |
-                              |                  pclk1
-                              +------DIV_APB1------------Peripheral(TIM, UART, ... etc.)
-                              |
-                              |                  pclk2
-                              +------DIV_APB2------------Peripheral(ADC, WWDT, ... etc.)
-
-     [..]
-       (+) Configure the division using cmu_div_config() API.
-       (+) Get sys_clk using cmu_get_sys_clock() API.
-       (+) Get hclk1 using cmu_get_hclk1_clock() API.
-       (+) Get pclk1 using cmu_get_pclk1_clock() API.
-       (+) Get pclk2 using cmu_get_pclk2_clock() API.
-
-     *** Clock safe configure ***
-     ===================================
-     [..]
-       (+) If you select CMU_CLOCK_HOSC as system clock, you need enable
-           clock safe using cmu_hosc_safe_config() API. It will change
-           CMU_CLOCK_HRC as system clock, when the outer crystal stoped.
-       (+) If you select CMU_CLOCK_LOSC as system clock, you need enable
-           clock safe using cmu_losc_safe_config() API. It will change
-           CMU_CLOCK_LRC as system clock, when the outer crystal stoped.
-       (+) If you select CMU_CLOCK_PLL1 as system clock, you need enable
-           clock safe using cmu_pll_safe_config() API. It will change
-           CMU_CLOCK_HRC as system clock, when the pll1 is lose.
-       (+) The cmu_irq_cbk() will be invoked, when CMU interrupt has
-           been occurred. You can overwrite this function in application.
-
-     *** Clock output configure ***
-     ===================================
-     [..]
-       (+) Output high-speed clock using cmu_output_high_clock_config() API.
-       (+) Output low-speed clock using cmu_output_low_clock_config() API.
-
-     *** Peripheral clock configure ***
-     ===================================
-     [..]
-       (+) Configure buzz clock using cmu_buzz_config() API.
-       (+) Selected lptim0 clock using cmu_lptim0_clock_select() API.
-       (+) Selected lpuart clock using cmu_lpuart0_clock_select() API.
-       (+) Selected lcd clock using cmu_lcd_clock_select() API.
-       (+) Enable/Disable peripheral clock using cmu_perh_clock_config() API.
-
-     *** CMU ALD driver macros list ***
-     =============================================
-     [..]
-       Below the list of most used macros in CMU driver.
-
-      (+) CMU_LOSC_ENABLE():     Enable outer low crystal(32768Hz).
-      (+) CMU_LOSC_DISABLE():    Disable outer low crystal(32768Hz).
-      (+) CMU_LRC_ENABLE():      Enable LRC(32768Hz).
-      (+) CMU_LRC_DISABLE():     Disable LRC(32768Hz).
-      (+) CMU_ULRC_ENABLE():     Enable ULRC(10KHz).
-      (+) CMU_ULRC_DISABLE():    Disable ULRC(10KHz).
-      (+) CMU_LP_LRC_ENABLE():   Enable low power LRC(32768Hz).
-      (+) CMU_LP_LRC_DISABLE():  Disable low power LRC(32768Hz).
-      (+) CMU_LP_LOSC_ENABLE():  Enable low power LOSC(32768Hz).
-      (+) CMU_LP_LOSC_DISABLE(): Disable low power LOSC(32768Hz).
-      (+) CMU_LP_HRC_ENABLE():   Enable low power HRC(2MHz or 24MHz).
-      (+) CMU_LP_HRC_DISABLE():  Disable low power HRC(2MHz OR 24MHz).
-      (+) CMU_LP_HOSC_ENABLE():  Enable low power HOSC(1MHz -- 24MHz).
-      (+) CMU_LP_HOSC_DISABLE(): Disable low power HOSC(1MHz -- 24MHz).
-
-     [..]
-      (@) You can refer to the CMU driver header file for used the macros
-
-  @endverbatim
-  ******************************************************************************
-  */
-
-#include "ald_cmu.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup CMU CMU
-  * @brief CMU module driver
-  * @{
-  */
-
-/**
-  * @defgroup CMU_Private_Variables CMU Private Variables
-  * @{
-  */
-uint32_t __system_clock  = 24000000;
-/**
-  * @}
-  */
-
-/** @defgroup CMU_Private_Functions CMU Private Functions
-  * @{
-  */
-
-/**
-  * @brief  Update the current system clock. This function
-  *         will be invoked, when system clock has changed.
-  * @param  clock: The new clock.
-  * @retval None
-  */
-
-static void cmu_clock_update(uint32_t clock)
-{
-	__system_clock = clock;
-
-	if (clock > 1000000)
-		__init_tick(TICK_INT_PRIORITY);
-
-	return;
-}
-
-/**
-  * @brief  CMU module interrupt handler
-  * @retval None
-  */
-void CMU_Handler(void)
-{
-	/* HOSC stop */
-	if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) {
-		SYSCFG_UNLOCK();
-		SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK);
-		SYSCFG_LOCK();
-
-		if ((READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK))
-				&& ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1)
-				|| ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))))
-			cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000);
-		cmu_irq_cbk(CMU_HOSC_STOP);
-	}
-	
-	/* HOSC start */
-	if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK)) {
-		SYSCFG_UNLOCK();
-		SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK);
-		SYSCFG_LOCK();
-
-		if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK))
-				&& ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))
-			cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 1000000);
-		cmu_irq_cbk(CMU_HOSC_START);
-	}
-
-	/* LOSC stop */
-	if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK)) {
-		SYSCFG_UNLOCK();
-		SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK);
-		SYSCFG_LOCK();
-		cmu_irq_cbk(CMU_LOSC_STOP);
-	}
-	
-	/* LOSC start */
-	if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIE_MSK)) {
-		SYSCFG_UNLOCK();
-		SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK);
-		SYSCFG_LOCK();
-		cmu_irq_cbk(CMU_LOSC_START);
-	}
-
-	/* PLL1 lose */
-	if (READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK) && READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK)) {
-		SYSCFG_UNLOCK();
-		SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK);
-		SYSCFG_LOCK();
-
-		if (READ_BIT(CMU->PULMCR, CMU_PULMCR_CLKS_MSK)
-				&& ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1)
-				|| ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))))
-			cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000);
-		cmu_irq_cbk(CMU_PLL1_UNLOCK);
-	}
-
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup CMU_Public_Functions CMU Public Functions
-  * @{
-  */
-
-/** @defgroup CMU_Public_Functions_Group1 System clock configuration
-  * @brief    System clock configuration functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### System clock Configuration functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure system clock using default parameters.
-      (+) Configure system clock using specified parameters.
-      (+) Configure PLL1 using specified parameters.
-      (+) Get system clock.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure system clock using default.
-  *         Select CMU_CLOCK_HRC(24MHz) as system clock and
-  *         enable CMU_CLOCK_LRC(32768Hz).
-  * @retval The status of ALD.
-  */
-ald_status_t cmu_clock_config_default(void)
-{
-	uint32_t cnt = 4000, tmp;
-
-	SYSCFG_UNLOCK();
-
-	/* Select HRC */
-	MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS);
-	while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
-
-	if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) {
-		SYSCFG_LOCK();
-		return ERROR;
-	}
-
-	CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK);	/* Select 24Mhz */
-
-	tmp = READ_REG(CMU->CLKENR);
-	/* Enable HRC/LRC/LOSC */
-	SET_BIT(tmp, CMU_CLKENR_HRCEN_MSK | CMU_CLKENR_LRCEN_MSK | CMU_CLKENR_LOSCEN_MSK);
-	WRITE_REG(CMU->CLKENR, tmp);
-
-	SYSCFG_LOCK();
-	return OK;
-}
-
-/**
-  * @brief  Configure system clock using specified parameters
-  * @param  clk: The parameter can be one of the following:
-  *           @arg @ref CMU_CLOCK_HRC  2MHz or 24MHz
-  *           @arg @ref CMU_CLOCK_LRC  32768Hz
-  *           @arg @ref CMU_CLOCK_LOSC 32768Hz
-  *           @arg @ref CMU_CLOCK_PLL1 32MHz, 48MHz or (32768*1024)Hz
-  *           @arg @ref CMU_CLOCK_HOSC 1MHz -- 24MHz
-  * @param  clock: The clock which will be set. the value depends
-  *         on the parameter of clk.
-  * @retval The status of ALD.
-  */
-ald_status_t cmu_clock_config(cmu_clock_t clk, uint32_t clock)
-{
-	uint32_t cnt = 4000;
-
-	assert_param(IS_CMU_CLOCK(clk));
-	SYSCFG_UNLOCK();
-
-	switch (clk) {
-	case CMU_CLOCK_HRC:
-		assert_param(clock == 24000000 || clock == 2000000);
-
-		MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS);
-		while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
-
-		if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) {
-			SYSCFG_LOCK();
-			return ERROR;
-		}
-
-		if (clock == 24000000)
-			CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK);
-		else
-			SET_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK);
-
-		SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK);
-
-		for (cnt = 4000; cnt; --cnt);
-		cnt = 4000;
-		while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCACT_MSK))) && (--cnt));
-		cnt = 4000;
-		while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCRDY_MSK))) && (--cnt));
-
-		cmu_clock_update(clock);
-		break;
-
-	case CMU_CLOCK_LRC:
-		/* Close SysTick interrupt in lower clock */
-		SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
-
-		MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS);
-		while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
-
-		if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC) {
-			SYSCFG_LOCK();
-			return ERROR;
-		}
-
-		SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);
-
-		cnt = 4000;
-		while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCACT_MSK))) && (--cnt));
-		cnt = 4000;
-		while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt));
-
-		cmu_clock_update(32768);
-		break;
-
-	case CMU_CLOCK_LOSC:
-		/* Close SysTick interrupt in lower clock */
-		SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
-
-		MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LOSC << CMU_CSR_SYS_CMD_POSS);
-		while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
-
-		if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC) {
-			SYSCFG_LOCK();
-			return ERROR;
-		}
-
-		SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);
-
-		cnt = 4000;
-		while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCACT_MSK))) && (--cnt));
-		cnt = 4000;
-		while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCRDY_MSK))) && (--cnt));
-
-		cmu_clock_update(32768);
-		break;
-
-	case CMU_CLOCK_PLL1:
-		MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS);
-		while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
-
-		if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1) {
-			SYSCFG_LOCK();
-			return ERROR;
-		}
-
-		SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK);
-
-		for (cnt = 4000; cnt; --cnt);
-		cnt = 4000;
-		while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1ACT_MSK))) && (--cnt));
-		cnt = 4000;
-		while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt));
-
-		cmu_clock_update(clock);
-		break;
-
-	case CMU_CLOCK_HOSC:
-		assert_param(clock <= 24000000);
-
-		MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS);
-		while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
-
-		if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC) {
-			SYSCFG_LOCK();
-			return ERROR;
-		}
-
-		SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK);
-		MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1);
-
-		for (cnt = 4000; cnt; --cnt);
-		cnt = 4000;
-		while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt));
-		cnt = 4000;
-		while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt));
-
-		cmu_clock_update(clock);
-		break;
-
-	default:
-		break;
-	}
-
-	SYSCFG_LOCK();
-	return OK;
-}
-
-
-
-/**
-  * @brief  Configure PLL1 using specified parameters.
-  * @param  input: The input clock type.
-  * @param  output: The output clock which can be 32MHz or 48MHz.
-  *           When input = CMU_PLL1_INPUT_PLL2; then output must be
-  *           CMU_PLL1_OUTPUT_32M, and then the real clock is (32768x1024)Hz.
-  * @retval None
-  */
-void cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output)
-{
-	uint32_t cnt = 4000;
-
-	assert_param(IS_CMU_PLL1_INPUT(input));
-	assert_param(IS_CMU_PLL1_OUTPUT(output));
-
-	SYSCFG_UNLOCK();
-
-	if (input == CMU_PLL1_INPUT_HRC_6) {
-		SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK);
-	}
-	else if (input == CMU_PLL1_INPUT_PLL2) {
-		SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);
-		CLEAR_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2RFS_MSK);
-		SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK);
-	}
-	else {
-		SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK);
-	}
-
-	MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1RFS_MSK, input << CMU_PLLCFG_PLL1RFS_POSS);
-	MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1OS_MSK, output << CMU_PLLCFG_PLL1OS_POS);
-	SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK);
-
-	while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL1LCKN_MSK)) && (--cnt));
-	cnt = 4000;
-	while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt));
-
-	SYSCFG_LOCK();
-	return;
-}
-
-/**
-  * @brief  Gets current system clock.
-  * @retval The value of system clock.
-  */
-uint32_t cmu_get_clock(void)
-{
-	return __system_clock;
-}
-
-/**
-  * @brief  Automatic-calibrate internal clock.
-  * @param  input: input type: HOSC or LOSC.
-  * @param  freq: output frequency: 24MHz or 2MHz.
-  * @retval The result:
-  *           - 0  Success
-  *           - -1 Failed
-  */
-int32_t cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output_t freq)
-{
-	uint32_t cnt = 5000, tmp;
-
-	assert_param(IS_CMU_AUTO_CALIB_INPUT(input));
-	assert_param(IS_CMU_AUTO_CALIB_OUTPUT(freq));
-
-	SYSCFG_UNLOCK();
-
-	tmp = READ_REG(CMU->HRCACR);
-
-	MODIFY_REG(tmp, CMU_HRCACR_AC_MSK, 1 << CMU_HRCACR_AC_POSS);
-	MODIFY_REG(tmp, CMU_HRCACR_RFSEL_MSK, input << CMU_HRCACR_RFSEL_POS);
-	MODIFY_REG(tmp, CMU_HRCACR_FREQ_MSK, freq << CMU_HRCACR_FREQ_POS);
-	SET_BIT(tmp, CMU_HRCACR_EN_MSK);
-	WRITE_REG(CMU->HRCACR, tmp);
-
-	while (cnt--);
-	cnt = 30000;
-	while ((READ_BIT(CMU->HRCACR, CMU_HRCACR_BUSY_MSK)) && (--cnt));
-
-	if (READ_BITS(CMU->HRCACR, CMU_HRCACR_STA_MSK, CMU_HRCACR_STA_POSS) != 1) {
-		CLEAR_BIT(CMU->HRCACR, CMU_HRCACR_EN_MSK);
-		SYSCFG_LOCK();
-		return -1;
-	}
-
-	SET_BIT(CMU->HRCACR, CMU_HRCACR_WRTRG_MSK);
-	CLEAR_BIT(CMU->HRCACR, CMU_HRCACR_EN_MSK);
-	SYSCFG_LOCK();
-
-	return 0;
-}
-/**
-  * @}
-  */
-
-/** @defgroup CMU_Public_Functions_Group2 BUS division control
-  * @brief    BUS division control functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### BUS division control functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure the bus division.
-      (+) Get ahb1 clock.
-      (+) Get sys bus clock.
-      (+) Get apb1 clock.
-      (+) Get apb2 clock.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure the bus division.
-  * @param  bus: The type of bus:
-  *          @arg CMU_HCLK_1
-  *          @arg CMU_SYS
-  *          @arg CMU_PCLK_1
-  *          @arg CMU_PCLK_2
-  * @param  div: The value of divider.
-  * @retval None
-  */
-void cmu_div_config(cmu_bus_t bus, cmu_div_t div)
-{
-	assert_param(IS_CMU_BUS(bus));
-	assert_param(IS_CMU_DIV(div));
-
-	SYSCFG_UNLOCK();
-
-	switch (bus) {
-	case CMU_HCLK_1:
-		MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS);
-		break;
-
-	case CMU_SYS:
-		MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS);
-		break;
-
-	case CMU_PCLK_1:
-		MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS);
-		break;
-
-	case CMU_PCLK_2:
-		MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, div << CMU_CFGR_PCLK2DIV_POSS);
-		break;
-
-	default:
-		break;
-	}
-
-	SYSCFG_LOCK();
-	return;
-}
-
-/**
-  * @brief  Get AHB1 clock.
-  * @retval The value of AHB1 clock.
-  */
-uint32_t cmu_get_hclk1_clock(void)
-{
-	uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS);
-	uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, CMU_CFGR_HCLK1DIV_POSS);
-
-	return (__system_clock >> sys_div) >> ahb_div;
-}
-
-/**
-  * @brief  Get SYS clock
-  * @retval The value of SYS clock
-  */
-uint32_t cmu_get_sys_clock(void)
-{
-	uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS);
-
-	return __system_clock >> sys_div;
-}
-
-/**
-  * @brief  Get APB1 clock.
-  * @retval The value of APB1 clock.
-  */
-uint32_t cmu_get_pclk1_clock(void)
-{
-	uint32_t sys_div  = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS);
-	uint32_t apb1_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, CMU_CFGR_PCLK1DIV_POSS);
-
-	return (__system_clock >> sys_div) >> apb1_div;
-}
-
-/**
-  * @brief  Get APB2 clock.
-  * @retval The value of APB2 clock.
-  */
-uint32_t cmu_get_pclk2_clock(void)
-{
-	uint32_t sys_div  = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS);
-	uint32_t apb2_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, CMU_CFGR_PCLK2DIV_POSS);
-
-	return (__system_clock >> sys_div) >> apb2_div;
-}
-/**
-  * @}
-  */
-
-/** @defgroup CMU_Public_Functions_Group3 Clock safe configure
-  * @brief    Clock safe configure functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### Clock safe configure functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Enable/Disable outer high crystal safe mode.
-      (+) Enable/Disable outer low crystal safe mode.
-      (+) Enable/Disable PLL1 safe mode.
-      (+) Interrupt callback function.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enable/Disable outer high crystal safe mode.
-  * @param  clock: the value of outer crystal frequency.
-  * @param  status: The new status.
-  * @retval None
-  */
-void cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status)
-{
-	assert_param(IS_CMU_HOSC_RANGE(clock));
-	assert_param(IS_FUNC_STATE(status));
-
-	SYSCFG_UNLOCK();
-
-	if (status) {
-		SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK);
-		MODIFY_REG(CMU->HOSMCR, CMU_HOSMCR_FRQS_MSK, clock << CMU_HOSMCR_FRQS_POSS);
-		SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK);
-		SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK);
-
-		mcu_irq_config(CMU_IRQn, 3, ENABLE);
-	}
-	else {
-		CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK);
-		CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK);
-
-		if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0)
-			mcu_irq_config(CMU_IRQn, 3, DISABLE);
-	}
-
-	SYSCFG_LOCK();
-	return;
-}
-
-/**
-  * @brief  Enable/Disable outer low crystal safe mode.
-  * @param  status: The new status.
-  * @retval None
-  */
-void cmu_losc_safe_config(type_func_t status)
-{
-	assert_param(IS_FUNC_STATE(status));
-	SYSCFG_UNLOCK();
-
-	if (status) {
-		SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK);
-		SET_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK);
-		SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK);
-
-		mcu_irq_config(CMU_IRQn, 3, ENABLE);
-	}
-	else {
-		CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK);
-		CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK);
-
-		if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0)
-			mcu_irq_config(CMU_IRQn, 3, DISABLE);
-	}
-
-	SYSCFG_LOCK();
-	return;
-}
-
-/**
-  * @brief  Enable/Disable PLL1 safe mode.
-  * @param  status: The new status.
-  * @retval None
-  */
-void cmu_pll_safe_config(type_func_t status)
-{
-	assert_param(IS_FUNC_STATE(status));
-	SYSCFG_UNLOCK();
-
-	if (status) {
-		SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK);
-		MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS);
-		SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK);
-		SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK);
-
-		mcu_irq_config(CMU_IRQn, 3, ENABLE);
-	}
-	else {
-		CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK);
-		CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK);
-
-		if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0)
-			mcu_irq_config(CMU_IRQn, 3, DISABLE);
-	}
-
-	SYSCFG_LOCK();
-	return;
-}
-
-/**
-  * @brief  Get clock state.
-  * @param  sr: The state type, see @ref cmu_clock_state_t.
-  * @retval SET/RESET
-  */
-flag_status_t cmu_get_clock_state(cmu_clock_state_t sr)
-{
-	assert_param(IS_CMU_CLOCK_STATE(sr));
-
-	if (READ_BIT(CMU->CLKSR, sr))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Interrupt callback function.
-  * @note   This function is declared as __weak to be overwritten in case of other
-  *         implementations in user file.
-  * @retval None
-  */
-__weak void cmu_irq_cbk(cmu_security_t se)
-{
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup CMU_Public_Functions_Group4 Clock output configure
-  * @brief    Clock output configure functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### Clock output configure functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure the high-speed clock output.
-      (+) Configure the low-speed clock output.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure the high-speed clock output.
-  * @param  sel: Select the source:
-  *           @arg CMU_OUTPUT_HIGH_SEL_HOSC
-  *           @arg CMU_OUTPUT_HIGH_SEL_LOSC
-  *           @arg CMU_OUTPUT_HIGH_SEL_HRC
-  *           @arg CMU_OUTPUT_HIGH_SEL_LRC
-  *           @arg CMU_OUTPUT_HIGH_SEL_HOSM
-  *           @arg CMU_OUTPUT_HIGH_SEL_PLL1
-  *           @arg CMU_OUTPUT_HIGH_SEL_PLL2
-  *           @arg CMU_OUTPUT_HIGH_SEL_SYSCLK
-  * @param  div: The value of divider:
-  *           @arg CMU_OUTPUT_DIV_1
-  *           @arg CMU_OUTPUT_DIV_2
-  *           @arg CMU_OUTPUT_DIV_4
-  *           @arg CMU_OUTPUT_DIV_8
-  *           @arg CMU_OUTPUT_DIV_16
-  *           @arg CMU_OUTPUT_DIV_32
-  *           @arg CMU_OUTPUT_DIV_64
-  *           @arg CMU_OUTPUT_DIV_128
-  * @param  status: The new status.
-  * @retval None
-  */
-void cmu_output_high_clock_config(cmu_output_high_sel_t sel,
-		cmu_output_high_div_t div, type_func_t status)
-{
-	assert_param(IS_CMU_OUTPUT_HIGH_SEL(sel));
-	assert_param(IS_CMU_OUTPUT_HIGH_DIV(div));
-	assert_param(IS_FUNC_STATE(status));
-
-	SYSCFG_UNLOCK();
-
-	if (status) {
-		MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCOS_MSK, sel << CMU_CLKOCR_HSCOS_POSS);
-		MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCODIV_MSK, div << CMU_CLKOCR_HSCODIV_POSS);
-		SET_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK);
-	}
-	else {
-		CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK);
-	}
-
-	SYSCFG_LOCK();
-	return;
-}
-
-/**
-  * @brief  Configure the low-speed clock output.
-  * @param  sel: Select the source:
-  *           @arg CMU_OUTPUT_LOW_SEL_LOSC
-  *           @arg CMU_OUTPUT_LOW_SEL_LRC
-  *           @arg CMU_OUTPUT_LOW_SEL_LOSM
-  *           @arg CMU_OUTPUT_LOW_SEL_BUZZ
-  *           @arg CMU_OUTPUT_LOW_SEL_ULRC
-  * @param  status: The new status.
-  * @retval None
-  */
-void cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status)
-{
-	assert_param(IS_CMU_OUTPUT_LOW_SEL(sel));
-	assert_param(IS_FUNC_STATE(status));
-
-	SYSCFG_UNLOCK();
-
-	if (status) {
-		MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_LSCOS_MSK, sel << CMU_CLKOCR_LSCOS_POSS);
-		SET_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK);
-	}
-	else {
-		CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK);
-	}
-
-	SYSCFG_LOCK();
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup CMU_Public_Functions_Group5 Peripheral Clock configure
-  * @brief    Peripheral clock configure functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### Peripheral clock configure functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure buzz clock.
-      (+) Select lptim0 clock source.
-      (+) Select lpuart0 clock source.
-      (+) Select lcd clock source.
-      (+) Enable/Disable peripheral clock.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure buzz clock.
-  *         freq = sysclk / (2^(div + 1) * (dat + 1))
-  * @param  div: The value of divider.
-  * @param  dat: The value of coefficient.
-  * @param  status: The new status.
-  * @retval None
-  */
-void cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status)
-{
-	assert_param(IS_CMU_BUZZ_DIV(div));
-	assert_param(IS_FUNC_STATE(status));
-
-	SYSCFG_UNLOCK();
-
-	if (status) {
-		MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS);
-		MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, dat << CMU_BUZZCR_DAT_POSS);
-		SET_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK);
-	}
-	else {
-		CLEAR_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK);
-	}
-
-	SYSCFG_LOCK();
-	return;
-}
-
-/**
-  * @brief  Select lptim0 clock source.
-  * @param  clock: The clock source:
-  *           @arg CMU_LP_PERH_CLOCK_SEL_PCLK2
-  *           @arg CMU_LP_PERH_CLOCK_SEL_PLL1
-  *           @arg CMU_LP_PERH_CLOCK_SEL_PLL2
-  *           @arg CMU_LP_PERH_CLOCK_SEL_HRC
-  *           @arg CMU_LP_PERH_CLOCK_SEL_HOSC
-  *           @arg CMU_LP_PERH_CLOCK_SEL_LRC
-  *           @arg CMU_LP_PERH_CLOCK_SEL_LOSC
-  *           @arg CMU_LP_PERH_CLOCK_SEL_ULRC
-  *           @arg CMU_LP_PERH_CLOCK_SEL_HRC_1M
-  *           @arg CMU_LP_PERH_CLOCK_SEL_HOSC_1M
-  *           @arg CMU_LP_PERH_CLOCK_SEL_LOSM
-  *           @arg CMU_LP_PERH_CLOCK_SEL_HOSM
-  * @retval None
-  */
-void cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock)
-{
-	assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock));
-
-	SYSCFG_UNLOCK();
-	MODIFY_REG(CMU->PERICR, CMU_PERICR_LPTIM0_MSK, clock << CMU_PERICR_LPTIM0_POSS);
-	SYSCFG_LOCK();
-
-	return;
-}
-
-/**
-  * @brief  Select lpuart0 clock source.
-  * @param  clock: The clock source:
-  *           @arg CMU_LP_PERH_CLOCK_SEL_PCLK2
-  *           @arg CMU_LP_PERH_CLOCK_SEL_PLL1
-  *           @arg CMU_LP_PERH_CLOCK_SEL_PLL2
-  *           @arg CMU_LP_PERH_CLOCK_SEL_HRC
-  *           @arg CMU_LP_PERH_CLOCK_SEL_HOSC
-  *           @arg CMU_LP_PERH_CLOCK_SEL_LRC
-  *           @arg CMU_LP_PERH_CLOCK_SEL_LOSC
-  *           @arg CMU_LP_PERH_CLOCK_SEL_ULRC
-  *           @arg CMU_LP_PERH_CLOCK_SEL_HRC_1M
-  *           @arg CMU_LP_PERH_CLOCK_SEL_HOSC_1M
-  *           @arg CMU_LP_PERH_CLOCK_SEL_LOSM
-  *           @arg CMU_LP_PERH_CLOCK_SEL_HOSM
-  * @retval None
-  */
-void cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock)
-{
-	assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock));
-
-	SYSCFG_UNLOCK();
-	MODIFY_REG(CMU->PERICR, CMU_PERICR_LPUART0_MSK, clock << CMU_PERICR_LPUART0_POSS);
-	SYSCFG_LOCK();
-
-	return;
-}
-
-/**
-  * @brief  Select lcd clock source.
-  * @param  clock: The clock source:
-  *           @arg CMU_LCD_SEL_LOSM
-  *           @arg CMU_LCD_SEL_LOSC
-  *           @arg CMU_LCD_SEL_LRC
-  *           @arg CMU_LCD_SEL_ULRC
-  *           @arg CMU_LCD_SEL_HRC_1M
-  *           @arg CMU_LCD_SEL_HOSC_1M
-  * @retval None
-  */
-void cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock)
-{
-	assert_param(IS_CMU_LCD_CLOCK_SEL(clock));
-
-	SYSCFG_UNLOCK();
-	MODIFY_REG(CMU->PERICR, CMU_PERICR_LCD_MSK, clock << CMU_PERICR_LCD_POSS);
-	SYSCFG_LOCK();
-
-	return;
-}
-
-/**
-  * @brief  Enable/Disable peripheral clock.
-  * @param  perh: The type of peripheral, you can see @ref cmu_perh_t
-  * @param  status: The new status.
-  * @retval None
-    */
-void cmu_perh_clock_config(cmu_perh_t perh, type_func_t status)
-{
-	uint32_t idx, pos;
-
-	assert_param(IS_CMU_PERH(perh));
-	assert_param(IS_FUNC_STATE(status));
-
-	SYSCFG_UNLOCK();
-
-	if (perh == CMU_PERH_ALL) {
-		if (status) {
-			WRITE_REG(CMU->AHB1ENR, ~0);
-			WRITE_REG(CMU->APB1ENR, ~0);
-			WRITE_REG(CMU->APB2ENR, ~0);
-		}
-		else {
-			WRITE_REG(CMU->AHB1ENR, 0);
-			WRITE_REG(CMU->APB1ENR, 0);
-			WRITE_REG(CMU->APB2ENR, 0);
-		}
-
-		SYSCFG_LOCK();
-		return;
-	}
-
-	idx = (perh >> 27) & 0x3;
-	pos = perh & ~(0x3 << 27);
-
-	if (status) {
-		switch (idx) {
-		case 0:
-			SET_BIT(CMU->AHB1ENR, pos);
-			break;
-
-		case 1:
-			SET_BIT(CMU->APB1ENR, pos);
-			break;
-
-		case 2:
-			SET_BIT(CMU->APB2ENR, pos);
-			break;
-
-		default:
-			break;
-		}
-	}
-	else {
-		switch (idx) {
-		case 0:
-			CLEAR_BIT(CMU->AHB1ENR, pos);
-			break;
-
-		case 1:
-			CLEAR_BIT(CMU->APB1ENR, pos);
-			break;
-
-		case 2:
-			CLEAR_BIT(CMU->APB2ENR, pos);
-			break;
-
-		default:
-			break;
-		}
-	}
-
-	SYSCFG_LOCK();
-	return;
-}
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crc.c

@@ -1,342 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_crc.c
-  * @brief   CRC module driver.
-  *
-  * @version V1.0
-  * @date    6 Dec 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#include "ald_crc.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup CRC CRC
-  * @brief CRC module driver
-  * @{
-  */
-#ifdef ALD_CRC
-
-/** @addtogroup CRC_Private_Functions   CRC Private Functions
-  * @{
-  */
-void crc_reset(crc_handle_t *hperh);
-#ifdef ALD_DMA
-static void crc_dma_calculate_cplt(void *arg);
-static void crc_dma_error(void *arg);
-#endif
-/**
-  * @}
-  */
-
-
-/** @defgroup CRC_Public_Functions CRC Public Functions
-  * @{
-  */
-
-/** @defgroup CRC_Public_Functions_Group1 Initialization functions
-  * @brief Initialization and Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  Initializes the CRC mode according to the specified parameters in
-  *         the crc_handle_t and create the associated handle.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t crc_init(crc_handle_t *hperh)
-{
-	uint32_t tmp = 0;
-
-	if (hperh == NULL)
-		return ERROR;
-
-	assert_param(IS_CRC(hperh->perh));
-	assert_param(IS_CRC_MODE(hperh->init.mode));
-	assert_param(IS_FUNC_STATE(hperh->init.chs_rev));
-	assert_param(IS_FUNC_STATE(hperh->init.data_inv));
-	assert_param(IS_FUNC_STATE(hperh->init.data_rev));
-	assert_param(IS_FUNC_STATE(hperh->init.chs_inv));
-
-	crc_reset(hperh);
-	__LOCK(hperh);
-
-	CRC_ENABLE(hperh);
-
-	tmp = hperh->perh->CR;
-
-	tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATREV_POS) |
-		(hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) |
-		(CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) |
-		(1 << CRC_CR_BYTORD_POS));
-
-	hperh->perh->CR = tmp;
-	hperh->perh->SEED = hperh->init.seed;
-	CRC_RESET(hperh);
-
-	hperh->state = CRC_STATE_READY;
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Public_Functions_Group2 Calculate functions
-  * @brief Calculate functions
-  * @{
-  */
-
-/**
-  * @brief  Calculate the crc value of data.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: The size of data to be calculate
-  * @retval result, the result of a amount data
-  */
-uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size)
-{
-	uint32_t i;
-	uint32_t ret;
-
-	assert_param(IS_CRC(hperh->perh));
-
-	if (buf == NULL || size == 0)
-		return 0;
-
-	__LOCK(hperh);
-	hperh->state = CRC_STATE_BUSY;
-
-	for (i = 0; i < size; i++)
- 		CRC->DATA = buf[i];
-
-	ret          = CRC->CHECKSUM;
-	hperh->state = CRC_STATE_READY;
-	__UNLOCK(hperh);
-
-	return ret;
-}
-/**
-  * @}
-  */
-
-#ifdef ALD_DMA
-/** @defgroup CRC_Public_Functions_Group3 DMA operation functions
-  * @brief DMA operation functions
-  * @{
-  */
-
-/**
-  * @brief  Calculate an amount of data used dma channel
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @param  buf: Pointer to data buffer
-  * @param  res: Pointer to result
-  * @param  size: Amount of data to be Calculate
-  * @param  channel: DMA channel as CRC transmit
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
-{
-	if (hperh->state != CRC_STATE_READY)
-		return BUSY;
-
-	if (buf == NULL || size == 0)
-		return ERROR;
-
-	__LOCK(hperh);
-
-	hperh->state = CRC_STATE_BUSY;
-
-	hperh->cal_buf = buf;
-	hperh->cal_res = res;
-
-	if (hperh->hdma.perh == NULL)
-		hperh->hdma.perh = DMA0;
-
-	hperh->hdma.cplt_arg = (void *)hperh;
-	hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
-	hperh->hdma.err_arg  = (void *)hperh;
-	hperh->hdma.err_cbk  = &crc_dma_error;
-
-	dma_config_struct(&(hperh->hdma.config));
-	hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE;
-	hperh->hdma.config.src        = (void *)buf;
-	hperh->hdma.config.dst        = (void *)&hperh->perh->DATA;
-	hperh->hdma.config.size       = size;
-	hperh->hdma.config.src_inc    = DMA_DATA_INC_BYTE;
-	hperh->hdma.config.dst_inc    = DMA_DATA_INC_NONE;
-	hperh->hdma.config.msel       = DMA_MSEL_CRC;
-	hperh->hdma.config.msigsel    = DMA_MSIGSEL_NONE;
-	hperh->hdma.config.channel    = channel;
-	dma_config_basic(&(hperh->hdma));
-
-	__UNLOCK(hperh);
-	CRC_DMA_ENABLE(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Pauses the DMA Transfer.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t crc_dma_pause(crc_handle_t *hperh)
-{
-	__LOCK(hperh);
-	CRC_DMA_DISABLE(hperh);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Resumes the DMA Transfer.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t crc_dma_resume(crc_handle_t *hperh)
-{
-	__LOCK(hperh);
-	CRC_DMA_ENABLE(hperh);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Stops the DMA Transfer.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t crc_dma_stop(crc_handle_t *hperh)
-{
-	__LOCK(hperh);
-	CRC_DMA_DISABLE(hperh);
-	__UNLOCK(hperh);
-
-	hperh->state = CRC_STATE_READY;
-	return OK;
-}
-
-/**
-  * @}
-  */
-#endif
-
-/** @defgroup CRC_Public_Functions_Group4 Peripheral State and Errors functions
-  * @brief    CRC State and Errors functions
-  * @{
-  */
-
-/**
-  * @brief  Returns the CRC state.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @retval CRC state
-  */
-crc_state_t crc_get_state(crc_handle_t *hperh)
-{
-	assert_param(IS_CRC(hperh->perh));
-
-	return hperh->state;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Private_Functions   CRC Private Functions
-  *  @brief   CRC Private functions
-  * @{
-  */
-
-/**
-  * @brief  Reset the CRC peripheral.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @retval None
-  */
-void crc_reset(crc_handle_t *hperh)
-{
-	hperh->perh->DATA = 0x0;
-	hperh->perh->CR   = 0x2;
-	hperh->perh->SEED = 0xFFFFFFFF;
-
-	hperh->state = CRC_STATE_READY;
-	__UNLOCK(hperh);
-	return;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  DMA CRC calculate process complete callback.
-  * @param  arg: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @retval None
-  */
-static void crc_dma_calculate_cplt(void *arg)
-{
-	crc_handle_t *hperh = (crc_handle_t *)arg;
-
-	*(hperh->cal_res) = CRC->CHECKSUM;
-	CRC_DMA_DISABLE(hperh);
-
-	hperh->state = CRC_STATE_READY;
-
-	if (hperh->cal_cplt_cbk)
-		hperh->cal_cplt_cbk(hperh);
-}
-
-/**
-  * @brief  DMA CRC communication error callback.
-  * @param  arg: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @retval None
-  */
-static void crc_dma_error(void *arg)
-{
-	crc_handle_t *hperh = (crc_handle_t *)arg;
-
-	CRC_CLEAR_ERROR_FLAG(hperh);
-	CRC_DMA_DISABLE(hperh);
-
-	hperh->state = CRC_STATE_READY;
-
-	if (hperh->err_cplt_cbk)
-		hperh->err_cplt_cbk(hperh);
-}
-#endif
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* ALD_CRC */
-
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crypt.c

@@ -1,999 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_crypt.c
-  * @brief   CRYPT module driver.
-  *	     This is the common part of the CRYPT initialization
-  *
-  * @version V1.0
-  * @date    7 Dec 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-
-#include "ald_crypt.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup CRYPT CRYPT
-  * @brief CRYPT module driver
-  * @{
-  */
-#ifdef ALD_CRYPT
-
-/** @addtogroup CRYPT_Private_Functions CRYPT Private Functions
-  * @{
-  */
-void crypt_reset(crypt_handle_t *hperh);
-#ifdef ALD_DMA
-static void crypt_dma_crypt_cplt(void *arg);
-static void crypt_dma_error(void *arg);
-#endif
-/**
-  * @}
-  */
-
-
-/** @defgroup CRYPT_Public_Functions CRYPT Public Functions
-  * @{
-  */
-
-/** @defgroup CRYPT_Public_Functions_Group1 Initialization functions
-  * @brief Initialization and Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  Initializes the CRYPT mode according to the specified parameters in
-  *         the crypt_init_t and create the associated handle.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t crypt_init(crypt_handle_t *hperh)
-{
-	uint32_t tmp = 0;
-
-	if (hperh == NULL)
-		return ERROR;
-
-	assert_param(IS_CRYPT(hperh->perh));
-	assert_param(IS_CRYPT_MODE(hperh->init.mode));
-
-	__LOCK(hperh);
-	crypt_reset(hperh);
-
-	if (hperh->state == CRYPT_STATE_RESET)
-		__UNLOCK(hperh);
-
-	tmp = hperh->perh->CON;
-	hperh->step = 4;
-	tmp |= ((1 << CRYPT_CON_FIFOODR_POS) | (hperh->init.mode << CRYPT_CON_MODE_POSS) | \
-		(hperh->init.type << CRYPT_CON_TYPE_POSS) | (1 << CRYPT_CON_FIFOEN_POS));
-	WRITE_REG(hperh->perh->CON, tmp);
-	hperh->state = CRYPT_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Write the Content of KEY.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @param  key: Pointer to key data buffer
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t crypt_write_key(crypt_handle_t *hperh, uint32_t *key)
-{
-	uint32_t *temp   = key;
-	uint32_t i;
-
-	if (hperh->state == CRYPT_STATE_BUSY)
-		return BUSY;
-
-	if ((hperh == NULL) || (key == NULL))
-		return ERROR;
-
-	assert_param(IS_CRYPT(hperh->perh));
-
-	hperh->perh->KEY[3] = *temp++;
-	hperh->perh->KEY[2] = *temp++;
-	hperh->perh->KEY[1] = *temp++;
-	hperh->perh->KEY[0] = *temp;
-
-	for (i = 0; i < 4; i++)
-		hperh->key[i] = *key++;
-
-	return OK;
-}
-
-/**
-  * @brief  Read the Content of KEY.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @param  key: The pointer to the key
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t crypt_read_key(crypt_handle_t *hperh, uint32_t *key)
-{
-	uint32_t *temp   = key;
-
-	if (hperh->state == CRYPT_STATE_BUSY)
-		return BUSY;
-
-	if ((hperh == NULL) || (key == NULL))
-		return ERROR;
-
-	assert_param(IS_CRYPT(hperh->perh));
-
-	*temp++ = hperh->perh->KEY[3];
-	*temp++ = hperh->perh->KEY[2];
-	*temp++ = hperh->perh->KEY[1];
-	*temp = hperh->perh->KEY[0];
-
-	return OK;
-}
-
-/**
-  * @brief  Write the Content of IV if you use CBC mode
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @param  iv: Pointer to iv data buffer
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv)
-{
-	uint32_t *temp = iv;
-	uint32_t i;
-	if (hperh->state == CRYPT_STATE_BUSY)
-		return BUSY;
-
-	if ((hperh == NULL) || (iv == NULL))
-		return ERROR;
-
-	assert_param(IS_CRYPT(hperh->perh));
-
-	hperh->perh->IV[3] = *temp++;
-	hperh->perh->IV[2] = *temp++;
-	hperh->perh->IV[1] = *temp++;
-	hperh->perh->IV[0] = *temp;
-
-	for (i = 0; i < 4; i++)
-		hperh->iv[i] = *iv++;
-
-	CRYPT_IVEN_ENABLE(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Read the Content of IV.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @param  iv: Pointer to iv data buffer
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv)
-{
-	uint32_t *temp = iv;
-
-	if (hperh->state == CRYPT_STATE_BUSY)
-		return BUSY;
-
-	if ((hperh == NULL) || (iv == NULL))
-		return ERROR;
-
-	assert_param(IS_CRYPT(hperh->perh));
-
-	*temp++ = hperh->perh->IV[3];
-	*temp++ = hperh->perh->IV[2];
-	*temp++ = hperh->perh->IV[1];
-	*temp   = hperh->perh->IV[0];
-
-	return OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYPT_Public_Functions_Group2 Encrypt or Decrypt functions
-  * @brief Encrypt or Decrypt functions
-  * @{
-  */
-
-/**
-  * @brief  Encrypt an amount of data in blocking mode.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @param  plain_text: Pointer to plain data buffer
-  * @param  cipher_text: Pointer to cipher data buffer
-  * @param  size: Amount of plain data
-  * @retval Status, see @ref ald_status_t.
-  * @note   the size is multiple of 16(ase)
-  */
-ald_status_t crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size)
-{
-	uint32_t count = 0;
-	uint32_t i;
-	uint32_t *plain_buf  = (uint32_t *)plain_text;
-	uint32_t *cipher_buf = (uint32_t *)cipher_text;
-
-	if (hperh->state != CRYPT_STATE_READY)
-		return ERROR;
-
-	if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0))
-		return ERROR;
-
-	assert_param(IS_CRYPT(hperh->perh));
-
-	__LOCK(hperh);
-	hperh->state = CRYPT_STATE_BUSY;
-	CRYPT_SETDIR(hperh, CRYPT_ENCRYPT);
-	count = size / (4 * hperh->step);
-
-	while (count--) {
-		for (i = 0; i < hperh->step; i++) {
-			CRYPT_WRITE_FIFO(hperh, *plain_buf);
-			plain_buf++;
-		}
-
-		while (crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET);
-
-		for (i = 0; i < hperh->step; i++) {
-			*cipher_buf = CRYPT_READ_FIFO(hperh);
-			cipher_buf++;
-		}
-	}
-
-	hperh->state = CRYPT_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Decrypt an amount of data in blocking mode.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @param  cipher_text: Pointer to cipher data buffer
-  * @param  plain_text: Pointer to plain data buffer
-  * @param  size: Amount of cipher data
-  * @retval Status, see @ref ald_status_t.
-  * @note   the size is multiple of 16(ase)
-  */
-ald_status_t crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size)
-{
-	uint32_t count = 0;
-	uint32_t i;
-	uint32_t *plain_buf  = (uint32_t*)plain_text;
-	uint32_t *cipher_buf = (uint32_t*)cipher_text;
-
-	if (hperh->init.mode == CRYPT_MODE_CTR) {
-		return crypt_encrypt(hperh, cipher_text, plain_text, size);
-	}
-
-	if (hperh->state != CRYPT_STATE_READY)
-		return ERROR;
-
-	if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0))
-		return ERROR;
-
-	assert_param(IS_CRYPT(hperh->perh));
-
-	__LOCK(hperh);
-	hperh->state = CRYPT_STATE_BUSY;
-	CRYPT_SETDIR(hperh, CRYPT_DECRYPT);
-	count = size / (4 * hperh->step);
-
-	while (count--) {
-		for (i = 0; i < hperh->step; i++) {
-			CRYPT_WRITE_FIFO(hperh, *cipher_buf);
-			cipher_buf++;
-		}
-
-		while (crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET);
-
-		for (i = 0; i < hperh->step; i++) {
-			*plain_buf = CRYPT_READ_FIFO(hperh);
-			plain_buf++;
-		}
-	}
-
-	hperh->state = CRYPT_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-void gcm_mul(uint32_t *res, uint32_t *data, uint32_t *iv)
-{
-	CRYPT->CON = 0;
-	CRYPT->DATA[0] = data[3];
-	CRYPT->DATA[1] = data[2];
-	CRYPT->DATA[2] = data[1];
-	CRYPT->DATA[3] = data[0];
-	CRYPT->IV[0]   = iv[3];
-	CRYPT->IV[1]   = iv[2];
-	CRYPT->IV[2]   = iv[1];
-	CRYPT->IV[3]   = iv[0];
-	CRYPT->CON |= ((1 << CRYPT_CON_RESCLR_POS) | (3 << CRYPT_CON_MODE_POSS) | \
-		       (1 << CRYPT_CON_GO_POS));
-
-	while (READ_BIT(CRYPT->IF, CRYPT_IF_MULTHIF_MSK) == 0);
-
-	res[3] = CRYPT->RES[0];
-	res[2] = CRYPT->RES[1];
-	res[1] = CRYPT->RES[2];
-	res[0] = CRYPT->RES[3];
-
-	WRITE_REG(CRYPT->IFC, CRYPT_IFC_MULTHIFC_MSK);
-	return;
-}
-
-/**
-  * @brief  verify an amount of data in gcm mode.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @param  cipher_text: Pointer to cipher data buffer
-  * @param  size: Amount of cipher data
-  * @param  aadata: Pointer to additional authenticated data buffer
-  * @param  alen: Amount of additional authenticated data
-  * @param  tag: Pointer to authentication tag buffer
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag)
-{
-	uint8_t GCM_HASH_in[0x60] = {0};
-	uint8_t ecb[16] = {0};
-	uint32_t x_temp[4];
-	uint64_t u, v;
-	uint32_t len = 0;
-	uint32_t j, i, k;
-	uint32_t *tag_temp, *cipher_text_temp;
-
-	/* calculate u and v */
-	u = 128 * ((size % 16) ? (size / 16 + 1) : size / 16) - size * 8;
-	v = 128 * ((alen % 16) ? (alen / 16 + 1): alen / 16) - alen * 8;
-
-	/* get the input of GHASH algorithm,the input:A||0^v||C||0^u||[len(A)]_64||[len(C)]_64 */
-	for (i = 0; i < alen; i++) {
-		GCM_HASH_in [i] = * (aadata + i);
-	}
-	len += alen;
-	for (i = 0; i < v / 8; i++) {
-		GCM_HASH_in[i + len] = 0;
-	}
-	len += v / 8;
-	for (i = 0; i < size; i++) {
-		GCM_HASH_in[i + len] = * (cipher_text + i);
-	}
-	len += size;
-	for (i = 0; i < u / 8; i++) {
-		GCM_HASH_in[i + len] = 0;
-	}
-	len += u / 8;
-
-	for (i = 0; i < 4; i++) {
-		GCM_HASH_in[i + len] = 0;
-	}
-	len += 4;
-
-	for (i = 0; i < 4; i++) {
-		GCM_HASH_in[i + len] = ((alen * 8) >> (8 * i)) & 0xFF;
-	}
-	len += 4;
-
-	for (i = 0; i < 4; i++) {
-		GCM_HASH_in[i + len] = 0;
-	}
-	len += 4;
-
-	for (i = 0; i < 4; i++) {
-		GCM_HASH_in[i + len] = ((size * 8) >> (8 * i)) & 0xFF;
-	}
-	len += 4;
-
-	CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS);
-	CRYPT->CON |= (CRYPT_MODE_ECB << CRYPT_CON_MODE_POSS);
-
-	crypt_encrypt(hperh, ecb, ecb, 16);
-
-	k = len / 16;
-	for (i = 0; i < 16; i++) {
-		tag[i] = 0;
-	}
-
-	cipher_text_temp = (uint32_t *)GCM_HASH_in;
-	tag_temp         = (uint32_t *)tag;
-	for (i = 0; i < k; i++) {
-		for (j = 0; j < 4; j++) {
-			x_temp[j] = (*cipher_text_temp) ^ tag_temp[j];
-			++cipher_text_temp;
-		}
-
-		gcm_mul((uint32_t *)tag_temp, x_temp, (uint32_t *)ecb);
-	}
-
-	/* calculate the authentication tag T,
-	 * T = CIPH_K(J0)^S,J0=IV||0^31||1,CIPH_K is the algorithm of AES in ECB mode
-	 */
-	tag_temp = (uint32_t *)tag;
-	crypt_init(hperh);
-	CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS);
-	CRYPT->CON |= (CRYPT_MODE_CTR << CRYPT_CON_MODE_POSS);
-	crypt_write_key(hperh, hperh->key);
-	hperh->iv[3] = 1;
-	crypt_write_ivr(hperh, hperh->iv);
-	crypt_encrypt(hperh, tag, tag, 16);
-
-	return OK;
-}
-
-/**
-  * @brief  Encrypt an amount of data in non-blocking mode.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @param  plain_text: Pointer to plain data buffer
-  * @param  cipher_text: Pointer to cipher data buffer
-  * @param  size: Amount of plain data
-  * @retval Status, see @ref ald_status_t.
-  * @note   the size is multiple of 16(ase)
-  */
-ald_status_t crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t * plain_text, uint8_t *cipher_text, uint32_t size)
-{
-	uint32_t i;
-	uint32_t *plain_buf = (uint32_t *)plain_text;
-
-	if (hperh->state != CRYPT_STATE_READY)
-		return ERROR;
-
-	if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0))
-		return ERROR;
-
-	assert_param(IS_CRYPT(hperh->perh));
-
-	__LOCK(hperh);
-	hperh->state = CRYPT_STATE_BUSY;
-	CRYPT_SETDIR(hperh, CRYPT_ENCRYPT);
-	hperh->count       = hperh->step;
-	hperh->plain_text  = plain_text;
-	hperh->cipher_text = cipher_text;
-	hperh->size        = size;
-	crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE);
-
-	for (i = 0; i < hperh->step; i++) {
-		CRYPT_WRITE_FIFO(hperh, *plain_buf);
-		++plain_buf;
-	}
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Decrypt an amount of data in non-blocking mode.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @param  plain_text: Pointer to plain data buffer
-  * @param  cipher_text: Pointer to cipher data buffer
-  * @param  size: Amount of cipher data
-  * @retval Status, see @ref ald_status_t.
-  * @note   the size is multiple of 16(ase)
-  */
-ald_status_t crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size)
-{
-	uint32_t i;
-	uint32_t *cipher_buf = (uint32_t*)cipher_text;
-
-	if (hperh->init.mode == CRYPT_MODE_CTR) {
-		return crypt_decrypt_by_it(hperh, cipher_text, plain_text, size);
-	}
-
-	if (hperh->state != CRYPT_STATE_READY)
-		return ERROR;
-
-	if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0))
-		return ERROR;
-
-	assert_param(IS_CRYPT(hperh->perh));
-
-	__LOCK(hperh);
-	hperh->state = CRYPT_STATE_BUSY;
-	CRYPT_SETDIR(hperh, CRYPT_DECRYPT);
-	hperh->count       = hperh->step;
-	hperh->plain_text  = plain_text;
-	hperh->cipher_text = cipher_text;
-	hperh->size        = size;
-	crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE);
-
-	for (i = 0; i < hperh->step; i++) {
-		CRYPT_WRITE_FIFO(hperh, *cipher_buf);
-		cipher_buf++;
-	}
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  Encrypt an amount of data in non-blocking mode.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @param  plain_text: Pointer to plain data buffer
-  * @param  cipher_text: Pointer to cipher data buffer
-  * @param  size: Amount of plain data
-  * @param  channel_m2p: Memory to Crypt module DMA channel
-  * @param  channel_p2m: Crypt module to Memory DMA channel
-  * @retval Status, see @ref ald_status_t.
-  * @note   the size is multiple of 16(ase)
-  */
-ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t * plain_text,
-             uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
-{
-	if (hperh->state != CRYPT_STATE_READY)
-		return ERROR;
-
-	if (plain_text == NULL || cipher_text == NULL || size == 0)
-		return ERROR;
-
-	assert_param(IS_CRYPT(hperh->perh));
-
-	__LOCK(hperh);
-	hperh->state = CRYPT_STATE_BUSY;
-
-	hperh->plain_text  = plain_text;
-	hperh->cipher_text = cipher_text;
-	hperh->size        = size;
-	hperh->count       = size;
-
-	if (hperh->hdma_m2p.perh == NULL)
-		hperh->hdma_m2p.perh = DMA0;
-	if (hperh->hdma_p2m.perh == NULL)
-		hperh->hdma_p2m.perh = DMA0;
-
-	hperh->hdma_m2p.cplt_arg = NULL;
-	hperh->hdma_m2p.cplt_cbk = NULL;
-	hperh->hdma_m2p.err_arg  = NULL;
-	hperh->hdma_m2p.err_cbk  = NULL;
-
-	hperh->hdma_p2m.cplt_arg = (void *)hperh;
-	hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt;
-	hperh->hdma_p2m.err_arg  = (void *)hperh;
-	hperh->hdma_p2m.err_cbk  = &crypt_dma_error;
-
-	CRYPT_SETDIR(hperh, CRYPT_ENCRYPT);
-
-	dma_config_struct(&hperh->hdma_m2p.config);
-	hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD;
-	hperh->hdma_m2p.config.src        = (void *)hperh->plain_text;
-	hperh->hdma_m2p.config.dst        = (void *)&hperh->perh->FIFO;
-	hperh->hdma_m2p.config.size       = size / 4;
-	hperh->hdma_m2p.config.src_inc    = DMA_DATA_INC_WORD;
-	hperh->hdma_m2p.config.dst_inc    = DMA_DATA_INC_NONE;
-	hperh->hdma_m2p.config.msel       = DMA_MSEL_CRYPT;
-	hperh->hdma_m2p.config.msigsel    = DMA_MSIGSEL_CRYPT_WRITE;
-	hperh->hdma_m2p.config.channel    = channel_m2p;
-	dma_config_basic(&(hperh->hdma_m2p));
-
-	dma_config_struct(&hperh->hdma_p2m.config);
-	hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD;
-	hperh->hdma_p2m.config.src        = (void *)&hperh->perh->FIFO;
-	hperh->hdma_p2m.config.dst        = (void *)hperh->cipher_text;
-	hperh->hdma_p2m.config.size       = size / 4;
-	hperh->hdma_p2m.config.src_inc    = DMA_DATA_INC_NONE;
-	hperh->hdma_p2m.config.dst_inc    = DMA_DATA_INC_WORD;
-	hperh->hdma_p2m.config.msel       = DMA_MSEL_CRYPT;
-	hperh->hdma_p2m.config.msigsel    = DMA_MSIGSEL_CRYPT_READ;
-	hperh->hdma_p2m.config.channel    = channel_p2m;
-	dma_config_basic(&(hperh->hdma_p2m));
-
-	CRYPT_DMA_ENABLE(hperh);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Decrypt an amount of data in non-blocking mode.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @param  plain_text: Pointer to plain data buffer
-  * @param  cipher_text: Pointer to cipher data buffer
-  * @param  size: Amount of cipher data
-  * @param  channel_m2p: Memory to Crypt module DMA channel
-  * @param  channel_p2m: Crypt module to Memory DMA channel
-  * @retval Status, see @ref ald_status_t.
-  * @note   the size is multiple of 16(ase)
-  */
-ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t * cipher_text,
-               uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
-{
-	if (hperh->init.mode == CRYPT_MODE_CTR)
-		return crypt_decrypt_by_dma(hperh, cipher_text, plain_text, size, channel_m2p, channel_p2m);
-
-	if (hperh->state != CRYPT_STATE_READY)
-		return ERROR;
-	if (plain_text == NULL || cipher_text == NULL || size == 0)
-		return ERROR;
-
-	__LOCK(hperh);
-	hperh->state = CRYPT_STATE_BUSY;
-
-	hperh->plain_text  = plain_text;
-	hperh->cipher_text = cipher_text;
-	hperh->size        = size;
-	hperh->count       = size;
-
-	if (hperh->hdma_m2p.perh == NULL)
-		hperh->hdma_m2p.perh = DMA0;
-	if (hperh->hdma_p2m.perh == NULL)
-		hperh->hdma_p2m.perh = DMA0;
-
-
-	hperh->hdma_m2p.cplt_arg = NULL;
-	hperh->hdma_m2p.cplt_cbk = NULL;
-	hperh->hdma_m2p.err_arg  = NULL;
-	hperh->hdma_m2p.err_cbk  = NULL;
-
-	hperh->hdma_p2m.cplt_arg = (void *)hperh;
-	hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt;
-	hperh->hdma_p2m.err_arg  = (void *)hperh;
-	hperh->hdma_p2m.err_cbk  = &crypt_dma_error;
-
-	CRYPT_SETDIR(hperh, CRYPT_DECRYPT);
-
-	dma_config_struct(&hperh->hdma_m2p.config);
-	hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD;
-	hperh->hdma_m2p.config.src        = (void *)hperh->cipher_text;
-	hperh->hdma_m2p.config.dst        = (void *)&hperh->perh->FIFO;
-	hperh->hdma_m2p.config.size       = size / 4;
-	hperh->hdma_m2p.config.src_inc    = DMA_DATA_INC_WORD;
-	hperh->hdma_m2p.config.dst_inc    = DMA_DATA_INC_NONE;
-	hperh->hdma_m2p.config.msel       = DMA_MSEL_CRYPT;
-	hperh->hdma_m2p.config.msigsel    = DMA_MSIGSEL_CRYPT_WRITE;
-	hperh->hdma_m2p.config.channel    = channel_m2p;
-	dma_config_basic(&(hperh->hdma_m2p));
-
-	dma_config_struct(&hperh->hdma_p2m.config);
-	hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD;
-	hperh->hdma_p2m.config.src        = (void *)&hperh->perh->FIFO;
-	hperh->hdma_p2m.config.dst        = (void *)hperh->plain_text;
-	hperh->hdma_p2m.config.size       = size / 4;
-	hperh->hdma_p2m.config.src_inc    = DMA_DATA_INC_NONE;
-	hperh->hdma_p2m.config.dst_inc    = DMA_DATA_INC_WORD;
-	hperh->hdma_p2m.config.msel       = DMA_MSEL_CRYPT;
-	hperh->hdma_p2m.config.msigsel    = DMA_MSIGSEL_CRYPT_READ;
-	hperh->hdma_p2m.config.channel    = channel_p2m;
-	dma_config_basic(&(hperh->hdma_p2m));
-
-	CRYPT_DMA_ENABLE(hperh);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYPT_Public_Functions_Group3 DMA operation functions
-  * @brief DMA operation functions
-  * @{
-  */
-
-/**
-  * @brief  Pauses the DMA Transfer.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t crypt_dma_pause(crypt_handle_t *hperh)
-{
-	__LOCK(hperh);
-	CRYPT_DMA_DISABLE(hperh);
-	__UNLOCK(hperh);
-
-	return OK;
-
-}
-
-/**
-  * @brief  Resumes the DMA Transfer.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t crypt_dma_resume(crypt_handle_t *hperh)
-{
-	__LOCK(hperh);
-	CRYPT_DMA_ENABLE(hperh);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Stops the DMA Transfer.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t crypt_dma_stop(crypt_handle_t *hperh)
-{
-	__LOCK(hperh);
-	CRYPT_DMA_DISABLE(hperh);
-	__UNLOCK(hperh);
-
-	hperh->state = CRYPT_STATE_READY;
-	return OK;
-}
-#endif
-
-/**
-  * @brief  This function handles CRYPT interrupt request.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @retval None
-  */
-void crypt_irq_handle(crypt_handle_t *hperh)
-{
-	uint32_t i;
-	uint32_t *in_buf;
-	uint32_t *out_buf;
-
-	if (READ_BIT(hperh->perh->CON, CRYPT_CON_ENCS_MSK)) {
-		in_buf  = (uint32_t *)hperh->plain_text + hperh->count;
-		out_buf = (uint32_t *)hperh->cipher_text + hperh->count - hperh->step;
-	}
-	else {
-		in_buf  = (uint32_t *)hperh->cipher_text + hperh->count;
-		out_buf = (uint32_t *)hperh->plain_text + hperh->count - hperh->step;
-	}
-
-	if (crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET) {
-		crypt_clear_flag_status(hperh, CRYPT_FLAG_AESIF);
-	}
-
-	for (i = 0; i < hperh->step; i++)
-		*out_buf++ = CRYPT_READ_FIFO(hperh);
-
-	hperh->count += hperh->step;
-	if (hperh->count > (hperh->size / 4)) {
-		hperh->count = 0;
-		hperh->state = CRYPT_STATE_READY;
-
-		if (hperh->crypt_cplt_cbk)
-			hperh->crypt_cplt_cbk(hperh);
-	}
-	else {
-		for (i = 0; i < hperh->step; i++) {
-			CRYPT_WRITE_FIFO(hperh, *in_buf++);
-		}
-	}
-}
-/**
-  * @}
-  */
-
-/** @defgroup CRYPT_Public_Functions_Group4 Peripheral Control functions
-  *  @brief   CRYPT control functions
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified CRYPT interrupts.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @param  it: Specifies the CRYPT interrupt sources to be enabled or disabled.
-  *           This parameter can be one of the following values:
-  *           @arg crypt_it_t:  CRYPT interrupt
-  * @param  state: New status
-  *           - ENABLE
-  *           - DISABLE
-  * @retval None
-  */
-void crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state)
-{
-	assert_param(IS_CRYPT(hperh->perh));
-
-	if (it == CRYPT_IT_IT) {
-		CLEAR_BIT(CRYPT->CON, CRYPT_CON_IE_MSK);
-		CRYPT->CON |= (state << CRYPT_CON_IE_POS);
-	}
-
-	return;
-}
-
-/** @brief  Check whether the specified CRYPT flag is set or not.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @param  flag: specifies the flag to check.
-  *         This parameter can be one of the @ref crypt_flag_t.
-  * @retval Status
-  *           - SET
-  *           - RESET
-  */
-flag_status_t crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag)
-{
-	assert_param(IS_CRYPT(hperh->perh));
-	assert_param(IS_CRYPT_FLAG(flag));
-
-	if (CRYPT->IF & flag)
-		return SET;
-
-	return RESET;
-}
-
-/** @brief  Clear the specified CRYPT pending flags.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @param  flag: specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg CRYPT_FLAG_AESIF: AES encrypt or decrypt Complete flag.
-  *            @arg CRYPT_FLAG_DONE: encrypt or decrypt Complete flag.
-  * @retval None
-  */
-void crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag)
-{
-	assert_param(IS_CRYPT(hperh->perh));
-	assert_param(IS_CRYPT_FLAG(flag));
-
-	WRITE_REG(CRYPT->IFC, flag);
-	return;
-}
-
-/**
-  * @brief  Checks whether the specified CRYPT interrupt has occurred or not.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @param  it: Specifies the CRYPT interrupt source to check.
-  *	       This parameter can be one of the following values:
-  *	       @arg crypt_it_t:  CRYPT interrupt
-  * @retval Status
-  *           - SET
-  *           - RESET
-  */
-it_status_t crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it)
-{
-	assert_param(IS_CRYPT_IT(it));
-
-	if (READ_BIT(CRYPT->CON, CRYPT_CON_IE_MSK))
-		return SET;
-
-	return RESET;
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYPT_Public_Functions_Group5 Peripheral State and Errors functions
-  * @brief    State and Errors functions
-  * @{
-  */
-
-/**
-  * @brief  Returns the CRYPT state.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @retval CRYPT state
-  */
-crypt_state_t crypt_get_state(crypt_handle_t *hperh)
-{
-	assert_param(IS_CRYPT(hperh->perh));
-
-
-	return hperh->state;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYPT_Private_Functions   CRYPT Private Functions
-  *  @brief   CRYPT Private functions
-  * @{
-  */
-
-/**
-  * @brief  Reset the CRYPT peripheral.
-  * @param  hperh: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @retval None
-  */
-void crypt_reset(crypt_handle_t *hperh)
-{
-	hperh->perh->DATA[0] = 0x0;
-	hperh->perh->DATA[1] = 0x0;
-	hperh->perh->DATA[2] = 0x0;
-	hperh->perh->DATA[3] = 0x0;
-	hperh->perh->KEY[0] = 0x0;
-	hperh->perh->KEY[1] = 0x0;
-	hperh->perh->KEY[2] = 0x0;
-	hperh->perh->KEY[3] = 0x0;
-	hperh->perh->KEY[4] = 0x0;
-	hperh->perh->KEY[5] = 0x0;
-	hperh->perh->KEY[6] = 0x0;
-	hperh->perh->KEY[7] = 0x0;
-	hperh->perh->IV[0] = 0x0;
-	hperh->perh->IV[1] = 0x0;
-	hperh->perh->IV[2] = 0x0;
-	hperh->perh->IV[3] = 0x0;
-	hperh->perh->CON = 0x0;
-
-	hperh->state = CRYPT_STATE_READY;
-	__UNLOCK(hperh);
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  DMA CRYPT encrypt or decrypt process complete callback.
-  * @param  arg: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @retval None
-  */
-static void crypt_dma_crypt_cplt(void *arg)
-{
-	crypt_handle_t *hperh = (crypt_handle_t *)arg;
-
-	CRYPT_DMA_DISABLE(hperh);
-	hperh->count       = 0;
-	hperh->plain_text  = NULL;
-	hperh->cipher_text = NULL;
-	hperh->size        = 0;
-
-	hperh->state = CRYPT_STATE_READY;
-
-	if (hperh->crypt_cplt_cbk)
-		hperh->crypt_cplt_cbk(hperh);
-}
-
-/**
-  * @brief  DMA CRYPT communication error callback.
-  * @param  arg: Pointer to a crypt_handle_t structure that contains
-  *         the configuration information for the specified CRYPT module.
-  * @retval None
-  */
-static void crypt_dma_error(void *arg)
-{
-	crypt_handle_t *hperh = (crypt_handle_t *)arg;
-	CRYPT_DMA_DISABLE(hperh);
-
-	hperh->count       = 0;
-	hperh->plain_text  = NULL;
-	hperh->cipher_text = NULL;
-	hperh->size        = 0;
-
-	hperh->state = CRYPT_STATE_READY;
-
-	if (hperh->err_cplt_cbk)
-		hperh->err_cplt_cbk(hperh);
-}
-#endif
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* ALD_CRYPT */
-
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_dma.c

@@ -1,734 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_dma.c
-  * @brief   DMA module driver.
-  *
-  * @version V1.0
-  * @date    09 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  * @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The DMA driver can be used as follows:
-
-    (#) System initialization invokes dma_init(), mcu_ald_init() --> dma_init().
-
-    (#) Declare a dma_handle_t handle structure.
-
-    (#) Configure the dma_handle_t structure, you can configure the
-        dma_config_t structure with the help of dma_config_struct().
-
-    (#) Enable the DMA Configure:
-        (##) Memory     -- memory: call dma_config_auto().
-	(##) Peripheral -- memory: call dma_config_basic().
-	(##) If you want use the dma easily, you can do this:
-	    (+++) Memory     -- memory: call dma_config_auto_easy().
-	    (+++) Peripheral -- memory: call dma_config_basic_easy().
-
-    (#) Enable the DMA request signal:
-        (##) Memory     -- memory: the DMA request signal is request automatic.
-	(##) Peripheral -- memory: you need enable peripheral request signal.
-
-    (#) If you enable DMA interrupt, the callback will be invoked:
-        (##) When DMA transfer is completed, the cplt_cbk() will be invoked.
-	(##) When DMA bus occurs error, the err_cbk() will be invoked.
-
-    (#) If you don't enable the DMA interrupt, you need do this:
-        (##) Polling the dma_get_flag_status(), this function's parameter is channel
-	     or DMA_ERR.
-	    (+++) When the function's Parameter is channel, if retval is SET, it means
-	          the DMA transfer is completed. at this moment, you can do something,
-		  and then, you need invoke dma_clear_flag_status() to clear flag.
-
-	    (+++) When the function's Parameter is DMA_ERR, if retval is SET, it means
-	          the DMA bus occurs error. at this moment, you can do something,
-		  and then, you need invoke dma_clear_flag_status() to clear flag.
-
-    @endverbatim
-  */
-
-#include <string.h>
-#include "ald_conf.h"
-#include "ald_dma.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup DMA DMA
-  * @brief DMA module driver
-  * @{
-  */
-
-#ifdef ALD_DMA
-/** @defgroup DMA_Private_Variables DMA Private Variables
-  * @{
-  */
-dma_descriptor_t dma0_ctrl_base[28] __attribute__ ((aligned(512)));
-dma_call_back_t dma0_cbk[6];
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Private_Functions DMA Private Functions
-  * @{
-  */
-
-/**
-  * @brief  Configure DMA channel using dma_config_t structure
-  * @param  DMAx: Pointer to DMA peripheral
-  * @param  mode: DMA transfer mode. see @ref dma_cycle_ctrl_t
-  * @param  p: Pointer to dma_cycle_ctrl_t which contains
-  *            DMA channel parameter. see @ref dma_config_t
-  * @retval None
-  */
-static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config_t *p)
-{
-	dma_descriptor_t *descr;
-
-	assert_param(IS_DMA(DMAx));
-	assert_param(IS_CYCLECTRL_TYPE(mode));
-	assert_param(p->src != NULL);
-	assert_param(p->dst != NULL);
-	assert_param(IS_DMA_DATA_SIZE(p->size));
-	assert_param(IS_DMA_DATASIZE_TYPE(p->data_width));
-	assert_param(IS_DMA_DATAINC_TYPE(p->src_inc));
-	assert_param(IS_DMA_DATAINC_TYPE(p->dst_inc));
-	assert_param(IS_DMA_ARBITERCONFIG_TYPE(p->R_power));
-	assert_param(IS_FUNC_STATE(p->primary));
-	assert_param(IS_FUNC_STATE(p->burst));
-	assert_param(IS_FUNC_STATE(p->high_prio));
-	assert_param(IS_FUNC_STATE(p->iterrupt));
-	assert_param(IS_DMA_MSEL_TYPE(p->msel));
-	assert_param(IS_DMA_MSIGSEL_TYPE(p->msigsel));
-	assert_param(IS_DMA_CHANNEL(p->channel));
-
-	if (p->primary)
-		descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + p->channel;
-	else
-		descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + p->channel;
-
-	if (p->src_inc == DMA_DATA_INC_NONE)
-		descr->src = p->src;
-	else
-		descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << p->data_width));
-
-	if (p->dst_inc == DMA_DATA_INC_NONE)
-		descr->dst = p->dst;
-	else
-		descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << p->data_width));
-
-	descr->ctrl.cycle_ctrl    = mode;
-	descr->ctrl.next_useburst = 0;
-	descr->ctrl.n_minus_1     = p->size - 1;
-	descr->ctrl.R_power       = p->R_power;
-	descr->ctrl.src_prot_ctrl = 0,
-	descr->ctrl.dst_prot_ctrl = 0,
-	descr->ctrl.src_size      = p->data_width;
-	descr->ctrl.src_inc       = p->src_inc;
-	descr->ctrl.dst_size      = p->data_width;
-	descr->ctrl.dst_inc       = p->dst_inc;
-
-	if (p->primary)
-		WRITE_REG(DMAx->CHPRIALTCLR, (1 << p->channel));
-	else
-		WRITE_REG(DMAx->CHPRIALTSET, (1 << p->channel));
-
-	if (p->burst)
-		WRITE_REG(DMAx->CHUSEBURSTSET, (1 << p->channel));
-	else
-		WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << p->channel));
-
-	if (p->high_prio)
-		WRITE_REG(DMAx->CHPRSET, (1 << p->channel));
-	else
-		WRITE_REG(DMAx->CHPRCLR, (1 << p->channel));
-
-	if (p->iterrupt)
-		SET_BIT(DMAx->IER, (1 << p->channel));
-	else
-		CLEAR_BIT(DMAx->IER, (1 << p->channel));
-
-	MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSEL_MSK, p->msel << DMA_CH0_SELCON_MSEL_POSS);
-	MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSIGSEL_MSK, p->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS);
-	return;
-}
-
-/**
-  * @brief  Handle DMA interrupt
-  * @retval None
-  */
-void DMA_Handler(void)
-{
-	uint32_t i, reg = DMA0->IFLAG;
-
-	for (i = 0; i < DMA_CH_COUNT; ++i) {
-		if (READ_BIT(reg, (1 << i))) {
-			if (dma0_cbk[i].cplt_cbk != NULL)
-				dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg);
-
-			dma_clear_flag_status(DMA0, i);
-		}
-	}
-
-	if (READ_BIT(reg, (1U << DMA_ERR))) {
-		dma_clear_flag_status(DMA0, DMA_ERR);
-
-		for (i = 0; i < DMA_CH_COUNT; ++i) {
-			if (((DMA0->CHENSET >> i) & 0x1) && (dma0_cbk[i].err_cbk != NULL))
-				dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg);
-		}
-	}
-
-	dma0_irq_cbk();
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Public_Functions DMA Public Functions
-  * @{
-  */
-
-/** @defgroup DMA_Public_Functions_Group1 Initialization functions
-  * @brief Initialization functions
-  *
-  * @verbatim
-    ===================================================================
-
-                    #### Initialization functions ####
-
-    ===================================================================
-    [..]
-    This subsection provides two functions to Initilizate DMA:
-    (+) dma_reset(): Reset the DMA register.
-
-    (+) dma_init(): Initializate the DMA module. this function is
-        invoked by mcu_ald_init().
-	this function do this:
-	(++) Initializte private variable dma_ctrl_base and dma_cbk.
-	(++) Reset DMA register.
-	(++) Set DMA interrupt priority: preempt_prio=1, sub_priority=1
-	(++) Enable DMA interrupt.
-	(++) Enable DMA bus error interrupt.
-	(++) Configure CTRLBASE resigter.
-	(++) Enable DMA module.
-
-    (+) dma_config_struct(): Configure dma_config_t
-        structure using default parameter.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reset the DMA register
-  * @param  DMAx: Pointer to DMA peripheral
-  * @retval None
-  */
-void dma_reset(DMA_TypeDef *DMAx)
-{
-	uint32_t i;
-
-	assert_param(IS_DMA(DMAx));
-
-	WRITE_REG(DMAx->CFG, 0x0);
-	WRITE_REG(DMAx->CHUSEBURSTCLR, 0xFFF);
-	WRITE_REG(DMAx->CHREQMASKCLR, 0xFFF);
-	WRITE_REG(DMAx->CHENCLR, 0xFFF);
-	WRITE_REG(DMAx->CHPRIALTCLR, 0xFFF);
-	WRITE_REG(DMAx->CHPRCLR, 0xFFF);
-	WRITE_REG(DMAx->ERRCLR, 0x1);
-	WRITE_REG(DMAx->IER, 0x0);
-	WRITE_REG(DMAx->ICFR, 0x80000FFF);
-
-	for (i = 0; i < DMA_CH_COUNT; ++i)
-		WRITE_REG(DMAx->CH_SELCON[i], 0x0);
-
-	return;
-}
-
-/**
-  * @brief  DMA module initialization, this function
-  *         is invoked by mcu_ald_init().
-  * @param  DMAx: Pointer to DMA peripheral
-  * @retval None
-  */
-void dma_init(DMA_TypeDef *DMAx)
-{
-	assert_param(IS_DMA(DMAx));
-
-	memset(dma0_ctrl_base, 0x0, sizeof(dma0_ctrl_base));
-	memset(dma0_cbk, 0x0, sizeof(dma0_cbk));
-
-	dma_reset(DMAx);
-	NVIC_SetPriority(DMA_IRQn, 2);
-	NVIC_EnableIRQ(DMA_IRQn);
-	SET_BIT(DMAx->IER, DMA_IER_DMAERRIE_MSK);
-
-	WRITE_REG(DMAx->CTRLBASE, (uint32_t)&dma0_ctrl_base);
-	SET_BIT(DMAx->CFG, DMA_CFG_MASTER_ENABLE_MSK);
-
-	return;
-}
-
-/**
-  * @brief  Configure dma_config_t structure using default parameter.
-  *         User can invoked this function, before configure dma_config_t
-  * @param  p: Pointer to dma_config_t structure, see @ref dma_config_t
-  * @retval None
-  */
-void dma_config_struct(dma_config_t *p)
-{
-	p->data_width = DMA_DATA_SIZE_BYTE;
-	p->src_inc    = DMA_DATA_INC_BYTE;
-	p->dst_inc    = DMA_DATA_INC_BYTE;
-	p->R_power    = DMA_R_POWER_1;
-	p->primary    = ENABLE;
-	p->burst      = DISABLE;
-	p->high_prio  = DISABLE;
-	p->iterrupt   = ENABLE;
-
-	return;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Public_Functions_Group2 Configure DMA channel functions
-  * @brief Configure DMA channel functions
-  *
-  * @verbatim
-    ===================================================================
-
-                    #### Configure DMA channel functions ####
-
-    ===================================================================
-    [..]
-    This subsection provides some functions allowing to configure
-    DMA channel. Include two type DMA transfer:
-    (+) Carry data from memory to memory, this mode APIs are:
-        (++) dma_config_auto(): Configure DMA channel according to
-	     the specified parameter in the dma_handle_t structure.
-	(++) dma_restart_auto(): Restart DMA transmitted.
-        (++) dma_config_auto_easy(): Configure DMA channel according
-	     to the specified parameter. If you want use the dma easily,
-             you can invoke this function.
-    (+) Carry data from peripheral to memory or from memory to peripheral,
-        this mode APIs are:
-	(++) dma_config_basic(): Configure DMA channel according to
-	     the specified parameter in the dma_handle_t structure.
-	(++) dma_restart_basic(): Restart DMA transmitted.
-        (++) dma_config_basic_easy(): Configure DMA channel according
-	     to the specified parameter. If you want use the dma easily,
-             you can invoke this function.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure DMA channel according to the specified parameter
-  *         in the dma_handle_t structure. The DMA mode is automatic.
-  *         This mode is used to carry data from memory to memory.
-  * @param  hperh: Pointer to DMA_handle_t structure that contains
-  *               configuration information for specified DMA channel.
-  * @retval None
-  */
-void dma_config_auto(dma_handle_t *hperh)
-{
-	dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk;
-	dma0_cbk[hperh->config.channel].err_cbk  = hperh->err_cbk;
-	dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg;
-	dma0_cbk[hperh->config.channel].err_arg  = hperh->err_arg;
-	dma_config_base(hperh->perh, DMA_CYCLE_CTRL_AUTO, &hperh->config);
-
-	dma_clear_flag_status(hperh->perh, hperh->config.channel);
-	WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
-	SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel));
-
-	return;
-}
-
-/**
-  * @brief  Restart DMA transmitted. The DMA mode is automatic.
-  *         The other parameters have not changed except 'size' and 'addr'.
-  * @param  hperh: Pointer to DMA_handle_t structure that contains
-  *               configuration information for specified DMA channel.
-  * @param  src: Source data begin pointer
-  * @param  dst: Destination data begin pointer
-  * @param  size: Size.
-  * @retval None
-  */
-void dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size)
-{
-	dma_descriptor_t *descr;
-
-	if (hperh->config.primary)
-		descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel;
-	else
-		descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel;
-
-	if (src) {
-		if (hperh->config.src_inc == DMA_DATA_INC_NONE)
-			descr->src = src;
-		else
-			descr->src = (void *)((uint32_t)src + ((size - 1) << hperh->config.data_width));
-	}
-
-	if (dst) {
-		if (hperh->config.dst_inc == DMA_DATA_INC_NONE)
-			descr->dst = dst;
-		else
-			descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width));
-	}
-
-	dma_clear_flag_status(hperh->perh, hperh->config.channel);
-	descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO;
-	descr->ctrl.n_minus_1  = size - 1;
-	WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
-	SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel));
-	return;
-}
-
-
-
-/**
-  * @brief  Configure DMA channel according to the specified parameter.
-  *         The DMA mode is automatic. This mode is used to carry data
-  *         from memory to memory. If User want use the dma easily,
-  *         they can invoke this function.
-  * @param  DMAx: Pointer to DMA peripheral
-  * @param  src: Source data begin pointer
-  * @param  dst: Destination data begin pointer
-  * @param  size: The total number of DMA transfers that DMA cycle contains
-  * @param  channel: Channel index which well be used.
-  * @param  cbk: DMA complete callback function
-  *
-  * @retval None
-  */
-void dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst,
-                       uint16_t size, uint8_t channel, void (*cbk)(void *arg))
-{
-	dma_handle_t hperh;
-
-	assert_param(IS_DMA(DMAx));
-
-	dma_config_struct(&hperh.config);
-	hperh.config.src     = src;
-	hperh.config.dst     = dst;
-	hperh.config.size    = size;
-	hperh.config.msel    = DMA_MSEL_NONE;
-	hperh.config.msigsel = DMA_MSIGSEL_NONE;
-	hperh.config.channel = channel;
-
-	hperh.perh     = DMAx;
-	hperh.cplt_cbk = cbk;
-	hperh.cplt_arg = NULL;
-	hperh.err_cbk  = NULL;
-
-	dma_clear_flag_status(DMAx, channel);
-	dma_config_auto(&hperh);
-
-	return;
-}
-
-/**
-  * @brief  Configure DMA channel according to the specified parameter
-  *         in the dma_handle_t structure. The DMA mode is basic.
-  *         This mode is used to carry data from peripheral to memory
-  *         or from memory to peripheral.
-  * @param  hperh: Pointer to dma_handle_t structure that contains
-  *         configuration information for specified DMA channel.
-  * @retval None
-  */
-void dma_config_basic(dma_handle_t *hperh)
-{
-	dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk;
-	dma0_cbk[hperh->config.channel].err_cbk  = hperh->err_cbk;
-	dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg;
-	dma0_cbk[hperh->config.channel].err_arg  = hperh->err_arg;
-
-	dma_clear_flag_status(hperh->perh, hperh->config.channel);
-	dma_config_base(hperh->perh, DMA_CYCLE_CTRL_BASIC, &hperh->config);
-	WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
-
-	return;
-}
-
-/**
-  * @brief  Restart DMA transmitted. The DMA mode is basic.
-  *         The other parameters have not changed except 'size' and 'addr'.
-  * @param  hperh: Pointer to DMA_handle_t structure that contains
-  *               configuration information for specified DMA channel.
-  * @param  src: Source data begin pointer
-  * @param  dst: Destination data begin pointer
-  * @param  size: Size.
-  * @retval None
-  */
-void dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size)
-{
-	dma_descriptor_t *descr;
-
-	if (hperh->config.primary)
-		descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel;
-	else
-		descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel;
-
-	if (src) {
-		if (hperh->config.src_inc == DMA_DATA_INC_NONE)
-			descr->src = src;
-		else
-			descr->src = (void *)((uint32_t)src + ((size - 1) << hperh->config.data_width));
-	}
-
-	if (dst) {
-		if (hperh->config.dst_inc == DMA_DATA_INC_NONE)
-			descr->dst = dst;
-		else
-			descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width));
-	}
-
-	dma_clear_flag_status(hperh->perh, hperh->config.channel);
-	descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC;
-	descr->ctrl.n_minus_1  = size - 1;
-	WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
-
-	return;
-}
-
-/**
-  * @brief  Configure DMA channel according to the specified parameter.
-  *         The DMA mode is basic. This mode is used to carry data
-  *         from peripheral to memory or negative direction. If user want
-  *         use the dma easily, they can invoke this function.
-  * @param  DMAx: Pointer to DMA peripheral
-  * @param  src: Source data begin pointer
-  * @param  dst: Destination data begin pointer
-  * @param  size: The total number of DMA transfers that DMA cycle contains
-  * @param  msel: Input source to DMA channel @ref dma_msel_t
-  * @param  msigsel: Input signal to DMA channel @ref dma_msigsel_t
-  * @param  channel: Channel index which well be used
-  * @param  cbk: DMA complete callback function
-  *
-  * @retval None
-  *
- */
-void dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel,
-		dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg))
-{
-	dma_handle_t hperh;
-
-	assert_param(IS_DMA(DMAx));
-	dma_config_struct(&hperh.config);
-
-	if (((uint32_t)src) >= 0x40000000)
-		hperh.config.src_inc = DMA_DATA_INC_NONE;
-
-	if (((uint32_t)dst) >= 0x40000000)
-		hperh.config.dst_inc = DMA_DATA_INC_NONE;
-
-	hperh.config.src     = src;
-	hperh.config.dst     = dst;
-	hperh.config.size    = size;
-	hperh.config.msel    = msel;
-	hperh.config.msigsel = msigsel;
-	hperh.config.channel = channel;
-
-	hperh.perh     = DMAx;
-	hperh.cplt_cbk = cbk;
-	hperh.cplt_arg = NULL;
-	hperh.err_cbk  = NULL;
-
-	dma_clear_flag_status(DMAx, channel);
-	dma_config_basic(&hperh);
-
-	return;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Public_Functions_Group3 DMA Control functions
-  * @brief DMA control functions
-  *
-  * @verbatim
-    ===================================================================
-
-                    #### DMA control functions ####
-
-    ===================================================================
-    [..]
-    This subsection provides some functions allowing to control DMA:
-    (+) dma_channel_config(): Control DMA channel ENABLE/DISABLE.
-    (+) dma_interrupt_config(): Control DMA channel interrupt ENABLE or
-        DISABLE.
-    (+) dma_get_it_status(): Check whether the specified channel
-        interrupt is SET or RESET.
-    (+) dma_get_flag_status(): Check whether the specified channel
-        flag is SET or RESET.
-    (+) dma_clear_flag_status(): Clear the specified channel
-        pending flag
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure channel enable or disable. It will unbind descriptor with
-  *         channel, when channel has been disable.
-  * @param  DMAx: Pointer to DMA peripheral
-  * @param  channel: channel index
-  * @param  state: status of channel:
-  *           @arg ENABLE: Enable the channel
-  *           @arg DISABLE: Disable the channel
-  * @retval None
-  */
-void dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
-{
-	dma_descriptor_t *descr, *alt_descr;
-
-	assert_param(IS_DMA(DMAx));
-	assert_param(IS_DMA_CHANNEL(channel));
-	assert_param(IS_FUNC_STATE(state));
-
-	descr     = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
-	alt_descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
-
-	if (state) {
-		WRITE_REG(DMAx->CHENSET, (1 << channel));
-	}
-	else {
-		memset(descr, 0x00, sizeof(dma_descriptor_t));
-		memset(alt_descr, 0x00, sizeof(dma_descriptor_t));
-		WRITE_REG(DMAx->CH_SELCON[channel], 0x0);
-		WRITE_REG(DMAx->CHENCLR, (1 << channel));
-	}
-
-	return;
-}
-
-/**
-  * @brief  Configure the interrupt enable or disable
-  * @param  DMAx: Pointer to DMA peripheral
-  * @param  channel: Channel index or DMA_ERR.
-  *           @arg 0~5: Channel index
-  *           @arg DMA_ERR: DMA bus error
-  * @param  state: status of channel:
-  *           @arg ENABLE: Enable the channel
-  *           @arg DISABLE: Disable the channel
-  *
-  * @retval None
-  */
-void dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
-{
-	assert_param(IS_DMA(DMAx));
-	assert_param(IS_DMA_IT_TYPE(channel));
-	assert_param(IS_FUNC_STATE(state));
-
-	if (state)
-		SET_BIT(DMAx->IER, (1 << channel));
-	else
-		CLEAR_BIT(DMAx->IER, (1 << channel));
-
-	return;
-}
-
-/**
-  * @brief  Check whether the specified channel interrupt
-  *         is set or reset
-  * @param  DMAx: Pointer to DMA peripheral
-  * @param  channel: Channel index or DMA_ERR
-  *           @arg 0~5: Channel index
-  *           @arg DMA_ERR: DMA bus error
-  * @retval Status:
-  *           - SET: Channel interrupt is set
-  *           - RESET: Channel interrupt is reset
-  */
-it_status_t dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel)
-{
-	assert_param(IS_DMA(DMAx));
-	assert_param(IS_DMA_IT_TYPE(channel));
-
-	if (READ_BIT(DMAx->IER, (1 << channel)))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Check whether the specified channel flag
-  *         is set or reset
-  * @param  DMAx: Pointer to DMA peripheral
-  * @param  channel: Channel index or DMA_ERR
-  *           @arg 0~5: Channel index
-  *           @arg DMA_ERR: DMA bus error
-  * @retval Status:
-  *           - SET: Channel flag is set
-  *           - RESET: Channel flag is reset
-  */
-flag_status_t dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
-{
-	assert_param(IS_DMA(DMAx));
-	assert_param(IS_DMA_IT_TYPE(channel));
-
-	if (READ_BIT(DMAx->IFLAG, (1 << channel)))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Clear the specified channel pending flag
-  * @param  DMAx: Pointer to DMA peripheral
-  * @param  channel: Channel index or DMA_ERR
-  *           @arg 0~5: Channel index
-  *           @arg DMA_ERR: DMA bus error
-  * @retval None
-  */
-void dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
-{
-	assert_param(IS_DMA(DMAx));
-	assert_param(IS_DMA_IT_TYPE(channel));
-
-	WRITE_REG(DMAx->ICFR, (1 << channel));
-	return;
-}
-
-/**
-  * @brief  Interrupt callback function.
-  * @note   This function is declared as __weak to be overwritten in case of other
-  *         implementations in user file.
-  * @retval None
-  */
-__weak void dma0_irq_cbk(void)
-{
-	return;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* ALD_DMA */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash.c

@@ -1,508 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_flash.c
-  * @brief   FLASH module driver.
-  *
-  * @version V1.0
-  * @date    20 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  *
-  *********************************************************************************
-  * @verbatim
-  ==============================================================================
-                    ##### FLASH Peripheral features #####
-  ==============================================================================
-  [..]
-  Base address is 0x00000000
-
-  [..]
-  FLASH have just one programme mode , word programme.
-  word programme can programme 8 bytes once ;
-
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-   (#) programme flash using flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
-       (++) call the function and supply all the three paraments is needs, addr means
-            the first address to write in this operation, buf is a pointer to the data which
-	    need writing to flash.
-
-   (#) erase flash using flash_erase(uint32_t addr, uint16_t len)
-       (++) call the function and supply two paraments, addr is the first address to erase,
-            len is the length to erase
-
-   (#) read flash using flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len)
-       (++) read the flash and save to a buffer, ram_addr is the buffer's first address,
-            addr is the start reading address in flash, len is the length need read
-
-    @endverbatim
-  */
-
-#include "ald_flash.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup FLASH FLASH
-  * @brief FLASH module driver
-  * @{
-  */
-
-#ifdef ALD_FLASH
-
-/** @addtogroup FLASH_Private_Types
-  * @{
-  */
-
-/* opration buffer, global variable*/
-static uint8_t write_buf[FLASH_PAGE_SIZE];
-static op_cmd_type OP_CMD = OP_FLASH;
-
-#if defined ( __ICCARM__ )
-#define __RAMFUNC       __ramfunc
-#else
-#define __RAMFUNC
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup Flash_Private_Functions Flash Private Functions
-  *  @brief   Flash Private functions
-  * @{
-  */
-
-/**
-  * @brief  Unlock the flash.
-  * @retval Status, see @ref ald_status_t.
-  */
-__RAMFUNC static ald_status_t flash_unlock(void)
-{
-	uint16_t i;
-	uint16_t op_cmd = OP_CMD;
-
-	if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
-		return ERROR;
-
-	FLASH_REG_UNLOCK();
-	FLASH_IAP_ENABLE();
-	FLASH_REQ();
-
-	for (i = 0; i < 0xFFFF; i++) {
-		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))
-			break;
-	}
-
-	return i == 0xFFFF ? ERROR : OK;
-}
-
-/**
-  * @brief  Lock the flash.
-  * @retval Status, see @ref ald_status_t.
-  */
-__RAMFUNC static ald_status_t flash_lock(void)
-{
-	uint16_t i;
-	uint16_t op_cmd = OP_CMD;
-
-	FLASH_REG_UNLOCK();
-	WRITE_REG(MSC->FLASHCR, 0x0);
-
-	for (i = 0; i < 0xFFFF; i++) {
-		if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)))
-			break;
-	}
-
-	return i == 0xFFFF ? ERROR : OK;
-}
-
-/**
-  * @brief  Erase one page.
-  * @param  addr: The erased page's address
-  * @retval Status, see @ref ald_status_t.
-  */
-__RAMFUNC static ald_status_t flash_page_erase(uint32_t addr)
-{
-	uint32_t i;
-	uint16_t op_cmd = OP_CMD;
-
-	__disable_irq();
-	if (flash_unlock() != OK)
-		goto end;
-
-	if (op_cmd == OP_FLASH) {
-		CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
-		MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS);
-	}
-	else {
-		SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
-		MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS);
-	}
-
-	WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE);
-
-	for (i = 0; i < 0xFFFF; i++) {
-		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
-			continue;
-		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK))
-			goto end;
-		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK))
-			goto end;
-		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK))
-			break;
-	}
-
-	if (i == 0xFFFF)
-		goto end;
-
-	if (flash_lock() == ERROR)
-		goto end;
-
-	__enable_irq();
-	return OK;
-end:
-
-	if (flash_lock() == ERROR)
-		while (1);
-
-	__enable_irq();
-	return ERROR;
-}
-
-/**
-  * @brief  Programme a word.
-  * @param  addr: The word's address, it is must word align.
-  * @param  data: The 8 bytes data be write.
-  * @param  len: The number of data be write.
-  * @param  fifo: Choose if use fifo.
-  * @retval Status, see @ref ald_status_t.
-  */
-__RAMFUNC static ald_status_t flash_word_program(uint32_t addr, uint32_t data[], uint32_t len, uint32_t fifo)
-{
-	uint16_t i;
-	uint16_t prog_len;
-	uint32_t *p_data = data;
-	uint16_t op_cmd = OP_CMD;
-
-	__disable_irq();
-	if (flash_unlock() != OK)
-		goto end;
-
-	if (op_cmd == OP_FLASH)
-		CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
-	else
-		SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
-
-	MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS);
-	MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS);
-
-	for (prog_len = 0; prog_len < len; prog_len++) {
-		if (fifo) {
-			WRITE_REG(MSC->FLASHFIFO, p_data[0]);
-			WRITE_REG(MSC->FLASHFIFO, p_data[1]);
-		}
-		else {
-			WRITE_REG(MSC->FLASHDL, p_data[0]);
-			WRITE_REG(MSC->FLASHDH, p_data[1]);
-			WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP);
-		}
-
-		p_data += 2;
-
-		for (i = 0; i < 0xFFFF; i++) {
-			if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
-				continue;
-			if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK))
-				break;
-		}
-	}
-	if (i == 0xFFFF)
-		goto end;
-
-	if (flash_lock() == ERROR)
-		goto end;
-
-	__enable_irq();
-	return OK;
-end:
-	if (flash_lock() == ERROR)
-		while (1);
-
-	__enable_irq();
-	return ERROR;
-}
-
-/**
-  * @brief  Read data from flash, and store in buffer.
-  * @param  ram_addr: The stored buffer's address.
-  * @param  addr: The start address in flash to read.
-  * @param  len: The length of byte to read.
-  * @retval Status, see @ref ald_status_t.
-  */
-__RAMFUNC static ald_status_t __flash_read(uint32_t ram_addr[], uint32_t addr, uint32_t len)
-{
-	uint32_t i;
-
-	if (!len)
-		return ERROR;
-
-	for (i = 0; i < len; i++) {
-		ram_addr[i] = ((uint32_t *)addr)[i];
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  Check whether the flash between the given address section
-  *         have been writen, if it have been writen, return TRUE, else
-  *         return FALSE.
-  * @param  begin_addr: The begin address.
-  * @param  end_addr: The end address.
-  * @retval The check result
-  *         - TRUE
-  *         - FALSE
-  */
-__RAMFUNC static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr)
-{
-	uint8_t* addr_to_read;
-	uint8_t value;
-	uint32_t index;
-
-	/* Check the parameters */
-	assert_param(IS_FLASH_ADDRESS(begin_addr));
-	assert_param(IS_FLASH_ADDRESS(end_addr));
-
-	addr_to_read = (uint8_t *)begin_addr;
-	index        = begin_addr;
-	value        = 0xFF;
-
-	if (begin_addr > end_addr)
-		return FALSE;
-
-	while (index++ <= end_addr) {
-		value = *addr_to_read++;
-
-		if (value != 0xFF)
-			break;
-	}
-
-	return value == 0xFF ? FALSE : TRUE;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
-  * @verbatim
- ===============================================================================
-              ##### Flash oprate functions #####
- ===============================================================================
-  [..]
-    This section provides functions allowing to operate flash, such as read and write.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Write the give bytes to the given address section.
-  * @param  addr: The start address to write.
-  * @param  buf: The bytes' address.
-  * @param  len: The length to write,and multiple of 2.
-  * @retval Status, see @ref ald_status_t.
-  */
-
-__RAMFUNC ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
-{
-	uint32_t index = 0;
-	uint32_t para = 0;
-	uint32_t index2 = 0;
-	uint32_t start_write_addr;
-	uint32_t end_write_addr;
-	uint32_t start_word_addr;
-	uint32_t end_word_addr;
-	uint16_t len_to_write;
-	uint32_t len_index;
-	type_bool_t need_erase_page;
-
-	assert_param(IS_FLASH_ADDRESS(addr));
-	assert_param(IS_FLASH_ADDRESS(addr + len - 1));
-
-	len_to_write = len;
-
-	while (len_to_write > 0) {
-		need_erase_page = FALSE;
-
-		for (index = 0; index < FLASH_PAGE_SIZE; index++)
-			write_buf[index] = 0xFF;
-
-		start_write_addr = addr + (len - len_to_write);
-		end_write_addr   = addr + len - 1;
-		end_write_addr   = FLASH_PAGE_ADDR(start_write_addr) == FLASH_PAGE_ADDR(end_write_addr)
-		                   ? end_write_addr : FLASH_PAGEEND_ADDR(start_write_addr);
-		need_erase_page  = page_have_writen(FLASH_WORD_ADDR(start_write_addr),
-		                                    FLASH_WORDEND_ADDR(end_write_addr));
-
-		if (need_erase_page) {
-			if (ERROR == __flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr),
-                                 		  FLASH_PAGE_SIZE >> 2))
-				return ERROR;
-
-			if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr)))
-				return ERROR;
-
-			para   = end_write_addr & (FLASH_PAGE_SIZE - 1);
-			index  = start_write_addr & (FLASH_PAGE_SIZE - 1);
-			index2 = len - len_to_write;
-
-			while (index <= para)
-				write_buf[index++] = buf[index2++];
-
-			index2     = 0;
-			index      = FLASH_PAGE_ADDR(start_write_addr);
-			para       = FLASH_PAGE_ADDR(start_write_addr) + FLASH_PAGE_SIZE;
-			len_index  = FLASH_PAGE_SIZE;
-		}
-		else {
-			para   = end_write_addr & (FLASH_PAGE_SIZE - 1);
-			index  = start_write_addr & (FLASH_PAGE_SIZE - 1);
-			index2 = len - len_to_write;
-
-			while (index <= para)
-				write_buf[index++] = buf[index2++];
-
-			start_word_addr = FLASH_WORD_ADDR(start_write_addr);
-			end_word_addr   = FLASH_WORDEND_ADDR(end_write_addr);
-			index2          = (FLASH_WORD_ADDR(start_word_addr) - FLASH_PAGE_ADDR(start_word_addr));
-			index           = start_word_addr;
-			len_index       = end_word_addr - start_word_addr + 1;
-		}
-
-		if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO))
-			return ERROR;
-
-		len_to_write = len_to_write - (end_write_addr - start_write_addr + 1);
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  erase The flash between the given address section.
-  * @param  addr: The start address to erase.
-  * @param  len: The length to erase.
-  * @retval Status, see @ref ald_status_t.
-  */
-__RAMFUNC ald_status_t flash_erase(uint32_t addr, uint16_t len)
-{
-	int32_t	index;
-	int32_t para;
-	int32_t start_erase_addr;
-	int32_t end_erase_addr;
-	uint16_t len_not_erase;
-	uint32_t len_index;
-	type_bool_t page_need_save;
-
-	assert_param(IS_FLASH_ADDRESS(addr));
-	assert_param(IS_FLASH_ADDRESS(addr + len - 1));
-
-	len_not_erase = len;
-
-	while (len_not_erase > 0) {
-		page_need_save = FALSE;
-
-		start_erase_addr = addr + len - len_not_erase;
-		end_erase_addr   = addr + len - 1;
-		end_erase_addr   = (FLASH_PAGE_ADDR(start_erase_addr) == FLASH_PAGE_ADDR(end_erase_addr))
-		                    ? end_erase_addr : FLASH_PAGEEND_ADDR(start_erase_addr);
-
-		if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr)) {
-			if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1)))
-				page_need_save = TRUE;
-		}
-		if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) {
-			if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr)))
-				page_need_save = TRUE;
-		}
-
-		if (page_need_save) {
-			if (ERROR == __flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr),
-			                                                     FLASH_PAGE_SIZE >> 2)) {
-				__enable_irq();
-				return ERROR;
-			}
-		}
-
-		if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr))) {
-			__enable_irq();
-			return ERROR;
-		}
-
-		if (page_need_save) {
-			para  = end_erase_addr & (FLASH_PAGE_SIZE - 1);
-			index = start_erase_addr & (FLASH_PAGE_SIZE - 1);
-
-			while (index <= para)
-				write_buf[index++] = 0xFF;
-
-			index     = FLASH_PAGE_ADDR(start_erase_addr);
-			len_index = FLASH_PAGE_SIZE;
-			if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) {
-				__enable_irq();
-				return ERROR;
-			}
-		}
-		len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1);
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  read the specified length bytes from flash, and store to the specified area.
-  * @param  ram_addr: the specified area to store the reading bytes.
-  * @param  addr: the start address.
-  * @param  len: the length to read.
-  * @retval Status, see @ref ald_status_t.
-  */
-__RAMFUNC ald_status_t flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len)
-{
-	uint32_t temp;
-
-	assert_param(IS_4BYTES_ALIGN(ram_addr));
-	assert_param(IS_FLASH_ADDRESS(addr));
-	assert_param(IS_FLASH_ADDRESS(addr + len - 1));
-
-	temp = (uint32_t)ram_addr;
-
-	if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0))
-		return ERROR;
-
-	return __flash_read(ram_addr, addr, len) == ERROR ? ERROR : OK;
-}
-
-/**
-  * @}
-  */
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_i2c.c

@@ -1,3136 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_i2c.c
-  * @brief   I2C module driver.
-  *
-  * @version V1.0
-  * @date    15 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
- @verbatim
- ==============================================================================
-                       ##### How to use this driver #####
- ==============================================================================
- [..]
-   The I2C driver can be used as follows:
-
-   (#) Declare a i2c_handle_t handle structure, for example:
-       i2c_handle_t  hperh;
-
-   (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
-       Dual Addressing mode, Own Address2, General call and Nostretch mode in the hperh init structure.
-
-   (#) Initialize the I2C registers by calling the i2c_init().
-   (#) To check if target device is ready for communication, use the function i2c_is_device_ready()
-
-   (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
-
-   *** Polling mode IO operation ***
-   =================================
-   [..]
-     (+) Transmit in master mode an amount of data in blocking mode using i2c_master_send()
-     (+) Receive in master mode an amount of data in blocking mode using i2c_master_recv()
-     (+) Transmit in slave mode an amount of data in blocking mode using i2c_slave_send()
-     (+) Receive in slave mode an amount of data in blocking mode using i2c_slave_recv()
-
-   *** Polling mode IO MEM operation ***
-   =====================================
-   [..]
-     (+) Write an amount of data in blocking mode to a specific memory address using i2c_mem_write()
-     (+) Read an amount of data in blocking mode from a specific memory address using i2c_mem_read()
-
-
-   *** Interrupt mode IO operation ***
-   ===================================
-   [..]
-     (+) The I2C interrupts should have the highest priority in the application in order
-         to make them uninterruptible.
-     (+) Transmit in master mode an amount of data in non-blocking mode using i2c_master_send_by_it()
-     (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can
-          add his own code by customization of function pointer hperh->master_tx_cplt_cbk()
-     (+) Receive in master mode an amount of data in non-blocking mode using i2c_master_recv_by_it()
-     (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can
-          add his own code by customization of function pointer hperh->master_rx_cplt_cbk()
-     (+) Transmit in slave mode an amount of data in non-blocking mode using i2c_slave_send_by_it()
-     (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can
-          add his own code by customization of function pointer hperh->slave_tx_cplt_cbk()
-     (+) Receive in slave mode an amount of data in non-blocking mode using i2c_slave_recv_by_it()
-     (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can
-          add his own code by customization of function pointer hperh->slave_rx_cplt_cbk()
-     (+) In case of transfer Error, hperh->error_callback() function is executed and user can
-          add his own code by customization of function pointer hperh->error_callback()
-
-   *** Interrupt mode IO MEM operation ***
-   =======================================
-   [..]
-     (+) The I2C interrupts should have the highest priority in the application in order
-         to make them uninterruptible.
-     (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
-         i2c_mem_write_by_it()
-     (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can
-          add his own code by customization of function pointer hperh->mem_tx_cplt_cbk()
-     (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
-         i2c_mem_read_by_it()
-     (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can
-          add his own code by customization of function pointer hperh->mem_rx_cplt_cbk()
-     (+) In case of transfer Error, hperh->error_callback() function is executed and user can
-          add his own code by customization of function pointer hperh->error_callback()
-
-   *** DMA mode IO operation ***
-   ==============================
-   [..]
-     (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
-         i2c_master_send_by_dma()
-     (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can
-          add his own code by customization of function pointer hperh->master_tx_cplt_cbk()
-     (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
-         i2c_master_recv_by_dma()
-     (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can
-          add his own code by customization of function pointer hperh->master_rx_cplt_cbk()
-     (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
-         i2c_slave_send_by_dma()
-     (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can
-          add his own code by customization of function pointer hperh->slave_tx_cplt_cbk()
-     (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
-         i2c_slave_recv_by_dma()
-     (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can
-          add his own code by customization of function pointer hperh->slave_rx_cplt_cbk()
-     (+) In case of transfer Error, hperh->error_callback() function is executed and user can
-          add his own code by customization of function pointer hperh->error_callback()
-
-   *** DMA mode IO MEM operation ***
-   =================================
-   [..]
-     (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
-         i2c_mem_write_by_dma()
-     (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can
-          add his own code by customization of function pointer hperh->mem_tx_cplt_cbk()
-     (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
-         i2c_mem_read_by_dma()
-     (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can
-          add his own code by customization of function pointer hperh->mem_rx_cplt_cbk()
-     (+) In case of transfer Error, hperh->error_callback() function is executed and user can
-          add his own code by customization of function pointer hperh->error_callback()
-
-
-    *** I2C ald_status_t driver macros list ***
-    ==================================
-    [..]
-      Below the list of most used macros in I2C ald_status_t driver.
-
-     (+) I2C_ENABLE: Enable the I2C peripheral
-     (+) I2C_DISABLE: Disable the I2C peripheral
-      (@) You can refer to the I2C ald_status_t driver header file for more useful macros
-
-
-    *** I2C Workarounds linked to Silicon Limitation ***
-    ====================================================
-    [..]
-      Below the list of all silicon limitations implemented for library on our product.
-      (@) See ErrataSheet to know full silicon limitation list of your product.
-
-      (#) Workarounds Implemented inside I2C library
-         (##) Wrong data read into data register (Polling and Interrupt mode)
-         (##) Start cannot be generated after a misplaced Stop
-         (##) Some software events must be managed before the current byte is being transferred:
-              Workaround: Use DMA in general, except when the Master is receiving a single byte.
-              For Interupt mode, I2C should have the highest priority in the application.
-         (##) Mismatch on the "Setup time for a repeated Start condition" timing parameter:
-              Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if
-              supported by the slave.
-         (##) Data valid time (tVD;DAT) violated without the OVR flag being set:
-              Workaround: If the slave device allows it, use the clock stretching mechanism
-              by programming no_stretch = I2C_NOSTRETCH_DISABLE in i2c_init.
-
- @endverbatim
- *********************************************************************************
- */
-
-#include "ald_i2c.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup I2C I2C
-  * @brief I2C module driver
-  * @{
-  */
-#ifdef ALD_I2C
-
-/** @addtogroup I2C_Private_Constants I2C Private Constants
-  * @{
-  */
-#define I2C_TIMEOUT_FLAG          (__systick_interval / 20 + 1)
-#define I2C_TIMEOUT_ADDR_SLAVE    (__systick_interval * 10)
-#define I2C_TIMEOUT_BUSY_FLAG     (__systick_interval * 10)
-#define I2C_MAX_DELAY             0xFFFFFFFF
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Private_Functions I2C Private Functions
-  * @{
-  */
-#ifdef ALD_DMA
-static void i2c_dma_master_send_cplt(void *argv);
-static void i2c_dma_master_recv_cplt(void *argv);
-static void i2c_dma_slave_send_cplt(void *argv);
-static void i2c_dma_slave_recv_cplt(void *argv);
-static void i2c_dma_mem_send_cplt(void *argv);
-static void i2c_dma_mem_recv_cplt(void *argv);
-static void i2c_dma_error(void *argv);
-#endif
-static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout);
-static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout);
-static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                                      uint16_t add_size, uint32_t timeout);
-static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                                     uint16_t add_size, uint32_t timeout);
-static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag,
-                                                flag_status_t status, uint32_t timeout);
-static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, uint32_t timeout);
-static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout);
-static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeout);
-static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout);
-static ald_status_t i2c_wait_stop_to_timeout(i2c_handle_t *hperh, uint32_t timeout);
-static ald_status_t i2c_is_ack_failed(i2c_handle_t *hperh);
-static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh);
-static ald_status_t i2c_master_send_btf(i2c_handle_t *hperh);
-static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh);
-static ald_status_t i2c_master_recv_btf(i2c_handle_t *hperh);
-static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh);
-static ald_status_t i2c_slave_send_btf(i2c_handle_t *hperh);
-static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh);
-static ald_status_t i2c_slave_recv_btf(i2c_handle_t *hperh);
-static ald_status_t i2c_slave_addr(i2c_handle_t *hperh);
-static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh);
-static ald_status_t i2c_slave_af(i2c_handle_t *hperh);
-static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk);
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Public_Functions I2C Public functions
-  * @{
-  */
-
-/** @defgroup I2C_Public_Functions_Group1 Initialization functions
-  * @brief     Initialization and Configuration functions
-  *
-@verbatim
- ===============================================================================
-              ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          de-initialiaze the I2Cx peripheral:
-
-      (+) Call the function i2c_init() to configure the selected device with
-          the selected configuration:
-        (++) Communication Speed
-        (++) Duty cycle
-        (++) Addressing mode
-        (++) Own Address 1
-        (++) Dual Addressing mode
-        (++) Own Address 2
-        (++) General call mode
-        (++) Nostretch mode
-
-      (+) Call the function i2c_reset() to restore the default configuration
-          of the selected I2Cx periperal.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the I2C according to the specified parameters
-  *         in the i2c_init_t and initialize the associated handle.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_init(i2c_handle_t *hperh)
-{
-	uint32_t freqrange = 0;
-	uint32_t pclk1 = 0;
-
-	if (hperh == NULL)
-		return ERROR;
-
-	/* Check the parameters */
-	assert_param(IS_I2C_TYPE(hperh->perh));
-	assert_param(IS_I2C_CLOCK_SPEED(hperh->init.clk_speed));
-	assert_param(IS_I2C_DUTY_CYCLE(hperh->init.duty));
-	assert_param(IS_I2C_OWN_ADDRESS1(hperh->init.own_addr1));
-	assert_param(IS_I2C_ADDRESSING_MODE(hperh->init.addr_mode));
-	assert_param(IS_I2C_GENERAL_CALL(hperh->init.general_call));
-	assert_param(IS_I2C_NO_STRETCH(hperh->init.no_stretch));
-
-	if (hperh->init.dual_addr == I2C_DUALADDR_ENABLE)
-		assert_param(IS_I2C_OWN_ADDRESS2(hperh->init.own_addr2));
-
-	if (hperh->state == I2C_STATE_RESET)
-		hperh->lock = UNLOCK;
-
-	hperh->state = I2C_STATE_BUSY;
-	pclk1 = cmu_get_pclk1_clock();
-	I2C_DISABLE(hperh);
-
-	freqrange = I2C_FREQ_RANGE(pclk1);
-	WRITE_REG(hperh->perh->CON2, freqrange);
-	WRITE_REG(hperh->perh->RT, I2C_RISE_TIME(freqrange, hperh->init.clk_speed));
-	WRITE_REG(hperh->perh->CKCFG, i2c_configure_speed(hperh, pclk1));
-	WRITE_REG(hperh->perh->CON1, hperh->init.general_call);
-	SET_BIT(hperh->perh->CON1, hperh->init.no_stretch);
-	WRITE_REG(hperh->perh->ADDR1, (hperh->init.addr_mode | hperh->init.own_addr1));
-	WRITE_REG(hperh->perh->ADDR2, (hperh->init.dual_addr | hperh->init.own_addr2));
-
-	I2C_ENABLE(hperh);
-
-	hperh->error_code = I2C_ERROR_NONE;
-	hperh->state      = I2C_STATE_READY;
-	hperh->mode       = I2C_MODE_NONE;
-
-	return OK;
-}
-
-/**
-  * @brief  DeInitialize the I2C peripheral.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_reset(i2c_handle_t *hperh)
-{
-	if (hperh == NULL)
-		return ERROR;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-
-	hperh->state = I2C_STATE_BUSY;
-	I2C_DISABLE(hperh);
-
-	hperh->error_code = I2C_ERROR_NONE;
-	hperh->state      = I2C_STATE_RESET;
-	hperh->mode       = I2C_MODE_NONE;
-
-	__UNLOCK(hperh);
-
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Public_Functions_Group2 Input and Output operation functions
-  *  @brief   Data transfers functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the I2C data
-    transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode : The communication is performed in the polling mode.
-            The status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) No-Blocking mode : The communication is performed using Interrupts
-            or DMA. These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the
-            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-
-    (#) Blocking mode functions are :
-        (++) i2c_master_send()
-        (++) i2c_master_recv()
-        (++) i2c_slave_send()
-        (++) i2c_slave_recv()
-        (++) i2c_mem_write()
-        (++) i2c_mem_read()
-        (++) i2c_is_device_ready()
-
-    (#) No-Blocking mode functions with Interrupt are :
-        (++) i2c_master_send_by_it()
-        (++) i2c_master_recv_by_it()
-        (++) i2c_slave_send_by_it()
-        (++) i2c_slave_recv_by_it()
-        (++) i2c_mem_write_by_it()
-        (++) i2c_mem_read_by_it()
-
-    (#) No-Blocking mode functions with DMA are :
-        (++) i2c_master_send_by_dma()
-        (++) i2c_master_recv_by_dma()
-        (++) i2c_slave_send_by_dma()
-        (++) i2c_slave_recv_by_dma()
-        (++) i2c_mem_write_by_dma()
-        (++) i2c_mem_read_by_dma()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) hperh->mem_tx_cplt_cbk()
-        (++) hperh->mem_rx_cplt_cbk()
-        (++) hperh->master_tx_cplt_cbk()
-        (++) hperh->master_rx_cplt_cbk()
-        (++) hperh->slave_tx_cplt_cbk()
-        (++) hperh->slave_rx_cplt_cbk()
-        (++) hperh->error_callback()
-
-@endverbatim
- * @{
- */
-
-/**
-  * @brief  Transmits in master mode an amount of data in blocking mode.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf,
-                                 uint16_t size, uint32_t timeout)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_TX;
-	hperh->mode       = I2C_MODE_MASTER;
-	hperh->error_code = I2C_ERROR_NONE;
-
-	if (i2c_master_req_write(hperh, dev_addr, timeout) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-		else {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-
-	I2C_CLEAR_ADDRFLAG(hperh);
-
-	while (size > 0) {
-		if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) {
-			if (hperh->error_code == I2C_ERROR_AF) {
-				SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-				__UNLOCK(hperh);
-				return ERROR;
-			}
-			else {
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-		}
-
-		hperh->perh->DATA = (*buf++);
-		--size;
-
-		if ((i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) {
-			hperh->perh->DATA = (*buf++);
-			--size;
-		}
-	}
-
-	if (i2c_wait_btf_to_timeout(hperh, timeout) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-		else {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-
-	SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-	hperh->state = I2C_STATE_READY;
-	__UNLOCK(hperh);
-	return OK;
-
-}
-
-/**
-  * @brief  Receives in master mode an amount of data in blocking mode.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf,
-                                uint16_t size, uint32_t timeout)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-	__LOCK(hperh);
-
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_RX;
-	hperh->mode       = I2C_MODE_MASTER;
-	hperh->error_code = I2C_ERROR_NONE;
-
-	if (i2c_master_req_read(hperh, dev_addr, timeout) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-		else {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-
-	if (size == 1) {
-		CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-		__disable_irq();
-		I2C_CLEAR_ADDRFLAG(hperh);
-		SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-		__enable_irq();
-	}
-	else if (size == 2) {
-		SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-		__disable_irq();
-		I2C_CLEAR_ADDRFLAG(hperh);
-		CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-		__enable_irq();
-	}
-	else {
-		SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-		I2C_CLEAR_ADDRFLAG(hperh);
-	}
-
-	while (size > 3) {
-		if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) {
-			if (hperh->error_code == I2C_ERROR_TIMEOUT) {
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-			else {
-				__UNLOCK(hperh);
-				return ERROR;
-			}
-		}
-
-		(*buf++) = hperh->perh->DATA;
-		--size;
-
-		if (i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) {
-			(*buf++) = hperh->perh->DATA;
-			--size;
-		}
-	}
-
-	switch (size) {
-	case 1:
-		if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) {
-			if (hperh->error_code == I2C_ERROR_TIMEOUT) {
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-			else {
-				__UNLOCK(hperh);
-				return ERROR;
-			}
-		}
-
-		(*buf++) = hperh->perh->DATA;
-		break;
-
-	case 2:
-		if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-
-		__disable_irq();
-		SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-		(*buf++) = hperh->perh->DATA;
-		__enable_irq();
-		(*buf++) = hperh->perh->DATA;
-		break;
-
-	case 3:
-		if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-
-		CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-		__disable_irq();
-		(*buf++) = hperh->perh->DATA;
-
-		if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) {
-			__UNLOCK(hperh);
-			__enable_irq();
-			return TIMEOUT;
-		}
-
-		SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-		(*buf++) = hperh->perh->DATA;
-		__enable_irq();
-		(*buf++) = hperh->perh->DATA;
-		break;
-
-	default :
-		break;
-	}
-
-	hperh->state = I2C_STATE_READY;
-	hperh->mode  = I2C_MODE_NONE;
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Transmits in slave mode an amount of data in blocking mode.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_TX;
-	hperh->mode       = I2C_MODE_SLAVE;
-	hperh->error_code = I2C_ERROR_NONE;
-	SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) {
-		__UNLOCK(hperh);
-		return TIMEOUT;
-	}
-
-	I2C_CLEAR_ADDRFLAG(hperh);
-
-	if (hperh->init.addr_mode == I2C_ADDR_10BIT) {
-		if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-
-		I2C_CLEAR_ADDRFLAG(hperh);
-	}
-
-	while (size > 0) {
-		if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) {
-			CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-
-			if (hperh->error_code == I2C_ERROR_AF) {
-				__UNLOCK(hperh);
-				return ERROR;
-			}
-			else {
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-		}
-
-		hperh->perh->DATA = (*buf++);
-		--size;
-
-		if ((i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) {
-			hperh->perh->DATA = (*buf++);
-			--size;
-		}
-	}
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_AF, RESET, timeout) != OK) {
-		__UNLOCK(hperh);
-		return TIMEOUT;
-	}
-
-	i2c_clear_flag_status(hperh, I2C_FLAG_AF);
-
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-	hperh->state = I2C_STATE_READY;
-	hperh->mode  = I2C_MODE_NONE;
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in blocking mode
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_RX;
-	hperh->mode       = I2C_MODE_SLAVE;
-	hperh->error_code = I2C_ERROR_NONE;
-	SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) {
-		__UNLOCK(hperh);
-		return TIMEOUT;
-	}
-
-	I2C_CLEAR_ADDRFLAG(hperh);
-
-	while (size > 0) {
-		if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) {
-			hperh->perh->CON1 &= ~I2C_CON1_ACKEN;
-
-			if (hperh->error_code == I2C_ERROR_TIMEOUT) {
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-			else {
-				__UNLOCK(hperh);
-				return ERROR;
-			}
-		}
-
-		(*buf++) = hperh->perh->DATA;
-		--size;
-
-		if ((i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) {
-			(*buf++) = hperh->perh->DATA;
-			--size;
-		}
-	}
-
-	if (i2c_wait_stop_to_timeout(hperh, I2C_TIMEOUT_FLAG) != OK) {
-		CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-		if (hperh->error_code == I2C_ERROR_AF) {
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-		else {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-
-	__I2C_CLEAR_STOPFLAG(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-	hperh->state = I2C_STATE_READY;
-	hperh->mode  = I2C_MODE_NONE;
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_TX;
-	hperh->mode       = I2C_MODE_MASTER;
-	hperh->error_code = I2C_ERROR_NONE;
-	hperh->p_buff     = buf;
-	hperh->xfer_size  = size;
-	hperh->xfer_count = size;
-
-	if (i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-		else {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-
-	I2C_CLEAR_ADDRFLAG(hperh);
-
-	__UNLOCK(hperh);
-
-	/* Note : The I2C interrupts must be enabled after unlocking current process
-	 *        to avoid the risk of I2C interrupt handle execution before current
-	 *        process unlock */
-	i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE);
-	i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE);
-	i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE);
-	return OK;
-}
-
-/**
-  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_RX;
-	hperh->mode       = I2C_MODE_MASTER;
-	hperh->error_code = I2C_ERROR_NONE;
-	hperh->p_buff     = buf;
-	hperh->xfer_size  = size;
-	hperh->xfer_count = size;
-
-	if (i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-		else {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-
-	if (hperh->xfer_count == 1) {
-		CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-		I2C_CLEAR_ADDRFLAG(hperh);
-		SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-	}
-	else if (hperh->xfer_count == 2) {
-		SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-		I2C_CLEAR_ADDRFLAG(hperh);
-		CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-	}
-	else {
-		SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-		I2C_CLEAR_ADDRFLAG(hperh);
-	}
-
-	__UNLOCK(hperh);
-
-	/* Note : The I2C interrupts must be enabled after unlocking current process
-	 *        to avoid the risk of I2C interrupt handle execution before current
-	 *        process unlock */
-	i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE);
-	i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE);
-	i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE);
-	return OK;
-}
-
-/**
-  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_TX;
-	hperh->mode       = I2C_MODE_SLAVE;
-	hperh->error_code = I2C_ERROR_NONE;
-	hperh->p_buff     = buf;
-	hperh->xfer_size  = size;
-	hperh->xfer_count = size;
-	SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-	__UNLOCK(hperh);
-
-	/* Note : The I2C interrupts must be enabled after unlocking current process
-	 *        to avoid the risk of I2C interrupt handle execution before current
-	 *        process unlock */
-	i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE);
-	i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE);
-	i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE);
-
-	return OK;
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_RX;
-	hperh->mode       = I2C_MODE_SLAVE;
-	hperh->error_code = I2C_ERROR_NONE;
-	hperh->p_buff     = buf;
-	hperh->xfer_size  = size;
-	hperh->xfer_count = size;
-	SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-	__UNLOCK(hperh);
-
-	/* Note : The I2C interrupts must be enabled after unlocking current process
-	 *        to avoid the risk of I2C interrupt handle execution before current
-	 *        process unlock */
-	i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE);
-	i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE);
-	i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE);
-
-	return OK;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  channel: DMA channel as I2C transmit
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf,
-                                     uint16_t size, uint8_t channel)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_TX;
-	hperh->mode       = I2C_MODE_MASTER;
-	hperh->error_code = I2C_ERROR_NONE;
-	hperh->p_buff     = buf;
-	hperh->xfer_size  = size;
-	hperh->xfer_count = size;
-
-	if (hperh->hdmatx.perh == NULL)
-		hperh->hdmatx.perh = DMA0;
-
-	hperh->hdmatx.cplt_cbk = i2c_dma_master_send_cplt;
-	hperh->hdmatx.cplt_arg = hperh;
-	hperh->hdmatx.err_cbk  = i2c_dma_error;
-	hperh->hdmatx.err_arg  = hperh;
-
-	dma_config_struct(&hperh->hdmatx.config);
-	hperh->hdmatx.config.src        = (void *)buf;
-	hperh->hdmatx.config.dst        = (void *)&hperh->perh->DATA;
-	hperh->hdmatx.config.size       = size;
-	hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE;
-	hperh->hdmatx.config.src_inc    = DMA_DATA_INC_BYTE;
-	hperh->hdmatx.config.dst_inc    = DMA_DATA_INC_NONE;
-	hperh->hdmatx.config.msel       = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
-	hperh->hdmatx.config.msigsel    = DMA_MSIGSEL_I2C_TXEMPTY;
-	hperh->hdmatx.config.channel    = channel;
-	dma_config_basic(&hperh->hdmatx);
-
-	if (i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-		else {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-
-	SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN);
-	I2C_CLEAR_ADDRFLAG(hperh);
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  channel: DMA channel as I2C receive
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf,
-                                    uint16_t size, uint8_t channel)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_RX;
-	hperh->mode       = I2C_MODE_MASTER;
-	hperh->error_code = I2C_ERROR_NONE;
-	hperh->p_buff     = buf;
-	hperh->xfer_size  = size;
-	hperh->xfer_count = size;
-
-	if (hperh->hdmarx.perh == NULL)
-		hperh->hdmarx.perh = DMA0;
-
-	hperh->hdmarx.cplt_cbk = i2c_dma_master_recv_cplt;
-	hperh->hdmarx.cplt_arg = (void *)hperh;
-	hperh->hdmarx.err_cbk  = i2c_dma_error;
-	hperh->hdmarx.err_arg  = (void *)hperh;
-
-	dma_config_struct(&hperh->hdmarx.config);
-	hperh->hdmarx.config.src        = (void *)&hperh->perh->DATA;
-	hperh->hdmarx.config.dst        = (void *)buf;
-	hperh->hdmarx.config.size       = size;
-	hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE;
-	hperh->hdmarx.config.src_inc    = DMA_DATA_INC_NONE;
-	hperh->hdmarx.config.dst_inc    = DMA_DATA_INC_BYTE;
-	hperh->hdmarx.config.msel       = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
-	hperh->hdmarx.config.msigsel    = DMA_MSIGSEL_I2C_RNR;
-	hperh->hdmarx.config.channel    = channel;
-	dma_config_basic(&hperh->hdmarx);
-
-	if (i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-		else {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-
-	if (size == 1)
-		CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-	else
-		SET_BIT(hperh->perh->CON2, I2C_CON2_LDMA);
-
-	SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN);
-	I2C_CLEAR_ADDRFLAG(hperh);
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  channel: DMA channel as I2C Transmit
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_TX;
-	hperh->mode       = I2C_MODE_SLAVE;
-	hperh->error_code = I2C_ERROR_NONE;
-	hperh->p_buff     = buf;
-	hperh->xfer_size  = size;
-	hperh->xfer_count = size;
-
-	if (hperh->hdmatx.perh == NULL)
-		hperh->hdmatx.perh = DMA0;
-
-	hperh->hdmatx.cplt_cbk = i2c_dma_slave_send_cplt;
-	hperh->hdmatx.cplt_arg = hperh;
-	hperh->hdmatx.err_cbk  = i2c_dma_error;
-	hperh->hdmatx.err_arg  = hperh;
-
-	dma_config_struct(&hperh->hdmatx.config);
-	hperh->hdmatx.config.src        = (void *)buf;
-	hperh->hdmatx.config.dst        = (void *)&hperh->perh->DATA;
-	hperh->hdmatx.config.size       = size;
-	hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE;
-	hperh->hdmatx.config.src_inc    = DMA_DATA_INC_BYTE;
-	hperh->hdmatx.config.dst_inc    = DMA_DATA_INC_NONE;
-	hperh->hdmatx.config.msel       = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
-	hperh->hdmatx.config.msigsel    = DMA_MSIGSEL_I2C_TXEMPTY;
-	hperh->hdmatx.config.channel    = channel;
-	dma_config_basic(&hperh->hdmatx);
-
-	SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN);
-	SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) {
-		__UNLOCK(hperh);
-		return TIMEOUT;
-	}
-
-	if (hperh->init.addr_mode == I2C_ADDR_7BIT) {
-		I2C_CLEAR_ADDRFLAG(hperh);
-	}
-	else {
-		I2C_CLEAR_ADDRFLAG(hperh);
-
-		if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-
-		I2C_CLEAR_ADDRFLAG(hperh);
-	}
-
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  channel: DMA channel as I2C receive
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_RX;
-	hperh->mode       = I2C_MODE_SLAVE;
-	hperh->error_code = I2C_ERROR_NONE;
-	hperh->p_buff     = buf;
-	hperh->xfer_size  = size;
-	hperh->xfer_count = size;
-
-	if (hperh->hdmarx.perh == NULL)
-		hperh->hdmarx.perh = DMA0;
-
-	hperh->hdmarx.cplt_cbk = i2c_dma_slave_recv_cplt;
-	hperh->hdmarx.cplt_arg = (void *)hperh;
-	hperh->hdmarx.err_cbk  = i2c_dma_error;
-	hperh->hdmarx.err_arg  = (void *)hperh;
-
-	dma_config_struct(&hperh->hdmarx.config);
-	hperh->hdmarx.config.src        = (void *)&hperh->perh->DATA;
-	hperh->hdmarx.config.dst        = (void *)buf;
-	hperh->hdmarx.config.size       = size;
-	hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE;
-	hperh->hdmarx.config.src_inc    = DMA_DATA_INC_NONE;
-	hperh->hdmarx.config.dst_inc    = DMA_DATA_INC_BYTE;
-	hperh->hdmarx.config.msel       = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
-	hperh->hdmarx.config.msigsel    = DMA_MSIGSEL_I2C_RNR;
-	hperh->hdmarx.config.channel    = channel;
-	dma_config_basic(&hperh->hdmarx);
-
-	SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN);
-	SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) {
-		__UNLOCK(hperh);
-		return TIMEOUT;
-	}
-
-	I2C_CLEAR_ADDRFLAG(hperh);
-	__UNLOCK(hperh);
-	return OK;
-}
-#endif
-
-/**
-  * @brief  Write an amount of data in blocking mode to a specific memory address
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  mem_addr: Internal memory address
-  * @param  add_size: size of internal memory address
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                           i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-	assert_param(IS_I2C_MEMADD_size(add_size));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_TX;
-	hperh->mode       = I2C_MODE_MEM;
-	hperh->error_code = I2C_ERROR_NONE;
-
-	if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, timeout) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-		else {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-
-	while (size > 0) {
-		if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) {
-			if (hperh->error_code == I2C_ERROR_AF) {
-				SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-				__UNLOCK(hperh);
-				return ERROR;
-			}
-			else {
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-		}
-
-		hperh->perh->DATA = (*buf++);
-		--size;
-
-		if ((i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) {
-			hperh->perh->DATA = (*buf++);
-			--size;
-		}
-	}
-
-	if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-		else {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-
-	SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-	hperh->state = I2C_STATE_READY;
-	hperh->mode  = I2C_MODE_NONE;
-	__delay_ms(10);
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Read an amount of data in blocking mode from a specific memory address
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  mem_addr: Internal memory address
-  * @param  add_size: size of internal memory address
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size,
-                          uint8_t *buf, uint16_t size, uint32_t timeout)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-	assert_param(IS_I2C_MEMADD_size(add_size));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_RX;
-	hperh->mode       = I2C_MODE_MEM;
-	hperh->error_code = I2C_ERROR_NONE;
-
-	if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, timeout) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-		else {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-
-	if (size == 1) {
-		CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-		__disable_irq();
-		I2C_CLEAR_ADDRFLAG(hperh);
-		SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-		__enable_irq();
-	}
-	else if (size == 2) {
-		SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-		__disable_irq();
-		I2C_CLEAR_ADDRFLAG(hperh);
-		CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-		__enable_irq();
-	}
-	else {
-		SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-		I2C_CLEAR_ADDRFLAG(hperh);
-	}
-
-	while (size > 3) {
-		if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) {
-			if (hperh->error_code == I2C_ERROR_TIMEOUT) {
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-			else {
-				__UNLOCK(hperh);
-				return ERROR;
-			}
-		}
-
-		(*buf++) = hperh->perh->DATA;
-		--size;
-
-		if (i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) {
-			(*buf++) = hperh->perh->DATA;
-			--size;
-		}
-	}
-
-	switch (size) {
-	case 1:
-		if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) {
-			if (hperh->error_code == I2C_ERROR_TIMEOUT) {
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-			else {
-				__UNLOCK(hperh);
-				return ERROR;
-			}
-		}
-
-		(*buf++) = hperh->perh->DATA;
-		break;
-
-	case 2:
-		if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-
-		__disable_irq();
-		SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-		(*buf++) = hperh->perh->DATA;
-		__enable_irq();
-		(*buf++) = hperh->perh->DATA;
-		break;
-
-	case 3:
-		if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-
-		CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-		__disable_irq();
-		(*buf++) = hperh->perh->DATA;
-
-		if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) {
-			__UNLOCK(hperh);
-			__enable_irq();
-			return TIMEOUT;
-		}
-
-		SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-		(*buf++) = hperh->perh->DATA;
-		__enable_irq();
-		(*buf++) = hperh->perh->DATA;
-		break;
-
-	default:
-		break;
-	}
-
-	hperh->state = I2C_STATE_READY;
-	hperh->mode  = I2C_MODE_NONE;
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  mem_addr: Internal memory address
-  * @param  add_size: size of internal memory address
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                              i2c_addr_size_t add_size, uint8_t *buf, uint16_t size)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-	assert_param(IS_I2C_MEMADD_size(add_size));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_TX;
-	hperh->mode       = I2C_MODE_MEM;
-	hperh->error_code = I2C_ERROR_NONE;
-	hperh->p_buff     = buf;
-	hperh->xfer_size  = size;
-	hperh->xfer_count = size;
-
-	if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-		else {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-
-	__UNLOCK(hperh);
-
-	/* Note : The I2C interrupts must be enabled after unlocking current process
-	 *        to avoid the risk of I2C interrupt handle execution before current
-	 *        process unlock */
-	i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE);
-	i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE);
-	i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE);
-
-	return OK;
-}
-
-/**
-  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  mem_addr: Internal memory address
-  * @param  add_size: size of internal memory address
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                             i2c_addr_size_t add_size, uint8_t *buf, uint16_t size)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-	assert_param(IS_I2C_MEMADD_size(add_size));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_RX;
-	hperh->mode       = I2C_MODE_MEM;
-	hperh->error_code = I2C_ERROR_NONE;
-	hperh->p_buff     = buf;
-	hperh->xfer_size  = size;
-	hperh->xfer_count = size;
-
-	if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-		else {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-
-	if (hperh->xfer_count == 1) {
-		CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-		I2C_CLEAR_ADDRFLAG(hperh);
-		SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-	}
-	else if (hperh->xfer_count == 2) {
-		SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-		I2C_CLEAR_ADDRFLAG(hperh);
-		CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-	}
-	else {
-		SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-		I2C_CLEAR_ADDRFLAG(hperh);
-	}
-
-	__UNLOCK(hperh);
-
-	/* Note : The I2C interrupts must be enabled after unlocking current process
-	 *        to avoid the risk of I2C interrupt handle execution before current
-	 *        process unlock */
-	i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE);
-	i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE);
-	i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE);
-
-	return OK;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  mem_addr: Internal memory address
-  * @param  add_size: size of internal memory address
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  channel: DMA channel
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size,
-                               uint8_t *buf, uint16_t size, uint8_t channel)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-	assert_param(IS_I2C_MEMADD_size(add_size));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_TX;
-	hperh->mode       = I2C_MODE_MEM;
-	hperh->error_code = I2C_ERROR_NONE;
-	hperh->p_buff     = buf;
-	hperh->xfer_size  = size;
-	hperh->xfer_count = size;
-
-	if (hperh->hdmatx.perh == NULL)
-		hperh->hdmatx.perh = DMA0;
-
-	hperh->hdmatx.cplt_cbk = i2c_dma_mem_send_cplt;
-	hperh->hdmatx.cplt_arg = hperh;
-	hperh->hdmatx.err_cbk  = i2c_dma_error;
-	hperh->hdmatx.err_arg  = hperh;
-	dma_config_struct(&hperh->hdmatx.config);
-
-	hperh->hdmatx.config.src        = (void *)buf;
-	hperh->hdmatx.config.dst        = (void *)&hperh->perh->DATA;
-	hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE;
-	hperh->hdmatx.config.size       = size;
-	hperh->hdmatx.config.src_inc    = DMA_DATA_INC_BYTE;
-	hperh->hdmatx.config.dst_inc    = DMA_DATA_INC_NONE;
-	hperh->hdmatx.config.msel       = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
-	hperh->hdmatx.config.msigsel    = DMA_MSIGSEL_I2C_TXEMPTY;
-	hperh->hdmatx.config.channel    = channel;
-	dma_config_basic(&hperh->hdmatx);
-
-	if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-		else {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-
-	SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN);
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  mem_addr: Internal memory address
-  * @param  add_size: size of internal memory address
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be read
-  * @param  channel: DMA channel
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size,
-                              uint8_t *buf, uint16_t size, uint8_t channel)
-{
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-	assert_param(IS_I2C_MEMADD_size(add_size));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state      = I2C_STATE_BUSY_RX;
-	hperh->mode       = I2C_MODE_MEM;
-	hperh->error_code = I2C_ERROR_NONE;
-	hperh->p_buff     = buf;
-	hperh->xfer_size  = size;
-	hperh->xfer_count = size;
-
-	if (hperh->hdmarx.perh == NULL)
-		hperh->hdmarx.perh = DMA0;
-
-	hperh->hdmarx.cplt_cbk = i2c_dma_mem_recv_cplt;
-	hperh->hdmarx.cplt_arg = (void *)hperh;
-	hperh->hdmarx.err_cbk  = i2c_dma_error;
-	hperh->hdmarx.err_arg  = (void *)hperh;
-	dma_config_struct(&hperh->hdmarx.config);
-
-	hperh->hdmarx.config.src        = (void *)&hperh->perh->DATA;
-	hperh->hdmarx.config.dst        = (void *)buf;
-	hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE;
-	hperh->hdmarx.config.size       = size;
-	hperh->hdmarx.config.src_inc    = DMA_DATA_INC_NONE;
-	hperh->hdmarx.config.dst_inc    = DMA_DATA_INC_BYTE;
-	hperh->hdmarx.config.msel       = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
-	hperh->hdmarx.config.msigsel    = DMA_MSIGSEL_I2C_RNR;
-	hperh->hdmarx.config.channel    = channel;
-	dma_config_basic(&hperh->hdmarx);
-
-	if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-		else {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-
-	if (size == 1)
-		CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-	else
-		SET_BIT(hperh->perh->CON2, I2C_CON2_LDMA);
-
-	SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN);
-	I2C_CLEAR_ADDRFLAG(hperh);
-	__UNLOCK(hperh);
-	return OK;
-}
-#endif
-
-/**
-  * @brief  Checks if target device is ready for communication.
-  * @note   This function is used with Memory devices
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  trials: Number of trials
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout)
-{
-	uint32_t tickstart = 0;
-	uint32_t tmp1 = 0;
-	uint32_t tmp2 = 0;
-	uint32_t tmp3 = 0;
-	uint32_t I2C_Trials = 1;
-
-	if (hperh->state != I2C_STATE_READY)
-		return BUSY;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
-		return BUSY;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-
-	__LOCK(hperh);
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-
-	hperh->state = I2C_STATE_BUSY;
-	hperh->error_code = I2C_ERROR_NONE;
-
-	do {
-		SET_BIT(hperh->perh->CON1, I2C_CON1_START);
-
-		if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) {
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-
-		hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr);
-		tickstart            = __get_tick();
-		tmp1                 = i2c_get_flag_status(hperh, I2C_FLAG_ADDR);
-		tmp2                 = i2c_get_flag_status(hperh, I2C_FLAG_AF);
-		tmp3                 = hperh->state;
-
-		while ((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != I2C_STATE_TIMEOUT)) {
-			if ((timeout == 0) || ((__get_tick() - tickstart ) > timeout))
-				hperh->state = I2C_STATE_TIMEOUT;
-
-			tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_ADDR);
-			tmp2 = i2c_get_flag_status(hperh, I2C_FLAG_AF);
-			tmp3 = hperh->state;
-		}
-		hperh->state = I2C_STATE_READY;
-
-		if (i2c_get_flag_status(hperh, I2C_FLAG_ADDR) == SET) {
-			SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-			I2C_CLEAR_ADDRFLAG(hperh);
-
-			if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET,
-							I2C_TIMEOUT_BUSY_FLAG) != OK) {
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-
-			hperh->state = I2C_STATE_READY;
-			__UNLOCK(hperh);
-			return OK;
-		}
-		else {
-			SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-			i2c_clear_flag_status(hperh, I2C_FLAG_AF);
-
-			if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET,
-							I2C_TIMEOUT_BUSY_FLAG) != OK) {
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-		}
-	} while (I2C_Trials++ < trials);
-
-	hperh->state = I2C_STATE_READY;
-	__UNLOCK(hperh);
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Public_Functions_Group3 Peripheral Control functions
-  * @brief   Peripheral state and Errors functions
-  *
-@verbatim
- ===============================================================================
-            ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
-  * @brief  Enable/disable the specified i2c interrupts.
-  * @param  hperh: Pointer to a i2c_handle_t structure.
-  * @param  it: Specifies the i2c interrupt sources to be enabled or disabled.
-  *         This parameter can be one of the @ref i2c_interrupt_t.
-  * @param  state: New state of the specified i2c interrupts.
-  *         This parameter can be:
-  *             @arg ENABLE
-  *             @arg DISABLE
-  * @retval None
-  */
-void i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state)
-{
-	assert_param(IS_I2C_TYPE(hperh->perh));
-	assert_param(IS_I2C_IT_TYPE(it));
-	assert_param(IS_FUNC_STATE(state));
-
-	if (state == ENABLE)
-		SET_BIT((hperh)->perh->CON2, (it));
-	else
-		CLEAR_BIT((hperh)->perh->CON2, (it));
-
-	return;
-}
-
-/**
-  * @brief  Get the status of I2C_SR register.
-  * @param  hperh: Pointer to a i2c_handle_t structure.
-  * @param  flag: Specifies the I2C status type.
-  *         This parameter can be one of the @ref i2c_flag_t.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-flag_status_t i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag)
-{
-	flag_status_t state = RESET;
-
-	assert_param(IS_I2C_TYPE(hperh->perh));
-	assert_param(IS_I2C_FLAG(flag));
-
-	if ((flag & 0xFF0000) == 0) {
-		if ((hperh->perh->STAT1 & flag) == flag)
-			state = SET;
-	}
-	else {
-		if ((hperh->perh->STAT2 & (flag >> 16)) == (flag >> 16))
-			state = SET;
-	}
-
-	return state;
-}
-
-/**
-  * @brief  Get the status of interrupt.
-  * @param  hperh: Pointer to a i2c_handle_t structure.
-  * @param  it: Specifies the i2c interrupt sources to be enabled or disabled.
-  *         This parameter can be one of the @ref i2c_interrupt_t.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-flag_status_t i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it)
-{
-	assert_param(IS_I2C_TYPE(hperh->perh));
-	assert_param(IS_I2C_IT_TYPE(it));
-
-	if ((hperh->perh->CON2 & it) == it)
-		return SET;
-	else
-		return RESET;
-}
-
-/**
-  * @brief  Clear the UART interrupt flag.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  flag: Specifies the UART interrupt flag.
-  *         This parameter can be one of the @ref uart_flag_t.
-  * @retval None
-  */
-void i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag)
-{
-	assert_param(IS_I2C_TYPE(hperh->perh));
-	assert_param(IS_I2C_FLAG(flag));
-
-	if (flag > 65535)
-		return;
-
-	hperh->perh->STAT1 = (hperh->perh->STAT1 & (~flag));
-
-	return;
-
-}
-
-/**
-  * @brief  Return the I2C handle state.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval ald_status_t state
-  */
-i2c_state_t i2c_get_state(i2c_handle_t *hperh)
-{
-	return hperh->state;
-}
-
-/**
-  * @brief  Return the I2C error code.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval I2C Error Code
-  */
-uint32_t i2c_get_error(i2c_handle_t *hperh)
-{
-	return hperh->error_code;
-}
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Public_Functions_Group4 IRQ Handler and Callbacks
-  * @{
-  */
-
-/**
-  * @brief  This function handles I2C event interrupt request.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-void i2c_ev_irq_handler(i2c_handle_t *hperh)
-{
-	uint32_t tmp1 = 0;
-	uint32_t tmp2 = 0;
-	uint32_t tmp3 = 0;
-	uint32_t tmp4 = 0;
-
-	if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) {
-		if (i2c_get_flag_status(hperh, I2C_FLAG_TRA) == SET) {
-			tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_TXE);
-			tmp2 = i2c_get_it_status(hperh, I2C_IT_BUF);
-			tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_BTF);
-			tmp4 = i2c_get_it_status(hperh, I2C_IT_EVT);
-
-			if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
-				i2c_master_send_txe(hperh);
-			else if ((tmp3 == SET) && (tmp4 == SET))
-				i2c_master_send_btf(hperh);
-		}
-
-		/* I2C in mode Receiver */
-		else {
-			tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_RXNE);
-			tmp2 = i2c_get_it_status(hperh, I2C_IT_BUF);
-			tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_BTF);
-			tmp4 = i2c_get_it_status(hperh, I2C_IT_EVT);
-
-			if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
-				i2c_master_recv_rxne(hperh);
-			else if ((tmp3 == SET) && (tmp4 == SET))
-				i2c_master_recv_btf(hperh);
-		}
-	}
-
-	/* Slave mode selected */
-	else {
-		tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_ADDR);
-		tmp2 = i2c_get_it_status(hperh, (I2C_IT_EVT));
-		tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_STOPF);
-		tmp4 = i2c_get_flag_status(hperh, I2C_FLAG_TRA);
-
-		if ((tmp1 == SET) && (tmp2 == SET)) {
-			i2c_slave_addr(hperh);
-		}
-		else if ((tmp3 == SET) && (tmp2 == SET)) {
-			i2c_slave_stopf(hperh);
-		}
-
-		/* I2C in mode Transmitter */
-		else if (tmp4 == SET) {
-			tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_TXE);
-			tmp2 = i2c_get_it_status(hperh, I2C_IT_BUF);
-			tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_BTF);
-			tmp4 = i2c_get_it_status(hperh, I2C_IT_EVT);
-
-			if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
-				i2c_slave_send_txe(hperh);
-			else if ((tmp3 == SET) && (tmp4 == SET))
-				i2c_slave_send_btf(hperh);
-		}
-
-		/* I2C in mode Receiver */
-		else {
-			tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_RXNE);
-			tmp2 = i2c_get_it_status(hperh, I2C_IT_BUF);
-			tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_BTF);
-			tmp4 = i2c_get_it_status(hperh, I2C_IT_EVT);
-
-			if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
-				i2c_slave_recv_rxne(hperh);
-			else if ((tmp3 == SET) && (tmp4 == SET))
-				i2c_slave_recv_btf(hperh);
-		}
-	}
-}
-
-/**
-  * @brief  This function handles I2C error interrupt request.
-  * @param  hperh: pointer to a i2c_handle_t structure that contains
-  *         the configuration information for I2C module
-  * @retval  NONE
-  */
-void i2c_er_irq_handler(i2c_handle_t *hperh)
-{
-	uint32_t tmp1 = 0;
-	uint32_t tmp2 = 0;
-	uint32_t tmp3 = 0;
-
-	tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_BERR);
-	tmp2 = i2c_get_it_status(hperh, I2C_IT_ERR);
-
-	/* I2C Bus error interrupt occurred */
-	if ((tmp1 == SET) && (tmp2 == SET)) {
-		hperh->error_code |= I2C_ERROR_BERR;
-		i2c_clear_flag_status(hperh, I2C_FLAG_BERR);
-		SET_BIT(hperh->perh->CON1, I2C_CON1_SRST);
-	}
-
-	tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_ARLO);
-	tmp2 = i2c_get_it_status(hperh, I2C_IT_ERR);
-
-	/* I2C Arbitration Loss error interrupt occurred */
-	if ((tmp1 == SET) && (tmp2 == SET)) {
-		hperh->error_code |= I2C_ERROR_ARLO;
-		i2c_clear_flag_status(hperh, I2C_FLAG_ARLO);
-	}
-
-	tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_AF);
-	tmp2 = i2c_get_it_status(hperh, I2C_IT_ERR);
-
-	/* I2C Acknowledge failure error interrupt occurred */
-	if ((tmp1 == SET) && (tmp2 == SET)) {
-		tmp1 = hperh->mode;
-		tmp2 = hperh->xfer_count;
-		tmp3 = hperh->state;
-		if ((tmp1 == I2C_MODE_SLAVE) && (tmp2 == 0) && \
-		   (tmp3 == I2C_STATE_BUSY_TX)) {
-			i2c_slave_af(hperh);
-		}
-		else {
-			hperh->error_code |= I2C_ERROR_AF;
-			SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-			i2c_clear_flag_status(hperh, I2C_FLAG_AF);
-		}
-	}
-
-	tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_OVR);
-	tmp2 = i2c_get_it_status(hperh, I2C_IT_ERR);
-
-	/* I2C Over-Run/Under-Run interrupt occurred */
-	if ((tmp1 == SET) && (tmp2 == SET)) {
-		hperh->error_code |= I2C_ERROR_OVR;
-		i2c_clear_flag_status(hperh, I2C_FLAG_OVR);
-	}
-
-	if (hperh->error_code != I2C_ERROR_NONE) {
-		hperh->state = I2C_STATE_READY;
-		CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP);
-		if (hperh->error_callback)
-			hperh->error_callback(hperh);
-	}
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Handle TXE flag for Master Transmit mode
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh)
-{
-	if (hperh->xfer_count == 0) {
-		i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE);
-	}
-	else {
-		hperh->perh->DATA = (*hperh->p_buff++);
-		hperh->xfer_count--;
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  Handle BTF flag for Master Transmit mode
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_master_send_btf(i2c_handle_t *hperh)
-{
-	if (hperh->xfer_count != 0) {
-		hperh->perh->DATA = (*hperh->p_buff++);
-		hperh->xfer_count--;
-	}
-	else {
-		i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE);
-		i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE);
-		i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE);
-		SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-		if (hperh->mode == I2C_MODE_MEM) {
-			hperh->state = I2C_STATE_READY;
-			if (hperh->mem_tx_cplt_cbk)
-				hperh->mem_tx_cplt_cbk(hperh);
-		}
-		else {
-			hperh->state = I2C_STATE_READY;
-			if (hperh->master_tx_cplt_cbk)
-				hperh->master_tx_cplt_cbk(hperh);
-		}
-	}
-	return OK;
-}
-
-/**
-  * @brief  Handle RXNE flag for Master Receive mode
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh)
-{
-	uint32_t tmp = 0;
-
-	tmp = hperh->xfer_count;
-	if (tmp > 3) {
-		(*hperh->p_buff++) = hperh->perh->DATA;
-		hperh->xfer_count--;
-	}
-	else if ((tmp == 2) || (tmp == 3)) {
-		i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE);
-	}
-	else {
-		i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE);
-		i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE);
-		i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE);
-		(*hperh->p_buff++) = hperh->perh->DATA;
-		hperh->xfer_count--;
-
-		if (hperh->mode == I2C_MODE_MEM) {
-			hperh->state = I2C_STATE_READY;
-			if (hperh->mem_rx_cplt_cbk)
-				hperh->mem_rx_cplt_cbk(hperh);
-		}
-		else {
-			hperh->state = I2C_STATE_READY;
-			if (hperh->master_rx_cplt_cbk)
-				hperh->master_rx_cplt_cbk(hperh);
-		}
-	}
-	return OK;
-}
-
-/**
-  * @brief  Handle BTF flag for Master Receive mode
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_master_recv_btf(i2c_handle_t *hperh)
-{
-	if (hperh->xfer_count == 3) {
-		CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-		(*hperh->p_buff++) = hperh->perh->DATA;
-		--hperh->xfer_count;
-	}
-	else if (hperh->xfer_count == 2) {
-		i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE);
-		i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE);
-		SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-		(*hperh->p_buff++) = hperh->perh->DATA;
-		--hperh->xfer_count;
-
-		(*hperh->p_buff++) = hperh->perh->DATA;
-		--hperh->xfer_count;
-
-		if (hperh->mode == I2C_MODE_MEM) {
-			hperh->state = I2C_STATE_READY;
-			if (hperh->mem_rx_cplt_cbk)
-				hperh->mem_rx_cplt_cbk(hperh);
-		}
-		else {
-			hperh->state = I2C_STATE_READY;
-			if (hperh->master_rx_cplt_cbk)
-				hperh->master_rx_cplt_cbk(hperh);
-		}
-	}
-	else {
-		(*hperh->p_buff++) = hperh->perh->DATA;
-		--hperh->xfer_count;
-	}
-	return OK;
-}
-
-/**
-  * @brief  Handle TXE flag for Slave Transmit mode
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh)
-{
-	if (hperh->xfer_count != 0) {
-		hperh->perh->DATA = (*hperh->p_buff++);
-		--hperh->xfer_count;
-	}
-	return OK;
-}
-
-/**
-  * @brief  Handle BTF flag for Slave Transmit mode
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_slave_send_btf(i2c_handle_t *hperh)
-{
-	if (hperh->xfer_count != 0) {
-		hperh->perh->DATA = (*hperh->p_buff++);
-		--hperh->xfer_count;
-	}
-	return OK;
-}
-
-/**
-  * @brief  Handle RXNE flag for Slave Receive mode
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh)
-{
-	if (hperh->xfer_count != 0) {
-		(*hperh->p_buff++) = hperh->perh->DATA;
-		--hperh->xfer_count;
-	}
-	return OK;
-}
-
-/**
-  * @brief  Handle BTF flag for Slave Receive mode
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_slave_recv_btf(i2c_handle_t *hperh)
-{
-	if (hperh->xfer_count != 0) {
-		(*hperh->p_buff++) = hperh->perh->DATA;
-		--hperh->xfer_count;
-	}
-	return OK;
-}
-
-/**
-  * @brief  Handle ADD flag for Slave
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_slave_addr(i2c_handle_t *hperh)
-{
-	I2C_CLEAR_ADDRFLAG(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Handle STOPF flag for Slave mode
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh)
-{
-	if (hperh->xfer_count != 0) {
-		(*hperh->p_buff++) = hperh->perh->DATA;
-		--hperh->xfer_count;
-	}
-
-	i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE);
-	i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE);
-	i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE);
-	__I2C_CLEAR_STOPFLAG(hperh);
-
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-	hperh->state = I2C_STATE_READY;
-
-	if (hperh->slave_rx_cplt_cbk)
-		hperh->slave_rx_cplt_cbk(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Handle Acknowledge Failed for Slave mode
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_slave_af(i2c_handle_t *hperh)
-{
-	i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE);
-	i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE);
-	i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE);
-	i2c_clear_flag_status(hperh, I2C_FLAG_AF);
-
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-	hperh->state = I2C_STATE_READY;
-
-	if (hperh->slave_tx_cplt_cbk)
-		hperh->slave_tx_cplt_cbk(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Master sends target device address followed by internal memory address for write request.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
-{
-	SET_BIT(hperh->perh->CON1, I2C_CON1_START);
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK)
-		return TIMEOUT;
-
-	if (hperh->init.addr_mode == I2C_ADDR_7BIT) {
-		hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr);
-	}
-	else {
-		hperh->perh->DATA = I2C_10BIT_HEADER_WRITE(dev_addr);
-
-		if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADD10, timeout) != OK) {
-			if (hperh->error_code == I2C_ERROR_AF) {
-				return ERROR;
-			}
-			else {
-				return TIMEOUT;
-			}
-		}
-
-		hperh->perh->DATA = I2C_10BIT_ADDRESS(dev_addr);
-	}
-
-	if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF)
-			return ERROR;
-		else
-			return TIMEOUT;
-	}
-	return OK;
-}
-
-/**
-  * @brief  Master sends target device address followed by internal memory address for read request.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
-{
-	SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-	SET_BIT(hperh->perh->CON1, I2C_CON1_START);
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK)
-		return TIMEOUT;
-
-	if (hperh->init.addr_mode == I2C_ADDR_7BIT) {
-		hperh->perh->DATA = I2C_7BIT_ADD_READ(dev_addr);
-	}
-	else {
-		hperh->perh->DATA = I2C_10BIT_HEADER_WRITE(dev_addr);
-		if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADD10, timeout) != OK) {
-			if (hperh->error_code == I2C_ERROR_AF)
-				return ERROR;
-			else
-				return TIMEOUT;
-		}
-
-		hperh->perh->DATA = I2C_10BIT_ADDRESS(dev_addr);
-
-		if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) {
-			if (hperh->error_code == I2C_ERROR_AF)
-				return ERROR;
-			else
-				return TIMEOUT;
-		}
-
-		I2C_CLEAR_ADDRFLAG(hperh);
-		SET_BIT(hperh->perh->CON1, I2C_CON1_START);
-
-		if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK)
-			return TIMEOUT;
-
-		hperh->perh->DATA = I2C_10BIT_HEADER_READ(dev_addr);
-	}
-
-	if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF)
-			return ERROR;
-		else
-			return TIMEOUT;
-	}
-
-	I2C_CLEAR_ADDRFLAG(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Master sends target device address followed by internal memory address for write request.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  mem_addr: Internal memory address
-  * @param  add_size: size of internal memory address
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout)
-{
-	SET_BIT(hperh->perh->CON1, I2C_CON1_START);
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) {
-		return TIMEOUT;
-	}
-
-	hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr);
-
-	if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF)
-			return ERROR;
-		else
-			return TIMEOUT;
-	}
-
-	I2C_CLEAR_ADDRFLAG(hperh);
-
-	if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-			return ERROR;
-		}
-		else {
-			return TIMEOUT;
-		}
-	}
-
-	if (add_size == I2C_MEMADD_SIZE_8BIT) {
-		hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr);
-	}
-	else {
-		hperh->perh->DATA = I2C_MEM_ADD_MSB(mem_addr);
-		if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) {
-			if (hperh->error_code == I2C_ERROR_AF) {
-				SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-				return ERROR;
-			}
-			else {
-				return TIMEOUT;
-			}
-		}
-		hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr);
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  Master sends target device address followed by internal memory address for read request.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  dev_addr: Target device address
-  * @param  mem_addr: Internal memory address
-  * @param  add_size: size of internal memory address
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout)
-{
-	SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-	SET_BIT(hperh->perh->CON1, I2C_CON1_START);
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK)
-		return TIMEOUT;
-
-	hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr);
-
-	if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF)
-			return ERROR;
-		else
-			return TIMEOUT;
-	}
-
-	I2C_CLEAR_ADDRFLAG(hperh);
-
-	if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-			return ERROR;
-		}
-		else {
-			return TIMEOUT;
-		}
-	}
-
-	if (add_size == I2C_MEMADD_SIZE_8BIT) {
-		hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr);
-	}
-	else {
-		hperh->perh->DATA = I2C_MEM_ADD_MSB(mem_addr);
-
-		if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) {
-			if (hperh->error_code == I2C_ERROR_AF) {
-				SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-				return ERROR;
-			}
-			else {
-				return TIMEOUT;
-			}
-		}
-		hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr);
-	}
-
-	if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF) {
-			SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-			return ERROR;
-		}
-		else {
-			return TIMEOUT;
-		}
-	}
-
-	SET_BIT(hperh->perh->CON1, I2C_CON1_START);
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK)
-		return TIMEOUT;
-
-	hperh->perh->DATA = I2C_7BIT_ADD_READ(dev_addr);
-
-	if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF)
-			return ERROR;
-		else
-			return TIMEOUT;
-	}
-
-	return OK;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  DMA I2C master transmit process complete callback.
-  * @param  argv: I2C handle
-  * @retval None
-  */
-static void i2c_dma_master_send_cplt(void *argv)
-{
-	i2c_handle_t* hperh = (i2c_handle_t*)argv;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != OK)
-		hperh->error_code |= I2C_ERROR_TIMEOUT;
-
-	SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-	CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN);
-
-	hperh->xfer_count = 0;
-	hperh->state      = I2C_STATE_READY;
-	hperh->mode       = I2C_MODE_NONE;
-
-	if (hperh->error_code != I2C_ERROR_NONE) {
-		if (hperh->error_callback)
-			hperh->error_callback(hperh);
-	}
-	else {
-		if (hperh->master_tx_cplt_cbk)
-			hperh->master_tx_cplt_cbk(hperh);
-	}
-}
-
-/**
-  * @brief  DMA I2C slave transmit process complete callback.
-  * @param  argv: I2C handle
-  * @retval None
-  */
-static void i2c_dma_slave_send_cplt(void *argv)
-{
-	i2c_handle_t* hperh = (i2c_handle_t*)argv;
-
-	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != OK)
-		hperh->error_code |= I2C_ERROR_TIMEOUT;
-
-	i2c_clear_flag_status(hperh, I2C_FLAG_AF);
-
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-	CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN);
-
-	hperh->xfer_count = 0;
-	hperh->state      = I2C_STATE_READY;
-	hperh->mode       = I2C_MODE_NONE;
-
-	if (hperh->error_code != I2C_ERROR_NONE) {
-		if (hperh->error_callback)
-			hperh->error_callback(hperh);
-	}
-	else {
-		if (hperh->slave_tx_cplt_cbk)
-			hperh->slave_tx_cplt_cbk(hperh);
-	}
-}
-
-/**
-  * @brief  DMA I2C master receive process complete callback
-  * @param  argv: I2C handle
-  * @retval None
-  */
-static void i2c_dma_master_recv_cplt(void *argv)
-{
-	i2c_handle_t* hperh = (i2c_handle_t*)argv;
-
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-	SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-	CLEAR_BIT(hperh->perh->CON2, I2C_CON2_LDMA);
-	CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN);
-
-	hperh->xfer_count = 0;
-	hperh->state      = I2C_STATE_READY;
-	hperh->mode       = I2C_MODE_NONE;
-
-	if (hperh->error_code != I2C_ERROR_NONE) {
-		if (hperh->error_callback)
-			hperh->error_callback(hperh);
-	}
-	else {
-		if (hperh->master_rx_cplt_cbk)
-			hperh->master_rx_cplt_cbk(hperh);
-	}
-}
-
-/**
-  * @brief  DMA I2C slave receive process complete callback.
-  * @param  argv: I2C handle
-  * @retval None
-  */
-static void i2c_dma_slave_recv_cplt(void *argv)
-{
-	i2c_handle_t* hperh = (i2c_handle_t*)argv;
-
-	if (i2c_wait_stop_to_timeout(hperh, I2C_TIMEOUT_FLAG) != OK) {
-		if (hperh->error_code == I2C_ERROR_AF)
-			hperh->error_code |= I2C_ERROR_AF;
-		else
-			hperh->error_code |= I2C_ERROR_TIMEOUT;
-	}
-
-	__I2C_CLEAR_STOPFLAG(hperh);
-
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-	CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN);
-
-	hperh->xfer_count = 0;
-	hperh->state      = I2C_STATE_READY;
-	hperh->mode       = I2C_MODE_NONE;
-
-	if (hperh->error_code != I2C_ERROR_NONE) {
-		if (hperh->error_callback)
-			hperh->error_callback(hperh);
-	}
-	else {
-		if (hperh->slave_rx_cplt_cbk)
-			hperh->slave_rx_cplt_cbk(hperh);
-	}
-}
-
-/**
-  * @brief  DMA I2C Memory Write process complete callback
-  * @param  argv: I2C handle
-  * @retval None
-  */
-static void i2c_dma_mem_send_cplt(void *argv)
-{
-	i2c_handle_t* hperh = (i2c_handle_t*)argv;
-
- 	if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != OK)
-		hperh->error_code |= I2C_ERROR_TIMEOUT;
-
-	SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-	CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN);
-
-	hperh->xfer_count = 0;
-	hperh->state      = I2C_STATE_READY;
-	hperh->mode       = I2C_MODE_NONE;
-
-	if (hperh->error_code != I2C_ERROR_NONE) {
-		if (hperh->error_callback)
-			hperh->error_callback(hperh);
-	}
-	else {
-		if (hperh->mem_tx_cplt_cbk)
-			hperh->mem_tx_cplt_cbk(hperh);
-	}
-}
-
-/**
-  * @brief  DMA I2C Memory Read process complete callback
-  * @param  argv: I2C handle
-  * @retval None
-  */
-static void i2c_dma_mem_recv_cplt(void *argv)
-{
-	i2c_handle_t* hperh = (i2c_handle_t*)argv;
-
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-	SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-	CLEAR_BIT(hperh->perh->CON2, I2C_CON2_LDMA);
-	CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN);
-
-	hperh->xfer_count = 0;
-	hperh->state      = I2C_STATE_READY;
-	hperh->mode       = I2C_MODE_NONE;
-
-	if (hperh->error_code != I2C_ERROR_NONE) {
-		if (hperh->error_callback)
-			hperh->error_callback(hperh);
-	}
-	else {
-		if (hperh->mem_rx_cplt_cbk)
-			hperh->mem_rx_cplt_cbk(hperh);
-	}
-}
-#endif
-
-/**
-  * @brief  I2C Configuration Speed function
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  i2c_clk: PCLK frequency from RCC.
-  * @retval CCR Speed: Speed to set in I2C CCR Register
-  */
-static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk)
-{
-	uint32_t tmp1 = 0;
-
-	if (hperh->init.clk_speed <= I2C_STANDARD_MODE_MAX_CLK) {
-		tmp1 = (i2c_clk / (hperh->init.clk_speed << 1));
-		if ((tmp1 & I2C_CKCFG_CLKSET) < 4 )
-			return 4;
-		else
-			return tmp1;
-	}
-	else {
-		tmp1 = I2C_CKCFG_CLKMOD;
-
-		if (hperh->init.duty == I2C_DUTYCYCLE_2)
-			tmp1 |= (i2c_clk / (hperh->init.clk_speed * 3)) | I2C_DUTYCYCLE_2;
-		else
-			tmp1 |= (i2c_clk / (hperh->init.clk_speed * 25)) | I2C_DUTYCYCLE_16_9;
-
-		if ((tmp1 & I2C_CKCFG_CLKSET) < 1 )
-			return 1;
-		else
-			return tmp1;
-	}
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  DMA I2C communication error callback.
-  * @param  argv: I2C handle
-  * @retval None
-  */
-static void i2c_dma_error(void *argv)
-{
-	i2c_handle_t* hperh = (i2c_handle_t*)argv;
-
-	CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN);
-
-	hperh->xfer_count  = 0;
-	hperh->state       = I2C_STATE_READY;
-	hperh->mode        = I2C_MODE_NONE;
-	hperh->error_code |= I2C_ERROR_DMA;
-
-	if (hperh->error_callback)
-		hperh->error_callback(hperh);
-}
-#endif
-
-/**
-  * @brief  This function handles I2C Communication timeout.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  flag: specifies the I2C flag to check.
-  * @param  status: The new flag status (SET or RESET).
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, flag_status_t status, uint32_t timeout)
-{
-	uint32_t tickstart = 0;
-
-	tickstart = __get_tick();
-
-	if (status == RESET) {
-		while (i2c_get_flag_status(hperh, flag) == RESET) {
-			if ((timeout == 0) || ((__get_tick() - tickstart ) > timeout)) {
-				hperh->state = I2C_STATE_READY;
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-		}
-	}
-	else {
-		while (i2c_get_flag_status(hperh, flag) != RESET) {
-			if ((timeout == 0) || ((__get_tick() - tickstart ) > timeout)) {
-				hperh->state = I2C_STATE_READY;
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-		}
-	}
-	return OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication timeout for Master addressing phase.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  flag: specifies the I2C flag to check.
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, uint32_t timeout)
-{
-	uint32_t tickstart = 0;
-
-	tickstart = __get_tick();
-	while (i2c_get_flag_status(hperh, flag) == RESET) {
-		if (i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) {
-			SET_BIT(hperh->perh->CON1, I2C_CON1_STOP);
-			i2c_clear_flag_status(hperh, I2C_FLAG_AF);
-
-			hperh->error_code = I2C_ERROR_AF;
-			hperh->state = I2C_STATE_READY;
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-
-		if (timeout != I2C_MAX_DELAY) {
-			if ((timeout == 0) || ((__get_tick() - tickstart ) > timeout)) {
-				hperh->state = I2C_STATE_READY;
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-		}
-	}
-	return OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication timeout for specific usage of TXE flag.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout)
-{
-	uint32_t tickstart = __get_tick();
-
-	while (i2c_get_flag_status(hperh, I2C_FLAG_TXE) == RESET) {
-		if (i2c_is_ack_failed(hperh) != OK)
-			return ERROR;
-
-		if (timeout != I2C_MAX_DELAY) {
-			if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) {
-				hperh->error_code |= I2C_ERROR_TIMEOUT;
-				hperh->state = I2C_STATE_READY;
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-		}
-	}
-	return OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication timeout for specific usage of BTF flag.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeout)
-{
-	uint32_t tickstart = __get_tick();
-
-	while (i2c_get_flag_status(hperh, I2C_FLAG_BTF) == RESET) {
-		if (i2c_is_ack_failed(hperh) != OK) {
-			return ERROR;
-		}
-
-		if (timeout != I2C_MAX_DELAY) {
-			if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) {
-				hperh->error_code |= I2C_ERROR_TIMEOUT;
-				hperh->state = I2C_STATE_READY;
-				__UNLOCK(hperh);
-				return TIMEOUT;
-			}
-		}
-	}
-	return OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication timeout for specific usage of STOP flag.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_wait_stop_to_timeout(i2c_handle_t *hperh, uint32_t timeout)
-{
-	uint32_t tickstart = 0x00;
-	tickstart = __get_tick();
-
-	while (i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == RESET) {
-		if (i2c_is_ack_failed(hperh) != OK)
-			return ERROR;
-
-		if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) {
-			hperh->error_code |= I2C_ERROR_TIMEOUT;
-			hperh->state = I2C_STATE_READY;
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-	return OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication timeout for specific usage of RXNE flag.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout)
-{
-	uint32_t tickstart = 0x00;
-	tickstart = __get_tick();
-
-	while (i2c_get_flag_status(hperh, I2C_FLAG_RXNE) == RESET) {
-		if (i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == SET) {
-			i2c_clear_flag_status(hperh, I2C_FLAG_STOPF);
-			hperh->error_code = I2C_ERROR_NONE;
-			hperh->state = I2C_STATE_READY;
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-
-		if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) {
-			hperh->error_code |= I2C_ERROR_TIMEOUT;
-			hperh->state = I2C_STATE_READY;
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-	}
-	return OK;
-}
-
-/**
-  * @brief  This function handles Acknowledge failed detection during an I2C Communication.
-  * @param  hperh: Pointer to a i2c_handle_t structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t i2c_is_ack_failed(i2c_handle_t *hperh)
-{
-	if (i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) {
-		i2c_clear_flag_status(hperh, I2C_FLAG_AF);
-		hperh->error_code = I2C_ERROR_AF;
-		hperh->state = I2C_STATE_READY;
-		__UNLOCK(hperh);
-
-		return ERROR;
-	}
-
-	return OK;
-}
-/**
-  * @}
-  */
-
-#endif /* ALD_I2C */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lcd.c

@@ -1,345 +0,0 @@
- /**
-   *********************************************************************************
-   *
-   * @file    ald_lcd.c
-   * @brief   LCD module driver.
-   *
-   * @version V1.0
-   * @date    29 Nov 2017
-   * @author  AE Team
-   * @note
-   *
-   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-   *
-   *********************************************************************************
-   */
-
-#include "ald_lcd.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup LCD LCD
-  * @brief LCD module library
-  * @{
-  */
-#ifdef ALD_LCD
-
-/** @defgroup LCD_Public_Functions LCD Public Functions
-  * @{
-  */
-
-/** @defgroup LCD_Public_Functions_Group1 Initialize and Enable functions
-  * @brief Initialize and Enable Functions
-  * @{
-  */
-
-/**
-  * @brief Initializes the LCD Peripheral according to the specified parameters.
-  * @note This function can be used only when the LCD is disabled.
-  * @param hperh: Pointer to a lcd_handle_t structure that contains
-  *               the configuration information for the specified LCD.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lcd_init(lcd_handle_t *hperh)
-{
-	uint16_t delay = 0;
-
-	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-	assert_param(IS_LCD_VCHPS_TYPE(hperh->init.lcd_vchps));
-	assert_param(IS_LCD_VSEL_TYPE(hperh->init.lcd_vsel));
-	assert_param(IS_LCD_FUNC_TYPE(hperh->init.lcd_vbufld));
-	assert_param(IS_LCD_FUNC_TYPE(hperh->init.lcd_vbufhd));
-	assert_param(IS_LCD_LEVEL_TYPE(hperh->init.lcd_dsld));
-	assert_param(IS_LCD_LEVEL_TYPE(hperh->init.lcd_dshd));
-	assert_param(IS_LCD_RES_TYPE(hperh->init.lcd_resld));
-	assert_param(IS_LCD_RES_TYPE(hperh->init.lcd_reshd));
-	assert_param(IS_LCD_BIAS_TYPE(hperh->init.lcd_bias));
-	assert_param(IS_LCD_DUTY_TYPE(hperh->init.lcd_duty));
-	assert_param(IS_LCD_WFS_TYPE(hperh->init.lcd_wfs));
-	assert_param(IS_LCD_PRS_TYPE(hperh->init.lcd_prs));
-	assert_param(IS_LCD_DIV_TYPE(hperh->init.lcd_div));
-	assert_param(IS_LCD_DEAD_TYPE(hperh->init.lcd_dead));
-	assert_param(IS_LCD_PON_TYPE(hperh->init.lcd_pon));
-	assert_param(IS_LCD_VGS_TYPE(hperh->init.lcd_vgs));
-
-	__LOCK(hperh);
-
-	cmu_lcd_clock_select(hperh->init.clock);
-
-	MODIFY_REG(hperh->perh->FCR, LCD_FCR_WFS_MSK, hperh->init.lcd_wfs << LCD_FCR_WFS_POS);
-	MODIFY_REG(hperh->perh->FCR, LCD_FCR_PRS_MSK, hperh->init.lcd_prs << LCD_FCR_PRS_POSS);
-	for (delay = 0; delay < 3000; delay++);
-	MODIFY_REG(hperh->perh->FCR, LCD_FCR_DIV_MSK, hperh->init.lcd_div << LCD_FCR_DIV_POSS);
-	MODIFY_REG(hperh->perh->FCR, LCD_FCR_DEAD_MSK, hperh->init.lcd_dead << LCD_FCR_DEAD_POSS);
-	MODIFY_REG(hperh->perh->FCR, LCD_FCR_PON_MSK, hperh->init.lcd_pon << LCD_FCR_PON_POSS);
-	MODIFY_REG(hperh->perh->FCR, LCD_FCR_VGS_MSK, hperh->init.lcd_vgs << LCD_FCR_VGS_POSS);
-
-	MODIFY_REG(hperh->perh->CR, LCD_CR_DUTY_MSK, hperh->init.lcd_duty << LCD_CR_DUTY_POSS);
-	MODIFY_REG(hperh->perh->CR, LCD_CR_BIAS_MSK, hperh->init.lcd_bias << LCD_CR_BIAS_POSS);
-	MODIFY_REG(hperh->perh->CR, LCD_CR_VBUFHD_MSK, hperh->init.lcd_vbufhd << LCD_CR_VBUFHD_POS);
-	MODIFY_REG(hperh->perh->CR, LCD_CR_VBUFLD_MSK, hperh->init.lcd_vbufld << LCD_CR_VBUFLD_POS);
-	MODIFY_REG(hperh->perh->CR, LCD_CR_DSHD_MSK, hperh->init.lcd_dshd << LCD_CR_DSHD_POSS);
-	MODIFY_REG(hperh->perh->CR, LCD_CR_DSLD_MSK, hperh->init.lcd_dsld << LCD_CR_DSLD_POSS);
-	MODIFY_REG(hperh->perh->CR, LCD_CR_RESHD_MSK, hperh->init.lcd_reshd << LCD_CR_RESHD_POSS);
-	MODIFY_REG(hperh->perh->CR, LCD_CR_RESLD_MSK, hperh->init.lcd_resld << LCD_CR_RESLD_POSS);
-	MODIFY_REG(hperh->perh->CR, LCD_CR_VSEL_MSK, hperh->init.lcd_vsel << LCD_CR_VSEL_POSS);
-	MODIFY_REG(hperh->perh->CR, LCD_CR_VCHPS_MSK, hperh->init.lcd_vchps << LCD_CR_VCHPS_POSS);
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief Enables or disables the LCD controller.
-  * @param hperh: Pointer to a lcd_handle_t structure that contains
-  *               the configuration information for the specified LCD.
-  * @param state: This parameter can be: ENABLE or DISABLE.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lcd_cmd(lcd_handle_t *hperh, type_func_t state)
-{
-	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-	assert_param(IS_FUNC_STATE(state));
-
-	__LOCK(hperh);
-
-	MODIFY_REG(hperh->perh->CR, LCD_CR_OE_MSK, state << LCD_CR_OE_POS);
-	MODIFY_REG(hperh->perh->CR, LCD_CR_EN_MSK, state << LCD_CR_EN_POS);
-
-	__UNLOCK(hperh);
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup LCD_Public_Functions_Group2 Config output functions
-  * @brief Config output and blink functions
-  * @{
-  */
-
-/**
-  * @brief Configures the LCD blink mode and blink frequency.
-  * @param hperh: Pointer to a lcd_handle_t structure that contains
-  *               the configuration information for the specified LCD.
-  * @param blink_mode: Specifies the LCD blink mode.
-  * @param blink_freq: Specifies the LCD blink frequency.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lcd_blink_config(lcd_handle_t *hperh, lcd_blink_t blink_mode, lcd_blfrq_t blink_freq)
-{
-	uint16_t delay = 0;
-	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-	assert_param(IS_LCD_BLINK_MODE(blink_mode));
-	assert_param(IS_LCD_BLFRQ_TYPE(blink_freq));
-	__LOCK(hperh);
-
-	MODIFY_REG(hperh->perh->FCR, LCD_FCR_BLMOD_MSK, blink_mode << LCD_FCR_BLMOD_POSS);
-	for (delay = 0; delay < 3000; delay++);
-	MODIFY_REG(hperh->perh->FCR, LCD_FCR_BLFRQ_MSK, blink_freq << LCD_FCR_BLFRQ_POSS);
-
-	__UNLOCK(hperh);
-	return OK;
- }
-
-/**
-  * @brief Control segment port enable or disable
-  * @param hperh: Pointer to a lcd_handle_t structure that contains
-  *               the configuration information for the specified LCD.
-  * @param seg: Specifies the LCD segment index
-  * @param seg_data: Specifies LCD segment data to be written to control segment output enable.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lcd_write_seg(lcd_handle_t *hperh, lcd_seg_t seg, uint32_t seg_data)
-{
-	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-	assert_param(IS_LCD_SEG_TYPE(seg));
-	__LOCK(hperh);
-
-	if (seg == SEG_0_TO_31)
-		WRITE_REG(hperh->perh->SEGCR0, seg_data);
-	else
-		WRITE_REG(hperh->perh->SEGCR1, seg_data);
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief Writes a word in the specific LCD buffer to determine display.
-  * @param hperh: Pointer to a lcd_handle_t structure that contains
-  *               the configuration information for the specified LCD.
-  * @param buf: Specifies the LCD buffer index.
-  * @param buf_data: Specifies LCD buffer data to be written to control display.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lcd_write(lcd_handle_t *hperh, uint8_t buf, uint32_t buf_data)
-{
-	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-	assert_param(IS_LCD_BUFFER_TYPE(buf));
-
-	__LOCK(hperh);
-	WRITE_REG(hperh->perh->BUF[buf], buf_data);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup LCD_Public_Functions_Group3 Peripheral State functions
-  * @brief LCD State functions
-  * @{
-  */
-
-/**
-  * @brief Checks whether the specified LCD flag is set or not.
-  * @param hperh: Pointer to a lcd_handle_t structure that contains
-  *               the configuration information for the specified LCD.
-  * @param lcd_status: Specifies the flag to check.
-  * @retval The new state of LCD_STATUS
-  */
-uint32_t lcd_get_status(lcd_handle_t *hperh, lcd_status_t lcd_status)
-{
-	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-	assert_param(IS_LCD_STATUS_TYPE(lcd_status));
-
-	if (lcd_status == LCD_STATUS_ALL)
-		return hperh->perh->SR;
-	else
-		return hperh->perh->SR & lcd_status ? 1 : 0;
-}
-/**
-  * @}
-  */
-
-/** @defgroup LCD_Public_Functions_Group4 Interrupt functions
-  * @brief LCD Interrupt functions
-  * @{
-  */
-
-/**
-  * @brief Enable or disable the specified interrupt
-  * @param hperh: Pointer to a lcd_handle_t structure that contains
-  *               the configuration information for the specified LCD.
-  * @param it: Specifies the interrupt type to be enabled or disabled
-  *        @arg @ref LCD_IT_SOF Start of frame interrupt enable
-  *        @arg @ref LCD_IT_UDD Update display done interrupt
-  * @param state: New state of the specified interrupt.
-  *        This parameter can be: ENABLE or DISABLE
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lcd_interrupt_config(lcd_handle_t *hperh, lcd_it_t it, type_func_t state)
-{
-	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-	assert_param(IS_LCD_IT_TYPE(it));
-	assert_param(IS_FUNC_STATE(state));
-	__LOCK(hperh);
-
-	if (state)
-		SET_BIT(hperh->perh->IE, it);
-	else
-		CLEAR_BIT(hperh->perh->IE, it);
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief Checks whether the specified interrupt has set or not.
-  * @param hperh: Pointer to a lcd_handle_t structure that contains
-  *               the configuration information for the specified LCD.
-  * @param it: Specifies the interrupt type to check
-  *        This parameter can be one of the following values:
-  *        @arg @ref LCD_IT_SOF Start of frame interrupt enable
-  *        @arg @ref LCD_IT_UDD Update display done interrupt
-  * @retval The new state of the LCD_IT
-  */
-flag_status_t lcd_get_it_status(lcd_handle_t *hperh, lcd_it_t it)
-{
-	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-	assert_param(IS_LCD_IT_TYPE(it));
-
-	return hperh->perh->IE & it ? SET : RESET;
-}
-
-/**
-  * @brief Checks whether the specified interrupt has occurred or not.
-  * @param hperh: Pointer to a lcd_handle_t structure that contains
-  *               the configuration information for the specified LCD.
-  * @param flag: Specifies the interrupt type to check
-  *        This parameter can be one of the following values:
-  *        @arg @ref LCD_FLAG_SOF Start of frame interrupt enable
-  *        @arg @ref LCD_FLAG_UDD Update display done interrupt
-  * @retval The new state of the LCD_IT
-  */
-it_status_t lcd_get_flag_status(lcd_handle_t *hperh, lcd_flag_t flag)
-{
-	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-	assert_param(IS_LCD_FLAG_TYPE(flag));
-
-	return hperh->perh->IF & flag ? SET : RESET;
-}
-
-/**
-  * @brief Clear interrupt state flag
-  * @param hperh: Pointer to a lcd_handle_t structure that contains
-  *               the configuration information for the specified LCD.
-  * @param flag: Specifies the interrupt type to clear
-  *        This parameter can be one of the following values:
-  *        @arg @ref LCD_FLAG_SOF Start of frame interrupt enable
-  *        @arg @ref LCD_FLAG_UDD Update display done interrupt
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lcd_clear_flag_status(lcd_handle_t *hperh, lcd_flag_t flag)
-{
-	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-	assert_param(IS_LCD_FLAG_TYPE(flag));
-
-	__LOCK(hperh);
-	WRITE_REG(hperh->perh->IFCR, flag);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  This function handles LCD event interrupt request.
-  * @param hperh: Pointer to a lcd_handle_t structure that contains
-  *               the configuration information for the specified LCD.
-  * @retval None
-  */
-void lcd_irq_handler(lcd_handle_t *hperh)
-{
-	if (lcd_get_flag_status(hperh, LCD_FLAG_UDD)) {
-		lcd_clear_flag_status(hperh, LCD_FLAG_UDD);
-
-		if (hperh->display_cplt_cbk)
-			hperh->display_cplt_cbk(hperh);
-	}
-
-	if (lcd_get_flag_status(hperh, LCD_FLAG_SOF)) {
-		lcd_clear_flag_status(hperh, LCD_FLAG_SOF);
-
-		if (hperh->frame_start_cbk)
-			hperh->frame_start_cbk(hperh);
-	}
-
-	return;
-}
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#endif /* ALD_LCD */
-/**
-  * @}
-  */
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lptim.c

@@ -1,675 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_lptim.c
-  * @brief   LPTIM module driver.
-  *	     This is the common part of the LPTIM initialization
-  *
-  * @version V1.0
-  * @date    09 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#include "ald_lptim.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup LPTIM LPTIM
-  * @brief LPTIM module driver
-  * @{
-  */
-#ifdef ALD_LPTIM
-
-/** @defgroup LPTIM_Public_Functions LPTIM Public Functions
-  * @{
-  */
-
-/** @defgroup LPTIM_Public_Functions_Group1 Initialization functions
-  * @brief    Initialization and Configuration functions
-  *
-  * @{
-  */
-/**
-  * @brief  Reset the LPTIM peripheral.
-  * @param  hperh: Pointer to a lptim_handle_t.
-  * @retval None
-  */
-void lptim_reset(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-
-	hperh->state = LPTIM_STATE_BUSY;
-	LPTIM_DISABLE(hperh);
-	hperh->state = LPTIM_STATE_RESET;
-	__UNLOCK(hperh);
-
-	return;
-}
-
-/**
-  * @brief  Configure the LPTIM trigger mode according to the specified parameters in
-  *         the lptim_trigger_init_t.
-  * @param  hperh: Pointer to a lptim_handle_t.
-  * @param  config: Pointer to a lptim_trigger_init_t.
-  * @retval None
-  */
-void lptim_trigger_config(lptim_handle_t *hperh, lptim_trigger_init_t *config)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_TRIGEN(config->mode));
-	assert_param(IS_LPTIM_TRIGSEL(config->sel));
-
-	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRIGEN_MSK, (config->mode) << LP16T_CON0_TRIGEN_POSS);
-	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRIGSEL_MSK, (config->sel) << LP16T_CON0_TRIGSEL_POSS);
-
-	return;
-}
-
-/**
-  * @brief  Configure the LPTIM clock source according to the specified parameters in
-  *         the lptim_clock_source_init_t.
-  * @param  hperh: Pointer to a lptim_handle_t.
-  * @param  config: Pointer to a lptim_clock_source_init_t.
-  * @retval None
-  */
-void lptim_clock_source_config(lptim_handle_t *hperh, lptim_clock_source_init_t *config)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_CKSEL(config->sel));
-	assert_param(IS_LPTIM_CKPOL(config->polarity));
-
-	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKSEL_MSK, (config->sel) << LP16T_CON0_CKSEL_POS);
-	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKPOL_MSK, (config->polarity) << LP16T_CON0_CKPOL_POS);
-
-	return;
-}
-
-/**
-  * @brief  Configure the LPTIM trigger filter parameter according to
-  *         the specified parameters in the lptim_trgflt_t.
-  * @param  hperh: Pointer to a lptim_handle_t.
-  * @param  flt: Pointer to a lptim_trgflt_t.
-  * @retval None
-  */
-void lptim_trigger_filter_config(lptim_handle_t *hperh, lptim_trgflt_t flt)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_TRGFLT(flt));
-
-	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRGFLT_MSK, flt << LP16T_CON0_TRGFLT_POSS);
-
-	return;
-}
-
-/**
-  * @brief  Configure the LPTIM clock filter parameter according to
-  *         the specified parameters in the lptim_ckflt_t.
-  * @param  hperh: Pointer to a lptim_handle_t.
-  * @param  flt: Pointer to a lptim_ckflt_t.
-  * @retval None
-  */
-void lptim_clock_filter_config(lptim_handle_t *hperh, lptim_ckflt_t flt)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_TRGFLT(flt));
-
-	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKFLT_MSK, flt << LP16T_CON0_CKFLT_POSS);
-
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Public_Functions_Group2 LPTIM output toggle functions
-  *  @brief    LPTime output toggle functions
-  *
-  * @verbatim
-  ==============================================================================
-                  ##### Time Output Compare functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize the LPTIM Output Toggle.
-    (+) Start the LPTIM Output Toggle.
-    (+) Stop the LPTIM Output Toggle.
-    (+) Start the LPTIM Output Toggle and enable interrupt.
-    (+) Stop the LPTIM Output Toggle and disable interrupt.
-
-    @endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Output toggle according to the specified
-  *		parameters in the tim_handle_t.
-  * @param  hperh: LPTIM handle
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lptim_toggle_init(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_PRESC(hperh->init.psc));
-
-	__LOCK(hperh);
-	hperh->state = LPTIM_STATE_BUSY;
-
-	cmu_lptim0_clock_select(hperh->init.clock);
-
-	WRITE_REG(hperh->perh->UPDATE, 1);
-	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_TOGGLE << LP16T_CON0_WAVE_POSS);
-	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS);
-	WRITE_REG(hperh->perh->ARR, hperh->init.arr);
-	WRITE_REG(hperh->perh->CMP, hperh->init.cmp);
-	WRITE_REG(hperh->perh->UPDATE, 0);
-
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK));
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK));
-
-	hperh->state = LPTIM_STATE_READY;
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Starts the LPTIM Output toggle.
-  * @param  hperh: LPTIM handle
-  * @retval None
-  */
-void lptim_toggle_start(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_MODE(hperh->init.mode));
-
-	LPTIM_ENABLE(hperh);
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-
-	if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
-		LPTIM_CNTSTART(hperh);
-	else
-		LPTIM_SNGSTART(hperh);
-
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-	return;
-}
-
-/**
-  * @brief  Stops the LPTIM Output toggle.
-  * @param  hperh: LPTIM handle
-  * @retval None
-  */
-void lptim_toggle_stop(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-
-	LPTIM_DISABLE(hperh);
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-	return;
-}
-
-/**
-  * @brief  Starts the LPTIM Output toggle in interrupt mode.
-  * @param  hperh: LPTIM handle
-  * @retval None
-  */
-void lptim_toggle_start_by_it(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_MODE(hperh->init.mode));
-
-	lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE);
-	LPTIM_ENABLE(hperh);
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-
-	if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
-		LPTIM_CNTSTART(hperh);
-	else
-		LPTIM_SNGSTART(hperh);
-
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-	return;
-}
-
-/**
-  * @brief  Stops the LPTIM Output toggle in interrupt mode.
-  * @param  hperh: LPTIM handle
-  * @retval None
-  */
-void lptim_toggle_stop_by_it(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-
-	lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE);
-	LPTIM_DISABLE(hperh);
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Public_Functions_Group3 LPTIM output pulse functions
-  *  @brief    LPTime output pulse functions
-  *
-  * @verbatim
-  ==============================================================================
-                  ##### Time Output Compare functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize the LPTIM Output pulse.
-    (+) Start the LPTIM Output pulse.
-    (+) Stop the LPTIM Output pulse.
-    (+) Start the LPTIM Output pulse and enable interrupt.
-    (+) Stop the LPTIM Output pulse and disable interrupt.
-
-    @endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Output pulse according to the specified
-  *		parameters in the tim_handle_t.
-  * @param  hperh: LPTIM handle
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lptim_pulse_init(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_PRESC(hperh->init.psc));
-
-	__LOCK(hperh);
-	hperh->state = LPTIM_STATE_BUSY;
-	cmu_lptim0_clock_select(hperh->init.clock);
-
-	WRITE_REG(hperh->perh->UPDATE, 1);
-	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_PULSE << LP16T_CON0_WAVE_POSS);
-	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS);
-	WRITE_REG(hperh->perh->ARR, hperh->init.arr);
-	WRITE_REG(hperh->perh->CMP, hperh->init.cmp);
-	WRITE_REG(hperh->perh->UPDATE, 0);
-
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK));
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK));
-
-	hperh->state = LPTIM_STATE_READY;
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Starts the LPTIM Output pulse.
-  * @param  hperh: LPTIM handle
-  * @retval None
-  */
-void lptim_pulse_start(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_MODE(hperh->init.mode));
-
-	LPTIM_ENABLE(hperh);
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-
-	if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
-		LPTIM_CNTSTART(hperh);
-	else
-		LPTIM_SNGSTART(hperh);
-
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-	return;
-}
-
-/**
-  * @brief  Stops the LPTIM Output pulse.
-  * @param  hperh: LPTIM handle
-  * @retval None
-  */
-void lptim_pulse_stop(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-
-	LPTIM_DISABLE(hperh);
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-
-	return;
-}
-
-/**
-  * @brief  Starts the LPTIM Output pulse in interrupt mode.
-  * @param  hperh: LPTIM handle
-  * @retval None
-  */
-void lptim_pulse_start_by_it(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_MODE(hperh->init.mode));
-
-	lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE);
-	LPTIM_ENABLE(hperh);
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-
-	if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
-		LPTIM_CNTSTART(hperh);
-	else
-		LPTIM_SNGSTART(hperh);
-
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-	return;
-}
-
-/**
-  * @brief  Stops the LPTIM Output pulse in interrupt mode.
-  * @param  hperh: LPTIM handle
-  * @retval None
-  */
-void lptim_pulse_stop_by_it(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-
-	lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE);
-	LPTIM_DISABLE(hperh);
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Public_Functions_Group4 LPTIM output pwm functions
-  *  @brief    LPTime output pwm functions
-  *
-  * @verbatim
-  ==============================================================================
-                  ##### Time Output Compare functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize the LPTIM Output pwm.
-    (+) Start the LPTIM Output pwm.
-    (+) Stop the LPTIM Output pwm.
-    (+) Start the LPTIM Output pwm and enable interrupt.
-    (+) Stop the LPTIM Output pwm and disable interrupt.
-
-    @endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Output pwm according to the specified
-  *		parameters in the tim_handle_t.
-  * @param  hperh: LPTIM handle
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lptim_pwm_init(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_PRESC(hperh->init.psc));
-
-	__LOCK(hperh);
-	hperh->state = LPTIM_STATE_BUSY;
-
-	WRITE_REG(hperh->perh->UPDATE, 1);
-	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_PWM << LP16T_CON0_WAVE_POSS);
-	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS);
-	WRITE_REG(hperh->perh->ARR, hperh->init.arr);
-	WRITE_REG(hperh->perh->CMP, hperh->init.cmp);
-	WRITE_REG(hperh->perh->UPDATE, 0);
-
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK));
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK));
-
-	hperh->state = LPTIM_STATE_READY;
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Starts the LPTIM Output pwm.
-  * @param  hperh: LPTIM handle
-  * @retval None
-  */
-void lptim_pwm_start(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_MODE(hperh->init.mode));
-
-	LPTIM_ENABLE(hperh);
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-
-	if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
-		LPTIM_CNTSTART(hperh);
-	else
-		LPTIM_SNGSTART(hperh);
-
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-	return;
-}
-
-/**
-  * @brief  Stops the LPTIM Output pwm.
-  * @param  hperh: LPTIM handle
-  * @retval None
-  */
-void lptim_pwm_stop(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-
-	LPTIM_DISABLE(hperh);
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-
-	return;
-}
-
-/**
-  * @brief  Starts the LPTIM Output pwm in interrupt mode.
-  * @param  hperh: LPTIM handle
-  * @retval None
-  */
-void lptim_pwm_start_by_it(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_MODE(hperh->init.mode));
-
-	lptim_interrupt_config(hperh, LPTIM_IT_CMPMAT, ENABLE);
-	LPTIM_ENABLE(hperh);
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-
-	if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
-		LPTIM_CNTSTART(hperh);
-	else
-		LPTIM_SNGSTART(hperh);
-
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-	return;
-}
-
-/**
-  * @brief  Stops the LPTIM Output pwm in interrupt mode.
-  * @param  hperh: LPTIM handle
-  * @retval None
-  */
-void lptim_pwm_stop_by_it(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-
-	lptim_interrupt_config(hperh, LPTIM_IT_CMPMAT, DISABLE);
-	LPTIM_DISABLE(hperh);
-	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-
-	return;
-}
-/**
-  * @}
-  */
-
-
-/** @defgroup LPTIM_Public_Functions_Group5 Control functions
-  * @brief LPTIM Control functions
-  *
-  * @{
-  */
-/**
-  * @brief  This function handles LPTIM interrupts requests.
-  * @param  hperh: LPTIM  handle
-  * @retval None
-  */
-void lptim_irq_handle(lptim_handle_t *hperh)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-
-	/* Output compare event */
-	if (((lptim_get_it_status(hperh, LPTIM_IT_CMPMAT)) != RESET) &&
-                           ((lptim_get_flag_status(hperh, LPTIM_FLAG_CMPMAT)) != RESET)) {
-		lptim_clear_flag_status(hperh, LPTIM_FLAG_CMPMAT);
-
-		if (hperh->cmp_cbk)
-			hperh->cmp_cbk(hperh);
-	}
-
-	/* Output update event */
-	if (((lptim_get_it_status(hperh, LPTIM_IT_ARRMAT)) != RESET) &&
-                           ((lptim_get_flag_status(hperh, LPTIM_FLAG_ARRMAT)) != RESET)) {
-		lptim_clear_flag_status(hperh, LPTIM_FLAG_ARRMAT);
-
-		if (hperh->update_cbk)
-			hperh->update_cbk(hperh);
-	}
-
-	/* Trigger event */
-	if (((lptim_get_it_status(hperh, LPTIM_IT_EXTTRIG)) != RESET) &&
-                           ((lptim_get_flag_status(hperh, LPTIM_FLAG_EXTTRIG)) != RESET)) {
-		lptim_clear_flag_status(hperh, LPTIM_FLAG_EXTTRIG);
-
-		if (hperh->trig_cbk)
-			hperh->trig_cbk(hperh);
-	}
-
-	return;
-}
-
-/**
-  * @brief  Enables or disables the specified LPTIM interrupts.
-  * @param  hperh: Pointer to a lptim_handle_t structure that contains
-  *         the configuration information for the specified LPTIM module.
-  * @param  it: Specifies the SPI interrupt sources to be enabled or disabled.
-  *         This parameter can be one of the @ref lptim_it_t.
-  * @param  state: New status
-  *           - ENABLE
-  *           - DISABLE
-  * @retval None
-  */
-void lptim_interrupt_config(lptim_handle_t *hperh, lptim_it_t it, type_func_t state)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_IT(it));
-	assert_param(IS_FUNC_STATE(state));
-
-	if (state == ENABLE)
-		SET_BIT(hperh->perh->IER, (uint32_t)it);
-	else
-		CLEAR_BIT(hperh->perh->IER, (uint32_t)it);
-	return;
-}
-
-/**
-  * @brief  Checks whether the specified LPTIM interrupt has occurred or not.
-  * @param  hperh: Pointer to a lptim_handle_t structure that contains
-  *         the configuration information for the specified LPTIM module.
-  * @param  it: Specifies the LPTIM interrupt source to check.
-  *         This parameter can be one of the @ref lptim_it_t.
-  * @retval Status
-  *           - SET
-  *           - RESET
-  */
-it_status_t lptim_get_it_status(lptim_handle_t *hperh, lptim_it_t it)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_IT(it));
-
-	if (READ_BIT(hperh->perh->IER, it))
-		return SET;
-
-	return RESET;
-}
-
-/** @brief  Check whether the specified LPTIM flag is set or not.
-  * @param  hperh: Pointer to a lptim_handle_t structure that contains
-  *         the configuration information for the specified LPTIM module.
-  * @param  flag: specifies the flag to check.
-  *         This parameter can be one of the @ref lptim_flag_t.
-  * @retval Status
-  *           - SET
-  *           - RESET
-  */
-flag_status_t lptim_get_flag_status(lptim_handle_t *hperh, lptim_flag_t flag)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_FLAG(flag));
-
-	if (READ_BIT(hperh->perh->ISR, flag))
-		return SET;
-
-	return RESET;
-}
-
-/** @brief  Clear the specified LPTIM pending flags.
-  * @param  hperh: Pointer to a lptim_handle_t structure that contains
-  *         the configuration information for the specified LPTIM module.
-  * @param  flag: specifies the flag to check.
-  *         This parameter can be one of the @ref lptim_flag_t.
-  * @retval None
-  */
-void lptim_clear_flag_status(lptim_handle_t *hperh, lptim_flag_t flag)
-{
-	assert_param(IS_LPTIM(hperh->perh));
-	assert_param(IS_LPTIM_FLAG(flag));
-
-	WRITE_REG(hperh->perh->IFC, (uint32_t)flag);
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Public_Functions_Group6 Peripheral State functions
- *  @brief   Peripheral State functions
- *
- * @verbatim
-  ==============================================================================
-                        ##### Peripheral State functions #####
-  ==============================================================================
-    [..]
-    This subsection permit to get in run-time the status of the peripheral.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the LPTIM state
-  * @param  hperh: LPTIM handle
-  * @retval LPTIM peripheral state
-  */
-lptim_state_t lptim_get_state(lptim_handle_t *hperh)
-{
-	return hperh->state;
-}
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#endif /* ALD_LPTIM */
-/**
-  * @}
-  */
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lpuart.c

@@ -1,1192 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_lpuart.c
-  * @brief   Low Power UART module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Low Power Universal Asynchronous Receiver
-  *          Transmitter (LPUART) peripheral:
-  *           + Initialization and Configuration functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Errors functions
-  *
-  * @version V1.0
-  * @date    30 May 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  * @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The LPUART driver can be used as follows:
-
-    (#) Declare a lpuart_handle_t handle structure.
-
-    (#) Initialize the LPUART resources:
-        (##) Enable the LPUART interface clock.
-        (##) LPUART pins configuration:
-            (+++) Enable the clock for the LPUART GPIOs.
-            (+++) Configure the LPUART pins (TX as alternate function pull-up, RX as alternate function Input).
-        (##) NVIC configuration if you need to use interrupt process (lpuart_send_by_it()
-             and lpuart_recv_by_it() APIs):
-            (+++) Configure the LPUART interrupt priority.
-            (+++) Enable the NVIC LPUART IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (lpuart_send_by_dma()
-             and lpuart_recv_by_dma() APIs):
-            (+++) Declare a DMA handle structure for the Tx/Rx channel.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required
-                  Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx channel.
-            (+++) Associate the initialized DMA handle to the LPUART DMA Tx/Rx handle.
-
-    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
-        flow control and Mode(Receiver/Transmitter) in the hperh Init structure.
-
-    (#) Initialize the LPUART registers by calling the lpuart_init() API.
-
-     [..]
-        Three operation modes are available within this driver:
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]
-       (+) Send an amount of data in blocking mode using lpuart_send()
-       (+) Receive an amount of data in blocking mode using lpuart_recv()
-
-     *** Interrupt mode IO operation ***
-     ===================================
-     [..]
-       (+) Send an amount of data in non blocking mode using lpuart_send_by_it()
-       (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can
-           add his own code by customization of function pointer hperh->tx_cplt_cbk()
-       (+) Receive an amount of data in non blocking mode using lpuart_recv_by_it()
-       (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can
-           add his own code by customization of function pointer hperh->rx_cplt_cbk()
-       (+) In case of transfer Error, hperh->error_cbk() function is executed and user can
-           add his own code by customization of function pointer hperh->error_cbk()
-
-     *** DMA mode IO operation ***
-     ==============================
-     [..]
-       (+) Send an amount of data in non blocking mode (DMA) using lpuart_send_by_dma()
-       (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can
-           add his own code by customization of function pointer hperh->tx_cplt_cbk()
-       (+) Receive an amount of data in non blocking mode (DMA) using lpuart_recv_by_dma()
-       (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can
-           add his own code by customization of function pointer hperh->rx_cplt_cbk()
-       (+) In case of transfer Error, hperh->error_cbk() function is executed and user can
-           add his own code by customization of function pointer hperh->error_cbk()
-       (+) Pause the DMA Transfer using lpuart_dma_pause()
-       (+) Resume the DMA Transfer using lpuart_dma_resume()
-       (+) Stop the DMA Transfer using lpuart_dma_stop()
-
-    @endverbatim
-  ******************************************************************************
-  */
-
-#include "ald_lpuart.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup LPUART LPUART
-  * @brief Low Power UART module driver
-  * @{
-  */
-#ifdef ALD_LPUART
-
-/** @defgroup LPUART_Private_Functions   LPUART Private Functions
-  *  @brief   LPUART Private functions
-  * @{
-  */
-
-#ifdef ALD_DMA
-/**
-  * @brief  DMA LPUART transmit process complete callback.
-  * @param  arg: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @retval None
-  */
-static void lpuart_dma_send_cplt(void *arg)
-{
-	lpuart_handle_t *hperh = (lpuart_handle_t *)arg;
-
-	hperh->tx_count = 0;
-	lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE);
-	lpuart_interrupt_config(hperh, LPUART_IT_TC, ENABLE);
-}
-
-/**
-  * @brief  DMA LPUART receive process complete callback.
-  * @param  arg: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @retval None
-  */
-static void lpuart_dma_recv_cplt(void *arg)
-{
-	lpuart_handle_t *hperh = (lpuart_handle_t *)arg;
-
-	hperh->rx_count = 0;
-	lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE);
-	CLEAR_BIT(hperh->state, LPUART_STATE_RX_MASK);
-
-	if (hperh->rx_cplt_cbk)
-		hperh->rx_cplt_cbk(hperh);
-}
-
-/**
-  * @brief  DMA LPUART communication error callback.
-  * @param  arg: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @retval None
-  */
-static void lpuart_dma_error(void *arg)
-{
-	lpuart_handle_t *hperh = (lpuart_handle_t *)arg;
-
-	hperh->rx_count  = 0;
-	hperh->tx_count  = 0;
-	hperh->state     = LPUART_STATE_READY;
-	hperh->err_code |= LPUART_ERROR_DMA;
-
-	if (hperh->error_cbk)
-		hperh->error_cbk(hperh);
-}
-#endif
-
-/**
-  * @brief  This function handles uart Communication Timeout.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  flag: specifies the uart flag to check.
-  * @param  status: The new Flag status (SET or RESET).
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t lpuart_wait_flag(lpuart_handle_t *hperh, lpuart_status_t flag, flag_status_t status, uint32_t timeout)
-{
-	uint32_t tick;
-
-	if (timeout == 0)
-		return OK;
-
-	tick = __get_tick();
-
-	/* Waiting for flag */
-	while ((lpuart_get_status(hperh, flag)) != status) {
-		if (((__get_tick()) - tick) > timeout)
-			return TIMEOUT;
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t __lpuart_send_by_it(lpuart_handle_t *hperh)
-{
-	if ((hperh->state & LPUART_STATE_TX_MASK) == 0x0)
-		return BUSY;
-
-	WRITE_REG(hperh->perh->TXDR, *hperh->tx_buf++);
-
-	if (--hperh->tx_count == 0) {
-		lpuart_interrupt_config(hperh, LPUART_IT_TBEMP, DISABLE);
-		lpuart_interrupt_config(hperh, LPUART_IT_TC, ENABLE);
-	}
-
-	return OK;
-}
-
-
-/**
-  * @brief  Wraps up transmission in non blocking mode.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t __lpuart_end_send_by_it(lpuart_handle_t *hperh)
-{
-	lpuart_interrupt_config(hperh, LPUART_IT_TC, DISABLE);
-	CLEAR_BIT(hperh->state, LPUART_STATE_TX_MASK);
-
-	if (hperh->tx_cplt_cbk)
-		hperh->tx_cplt_cbk(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t __lpuart_recv_by_it(lpuart_handle_t *hperh)
-{
-	uint8_t tmp;
-	uint16_t i;
-
-	if ((hperh->state & LPUART_STATE_RX_MASK) == 0x0)
-		return BUSY;
-
-	do {
-		i   = 10000;
-		tmp = hperh->perh->STAT & LPUART_STAT_RXPTR_MSK;
-		*hperh->rx_buf++ = (uint8_t)(hperh->perh->RXDR & 0xFF);
-		--hperh->rx_count;
-
-		while (((hperh->perh->STAT & LPUART_STAT_RXPTR_MSK) != tmp - 1) && (i--));
-	} while (hperh->perh->STAT & LPUART_STAT_RXPTR_MSK);
-
-	if (hperh->rx_count == 0) {
-		lpuart_interrupt_config(hperh, LPUART_IT_RBR, DISABLE);
-		CLEAR_BIT(hperh->state, LPUART_STATE_RX_MASK);
-
-		if (hperh->state == LPUART_STATE_READY) {
-			lpuart_interrupt_config(hperh, LPUART_IT_PERR, DISABLE);
-			lpuart_interrupt_config(hperh, LPUART_IT_FERR, DISABLE);
-		}
-
-		if (hperh->rx_cplt_cbk)
-			hperh->rx_cplt_cbk(hperh);
-	}
-
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_Public_Functions LPUART Public Functions
-  * @{
-  */
-
-/** @defgroup LPUART_Public_Functions_Group1 Initialization and Configuration functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to initialize the LPUART
-    and configure LPUART param.
-      (+) For the LPUART only these parameters can be configured:
-        (++) Baud Rate
-        (++) Word Length
-        (++) Stop Bit
-        (++) Parity
-        (++) Hardware flow control
-      (+) For RS485 mode, user also need configure some parameters by
-      lpuart_rs485_config():
-        (++) Enable/disable normal point mode
-	(++) Enable/disable auto-address detect
-	(++) Enable/disable auto-direction
-	(++) Enable/disable address detect
-	(++) Enable/disable address for compare
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reset LPUART peripheral
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @retval None
-  */
-void lpuart_reset(lpuart_handle_t *hperh)
-{
-	WRITE_REG(hperh->perh->CON0, 0x3000);
-	WRITE_REG(hperh->perh->CON1, 0x4);
-	WRITE_REG(hperh->perh->CLKDIV, 0x0);
-	WRITE_REG(hperh->perh->FIFOCON, 0x0);
-	WRITE_REG(hperh->perh->IER, 0x0);
-	hperh->err_code = LPUART_ERROR_NONE;
-	hperh->state    = LPUART_STATE_RESET;
-
-	__UNLOCK(hperh);
-	return;
-}
-
-/**
-  * @brief  Initializes the LPUART according to the specified
-  *         parameters in the lpuart_handle_t.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @retval None
-  */
-void lpuart_init(lpuart_handle_t *hperh)
-{
-	uint32_t tmp;
-
-	assert_param(IS_LPUART(hperh->perh));
-	assert_param(IS_LPUART_BAUDRATE(hperh->init.baud));
-	assert_param(IS_LPUART_WORD_LENGTH(hperh->init.word_length));
-	assert_param(IS_LPUART_STOPBITS(hperh->init.stop_bits));
-	assert_param(IS_LPUART_PARITY(hperh->init.parity));
-	assert_param(IS_LPUART_MODE(hperh->init.mode));
-	assert_param(IS_LPUART_HARDWARE_FLOW_CONTROL(hperh->init.fctl));
-
-	if ((hperh->init.clock != CMU_LP_PERH_CLOCK_SEL_LOSC)
-			&& (hperh->init.clock != CMU_LP_PERH_CLOCK_SEL_LRC))
-		hperh->init.clock = CMU_LP_PERH_CLOCK_SEL_LRC;
-
-	cmu_lpuart0_clock_select(hperh->init.clock);
-	lpuart_reset(hperh);
-	LPUART_UPDATE_DISABLE(hperh);
-
-	tmp = READ_REG(hperh->perh->CON0);
-	MODIFY_REG(tmp, LPUART_CON0_DATLENTH_MSK, hperh->init.word_length << LPUART_CON0_DATLENTH_POSS);
-	MODIFY_REG(tmp, LPUART_CON0_STPLENTH_MSK, hperh->init.stop_bits << LPUART_CON0_STPLENTH_POS);
-
-	if (hperh->init.parity == LPUART_PARITY_NONE)
-		CLEAR_BIT(tmp, LPUART_CON0_PARCHKE_MSK);
-	else
-		SET_BIT(tmp, LPUART_CON0_PARCHKE_MSK);
-
-	if (hperh->init.parity == LPUART_PARITY_EVEN)
-		SET_BIT(tmp, LPUART_CON0_EVENPARSEL_MSK);
-	else
-		CLEAR_BIT(tmp, LPUART_CON0_EVENPARSEL_MSK);
-
-	MODIFY_REG(tmp, LPUART_CON0_ATRTSE_MSK, (hperh->init.fctl & 1) << LPUART_CON0_ATRTSE_POS);
-	MODIFY_REG(tmp, LPUART_CON0_ATCTSE_MSK, ((hperh->init.fctl >> 1) & 1) << LPUART_CON0_ATCTSE_POS);
-	WRITE_REG(hperh->perh->CON0, tmp);
-	WRITE_REG(hperh->perh->CLKDIV, (32768 << 8) / hperh->init.baud);
-
-	if (hperh->init.mode == LPUART_MODE_IrDA)
-		CLEAR_BIT(hperh->perh->CON1, LPUART_CON1_IRRXINV_MSK);
-
-	MODIFY_REG(hperh->perh->CON0, LPUART_CON0_MODESEL_MSK, hperh->init.mode << LPUART_CON0_MODESEL_POSS);
-	LPUART_UPDATE_ENABLE(hperh);
-
-	while (hperh->perh->SYNCSTAT & 0xF)
-		;
-
-	hperh->state = LPUART_STATE_READY;
-	return;
-}
-
-/**
-  * @brief  Configure the RS485 mode according to the specified
-  *         parameters in the lpuart_rs485_config_Typedef.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  config: Specifies the RS485 parameters.
-  * @retval None
-  */
-void lpuart_rs485_config(lpuart_handle_t *hperh, lpuart_rs485_config_t *config)
-{
-	uint32_t tmp;
-
-	assert_param(IS_LPUART(hperh->perh));
-	assert_param(IS_FUNC_STATE(config->RS485_NMM));
-	assert_param(IS_FUNC_STATE(config->RS485_AAD));
-	assert_param(IS_FUNC_STATE(config->RS485_AUD));
-	assert_param(IS_FUNC_STATE(config->RS485_ADD_DET));
-
-	tmp = READ_REG(hperh->perh->CON1);
-	MODIFY_REG(tmp, LPUART_CON1_NMPMOD_MSK, config->RS485_NMM << LPUART_CON1_NMPMOD_POS);
-	MODIFY_REG(tmp, LPUART_CON1_ATADETE_MSK, config->RS485_AAD << LPUART_CON1_ATADETE_POS);
-	MODIFY_REG(tmp, LPUART_CON1_ATDIRM_MSK, config->RS485_AUD << LPUART_CON1_ATDIRM_POS);
-	MODIFY_REG(tmp, LPUART_CON1_ADETE_MSK, config->RS485_ADD_DET << LPUART_CON1_ADETE_POS);
-	MODIFY_REG(tmp, LPUART_CON1_ADDCMP_MSK, config->RS485_ADDCMP << LPUART_CON1_ADDCMP_POSS);
-	WRITE_REG(hperh->perh->CON1, tmp);
-
-	return;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_Public_Functions_Group2 IO operation functions
-  * @brief    LPUART Transmit and Receive functions
-  * @verbatim
-  ==============================================================================
-                      ##### IO operation functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to manage the LPUART data transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode.
-            The status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) Non blocking mode: The communication is performed using Interrupts
-            or DMA, these APIs return the status.
-            The end of the data processing will be indicated through the
-            dedicated LPUART IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-            The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks
-            will be executed respectively at the end of the transmit or receive process.
-            The hperh->error_cbk() user callback will be executed when
-            a communication error is detected.
-
-    (#) Blocking mode APIs are:
-        (++) lpuart_send()
-        (++) lpuart_recv()
-
-    (#) Non Blocking mode APIs with Interrupt are:
-        (++) lpuart_send_by_it()
-        (++) lpuart_recv_by_it()
-        (++) lpuart_irq_handle()
-
-    (#) Non Blocking mode functions with DMA are:
-        (++) lpuart_send_by_dma()
-        (++) lpuart_recv_by_dma()
-        (++) lpuart_dma_pause()
-        (++) lpuart_dma_resume()
-        (++) lpuart_dma_stop()
-
-    (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
-        (++) hperh->tx_cplt_cbk()
-        (++) hperh->rx_cplt_cbk()
-        (++) hperh->error_cbk()
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sends an amount of data in blocking mode.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lpuart_send(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
-{
-	if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX))
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	__LOCK(hperh);
-	hperh->err_code = LPUART_ERROR_NONE;
-	SET_BIT(hperh->state, LPUART_STATE_TX_MASK);
-
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-
-	while (hperh->tx_count-- > 0) {
-		if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, SET, timeout) != OK) {
-			__UNLOCK(hperh);
-			hperh->state = LPUART_STATE_READY;
-			return TIMEOUT;
-		}
-
-		WRITE_REG(hperh->perh->TXDR, *buf++);
-
-		if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, RESET, timeout) != OK) {
-			__UNLOCK(hperh);
-			hperh->state = LPUART_STATE_READY;
-			return TIMEOUT;
-		}
-	}
-
-	if (lpuart_wait_flag(hperh, LPUART_STAT_TXIDLE, SET, timeout) != OK) {
-		__UNLOCK(hperh);
-		hperh->state = LPUART_STATE_READY;
-		return TIMEOUT;
-	}
-
-	CLEAR_BIT(hperh->state, LPUART_STATE_TX_MASK);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Receives an amount of data in blocking mode.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be received
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lpuart_recv(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
-{
-	if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_TX))
-		return BUSY;
-
-	if ((buf == NULL ) || (size == 0))
-		return  ERROR;
-
-	__LOCK(hperh);
-
-	hperh->err_code = LPUART_ERROR_NONE;
-	SET_BIT(hperh->state, LPUART_STATE_RX_MASK);
-
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-
-	/* Check the remain data to be received */
-	while (hperh->rx_count-- > 0) {
-		if (lpuart_wait_flag(hperh, LPUART_STAT_RXEMP, RESET, timeout) != OK) {
-			__UNLOCK(hperh);
-			hperh->state = LPUART_STATE_READY;
-			return TIMEOUT;
-		}
-
-		*buf++ = (uint8_t)(hperh->perh->RXDR & 0xFF);
-	}
-
-	CLEAR_BIT(hperh->state, LPUART_STATE_RX_MASK);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lpuart_send_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size)
-{
-	if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX))
-		return BUSY;
-
-	if ((buf == NULL ) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-
-	hperh->tx_buf   = buf;
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-	hperh->err_code = LPUART_ERROR_NONE;
-	SET_BIT(hperh->state, LPUART_STATE_TX_MASK);
-
-	__UNLOCK(hperh);
-	lpuart_interrupt_config(hperh, LPUART_IT_TBEMP, ENABLE);
-
-	return OK;
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be received
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lpuart_recv_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size)
-{
-	if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_TX))
-		return BUSY;
-
-	if ((buf == NULL ) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-
-	hperh->rx_buf   = buf;
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-	hperh->err_code = LPUART_ERROR_NONE;
-	SET_BIT(hperh->state, LPUART_STATE_RX_MASK);
-
-	__UNLOCK(hperh);
-
-	lpuart_interrupt_config(hperh, LPUART_IT_PERR, ENABLE);
-	lpuart_interrupt_config(hperh, LPUART_IT_FERR, ENABLE);
-	lpuart_interrupt_config(hperh, LPUART_IT_RBR, ENABLE);
-
-	return OK;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  channel: DMA channel as LPUART transmit
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lpuart_send_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
-{
-	if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX))
-		return BUSY;
-
-	if ((buf == NULL ) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-
-	hperh->tx_buf   = buf;
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-	hperh->err_code = LPUART_ERROR_NONE;
-	SET_BIT(hperh->state, LPUART_STATE_TX_MASK);
-
-	if (hperh->hdmatx.perh == NULL)
-		hperh->hdmatx.perh = DMA0;
-
-	/* Set the dma parameters */
-	hperh->hdmatx.cplt_cbk = lpuart_dma_send_cplt;
-	hperh->hdmatx.cplt_arg = (void *)hperh;
-	hperh->hdmatx.err_cbk  = lpuart_dma_error;
-	hperh->hdmatx.err_arg  = (void *)hperh;
-
-	dma_config_struct(&hperh->hdmatx.config);
-	hperh->hdmatx.config.src     = (void *)buf;
-	hperh->hdmatx.config.dst     = (void *)&hperh->perh->TXDR;
-	hperh->hdmatx.config.size    = size;
-	hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE;
-	hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
-	hperh->hdmatx.config.msel    = DMA_MSEL_LPUART0;
-	hperh->hdmatx.config.msigsel = DMA_MSIGSEL_LPUART_TXEMPTY;
-	hperh->hdmatx.config.channel = channel;
-
-	if (hperh->init.mode == LPUART_MODE_RS485) {
-		hperh->hdmatx.config.src_inc    = DMA_DATA_INC_HALFWORD;
-		hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
-	}
-
-	dma_config_basic(&hperh->hdmatx);
-	lpuart_clear_flag_status(hperh, LPUART_IF_TC);
-	__UNLOCK(hperh);
-	lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, ENABLE);
-
-	return OK;
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be received
-  * @param  channel: DMA channel as LPUART receive
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lpuart_recv_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
-{
-	if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_TX))
-		return BUSY;
-
-	if ((buf == NULL ) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-
-	hperh->rx_buf   = buf;
-	hperh->rx_size  = size;
-	hperh->err_code = LPUART_ERROR_NONE;
-	SET_BIT(hperh->state, LPUART_STATE_RX_MASK);
-
-	if (hperh->hdmarx.perh == NULL)
-		hperh->hdmarx.perh = DMA0;
-
-	/* Set the dma parameters */
-	hperh->hdmarx.cplt_cbk = lpuart_dma_recv_cplt;
-	hperh->hdmarx.cplt_arg = (void *)hperh;
-	hperh->hdmarx.err_cbk  = lpuart_dma_error;
-	hperh->hdmarx.err_arg  = (void *)hperh;
-
-	dma_config_struct(&hperh->hdmarx.config);
-	hperh->hdmarx.config.src     = (void *)&hperh->perh->RXDR;
-	hperh->hdmarx.config.dst     = (void *)buf;
-	hperh->hdmarx.config.size    = size;
-	hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
-	hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE;
-	hperh->hdmarx.config.msel    = DMA_MSEL_LPUART0;
-	hperh->hdmarx.config.msigsel = DMA_MSIGSEL_LPUART_RNR;
-	hperh->hdmarx.config.channel = channel;
-
-	if (hperh->init.mode == LPUART_MODE_RS485) {
-		hperh->hdmarx.config.dst_inc    = DMA_DATA_INC_HALFWORD;
-		hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD;
-	}
-
-	dma_config_basic(&hperh->hdmarx);
-	__UNLOCK(hperh);
-	lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, ENABLE);
-
-	return OK;
-}
-
-/**
-  * @brief  Pauses the DMA Transfer.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lpuart_dma_pause(lpuart_handle_t *hperh)
-{
-	__LOCK(hperh);
-
-	if (hperh->state == LPUART_STATE_BUSY_TX) {
-		lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE);
-	}
-	else if (hperh->state == LPUART_STATE_BUSY_RX) {
-		lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE);
-	}
-	else if (hperh->state == LPUART_STATE_BUSY_TX_RX) {
-		lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE);
-		lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE);
-	}
-	else {
-		__UNLOCK(hperh);
-		return ERROR;
-	}
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Resumes the DMA Transfer.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lpuart_dma_resume(lpuart_handle_t *hperh)
-{
-	__LOCK(hperh);
-
-	if (hperh->state == LPUART_STATE_BUSY_TX) {
-		lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, ENABLE);
-	}
-	else if (hperh->state == LPUART_STATE_BUSY_RX) {
-		lpuart_clear_flag_status(hperh, LPUART_IF_RXOV);
-		lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, ENABLE);
-	}
-	else if (hperh->state == LPUART_STATE_BUSY_TX_RX) {
-		lpuart_clear_flag_status(hperh, LPUART_IF_RXOV);
-		lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, ENABLE);
-		lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, ENABLE);
-	}
-	else {
-		__UNLOCK(hperh);
-		return ERROR;
-	}
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Stops the DMA Transfer.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t lpuart_dma_stop(lpuart_handle_t *hperh)
-{
-	lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE);
-	lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE);
-
-	hperh->state = LPUART_STATE_READY;
-	return OK;
-}
-#endif
-
-/**
-  * @brief  This function handles LPUART interrupt request.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @retval None
-  */
-void lpuart_irq_handle(lpuart_handle_t *hperh)
-{
-	uint32_t flag;
-	uint32_t source;
-
-	/* Handle CTS wakeup */
-	flag = lpuart_get_flag_status(hperh, LPUART_IF_CTSWK);
-	source = lpuart_get_it_status(hperh, LPUART_IT_CTSWK);
-	if ((flag != RESET) && (source != RESET))
-		lpuart_clear_flag_status(hperh, LPUART_IF_CTSWK);
-
-	/* Handle DATA wakeup */
-	flag = lpuart_get_flag_status(hperh, LPUART_IF_DATWK);
-	source = lpuart_get_it_status(hperh, LPUART_IT_DATWK);
-	if ((flag != RESET) && (source != RESET))
-		lpuart_clear_flag_status(hperh, LPUART_IF_DATWK);
-
-	/* Handle parity error */
-	flag   = lpuart_get_flag_status(hperh, LPUART_IF_PERR);
-	source = lpuart_get_it_status(hperh, LPUART_IT_PERR);
-	if ((flag != RESET) && (source != RESET))
-		hperh->err_code |= LPUART_ERROR_PE;
-
-	/* Handle frame error */
-	flag   = lpuart_get_flag_status(hperh, LPUART_IF_FERR);
-	source = lpuart_get_it_status(hperh, LPUART_IT_FERR);
-	if ((flag != RESET) && (source != RESET))
-		hperh->err_code |= LPUART_ERROR_FE;
-
-	/* Handle overflow error */
-	flag   = lpuart_get_flag_status(hperh, LPUART_IF_RXOV);
-	source = lpuart_get_it_status(hperh, LPUART_IT_RXOV);
-	if ((flag != RESET) && (source != RESET))
-		hperh->err_code |= LPUART_ERROR_ORE;
-
-	/* Receive */
-	flag   = lpuart_get_flag_status(hperh, LPUART_IF_RBR);
-	source = lpuart_get_it_status(hperh, LPUART_IT_RBR);
-	if ((flag != RESET) && (source != RESET))
-		__lpuart_recv_by_it(hperh);
-
-	/* Transmite */
-	flag   = lpuart_get_flag_status(hperh, LPUART_IF_TBEMP);
-	source = lpuart_get_it_status(hperh, LPUART_IT_TBEMP);
-	if ((flag != RESET) && (source != RESET))
-		__lpuart_send_by_it(hperh);
-
-	/* End Transmite */
-	flag   = lpuart_get_flag_status(hperh, LPUART_IF_TC);
-	source = lpuart_get_it_status(hperh, LPUART_IT_TC);
-	if ((flag != RESET) && (source != RESET))
-		__lpuart_end_send_by_it(hperh);
-
-	/* Handle error state */
-	if (hperh->err_code != LPUART_ERROR_NONE) {
-		lpuart_clear_flag_status(hperh, LPUART_IF_PERR);
-		lpuart_clear_flag_status(hperh, LPUART_IF_FERR);
-		lpuart_clear_flag_status(hperh, LPUART_IF_RXOV);
-		hperh->state = LPUART_STATE_READY;
-
-		if (hperh->error_cbk)
-			hperh->error_cbk(hperh);
-	}
-}
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_Public_Functions_Group3 Peripheral Control functions
-  *  @brief   Low Power UART control functions
-  *
-  * @verbatim
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to control the LPUART:
-    (+) lpuart_interrupt_config() API can be helpful to configure LPUART interrupt source.
-    (+) lpuart_tx_interval_config() API can be helpful to configure TX interval.
-    (+) lpuart_dma_req_config() API can be helpful to configure LPUART DMA request.
-    (+) lpuart_rx_fifo_it_config() API can be helpful to configure LPUART RX FIFO interrupt.
-    (+) lpuart_rx_fifo_rts_config() API can be helpful to configure RTS threshold value.
-    (+) lpuart_get_flag_status() API can get the status of LPUART flag.
-    (+) lpuart_clear_flag_status() API can clear LPUART flag.
-    (+) lpuart_get_it_status() API can get the status of interrupt source.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enable/disable the specified LPUART interrupts.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  it: Specifies the LPUART interrupt sources to be enabled or
-  *         disabled. This parameter can be one of the @ref lpuart_it_t.
-  * @param  status: New state of the specified LPUART interrupts.
-  *         This parameter can be:
-  *             @arg ENABLE
-  *             @arg DISABLE
-  * @retval None
-  */
-void lpuart_interrupt_config(lpuart_handle_t *hperh, lpuart_it_t it, type_func_t status)
-{
-	assert_param(IS_LPUART(hperh->perh));
-	assert_param(IS_LPUART_IT(it));
-	assert_param(IS_FUNC_STATE(status));
-
-	if (status == ENABLE)
-		SET_BIT(hperh->perh->IER, it);
-	else
-		CLEAR_BIT(hperh->perh->IER, it);
-
-	return;
-}
-
-/**
-  * @brief  Configure transmite interval.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  val: The value of interval.
-  * @retval None
-  */
-void lpuart_tx_interval_config(lpuart_handle_t *hperh, uint8_t val)
-{
-	assert_param(IS_LPUART(hperh->perh));
-
-	MODIFY_REG(hperh->perh->CON0, LPUART_CON0_INTERVAL_MSK, val << LPUART_CON0_INTERVAL_POSS);
-	return;
-}
-
-/**
-  * @brief  Configure LPUART DMA request.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  req: The DMA type:
-  *             @arg LPUART_DMA_REQ_TX
-  *             @arg LPUART_DMA_REQ_RX
-  * @param  status: New state of the specified DMA request.
-  *         This parameter can be:
-  *             @arg ENABLE
-  *             @arg DISABLE
-  * @retval None
-  */
-void lpuart_dma_req_config(lpuart_handle_t *hperh, lpuart_dma_req_t req, type_func_t status)
-{
-	assert_param(IS_LPUART(hperh->perh));
-	assert_param(IS_LPUART_DMAREQ(req));
-	assert_param(IS_FUNC_STATE(status));
-
-	if (req == LPUART_DMA_REQ_TX) {
-		if (status == ENABLE)
-			SET_BIT(hperh->perh->CON0, LPUART_CON0_TXDMAE_MSK);
-		else
-			CLEAR_BIT(hperh->perh->CON0, LPUART_CON0_TXDMAE_MSK);
-	}
-	else {
-		if (status == ENABLE)
-			SET_BIT(hperh->perh->CON0, LPUART_CON0_RXDMAE_MSK);
-		else
-			CLEAR_BIT(hperh->perh->CON0, LPUART_CON0_RXDMAE_MSK);
-	}
-
-	return;
-}
-
-/**
-  * @brief  Configure receive FIFO interrupt threshold value.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  config: The value of RX FIFO interrupt threshold value.
-  * @retval None
-  */
-void lpuart_rx_fifo_it_config(lpuart_handle_t *hperh, lpuart_rxfifo_t config)
-{
-	assert_param(IS_LPUART(hperh->perh));
-	assert_param(IS_LPUART_RXFIFO(config));
-
-	MODIFY_REG(hperh->perh->FIFOCON, LPUART_FIFOCON_RXTRGLVL_MSK, config << LPUART_FIFOCON_RXTRGLVL_POSS);
-	return;
-}
-
-/**
-  * @brief  Configure receive FIFO RTS threshold value.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  config: The value of RX FIFO RTS threshold value.
-  * @retval None
-  */
-void lpuart_rx_fifo_rts_config(lpuart_handle_t *hperh, lpuart_rxfifo_t config)
-{
-	assert_param(IS_LPUART(hperh->perh));
-	assert_param(IS_LPUART_RXFIFO(config));
-
-	MODIFY_REG(hperh->perh->FIFOCON, LPUART_FIFOCON_RTSTRGLVL_MSK, config << LPUART_FIFOCON_RTSTRGLVL_POSS);
-	return;
-}
-
-/**
-  * @brief  Send address in RS485 mode.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  addr: the address of RS485 device.
-  * @param  timeout: Timeout duration
-  * @retval The hal status.
-  */
-ald_status_t lpuart_rs485_send_addr(lpuart_handle_t *hperh, uint16_t addr, uint32_t timeout)
-{
-	assert_param(IS_LPUART(hperh->perh));
-
-	if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX))
-		return BUSY;
-
-	SET_BIT(hperh->state, LPUART_STATE_TX_MASK);
-
-	if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, SET, timeout) != OK) {
-		hperh->state = LPUART_STATE_READY;
-		return TIMEOUT;
-	}
-
-	WRITE_REG(hperh->perh->TXDR, addr | 0x100);
-
-	if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, RESET, timeout) != OK) {
-		hperh->state = LPUART_STATE_READY;
-		return TIMEOUT;
-	}
-
-	if (lpuart_wait_flag(hperh, LPUART_STAT_TXIDLE, SET, timeout) != OK) {
-		hperh->state = LPUART_STATE_READY;
-		return TIMEOUT;
-	}
-
-	CLEAR_BIT(hperh->state, LPUART_STATE_TX_MASK);
-	return OK;
-}
-
-/**
-  * @brief  Get the status of LPUART status.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  flag: Specifies the LPUART status flag.
-  *         This parameter can be one of the @ref lpuart_status_t.
-  * @retval Status:
-  *           - RESET
-  *           - SET
-  */
-flag_status_t lpuart_get_status(lpuart_handle_t *hperh, lpuart_status_t flag)
-{
-	assert_param(IS_LPUART(hperh->perh));
-	assert_param(IS_LPUART_STAT(flag));
-
-	if (READ_BIT(hperh->perh->STAT, flag))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Get the status of LPUART interrupt flag.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  flag: Specifies the LPUART interrupt flag.
-  *         This parameter can be one of the @ref lpuart_flag_t.
-  * @retval Status:
-  *           - RESET
-  *           - SET
-  */
-flag_status_t lpuart_get_flag_status(lpuart_handle_t *hperh, lpuart_flag_t flag)
-{
-	assert_param(IS_LPUART(hperh->perh));
-	assert_param(IS_LPUART_IF(flag));
-
-	if (READ_BIT(hperh->perh->IFLAG, flag))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Clear the LPUART interrupt flag.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  flag: Specifies the LPUART interrupt flag.
-  *         This parameter can be one of the @ref lpuart_flag_t.
-  * @retval None
-  */
-void lpuart_clear_flag_status(lpuart_handle_t *hperh, lpuart_flag_t flag)
-{
-	assert_param(IS_LPUART(hperh->perh));
-	assert_param(IS_LPUART_IF(flag));
-
-	WRITE_REG(hperh->perh->IFC, flag);
-	return;
-}
-
-/**
-  * @brief  Get the status of LPUART interrupt source.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @param  it: Specifies the LPUART interrupt source.
-  *         This parameter can be one of the @ref lpuart_it_t.
-  * @retval Status:
-  *           - RESET
-  *           - SET
-  */
-it_status_t lpuart_get_it_status(lpuart_handle_t *hperh, lpuart_it_t it)
-{
-	assert_param(IS_LPUART(hperh->perh));
-	assert_param(IS_LPUART_IT(it));
-
-	if (READ_BIT(hperh->perh->IER, it))
-		return SET;
-
-	return RESET;
-}
-/**
-  * @}
-  */
-
-/** @defgroup LPUART_Public_Functions_Group4 Peripheral State and Errors functions
-  *  @brief   LPUART State and Errors functions
-  *
-@verbatim
-  ==============================================================================
-                 ##### Peripheral State and Errors functions #####
-  ==============================================================================
- [..]
-   This subsection provides a set of functions allowing to return the State of
-   LPUART communication process, return Peripheral Errors occurred during communication
-   process
-   (+) lpuart_get_state() API can be helpful to check in run-time the state of the LPUART peripheral.
-   (+) lpuart_get_error() check in run-time errors that could be occurred during communication.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the LPUART state.
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART module.
-  * @retval HAL state
-  */
-lpuart_state_t lpuart_get_state(lpuart_handle_t *hperh)
-{
-	return hperh->state;
-}
-
-/**
-  * @brief  Return the LPUART error code
-  * @param  hperh: Pointer to a lpuart_handle_t structure that contains
-  *         the configuration information for the specified LPUART.
-  * @retval LPUART Error Code
-  */
-uint32_t lpuart_get_error(lpuart_handle_t *hperh)
-{
-	return hperh->err_code;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* ALD_LPUART */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pis.c

@@ -1,317 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_pis.c
-  * @brief   PIS module driver.
-  *
-  * @version V1.0
-  * @date    27 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#include "ald_pis.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup PIS PIS
-  * @brief PIS module driver
-  * @{
-  */
-#ifdef ALD_PIS
-
-/** @defgroup PIS_Public_Functions PIS Public Functions
-  * @{
-  */
-
-/** @defgroup PIS_Public_Functions_Group1 Initialization functions
-  * @brief Initialization and Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  Create the PIS mode according to the specified parameters in
-  *         the pis_handle_t and create the associated handle.
-  * @param  hperh: Pointer to a pis_handle_t structure that contains
-  *         the configuration information for the specified PIS module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t pis_create(pis_handle_t *hperh)
-{
-	pis_divide_t temp;
-	uint8_t clock_menu = 0;
-
-	if (hperh == NULL)
-		return ERROR;
-
-	assert_param(IS_PIS_SRC(hperh->init.producer_src));
-	assert_param(IS_PIS_TRIG(hperh->init.consumer_trig));
-	assert_param(IS_PIS_CLOCK(hperh->init.producer_clk));
-	assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk));
-	assert_param(IS_PIS_EDGE(hperh->init.producer_edge));
-
-	__LOCK(hperh);
-	hperh->perh = PIS;
-
-	/* get location of consumer in channel and position of con0/con1
-	 * accord to comsumer_trig information */
-	temp.HalfWord       = (hperh->init.consumer_trig);
-	hperh->consumer_ch  = (pis_ch_t)(temp.ch);
-	hperh->consumer_con = (pis_con_t)(temp.con);
-	hperh->consumer_pos = (1 << temp.shift);
-
-	/* union producer clock and consumer clock */
-	clock_menu = (hperh->init.producer_clk << 4) | (hperh->init.consumer_clk);
-
-	if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) {
-		__UNLOCK(hperh);
-		return BUSY;
-	}
-
-	MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS);
-	MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS);
-
-	/* configure sync clock, judging by producer clock with consumer clock */
-	switch (clock_menu) {
-	case 0x00:
-	case 0x11:
-	case 0x22:
-	case 0x33:
-		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 0 << PIS_CH0_CON_SYNCSEL_POSS);
-		break;
-	case 0x01:
-		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 5 << PIS_CH0_CON_SYNCSEL_POSS);
-		break;
-	case 0x02:
-	case 0x12:
-		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 6 << PIS_CH0_CON_SYNCSEL_POSS);
-		break;
-	case 0x21:
-		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 4 << PIS_CH0_CON_SYNCSEL_POSS);
-		break;
-	case 0x30:
-		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 1 << PIS_CH0_CON_SYNCSEL_POSS);
-		break;
-	case 0x31:
-		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 2 << PIS_CH0_CON_SYNCSEL_POSS);
-		break;
-	case 0x32:
-		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 3 << PIS_CH0_CON_SYNCSEL_POSS);
-	default:
-		break;
-	}
-
-	MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS);
-	MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS);
-	hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch];
-
-	/* enable consumer bit, switch pin of consumer */
-	switch (hperh->consumer_con) {
-	case PIS_CON_0:
-		PIS->TAR_CON0 |= hperh->consumer_pos;
-		break;
-	case PIS_CON_1:
-		PIS->TAR_CON1 |= hperh->consumer_pos;
-		break;
-	default:
-		break;
-	}
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Destroy the PIS mode according to the specified parameters in
-  *         the pis_init_t and create the associated handle.
-  * @param  hperh: Pointer to a pis_handle_t structure that contains
-  *         the configuration information for the specified PIS module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t pis_destroy(pis_handle_t *hperh)
-{
-	assert_param(IS_PIS(hperh->perh));
-
-	if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch])
-		return ERROR;
-
-	__LOCK(hperh);
-
-	CLEAR_BIT(PIS->CH_OER, (1 << hperh->consumer_ch));
-	WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0);
-
-	switch (hperh->consumer_con) {
-	case PIS_CON_0:
-		PIS->TAR_CON0 &= ~(hperh->consumer_pos);
-		break;
-	case PIS_CON_1:
-		PIS->TAR_CON1 &= ~(hperh->consumer_pos);
-		break;
-	default:
-		break;
-	}
-
-	hperh->state = PIS_STATE_RESET;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup PIS_Public_Functions_Group2 Operation functions
-  * @brief PIS output enable or disable functions
-  * @{
-  */
-
-/**
-  * @brief  Start the PIS output function.
-  * @param  hperh: Pointer to a pis_handle_t structure that contains
-  *         the configuration information for the specified PIS module.
-  * @param  ch: The PIS channel enable output
-  *	    This parameter can be one of the following values:
-  *		@arg PIS_OUT_CH_0
-  *		@arg PIS_OUT_CH_1
-  *		@arg PIS_OUT_CH_2
-  *		@arg PIS_OUT_CH_3
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch)
-{
-	assert_param(IS_PIS(hperh->perh));
-	assert_param(IS_PIS_OUPUT_CH(ch));
-	__LOCK(hperh);
-	SET_BIT(PIS->CH_OER, (1 << ch));
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Stop the PIS output function.
-  * @param  hperh: Pointer to a pis_handle_t structure that contains
-  *         the configuration information for the specified PIS module.
-  * @param  ch: The PIS channel disable output
-  *	    This parameter can be one of the following values:
-  *		@arg PIS_OUT_CH_0
-  *		@arg PIS_OUT_CH_1
-  *		@arg PIS_OUT_CH_2
-  *		@arg PIS_OUT_CH_3
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch)
-{
-	assert_param(IS_PIS(hperh->perh));
-	assert_param(IS_PIS_OUPUT_CH(ch));
-	__LOCK(hperh);
-	CLEAR_BIT(PIS->CH_OER, (1 << ch));
-	__UNLOCK(hperh);
-
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup PIS_Public_Functions_Group3 Peripheral State and Errors functions
-  *  @brief   PIS State and Errors functions
-  * @{
-  */
-
-/**
-  * @brief  Returns the PIS state.
-  * @param  hperh: Pointer to a pis_handle_t structure that contains
-  *         the configuration information for the specified PIS module.
-  * @retval ALD state
-  */
-pis_state_t pis_get_state(pis_handle_t *hperh)
-{
-	assert_param(IS_PIS(hperh->perh));
-	return hperh->state;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PIS_Public_Functions_Group4 modulate output functions
-  *  @brief   PIS modulate output signal functions
-  * @{
-  */
-
-/**
-  * @brief  Config the PIS modulate signal function
-  * @param  hperh: Pointer to a pis_handle_t structure that contains
-  *         the configuration information for the specified PIS module.
-  * @param  config: Pointer to a pis_modulate_config_t structure that
-  *         contains the selected target (UART0,UART1,UART2,UART3 or
-  *         LPUART0) how to modulate the target output signal.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config)
-{
-	assert_param(IS_PIS(hperh->perh));
-	assert_param(IS_PIS_MODU_TARGET(config->target));
-	assert_param(IS_PIS_MODU_LEVEL(config->level));
-	assert_param(IS_PIS_MODU_SRC(config->src));
-	assert_param(IS_PIS_MODU_CHANNEL(config->channel));
-	__LOCK(hperh);
-
-	switch (config->target) {
-	case PIS_UART0_TX:
-		MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
-		MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
-		MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
-		break;
-
-	case PIS_UART1_TX:
-		MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
-		MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
-		MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
-		break;
-
-	case PIS_UART2_TX:
-		MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
-		MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
-		MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
-		break;
-
-	case PIS_UART3_TX:
-		MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
-		MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
-		MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
-		break;
-
-	case PIS_LPUART0_TX:
-		MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
-		MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
-		MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
-		break;
-
-	default:
-		break;
-	}
-
-	__UNLOCK(hperh);
-	return OK;
-}
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#endif /* ALD_PIS */
-/**
-  * @}
-  */
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pmu.c

@@ -1,283 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_pmu.c
-  * @brief   PMU module driver.
-  *
-  * @version V1.0
-  * @date    04 Dec 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#include "ald_pmu.h"
-#include "ald_bkpc.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup PMU PMU
-  * @brief PMU module driver
-  * @{
-  */
-#ifdef ALD_PMU
-
-
-/** @defgroup PMU_Private_Functions PMU Private Functions
-  * @{
-  */
-
-/**
-  * @brief  PMU module interrupt handler
-  * @retval None
-  */
-void LVD_Handler(void)
-{
-	SYSCFG_UNLOCK();
-	SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
-	SYSCFG_LOCK();
-
-	lvd_irq_cbk();
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup PMU_Public_Functions PMU Public Functions
-  * @{
-  */
-
-/** @addtogroup PMU_Public_Functions_Group1 Low Power Mode
-  * @brief Low power mode select functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### Low power mode select functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Enter stop1 mode.
-      (+) Enter stop2 mode.
-      (+) Enter standby mode.
-      (+) Get wakeup status.
-      (+) Clear wakeup status.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enter stop1 mode
-  * @retval None
-  */
-void pmu_stop1_enter(void)
-{
-	SYSCFG_UNLOCK();
-	SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);
-	MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP1 << PMU_CR_LPM_POSS);
-	SYSCFG_LOCK();
-
-	SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
-	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-	__WFI();
-	SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
-
-	return;
-}
-
-/**
-  * @brief  Enter stop2 mode
-  * @retval None
-  */
-void pmu_stop2_enter(void)
-{
-	SYSCFG_UNLOCK();
-	SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);
-	MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP2 << PMU_CR_LPM_POSS);
-	SYSCFG_LOCK();
-
-	SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
-	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-	__WFI();
-	SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
-
-	return;
-
-}
-
-/**
-  * @brief  Enter standby mode
-  * @param  port: The port whick wake up the standby mode.
-  * @retval None
-  */
-void pmu_standby_enter(pmu_standby_wakeup_sel_t port)
-{
-	assert_param(IS_PMU_STANDBY_PORT_SEL(port));
-
-	if (port != PMU_STANDBY_PORT_NONE) {
-		BKPC_UNLOCK();
-		SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);
-		MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS);
-		SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK);
-		BKPC_LOCK();
-
-		SYSCFG_UNLOCK();
-		MODIFY_REG(PMU->CR, PMU_CR_WKPS_MSK, port << PMU_CR_WKPS_POSS);
-		SET_BIT(PMU->CR, PMU_CR_WKPEN_MSK);
-		MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STANDBY << PMU_CR_LPM_POSS);
-		SYSCFG_LOCK();
-	}
-
-	SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
-	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-	__WFI();
-	SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
-
-	return;
-}
-
-/**
-  * @brief  Configures low power mode. The system clock must
-  *         be less than 2MHz. Such as: LOSC or LRC.
-  * @param  vol: LDO output voltage select in low power mode.
-  * @param  state: New state, ENABLE/DISABLE;
-  * @retval None
-  */
-void pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state)
-{
-	assert_param(IS_FUNC_STATE(state));
-	SYSCFG_UNLOCK();
-
-	if (state) {
-		assert_param(IS_PMU_LDO_LPMODE_OUTPUT(vol));
-
-		MODIFY_REG(PMU->CR, PMU_CR_LPVS_MSK, vol << PMU_CR_LPVS_POSS);
-		SET_BIT(PMU->CR, PMU_CR_LPRUN_MSK);
-	}
-	else {
-		CLEAR_BIT(PMU->CR, PMU_CR_LPRUN_MSK);
-	}
-
-	SYSCFG_LOCK();
-	return;
-}
-
-/**
-  * @brief  Get wakup status.
-  * @param  sr: Status bit.
-  * @retval Status.
-  */
-flag_status_t pmu_get_status(pmu_status_t sr)
-{
-	assert_param(IS_PMU_STATUS(sr));
-
-	if (READ_BIT(PMU->SR, sr))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Clear wakup status.
-  * @param  sr: Status bit.
-  * @retval None
-  */
-void pmu_clear_status(pmu_status_t sr)
-{
-	assert_param(IS_PMU_STATUS(sr));
-	SYSCFG_UNLOCK();
-
-	if (sr == PMU_SR_WUF)
-		SET_BIT(PMU->CR, PMU_CR_CWUF_MSK);
-	else
-		SET_BIT(PMU->CR, PMU_CR_CSTANDBYF_MSK);
-
-	SYSCFG_LOCK();
-	return;
-}
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup PMU_Public_Functions_Group2 LVD Configure
-  * @brief LVD configure functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### LVD configure functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure lvd parameters.
-      (+) Interrupt callback function.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure lvd using specified parameters.
-  * @param  sel: LVD threshold voltage.
-  * @param  mode: LVD trigger mode.
-  * @param  state: New state, ENABLE/DISABLE;
-  * @retval None
-  */
-void pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state)
-{
-	assert_param(IS_FUNC_STATE(state));
-	SYSCFG_UNLOCK();
-
-	if (state) {
-		assert_param(IS_PMU_LVD_VOL_SEL(sel));
-		assert_param(IS_PMU_LVD_TRIGGER_MODE(mode));
-
-		MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS);
-		MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS);
-		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK);
-		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
-		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
-		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
-	}
-	else {
-		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
-		CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
-		CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
-	}
-
-	SYSCFG_LOCK();
-	return;
-}
-
-/**
-  * @brief  Interrupt callback function.
-  * @note   This function is declared as __weak to be overwritten in case of other
-  *         implementations in user file.
-  * @retval None
-  */
-__weak void lvd_irq_cbk(void)
-{
-	return;
-}
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-#endif /* ALD_PMU */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rmu.c

@@ -1,143 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_rmu.c
-  * @brief   RMU module driver.
-  *
-  * @version V1.0
-  * @date    04 Dec 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#include "ald_rmu.h"
-#include "ald_syscfg.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup RMU RMU
-  * @brief RMU module driver
-  * @{
-  */
-#ifdef ALD_RMU
-
-/** @defgroup RMU_Public_Functions RMU Public Functions
-  * @{
-  */
-
-/**
-  * @brief  Configure BOR parameters.
-  * @param  flt: filter time.
-  * @param  vol: The voltage.
-  * @param  state: The new status: ENABLE/DISABLE.
-  * @retval None
-  */
-void rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state)
-{
-	assert_param(IS_FUNC_STATE(state));
-
-	SYSCFG_UNLOCK();
-
-	if (state) {
-		assert_param(IS_RMU_BORFLT(flt));
-		assert_param(IS_RMU_BORVOL(vol));
-
-		MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS);
-		MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS);
-		SET_BIT(RMU->CR, RMU_CR_BOREN_MSK);
-	}
-	else {
-		CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK);
-	}
-
-	SYSCFG_LOCK();
-	return;
-}
-
-/**
-  * @brief  Get specified reset status
-  * @param  state: Speicifies the type of the reset,
-  * @retval The status: SET/RESET.
-  */
-flag_status_t rmu_get_reset_status(rmu_state_t state)
-{
-	assert_param(IS_RMU_STATE(state));
-
-	if (READ_BIT(RMU->RSTSR, state))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Clear the specified reset status
-  * @param  state: Specifies the type of the reset,
-  * @retval None
-  */
-void rmu_clear_reset_status(rmu_state_t state)
-{
-	assert_param(IS_RMU_STATE_CLEAR(state));
-
-	SYSCFG_UNLOCK();
-	WRITE_REG(RMU->CRSTSR, state);
-	SYSCFG_LOCK();
-
-	return;
-}
-/**
-  * @brief  Reset peripheral device
-  * @param  perh: The peripheral device,
-  * @retval None
-  */
-void rmu_reset_periperal(rmu_peripheral_t perh)
-{
-	uint32_t idx, pos;
-
-	assert_param(IS_RMU_PERH(perh));
-
-	idx = (perh >> 27) & 0x7;
-	pos = perh & ~(0x7 << 27);
-	SYSCFG_UNLOCK();
-
-	switch (idx) {
-	case 0:
-		WRITE_REG(RMU->AHB1RSTR, pos);
-		break;
-
-	case 1:
-		WRITE_REG(RMU->AHB2RSTR, pos);
-		break;
-
-	case 2:
-		WRITE_REG(RMU->APB1RSTR, pos);
-		break;
-
-	case 4:
-		WRITE_REG(RMU->APB2RSTR, pos);
-		break;
-
-	default:
-		break;
-	}
-
-	SYSCFG_LOCK();
-	return;
-}
-
-/**
-  * @}
-  */
-#endif /* ALD_RMU */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rtc.c

@@ -1,1193 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ald_rtc.c
-  * @brief   RTC module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the RTC peripheral:
-  *           + Initialization  functions
-  *           + Time and date functions
-  *           + Alarm functions
-  *           + Time stamp functions
-  *           + Tamper functions
-  *           + Wake-up functions
-  *           + Clock output functions
-  *           + Peripheral Control functions
-  * @version V1.0
-  * @date    25 Apr 2017
-  * @author  AE Team
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  ********************************************************************************
-  * @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      (+) Enable the RTC controller interface clock.
-      (+) Select the RTC source clock(default LOSC).
-      (+) Configure the RTC asynchronous prescaler, synchronous prescaler and hour
-          format using the rtc_init() function.
-
-     *** Time and date operation ***
-     =================================
-     [..]
-       (+) To configure the time use the rtc_set_time() function.
-       (+) To configure the date use the rtc_set_date() function.
-       (+) To read the time use the rtc_get_time() function.
-       (+) To read the date use the rtc_get_date() function.
-
-     *** Alarm operation ***
-     ===================================
-     [..]
-       (+) To configure the alarm use rtc_set_alarm() function
-       (+) To read the alarm use rtc_get_alarm() function
-       (+) To cancel the alarm use rtc_alarm_cmd() function
-
-     *** Time stamp operation ***
-     ===================================
-     [..]
-       (+) To configure the time stamp use rtc_set_time_stamp() function
-       (+) To read the time stamp use rtc_get_time_stamp() function
-       (+) To cancel the time stamp use rtc_cancel_time_stamp() function
-
-     *** Tamper operation ***
-     ===================================
-     [..]
-       (+) To configure the tamper use rtc_set_tamper() function
-       (+) To cancel the tamper use rtc_alarm_cmd() function
-
-     *** Wake-up operation ***
-     ===================================
-     [..]
-       (+) To configure the wake-up parameters use rtc_set_wakeup() function
-       (+) To read the re-load register value use rtc_get_wakeup_timer_value() function
-       (+) To cancel the wake-up use rtc_cancel_wakeup() function
-
-     *** Output clock operation ***
-     ===================================
-     [..]
-       (+) To configure the clock output type use rtc_set_clock_output() function
-       (+) To cancel the clock output use rtc_cancel_clock_output() function
-
-     *** Control functions ***
-     ===================================
-     [..]
-       (+) Configure interrupt enable/disable.
-       (+) Enable/disable alarm.
-       (+) Configure rtc shift.
-       (+) Calibrate time.
-       (+) Get interrupt source status.
-       (+) Get interrupt flag status.
-       (+) Clear interrupt flag.
-
-  ==================================================================
-                  ##### RTC and low power modes #####
-  ==================================================================
-  [..] The MCU can be woken up from a low power mode by an RTC alternate function.
-  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
-       RTC wake-up, RTC tamper event detection and RTC time stamp event detection.
-       These RTC alternate functions can wake up the system from the Stop and
-       Standby low power modes.
-  [..] The system can also wake up from low power modes without depending
-       on an external interrupt (Auto-wake-up mode), by using the RTC alarm
-       or the RTC wake-up events.
-  [..] The RTC provides a programmable time base for waking up from the Stop or
-       Standby mode at regular intervals. Wake-up from STOP and STANDBY modes
-       is possible only when the RTC clock source is LSE or LSI.
-
-     *** RTC driver macros list ***
-     =============================================
-     [..]
-       Below the list of most used macros in RTC driver.
-
-      (+) RTC_UNLOCK() Disable the protect.
-      (+) RTC_LOCK() Enable the protect.
-      (+) RTC_BY_PASS_ENABLE() Enable the by-pass shadow register.
-      (+) RTC_BY_PASS_DISABLE() Disable the by-pass shadow register.
-      (+) RTC_SUMMER_TIME_ENABLE() Enable summer time.
-      (+) RTC_SUMMER_TIME_DISABLE() Disable summer time.
-      (+) RTC_WINTER_TIME_ENABLE() Enable winter time.
-      (+) RTC_WINTER_TIME_DISABLE() Disable winter time.
-     [..]
-      (@) You can refer to the RTC driver header file for used the macros
-
-    @endverbatim
-  ******************************************************************************
-  */
-
-#include "ald_rtc.h"
-#include "ald_bkpc.h"
-#include "ald_temp.h"
-#include "ald_syscfg.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup RTC RTC
-  * @brief RTC module driver
-  * @{
-  */
-#ifdef ALD_RTC
-
-/** @addtogroup RTC_Private_Functions  RTC Private Functions
-  * @{
-  */
-/**
-  * @brief  Converts form 2 digit BCD to Binary.
-  * @param  bcd: BCD value to be converted.
-  * @retval Converted word.
-  */
-static uint32_t bcd_to_dec(uint32_t bcd)
-{
-	return ((bcd & 0xF) + ((bcd >> 4) & 0xF) * 10);
-}
-
-/**
-  * @brief  Converts a 2 digit decimal to BCD format.
-  * @param  dec: Byte to be converted.
-  * @retval Converted byte.
-  */
-static uint32_t dec_to_bcd(uint32_t dec)
-{
-	return (((dec / 10) << 4) | (dec % 10));
-}
-
-/**
-  * @brief  Time and Date consistency check.
-  * @param  t_last: Last time.
-  * @param  d_last: Last date.
-  * @param  time: Current time.
-  * @param  date: Current time.
-  * @retval status:
-  *           0 - Not consistency
-  *           1 - Consistency
-  */
-static int32_t rtc_consistency_check(rtc_time_t *t_last,
-			rtc_date_t *d_last, rtc_time_t *time, rtc_date_t *date)
-{
-	if (t_last->second != time->second)
-		return 0;
-	if (t_last->minute != time->minute)
-		return 0;
-	if (t_last->hour != time->hour)
-		return 0;
-	if (d_last->day != date->day)
-		return 0;
-	if (d_last->month != date->month)
-		return 0;
-	if (d_last->year != date->year)
-		return 0;
-
-	return 1;
-}
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Public_Functions RTC Public Functions
-  * @{
-  */
-
-/** @defgroup RTC_Public_Functions_Group1 Initialization functions
-  * @brief    Initialization functions
-  *
-  * @verbatim
- ===============================================================================
-              ##### Initialization function #####
- ===============================================================================
-   [..] This section provides functions allowing to initialize and configure the
-         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
-         RTC registers Write protection.
-         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
-             It is split into 2 programmable prescalers to minimize power consumption.
-             (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.
-             (++) When both prescalers are used, it is recommended to configure the
-                 asynchronous prescaler to a high value to minimize power consumption.
-         (#) All RTC registers are Write protected. Writing to the RTC registers
-             is enabled by writing a key into the Write Protection register.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reset RTC register.
-  * @retval None
-  */
-void rtc_reset(void)
-{
-	RTC_UNLOCK();
-
-	WRITE_REG(RTC->CON, 0x0);
-	WRITE_REG(RTC->TAMPCON, 0x0);
-	WRITE_REG(RTC->WUMAT, 0x0);
-	WRITE_REG(RTC->IER, 0x0);
-	WRITE_REG(RTC->IFCR, ~0x0);
-
-	RTC_LOCK();
-	return;
-}
-
-/**
-  * @brief  Initialize the RTC module.
-  * @param  init: Pointer to rtc_init_t structure which contains
-  *         the configuration parameters.
-  * @retval None
-  */
-void rtc_init(rtc_init_t *init)
-{
-	assert_param(IS_RTC_HOUR_FORMAT(init->hour_format));
-	assert_param(IS_RTC_OUTPUT_SEL(init->output));
-	assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity));
-
-	rtc_reset();
-	RTC_UNLOCK();
-
-	MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS);
-	MODIFY_REG(RTC->CON, RTC_CON_EOS_MSK, init->output << RTC_CON_EOS_POSS);
-	MODIFY_REG(RTC->CON, RTC_CON_POL_MSK, init->output_polarity << RTC_CON_POL_POS);
-	MODIFY_REG(RTC->PSR, RTC_PSR_SPRS_MSK, init->synch_pre_div << RTC_PSR_SPRS_POSS);
-	MODIFY_REG(RTC->PSR, RTC_PSR_APRS_MSK, init->asynch_pre_div << RTC_PSR_APRS_POSS);
-	SET_BIT(RTC->CON, RTC_CON_GO_MSK);
-
-	RTC_LOCK();
-	return;
-}
-
-/**
-  * @brief  Configure the RTC source.
-  * @param  sel: RTC source type.
-  * @retval None
-  */
-void rtc_source_selcet(rtc_source_sel_t sel)
-{
-	assert_param(IS_RTC_SOURCE_SEL(sel));
-
-	BKPC_UNLOCK();
-	MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, sel << BKPC_PCCR_RTCCS_POSS);
-
-	if (sel == RTC_SOURCE_LOSC) {
-		SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);
-	}
-	else if (sel == RTC_SOURCE_LRC) {
-		SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);
-	}
-	else {
-		; /* do nothing */
-	}
-
-	BKPC_LOCK();
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Public_Functions_Group2 Time and Date functions
-  * @brief    RTC Time and Date functions
-  *
-  * @verbatim
- ===============================================================================
-                 ##### Time and Date functions #####
- ===============================================================================
-
- [..] This section provides functions allowing:
-     [#]
-       (+) To configure the time use the rtc_set_time() function.
-       (+) To configure the date use the rtc_set_date() function.
-       (+) To read the time use the rtc_get_time() function.
-       (+) To read the date use the rtc_get_date() function.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set specified time.
-  * @param  time: pointer to a rtc_time_t structure.
-  * @param  format: Data format.
-  * @retval ALD status.
-  */
-ald_status_t  rtc_set_time(rtc_time_t *time, rtc_format_t format)
-{
-	uint32_t tmp;
-
-	assert_param(IS_RTC_FORMAT(format));
-
-	if (format == RTC_FORMAT_DEC) {
-		assert_param(IS_RTC_SECOND(time->second));
-		assert_param(IS_RTC_MINUTE(time->minute));
-		assert_param(IS_RTC_HOUR(time->hour));
-
-		tmp = (dec_to_bcd(time->second)) |
-			(dec_to_bcd(time->minute) << 8) |
-			(dec_to_bcd(time->hour) << 16);
-	}
-	else {
-		assert_param(IS_RTC_SECOND(bcd_to_dec(time->second)));
-		assert_param(IS_RTC_MINUTE(bcd_to_dec(time->minute)));
-		assert_param(IS_RTC_HOUR(bcd_to_dec(time->hour)));
-
-		tmp = time->second | (time->minute << 8) | (time->hour << 16);
-	}
-
-	RTC_UNLOCK();
-	WRITE_REG(RTC->TIME, tmp);
-	WRITE_REG(RTC->SSEC, time->sub_sec);
-	RTC_LOCK();
-
-	tmp = __get_tick();
-
-	while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) {
-		if ((__get_tick() - tmp) > RTC_TIMEOUT_VALUE)
-			return TIMEOUT;
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  Set specified date.
-  * @param  date: pointer to a rtc_date_t structure.
-  * @param  format: Data format.
-  * @retval ALD status.
-  */
-ald_status_t rtc_set_date(rtc_date_t *date, rtc_format_t format)
-{
-	uint32_t tmp;
-
-	assert_param(IS_RTC_FORMAT(format));
-
-	if (format == RTC_FORMAT_DEC) {
-		assert_param(IS_RTC_DAY(date->day));
-		assert_param(IS_RTC_MONTH(date->month));
-		assert_param(IS_RTC_YEAR(date->year));
-
-		tmp = (dec_to_bcd(date->day)) |
-			(dec_to_bcd(date->month) << 8) |
-			(dec_to_bcd(date->year) << 16) |
-			(dec_to_bcd(date->week) << 24);
-	}
-	else {
-		assert_param(IS_RTC_DAY(bcd_to_dec(date->day)));
-		assert_param(IS_RTC_MONTH(bcd_to_dec(date->month)));
-		assert_param(IS_RTC_YEAR(bcd_to_dec(date->year)));
-
-		tmp = date->day | (date->month << 8) |
-			(date->year << 16) | (date->week << 24);
-	}
-
-	RTC_UNLOCK();
-	WRITE_REG(RTC->DATE, tmp);
-	RTC_LOCK();
-
-	tmp = __get_tick();
-
-	while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) {
-		if ((__get_tick() - tmp) > RTC_TIMEOUT_VALUE)
-			return TIMEOUT;
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  Get current time.
-  * @param  time: pointer to a rtc_time_t structure.
-  * @param  format: Data format.
-  * @retval None
-  */
-void rtc_get_time(rtc_time_t *time, rtc_format_t format)
-{
-	uint32_t tmp;
-
-	assert_param(time != NULL);
-	assert_param(IS_RTC_FORMAT(format));
-
-	time->sub_sec = RTC->SSEC & 0xFFFF;
-	tmp = RTC->TIME;
-
-	if (format == RTC_FORMAT_DEC) {
-		time->second = bcd_to_dec(tmp & 0x7F);
-		time->minute = bcd_to_dec((tmp >> 8) & 0x7F);
-		time->hour   = bcd_to_dec((tmp >> 16) & 0x7F);
-	}
-	else {
-		time->second = tmp & 0x7F;
-		time->minute = (tmp >> 8) & 0x7F;
-		time->hour   = (tmp >> 16) & 0x7F;
-	}
-
-	return;
-}
-
-/**
-  * @brief  Get current date.
-  * @param  date: pointer to a rtc_date_t structure.
-  * @param  format: Data format.
-  * @retval None
-  */
-void rtc_get_date(rtc_date_t *date, rtc_format_t format)
-{
-	uint32_t tmp = RTC->DATE;
-
-	assert_param(date != NULL);
-	assert_param(IS_RTC_FORMAT(format));
-
-	if (format == RTC_FORMAT_DEC) {
-		date->day   = bcd_to_dec(tmp & 0x3F);
-		date->month = bcd_to_dec((tmp >> 8) & 0x1F);
-		date->year  = bcd_to_dec((tmp >> 16) & 0xFF);
-		date->week  = bcd_to_dec((tmp >> 24) & 0x7);
-	}
-	else {
-		date->day   = tmp & 0x3F;
-		date->month = (tmp >> 8) & 0x1F;
-		date->year  = (tmp >> 16) & 0xFF;
-		date->week  = (tmp >> 24) & 0x7;
-	}
-
-	return;
-}
-
-/**
-  * @brief  Get time and date consistency.
-  * @param  date: pointer to a rtc_date_t structure.
-  * @param  time: pointer to a rtc_time_t structure.
-  * @param  format: Data format.
-  * @retval Status:
-  *            0 - Consistency
-  *           -1 - Not consistency
-  */
-int32_t rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format)
-{
-	int32_t nr = 3;
-	rtc_date_t d_last;
-	rtc_time_t t_last;
-
-	while (nr--) {
-		rtc_get_time(&t_last, format);
-		rtc_get_date(&d_last, format);
-		rtc_get_time(time, format);
-		rtc_get_date(date, format);
-
-		if (rtc_consistency_check(&t_last, &d_last, time, date))
-			return 0;
-	}
-
-	return -1;
-}
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Public_Functions_Group3 Alarm functions
-  * @brief    RTC alarm functions
-  *
-  * @verbatim
- ===============================================================================
-                 ##### Alarm functions #####
- ===============================================================================
-
- [..] This section provides functions allowing:
-     [#]
-       (+) To configure the alarm use rtc_set_alarm() function
-       (+) To read the alarm use rtc_get_alarm() function
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set alarm.
-  * @param  alarm: pointer to rtc_alarm_t struct.
-  * @param  format: Data format.
-  * @retval None
-  */
-void rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format)
-{
-	unsigned int tmp, ss_tmp;
-
-	assert_param(IS_RTC_ALARM(alarm->idx));
-	assert_param(IS_RTC_ALARM_SEL(alarm->sel));
-	assert_param(IS_RTC_ALARM_SS_MASK(alarm->ss_mask));
-	assert_param(IS_RTC_FORMAT(format));
-
-	if (format == RTC_FORMAT_DEC) {
-		assert_param(IS_RTC_SECOND(alarm->time.second));
-		assert_param(IS_RTC_MINUTE(alarm->time.minute));
-		assert_param(IS_RTC_HOUR(alarm->time.hour));
-
-		tmp = (dec_to_bcd(alarm->time.second)) |
-		      (dec_to_bcd(alarm->time.minute) << 8) |
-		      (dec_to_bcd(alarm->time.hour) << 16) |
-		      alarm->mask;
-
-		if (alarm->sel == RTC_SELECT_DAY) {
-			assert_param(IS_RTC_DAY(alarm->day));
-
-			tmp |= (dec_to_bcd(alarm->day) << 24);
-			tmp &= 0x7FFFFFFF; /* Reset bit31 */
-		}
-		else {
-			tmp |= (1 << (alarm->week + 24));
-			tmp |= 0x80000000; /* Set bit31 */
-		}
-	}
-	else {
-		assert_param(IS_RTC_SECOND(bcd_to_dec(alarm->time.second)));
-		assert_param(IS_RTC_MINUTE(bcd_to_dec(alarm->time.minute)));
-		assert_param(IS_RTC_HOUR(bcd_to_dec(alarm->time.hour)));
-
-		tmp = alarm->time.second |
-		      (alarm->time.minute << 8) |
-		      (alarm->time.hour << 16) |
-		      alarm->mask;
-
-		if (alarm->sel == RTC_SELECT_DAY) {
-			assert_param(IS_RTC_DAY(bcd_to_dec(alarm->day)));
-
-			tmp |= (alarm->day << 24);
-			tmp &= 0x7FFFFFFF; /* Reset bit31 */
-		}
-		else {
-			tmp |= (1 << (alarm->week + 24));
-			tmp |= 0x80000000; /* Set bit31 */
-		}
-	}
-
-	ss_tmp = (alarm->time.sub_sec & 0x7F) |
-	         (alarm->ss_mask << 24);
-
-	RTC_UNLOCK();
-
-	if (alarm->idx == RTC_ALARM_A) {
-		WRITE_REG(RTC->ALMA, tmp);
-		WRITE_REG(RTC->ALMASSEC, ss_tmp);
-		SET_BIT(RTC->CON, RTC_CON_ALMAEN_MSK);
-	}
-	else {
-		WRITE_REG(RTC->ALMB, tmp);
-		WRITE_REG(RTC->ALMBSSEC, ss_tmp);
-		SET_BIT(RTC->CON, RTC_CON_ALMBEN_MSK);
-	}
-
-	RTC_LOCK();
-	return;
-}
-
-/**
-  * @brief  Get alarm parameters.
-  * @param  alarm: pointer to rtc_alarm_t struct.
-  * @param  format: Data format.
-  * @retval None
-  */
-void rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format)
-{
-	uint8_t week;
-	uint32_t tmp, ss_tmp;
-
-	assert_param(alarm != NULL);
-	assert_param(IS_RTC_FORMAT(format));
-
-	if (alarm->idx == RTC_ALARM_A) {
-		tmp    = RTC->ALMA;
-		ss_tmp = RTC->ALMASSEC;
-	}
-	else {
-		tmp    = RTC->ALMB;
-		ss_tmp = RTC->ALMBSSEC;
-	}
-
-	if ((tmp >> 31) & 0x1) {
-		alarm->sel = RTC_SELECT_WEEK;
-		week = ((tmp >> 24) & 0x7F);
-
-		switch (week) {
-		case 1:
-			alarm->week = 0;
-			break;
-		case 2:
-			alarm->week = 1;
-			break;
-		case 4:
-			alarm->week = 2;
-			break;
-		case 8:
-			alarm->week = 3;
-			break;
-		case 16:
-			alarm->week = 4;
-			break;
-		case 32:
-			alarm->week = 5;
-			break;
-		case 64:
-			alarm->week = 6;
-			break;
-		default:
-			break;
-		}
-	}
-	else {
-		alarm->sel = RTC_SELECT_DAY;
-
-		if (format == RTC_FORMAT_DEC)
-			alarm->day = bcd_to_dec((tmp >> 24) & 0x3F);
-		else
-			alarm->day = (tmp >> 24) & 0x3F;
-	}
-
-	if (format == RTC_FORMAT_DEC) {
-		alarm->time.second  = bcd_to_dec(tmp & 0x7F);
-		alarm->time.minute  = bcd_to_dec((tmp >> 8) & 0x7F);
-		alarm->time.hour    = bcd_to_dec((tmp >> 16) & 0x3F);
-	}
-	else {
-		alarm->time.second  = tmp & 0x7F;
-		alarm->time.minute  = (tmp >> 8) & 0x7F;
-		alarm->time.hour    = (tmp >> 16) & 0x3F;
-	}
-
-	alarm->time.sub_sec = ss_tmp & 0x7FFF;
-	alarm->ss_mask      = (rtc_sub_second_mask_t)((ss_tmp >> 24) & 0xF);
-	alarm->mask         = tmp & ALARM_MASK_ALL;
-
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Public_Functions_Group4 Time stamp functions
-  * @brief    RTC time stamp functions
-  *
-  * @verbatim
- ===============================================================================
-                 ##### Time stamp functions #####
- ===============================================================================
-
- [..] This section provides functions allowing:
-     [#]
-       (+) To configure the time stamp use rtc_set_time_stamp() function
-       (+) To read the time stamp use rtc_get_time_stamp() function
-       (+) To cancel the time stamp use rtc_cancel_time_stamp() function
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set time stamp.
-  * @param  sel: time stamp signal select:
-  *           @arg RTC_TS_SIGNAL_SEL_TAMPER0
-  *           @arg RTC_TS_SIGNAL_SEL_TAMPER1
-  * @param  style: time stamp trigger style:
-  *           @arg RTC_TS_RISING_EDGE
-  *           @arg RTC_TS_FALLING_EDGE
-  * @retval None
-  */
-void rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style)
-{
-	assert_param(IS_RTC_TS_SIGNAL(sel));
-	assert_param(IS_RTC_TS_STYLE(style));
-
-	RTC_UNLOCK();
-
-	CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK);
-	MODIFY_REG(RTC->CON, RTC_CON_TSSEL_MSK, style << RTC_CON_TSSEL_POS);
-	MODIFY_REG(RTC->CON, RTC_CON_TSPIN_MSK, sel << RTC_CON_TSPIN_POS);
-	SET_BIT(RTC->CON, RTC_CON_TSEN_MSK);
-
-	RTC_LOCK();
-	return;
-}
-
-/**
-  * @brief  Cancel time stamp.
-  * @retval None
-  */
-void rtc_cancel_time_stamp(void)
-{
-	RTC_UNLOCK();
-	CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK);
-	RTC_LOCK();
-
-	return;
-}
-
-/**
-  * @brief  Get time stamp value.
-  * @param  ts_time: pointer to rtc_time_t structure.
-  * @param  ts_date: pointer to rtc_date_t structure.
-  * @param  format: Data format.
-  * @retval None
-  */
-void rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format)
-{
-	uint32_t tmp0, tmp1;
-
-	assert_param(ts_time != NULL);
-	assert_param(ts_date != NULL);
-	assert_param(IS_RTC_FORMAT(format));
-
-	ts_time->sub_sec = RTC->TSSSEC & 0xFFFF;
-	tmp0 = RTC->TSTIME;
-	tmp1 = RTC->TSDATE;
-
-	if (format == RTC_FORMAT_DEC) {
-		ts_time->second = bcd_to_dec(tmp0 & 0x7F);
-		ts_time->minute = bcd_to_dec((tmp0 >> 8) & 0x7F);
-		ts_time->hour   = bcd_to_dec((tmp0 >> 16) & 0x3F);
-		ts_date->day    = bcd_to_dec(tmp1 & 0x3F);
-		ts_date->month  = bcd_to_dec((tmp1 >> 8) & 0x1F);
-		ts_date->year   = bcd_to_dec((tmp1 >> 16) & 0xFF);
-		ts_date->week   = bcd_to_dec((tmp1 >> 24) & 0x7);
-	}
-	else {
-		ts_time->second = tmp0 & 0x7F;
-		ts_time->minute = (tmp0 >> 8) & 0x7F;
-		ts_time->hour   = (tmp0 >> 16) & 0x3F;
-		ts_date->day    = tmp1 & 0x3F;
-		ts_date->month  = (tmp1 >> 8) & 0x1F;
-		ts_date->year   = (tmp1 >> 16) & 0xFF;
-		ts_date->week   = (tmp1 >> 24) & 0x7;
-	}
-
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Public_Functions_Group5 Tamper functions
-  * @brief    RTC tamper functions
-  *
-  * @verbatim
- ===============================================================================
-                 ##### Tamper functions #####
- ===============================================================================
-
- [..] This section provides functions allowing:
-     [#]
-       (+) To configure the tamper use rtc_set_tamper() function
-       (+) To cancel the tamper use rtc_alarm_cmd() function
-
-    @endverbatim
-  * @{
-  */
-/**
-  * @brief  Set tamper parameters.
-  * @param  tamper: pointer to rtc_tamper_t structure.
-  * @retval None
-  */
-void rtc_set_tamper(rtc_tamper_t *tamper)
-{
-	assert_param(IS_RTC_TAMPER(tamper->idx));
-	assert_param(IS_RTC_TAMPER_TRIGGER(tamper->trig));
-	assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(tamper->freq));
-	assert_param(IS_RTC_TAMPER_DURATION(tamper->dur));
-	assert_param(IS_FUNC_STATE(tamper->ts));
-
-	RTC_UNLOCK();
-	MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPTS_MSK, tamper->ts << RTC_TAMPCON_TAMPTS_POS);
-	MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPCKS_MSK, tamper->freq << RTC_TAMPCON_TAMPCKS_POSS);
-	MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPFLT_MSK, tamper->dur << RTC_TAMPCON_TAMPFLT_POSS);
-
-	if (tamper->idx == RTC_TAMPER_0) {
-		MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP1LV_MSK, tamper->trig << RTC_TAMPCON_TAMP1LV_POS);
-		SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK);
-	}
-	else {
-		MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP2LV_MSK, tamper->trig << RTC_TAMPCON_TAMP2LV_POS);
-		SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK);
-	}
-
-	RTC_LOCK();
-	return;
-}
-
-/**
-  * @brief  Cancel tamper.
-  * @param  idx: index of tamper:
-  *           @arg RTC_TAMPER_0
-  *           @arg RTC_TAMPER_1
-  * @retval None
-  */
-void rtc_cancel_tamper(rtc_tamper_idx_t idx)
-{
-	assert_param(IS_RTC_TAMPER(idx));
-
-	RTC_UNLOCK();
-
-	if (idx == RTC_TAMPER_0)
-		CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK);
-	else
-		CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK);
-
-	RTC_LOCK();
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Public_Functions_Group6 Wake-up functions
-  * @brief    RTC wake-up functions
-  *
-  * @verbatim
- ===============================================================================
-                 ##### Wake-up functions #####
- ===============================================================================
-
- [..] This section provides functions allowing:
-     [#]
-       (+) To configure the wake-up parameters use rtc_set_wakeup() function
-       (+) To read the re-load register value use rtc_get_wakeup_timer_value() function
-       (+) To cancel the wake-up use rtc_cancel_wakeup() function
-
-    @endverbatim
-  * @{
-  */
-/**
-  * @brief  Set wake-up parameters.
-  * @param  clock: pointer to rtc_wakeup_clock_t structure.
-  * @param  value: re-load value.
-  * @retval None
-  */
-void rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value)
-{
-	assert_param(IS_RTC_WAKEUP_CLOCK(clock));
-
-	RTC_UNLOCK();
-	MODIFY_REG(RTC->CON, RTC_CON_WUCKS_MSK, clock << RTC_CON_WUCKS_POSS);
-	WRITE_REG(RTC->WUMAT, value & 0xFFFF);
-	SET_BIT(RTC->CON, RTC_CON_WUTE_MSK);
-	RTC_LOCK();
-
-	return;
-}
-
-/**
-  * @brief  Cancel wake-up.
-  * @retval None
-  */
-void rtc_cancel_wakeup(void)
-{
-	RTC_UNLOCK();
-	CLEAR_BIT(RTC->CON, RTC_CON_WUTE_MSK);
-	RTC_LOCK();
-
-	return;
-}
-
-/**
-  * @brief  Get wake-up re-load register value.
-  * @retval Value of re-load register.
-  */
-uint16_t rtc_get_wakeup_timer_value(void)
-{
-	return RTC->WUMAT & 0xFFFF;
-}
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Public_Functions_Group7 Clock output functions
-  * @brief    RTC clock output functions
-  *
-  * @verbatim
- ===============================================================================
-                 ##### Clock output functions #####
- ===============================================================================
-
- [..] This section provides functions allowing:
-     [#]
-       (+) To configure the clock output type use rtc_set_clock_output() function
-       (+) To cancel the clock output use rtc_cancel_clock_output() function
-
-    @endverbatim
-  * @{
-  */
-/**
-  * @brief  Set clock output parameters.
-  * @param  clock: pointer to rtc_clock_output_t structure.
-  * @retval ALD status.
-  */
-ald_status_t rtc_set_clock_output(rtc_clock_output_t clock)
-{
-	uint32_t cnt = 4000;
-	assert_param(IS_RTC_CLOCK_OUTPUT(clock));
-
-	SYSCFG_UNLOCK();
-
-	if (clock == RTC_CLOCK_OUTPUT_EXA_1) {
-		SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK);
-		while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2LCKN_MSK)) && (--cnt));
-		cnt = 4000;
-		while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL2RDY_MSK))) && (--cnt));
-	}
-	else {
-		CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK);
-	}
-
-	SYSCFG_LOCK();
-	RTC_UNLOCK();
-	MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, clock << RTC_CON_CKOS_POSS);
-	SET_BIT(RTC->CON, RTC_CON_CKOE_MSK);
-	RTC_LOCK();
-
-	return OK;
-}
-
-/**
-  * @brief  Cancel clock output.
-  * @retval None
-  */
-void rtc_cancel_clock_output(void)
-{
-	RTC_UNLOCK();
-	CLEAR_BIT(RTC->CON, RTC_CON_CKOE_MSK);
-	RTC_LOCK();
-
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Public_Functions_Group8 Control functions
-  * @brief    RTC control functions
-  *
-  * @verbatim
- ===============================================================================
-                 ##### Control functions #####
- ===============================================================================
-
- [..] This section provides functions allowing:
-     [#]
-       (+) Configure interrupt enable/disable.
-       (+) Enable/disable alarm.
-       (+) Configure rtc shift.
-       (+) Calibrate time.
-       (+) Get interrupt source status.
-       (+) Get interrupt flag status.
-       (+) Clear interrupt flag.
-
-    @endverbatim
-  * @{
-  */
-/**
-  * @brief  Enable/disable the specified RTC interrupts.
-  * @param  it: Specifies the RTC interrupt sources to be enabled or disabled.
-  *         This parameter can be one of the @ref rtc_it_t.
-  * @param  state: New state of the specified RTC interrupts.
-  *         This parameter can be:
-  *           @arg ENABLE
-  *           @arg DISABLE
-  * @retval None
-  */
-void rtc_interrupt_config(rtc_it_t it, type_func_t state)
-{
-	assert_param(IS_RTC_IT(it));
-	assert_param(IS_FUNC_STATE(state));
-
-	RTC_UNLOCK();
-
-	if (state == ENABLE)
-		SET_BIT(RTC->IER, it);
-	else
-		CLEAR_BIT(RTC->IER, it);
-
-	RTC_LOCK();
-	return;
-}
-
-/**
-  * @brief  Enable/Disable alarm.
-  * @param  idx: index of alarm:
-  *           @arg RTC_ALARM_A
-  *           @arg RTC_ALARM_B
-  * @param  state: New status of the specified alarm:
-  *           @arg ENABLE
-  *           @arg DISABLE
-  * @retval None
-  */
-void rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state)
-{
-	assert_param(IS_RTC_ALARM(idx));
-	assert_param(IS_FUNC_STATE(state));
-
-	RTC_UNLOCK();
-
-	if (idx == RTC_ALARM_A)
-		MODIFY_REG(RTC->CON, RTC_CON_ALMAEN_MSK, state << RTC_CON_ALMAEN_POS);
-	else
-		MODIFY_REG(RTC->CON, RTC_CON_ALMBEN_MSK, state << RTC_CON_ALMBEN_POS);
-
-	RTC_LOCK();
-	return;
-}
-
-/**
-  * @brief  Set shift parameters.
-  * @param  add_1s: Enable/Disable added 1 second.
-  * @param  sub_ss: value of sub-sconde.
-  * @retval ALD status.
-  */
-ald_status_t rtc_set_shift(type_func_t add_1s, uint16_t sub_ss)
-{
-	uint32_t tick;
-
-	assert_param(IS_FUNC_STATE(add_1s));
-	assert_param(IS_SHIFT_SUB_SS(sub_ss));
-
-	RTC_UNLOCK();
-	MODIFY_REG(RTC->SSECTR, RTC_SSECTR_TRIM_MSK, sub_ss << RTC_SSECTR_TRIM_POSS);
-	MODIFY_REG(RTC->SSECTR, RTC_SSECTR_INC_MSK, add_1s << RTC_SSECTR_INC_POS);
-	RTC_LOCK();
-
-	tick = __get_tick();
-
-	while (READ_BIT(RTC->CON, RTC_CON_SSEC_MSK)) {
-		if ((__get_tick() - tick) > RTC_TIMEOUT_VALUE)
-			return TIMEOUT;
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  Set calibation
-  * @param  config: pointer to rtc_cali_t structure.
-  * @retval None
-  */
-void rtc_set_cali(rtc_cali_t *config)
-{
-	assert_param(IS_RTC_CALI_FREQ(config->cali_freq));
-	assert_param(IS_RTC_CALI_TC(config->tc));
-	assert_param(IS_RTC_CALC_FREQ(config->calc_freq));
-	assert_param(IS_RTC_CALI_CALC(config->calc));
-	assert_param(IS_FUNC_STATE(config->acc));
-
-	RTC_UNLOCK();
-	RTC_CALI_UNLOCK();
-
-	MODIFY_REG(RTC->CALCON, RTC_CALCON_CALP_MSK, config->cali_freq << RTC_CALCON_CALP_POSS);
-	MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, config->tc << RTC_CALCON_TCM_POSS);
-	MODIFY_REG(RTC->CALCON, RTC_CALCON_TCP_MSK, config->calc_freq << RTC_CALCON_TCP_POSS);
-	MODIFY_REG(RTC->CALCON, RTC_CALCON_ALG_MSK, config->calc << RTC_CALCON_ALG_POS);
-	MODIFY_REG(RTC->CALCON, RTC_CALCON_DCMACC_MSK, config->acc << RTC_CALCON_DCMACC_POS);
-	SET_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK);
-
-	RTC_CALI_LOCK();
-	RTC_LOCK();
-
-	return;
-}
-
-/**
-  * @brief  Cancel calibration
-  * @retval None
-  */
-void rtc_cancel_cali(void)
-{
-	RTC_CALI_UNLOCK();
-	CLEAR_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK);
-	RTC_CALI_LOCK();
-
-	return;
-}
-
-/**
-  * @brief  Get calibration status.
-  * @retval ALD status.
-  */
-ald_status_t rtc_get_cali_status(void)
-{
-	if (READ_BIT(RTC->CALCON, RTC_CALCON_ERR_MSK))
-		return ERROR;
-	else
-		return OK;
-}
-
-/**
-  * @brief  Write temperature value.
-  * @param  temp: the value of temperature.
-  * @retval None
-  */
-void rtc_write_temp(uint16_t temp)
-{
-	RTC_CALI_UNLOCK();
-	MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, temp << RTC_TEMPR_VAL_POSS);
-	RTC_CALI_LOCK();
-
-	return;
-}
-
-/**
-  * @brief  Get the status of RTC interrupt source.
-  * @param  it: Specifies the RTC interrupt source.
-  *         This parameter can be one of the @ref rtc_it_t.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-it_status_t rtc_get_it_status(rtc_it_t it)
-{
-	assert_param(IS_RTC_IT(it));
-
-	if (READ_BIT(RTC->IER, it))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Get the status of RTC interrupt flag.
-  * @param  flag: Specifies the RTC interrupt flag.
-  *         This parameter can be one of the @ref rtc_flag_t.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-flag_status_t rtc_get_flag_status(rtc_flag_t flag)
-{
-	assert_param(IS_RTC_IF(flag));
-
-	if (READ_BIT(RTC->IFR, flag))
-		return SET;
-
-	return RESET;
-}
-
-/** @brief  Clear the specified RTC pending flag.
-  * @param  flag: specifies the flag to check.
-  * @retval None.
-  */
-void rtc_clear_flag_status(rtc_flag_t flag)
-{
-	assert_param(IS_RTC_IF(flag));
-
-	RTC_UNLOCK();
-	WRITE_REG(RTC->IFCR, flag);
-	RTC_LOCK();
-
-	return;
-}
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#endif /* ALD_RTC */
-/**
-  * @}
-  */
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_spi.c

@@ -1,1740 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_spi.c
-  * @brief   SPI module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of SPI peripheral:
-  *           + Initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  * @version V1.0
-  * @date    13 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The SPI driver can be used as follows:
-
-      (#) Declare a spi_handle_t structure, for example:
-          spi_handle_t hperh;
-
-      (#) Initialize the SPI low level resources:
-          (##) Enable the SPIx interface clock
-          (##) SPI pins configuration
-              (+++) Enable the clock for the SPI GPIOs
-              (+++) Configure these SPI pins as push-pull
-          (##) NVIC configuration if you need to use interrupt process
-               by implementing the mcu_irq_config() API.
-	       Invoked spi_irq_handle() function in SPI-IRQ function
-          (##) DMA Configuration if you need to use DMA process
-              (+++) Define ALD_DMA in ald_conf.h
- 	      (+++) Enable the DMAx clock
-
-      (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
-          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
-
-      (#) Initialize the SPI module by invoking the spi_init() API.
-
-     [..]
-       Circular mode restriction:
-      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
-          (##) Master 2Lines RxOnly
-          (##) Master 1Line Rx
-      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
-          the spi_dma_pause()/ spi_dma_stop().
-
-  * @endverbatim
-  */
-
-#include "ald_spi.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup SPI SPI
-  * @brief SPI module driver
-  * @{
-  */
-#ifdef ALD_SPI
-
-/** @addtogroup SPI_Private_Functions   SPI Private Functions
-  * @{
-  */
-static ald_status_t spi_wait_flag(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout);
-static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout);
-static void __spi_send_by_it(spi_handle_t *hperh);
-static void __spi_recv_by_it(spi_handle_t *hperh);
-static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status);
-#ifdef ALD_DMA
-static void spi_dma_send_cplt(void *arg);
-static void spi_dma_recv_cplt(void *arg);
-static void spi_dma_send_recv_cplt(void *arg);
-static void spi_dma_error(void *arg);
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Public_Functions SPI Public Functions
-  * @{
-  */
-
-/** @defgroup SPI_Public_Functions_Group1 Initialization functions
-  * @brief Initialization and Configuration functions
-  *
-  * @verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          reset the SPIx peripheral:
-
-      (+) User must configure all related peripherals resources
-          (CLOCK, GPIO, DMA, NVIC).
-
-      (+) Call the function spi_init() to configure the selected device with
-          the selected configuration:
-        (++) Mode
-        (++) Direction
-        (++) Data Size
-        (++) Clock Polarity and Phase
-        (++) NSS Management
-        (++) BaudRate Prescaler
-        (++) FirstBit
-        (++) TIMode
-        (++) CRC Calculation
-        (++) CRC Polynomial if CRC enabled
-
-      (+) Call the function spi_reset() to reset the selected SPIx periperal.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reset the SPI peripheral.
-  * @param  hperh: Pointer to a spi_handle_t structure that contains
-  *         the configuration information for the specified SPI module.
-  * @retval None
-  */
-void spi_reset(spi_handle_t *hperh)
-{
-	hperh->perh->CON1    = 0x0;
-	hperh->perh->CON2    = 0x0;
-	hperh->perh->CRCPOLY = 0x00000007;
-
-	SPI_RESET_HANDLE_STATE(hperh);
-	__UNLOCK(hperh);
-
-	return;
-}
-
-/**
-  * @brief  Initializes the SPI mode according to the specified parameters in
-  *         the SPI_init_t and create the associated handle.
-  * @param  hperh: Pointer to a spi_handle_t structure that contains
-  *         the configuration information for the specified SPI module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t spi_init(spi_handle_t *hperh)
-{
-	uint32_t tmp = 0;
-
-	assert_param(IS_SPI(hperh->perh));
-	assert_param(IS_SPI_MODE(hperh->init.mode));
-	assert_param(IS_SPI_DIRECTION(hperh->init.dir));
-	assert_param(IS_SPI_BAUD(hperh->init.baud));
-	assert_param(IS_FUNC_STATE(hperh->init.first_bit));
-	assert_param(IS_FUNC_STATE(hperh->init.ss_en));
-	assert_param(IS_FUNC_STATE(hperh->init.crc_calc));
-	assert_param(IS_SPI_DATASIZE(hperh->init.data_size));
-	assert_param(IS_SPI_CPHA(hperh->init.phase));
-	assert_param(IS_SPI_CPOL(hperh->init.polarity));
-
-	if (hperh == NULL)
-		return ERROR;
-
-	spi_reset(hperh);
-
-	tmp = hperh->perh->CON1;
-
-	if (hperh->init.mode == SPI_MODE_MASTER)
-		tmp |= 1 << SPI_CON1_SSOUT_POS;
-
-	tmp |= ((hperh->init.phase << SPI_CON1_CPHA_POS) | (hperh->init.polarity << SPI_CON1_CPOL_POS) |
-	        (hperh->init.baud << SPI_CON1_BAUD_POSS) | (hperh->init.data_size << SPI_CON1_FLEN_POS) |
-		(hperh->init.mode << SPI_CON1_MSTREN_POS) | (hperh->init.ss_en << SPI_CON1_SSEN_POS) |
-		(hperh->init.first_bit << SPI_CON1_LSBFST_POS));
-
-	hperh->perh->CON1 = tmp;
-
-	if (hperh->init.dir == SPI_DIRECTION_2LINES) {
-		CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK);
-		CLEAR_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK);
-	}
-	else if (hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) {
-		CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK);
-		SET_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK);
-	}
-	else {
-		SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK);
-	}
-
-	/* configure CRC */
-	hperh->perh->CON1   |= (hperh->init.crc_calc << SPI_CON1_CRCEN_POS);
-	hperh->perh->CRCPOLY = hperh->init.crc_poly;
-
-	hperh->err_code = SPI_ERROR_NONE;
-	hperh->state    = SPI_STATE_READY;
-
-	if (hperh->init.dir == SPI_DIRECTION_2LINES)
-		SPI_ENABLE(hperh);
-
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Public_Functions_Group2 IO operation functions
-  * @brief SPI Transmit and Receive functions
-  *
-  * @verbatim
-  ==============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    This subsection provides a set of functions allowing to manage the SPI
-    data transfers.
-
-    [..] The SPI supports master or slave mode:
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode.
-            The ALD status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) No-Blocking mode: The communication is performed using Interrupts
-            or DMA, These APIs return the ALD status.
-            The end of the data processing will be indicated through the
-            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-            The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() and hperh->tx_rx_cplt_cbk() user callbacks
-            will be executed respectivelly at the end of the transmit or Receive process
-            The hperh->err_cbk() user callback will be executed when a communication error is detected
-
-    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
-        exist for 1Line (simplex) and 2Lines (full duplex) modes.
-
-  * @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  transmit one byte fast in blocking mode.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  data: Data to be sent
-  * @retval status:
-  *           -  0 Success
-  *           - -1 Failed
-  */
-int32_t spi_send_byte_fast(spi_handle_t *hperh, uint8_t data)
-{
-	uint16_t cnt = 2000, temp;
-
-	hperh->perh->DATA = data;
-	while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt));
-
-	while ((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0);
-	temp = hperh->perh->DATA;
-	UNUSED(temp);
-
-	return cnt == 0 ? -1 : 0;
-}
-
-/**
-  * @brief  Receive one byte fast in blocking mode.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @retval Data.
-  */
-uint8_t spi_recv_byte_fast(spi_handle_t *hperh)
-{
-	uint16_t cnt = 2000;
-
-	if (hperh->init.mode == SPI_MODE_MASTER) {
-		hperh->perh->DATA = 0xFF;
-		while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt));
-	}
-
-	cnt = 2000;
-	while (((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0) && (--cnt));
-	return (uint8_t)hperh->perh->DATA;
-}
-
-/**
-  * @brief  transmit an amount of data in blocking mode.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
-{
-	assert_param(IS_SPI(hperh->perh));
-
-	if (hperh->state != SPI_STATE_READY)
-		return BUSY;
-	if (buf == NULL || size == 0)
-		return ERROR;
-
-	__LOCK(hperh);
-
-	hperh->state    = SPI_STATE_BUSY_TX;
-	hperh->err_code = SPI_ERROR_NONE;
-
-	hperh->tx_buf   = buf;
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-	hperh->rx_buf   = NULL;
-	hperh->rx_size  = 0;
-	hperh->rx_count = 0;
-
-	if (hperh->init.crc_calc)
-		SPI_CRC_RESET(hperh);
-	if (hperh->init.dir == SPI_DIRECTION_1LINE)
-		SPI_1LINE_TX(hperh);
-	if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0)
-		SPI_ENABLE(hperh);
-
-	if ((hperh->init.mode == SPI_MODE_SLAVER) || (hperh->tx_count == 1)) {
-		if (hperh->init.data_size == SPI_DATA_SIZE_8) {
-			hperh->perh->DATA = *hperh->tx_buf;
-			++hperh->tx_buf;
-			--hperh->tx_count;
-		}
-		else {
-			hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf);
-			hperh->tx_buf += 2;
-			--hperh->tx_count;
-		}
-	}
-
-	while (hperh->tx_count > 0) {
-		if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) {
-			if (hperh->init.crc_calc)
-				SPI_CRC_RESET(hperh);
-
-			hperh->state = SPI_STATE_READY;
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-
-		if (hperh->init.data_size == SPI_DATA_SIZE_8) {
-			hperh->perh->DATA = *hperh->tx_buf;
-			++hperh->tx_buf;
-			--hperh->tx_count;
-		}
-		else {
-			hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf);
-			hperh->tx_buf += 2;
-			--hperh->tx_count;
-		}
-	}
-
-	if (hperh->init.crc_calc)
-		SPI_CRCNEXT_ENABLE(hperh);
-
- 	if ((spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK)
-			|| (spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK)) {
- 		if (hperh->init.crc_calc)
- 			SPI_CRC_RESET(hperh);
-
- 		hperh->state = SPI_STATE_READY;
- 		__UNLOCK(hperh);
- 		return TIMEOUT;
- 	}
-
-	if (hperh->init.dir == SPI_DIRECTION_2LINES)
-		spi_clear_flag_status(hperh, SPI_IF_OVE);
-
-	hperh->state = SPI_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Receive an amount of data in blocking mode.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be received
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
-{
-	uint16_t temp;
-	assert_param(IS_SPI(hperh->perh));
-
-	if (hperh->state != SPI_STATE_READY)
-		return BUSY;
-	if (buf == NULL || size == 0)
-		return ERROR;
-
-	__LOCK(hperh);
-	hperh->state    = SPI_STATE_BUSY_RX;
-	hperh->err_code = SPI_ERROR_NONE;
-
-	hperh->rx_buf   = buf;
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-	hperh->tx_buf   = NULL;
-	hperh->tx_size  = 0;
-	hperh->tx_count = 0;
-
-	if (hperh->init.crc_calc)
-		SPI_CRC_RESET(hperh);
-	if (hperh->init.dir == SPI_DIRECTION_1LINE_RX)
-		SPI_1LINE_RX(hperh);
-
-	if ((hperh->init.mode == SPI_MODE_MASTER) && (hperh->init.dir == SPI_DIRECTION_2LINES)) {
-		__UNLOCK(hperh);
-		hperh->state = SPI_STATE_READY;
-		return spi_send_recv(hperh, buf, buf, size, timeout);
-	}
-
-	if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX))
-		SPI_ENABLE(hperh);
-
-	while (hperh->rx_count > 1) {
-		if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) {
-			if (hperh->init.crc_calc)
-				SPI_CRC_RESET(hperh);
-
-			hperh->state = SPI_STATE_READY;
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-
-		if (hperh->init.data_size == SPI_DATA_SIZE_8) {
-			*hperh->rx_buf = hperh->perh->DATA;
-			++hperh->rx_buf;
-			--hperh->rx_count;
-		}
-		else {
-			*(uint16_t *)hperh->rx_buf = hperh->perh->DATA;
-			hperh->rx_buf += 2;
-			--hperh->rx_count;
-		}
-	}
-
-	if (hperh->init.crc_calc)
-		SPI_CRCNEXT_ENABLE(hperh);
-
-	if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) {
-		if (hperh->init.crc_calc)
-			SPI_CRC_RESET(hperh);
-
-		hperh->state = SPI_STATE_READY;
-		__UNLOCK(hperh);
-		return TIMEOUT;
-	}
-
-	if (hperh->init.data_size == SPI_DATA_SIZE_8) {
-		*hperh->rx_buf = hperh->perh->DATA;
-		++hperh->rx_buf;
-		--hperh->rx_count;
-	}
-	else {
-		*(uint16_t *)hperh->rx_buf = hperh->perh->DATA;
-		hperh->rx_buf += 2;
-		--hperh->rx_count;
-	}
-
-	if (hperh->init.crc_calc) {
-		if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) {
-			if (hperh->init.crc_calc)
-				SPI_CRC_RESET(hperh);
-
-			hperh->state = SPI_STATE_READY;
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-
-		temp = hperh->perh->DATA;
-		UNUSED(temp);
-	}
-
-	if ((hperh->init.crc_calc) && (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) {
-		hperh->err_code |= SPI_ERROR_CRC;
-		SPI_CRC_RESET(hperh);
-		spi_clear_flag_status(hperh, SPI_IF_CRCERR);
-		hperh->state = SPI_STATE_READY;
-		__UNLOCK(hperh);
-		return ERROR;
-	}
-
-	hperh->state = SPI_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  tx_buf: Pointer to data transmitted buffer
-  * @param  rx_buf: Pointer to data received buffer
-  * @param  size: Amount of data to be sent
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout)
-{
-	uint16_t temp;
-
-	assert_param(IS_SPI(hperh->perh));
-
-	if (hperh->state != SPI_STATE_READY)
-		return BUSY;
-	if (hperh->init.dir != SPI_DIRECTION_2LINES)
-		return ERROR;
-	if (tx_buf == NULL || rx_buf == NULL || size == 0)
-		return ERROR;
-
-	__LOCK(hperh);
-	hperh->state    = SPI_STATE_BUSY_TX_RX;
-	hperh->err_code = SPI_ERROR_NONE;
-
-	hperh->tx_buf   = tx_buf;
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-	hperh->rx_buf   = rx_buf;
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-
-	if (hperh->init.crc_calc)
-		SPI_CRC_RESET(hperh);
-
-	if ((hperh->init.mode == SPI_MODE_SLAVER) || ((hperh->init.mode == SPI_MODE_SLAVER) && (hperh->tx_size == 1))) {
-		if (hperh->init.data_size == SPI_DATA_SIZE_8) {
-			hperh->perh->DATA = *hperh->tx_buf;
-			++hperh->tx_buf;
-			--hperh->tx_count;
-		}
-		else {
-			hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf);
-			hperh->tx_buf += 2;
-			--hperh->tx_count;
-		}
-	}
-
-	if (hperh->tx_buf == 0) {
-		if (hperh->init.crc_calc)
-			SPI_CRCNEXT_ENABLE(hperh);
-
-		if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) {
-			if (hperh->init.crc_calc)
-				SPI_CRC_RESET(hperh);
-
-			hperh->state = SPI_STATE_READY;
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-
-		if (hperh->init.data_size == SPI_DATA_SIZE_8) {
-			*hperh->rx_buf = hperh->perh->DATA;
-			++hperh->rx_buf;
-			--hperh->rx_count;
-		}
-		else {
-			(*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA;
-			hperh->rx_buf += 2;
-			--hperh->rx_count;
-		}
-	}
-
-	while (hperh->tx_count > 0) {
-		if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) {
-			if (hperh->init.crc_calc)
-				SPI_CRC_RESET(hperh);
-
-			hperh->state = SPI_STATE_READY;
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-
-		if (hperh->init.data_size == SPI_DATA_SIZE_8) {
-			hperh->perh->DATA = *hperh->tx_buf;
-			++hperh->tx_buf;
-			--hperh->tx_count;
-		}
-		else {
-			hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf);
-			hperh->tx_buf += 2;
-			--hperh->tx_count;
-		}
-
-		if ((hperh->tx_count == 0) && (hperh->init.crc_calc))
-			SPI_CRCNEXT_ENABLE(hperh);
-
-		if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) {
-			if (hperh->init.crc_calc)
-				SPI_CRC_RESET(hperh);
-
-			hperh->state = SPI_STATE_READY;
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-
-		if (hperh->init.data_size == SPI_DATA_SIZE_8) {
-			*hperh->rx_buf = hperh->perh->DATA;
-			++hperh->rx_buf;
-			--hperh->rx_count;
-		}
-		else {
-			(*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA;
-
-			hperh->rx_buf += 2;
-			--hperh->rx_count;
-		}
-	}
-
-	if (hperh->init.mode == SPI_MODE_SLAVER) {
-		if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) {
-			if (hperh->init.crc_calc)
-			SPI_CRC_RESET(hperh);
-
-			hperh->state = SPI_STATE_READY;
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-
-		if (hperh->init.data_size == SPI_DATA_SIZE_8) {
-			*hperh->rx_buf = hperh->perh->DATA;
-			++hperh->rx_buf;
-			--hperh->rx_count;
-		}
-		else {
-			(*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA;
-
-			hperh->rx_buf += 2;
-			--hperh->rx_count;
-		}
-	}
-
-	if (hperh->init.crc_calc) {
-		if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) {
-			if (hperh->init.crc_calc)
-				SPI_CRC_RESET(hperh);
-
-			hperh->state = SPI_STATE_READY;
-			__UNLOCK(hperh);
-			return TIMEOUT;
-		}
-
-		temp = hperh->perh->DATA;
-		UNUSED(temp);
-	}
-
-	if ((spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK)) {
-		if (hperh->init.crc_calc)
-			SPI_CRC_RESET(hperh);
-
-		hperh->state = SPI_STATE_READY;
-		__UNLOCK(hperh);
-		return TIMEOUT;
-	}
-
-	if ((hperh->init.crc_calc) && (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) {
-		hperh->err_code |= SPI_ERROR_CRC;
-		SPI_CRC_RESET(hperh);
-		spi_clear_flag_status(hperh, SPI_IF_CRCERR);
-		hperh->state = SPI_STATE_READY;
-		__UNLOCK(hperh);
-
-		return ERROR;
-	}
-
-	hperh->state = SPI_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Wraps up transmission in non blocking mode.
-  * @param  hperh: pointer to a spi_handle_t structure.
-  * @param  buf: Pointer to data transmitted buffer
-  * @param  size: Amount of data to be sent
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size)
-{
-	assert_param(IS_SPI(hperh->perh));
-
-	if (hperh->state != SPI_STATE_READY)
-		return BUSY;
-	if (buf == NULL || size == 0)
-		return ERROR;
-
-	__LOCK(hperh);
-	hperh->state    = SPI_STATE_BUSY_TX;
-	hperh->err_code = SPI_ERROR_NONE;
-
-	hperh->tx_buf   = buf;
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-	hperh->rx_buf   = NULL;
-	hperh->rx_size  = 0;
-	hperh->rx_count = 0;
-	__UNLOCK(hperh);
-
-	if (hperh->init.crc_calc)
-		SPI_CRC_RESET(hperh);
-
-	if (hperh->init.dir == SPI_DIRECTION_1LINE)
-		SPI_1LINE_TX(hperh);
-
-	if (hperh->init.dir == SPI_DIRECTION_2LINES) {
-		spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE);
-	}
-	else {
-		spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE);
-		spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE);
-	}
-
-	if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0)
-		SPI_ENABLE(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  buf: Pointer to data received buffer
-  * @param  size: Amount of data to be sent
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size)
-{
-	assert_param(IS_SPI(hperh->perh));
-
-	if (hperh->state != SPI_STATE_READY)
-		return BUSY;
-	if (buf == NULL || size == 0)
-		return ERROR;
-	if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER))
-		return ERROR;	/* Please call spi_send_recv_by_it() */
-
-	__LOCK(hperh);
-	hperh->state    = SPI_STATE_BUSY_RX;
-	hperh->err_code = SPI_ERROR_NONE;
-
-	hperh->rx_buf   = buf;
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-	hperh->tx_buf   = NULL;
-	hperh->tx_size  = 0;
-	hperh->tx_count = 0;
-	__UNLOCK(hperh);
-
-	if (hperh->init.dir == SPI_DIRECTION_1LINE_RX)
-		SPI_1LINE_RX(hperh);
-
-	if (hperh->init.crc_calc == ENABLE)
-		SPI_CRC_RESET(hperh);
-
-	spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE);
-	spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE);
-
-	if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX))
-		SPI_ENABLE(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Transmit and Receives an amount of data in non blocking mode
-  * @param  hperh: Pointer to a spi_handle_t structure that contains
-  *         the configuration information for the specified SPI module.
-  * @param  tx_buf: Pointer to data transmitted buffer
-  * @param  rx_buf: Pointer to data received buffer
-  * @param  size: Amount of data to be sent
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size)
-{
-	assert_param(IS_SPI(hperh->perh));
-
-	if (hperh->state != SPI_STATE_READY)
-		return BUSY;
-	if (tx_buf == NULL || rx_buf == NULL || size == 0)
-		return ERROR;
-
-	__LOCK(hperh);
-	hperh->state    = SPI_STATE_BUSY_TX_RX;
-	hperh->err_code = SPI_ERROR_NONE;
-
-	hperh->tx_buf   = tx_buf;
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-	hperh->rx_buf   = rx_buf;
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-	__UNLOCK(hperh);
-
-	if (hperh->init.crc_calc)
-		SPI_CRC_RESET(hperh);
-
-	spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE);
-	spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE);
- 	spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE);
-
-	return OK;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  Transmit an amount of data used dma channel
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  channel: DMA channel as SPI transmit
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
-{
-	assert_param(IS_SPI(hperh->perh));
-
-	if (hperh->state != SPI_STATE_READY)
-		return BUSY;
-	if (buf == NULL || size == 0)
-		return ERROR;
-
-	__LOCK(hperh);
-	hperh->state    = SPI_STATE_BUSY_TX;
-	hperh->err_code = SPI_ERROR_NONE;
-
-	hperh->tx_buf   = buf;
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-	hperh->rx_buf   = NULL;
-	hperh->rx_size  = 0;
-	hperh->rx_count = 0;
-
-	if (hperh->init.dir == SPI_DIRECTION_1LINE)
-		SPI_1LINE_TX(hperh);
-	if (hperh->init.crc_calc)
-		SPI_CRC_RESET(hperh);
-
-	if (hperh->hdmatx.perh == NULL)
-		hperh->hdmatx.perh = DMA0;
-
-	hperh->hdmatx.cplt_arg = (void *)hperh;
-	hperh->hdmatx.cplt_cbk = spi_dma_send_cplt;
-	hperh->hdmatx.err_arg  = (void *)hperh;
-	hperh->hdmatx.err_cbk  = spi_dma_error;
-
-	/* Configure SPI DMA transmit */
-	dma_config_struct(&(hperh->hdmatx.config));
-	hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD;
-	hperh->hdmatx.config.src        = (void *)buf;
-	hperh->hdmatx.config.dst        = (void *)&hperh->perh->DATA;
-	hperh->hdmatx.config.size       = size;
-	hperh->hdmatx.config.src_inc    = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;
-	hperh->hdmatx.config.dst_inc    = DMA_DATA_INC_NONE;
-	hperh->hdmatx.config.msel       = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
-	hperh->hdmatx.config.msigsel    = DMA_MSIGSEL_SPI_TXEMPTY;
-	hperh->hdmatx.config.channel    = channel;
-	dma_config_basic(&(hperh->hdmatx));
-
-	__UNLOCK(hperh);
-	spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE);
-
-	if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0)
-		SPI_ENABLE(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Receive an amount of data used dma channel
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  channel: DMA channel as SPI transmit
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
-{
-	assert_param(IS_SPI(hperh->perh));
-
-	if (hperh->state != SPI_STATE_READY)
-		return BUSY;
-	if (buf == NULL || size == 0)
-		return ERROR;
-
-	__LOCK(hperh);
-	hperh->state    = SPI_STATE_BUSY_RX;
-	hperh->err_code = SPI_ERROR_NONE;
-
-	hperh->rx_buf   = buf;
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-	hperh->tx_buf   = NULL;
-	hperh->tx_size  = 0;
-	hperh->tx_count = 0;
-
-	if (hperh->init.dir == SPI_DIRECTION_1LINE_RX)
-		SPI_1LINE_RX(hperh);
-	if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) {
-		__UNLOCK(hperh);
-		return ERROR;	/* Please use spi_send_recv_by_dma() */
-	}
-	if (hperh->init.crc_calc)
-		SPI_CRC_RESET(hperh);
-
-	if (hperh->hdmarx.perh == NULL)
-		hperh->hdmarx.perh = DMA0;
-
-	hperh->hdmarx.cplt_arg = (void *)hperh;
-	hperh->hdmarx.cplt_cbk = spi_dma_recv_cplt;
-	hperh->hdmarx.err_arg  = (void *)hperh;
-	hperh->hdmarx.err_cbk  = spi_dma_error;
-
-	/* Configure DMA Receive */
-	dma_config_struct(&(hperh->hdmarx.config));
-	hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD;
-	hperh->hdmarx.config.src        = (void *)&hperh->perh->DATA;
-	hperh->hdmarx.config.dst        = (void *)buf;
-	hperh->hdmarx.config.size       = size;
-	hperh->hdmarx.config.src_inc    = DMA_DATA_INC_NONE;
-	hperh->hdmarx.config.dst_inc    = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;;
-	hperh->hdmarx.config.msel       = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
-	hperh->hdmarx.config.msigsel    = DMA_MSIGSEL_SPI_RNR;
-	hperh->hdmarx.config.channel    = channel;
-	dma_config_basic(&(hperh->hdmarx));
-
-	__UNLOCK(hperh);
-	spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE);
-
-	if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX))
-		SPI_ENABLE(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data used dma channel
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  tx_buf: Pointer to data buffer
-  * @param  rx_buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  tx_channel: DMA channel as SPI transmit
-  * @param  rx_channel: DMA channel as SPI receive
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel)
-{
-	assert_param(IS_SPI(hperh->perh));
-
-	if (hperh->state != SPI_STATE_READY && hperh->state != SPI_STATE_BUSY_RX)
-		return BUSY;
-	if (tx_buf == NULL || rx_buf == NULL || size == 0)
-		return ERROR;
-
-	__LOCK(hperh);
-	hperh->state    = SPI_STATE_BUSY_RX;
-	hperh->err_code = SPI_ERROR_NONE;
-
-	hperh->tx_buf   = tx_buf;
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-	hperh->rx_buf   = rx_buf;
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-
-	if (hperh->hdmatx.perh == NULL)
-		hperh->hdmatx.perh = DMA0;
-	if (hperh->hdmarx.perh == NULL)
-		hperh->hdmarx.perh = DMA0;
-
-	hperh->hdmatx.cplt_arg = NULL;
-	hperh->hdmatx.cplt_cbk = NULL;
-	hperh->hdmatx.err_arg  = (void *)hperh;
-	hperh->hdmatx.err_cbk  = spi_dma_error;
-	hperh->hdmarx.cplt_arg = (void *)hperh;
-	hperh->hdmarx.cplt_cbk = spi_dma_send_recv_cplt;
-	hperh->hdmarx.err_arg  = (void *)hperh;
-	hperh->hdmarx.err_cbk  = spi_dma_error;
-
-	if (hperh->init.crc_calc)
-		SPI_CRC_RESET(hperh);
-
-	/* Configure SPI DMA transmit */
-	dma_config_struct(&(hperh->hdmatx.config));
-	hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD;
-	hperh->hdmatx.config.src        = (void *)tx_buf;
-	hperh->hdmatx.config.dst        = (void *)&hperh->perh->DATA;
-	hperh->hdmatx.config.size       = size;
-	hperh->hdmatx.config.src_inc    = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;
-	hperh->hdmatx.config.dst_inc    = DMA_DATA_INC_NONE;
-	hperh->hdmatx.config.msel       = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
-	hperh->hdmatx.config.msigsel    = DMA_MSIGSEL_SPI_TXEMPTY;
-	hperh->hdmatx.config.channel    = tx_channel;
-	dma_config_basic(&(hperh->hdmatx));
-
-	/* Configure DMA Receive */
-	dma_config_struct(&(hperh->hdmarx.config));
-	hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD;
-	hperh->hdmarx.config.src        = (void *)&hperh->perh->DATA;
-	hperh->hdmarx.config.dst        = (void *)rx_buf;
-	hperh->hdmarx.config.size       = size;
-	hperh->hdmarx.config.src_inc    = DMA_DATA_INC_NONE;
-	hperh->hdmarx.config.dst_inc    = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;;
-	hperh->hdmarx.config.msel       = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
-	hperh->hdmarx.config.msigsel    = DMA_MSIGSEL_SPI_RNR;
-	hperh->hdmarx.config.channel    = rx_channel;
-	dma_config_basic(&(hperh->hdmarx));
-
-	__UNLOCK(hperh);
-	spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE);
-	spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE);
-
-	return OK;
-}
-
-/**
-  * @brief  Pauses the DMA Transfer.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @retval Status
-  */
-ald_status_t spi_dma_pause(spi_handle_t *hperh)
-{
-	assert_param(IS_SPI(hperh->perh));
-
-	__LOCK(hperh);
-	spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE);
-	spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Resumes the DMA Transfer.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @retval Status
-  */
-ald_status_t spi_dma_resume(spi_handle_t *hperh)
-{
-	assert_param(IS_SPI(hperh->perh));
-
-	__LOCK(hperh);
-	spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE);
-	spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Stops the DMA Transfer.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @retval Status
-  */
-ald_status_t spi_dma_stop(spi_handle_t *hperh)
-{
-	assert_param(IS_SPI(hperh->perh));
-
-	__LOCK(hperh);
-	spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE);
-	spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE);
-	__UNLOCK(hperh);
-
-	hperh->state = SPI_STATE_READY;
-	return OK;
-}
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Public_Functions_Group3 Control functions
-  * @brief SPI Control functions
-  *
-  * @verbatim
-   ===============================================================================
-                      ##### Peripheral Control functions #####
-   ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the SPI.
-     (+) Handle interrupt about SPI module. The spi_irq_handle() function must
-         be invoked by SPI-IRQ function.
-     (+) Configure the interrupt DISABLE/ENABLE.
-     (+) Configure the DMA request.
-     (+) Get interrupt source status.
-     (+) Get interrupt flag status.
-     (+) Clear interrupt flag
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  This function handles SPI interrupt request.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @retval None
-  */
-void spi_irq_handle(spi_handle_t *hperh)
-{
-	if ((hperh->state == SPI_STATE_BUSY_RX) || (hperh->state == SPI_STATE_BUSY_TX)) {
-		if ((spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET))
-			__spi_recv_by_it(hperh);
-
-		if ((spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET))
-			__spi_send_by_it(hperh);
-	}
-
-	else if (hperh->state == SPI_STATE_BUSY_TX_RX) {
-		if (hperh->tx_size == hperh->tx_count) {
-			if ((spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET))
-				__spi_send_recv_by_it(hperh, SPI_SR_TXBE);
-		}
-		else {
-			if ((spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)
-			   && (spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET))
-				__spi_send_recv_by_it(hperh, SPI_SR_TXBE_RXBNE);
-		}
-	}
-
-	if ((spi_get_it_status(hperh, SPI_IT_ERR) != RESET)) {
-		if (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) {
-			hperh->err_code |= SPI_ERROR_CRC;
-			spi_clear_flag_status(hperh, SPI_IF_CRCERR);
-		}
-		if (spi_get_flag_status(hperh, SPI_IF_MODF) != RESET) {
-			hperh->err_code |= SPI_ERROR_MODF;
-			spi_clear_flag_status(hperh, SPI_IF_MODF);
-		}
-		if (spi_get_flag_status(hperh, SPI_IF_OVE) != RESET) {
-			if (hperh->state != SPI_STATE_BUSY_TX) {
-				hperh->err_code |= SPI_ERROR_OVE;
-				spi_clear_flag_status(hperh, SPI_IF_OVE);
-			}
-		}
-
-		if (hperh->err_code != SPI_ERROR_NONE) {
- 			spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE);
- 			spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE);
- 			spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE);
-			hperh->state = SPI_STATE_READY;
-
-			if (hperh->err_cbk)
-				hperh->err_cbk(hperh);
-		}
-	}
-
-	return;
-}
-
-/**
-  * @brief  Enables or disables the specified SPI interrupts.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  it: Specifies the SPI interrupt sources to be enabled or disabled.
-  *         This parameter can be one of the @ref spi_it_t.
-  * @param  state: New status
-  *           - ENABLE
-  *           - DISABLE
-  * @retval None
-  */
-void spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state)
-{
-	assert_param(IS_SPI(hperh->perh));
-	assert_param(IS_SPI_IT(it));
-	assert_param(IS_FUNC_STATE(state));
-
-	if (state == ENABLE)
-		hperh->perh->CON2 |= (uint32_t)it;
-	else
-		hperh->perh->CON2 &= ~((uint32_t)it);
-
-	return;
-}
-
-/**
-  * @brief  Configure the specified SPI speed.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  speed: Specifies the SPI speed.
-  *         This parameter can be one of the @ref spi_baud_t.
-  * @retval None
-  */
-void spi_speed_config(spi_handle_t *hperh, spi_baud_t speed)
-{
-	uint32_t tmp = 0;
-	assert_param(IS_SPI(hperh->perh));
-	assert_param(IS_SPI_BAUD(speed));
-
-	tmp = hperh->perh->CON1;
-	tmp &= ~(0x7 << SPI_CON1_BAUD_POSS);
-	tmp |= (speed << SPI_CON1_BAUD_POSS);
-	hperh->perh->CON1 = tmp;
-	return;
-}
-
-/**
-  * @brief  Enables or disables the dma request.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  req: Specifies the SPI dma request sources to be enabled or disabled.
-  *         This parameter can be one of the @ref spi_dma_req_t.
-  * @param  state: New status
-  *           - ENABLE
-  *           - DISABLE
-  * @retval None
-  */
-void spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state)
-{
-	assert_param(IS_SPI(hperh->perh));
-	assert_param(IS_SPI_DMA_REQ(req));
-	assert_param(IS_FUNC_STATE(state));
-
-	if (state == ENABLE) {
-		if (req == SPI_DMA_REQ_TX)
-			SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK);
-		else
-			SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK);
-	}
-	else {
-		if (req == SPI_DMA_REQ_TX)
-			CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK);
-		else
-			CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK);
-	}
-
-	return;
-}
-
-/**
-  * @brief  Checks whether the specified SPI interrupt has occurred or not.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  it: Specifies the SPI interrupt source to check.
-  *         This parameter can be one of the @ref spi_it_t.
-  * @retval Status
-  *           - SET
-  *           - RESET
-  */
-it_status_t spi_get_it_status(spi_handle_t *hperh, spi_it_t it)
-{
-	assert_param(IS_SPI(hperh->perh));
-	assert_param(IS_SPI_IT(it));
-
-	if (hperh->perh->CON2 & it)
-		return SET;
-
-	return RESET;
-}
-
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  flag: specifies the flag to check.
-  *         This parameter can be one of the @ref spi_flag_t.
-  * @retval Status
-  *           - SET
-  *           - RESET
-  */
-flag_status_t spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag)
-{
-	assert_param(IS_SPI(hperh->perh));
-	assert_param(IS_SPI_IF(flag));
-
-	if (hperh->perh->STAT & flag)
-		return SET;
-
-	return RESET;
-}
-
-/** @brief  Clear the specified SPI pending flags.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  flag: specifies the flag to check.
-  *         This parameter can be one of the @ref spi_flag_t.
-  * @retval None
-  */
-void spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag)
-{
-	uint32_t temp;
-
-	assert_param(IS_SPI(hperh->perh));
-	assert_param(IS_SPI_IF(flag));
-
-	if (flag == SPI_IF_CRCERR) {
-		SET_BIT(hperh->perh->STAT, SPI_STAT_CRCERR_MSK);
-		return;
-	}
-	if (flag == SPI_IF_OVE) {
-		temp = hperh->perh->DATA;
-		temp = hperh->perh->STAT;
-		UNUSED(temp);
-		return;
-	}
-	if (flag == SPI_IF_MODF) {
-		temp = hperh->perh->STAT;
-		UNUSED(temp);
-		hperh->perh->CON1 = hperh->perh->CON1;
-		return;
-	}
-
-	return;
-}
-
-/**
-  * @brief  This function handles SPI communication timeout.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  flag: specifies the SPI flag to check.
-  * @param  status: The new Flag status (SET or RESET).
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t spi_wait_flag(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout)
-{
-	uint32_t tick = __get_tick();
-
-	assert_param(timeout > 0);
-
-	while ((spi_get_flag_status(hperh, flag)) != status) {
-		if (((__get_tick()) - tick) > timeout) {
-			spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE);
-			spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE);
-			spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE);
-			return TIMEOUT;
-		}
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  This function handles SPI communication timeout in interrupt function.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  flag: specifies the SPI flag to check.
-  * @param  status: The new Flag status (SET or RESET).
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout)
-{
-	assert_param(timeout > 0);
-
-	while (((spi_get_flag_status(hperh, flag)) != status) && (--timeout));
-
-	if (timeout)
-		return OK;
-
-	spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE);
-	spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE);
-	spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE);
-
-	return TIMEOUT;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Public_Functions_Group4 Peripheral State and Errors functions
-  *  @brief   SPI State and Errors functions
-  *
-  * @verbatim
- ===============================================================================
-                      ##### Peripheral State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the SPI.
-     (+) spi_get_state() API can check in run-time the state of the SPI peripheral
-     (+) spi_get_error() check in run-time Errors occurring during communication
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the SPI state.
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @retval ALD state
-  */
-spi_state_t spi_get_state(spi_handle_t *hperh)
-{
-	assert_param(IS_SPI(hperh->perh));
-	return hperh->state;
-}
-
-/**
-  * @brief  Return the SPI error code
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @retval SPI Error Code
-  */
-uint32_t spi_get_error(spi_handle_t *hperh)
-{
-	assert_param(IS_SPI(hperh->perh));
-	return hperh->err_code;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Private_Functions SPI Private Functions
-  * @brief   SPI Private functions
-  * @{
-  */
-
-/**
-  * @brief  handle program when an tx empty interrupt flag arrived in non block mode
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @retval Status, see @ref ald_status_t.
-  */
-static void __spi_send_by_it(spi_handle_t *hperh)
-{
-	if (hperh->tx_count == 0) {
-		spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE);
-		hperh->state = SPI_STATE_READY;
-
-		if (hperh->init.dir == SPI_DIRECTION_2LINES)
-			spi_clear_flag_status(hperh, SPI_IF_OVE);
-
-		if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) {
-			if (hperh->err_cbk)
-				hperh->err_cbk(hperh);
-
-			return;
-		}
-
-		if (hperh->tx_cplt_cbk)
-			hperh->tx_cplt_cbk(hperh);
-
-		return;
-	}
-
-	if (hperh->init.data_size == SPI_DATA_SIZE_8) {
-		hperh->perh->DATA = *hperh->tx_buf;
-		++hperh->tx_buf;
-	}
-	else {
-		hperh->perh->DATA    = *(uint16_t *)hperh->tx_buf;
-		hperh->tx_buf       += 2;
-	}
-	--hperh->tx_count;
-
-	if (hperh->tx_count == 0) {
-		if (hperh->init.crc_calc)
-			SPI_CRCNEXT_ENABLE(hperh);
-	}
-
-	return;
-}
-
-/**
-  * @brief  handle program when an rx no empty interrupt flag arrived in non block mode
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @retval Status, see @ref ald_status_t.
-  */
-static void __spi_recv_by_it(spi_handle_t *hperh)
-{
-	uint16_t temp;
-	if (hperh->init.data_size == SPI_DATA_SIZE_8) {
-		*hperh->rx_buf = hperh->perh->DATA;
-		++hperh->rx_buf;
-	}
-	else {
-		*(uint16_t *)hperh->rx_buf = hperh->perh->DATA;
-		hperh->rx_buf             += 2;
-	}
-	--hperh->rx_count;
-
-	if ((hperh->rx_count == 1) && (hperh->init.crc_calc))
-		SPI_CRCNEXT_ENABLE(hperh);
-
-	if (hperh->rx_count == 0) {
-		spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE);
-		hperh->state = SPI_STATE_READY;
-
-		if ((hperh->init.crc_calc) && (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) {
-			hperh->err_code |= SPI_ERROR_CRC;
-			spi_clear_flag_status(hperh, SPI_IF_CRCERR);
-
-			if (hperh->err_cbk)
-				hperh->err_cbk(hperh);
-
-			return;
-		}
-
-		if (hperh->init.crc_calc) {
-			temp = hperh->perh->DATA;
-			UNUSED(temp);
-		}
-
-		if (hperh->rx_cplt_cbk)
-			hperh->rx_cplt_cbk(hperh);
-	}
-
-	return;
-}
-
-/**
-  * @brief  handle program when an rx no empty interrupt flag arrived in non block mode(2 lines)
-  * @param  hperh: Pointer to a spi_handle_t structure.
-  * @param  status: SR.TXE or SR.RXNE set.
-  * @retval Status, see @ref ald_status_t.
-  */
-static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status)
-{
-	assert_param(IS_SPI_SR_STATUS(status));
-
-	if (hperh->rx_count != 0) {
-		if ((status == SPI_SR_RXBNE) || (status == SPI_SR_TXBE_RXBNE)) {
-			if (hperh->init.data_size == SPI_DATA_SIZE_8) {
-				*hperh->rx_buf = hperh->perh->DATA;
-				++hperh->rx_buf;
-			}
-			else {
-				*(uint16_t *)hperh->rx_buf = hperh->perh->DATA;
-				hperh->rx_buf += 2;
-			}
-
-			--hperh->rx_count;
-		}
-	}
-
-	if (hperh->tx_count != 0) {
-		if ((status == SPI_SR_TXBE) || (status == SPI_SR_TXBE_RXBNE)) {
-			if (hperh->tx_count == 1) {
-				if (hperh->init.data_size == SPI_DATA_SIZE_8) {
-					hperh->perh->DATA = *hperh->tx_buf;
-					++hperh->tx_buf;
-				}
-				else {
-					hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
-					hperh->tx_buf       += 2;
-				}
-
-				--hperh->tx_count;
-
-				if (hperh->init.crc_calc)
-					SPI_CRCNEXT_ENABLE(hperh);
-			}
-			else {
-				if (hperh->init.data_size == SPI_DATA_SIZE_8) {
-					hperh->perh->DATA = *hperh->tx_buf;
-					++hperh->tx_buf;
-				}
-				else {
-					hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
-					hperh->tx_buf       += 2;
-				}
-
-				if (--hperh->tx_count == 0) {
-					if (hperh->init.crc_calc)
-						SPI_CRCNEXT_ENABLE(hperh);
-					spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE);
-				}
-			}
-		}
-	}
-
-	if (hperh->rx_count == 0) {
-		spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE);
-		spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE);
-		spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE);
-		hperh->state = SPI_STATE_READY;
-
-		if ((hperh->init.crc_calc) && (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) {
-			hperh->err_code |= SPI_ERROR_CRC;
-			spi_clear_flag_status(hperh, SPI_IF_CRCERR);
-
-			if (hperh->err_cbk)
-				hperh->err_cbk(hperh);
-
-			return;
-		}
-
-		if (hperh->tx_rx_cplt_cbk)
-			hperh->tx_rx_cplt_cbk(hperh);
-	}
-
-	return;
-}
-
-
-#ifdef ALD_DMA
-/**
-  * @brief  DMA SPI transmit process complete callback.
-  * @param  arg: Pointer to a spi_handle_t structure.
-  * @retval None
-  */
-static void spi_dma_send_cplt(void *arg)
-{
-	uint16_t delay;
-	spi_handle_t *hperh = (spi_handle_t *)arg;
-
-	hperh->tx_count = 0;
-	spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE);
-	hperh->state = SPI_STATE_READY;
-
-	if (hperh->init.dir == SPI_DIRECTION_2LINES)
-		spi_clear_flag_status(hperh, SPI_IF_OVE);
-
-	if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK)
-		hperh->err_code |= SPI_ERROR_FLAG;
-
-	for (delay = 0; delay < 3000; delay++);
-
-	if (hperh->err_code == SPI_ERROR_NONE) {
-		if (hperh->tx_cplt_cbk)
-			hperh->tx_cplt_cbk(hperh);
-	}
-	else {
-		if (hperh->err_cbk)
-			hperh->err_cbk(hperh);
-	}
-
-	return;
-}
-
-/**
-  * @brief  DMA SPI receive process complete callback.
-  * @param  arg: Pointer to a spi_handle_t structure.
-  * @retval None
-  */
-static void spi_dma_recv_cplt(void *arg)
-{
-	uint32_t tmp;
-	spi_handle_t *hperh = (spi_handle_t *)arg;
-
-	hperh->rx_count = 0;
-	spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE);
-	spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE);
-	hperh->state = SPI_STATE_READY;
-
-	if (hperh->init.crc_calc) {
-		if ((spi_wait_flag_irq(hperh, SPI_IF_RXBNE, SET, 5000)) != OK)
-			hperh->err_code |= SPI_ERROR_FLAG;
-
-		tmp = hperh->perh->DATA;
-		UNUSED(tmp);
-
-		if (spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) {
-			SET_BIT(hperh->err_code, SPI_ERROR_CRC);
-			SPI_CRC_RESET(hperh);
-			spi_clear_flag_status(hperh, SPI_IF_CRCERR);
-		}
-	}
-
-	if (hperh->err_code == SPI_ERROR_NONE) {
-		if (hperh->rx_cplt_cbk)
-			hperh->rx_cplt_cbk(hperh);
-	}
-	else {
-		if (hperh->err_cbk)
-			hperh->err_cbk(hperh);
-	}
-
-	return;
-}
-
-/**
-  * @brief  DMA SPI transmit and receive process complete callback.
-  * @param  arg: Pointer to a SPI_handle_t structure.
-  * @retval None
-  */
-static void spi_dma_send_recv_cplt(void *arg)
-{
-	uint32_t tmp;
-	uint16_t delay;
-	spi_handle_t *hperh = (spi_handle_t *)arg;
-
-	if (hperh->init.crc_calc) {
-		if ((spi_wait_flag_irq(hperh, SPI_IF_RXBNE, SET, 5000)) != OK)
-			hperh->err_code |= SPI_ERROR_FLAG;
-
-		tmp = hperh->perh->DATA;
-		UNUSED(tmp);
-
-		if (spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) {
-			SET_BIT(hperh->err_code, SPI_ERROR_CRC);
-			spi_clear_flag_status(hperh, SPI_IF_CRCERR);
-		}
-	}
-
-	if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK)
-		hperh->err_code |= SPI_ERROR_FLAG;
-
-	for (delay = 0; delay < 3000; delay++);
-
-	spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE);
-	spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE);
-	hperh->tx_count = 0;
-	hperh->rx_count = 0;
-	hperh->state    = SPI_STATE_READY;
-
-	if (hperh->err_code == SPI_ERROR_NONE) {
-		if (hperh->tx_rx_cplt_cbk)
-			hperh->tx_rx_cplt_cbk(hperh);
-	}
-	else {
-		if (hperh->err_cbk)
-			hperh->err_cbk(hperh);
-	}
-
-	return;
-}
-
-/**
-  * @brief  DMA SPI communication error callback.
-  * @param  arg: Pointer to a spi_handle_t structure that contains
-  *         the configuration information for the specified SPI module.
-  * @retval None
-  */
-static void spi_dma_error(void *arg)
-{
-	spi_handle_t *hperh = (spi_handle_t *)arg;
-
-	spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE);
-	spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE);
-	SET_BIT(hperh->err_code, SPI_ERROR_DMA);
-
- 	hperh->tx_count = 0;
- 	hperh->rx_count = 0;
-	hperh->state    = SPI_STATE_READY;
-
-	if (hperh->err_cbk)
-		hperh->err_cbk(hperh);
-
-	return;
-}
-#endif /* ALD_DMA */
-/**
-  * @}
-  */
-#endif /* ALD_SPI */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_temp.c

@@ -1,209 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_temp.c
-  * @brief   TEMP module driver.
-  *
-  * @version V1.0
-  * @date    15 Dec 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#include "ald_temp.h"
-#include "ald_bkpc.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup TEMP TEMP
-  * @brief TEMP module driver
-  * @{
-  */
-#ifdef ALD_TEMP
-
-
-/** @defgroup TEMP_Private_Variables TEMP Private Variables
-  * @{
-  */
-temp_cbk __temp_cbk;
-/**
-  * @}
-  */
-
-/** @defgroup TEMP_Public_Functions TEMP Public Functions
-  * @{
-  */
-
-/** @addtogroup TEMP_Public_Functions_Group1 Initialization functions
-  * @brief Initialization functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### Initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to initialize the TEMP:
-      (+) This parameters can be configured:
-        (++) Update Cycle
-        (++) Output Mode
-        (++) Perscaler
-      (+) Select TEMP source clock(default LOSC)
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the TEMP according to the specified
-  *         parameters in the temp_init_t.
-  * @param  init: Pointer to a temp_init_t structure that contains
-  *         the configuration information.
-  * @retval None
-  */
-void temp_init(temp_init_t *init)
-{
-	assert_param(IS_TEMP_UPDATE_CYCLE(init->cycle));
-	assert_param(IS_TEMP_OUTPUT_MODE(init->mode));
-
-	TEMP_UNLOCK();
-	MODIFY_REG(TEMP->CR, TEMP_CR_TSU_MSK, init->cycle << TEMP_CR_TSU_POSS);
-	MODIFY_REG(TEMP->CR, TEMP_CR_TOM_MSK, init->mode << TEMP_CR_TOM_POSS);
-	MODIFY_REG(TEMP->CR, TEMP_CR_CTN_MSK, init->ctn << TEMP_CR_CTN_POS);
-	MODIFY_REG(TEMP->PSR, TEMP_PSR_PRS_MSK, init->psc << TEMP_PSR_PRS_POSS);
-	TEMP_LOCK();
-
-	return;
-}
-
-/**
-  * @brief  Configure the TEMP source.
-  * @param  sel: TEMP source type.
-  * @retval None
-  */
-void temp_source_selcet(temp_source_sel_t sel)
-{
-	assert_param(IS_TEMP_SOURCE_SEL(sel));
-
-	BKPC_UNLOCK();
-	MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TEMPCS_MSK, sel << BKPC_PCCR_TEMPCS_POSS);
-
-	if (sel == TEMP_SOURCE_LOSC) {
-		SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);
-	}
-	else if (sel == TEMP_SOURCE_LRC) {
-		SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);
-	}
-	else {
-		; /* do nothing */
-	}
-
-	BKPC_LOCK();
-	return;
-}
-/**
-  * @}
-  */
-
-/** @addtogroup TEMP_Public_Functions_Group2 Peripheral Control functions
-  * @brief Peripheral Control functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### Peripheral Control functions #####
-  ==============================================================================
-  [..]  This section provides functions allowing to:
-    (+) temp_get_value() API can get the current temperature.
-    (+) temp_get_value_by_it() API can get the current temperature by interrupt.
-    (+) temp_irq_handle() API can handle the interrupt request.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Get the current temperature
-  * @param  temp: The value of current temperature.
-  * @retval ALD status:
-  *         @arg @ref OK    The value is valid
-  *         @arg @ref ERROR The value is invalid
-  */
-ald_status_t temp_get_value(uint16_t *temp)
-{
-	TEMP_UNLOCK();
-	SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK);
-	SET_BIT(TEMP->CR, TEMP_CR_EN_MSK);
-	TEMP_LOCK();
-
-	while (!(READ_BIT(TEMP->IF, TEMP_IF_TEMP_MSK)));
-
-	TEMP_UNLOCK();
-	SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK);
-	TEMP_LOCK();
-
-	if (READ_BIT(TEMP->DR, TEMP_DR_ERR_MSK))
-		return ERROR;
-
-	*temp = READ_BITS(TEMP->DR, TEMP_DR_DATA_MSK, TEMP_DR_DATA_POSS);
-	return OK;
-}
-
-/**
-  * @brief  Get the current temperature by interrupt
-  * @param  cbk: The callback function
-  * @retval None
-  */
-void temp_get_value_by_it(temp_cbk cbk)
-{
-	__temp_cbk = cbk;
-
-	TEMP_UNLOCK();
-	SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK);
-	SET_BIT(TEMP->IE, TEMP_IE_TEMP_MSK);
-	SET_BIT(TEMP->CR, TEMP_CR_EN_MSK);
-	TEMP_LOCK();
-
-	return;
-}
-
-/**
-  * @brief  This function handles TEMP interrupt request.
-  * @retval None
-  */
-void temp_irq_handle(void)
-{
-	TEMP_UNLOCK();
-	SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK);
-	TEMP_LOCK();
-
-	if (__temp_cbk == NULL)
-		return;
-
-	if (READ_BIT(TEMP->DR, TEMP_DR_ERR_MSK)) {
-		__temp_cbk(0, ERROR);
-		return;
-	}
-
-	__temp_cbk(READ_BITS(TEMP->DR, TEMP_DR_DATA_MSK, TEMP_DR_DATA_POSS), OK);
-
-	return;
-}
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#endif /* ALD_TEMP */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_timer.c

@@ -1,3709 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_timer.c
-  * @brief   TIMER module driver.
-  *	     This is the common part of the TIMER initialization
-  *
-  * @version V1.0
-  * @date    06 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#include <string.h>
-#include "ald_timer.h"
-#include "ald_cmu.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup TIMER TIMER
-  * @brief TIMER module driver
-  * @{
-  */
-#ifdef ALD_TIMER
-
-/** @defgroup TIMER_Private_Functions TIMER Private Functions
-  * @{
-  */
-static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init);
-static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config);
-static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config);
-static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config);
-static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config);
-static void timer_ccx_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state);
-static void timer_ccxn_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state);
-static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity,
-                                   timer_ic_select_t sel, uint32_t filter);
-static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter);
-static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity,
-                                   timer_ic_select_t sel, uint32_t filter);
-static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter);
-static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity,
-                                   timer_ic_select_t sel, uint32_t filter);
-static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity,
-                                   timer_ic_select_t sel, uint32_t filter);
-static void timer_etr_set_config(TIMER_TypeDef* TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter);
-static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config);
-#ifdef ALD_DMA
-static void timer_dma_oc_cplt(void *arg);
-static void timer_dma_capture_cplt(void *arg);
-static void timer_dma_period_elapse_cplt(void *arg);
-static void timer_dma_error(void *arg);
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup  TIMER_Public_Functions TIMER Public Functions
-  * @{
-  */
-
-/** @defgroup TIMER_Public_Functions_Group1 TIMER Base functions
-  * @brief    Time Base functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### Timer Base functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIMER base.
-    (+) Reset the TIMER base.
-    (+) Start the Time Base.
-    (+) Stop the Time Base.
-    (+) Start the Time Base and enable interrupt.
-    (+) Stop the Time Base and disable interrupt.
-    (+) Start the Time Base and enable DMA transfer.
-    (+) Stop the Time Base and disable DMA transfer.
-
-    @endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIMER Time base Unit according to the specified
-  *         parameters in the timer_handle_t and create the associated handle.
-  * @param  hperh: TIMER base handle
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_base_init(timer_handle_t *hperh)
-{
-	if (hperh == NULL)
-		return ERROR;
-
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode));
-	assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div));
-
-	if (hperh->state == TIMER_STATE_RESET)
-		hperh->lock = UNLOCK;
-
-	hperh->state = TIMER_STATE_BUSY;
-	timer_base_set_config(hperh->perh, &hperh->init);
-	hperh->state = TIMER_STATE_READY;
-
-	return OK;
-}
-
-/**
-  * @brief  Reset the TIMER base peripheral
-  * @param  hperh: TIMER base handle
-  * @retval Status, see @ref ald_status_t.
-  */
-void timer_base_reset(timer_handle_t *hperh)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-
-	hperh->state = TIMER_STATE_BUSY;
-	TIMER_DISABLE(hperh);
-	hperh->state = TIMER_STATE_RESET;
-	__UNLOCK(hperh);
-
-	return;
-}
-
-/**
-  * @brief  Starts the TIMER Base generation.
-  * @param  hperh: TIMER handle
-  * @retval None
-  */
-void timer_base_start(timer_handle_t *hperh)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-
-	hperh->state = TIMER_STATE_BUSY;
-	TIMER_ENABLE(hperh);
-	hperh->state = TIMER_STATE_READY;
-
-	return;
-}
-
-/**
-  * @brief  Stops the TIMER Base generation.
-  * @param  hperh: TIMER handle
-  * @retval None
-  */
-void timer_base_stop(timer_handle_t *hperh)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-
-	hperh->state = TIMER_STATE_BUSY;
-	TIMER_DISABLE(hperh);
-	hperh->state = TIMER_STATE_READY;
-
-	return;
-}
-
-/**
-  * @brief  Starts the TIMER Base generation in interrupt mode.
-  * @param  hperh: TIMER handle
-  * @retval None
-  */
-void timer_base_start_by_it(timer_handle_t *hperh)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-
-	timer_interrupt_config(hperh, TIMER_IT_UPDATE, ENABLE);
-	TIMER_ENABLE(hperh);
-
-	return;
-}
-
-/**
-  * @brief  Stops the TIMER Base generation in interrupt mode.
-  * @param  hperh: TIMER handle
-  * @retval None
-  */
-void timer_base_stop_by_it(timer_handle_t *hperh)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-
-	timer_interrupt_config(hperh, TIMER_IT_UPDATE, DISABLE);
-	TIMER_DISABLE(hperh);
-
-	return;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  Starts the TIMER Base generation in DMA mode.
-  * @param  hperh: TIMER handle
-  * @param  hdma: Pointer to dma_handle_t.
-  * @param  buf: The source Buffer address.
-  * @param  len: The length of buffer to be transferred from memory to TIMER peripheral
-  * @param  dma_ch: Channel of DMA.
-  * @retval Status, see @ref ald_status_t.
-*/
-ald_status_t timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma,
-                                  uint16_t *buf, uint32_t len, uint8_t dma_ch)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-
-	if ((hperh->state == TIMER_STATE_BUSY))
-		 return BUSY;
-	if ((hperh->state == TIMER_STATE_READY)) {
-		if (((uint32_t)buf == 0 ) || (len == 0))
-			return ERROR;
-	}
-
-	hperh->state   = TIMER_STATE_BUSY;
-
-	if (hdma->perh == NULL)
-		hdma->perh = DMA0;
-
-	hdma->cplt_cbk = timer_dma_period_elapse_cplt;
-	hdma->cplt_arg = (void *)hperh;
-	hdma->err_cbk  = timer_dma_error;
-	hdma->err_arg  = (void *)hperh;
-
-	dma_config_struct(&hdma->config);
-	hdma->config.src        = (void *)buf;
-	hdma->config.dst        = (void *)&hperh->perh->AR;
-	hdma->config.size       = len;
-	hdma->config.data_width = DMA_DATA_SIZE_HALFWORD;
-	hdma->config.src_inc    = DMA_DATA_INC_HALFWORD;
-	hdma->config.dst_inc    = DMA_DATA_INC_NONE;
-	hdma->config.msigsel    = DMA_MSIGSEL_TIMER_UPDATE;
-	hdma->config.channel    = dma_ch;
-
-	if (hperh->perh == TIMER0)
-		hdma->config.msel = DMA_MSEL_TIMER0;
-	else if (hperh->perh == TIMER1)
-		hdma->config.msel = DMA_MSEL_TIMER1;
-	else if (hperh->perh == TIMER2)
-		hdma->config.msel = DMA_MSEL_TIMER2;
-	else if (hperh->perh == TIMER3)
-		hdma->config.msel = DMA_MSEL_TIMER3;
-	else if (hperh->perh == TIMER4)
-		hdma->config.msel = DMA_MSEL_TIMER4;
-	else if (hperh->perh == TIMER5)
-		hdma->config.msel = DMA_MSEL_TIMER5;
-	else if (hperh->perh == TIMER6)
-		hdma->config.msel = DMA_MSEL_TIMER6;
-	else if (hperh->perh == TIMER7)
-		hdma->config.msel = DMA_MSEL_TIMER7;
-	else
-		;
-
-	dma_config_basic(hdma);
-	timer_dma_req_config(hperh, TIMER_DMA_UPDATE, ENABLE);
-	TIMER_ENABLE(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Stops the TIMER Base generation in DMA mode.
-  * @param  hperh: TIMER handle
-  * @retval None
-*/
-void timer_base_stop_by_dma(timer_handle_t *hperh)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-
-	timer_dma_req_config(hperh, TIMER_DMA_UPDATE, DISABLE);
-	TIMER_DISABLE(hperh);
-	hperh->state = TIMER_STATE_READY;
-
-	return;
-}
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup TIMER_Public_Functions_Group2 TIMER Output Compare functions
-  *  @brief   Time Output Compare functions
-  *
-  * @verbatim
-  ==============================================================================
-                  ##### Time Output Compare functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIMER Output Compare.
-    (+) Start the Time Output Compare.
-    (+) Stop the Time Output Compare.
-    (+) Start the Time Output Compare and enable interrupt.
-    (+) Stop the Time Output Compare and disable interrupt.
-    (+) Start the Time Output Compare and enable DMA transfer.
-    (+) Stop the Time Output Compare and disable DMA transfer.
-
-    @endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIMER Output Compare according to the specified
-  *         parameters in the timer_handle_t and create the associated handle.
-  * @param  hperh: TIMER handle
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_oc_init(timer_handle_t *hperh)
-{
-	return timer_base_init(hperh);
-}
-
-/**
-  * @brief  Starts the TIMER Output Compare signal generation.
-  * @param  hperh: TIMER handle
-  * @param  ch : TIMER Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *            @arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval None
-  */
-void timer_oc_start(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
-
-	timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
-
-	if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
-		TIMER_MOE_ENABLE(hperh);
-
-	TIMER_ENABLE(hperh);
-	return;
-}
-
-/**
-  * @brief  Stops the TIMER Output Compare signal generation.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *            @arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval None
-  */
-void timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
-
-	timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
-
-	if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
-		TIMER_MOE_DISABLE(hperh);
-
-	TIMER_DISABLE(hperh);
-	hperh->state = TIMER_STATE_READY;
-	return;
-}
-
-/**
-  * @brief  Starts the TIMER Output Compare signal generation in interrupt mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *            @arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval None
-  */
-void timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
-		break;
-
-	case TIMER_CHANNEL_2:
-		timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
-		break;
-
-	case TIMER_CHANNEL_3:
-		timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE);
-		break;
-
-	case TIMER_CHANNEL_4:
-		timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE);
-		break;
-
-	default:
-		break;
-	}
-
-	timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
-
-	if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
-		TIMER_MOE_ENABLE(hperh);
-
-	TIMER_ENABLE(hperh);
-	return;
-}
-
-/**
-  * @brief  Stops the TIMER Output Compare signal generation in interrupt mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *            @arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval None
-  */
-void timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
-		break;
-
-	case TIMER_CHANNEL_2:
-		timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
-		break;
-
-	case TIMER_CHANNEL_3:
-		timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE);
-		break;
-
-	case TIMER_CHANNEL_4:
-		timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE);
-		break;
-
-	default:
-		break;
-	}
-
-	timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
-
-	if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
-		TIMER_MOE_DISABLE(hperh);
-
-	TIMER_DISABLE(hperh);
-	hperh->state = TIMER_STATE_READY;
-	return;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  Starts the TIMER Output Compare signal generation in DMA mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *		This parameter can be one of the following values:
-  *		@arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *		@arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *		@arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *		@arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @param  hdma: Pointer to dma_handle_t.
-  * @param  buf: The source Buffer address.
-  * @param  len: The length of buffer to be transferred from memory to TIMER peripheral
-  * @param  dma_ch: Channel of DMA.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
-                      dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch)
-{
-	assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
-
-	if ((hperh->state == TIMER_STATE_BUSY))
-		 return BUSY;
-	if ((hperh->state == TIMER_STATE_READY)) {
-		if (((uint32_t)buf == 0 ) || (len == 0))
-			return ERROR;
-	}
-
-	hperh->state   = TIMER_STATE_BUSY;
-
-	if (hdma->perh == NULL)
-		hdma->perh = DMA0;
-
-	hdma->cplt_cbk = timer_dma_oc_cplt;
-	hdma->cplt_arg = (void *)hperh;
-	hdma->err_cbk  = timer_dma_error;
-	hdma->err_arg  = (void *)hperh;
-
-	dma_config_struct(&hdma->config);
-	hdma->config.src        = (void *)buf;
-	hdma->config.size       = len;
-	hdma->config.data_width = DMA_DATA_SIZE_HALFWORD;
-	hdma->config.src_inc    = DMA_DATA_INC_HALFWORD;
-	hdma->config.dst_inc    = DMA_DATA_INC_NONE;
-	hdma->config.channel    = dma_ch;
-
-	if (hperh->perh == TIMER0)
-		hdma->config.msel = DMA_MSEL_TIMER0;
-	else if (hperh->perh == TIMER1)
-		hdma->config.msel = DMA_MSEL_TIMER1;
-	else if (hperh->perh == TIMER2)
-		hdma->config.msel = DMA_MSEL_TIMER2;
-	else if (hperh->perh == TIMER3)
-		hdma->config.msel = DMA_MSEL_TIMER3;
-	else if (hperh->perh == TIMER4)
-		hdma->config.msel = DMA_MSEL_TIMER4;
-	else if (hperh->perh == TIMER5)
-		hdma->config.msel = DMA_MSEL_TIMER5;
-	else if (hperh->perh == TIMER6)
-		hdma->config.msel = DMA_MSEL_TIMER6;
-	else if (hperh->perh == TIMER7)
-		hdma->config.msel = DMA_MSEL_TIMER7;
-	else
-		;//do nothing
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		hdma->config.dst     = (void *)&hperh->perh->CCVAL1;
-		hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1;
-		dma_config_basic(hdma);
-		timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
-		hperh->ch = TIMER_ACTIVE_CHANNEL_1;
-		break;
-
-	case TIMER_CHANNEL_2:
-		hdma->config.dst     = (void *)&hperh->perh->CCVAL2;
-		hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2;
-		dma_config_basic(hdma);
-		timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE);
-		hperh->ch = TIMER_ACTIVE_CHANNEL_2;
-		break;
-
-	case TIMER_CHANNEL_3:
-		hdma->config.dst     = (void *)&hperh->perh->CCVAL3;
-		hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3;
-		dma_config_basic(hdma);
-		timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE);
-		hperh->ch = TIMER_ACTIVE_CHANNEL_3;
-		break;
-
-	case TIMER_CHANNEL_4:
-		hdma->config.dst     = (void *)&hperh->perh->CCVAL4;
-		hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4;
-		dma_config_basic(hdma);
-		timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE);
-		hperh->ch = TIMER_ACTIVE_CHANNEL_4;
-		break;
-
-	default:
-		break;
-	}
-
-	timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
-
-	if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
-		TIMER_MOE_ENABLE(hperh);
-
-	TIMER_ENABLE(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Stops the TIMER Output Compare signal generation in DMA mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be disabled
-  *		This parameter can be one of the following values:
-  *		@arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *		@arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *		@arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *		@arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval None
-*/
-void timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
-		break;
-
-	case TIMER_CHANNEL_2:
-		timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE);
-		break;
-
-	case TIMER_CHANNEL_3:
-		timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE);
-		break;
-
-	case TIMER_CHANNEL_4:
-		timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE);
-		break;
-
-	default:
-		break;
-	}
-
-	timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
-
-	if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
-		TIMER_MOE_DISABLE(hperh);
-
-	TIMER_DISABLE(hperh);
-	hperh->state = TIMER_STATE_READY;
-	return;
-}
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup  TIMER_Public_Functions_Group3 TIMER PWM functions
-  * @brief     TIMER PWM functions
-  *
-  * @verbatim
-	==============================================================================
-	##### Time PWM functions #####
-	==============================================================================
-	[..]
-		This section provides functions allowing to:
-		(+) Initialize and configure the TIMER PWM.
-		(+) Start the Time PWM.
-		(+) Stop the Time PWM.
-		(+) Start the Time PWM and enable interrupt.
-		(+) Stop the Time PWM and disable interrupt.
-		(+) Start the Time PWM and enable DMA transfer.
-		(+) Stop the Time PWM and disable DMA transfer.
-
-    @endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIMER PWM Time Base according to the specified
-  *         parameters in the timer_handle_t and create the associated handle.
-  * @param  hperh: TIMER handle
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_pwm_init(timer_handle_t *hperh)
-{
-	return timer_base_init(hperh);
-}
-
-/**
-  * @brief  Starts the PWM signal generation.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *		This parameter can be one of the following values:
-  *		@arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *		@arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *		@arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *		@arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval None
-  */
-void timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch)
-{
-	timer_oc_start(hperh, ch);
-	return;
-}
-
-/**
-  * @brief  Stops the PWM signal generation.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be disabled
-  *		This parameter can be one of the following values:
-  *		@arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *		@arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *		@arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *		@arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval None
-  */
-void timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch)
-{
-	timer_oc_stop(hperh, ch);
-	return;
-}
-
-/**
-  * @brief  Starts the PWM signal generation in interrupt mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channel to be disabled
-  *		This parameter can be one of the following values:
-  *		@arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *		@arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *		@arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *		@arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval None
-  */
-void timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
-{
-	timer_oc_start_by_it(hperh, ch);
-	return;
-}
-
-/**
-  * @brief  Stops the PWM signal generation in interrupt mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be disabled
-  *		This parameter can be one of the following values:
-  *		@arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *		@arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *		@arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *		@arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval None
-  */
-void timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
-{
-	timer_oc_stop_by_it(hperh, ch);
-	return;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  Starts the TIMER PWM signal generation in DMA mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *		This parameter can be one of the following values:
-  *		@arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *		@arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *		@arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *		@arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @param  hdma: Pointer to dma_handle_t.
-  * @param  buf: The source Buffer address.
-  * @param  len: The length of buffer to be transferred from memory to TIMER peripheral
-  * @param  dma_ch: Channel of DMA.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
-                      dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch)
-{
-	return timer_oc_start_by_dma(hperh, ch, hdma, buf, len, dma_ch);
-}
-
-/**
-  * @brief  Stops the TIMER PWM signal generation in DMA mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be disabled
-  *		This parameter can be one of the following values:
-  *		@arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *		@arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *		@arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *		@arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval None
-  */
-void timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
-{
-	timer_oc_stop_by_dma(hperh, ch);
-	return;
-}
-#endif
-/**
-  * @brief  Set the PWM freq.
-  * @param  hperh: TIMER handle
-  * @param  freq: PWM freq to set
-  * @retval None
-  */
-void timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq)
-{
-	uint32_t _arr = cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1;
-
-	WRITE_REG(hperh->perh->AR, _arr);
-	hperh->init.period   = _arr;
-}
-
-/**
-  * @brief  Set the PWM duty.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *		This parameter can be one of the following values:
-  *		@arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *		@arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *		@arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *		@arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @param  duty: PWM duty to set
-  * @retval None
-  */
-void timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty)
-{
-	uint32_t tmp = (hperh->init.period + 1) * duty / 100 - 1;
-
-	if (ch == TIMER_CHANNEL_1)
-		WRITE_REG(hperh->perh->CCVAL1, tmp);
-	else if (ch == TIMER_CHANNEL_2)
-		WRITE_REG(hperh->perh->CCVAL2, tmp);
-	else if (ch == TIMER_CHANNEL_3)
-		WRITE_REG(hperh->perh->CCVAL3, tmp);
-	else if (ch == TIMER_CHANNEL_4)
-		WRITE_REG(hperh->perh->CCVAL4, tmp);
-	else {
-		;/* do nothing */
-	}
-}
-
-/**
-  * @brief  Set capture the PWM.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be captured the PWM
-  *		This parameter can be one of the following values:
-  *		@arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *		@arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  * @retval None
-  */
-void timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_PWM_INPUT_INSTANCE(hperh->perh, ch));
-
-	CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK);
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS);
-		MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS);
-		MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS);
-		MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS);
-		MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS);
-		MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS);
-		break;
-	case TIMER_CHANNEL_2:
-		MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS);
-		MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS);
-		MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS);
-		MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS);
-		MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS);
-		MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS);
-		break;
-	default:
-		break;
-	}
-
-	SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK);
-	SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2EN_MSK);
-
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIMER_Public_Functions_Group4 TIMER Input Capture functions
-  * @brief    Time Input Capture functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### Time Input Capture functions #####
-  ==============================================================================
- [..]
-   This section provides functions allowing to:
-   (+) Initialize and configure the TIMER Input Capture.
-   (+) Start the Time Input Capture.
-   (+) Stop the Time Input Capture.
-   (+) Start the Time Input Capture and enable interrupt.
-   (+) Stop the Time Input Capture and disable interrupt.
-   (+) Start the Time Input Capture and enable DMA transfer.
-   (+) Stop the Time Input Capture and disable DMA transfer.
-
-  * @endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIMER Input Capture Time base according to the specified
-  *         parameters in the timer_handle_t and create the associated handle.
-  * @param  hperh: TIMER handle
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_ic_init(timer_handle_t *hperh)
-{
-	return timer_base_init(hperh);
-}
-
-/**
-  * @brief  Starts the TIMER Input Capture measurement.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *            @arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval None
-  */
-void timer_ic_start(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
-
-	timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
-	TIMER_ENABLE(hperh);
-	return;
-}
-
-/**
-  * @brief  Stops the TIMER Input Capture measurement.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *            @arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval None
-  */
-void timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
-
-	timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
-	TIMER_DISABLE(hperh);
-	return;
-}
-
-/**
-  * @brief  Starts the TIMER Input Capture measurement in interrupt mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *            @arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval None
-  */
-void timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
-		break;
-	case TIMER_CHANNEL_2:
-		timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
-		break;
-	case TIMER_CHANNEL_3:
-		timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE);
-		break;
-	case TIMER_CHANNEL_4:
-		timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE);
-		break;
-	default:
-		break;
-	}
-
-	timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
-	TIMER_ENABLE(hperh);
-	return;
-}
-
-/**
-  * @brief  Stops the TIMER Input Capture measurement in interrupt mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *            @arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval None
-  */
-void timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
-		break;
-	case TIMER_CHANNEL_2:
-		timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
-		break;
-	case TIMER_CHANNEL_3:
-		timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE);
-		break;
-	case TIMER_CHANNEL_4:
-		timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE);
-		break;
-	default:
-		break;
-	}
-
-	timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
-	TIMER_DISABLE(hperh);
-	return;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  Starts the TIMER Input Capture measurement in DMA mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *		This parameter can be one of the following values:
-  *		@arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *		@arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *		@arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *		@arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @param  hdma: Pointer to dma_handle_t.
-  * @param  buf: The destination Buffer address.
-  * @param  len: The length of buffer to be transferred TIMER peripheral to memory
-  * @param  dma_ch: Channel of DMA.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
-                      dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch)
-{
-	assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
-
-	if ((hperh->state == TIMER_STATE_BUSY))
-		 return BUSY;
-	if ((hperh->state == TIMER_STATE_READY)) {
-		if (((uint32_t)buf == 0 ) || (len == 0))
-			return ERROR;
-	}
-
-	hperh->state   = TIMER_STATE_BUSY;
-
-	if (hdma->perh == NULL)
-		hdma->perh = DMA0;
-
-	hdma->cplt_cbk = timer_dma_capture_cplt;
-	hdma->cplt_arg = (void *)hperh;
-	hdma->err_cbk  = timer_dma_error;
-	hdma->err_arg  = (void *)hperh;
-
-	dma_config_struct(&hdma->config);
-	hdma->config.dst        = (void *)buf;
-	hdma->config.size       = len;
-	hdma->config.data_width = DMA_DATA_SIZE_HALFWORD;
-	hdma->config.src_inc    = DMA_DATA_INC_NONE;
-	hdma->config.dst_inc    = DMA_DATA_INC_HALFWORD;
-	hdma->config.channel    = dma_ch;
-
-	if (hperh->perh == TIMER0)
-		hdma->config.msel = DMA_MSEL_TIMER0;
-	else if (hperh->perh == TIMER1)
-		hdma->config.msel = DMA_MSEL_TIMER1;
-	else if (hperh->perh == TIMER2)
-		hdma->config.msel = DMA_MSEL_TIMER2;
-	else if (hperh->perh == TIMER3)
-		hdma->config.msel = DMA_MSEL_TIMER3;
-	else if (hperh->perh == TIMER4)
-		hdma->config.msel = DMA_MSEL_TIMER4;
-	else if (hperh->perh == TIMER5)
-		hdma->config.msel = DMA_MSEL_TIMER5;
-	else if (hperh->perh == TIMER6)
-		hdma->config.msel = DMA_MSEL_TIMER6;
-	else if (hperh->perh == TIMER7)
-		hdma->config.msel = DMA_MSEL_TIMER7;
-	else
-		;/* do nothing */
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		hdma->config.src     = (void *)&hperh->perh->CCVAL1;
-		hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1;
-		dma_config_basic(hdma);
-		timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
-		hperh->ch = TIMER_ACTIVE_CHANNEL_1;
-		break;
-
-	case TIMER_CHANNEL_2:
-		hdma->config.src     = (void *)&hperh->perh->CCVAL2;
-		hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2;
-		dma_config_basic(hdma);
-		timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE);
-		hperh->ch = TIMER_ACTIVE_CHANNEL_2;
-		break;
-
-	case TIMER_CHANNEL_3:
-		hdma->config.src     = (void *)&hperh->perh->CCVAL3;
-		hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3;
-		dma_config_basic(hdma);
-		timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE);
-		hperh->ch = TIMER_ACTIVE_CHANNEL_3;
-		break;
-
-	case TIMER_CHANNEL_4:
-		hdma->config.src     = (void *)&hperh->perh->CCVAL4;
-		hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4;
-		dma_config_basic(hdma);
-		timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE);
-		hperh->ch = TIMER_ACTIVE_CHANNEL_4;
-		break;
-
-	default:
-		break;
-	}
-
-	timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
-	TIMER_ENABLE(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Stops the TIMER Input Capture measurement in DMA mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be disabled
-  *		This parameter can be one of the following values:
-  *		@arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *		@arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *		@arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *		@arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval None
-  */
-void timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
-		break;
-	case TIMER_CHANNEL_2:
-		timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE);
-		break;
-	case TIMER_CHANNEL_3:
-		timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE);
-		break;
-	case TIMER_CHANNEL_4:
-		timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE);
-		break;
-	default:
-		break;
-	}
-
-	timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
-	TIMER_DISABLE(hperh);
-	hperh->state = TIMER_STATE_READY;
-	return;
-}
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup TIMER_Public_Functions_Group5 TIMER One Pulse functions
-  * @brief    Time One Pulse functions
-  *
-  * @verbatim
-  ==============================================================================
-                        ##### Time One Pulse functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIMER One Pulse.
-    (+) Start the Time One Pulse.
-    (+) Stop the Time One Pulse.
-    (+) Start the Time One Pulse and enable interrupt.
-    (+) Stop the Time One Pulse and disable interrupt.
-    (+) Start the Time One Pulse and enable DMA transfer.
-    (+) Stop the Time One Pulse and disable DMA transfer.
-
-  * @endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIMER One Pulse Time Base according to the specified
-  *         parameters in the timer_handle_t and create the associated handle.
-  * @param  hperh: TIMER handle
-  * @param  mode: Select the One pulse mode.
-  *         This parameter can be one of the following values:
-  *            @arg TIMER_OP_MODE_SINGLE: Only one pulse will be generated.
-  *            @arg TIMER_OP_MODE_REPEAT: Repetitive pulses wil be generated.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode)
-{
-	if (hperh == NULL)
-		return ERROR;
-
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode));
-	assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div));
-	assert_param(IS_TIMER_OP_MODE(mode));
-
-	if (hperh->state == TIMER_STATE_RESET)
-		hperh->lock = UNLOCK;
-
-	hperh->state = TIMER_STATE_BUSY;
-	timer_base_set_config(hperh->perh, &hperh->init);
-	MODIFY_REG(hperh->perh->CON1, TIMER_CON1_SPMEN_MSK, mode << TIMER_CON1_SPMEN_POS);
-	hperh->state = TIMER_STATE_READY;
-
-	return OK;
-}
-
-/**
-  * @brief  Starts the TIMER One Pulse signal generation.
-  * @param  hperh: TIMER One Pulse handle
-  * @param  ch: TIMER Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected
-  * @retval None
-  */
-void timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch)
-{
-	/* Enable the Capture compare and the Input Capture channels
-	 * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2)
-	 * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and
-	 * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output
-	 * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together
-	 */
-	timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
-	timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
-
-	if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
-		TIMER_MOE_ENABLE(hperh);
-
-	return;
-}
-
-/**
-  * @brief  Stops the TIMER One Pulse signal generation.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *         This parameter can be one of the following values:
-  *            @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected
-  * @retval None
-  */
-void timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch)
-{
-	timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
-	timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
-
-	if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
-		TIMER_MOE_DISABLE(hperh);
-
-	TIMER_DISABLE(hperh);
-	return;
-}
-
-/**
-  * @brief  Starts the TIMER One Pulse signal generation in interrupt mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *         This parameter can be one of the following values:
-  *            @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected
-  * @retval None
-  */
-void timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch)
-{
-	/* Enable the Capture compare and the Input Capture channels
-	 * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2)
-	 * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and
-	 * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output
-	 * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together
-	 */
-	timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
-	timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
-	timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
-	timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
-
-	if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
-		TIMER_MOE_ENABLE(hperh);
-
-	return;
-}
-
-/**
-  * @brief  Stops the TIMER One Pulse signal generation in interrupt mode.
-  * @param  hperh : TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *         This parameter can be one of the following values:
-  *            @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected
-  * @retval None
-  */
-void timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch)
-{
-	timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
-	timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
-	timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
-	timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
-
-	if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
-		TIMER_MOE_DISABLE(hperh);
-
-	TIMER_DISABLE(hperh);
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIMER_Public_Functions_Group6 TIMER Encoder functions
-  * @brief    TIMER Encoder functions
-  *
-  * @verbatim
-	==============================================================================
-	##### Time Encoder functions #####
-	==============================================================================
-	[..]
-		This section provides functions allowing to:
-		(+) Initialize and configure the TIMER Encoder.
-		(+) Start the Time Encoder.
-		(+) Stop the Time Encoder.
-		(+) Start the Time Encoder and enable interrupt.
-		(+) Stop the Time Encoder and disable interrupt.
-		(+) Start the Time Encoder and enable DMA transfer.
-		(+) Stop the Time Encoder and disable DMA transfer.
-
-  * @endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIMER Encoder Interface and create the associated handle.
-  * @param  hperh: TIMER handle
-  * @param  config: TIMER Encoder Interface configuration structure
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_encoder_init(timer_handle_t *hperh,  timer_encoder_init_t *config)
-{
-	if (hperh == NULL)
-		return ERROR;
-
-	assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_ENCODER_MODE(config->mode));
-	assert_param(IS_TIMER_IC_POLARITY(config->ic1_polarity));
-	assert_param(IS_TIMER_IC_POLARITY(config->ic2_polarity));
-	assert_param(IS_TIMER_IC_SELECT(config->ic1_sel));
-	assert_param(IS_TIMER_IC_SELECT(config->ic2_sel));
-	assert_param(IS_TIMER_IC_PSC(config->ic1_psc));
-	assert_param(IS_TIMER_IC_PSC(config->ic2_psc));
-	assert_param(IS_TIMER_IC_FILTER(config->ic1_filter));
-	assert_param(IS_TIMER_IC_FILTER(config->ic2_filter));
-
-	if (hperh->state == TIMER_STATE_RESET)
-		hperh->lock = UNLOCK;
-
-	hperh->state = TIMER_STATE_BUSY;
-	CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK);
-	timer_base_set_config(hperh->perh, &hperh->init);
-
-	MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS);
-	MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, config->ic1_sel << TIMER_CHMR1_CC1SSEL_POSS);
-	MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, config->ic2_sel << TIMER_CHMR1_CC2SSEL_POSS);
-	MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->ic1_psc << TIMER_CHMR1_IC1PRES_POSS);
-	MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->ic2_psc << TIMER_CHMR1_IC2PRES_POSS);
-	MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->ic1_filter << TIMER_CHMR1_I1FLT_POSS);
-	MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I2FLT_MSK, config->ic2_filter << TIMER_CHMR1_I2FLT_POSS);
-	MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, (config->ic1_polarity & 0x1) << TIMER_CCEP_CC1POL_POS);
-	MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((config->ic1_polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS);
-	MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, (config->ic2_polarity & 0x1) << TIMER_CCEP_CC2POL_POS);
-	MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((config->ic2_polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS);
-
-	hperh->state = TIMER_STATE_READY;
-	return OK;
-}
-
-/**
-  * @brief  Starts the TIMER Encoder Interface.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *         This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected
-  * @retval None
-  */
-void timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
-		break;
-	case TIMER_CHANNEL_2:
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
-		break;
-	default:
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
-		break;
-	}
-
-	TIMER_ENABLE(hperh);
-	return;
-}
-
-/**
-  * @brief  Stops the TIMER Encoder Interface.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *         This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected
-  * @retval None
-  */
-void timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
-		break;
-	case TIMER_CHANNEL_2:
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
-		break;
-	default:
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
-		break;
-	}
-
-	TIMER_DISABLE(hperh);
-	return;
-}
-
-/**
-  * @brief  Starts the TIMER Encoder Interface in interrupt mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *         This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected
-  * @retval None
-  */
-void timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
-		timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
-		break;
-	case TIMER_CHANNEL_2:
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
-		timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
-		break;
-	default:
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
-		timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
-		timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
-		break;
-	}
-
-	TIMER_ENABLE(hperh);
-	return;
-}
-
-/**
-  * @brief  Stops the TIMER Encoder Interface in interrupt mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *         This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected
-  * @retval None
-  */
-void timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
-		timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
-		break;
-	case TIMER_CHANNEL_2:
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
-		timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
-		break;
-	default:
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
-		timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
-		timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
-		break;
-	}
-
-	TIMER_DISABLE(hperh);
-	hperh->state = TIMER_STATE_READY;
-	return;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  Starts the TIMER Encoder Interface in DMA mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *         This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected
-  * @param  hdma1: Pointer to dma_handle_t.
-  * @param  hdma2: Pointer to dma_handle_t.
-  * @param  buf1: The destination Buffer address. Reading data from CCR1.
-  * @param  buf2: The destination Buffer address. Reading data from CCR2.
-  * @param  len: The length of buffer to be transferred TIMER peripheral to memory
-  * @param  dma_ch1: Channel of DMA.
-  * @param  dma_ch2: Channel of DMA.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
-                           dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1,
-			   uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2)
-{
-	assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
-
-	if ((hperh->state == TIMER_STATE_BUSY))
-		 return BUSY;
-	if ((hperh->state == TIMER_STATE_READY)) {
-		if (((uint32_t)buf1 == 0) || ((uint32_t)buf2 == 0) || (len == 0))
-			return ERROR;
-	}
-
-	if (hdma1->perh == NULL)
-		hdma1->perh = DMA0;
-	if (hdma2->perh == NULL)
-		hdma2->perh = DMA0;
-
-	hperh->state    = TIMER_STATE_BUSY;
-	hdma1->cplt_cbk = timer_dma_capture_cplt;
-	hdma1->cplt_arg = (void *)hperh;
-	hdma1->err_cbk  = timer_dma_error;
-	hdma1->err_arg  = (void *)hperh;
-
-	dma_config_struct(&hdma1->config);
-	hdma1->config.size       = len;
-	hdma1->config.data_width = DMA_DATA_SIZE_HALFWORD;
-	hdma1->config.src_inc    = DMA_DATA_INC_NONE;
-	hdma1->config.dst_inc    = DMA_DATA_INC_HALFWORD;
-
-	if (hperh->perh == TIMER0)
-		hdma1->config.msel = DMA_MSEL_TIMER0;
-	else if (hperh->perh == TIMER1)
-		hdma1->config.msel = DMA_MSEL_TIMER1;
-	else if (hperh->perh == TIMER2)
-		hdma1->config.msel = DMA_MSEL_TIMER2;
-	else if (hperh->perh == TIMER3)
-		hdma1->config.msel = DMA_MSEL_TIMER3;
-	else if (hperh->perh == TIMER4)
-		hdma1->config.msel = DMA_MSEL_TIMER4;
-	else if (hperh->perh == TIMER5)
-		hdma1->config.msel = DMA_MSEL_TIMER5;
-	else if (hperh->perh == TIMER6)
-		hdma1->config.msel = DMA_MSEL_TIMER6;
-	else if (hperh->perh == TIMER7)
-		hdma1->config.msel = DMA_MSEL_TIMER7;
-	else
-		;/* do nothing */
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		hdma1->config.src     = (void *)&hperh->perh->CCVAL1;
-		hdma1->config.dst     = (void *)buf1;
-		hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1;
-		hdma1->config.channel = dma_ch1;
-		dma_config_basic(hdma1);
-		timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
-		TIMER_ENABLE(hperh);
-		break;
-
-	case TIMER_CHANNEL_2:
-		hdma1->config.src     = (void *)&hperh->perh->CCVAL2;
-		hdma1->config.dst     = (void *)buf2;
-		hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH2;
-		hdma1->config.channel = dma_ch2;
-		dma_config_basic(hdma1);
-		timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE);
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
-		TIMER_ENABLE(hperh);
-		break;
-
-	default:
-		hdma2->cplt_cbk = timer_dma_capture_cplt;
-		hdma2->cplt_arg = (void *)hperh;
-		hdma2->err_cbk  = timer_dma_error;
-		hdma2->err_arg  = (void *)hperh;
-		memcpy(&hdma2->config, &hdma1->config, sizeof(dma_config_t));
-
-		hdma1->config.src     = (void *)&hperh->perh->CCVAL1;
-		hdma1->config.dst     = (void *)buf1;
-		hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1;
-		hdma1->config.channel = dma_ch1;
-		dma_config_basic(hdma1);
-		timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
-
-		hdma2->config.src     = (void *)&hperh->perh->CCVAL2;
-		hdma2->config.dst     = (void *)buf2;
-		hdma2->config.msigsel = DMA_MSIGSEL_TIMER_CH2;
-		hdma2->config.channel = dma_ch2;
-		dma_config_basic(hdma2);
-		timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE);
-
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
-		TIMER_ENABLE(hperh);
-		break;
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  Stops the TIMER Encoder Interface in DMA mode.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be disabled
-  *         This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected
-  * @retval None
-  */
-void timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
-		timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
-		break;
-	case TIMER_CHANNEL_2:
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
-		timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE);
-		break;
-	default:
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
-		timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
-		timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
-		timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE);
-		break;
-	}
-
-	TIMER_DISABLE(hperh);
-	hperh->state = TIMER_STATE_READY;
-	return;
-}
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup TIMER_Public_Functions_Group7 TIMER Hall Sensor functions
-  * @brief    TIMER Hall Sensor functions
-  *
-  * @verbatim
-	==============================================================================
-	##### Time Hall Sensor functions #####
-	==============================================================================
-	[..]
-		This section provides functions allowing to:
-		(+) Initialize and configure the TIMER hall sensor.
-		(+) Start the hall sensor.
-		(+) Stop the hall sensor.
-		(+) Start the hall sensor and enable interrupt.
-		(+) Stop the hall sensor and disable interrupt.
-		(+) Start the hall sensor and enable DMA transfer.
-		(+) Stop the hal sensor and disable DMA transfer.
-
-  * @endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIMER Encoder Interface and create the associated handle.
-  * @param  hperh: TIMER handle
-  * @param  config: TIMER Encoder Interface configuration structure
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_hall_sensor_init(timer_handle_t *hperh,  timer_hall_sensor_init_t *config)
-{
-	timer_oc_init_t oc;
-
-	assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode));
-	assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div));
-	assert_param(IS_TIMER_IC_POLARITY(config->polarity));
-	assert_param(IS_TIMER_IC_PSC(config->psc));
-	assert_param(IS_TIMER_IC_FILTER(config->filter));
-
-	if (hperh->state == TIMER_STATE_RESET)
-		hperh->lock = UNLOCK;
-
-	hperh->state = TIMER_STATE_READY;
-	timer_base_set_config(hperh->perh, &hperh->init);
-	timer_ti1_set_config(hperh->perh, config->polarity, TIMER_IC_SEL_TRC, config->filter);
-
-	MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS);
-	SET_BIT(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK);
-	MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS);
-	MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS);
-
-	oc.oc_mode        = TIMER_OC_MODE_PWM2;
-	oc.pulse          = config->delay;
-	oc.oc_polarity    = TIMER_OC_POLARITY_HIGH;
-	oc.ocn_polarity   = TIMER_OCN_POLARITY_HIGH;
-	oc.oc_fast_en     = DISABLE;
-	oc.oc_idle        = TIMER_OC_IDLE_RESET;
-	oc.ocn_idle       = TIMER_OCN_IDLE_RESET;
-	timer_oc2_set_config(hperh->perh, &oc);
-
-	MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_TRGO_OC2REF << TIMER_SMCON_SMODS_POSS);
-	return OK;
-}
-/**
-  * @brief  Starts the TIMER hall sensor interface.
-  * @param  hperh: TIMER handle
-  * @retval None
-  */
-void timer_hall_sensor_start(timer_handle_t *hperh)
-{
-	assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
-
-	timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
-	TIMER_ENABLE(hperh);
-
-	return;
-}
-
-/**
-  * @brief  Stops the TIMER hall sensor interface.
-  * @param  hperh: TIMER handle
-  * @retval None
-  */
-void timer_hall_sensor_stop(timer_handle_t *hperh)
-{
-	assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
-
-	timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
-	TIMER_DISABLE(hperh);
-
-	return;
-}
-
-/**
-  * @brief  Starts the TIMER hall sensor interface in interrupt mode.
-  * @param  hperh: TIMER handle
-  * @retval None
-  */
-void timer_hall_sensor_start_by_it(timer_handle_t *hperh)
-{
-	assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
-
-	timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
-	timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
-	TIMER_ENABLE(hperh);
-
-	return;
-}
-
-/**
-  * @brief  Stops the TIMER hall sensor interface in interrupt mode.
-  * @param  hperh: TIMER handle
-  * @retval None
-  */
-void timer_hall_sensor_stop_by_it(timer_handle_t *hperh)
-{
-	assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
-
-	timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
-	timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
-	TIMER_DISABLE(hperh);
-
-	return;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  Starts the TIMER hall sensor interface in DMA mode.
-  * @param  hperh: TIMER handle
-  * @param  hdma: Pointer to dma_handle_t.
-  * @param  buf: The destination Buffer address. Reading data from CCR1.
-  * @param  len: The length of buffer to be transferred TIMER peripheral to memory
-  * @param  dma_ch: Channel of DMA.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma,
-		                       uint16_t *buf, uint32_t len, uint8_t dma_ch)
-{
-	assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
-
-	if ((hperh->state == TIMER_STATE_BUSY))
-		 return BUSY;
-	if ((hperh->state == TIMER_STATE_READY)) {
-		if (((uint32_t)buf == 0) ||  (len == 0))
-			return ERROR;
-	}
-
-	if (hdma->perh == NULL)
-		hdma->perh = DMA0;
-
-	hperh->state   = TIMER_STATE_BUSY;
-	hdma->cplt_cbk = timer_dma_capture_cplt;
-	hdma->cplt_arg = (void *)hperh;
-	hdma->err_cbk  = timer_dma_error;
-	hdma->err_arg  = (void *)hperh;
-
-	dma_config_struct(&hdma->config);
-	hdma->config.size       = len;
-	hdma->config.data_width = DMA_DATA_SIZE_HALFWORD;
-	hdma->config.src_inc    = DMA_DATA_INC_NONE;
-	hdma->config.dst_inc    = DMA_DATA_INC_HALFWORD;
-
-	if (hperh->perh == TIMER0)
-		hdma->config.msel = DMA_MSEL_TIMER0;
-	else if (hperh->perh == TIMER6)
-		hdma->config.msel = DMA_MSEL_TIMER6;
-	else
-		;/* do nothing */
-
-	hdma->config.src     = (void *)&hperh->perh->CCVAL1;
-	hdma->config.dst     = (void *)buf;
-	hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1;
-	hdma->config.channel = dma_ch;
-	dma_config_basic(hdma);
-	timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
-	timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
-	TIMER_ENABLE(hperh);
-
-	return OK;
-}
-/**
-  * @brief  Stops the TIMER hall sensor interface in DMA mode.
-  * @param  hperh: TIMER handle
-  * @retval None
-  */
-void timer_hall_sensor_stop_by_dma(timer_handle_t *hperh)
-{
-	assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
-
-	timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
-	timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
-	TIMER_DISABLE(hperh);
-
-	return;
-}
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup TIMER_Public_Functions_Group8 TIMER complementary output compare functions
-  * @brief    TIMER complementary output compare functions
-  *
-  * @verbatim
-	==============================================================================
-	##### Time complementary output compare functions #####
-	==============================================================================
-	[..]
-		This section provides functions allowing to:
-		(+) Start the Time complementary output compare.
-		(+) Stop the Time complementary output compare.
-		(+) Start the Time complementary output compare and enable interrupt.
-		(+) Stop the Time complementary output compare and disable interrupt.
-		(+) Start the Time complementary output compare and enable DMA transfer.
-		(+) Stop the Time complementary output compare and disable DMA transfer.
-
-  * @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the TIMER output compare signal generation on the complementary output.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  * @retval None
-  */
-void timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
-
-	timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE);
-	TIMER_MOE_ENABLE(hperh);
-	TIMER_ENABLE(hperh);
-
-	return;
-}
-
-/**
-  * @brief  Stops the TIMER output compare signal generation on the complementary output.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  * @retval None
-  */
-void timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
-
-	timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE);
-	TIMER_MOE_DISABLE(hperh);
-	TIMER_DISABLE(hperh);
-
-	return;
-}
-
-/**
-  * @brief  Starts the TIMER output compare signal generation on the complementary output.
-  *         in interrupt mode
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  * @retval None
-  */
-void timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
-		break;
-
-	case TIMER_CHANNEL_2:
-		timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
-		break;
-
-	case TIMER_CHANNEL_3:
-		timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE);
-		break;
-	default:
-		break;
-	}
-
-	timer_interrupt_config(hperh, TIMER_IT_BREAK, ENABLE);
-	timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE);
-	TIMER_MOE_ENABLE(hperh);
-	TIMER_ENABLE(hperh);
-
-	return;
-}
-
-/**
-  * @brief  Stops the TIMER output compare signal generation on the complementary output.
-  *         in interrupt mode
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  * @retval None
-  */
-void timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
-		break;
-
-	case TIMER_CHANNEL_2:
-		timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
-		break;
-
-	case TIMER_CHANNEL_3:
-		timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE);
-		break;
-	default:
-		break;
-	}
-
-	if ((!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1NEN_MSK)))
-			&& (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2NEN_MSK)))
-			&& (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC3NEN_MSK)))) {
-		timer_interrupt_config(hperh, TIMER_IT_BREAK, DISABLE);
-	}
-
-	timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE);
-	TIMER_MOE_DISABLE(hperh);
-	TIMER_DISABLE(hperh);
-
-	return;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  Starts the TIMER output compare signal generation on the complementary output.
-  *         in DMA mode
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  * @param  hdma: Pointer to dma_handle_t.
-  * @param  buf: The destination Buffer address. Reading data from CCRx.
-  * @param  len: The length of buffer to be transferred TIMER peripheral to memory
-  * @param  dma_ch: Channel of DMA.
-  * @retval None
-  */
-ald_status_t timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma,
-		          timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
-{
-	assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
-
-	if ((hperh->state == TIMER_STATE_BUSY))
-		 return BUSY;
-	if ((hperh->state == TIMER_STATE_READY)) {
-		if (((uint32_t)buf == 0 ) || (len == 0))
-			return ERROR;
-	}
-
-	hperh->state   = TIMER_STATE_BUSY;
-
-	if (hdma->perh == NULL)
-		hdma->perh = DMA0;
-
-	hdma->cplt_cbk = timer_dma_oc_cplt;
-	hdma->cplt_arg = (void *)hperh;
-	hdma->err_cbk  = timer_dma_error;
-	hdma->err_arg  = (void *)hperh;
-
-	dma_config_struct(&hdma->config);
-	hdma->config.src        = (void *)buf;
-	hdma->config.size       = len;
-	hdma->config.data_width = DMA_DATA_SIZE_HALFWORD;
-	hdma->config.src_inc    = DMA_DATA_INC_HALFWORD;
-	hdma->config.dst_inc    = DMA_DATA_INC_NONE;
-	hdma->config.channel    = dma_ch;
-	hdma->config.msel       = DMA_MSEL_TIMER0;
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		hdma->config.dst     = (void *)&hperh->perh->CCVAL1;
-		hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1;
-		dma_config_basic(hdma);
-		timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
-		hperh->ch = TIMER_ACTIVE_CHANNEL_1;
-		break;
-
-	case TIMER_CHANNEL_2:
-		hdma->config.dst     = (void *)&hperh->perh->CCVAL2;
-		hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2;
-		dma_config_basic(hdma);
-		timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE);
-		hperh->ch = TIMER_ACTIVE_CHANNEL_2;
-		break;
-
-	case TIMER_CHANNEL_3:
-		hdma->config.dst     = (void *)&hperh->perh->CCVAL3;
-		hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3;
-		dma_config_basic(hdma);
-		timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE);
-		hperh->ch = TIMER_ACTIVE_CHANNEL_3;
-		break;
-
-	default:
-		break;
-	}
-
-	timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
-	TIMER_MOE_ENABLE(hperh);
-	TIMER_ENABLE(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Starts the TIMER output compare signal generation on the complementary output.
-  *         in DMA mode
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  * @retval None
-  */
-void timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
-		break;
-
-	case TIMER_CHANNEL_2:
-		timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE);
-		break;
-
-	case TIMER_CHANNEL_3:
-		timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE);
-		break;
-	default:
-		break;
-	}
-
-	timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE);
-	TIMER_MOE_DISABLE(hperh);
-	TIMER_DISABLE(hperh);
-
-	return;
-}
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup TIMER_Public_Functions_Group9 TIMER complementary PWM functions
-  * @brief    TIMER complementary PWM functions
-  *
-  * @verbatim
-	==============================================================================
-	##### Time complementary PWM functions #####
-	==============================================================================
-	[..]
-		This section provides functions allowing to:
-		(+) Start the Time complementary PWM.
-		(+) Stop the Time complementary PWM.
-		(+) Start the Time complementary PWM and enable interrupt.
-		(+) Stop the Time complementary PWM and disable interrupt.
-		(+) Start the Time complementary PWM and enable DMA transfer.
-		(+) Stop the Time complementary PWM and disable DMA transfer.
-
-  * @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the TIMER PWM signal generation on the complementary output.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  * @retval None
-  */
-void timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch)
-{
-	timer_ocn_start(hperh, ch);
-}
-
-/**
-  * @brief  Stops the TIMER PWM signal generation on the complementary output.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  * @retval None
-  */
-void timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch)
-{
-	timer_ocn_stop(hperh, ch);
-}
-
-/**
-  * @brief  Starts the TIMER PWM signal generation on the complementary output.
-  *         in interrupt mode
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  * @retval None
-  */
-void timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
-{
-	timer_ocn_start_by_it(hperh, ch);
-}
-
-/**
-  * @brief  Stops the TIMER PWM signal generation on the complementary output.
-  *         in interrupt mode
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  * @retval None
-  */
-void timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
-{
-	timer_ocn_stop_by_it(hperh, ch);
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  Starts the TIMER PWM signal generation on the complementary output.
-  *         in DMA mode
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  * @param  hdma: Pointer to dma_handle_t.
-  * @param  buf: The destination Buffer address. Reading data from CCRx.
-  * @param  len: The length of buffer to be transferred TIMER peripheral to memory
-  * @param  dma_ch: Channel of DMA.
-  * @retval None
-  */
-ald_status_t timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma,
-		          timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
-{
-	return timer_ocn_start_by_dma(hperh, hdma, ch, buf, len, dma_ch);
-}
-
-/**
-  * @brief  Starts the TIMER PWM signal generation on the complementary output.
-  *         in DMA mode
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  * @retval None
-  */
-void timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
-{
-	timer_ocn_stop_by_dma(hperh, ch);
-}
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup TIMER_Public_Functions_Group10 TIMER complementary one pulse functions
-  * @brief    TIMER complementary one pulse functions
-  *
-  * @verbatim
-	==============================================================================
-	##### Time complementary one pulse functions #####
-	==============================================================================
-	[..]
-		This section provides functions allowing to:
-		(+) Start the Time complementary one pulse.
-		(+) Stop the Time complementary one pulse.
-		(+) Start the Time complementary one pulse and enable interrupt.
-		(+) Stop the Time complementary one pulse and disable interrupt.
-
-  * @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the TIMER one pulse signal generation on the complementary output.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  * @retval None
-  */
-void timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch)
-{
-	timer_ocn_start(hperh, ch);
-}
-
-/**
-  * @brief  Stops the TIMER one pulse signal generation on the complementary output.
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  * @retval None
-  */
-void timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch)
-{
-	timer_ocn_stop(hperh, ch);
-}
-
-/**
-  * @brief  Starts the TIMER one pulse signal generation on the complementary output.
-  *         in interrupt mode
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  * @retval None
-  */
-void timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
-{
-	timer_ocn_start_by_it(hperh, ch);
-}
-
-/**
-  * @brief  Stops the TIMER one pulse signal generation on the complementary output.
-  *         in interrupt mode
-  * @param  hperh: TIMER handle
-  * @param  ch: TIMER Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  * @retval None
-  */
-void timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
-{
-	timer_ocn_stop_by_it(hperh, ch);
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIMER_Public_Functions_Group11 Peripheral Control functions
- *  @brief    Peripheral Control functions
- *
- * @verbatim
-  ==============================================================================
-                   ##### Peripheral Control functions #####
-  ==============================================================================
- [..]
-   This section provides functions allowing to:
-      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
-      (+) Configure External Clock source.
-      (+) Configure Complementary channels, break features and dead timere.
-      (+) Configure Master and the Slave synchronization.
-      (+) Handle TIMER interrupt.
-      (+) Get TIMER compare register's vale.
-      (+) Configure TIMER interrupt ENABLE/DISABLE.
-      (+) Get TIMER interrupt source status.
-      (+) Get TIMER interrupt flag status.
-      (+) Clear TIMER interrupt flag.
-
-    @endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIMER Output Compare Channels according to the specified
-  *         parameters in the timer_oc_init_t.
-  * @param  hperh: TIMER handle
-  * @param  config: TIMER Output Compare configuration structure
-  * @param  ch: TIMER Channels to be enabled
-  *		This parameter can be one of the following values:
-  *		@arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *		@arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *		@arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *		@arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t* config, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
-	assert_param(IS_TIMER_OC_MODE(config->oc_mode));
-	assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity));
-
-	__LOCK(hperh);
-	hperh->state = TIMER_STATE_BUSY;
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		timer_oc1_set_config(hperh->perh, config);
-		break;
-
-	case TIMER_CHANNEL_2:
-		timer_oc2_set_config(hperh->perh, config);
-		break;
-
-	case TIMER_CHANNEL_3:
-		timer_oc3_set_config(hperh->perh, config);
-		break;
-
-	case TIMER_CHANNEL_4:
-		timer_oc4_set_config(hperh->perh, config);
-		break;
-
-	default:
-		break;
-	}
-
-	hperh->state = TIMER_STATE_READY;
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Initializes the TIMER Input Capture Channels according to the specified
-  *         parameters in the timer_ic_init_t.
-  * @param  hperh: TIMER handle
-  * @param  config: TIMER Input Capture configuration structure
-  * @param  ch: TIMER Channels to be enabled
-  *         This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3 selected
-  *            @arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t* config, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_IC_POLARITY(config->polarity));
-	assert_param(IS_TIMER_IC_SELECT(config->sel));
-	assert_param(IS_TIMER_IC_PSC(config->psc));
-	assert_param(IS_TIMER_IC_FILTER(config->filter));
-
-	__LOCK(hperh);
-	hperh->state = TIMER_STATE_BUSY;
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter);
-		MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS);
-		break;
-
-	case TIMER_CHANNEL_2:
-		timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter);
-		MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS);
-		break;
-
-	case TIMER_CHANNEL_3:
-		timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter);
-		MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS);
-		break;
-
-	case TIMER_CHANNEL_4:
-		timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter);
-		MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS);
-		break;
-
-	default:
-		break;
-	}
-
-	hperh->state = TIMER_STATE_READY;
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Initializes the TIMER One Pulse Channels according to the specified
-  *         parameters in the timer_one_pulse_init_t.
-  * @param  hperh: TIMER handle
-  * @param  config: TIMER One Pulse configuration structure
-  * @param  ch_out: TIMER Channels to be enabled
-  *         This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  * @param  ch_in: TIMER Channels to be enabled
-  *         This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2 selected
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config,
-                                                   timer_channel_t ch_out,  timer_channel_t ch_in)
-{
-	timer_oc_init_t tmp;
-
-	assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_OC_MODE(config->mode));
-	assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity));
-	assert_param(IS_TIMER_OCN_POLARITY(config->ocn_polarity));
-	assert_param(IS_TIMER_OCIDLE_STATE(config->oc_idle));
-	assert_param(IS_TIMER_OCNIDLE_STATE(config->ocn_idle));
-	assert_param(IS_TIMER_IC_POLARITY(config->polarity));
-	assert_param(IS_TIMER_IC_SELECT(config->sel));
-	assert_param(IS_TIMER_IC_FILTER(config->filter));
-
-	if (ch_out == ch_in)
-		return ERROR;
-
-	__LOCK(hperh);
-	hperh->state = TIMER_STATE_BUSY;
-
-	tmp.oc_mode        = config->mode;
-	tmp.pulse          = config->pulse;
-	tmp.oc_polarity    = config->oc_polarity;
-	tmp.ocn_polarity   = config->ocn_polarity;
-	tmp.oc_idle  = config->oc_idle;
-	tmp.ocn_idle = config->ocn_idle;
-
-	switch (ch_out) {
-	case TIMER_CHANNEL_1:
-		timer_oc1_set_config(hperh->perh, &tmp);
-		break;
-	case TIMER_CHANNEL_2:
-		timer_oc2_set_config(hperh->perh, &tmp);
-		break;
-	default:
-		break;
-	}
-
-	switch (ch_in) {
-	case TIMER_CHANNEL_1:
-		timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter);
-		CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS);
-		break;
-
-	case TIMER_CHANNEL_2:
-		timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter);
-		CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS);
-		break;
-	default:
-		break;
-	}
-
-	hperh->state = TIMER_STATE_READY;
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Configures the OCRef clear feature
-  * @param  hperh: TIMER handle
-  * @param  config: pointer to a TIMER_ClearInputConfigTypeDef structure that
-  *         contains the OCREF clear feature and parameters for the TIMER peripheral.
-  * @param  ch: specifies the TIMER Channel
-  *         This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1: TIMER Channel 1
-  *            @arg TIMER_CHANNEL_2: TIMER Channel 2
-  *            @arg TIMER_CHANNEL_3: TIMER Channel 3
-  *            @arg TIMER_CHANNEL_4: TIMER Channel 4
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
-	assert_param(IS_FUNC_STATE(config->state));
-	assert_param(IS_TIMER_CLEAR_INPUT_SOURCE(config->source));
-	assert_param(IS_TIMER_CLEAR_INPUT_POLARITY(config->polarity));
-	assert_param(IS_TIMER_ETR_PSC(config->psc));
-	assert_param(IS_TIMER_IC_FILTER(config->filter));
-
-	if (config->source == TIMER_INPUT_NONE) {
-		timer_etr_set_config(hperh->perh, TIMER_ETR_PSC_DIV1, TIMER_CLK_POLARITY_NO_INV, 0);
-	}
-	else {
-		timer_etr_set_config(hperh->perh, config->psc,
-				(timer_clock_polarity_t)config->polarity, config->filter);
-	}
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS);
-		break;
-
-	case TIMER_CHANNEL_2:
-		MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS);
-		break;
-
-	case TIMER_CHANNEL_3:
-		assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh));
-		MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS);
-		break;
-
-	case TIMER_CHANNEL_4:
-		assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh));
-		MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS);
-		break;
-
-	default:
-		break;
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  Configures the clock source to be used
-  * @param  hperh: TIMER handle
-  * @param  config: pointer to a timer_clock_config_t structure that
-  *         contains the clock source information for the TIMER peripheral.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_CLOCK_SOURCE(config->source));
-	assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity));
-	assert_param(IS_TIMER_ETR_PSC(config->psc));
-	assert_param(IS_TIMER_IC_FILTER(config->filter));
-
-	__LOCK(hperh);
-	hperh->state = TIMER_STATE_BUSY;
-	WRITE_REG(hperh->perh->SMCON, 0x0);
-
-	switch (config->source) {
-	case TIMER_SRC_INTER:
-		CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK);
-		break;
-
-	case TIMER_SRC_ETRMODE1:
-		timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
-		break;
-
-	case TIMER_SRC_ETRMODE2:
-		timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter);
-		SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK);
-		break;
-
-	case TIMER_SRC_TI1:
-		timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
-		break;
-
-	case TIMER_SRC_TI2:
-		timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
-		break;
-
-	case TIMER_SRC_TI1ED:
-		timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
-		break;
-
-	case TIMER_SRC_ITR0:
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
-		break;
-
-	case TIMER_SRC_ITR1:
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
-		break;
-
-	case TIMER_SRC_ITR2:
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
-		break;
-
-	case TIMER_SRC_ITR3:
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS);
-		MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
-		break;
-	default:
-		break;
-	}
-
-	hperh->state = TIMER_STATE_READY;
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
-  *         or a XOR combination between CH1_input, CH2_input & CH3_input
-  * @param  hperh: TIMER handle.
-  * @param  ti1_select: Indicate whether or not channel 1 is connected to the
-  *         output of a XOR gate.
-  *         This parameter can be one of the following values:
-  *            @arg 0: The TIMERx_CH1 pin is connected to TI1 input
-  *            @arg 1: The TIMERx_CH1, CH2 and CH3
-  *            pins are connected to the TI1 input (XOR combination)
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-
-	MODIFY_REG(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK, ti1_select << TIMER_CON2_I1FSEL_POS);
-	return OK;
-}
-
-/**
-  * @brief  Configures the TIMER in Slave mode
-  * @param  hperh: TIMER handle.
-  * @param  config: pointer to a timer_slave_config_t structure that
-  *         contains the selected trigger (internal trigger input, filtered
-  *         timerer input or external trigger input) and the Slave
-  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_SLAVE_MODE(config->mode));
-	assert_param(IS_TIMER_TS(config->input));
-	assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity));
-	assert_param(IS_TIMER_ETR_PSC(config->psc));
-	assert_param(IS_TIMER_IC_FILTER(config->filter));
-
-	__LOCK(hperh);
-	hperh->state = TIMER_STATE_BUSY;
-
-	timer_slave_set_config(hperh, config);
-	timer_interrupt_config(hperh, TIMER_IT_TRIGGER, DISABLE);
-	timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE);
-
-	hperh->state = TIMER_STATE_READY;
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Configures the TIMER in Slave mode in interrupt mode
-  * @param  hperh: TIMER handle.
-  * @param  config: pointer to a timer_slave_config_t structure that
-  *         contains the selected trigger (internal trigger input, filtered
-  *         timerer input or external trigger input) and the ) and the Slave
-  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_SLAVE_MODE(config->mode));
-	assert_param(IS_TIMER_TS(config->input));
-	assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity));
-	assert_param(IS_TIMER_ETR_PSC(config->psc));
-	assert_param(IS_TIMER_IC_FILTER(config->filter));
-
-	__LOCK(hperh);
-	hperh->state = TIMER_STATE_BUSY;
-
-	timer_slave_set_config(hperh, config);
-	timer_interrupt_config(hperh, TIMER_IT_TRIGGER, ENABLE);
-	timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE);
-
-	hperh->state = TIMER_STATE_READY;
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Generate a software event
-  * @param  hperh: TIMER handle
-  * @param  event: specifies the event source.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t timer_generate_event(timer_handle_t *hperh, timer_event_source_t event)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_EVENT_SOURCE(event));
-
-	__LOCK(hperh);
-	hperh->state          = TIMER_STATE_BUSY;
-	WRITE_REG(hperh->perh->SGE, event);
-	hperh->state          = TIMER_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Read the captured value from Capture Compare unit
-  * @param  hperh: TIMER handle.
-  * @param  ch: TIMER Channels to be enabled
-  *         This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1 : TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2 : TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3 : TIMER Channel 3 selected
-  *            @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected
-  * @retval Captured value
-  */
-uint32_t timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch)
-{
-	uint32_t tmp;
-
-	__LOCK(hperh);
-	hperh->state = TIMER_STATE_BUSY;
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		tmp = hperh->perh->CCVAL1;
-		break;
-	case TIMER_CHANNEL_2:
-		tmp = hperh->perh->CCVAL2;
-		break;
-	case TIMER_CHANNEL_3:
-		tmp = hperh->perh->CCVAL3;
-		break;
-	case TIMER_CHANNEL_4:
-		tmp = hperh->perh->CCVAL4;
-		break;
-	default:
-		break;
-	}
-
-	hperh->state = TIMER_STATE_READY;
-	__UNLOCK(hperh);
-	return tmp;
-}
-
-/**
-  * @brief  Sets TIMER output mode.
-  * @param  hperh: TIMER handle.
-  * @param  mode: TIMER output mode.
-  * @param  ch: TIMER Channels.
-  *         This parameter can be one of the following values:
-  *            @arg TIMER_CHANNEL_1 : TIMER Channel 1 selected
-  *            @arg TIMER_CHANNEL_2 : TIMER Channel 2 selected
-  *            @arg TIMER_CHANNEL_3 : TIMER Channel 3 selected
-  *            @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected
-  * @retval None
-  */
-void timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch)
-{
-	assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_OC_MODE(mode));
-	assert_param(IS_TIMER_CHANNELS(ch));
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS);
-		break;
-	case TIMER_CHANNEL_2:
-		MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS);
-		break;
-	case TIMER_CHANNEL_3:
-		MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS);
-		break;
-	case TIMER_CHANNEL_4:
-		MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS);
-		break;
-	default:
-		break;
-	}
-
-	return;
-}
-
-/**
-  * @brief  Configure the channel in commutation event.
-  * @param  hperh: TIMER handel
-  * @param  config: Parameters of the channel.
-  * @retval None
-  */ 
-void timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config)
-{
-	uint32_t cm1, cm2, cce;
-
-	assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh));
-	assert_param(IS_FUNC_STATE(config->ch[0].en));
-	assert_param(IS_FUNC_STATE(config->ch[0].n_en));
-	assert_param(IS_TIMER_OC_MODE(config->ch[0].mode));
-	assert_param(IS_FUNC_STATE(config->ch[1].en));
-	assert_param(IS_FUNC_STATE(config->ch[1].n_en));
-	assert_param(IS_TIMER_OC_MODE(config->ch[1].mode));
-	assert_param(IS_FUNC_STATE(config->ch[2].en));
-	assert_param(IS_FUNC_STATE(config->ch[2].n_en));
-	assert_param(IS_TIMER_OC_MODE(config->ch[2].mode));
-
-	TIMER_MOE_DISABLE(hperh);
-	TIMER_DISABLE(hperh);
-
-	cm1 = hperh->perh->CHMR1;
-	cm2 = hperh->perh->CHMR2;
-	cce = hperh->perh->CCEP;
-
-	MODIFY_REG(cm1, (0x7 << 4), (config->ch[0].mode << 4));
-	MODIFY_REG(cm1, (0x7 << 12), (config->ch[1].mode << 12));
-	MODIFY_REG(cm2, (0x7 << 4), (config->ch[2].mode << 4));
-	MODIFY_REG(cce, (0x1 << 0), (config->ch[0].en << 0));
-	MODIFY_REG(cce, (0x1 << 2), (config->ch[0].n_en << 2));
-	MODIFY_REG(cce, (0x1 << 4), (config->ch[1].en << 4));
-	MODIFY_REG(cce, (0x1 << 6), (config->ch[1].n_en << 6));
-	MODIFY_REG(cce, (0x1 << 8), (config->ch[2].en << 8));
-	MODIFY_REG(cce, (0x1 << 10), (config->ch[2].n_en << 10));
-
-	WRITE_REG(hperh->perh->CHMR1, cm1);
-	WRITE_REG(hperh->perh->CHMR2, cm2);
-	WRITE_REG(hperh->perh->CCEP, cce);
-
-	TIMER_MOE_ENABLE(hperh);
-	TIMER_ENABLE(hperh);
-	return;
-}
-
-/**
-  * @brief  Configure the TIMER commutation event sequence.
-  * @param  hperh: TIMER handel
-  * @param  ts: the internal trigger corresponding to the timerer interfacing
-  *         with the hall sensor.
-  *         This parameter can be one of the following values:
-  *           @arg TIMER_TS_ITR0
-  *           @arg TIMER_TS_ITR1
-  *           @arg TIMER_TS_ITR2
-  *           @arg TIMER_TS_ITR3
-  * @param  trgi: the commutation event source.
-  *         This parameter can be one of the following values:
-  *           @arg ENABLE: Commutation event source is TRGI
-  *           @arg DISABLE: Commutation event source is set by software using the COMG bit
-  * @retval None
-  */ 
-void timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi)
-{
-	assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_TS(ts));
-	assert_param(IS_FUNC_STATE(trgi));
-
-	MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ts << TIMER_SMCON_TSSEL_POSS);
-	SET_BIT(hperh->perh->CON2, TIMER_CON2_CCPCEN_MSK);
-	MODIFY_REG(hperh->perh->CON2, TIMER_CON2_CCUSEL_MSK, trgi << TIMER_CON2_CCUSEL_POS);
-
-	return;
-}
-
-/**
-  * @brief  Configure the TIMER commutation event sequence with interrupt.
-  * @param  hperh: TIMER handel
-  * @param  ts: the internal trigger corresponding to the timerer interfacing
-  *         with the hall sensor.
-  *         This parameter can be one of the following values:
-  *           @arg TIMER_TS_ITR0
-  *           @arg TIMER_TS_ITR1
-  *           @arg TIMER_TS_ITR2
-  *           @arg TIMER_TS_ITR3
-  * @param  trgi: the commutation event source.
-  *         This parameter can be one of the following values:
-  *           @arg ENABLE: Commutation event source is TRGI
-  *           @arg DISABLE: Commutation event source is set by software using the COMG bit
-  * @retval None
-  */
-void timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi)
-{
-	timer_com_event_config(hperh, ts, trgi);
-	timer_interrupt_config(hperh, TIMER_IT_COM, ENABLE);
-}
-
-/**
-  * @brief  Configure the break, dead timere, lock level state.
-  * @param  hperh: TIMER handle
-  * @param  config: Pointer to the timer_break_dead_timere_t structure.
-  * @retval None
-  */ 
-void timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config)
-{
-	uint32_t tmp;
-
-	assert_param(IS_TIMER_BREAK_INSTANCE(hperh->perh));
-	assert_param(IS_FUNC_STATE(config->off_run));
-	assert_param(IS_FUNC_STATE(config->off_idle));
-	assert_param(IS_TIMER_CLOCK_LEVEL(config->lock_level));
-	assert_param(IS_TIMER_DEAD_TIMERE(config->dead_time));
-	assert_param(IS_FUNC_STATE(config->break_state));
-	assert_param(IS_TIMER_BREAK_POLARITY(config->polarity));
-	assert_param(IS_FUNC_STATE(config->auto_out));
-
-	tmp = READ_REG(hperh->perh->BDCFG);
-	MODIFY_REG(tmp, TIMER_BDCFG_OFFSSR_MSK, config->off_run << TIMER_BDCFG_OFFSSR_POS);
-	MODIFY_REG(tmp, TIMER_BDCFG_OFFSSI_MSK, config->off_idle << TIMER_BDCFG_OFFSSI_POS);
-	MODIFY_REG(tmp, TIMER_BDCFG_LOCKLVL_MSK, config->lock_level << TIMER_BDCFG_LOCKLVL_POSS);
-	MODIFY_REG(tmp, TIMER_BDCFG_DT_MSK, config->dead_time << TIMER_BDCFG_DT_POSS);
-	MODIFY_REG(tmp, TIMER_BDCFG_BRKEN_MSK, config->break_state << TIMER_BDCFG_BRKEN_POS);
-	MODIFY_REG(tmp, TIMER_BDCFG_BRKP_MSK, config->polarity << TIMER_BDCFG_BRKP_POS);
-	MODIFY_REG(tmp, TIMER_BDCFG_AOEN_MSK, config->auto_out << TIMER_BDCFG_AOEN_POS);
-	WRITE_REG(hperh->perh->BDCFG, tmp);
-
-	hperh->state = TIMER_STATE_READY;
-	return;
-}
-
-/**
-  * @brief  Configure the master mode
-  * @param  hperh: TIMER handle
-  * @param  config: Pointer to the timer_master_config_t structure.
-  * @retval None
-  */ 
-void timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_MASTER_MODE_SEL(config->sel));
-	assert_param(IS_FUNC_STATE(config->master_en));
-
-	hperh->state = TIMER_STATE_BUSY;
-	MODIFY_REG(hperh->perh->CON2, TIMER_CON2_TRGOSEL_MSK, config->sel << TIMER_CON2_TRGOSEL_POSS);
-	MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_MSCFG_MSK, config->master_en << TIMER_SMCON_MSCFG_POS);
-	hperh->state = TIMER_STATE_READY;
-
-	return;
-}
-
-/**
-  * @brief  This function handles TIMER interrupts requests.
-  * @param  hperh: TIMER handle
-  * @retval None
-  */
-void timer_irq_handle(timer_handle_t *hperh)
-{
-	uint32_t reg = hperh->perh->IFM;
-
-	/* Capture or compare 1 event */
-	if (READ_BIT(reg, TIMER_FLAG_CC1)) {
-		timer_clear_flag_status(hperh, TIMER_FLAG_CC1);
-		hperh->ch = TIMER_ACTIVE_CHANNEL_1;
-
-		/* Input capture event */
-		if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK)) {
-			if (hperh->capture_cbk)
-				hperh->capture_cbk(hperh);
-		}
-		else {	/* Output compare event */
-			if (hperh->delay_elapse_cbk)
-				hperh->delay_elapse_cbk(hperh);
-			if (hperh->pwm_pulse_finish_cbk)
-				hperh->pwm_pulse_finish_cbk(hperh);
-		}
-
-		hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
-	}
-	/* Capture or compare 2 event */
-	if (READ_BIT(reg, TIMER_FLAG_CC2)) {
-		timer_clear_flag_status(hperh, TIMER_FLAG_CC2);
-		hperh->ch = TIMER_ACTIVE_CHANNEL_2;
-
-		/* Input capture event */
-		if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK)) {
-			if (hperh->capture_cbk)
-				hperh->capture_cbk(hperh);
-		}
-		else {	/* Output compare event */
-			if (hperh->delay_elapse_cbk)
-				hperh->delay_elapse_cbk(hperh);
-			if (hperh->pwm_pulse_finish_cbk)
-				hperh->pwm_pulse_finish_cbk(hperh);
-		}
-
-		hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
-	}
-	/* Capture or compare 3 event */
-	if (READ_BIT(reg, TIMER_FLAG_CC3)) {
-		timer_clear_flag_status(hperh, TIMER_FLAG_CC3);
-		hperh->ch = TIMER_ACTIVE_CHANNEL_3;
-
-		/* Input capture event */
-		if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC3SSEL_MSK)) {
-			if (hperh->capture_cbk)
-				hperh->capture_cbk(hperh);
-		}
-		else {	/* Output compare event */
-			if (hperh->delay_elapse_cbk)
-				hperh->delay_elapse_cbk(hperh);
-			if (hperh->pwm_pulse_finish_cbk)
-				hperh->pwm_pulse_finish_cbk(hperh);
-		}
-
-		hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
-	}
-	/* Capture or compare 4 event */
-	if (READ_BIT(reg, TIMER_FLAG_CC4)) {
-		timer_clear_flag_status(hperh, TIMER_FLAG_CC4);
-		hperh->ch = TIMER_ACTIVE_CHANNEL_4;
-
-		/* Input capture event */
-		if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC4SSEL_MSK)) {
-			if (hperh->capture_cbk)
-				hperh->capture_cbk(hperh);
-		}
-		else {	/* Output compare event */
-			if (hperh->delay_elapse_cbk)
-				hperh->delay_elapse_cbk(hperh);
-			if (hperh->pwm_pulse_finish_cbk)
-				hperh->pwm_pulse_finish_cbk(hperh);
-		}
-
-		hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
-	}
-
-	/* TIMER Update event */
-	if (READ_BIT(reg, TIMER_FLAG_UPDATE)) {
-		timer_clear_flag_status(hperh, TIMER_FLAG_UPDATE);
-
-		if (hperh->period_elapse_cbk)
-			hperh->period_elapse_cbk(hperh);
-	}
-
-	/* TIMER Break input event */
-	if (READ_BIT(reg, TIMER_FLAG_BREAK)) {
-		timer_clear_flag_status(hperh, TIMER_FLAG_BREAK);
-
-		if (hperh->break_cbk)
-			hperh->break_cbk(hperh);
-	}
-
-	/* TIMER Trigger detection event */
-	if (READ_BIT(reg, TIMER_FLAG_TRIGGER)) {
-		timer_clear_flag_status(hperh, TIMER_FLAG_TRIGGER);
-
-		if (hperh->trigger_cbk)
-			hperh->trigger_cbk(hperh);
-	}
-
-	/* TIMER commutation event */
-	if (READ_BIT(reg, TIMER_FLAG_COM)) {
-		timer_clear_flag_status(hperh, TIMER_FLAG_COM);
-
-		if (hperh->com_cbk)
-			hperh->com_cbk(hperh);
-	}
-
-	return;
-}
-
-/**
-  * @brief  Configure DMA request source.
-  * @param  hperh: TIMER handle
-  * @param  req: DMA request source.
-  * @param  state: New state of the specified DMA request.
-  * @retval None
-  */
-void timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_DMA_REQ(req));
-	assert_param(IS_FUNC_STATE(state));
-
-	if (state == ENABLE)
-		SET_BIT(hperh->perh->DIER, req);
-	else
-		CLEAR_BIT(hperh->perh->DIER, req);
-
-	return;
-}
-
-/**
-  * @brief  Enable/disable the specified TIMER interrupts.
-  * @param  hperh: Pointer to a timer_handle_t structure.
-  * @param  it: Specifies the timer interrupt sources to be enabled or disabled.
-  *         This parameter can be one of the @ref timer_it_t.
-  * @param  state: New state of the specified TIMER interrupts.
-  *         This parameter can be:
-  *             @arg ENABLE
-  *             @arg DISABLE
-  * @retval None
-  */
-void timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_IT(it));
-	assert_param(IS_FUNC_STATE(state));
-
-	if (state == ENABLE)
-		SET_BIT(hperh->perh->DIER, it);
-	else
-		CLEAR_BIT(hperh->perh->DIER, it);
-
-	return;
-}
-
-/**
-  * @brief  Get the status of TIMER interrupt source.
-  * @param  hperh: Pointer to a timer_handle_t structure.
-  * @param  it: Specifies the TIMER interrupt source.
-  *         This parameter can be one of the @ref timer_it_t.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-it_status_t timer_get_it_status(timer_handle_t *hperh, timer_it_t it)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_IT(it));
-
-	if (hperh->perh->DIVS & it)
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Get the status of TIMER interrupt flag.
-  * @param  hperh: Pointer to a timer_handle_t structure.
-  * @param  flag: Specifies the TIMER interrupt flag.
-  *         This parameter can be one of the @ref timer_flag_t.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-flag_status_t timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_FLAG(flag));
-
-	if (hperh->perh->RIF & flag)
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Clear the TIMER interrupt flag.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  flag: Specifies the TIMER interrupt flag.
-  *         This parameter can be one of the @ref timer_flag_t.
-  * @retval None
-  */
-void timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag)
-{
-	assert_param(IS_TIMER_INSTANCE(hperh->perh));
-	assert_param(IS_TIMER_FLAG(flag));
-
-	hperh->perh->ICR = flag;
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIMER_Public_Functions_Group12 Peripheral State functions
-  * @brief    Peripheral State functions
-  *
-  * @verbatim
-  ==============================================================================
-                        ##### Peripheral State functions #####
-  ==============================================================================
-    [..]
-    This subsection permit to get in run-timere the status of the peripheral
-    and the data flow.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the TIMER Base state
-  * @param  hperh: TIMER handle
-  * @retval TIMER peripheral state
-  */
-timer_state_t timer_get_state(timer_handle_t *hperh)
-{
-	return hperh->state;
-}
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/** @addtogroup TIMER_Private_Functions
-  * @{
-  */
-
-#ifdef ALD_DMA
-/**
-  * @brief  TIMER DMA out compare complete callback.
-  * @param  arg: pointer to TIMER handle.
-  * @retval None
-  */
-void timer_dma_oc_cplt(void *arg)
-{
-	timer_handle_t *hperh = (timer_handle_t *)arg;
-
-	if (hperh->delay_elapse_cbk)
-		hperh->delay_elapse_cbk(hperh);
-
-	if (hperh->pwm_pulse_finish_cbk)
-		hperh->pwm_pulse_finish_cbk(hperh);
-
-	hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
-	return;
-}
-
-/**
-  * @brief  TIMER DMA Capture complete callback.
-  * @param  arg: pointer to TIMER handle.
-  * @retval None
-  */
-void timer_dma_capture_cplt(void *arg)
-{
-	timer_handle_t *hperh = (timer_handle_t *)arg;
-
-	if (hperh->capture_cbk)
-		hperh->capture_cbk(hperh);
-
-	hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
-	return;
-}
-
-/**
-  * @brief  TIMER DMA Period Elapse complete callback.
-  * @param  arg: pointer to TIMER handle.
-  * @retval None
-  */
-void timer_dma_period_elapse_cplt(void *arg)
-{
-	timer_handle_t *hperh = (timer_handle_t *)arg;
-
-	if (hperh->period_elapse_cbk)
-		hperh->period_elapse_cbk(hperh);
-
-	hperh->state = TIMER_STATE_READY;
-	return;
-}
-
-/**
-  * @brief  TIMER DMA error callback
-  * @param  arg: pointer to TIMER handle.
-  * @retval None
-  */
-void timer_dma_error(void *arg)
-{
-	timer_handle_t *hperh = (timer_handle_t *)arg;
-
-	hperh->state = TIMER_STATE_READY;
-	if (hperh->error_cbk)
-		hperh->error_cbk(hperh);
-
-	return;
-}
-#endif
-
-/**
-  * @brief  Time Base configuration
-  * @param  TIMERx: TIMER periheral
-  * @param  init: TIMER Base configuration structure
-  * @retval None
-  */
-static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init)
-{
-	assert_param(IS_TIMER_COUNTER_MODE(init->mode));
-	assert_param(IS_TIMER_CLOCK_DIVISION(init->clk_div));
-
-	if (init->mode == TIMER_CNT_MODE_UP || init->mode == TIMER_CNT_MODE_DOWN) {
-		CLEAR_BIT(TIMERx->CON1, TIMER_CON1_CMSEL_MSK);
-		MODIFY_REG(TIMERx->CON1, TIMER_CON1_DIRSEL_MSK, init->mode << TIMER_CON1_DIRSEL_POS);
-	}
-	else {
-		MODIFY_REG(TIMERx->CON1, TIMER_CON1_CMSEL_MSK, (init->mode - 1) << TIMER_CON1_CMSEL_POSS);
-	}
-
-	if (IS_TIMER_CLOCK_DIVISION_INSTANCE(TIMERx))
-		MODIFY_REG(TIMERx->CON1, TIMER_CON1_DFCKSEL_MSK, init->clk_div << TIMER_CON1_DFCKSEL_POSS);
-
-	WRITE_REG(TIMERx->AR, init->period);
-	WRITE_REG(TIMERx->PRES, init->prescaler);
-
-	if (IS_TIMER_REPETITION_COUNTER_INSTANCE(TIMERx))
-		WRITE_REG(TIMERx->REPAR, init->re_cnt);
-
-	return;
-}
-
-/**
-  * @brief  Time Ouput Compare 1 configuration
-  * @param  TIMERx: Select the TIMER peripheral
-  * @param  oc_config: The ouput configuration structure
-  * @retval None
-  */
-static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
-{
-	CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK);
-	CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK);
-	CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK);
-	MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH1OMOD_POSS);
-	MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC1POL_POS);
-
-	if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_1)) {
-		assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity));
-		MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC1NPOL_POS);
-		CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK);
-	}
-
-	if (IS_TIMER_BREAK_INSTANCE(TIMERx)) {
-		assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle));
-		assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle));
-
-		MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1_MSK, oc_config->oc_idle << TIMER_CON2_OISS1_POS);
-		MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS1N_POS);
-	}
-
-	WRITE_REG(TIMERx->CCVAL1, oc_config->pulse);
-}
-
-/**
-  * @brief  Time Ouput Compare 2 configuration
-  * @param  TIMERx: Select the TIMER peripheral
-  * @param  oc_config: The ouput configuration structure
-  * @retval None
-  */
-static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
-{
-	CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK);
-	CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK);
-	CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK);
-	MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH2OMOD_POSS);
-	MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC2POL_POS);
-
-	if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_2)) {
-		assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity));
-		MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC2NPOL_POS);
-		CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK);
-	}
-
-	if (IS_TIMER_BREAK_INSTANCE(TIMERx)) {
-		assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle));
-		assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle));
-
-		MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2_MSK, oc_config->oc_idle << TIMER_CON2_OISS2_POS);
-		MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS2N_POS);
-	}
-
-	WRITE_REG(TIMERx->CCVAL2, oc_config->pulse);
-}
-
-/**
-  * @brief  Time Ouput Compare 3 configuration
-  * @param  TIMERx: Select the TIMER peripheral
-  * @param  oc_config: The ouput configuration structure
-  * @retval None
-  */
-static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
-{
-	CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK);
-	CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK);
-	CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK);
-	MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH3OMOD_POSS);
-	MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC3POL_POS);
-
-	if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_3)) {
-		assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity));
-		MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC3NPOL_POS);
-		CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK);
-	}
-
-	if (IS_TIMER_BREAK_INSTANCE(TIMERx)) {
-		assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle));
-		assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle));
-
-		MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3_MSK, oc_config->oc_idle << TIMER_CON2_OISS3_POS);
-		MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS3N_POS);
-	}
-
-	WRITE_REG(TIMERx->CCVAL3, oc_config->pulse);
-}
-
-/**
-  * @brief  Time Ouput Compare 4 configuration
-  * @param  TIMERx: Select the TIMER peripheral
-  * @param  oc_config: The ouput configuration structure
-  * @retval None
-  */
-static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
-{
-	CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK);
-	CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK);
-	CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK);
-	MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH4OMOD_POSS);
-	MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC4POL_POS);
-
-	if (IS_TIMER_BREAK_INSTANCE(TIMERx)) {
-		assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle));
-		MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS4_MSK, oc_config->oc_idle << TIMER_CON2_OISS4_POS);
-	}
-
-	WRITE_REG(TIMERx->CCVAL4, oc_config->pulse);
-}
-
-/**
-  * @brief  Enables or disables the TIMER Capture Compare Channel x.
-  * @param  TIMERx: Select the TIMER peripheral
-  * @param  ch: specifies the TIMER Channel
-  *		This parameter can be one of the following values:
-  *		@arg TIMER_CHANNEL_1: TIMER Channel 1
-  *		@arg TIMER_CHANNEL_2: TIMER Channel 2
-  *		@arg TIMER_CHANNEL_3: TIMER Channel 3
-  *		@arg TIMER_CHANNEL_4: TIMER Channel 4
-  * @param  state: specifies the TIMER Channel CCxE bit new state.
-  * @retval None
-  */
-static void timer_ccx_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state)
-{
-	assert_param(IS_TIMER_CC2_INSTANCE(TIMERx));
-	assert_param(IS_TIMER_CHANNELS(ch));
-
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS);
-		break;
-
-	case TIMER_CHANNEL_2:
-		MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS);
-		break;
-
-	case TIMER_CHANNEL_3:
-		MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS);
-		break;
-
-	case TIMER_CHANNEL_4:
-		MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS);
-		break;
-
-	default:
-		break;
-	}
-}
-/**
-  * @brief  Enables or disables the TIMER Capture Compare Channel xN.
-  * @param  TIMERx: Select the TIMER peripheral
-  * @param  ch: specifies the TIMER Channel
-  *		This parameter can be one of the following values:
-  *		@arg TIMER_CHANNEL_1: TIMER Channel 1
-  *		@arg TIMER_CHANNEL_2: TIMER Channel 2
-  *		@arg TIMER_CHANNEL_3: TIMER Channel 3
-  * @param  state: specifies the TIMER Channel CCxNE bit new state.
-  * @retval None
-  */
-static void timer_ccxn_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state)
-{
-	switch (ch) {
-	case TIMER_CHANNEL_1:
-		MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK, state << TIMER_CCEP_CC1NEN_POS);
-		break;
-
-	case TIMER_CHANNEL_2:
-		MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK, state << TIMER_CCEP_CC2NEN_POS);
-		break;
-
-	case TIMER_CHANNEL_3:
-		MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK, state << TIMER_CCEP_CC3NEN_POS);
-		break;
-
-	default:
-		break;
-	}
-
-}
-
-/**
-  * @brief  Configure the TI1 as Input.
-  * @param  TIMERx: Select the TIMER peripheral.
-  * @param  polarity: The Input Polarity.
-  * @param  sel: specifies the input to be used.
-  * @param  filter: Specifies the Input Capture Filter.
-  *         This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity,
-                                   timer_ic_select_t sel, uint32_t filter)
-{
-	CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK);
-	MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, sel << TIMER_CHMR1_CC1SSEL_POSS);
-	MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS);
-	MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC1POL_POS);
-	MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS);
-
-	return;
-}
-
-/**
-  * @brief  Configure the Polarity and Filter for TI1.
-  * @param  TIMERx: Select the TIMER peripheral.
-  * @param  polarity: The Input Polarity.
-  * @param  filter: Specifies the Input Capture Filter.
-  *         This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter)
-{
-	MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS);
-	MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC1POL_POS);
-	MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS);
-
-	return;
-}
-
-/**
-  * @brief  Configure the TI2 as Input.
-  * @param  TIMERx: Select the TIMER peripheral.
-  * @param  polarity: The Input Polarity.
-  * @param  sel: specifies the input to be used.
-  * @param  filter: Specifies the Input Capture Filter.
-  *         This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity,
-                                   timer_ic_select_t sel, uint32_t filter)
-{
-	CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK);
-	MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, sel << TIMER_CHMR1_CC2SSEL_POSS);
-	MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS);
-	MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC2POL_POS);
-	MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS);
-
-	return;
-}
-
-/**
-  * @brief  Configure the Polarity and Filter for TI2.
-  * @param  TIMERx: Select the TIMER peripheral.
-  * @param  polarity: The Input Polarity.
-  * @param  filter: Specifies the Input Capture Filter.
-  *         This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter)
-{
-	MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS);
-	MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC2POL_POS);
-	MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS);
-	return;
-}
-
-/**
-  * @brief  Configure the TI3 as Input.
-  * @param  TIMERx: Select the TIMER peripheral.
-  * @param  polarity: The Input Polarity.
-  * @param  sel: specifies the input to be used.
-  * @param  filter: Specifies the Input Capture Filter.
-  *         This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity,
-                                   timer_ic_select_t sel, uint32_t filter)
-{
-	CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK);
-	MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, sel << TIMER_CHMR2_CC3SSEL_POSS);
-	MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, filter << TIMER_CHMR2_I3FLT_POSS);
-	MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC3POL_POS);
-	MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC3NPOL_POS);
-
-	return;
-}
-
-/**
-  * @brief  Configure the TI4 as Input.
-  * @param  TIMERx: Select the TIMER peripheral.
-  * @param  polarity: The Input Polarity.
-  * @param  sel: specifies the input to be used.
-  * @param  filter: Specifies the Input Capture Filter.
-  *         This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity,
-                                   timer_ic_select_t sel, uint32_t filter)
-{
-	CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK);
-	MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, sel << TIMER_CHMR2_CC4SSEL_POSS);
-	MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, filter << TIMER_CHMR2_I4FLT_POSS);
-	MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC4POL_POS);
-
-	return;
-}
-
-/**
-  * @brief  Configures the TIMERx External Trigger (ETR).
-  * @param  TIMERx: Select the TIMER peripheral
-  * @param  psc: The external Trigger Prescaler.
-  * @param  polarity: The external Trigger Polarity.
-  * @param  filter: External Trigger Filter.
-  *         This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-static void timer_etr_set_config(TIMER_TypeDef* TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter)
-{
-	MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETFLT_MSK, filter << TIMER_SMCON_ETFLT_POSS);
-	MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPSEL_MSK, psc << TIMER_SMCON_ETPSEL_POSS);
-	CLEAR_BIT(TIMERx->SMCON, TIMER_SMCON_ECM2EN_MSK);
-	MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPOL_MSK, polarity << TIMER_SMCON_ETPOL_POS);
-	return;
-}
-
-/**
-  * @brief  Time Slave configuration
-  * @param  hperh: pointer to a timer_handle_t structure that contains
-  *         the configuration information for TIMER module.
-  * @param  config: The slave configuration structure
-  * @retval None
-  */
-static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config)
-{
-	MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, config->input << TIMER_SMCON_TSSEL_POSS);
-	MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS);
-
-	switch (config->input) {
-	case TIMER_TS_ETRF:
-		timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter);
-		break;
-
-	case TIMER_TS_TI1F_ED:
-		CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK);
-		MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS);
-		break;
-
-	case TIMER_TS_TI1FP1:
-		timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter);
-		break;
-
-	case TIMER_TS_TI2FP2:
-		timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter);
-		break;
-
-	default:
-		break;
-	}
-}
-/**
-  * @}
-  */
-#endif /* ALD_TIMER */
-/**
-  * @}
-  */
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_trng.c

@@ -1,220 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_trng.c
-  * @brief   TRNG module driver.
-  *
-  * @version V1.0
-  * @date    04 Dec 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
-
-#include "ald_trng.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup TRNG TRNG
-  * @brief TRNG module driver
-  * @{
-  */
-#ifdef ALD_TRNG
-
-/** @defgroup TRNG_Public_Functions TRNG Public Functions
-  * @{
-  */
-
-/** @addtogroup TRNG_Public_Functions_Group1 Initialization functions
-  * @brief Initialization functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### Initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to initialize the TRNG:
-      (+) This parameters can be configured:
-        (++) Word Width
-        (++) Seed Type
-        (++) Seed
-        (++) Start Time
-        (++) Adjust parameter
-
-    @endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Initializes the TRNG according to the specified
-  *         parameters in the trng_init_t.
-  * @param  init: Pointer to a trng_init_t structure that contains
-  *         the configuration information.
-  * @retval None
-  */
-void trng_init(trng_init_t *init)
-{
-	assert_param(IS_TRNG_DATA_WIDTH(init->data_width));
-	assert_param(IS_TRNG_SEED_TYPE(init->seed_type));
-	assert_param(IS_TRNG_ADJC(init->adjc));
-
-	SET_BIT(TRNG->CR, TRNG_CR_TRNGSEL_MSK);
-	MODIFY_REG(TRNG->CR, TRNG_CR_DSEL_MSK, (init->data_width) << TRNG_CR_DSEL_POSS);
-	MODIFY_REG(TRNG->CR, TRNG_CR_SDSEL_MSK, (init->seed_type) << TRNG_CR_SDSEL_POSS);
-	MODIFY_REG(TRNG->CR, TRNG_CR_ADJC_MSK, (init->adjc) << TRNG_CR_ADJC_POSS);
-
-	if (init->adjc == 0) {
-		MODIFY_REG(TRNG->CR, TRNG_CR_ADJC_MSK, (0) << TRNG_CR_ADJC_POSS);
-	}
-	else {
-		MODIFY_REG(TRNG->CR, TRNG_CR_ADJC_MSK, (1) << TRNG_CR_ADJC_POSS);
-	}
-
-	WRITE_REG(TRNG->SEED, init->seed);
-	MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (init->t_start) << TRNG_CFGR_TSTART_POSS);
-	MODIFY_REG(TRNG->CR, TRNG_CR_POSTEN_MSK, (init->posten) << TRNG_CR_POSTEN_MSK);
-
-	return;
-}
-/**
-  * @}
-  */
-
-/** @addtogroup TRNG_Public_Functions_Group2 Peripheral Control functions
-  * @brief Peripheral Control functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### Peripheral Control functions #####
-  ==============================================================================
-  [..]  This section provides functions allowing to:
-    (+) trng_get_result() API can Get the result.
-    (+) trng_interrupt_config() API can be helpful to configure TRNG interrupt source.
-    (+) trng_get_it_status() API can get the status of interrupt source.
-    (+) trng_get_status() API can get the status of SR register.
-    (+) trng_get_flag_status() API can get the status of interrupt flag.
-    (+) trng_clear_flag_status() API can clear interrupt flag.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Get the result.
-  * @retval The resultl
-  */
-uint32_t trng_get_result(void)
-{
-	return (uint32_t)TRNG->DR;
-}
-
-/**
-  * @brief  Enable/disable the specified interrupts.
-  * @param  it: Specifies the interrupt sources to be enabled or disabled.
-  *         This parameter can be one of the @ref trng_it_t.
-  * @param  state: New state of the specified interrupts.
-  *         This parameter can be:
-  *             @arg ENABLE
-  *             @arg DISABLE
-  * @retval None
-  */
-void trng_interrupt_config(trng_it_t it, type_func_t state)
-{
-	assert_param(IS_TRNG_IT(it));
-	assert_param(IS_FUNC_STATE(state));
-
-	if (state)
-		SET_BIT(TRNG->IER, it);
-	else
-		CLEAR_BIT(TRNG->IER, it);
-
-	return;
-}
-
-/**
-  * @brief  Get the status of SR register.
-  * @param  status: Specifies the TRNG status type.
-  *         This parameter can be one of the @ref trng_status_t.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-flag_status_t trng_get_status(trng_status_t status)
-{
-	assert_param(IS_TRNG_STATUS(status));
-
-	if (READ_BIT(TRNG->SR, status))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Get the status of interrupt source.
-  * @param  it: Specifies the interrupt source.
-  *         This parameter can be one of the @ref trng_it_t.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-it_status_t trng_get_it_status(trng_it_t it)
-{
-	assert_param(IS_TRNG_IT(it));
-
-	if (READ_BIT(TRNG->IER, it))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Get the status of interrupt flag.
-  * @param  flag: Specifies the interrupt flag.
-  *         This parameter can be one of the @ref trng_flag_t.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-flag_status_t trng_get_flag_status(trng_flag_t flag)
-{
-	assert_param(IS_TRNG_FLAG(flag));
-
-	if (READ_BIT(TRNG->IFR, flag))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Clear the interrupt flag.
-  * @param  flag: Specifies the interrupt flag.
-  *         This parameter can be one of the @ref trng_flag_t.
-  * @retval None
-  */
-void trng_clear_flag_status(trng_flag_t flag)
-{
-	assert_param(IS_TRNG_FLAG(flag));
-	WRITE_REG(TRNG->IFCR, flag);
-
-	return;
-}
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#endif /* ALD_TRNG */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_uart.c

@@ -1,1182 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_uart.c
-  * @brief   UART module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
-  *           + Initialization and Configuration functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Errors functions
-  *
-  * @version V1.0
-  * @date    21 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  * @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The UART driver can be used as follows:
-
-    (#) Declare a uart_handle_t handle structure.
-
-    (#) Initialize the UART low level resources:
-        (##) Enable the UARTx interface clock.
-        (##) UART pins configuration:
-            (+++) Enable the clock for the UART GPIOs.
-            (+++) Configure the UART pins (TX as alternate function pull-up, RX as alternate function Input).
-        (##) NVIC configuration if you need to use interrupt process (uart_send_by_it()
-             and uart_recv_by_it() APIs):
-            (+++) Configure the uart interrupt priority.
-            (+++) Enable the NVIC UART IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (uart_send_by_dma()
-             and uart_recv_by_dma() APIs):
-            (+++) Select the DMA Tx/Rx channel.
-            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
-
-    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
-        flow control and Mode(Receiver/Transmitter) in the hperh Init structure.
-
-    (#) Initialize the UART registers by calling the uart_init() API.
-
-     [..]
-        Three operation modes are available within this driver:
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]
-       (+) Send an amount of data in blocking mode using uart_send()
-       (+) Receive an amount of data in blocking mode using uart_recv()
-
-     *** Interrupt mode IO operation ***
-     ===================================
-     [..]
-       (+) Send an amount of data in non blocking mode using uart_send_by_it()
-       (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can
-           add his own code by customization of function pointer hperh->tx_cplt_cbk()
-       (+) Receive an amount of data in non blocking mode using uart_recv_by_it()
-       (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can
-           add his own code by customization of function pointer hperh->rx_cplt_cbk()
-       (+) In case of transfer Error, hperh->error_cbk() function is executed and user can
-           add his own code by customization of function pointer hperh->error_cbk()
-
-     *** DMA mode IO operation ***
-     ==============================
-     [..]
-       (+) Send an amount of data in non blocking mode (DMA) using uart_send_by_dma()
-       (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can
-           add his own code by customization of function pointer hperh->tx_cplt_cbk()
-       (+) Receive an amount of data in non blocking mode (DMA) using uart_recv_by_dma()
-       (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can
-           add his own code by customization of function pointer hperh->rx_cplt_cbk()
-       (+) In case of transfer Error, hperh->error_cbk() function is executed and user can
-           add his own code by customization of function pointer hperh->error_cbk()
-       (+) Pause the DMA Transfer using uart_dma_pause()
-       (+) Resume the DMA Transfer using uart_dma_resume()
-       (+) Stop the DMA Transfer using uart_dma_stop()
-
-    @endverbatim
-  ******************************************************************************
-  */
-
-#include "ald_uart.h"
-#include "ald_cmu.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup UART UART
-  * @brief UART module driver
-  * @{
-  */
-#ifdef ALD_UART
-
-/** @defgroup UART_Private_Functions   UART Private Functions
-  *  @brief   UART Private functions
-  * @{
-  */
-#ifdef ALD_DMA
-/**
-  * @brief  DMA uart transmit process complete callback.
-  * @param  arg: Pointer to a uart_handle_t structure.
-  * @retval None
-  */
-static void uart_dma_send_cplt(void *arg)
-{
-	uart_handle_t *hperh = (uart_handle_t *)arg;
-
-	if (hperh->state == UART_STATE_BUSY_TX)
-		uart_dma_req_config(hperh, DISABLE);
-
-	hperh->tx_count = 0;
-	uart_interrupt_config(hperh, UART_IT_TC, ENABLE);
-	return;
-}
-
-/**
-  * @brief  DMA uart receive process complete callback.
-  * @param  arg: Pointer to a uart_handle_t structure.
-  * @retval None
-  */
-static void uart_dma_recv_cplt(void *arg)
-{
-	uart_handle_t *hperh = (uart_handle_t *)arg;
-
-	if (hperh->state == UART_STATE_BUSY_RX)
-		uart_dma_req_config(hperh, DISABLE);
-
-	hperh->rx_count = 0;
-	CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
-
-	if (hperh->rx_cplt_cbk)
-		hperh->rx_cplt_cbk(hperh);
-
-	return;
-}
-
-/**
-  * @brief  DMA uart communication error callback.
-  * @param  arg: Pointer to a uart_handle_t structure.
-  * @retval None
-  */
-static void uart_dma_error(void *arg)
-{
-	uart_handle_t *hperh = (uart_handle_t *)arg;
-
-	hperh->rx_count  = 0;
-	hperh->tx_count  = 0;
-	hperh->state     = UART_STATE_READY;
-	hperh->err_code |= UART_ERROR_DMA;
-	uart_dma_req_config(hperh, DISABLE);
-
-	if (hperh->error_cbk)
-		hperh->error_cbk(hperh);
-
-	return;
-}
-#endif
-
-/**
-  * @brief  This function handles uart Communication Timeout.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  flag: specifies the uart flag to check.
-  * @param  status: The new Flag status (SET or RESET).
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, flag_status_t status, uint32_t timeout)
-{
-	uint32_t tick;
-
-	if (timeout == 0)
-		return ERROR;
-
-	tick = __get_tick();
-
-	/* Waiting for flag */
-	while ((uart_get_status(hperh, flag)) != status) {
-		if (((__get_tick()) - tick) > timeout)
-			return TIMEOUT;
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t __uart_send_by_it(uart_handle_t *hperh)
-{
-	if ((hperh->state & UART_STATE_TX_MASK) == 0x0)
-		return BUSY;
-
-	WRITE_REG(hperh->perh->TBR, (uint8_t)(*hperh->tx_buf++ & 0x00FF));
-
-	if (--hperh->tx_count == 0) {
-		uart_clear_flag_status(hperh, UART_IF_TC);
-		uart_interrupt_config(hperh, UART_IT_TXS, DISABLE);
-		uart_interrupt_config(hperh, UART_IT_TC, ENABLE);
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  Wraps up transmission in non blocking mode.
-  * @param  hperh: pointer to a uart_handle_t structure.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t __uart_end_send_by_it(uart_handle_t *hperh)
-{
-	if (!(READ_BIT(hperh->perh->SR, UART_SR_TEM_MSK)))
-		return OK;
-
-	uart_interrupt_config(hperh, UART_IT_TC, DISABLE);
-	CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
-	if (hperh->tx_cplt_cbk)
-		hperh->tx_cplt_cbk(hperh);
-	
-	return OK;
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t __uart_recv_by_it(uart_handle_t *hperh)
-{
-	if ((hperh->state & UART_STATE_RX_MASK) == 0x0)
-		return BUSY;
-
-	*hperh->rx_buf++ = (uint8_t)(hperh->perh->RBR & 0xFF);
-
-	if (--hperh->rx_count == 0) {
-		uart_interrupt_config(hperh, UART_IT_RXRD, DISABLE);
-		CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
-
-		if (hperh->rx_cplt_cbk)
-			hperh->rx_cplt_cbk(hperh);
-	}
-
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup UART_Public_Functions UART Public Functions
-  * @{
-  */
-
-/** @defgroup UART_Public_Functions_Group1 Initialization and Configuration functions
-  * @brief    Initialization and Configuration functions
-  *
-  * @verbatim
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to initialize the UARTx
-    and configure UARTx param.
-      (+) For the UARTx only these parameters can be configured:
-        (++) Baud Rate
-        (++) Word Length
-        (++) Stop Bit
-        (++) Parity
-        (++) Hardware flow control
-      (+) For RS485 mode, user also need configure some parameters by
-          uart_rs485_config():
-        (++) Enable/disable normal point mode
-	(++) Enable/disable auto-direction
-	(++) Enable/disable address detection invert
-	(++) Enable/disable address for compare
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reset UART peripheral
-  * @param  hperh: Pointer to a uart_handle_t structure that contains
-  *         the configuration information for the specified uart module.
-  * @retval None
-  */
-void uart_reset(uart_handle_t *hperh)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-
-	WRITE_REG(hperh->perh->BRR, 0x0);
-	WRITE_REG(hperh->perh->LCR, 0x0);
-	WRITE_REG(hperh->perh->MCR, 0x0);
-	WRITE_REG(hperh->perh->CR, 0x0);
-	WRITE_REG(hperh->perh->RTOR, 0x0);
-	WRITE_REG(hperh->perh->FCR, 0x0);
-	WRITE_REG(hperh->perh->IDR, 0xFFF);
-
-	hperh->err_code = UART_ERROR_NONE;
-	hperh->state    = UART_STATE_RESET;
-
-	__UNLOCK(hperh);
-	return;
-}
-
-/**
-  * @brief  Initializes the UARTx according to the specified
-  *         parameters in the uart_handle_t.
-  * @param  hperh: Pointer to a uart_handle_t structure that contains
-  *         the configuration information for the specified UART module.
-  * @retval None
-  */
-void uart_init(uart_handle_t *hperh)
-{
-	uint32_t tmp;
-
-	assert_param(IS_UART_ALL(hperh->perh));
-	assert_param(IS_UART_BAUDRATE(hperh->init.baud));
-	assert_param(IS_UART_WORD_LENGTH(hperh->init.word_length));
-	assert_param(IS_UART_STOPBITS(hperh->init.stop_bits));
-	assert_param(IS_UART_PARITY(hperh->init.parity));
-	assert_param(IS_UART_MODE(hperh->init.mode));
-	assert_param(IS_UART_HARDWARE_FLOW_CONTROL(hperh->init.fctl));
-
-	uart_reset(hperh);
-
-	tmp = READ_REG(hperh->perh->LCR);
-	MODIFY_REG(tmp, UART_LCR_DLS_MSK, hperh->init.word_length << UART_LCR_DLS_POSS);
-	MODIFY_REG(tmp, UART_LCR_STOP_MSK, hperh->init.stop_bits << UART_LCR_STOP_POS);
-	MODIFY_REG(tmp, UART_LCR_PEN_MSK, (hperh->init.parity == UART_PARITY_NONE ? 0 : 1) << UART_LCR_PEN_POS);
-	MODIFY_REG(tmp, UART_LCR_PS_MSK, (hperh->init.parity == UART_PARITY_EVEN ? 1 : 0) << UART_LCR_PS_POS);
-	WRITE_REG(hperh->perh->LCR, tmp);
-	MODIFY_REG(hperh->perh->MCR, UART_MCR_AFCEN_MSK, hperh->init.fctl << UART_MCR_AFCEN_POS);
-	SET_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK);
-	WRITE_REG(hperh->perh->BRR, cmu_get_pclk1_clock() / hperh->init.baud);
-	CLEAR_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK);
-	SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK);
-	SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK);
-	SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK);
-	MODIFY_REG(hperh->perh->FCR, UART_FCR_RXTL_MSK, 0 << UART_FCR_RXTL_POSS);
-	MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, 0 << UART_FCR_TXTL_POSS);
-	SET_BIT(hperh->perh->LCR, UART_LCR_RXEN_MSK);
-
-	if (hperh->init.mode == UART_MODE_LIN)
-		SET_BIT(hperh->perh->MCR, UART_MCR_LINEN_MSK);
-	else if (hperh->init.mode == UART_MODE_IrDA)
-		SET_BIT(hperh->perh->MCR, UART_MCR_IREN_MSK);
-	else if (hperh->init.mode == UART_MODE_RS485)
-		SET_BIT(hperh->perh->MCR, UART_MCR_AADEN_MSK);
-	else if (hperh->init.mode == UART_MODE_HDSEL)
-		SET_BIT(hperh->perh->MCR, UART_MCR_HDSEL_MSK);
-	else
-		;/* do nothing */
-
-	if (hperh->init.fctl)
-		SET_BIT(hperh->perh->MCR, UART_MCR_RTSCTRL_MSK);
-	if (hperh->init.mode == UART_MODE_IrDA)
-		SET_BIT(hperh->perh->LCR, UART_LCR_RXINV_MSK);
-
-	hperh->state    = UART_STATE_READY;
-	hperh->err_code = UART_ERROR_NONE;
-	return;
-}
-
-/**
-  * @brief  Configure the RS485 mode according to the specified
-  *         parameters in the uart_rs485_config_t.
-  * @param  hperh: Pointer to a uart_handle_t structure that contains
-  *         the configuration information for the specified UART module.
-  * @param  config: Specifies the RS485 parameters.
-  * @retval None
-  */
-void uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-	assert_param(IS_FUNC_STATE(config->normal));
-	assert_param(IS_FUNC_STATE(config->dir));
-	assert_param(IS_FUNC_STATE(config->invert));
-
-	MODIFY_REG(hperh->perh->MCR, UART_MCR_AADNOR_MSK, config->normal << UART_MCR_AADNOR_POS);
-	MODIFY_REG(hperh->perh->MCR, UART_MCR_AADDIR_MSK, config->dir << UART_MCR_AADDIR_POS);
-	MODIFY_REG(hperh->perh->MCR, UART_MCR_AADINV_MSK, config->invert << UART_MCR_AADINV_POS);
-	MODIFY_REG(hperh->perh->CR, UART_CR_ADDR_MSK, config->addr << UART_CR_ADDR_POSS);
-
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup UART_Public_Functions_Group2 IO operation functions
-  * @brief UART Transmit and Receive functions
-  * @verbatim
-  ==============================================================================
-                      # IO operation functions #
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to manage the UART data transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode.
-            The Status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) Non blocking mode: The communication is performed using Interrupts
-            or DMA, these APIs return the Status.
-            The end of the data processing will be indicated through the
-            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-            The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks
-            will be executed respectively at the end of the transmit or receive process.
-            The hperh->error_cbk() user callback will be executed when
-            a communication error is detected.
-
-    (#) Blocking mode APIs are:
-        (++) uart_send()
-        (++) uart_recv()
-
-    (#) Non Blocking mode APIs with Interrupt are:
-        (++) uart_send_by_it()
-        (++) uart_recv_by_it()
-        (++) uart_irq_handle()
-
-    (#) Non Blocking mode functions with DMA are:
-        (++) uart_send_by_dma()
-        (++) uart_recv_by_dma()
-        (++) uart_dma_pause()
-        (++) uart_dma_resume()
-        (++) uart_dma_stop()
-
-    (#) A set of transfer complete callbacks are provided in non blocking mode:
-        (++) hperh->tx_cplt_cbk()
-        (++) hperh->rx_cplt_cbk()
-        (++) hperh->error_cbk()
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sends an amount of data in blocking mode.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-
-	if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX))
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	__LOCK(hperh);
-	hperh->err_code = UART_ERROR_NONE;
-	SET_BIT(hperh->state, UART_STATE_TX_MASK);
-
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-
-	while (hperh->tx_count-- > 0) {
-		if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK) {
-			__UNLOCK(hperh);
-			hperh->state = UART_STATE_READY;
-			return TIMEOUT;
-		}
-
-		WRITE_REG(hperh->perh->TBR, (*buf++ & 0xFF));
-	}
-
-	if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK) {
-		__UNLOCK(hperh);
-		hperh->state = UART_STATE_READY;
-		return TIMEOUT;
-	}
-
-	CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Receives an amount of data in blocking mode.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be received
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-
-	if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX))
-		return BUSY;
-
-	if ((buf == NULL ) || (size == 0))
-		return  ERROR;
-
-	__LOCK(hperh);
-
-	hperh->err_code = UART_ERROR_NONE;
-	SET_BIT(hperh->state, UART_STATE_RX_MASK);
-
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-
-	while (hperh->rx_count-- > 0) {
-		if (uart_wait_flag(hperh, UART_STATUS_DR, SET, timeout) != OK) {
-			__UNLOCK(hperh);
-			hperh->state = UART_STATE_READY;
-			return TIMEOUT;
-		}
-
-		*buf++ = (uint8_t)(hperh->perh->RBR & 0xFF);
-	}
-
-	CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-
-	if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX))
-		return BUSY;
-
-	if ((buf == NULL ) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-
-	hperh->tx_buf   = buf;
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-	hperh->err_code = UART_ERROR_NONE;
-	SET_BIT(hperh->state, UART_STATE_TX_MASK);
-	__UNLOCK(hperh);
-
-	if (((uart_get_status(hperh, UART_STATUS_TBEM)) == SET)
-			&& ((uart_get_flag_status(hperh, UART_IF_TXS)) == RESET)) {
-		WRITE_REG(hperh->perh->TBR, (*hperh->tx_buf++ & 0xFF));
-		--hperh->tx_count;
-	}
-
-	if (hperh->tx_count == 0) {
-		uart_interrupt_config(hperh, UART_IT_TC, ENABLE);
-		return OK;
-	}
-
-	uart_interrupt_config(hperh, UART_IT_TXS, ENABLE);
-	return OK;
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be received
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-
-	if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX))
-		return BUSY;
-
-	if ((buf == NULL ) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-	hperh->rx_buf   = buf;
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-	hperh->err_code = UART_ERROR_NONE;
-	SET_BIT(hperh->state, UART_STATE_RX_MASK);
-	__UNLOCK(hperh);
-
-	uart_interrupt_config(hperh, UART_IT_RXRD, ENABLE);
-	return OK;
-}
-#ifdef ALD_DMA
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  channel: DMA channel as UART transmit
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-
-	if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX))
-		return BUSY;
-
-	if ((buf == NULL ) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-
-	hperh->tx_buf   = buf;
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-	hperh->err_code = UART_ERROR_NONE;
-	SET_BIT(hperh->state, UART_STATE_TX_MASK);
-
-	if (hperh->hdmatx.perh == NULL)
-		hperh->hdmatx.perh = DMA0;
-
-	hperh->hdmatx.cplt_cbk = uart_dma_send_cplt;
-	hperh->hdmatx.cplt_arg = (void *)hperh;
-	hperh->hdmatx.err_cbk  = uart_dma_error;
-	hperh->hdmatx.err_arg  = (void *)hperh;
-
-	dma_config_struct(&hperh->hdmatx.config);
-	hperh->hdmatx.config.src     = (void *)buf;
-	hperh->hdmatx.config.dst     = (void *)&hperh->perh->TBR;
-	hperh->hdmatx.config.size    = size;
-	hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE;
-	hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
-	hperh->hdmatx.config.msigsel = DMA_MSIGSEL_UART_TXEMPTY;
-	hperh->hdmatx.config.burst   = ENABLE;
-	hperh->hdmatx.config.channel = channel;
-
-	if (hperh->init.mode == UART_MODE_RS485) {
-		hperh->hdmatx.config.src_inc    = DMA_DATA_INC_HALFWORD;
-		hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
-	}
-
-	if (hperh->perh == UART0)
-		hperh->hdmatx.config.msel = DMA_MSEL_UART0;
-	else if (hperh->perh == UART1)
-		hperh->hdmatx.config.msel = DMA_MSEL_UART1;
-	else if (hperh->perh == UART2)
-		hperh->hdmatx.config.msel = DMA_MSEL_UART2;
-	else if (hperh->perh == UART3)
-		hperh->hdmatx.config.msel = DMA_MSEL_UART3;
-	else
-		;	/* do nothing */
-
-	dma_config_basic(&hperh->hdmatx);
-
-	__UNLOCK(hperh);
-	uart_clear_flag_status(hperh, UART_IF_TC);
-	uart_dma_req_config(hperh, ENABLE);
-
-	return OK;
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be received
-  * @param  channel: DMA channel as UART receive
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-
-	if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX))
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-
-	hperh->rx_buf   = buf;
-	hperh->rx_size  = size;
-	hperh->err_code = UART_ERROR_NONE;
-	SET_BIT(hperh->state, UART_STATE_RX_MASK);
-
-	if (hperh->hdmarx.perh == NULL)
-		hperh->hdmarx.perh = DMA0;
-
-	hperh->hdmarx.cplt_cbk = uart_dma_recv_cplt;
-	hperh->hdmarx.cplt_arg = (void *)hperh;
-	hperh->hdmarx.err_cbk  = uart_dma_error;
-	hperh->hdmarx.err_arg  = (void *)hperh;
-
-	dma_config_struct(&hperh->hdmarx.config);
-	hperh->hdmarx.config.src     = (void *)&hperh->perh->RBR;
-	hperh->hdmarx.config.dst     = (void *)buf;
-	hperh->hdmarx.config.size    = size;
-	hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
-	hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE;
-	hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART_RNR;
-	hperh->hdmarx.config.burst   = ENABLE;
-	hperh->hdmarx.config.channel = channel;
-
-	if (hperh->init.mode == UART_MODE_RS485) {
-		hperh->hdmarx.config.dst_inc    = DMA_DATA_INC_HALFWORD;
-		hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD;
-	}
-
-	if (hperh->perh == UART0)
-		hperh->hdmarx.config.msel = DMA_MSEL_UART0;
-	else if (hperh->perh == UART1)
-		hperh->hdmarx.config.msel = DMA_MSEL_UART1;
-	else if (hperh->perh == UART2)
-		hperh->hdmarx.config.msel = DMA_MSEL_UART2;
-	else if (hperh->perh == UART3)
-		hperh->hdmarx.config.msel = DMA_MSEL_UART3;
-	else
-		;
-
-	dma_config_basic(&hperh->hdmarx);
-	__UNLOCK(hperh);
-	uart_dma_req_config(hperh, ENABLE);
-
-	return OK;
-}
-
-/**
-  * @brief  Pauses the DMA Transfer.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t uart_dma_pause(uart_handle_t *hperh)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-
-	uart_dma_req_config(hperh, DISABLE);
-	return OK;
-}
-
-/**
-  * @brief  Resumes the DMA Transfer.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t uart_dma_resume(uart_handle_t *hperh)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-
-	uart_dma_req_config(hperh, ENABLE);
-	return OK;
-}
-
-/**
-  * @brief  Stops the DMA Transfer.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t uart_dma_stop(uart_handle_t *hperh)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-
-	uart_dma_req_config(hperh, DISABLE);
-	hperh->state = UART_STATE_READY;
-	return OK;
-}
-#endif
-
-/**
-  * @brief  This function handles UART interrupt request.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @retval None
-  */
-void uart_irq_handle(uart_handle_t *hperh)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-
-	/* Handle parity error */
-	if ((uart_get_status(hperh, UART_STATUS_PE)) != RESET)
-		hperh->err_code |= UART_ERROR_PE;
-
-	/* Handle frame error */
-	if ((uart_get_status(hperh, UART_STATUS_FE)) != RESET)
-		hperh->err_code |= UART_ERROR_FE;
-
-	/* Handle overflow error */
-	if ((uart_get_status(hperh, UART_STATUS_OE)) != RESET)
-		hperh->err_code |= UART_ERROR_ORE;
-
-	/* Receive */
-	if ((uart_get_mask_flag_status(hperh, UART_IF_RXRD)) != RESET) {
-		uart_clear_flag_status(hperh, UART_IF_RXRD);
-		__uart_recv_by_it(hperh);
-	}
-
-	/* Transmite */
-	if ((uart_get_mask_flag_status(hperh, UART_IF_TXS)) != RESET) {
-		uart_clear_flag_status(hperh, UART_IF_TXS);
-		__uart_send_by_it(hperh);
-	}	
-
-	/* End Transmite */
-	if ((uart_get_mask_flag_status(hperh, UART_IF_TC)) != RESET) {
-		uart_clear_flag_status(hperh, UART_IF_TC);
-		__uart_end_send_by_it(hperh);
-	}
-
-	/* Handle error state */
-	if (hperh->err_code != UART_ERROR_NONE) {
-		hperh->state = UART_STATE_READY;
-
-		if (hperh->error_cbk)
-			hperh->error_cbk(hperh);
-	}
-}
-/**
-  * @}
-  */
-
-/** @defgroup UART_Public_Functions_Group3 Peripheral Control functions
-  *  @brief   UART control functions
-  *
-  * @verbatim
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to control the UART:
-    (+) uart_interrupt_config() API can be helpful to configure UART interrupt source.
-    (+) uart_dma_req_config() API can be helpful to configure UART DMA request.
-    (+) uart_tx_fifo_config() API can be helpful to configure UART TX FIFO paramters.
-    (+) uart_rx_fifo_config() API can be helpful to configure UART RX FIFO paramters.
-    (+) uart_lin_send_break() API can send a frame of break in LIN mode.
-    (+) uart_lin_detect_break_len_config() API can be helpful to configure the length of break frame.
-    (+) uart_auto_baud_config() API can be helpful to configure detection data mode.
-    (+) uart_get_it_status() API can get the status of interrupt source.
-    (+) uart_get_status() API can get the status of UART_SR register.
-    (+) uart_get_flag_status() API can get the status of UART flag.
-    (+) uart_get_mask_flag_status() API can get status os flag and interrupt source.
-    (+) uart_clear_flag_status() API can clear UART flag.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enable/disable the specified UART interrupts.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  it: Specifies the UART interrupt sources to be enabled or disabled.
-  *         This parameter can be one of the @ref uart_it_t.
-  * @param  state: New state of the specified UART interrupts.
-  *         This parameter can be:
-  *             @arg ENABLE
-  *             @arg DISABLE
-  * @retval None
-  */
-void uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-	assert_param(IS_UART_IT(it));
-	assert_param(IS_FUNC_STATE(state));
-
-	if (state == ENABLE)
-		WRITE_REG(hperh->perh->IER, it);
-	else
-		WRITE_REG(hperh->perh->IDR, it);
-
-	return;
-}
-
-/**
-  * @brief  Configure UART DMA request.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  state: New state of the specified DMA request.
-  *         This parameter can be:
-  *             @arg ENABLE
-  *             @arg DISABLE
-  * @retval None
-  */
-void uart_dma_req_config(uart_handle_t *hperh, type_func_t state)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-	assert_param(IS_FUNC_STATE(state));
-
-	if (state == ENABLE)
-		SET_BIT(hperh->perh->MCR, UART_MCR_DMAEN_MSK);
-	else
-		CLEAR_BIT(hperh->perh->MCR, UART_MCR_DMAEN_MSK);
-
-	return;
-}
-
-/**
-  * @brief  Configure transmit fifo parameters.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  config: Transmit fifo trigger level.
-  * @param  level: Transmit fifo level.
-  * @retval None
-  */
-void uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-	assert_param(IS_UART_TXFIFO_TYPE(config));
-
-	SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK);
-	MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, config << UART_FCR_TXTL_POSS);
-	MODIFY_REG(hperh->perh->FCR, UART_FCR_TXFL_MSK, level << UART_FCR_TXFL_POSS);
-	SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK);
-
-	return;
-}
-
-/**
-  * @brief  Configure receive fifo parameters.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  config: Receive fifo trigger level.
-  * @param  level: Receive fifo level.
-  * @retval None
-  */
-void uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-	assert_param(IS_UART_RXFIFO_TYPE(config));
-
-	SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK);
-	MODIFY_REG(hperh->perh->FCR, UART_FCR_RXTL_MSK, config << UART_FCR_RXTL_POSS);
-	MODIFY_REG(hperh->perh->FCR, UART_FCR_RXFL_MSK, level << UART_FCR_RXFL_POSS);
-	SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK);
-
-	return;
-}
-
-/**
-  * @brief  request to send a frame of break.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @retval None
-  */
-void uart_lin_send_break(uart_handle_t *hperh)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-
-	SET_BIT(hperh->perh->MCR, UART_MCR_BKREQ_MSK);
-	return;
-}
-
-/**
-  * @brief  Configure the length of break frame to be detect.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  len: Length of break frame.
-  *           @arg LIN_BREAK_LEN_10B
-  *           @arg LIN_BREAK_LEN_11B
-  * @retval None
-  */
-void uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-	assert_param(IS_UART_LIN_BREAK_LEN(len));
-
-	MODIFY_REG(hperh->perh->MCR, UART_MCR_LINBDL_MSK, len << UART_MCR_LINBDL_POS);
-	return;
-}
-
-/**
-  * @brief  Configure the mode of auto-baud-rate detect.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  mode: The mode of auto-baud-rate detect.
-  *           @arg UART_ABRMOD_1_TO_0
-  *           @arg UART_ABRMOD_1
-  *           @arg UART_ABRMOD_0_TO_1
-  * @retval None
-  */
-void uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-	assert_param(IS_UART_AUTO_BAUD_MODE(mode));
-
-	MODIFY_REG(hperh->perh->MCR, UART_MCR_ABRMOD_MSK, mode << UART_MCR_ABRMOD_POSS);
-	return;
-}
-
-/**
-  * @brief  Send address in RS485 mode.
-  * @param  hperh: Pointer to a uart_handle_t structure that contains
-  *         the configuration information for the specified UART module.
-  * @param  addr: the address of RS485 device.
-  * @param  timeout: Timeout duration
-  * @retval The ALD status.
-  */
-ald_status_t uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-
-	if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX))
-		return BUSY;
-
-	SET_BIT(hperh->state, UART_STATE_TX_MASK);
-
-	if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK) {
-		hperh->state = UART_STATE_READY;
-		return TIMEOUT;
-	}
-
-	WRITE_REG(hperh->perh->TBR, (addr | 0x100));
-
-	if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK) {
-		hperh->state = UART_STATE_READY;
-		return TIMEOUT;
-	}
-
-	CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
-
-	return OK;
-}
-
-/**
-  * @brief  Get the status of UART interrupt source.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  it: Specifies the UART interrupt source.
-  *         This parameter can be one of the @ref uart_it_t.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-it_status_t uart_get_it_status(uart_handle_t *hperh, uart_it_t it)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-	assert_param(IS_UART_IT(it));
-
-	if (READ_BIT(hperh->perh->IVS, it))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Get the status of UART_SR register.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  status: Specifies the UART status type.
-  *         This parameter can be one of the @ref uart_status_t.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-flag_status_t uart_get_status(uart_handle_t *hperh, uart_status_t status)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-	assert_param(IS_UART_STATUS(status));
-
-	if (READ_BIT(hperh->perh->SR, status))
-		return SET;
-
-	return RESET;
-}
-
-
-/**
-  * @brief  Get the status of UART interrupt flag.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  flag: Specifies the UART interrupt flag.
-  *         This parameter can be one of the @ref uart_flag_t.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-flag_status_t uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-	assert_param(IS_UART_IF(flag));
-
-	if (READ_BIT(hperh->perh->RIF, flag))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Get the status of interrupt flag and interupt source.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  flag: Specifies the UART interrupt flag.
-  *         This parameter can be one of the @ref uart_flag_t.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-flag_status_t uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-	assert_param(IS_UART_IF(flag));
-
-	if (READ_BIT(hperh->perh->IFM, flag))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Clear the UART interrupt flag.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @param  flag: Specifies the UART interrupt flag.
-  *         This parameter can be one of the @ref uart_flag_t.
-  * @retval None
-  */
-void uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag)
-{
-	assert_param(IS_UART_ALL(hperh->perh));
-	assert_param(IS_UART_IF(flag));
-
-	WRITE_REG(hperh->perh->ICR, flag);
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup UART_Public_Functions_Group4 Peripheral State and Errors functions
-  *  @brief   UART State and Errors functions
-  *
-@verbatim
-  ==============================================================================
-                 ##### Peripheral State and Errors functions #####
-  ==============================================================================
- [..]
-   This subsection provides a set of functions allowing to return the State of
-   UART communication process, return Peripheral Errors occurred during communication
-   process
-   (+) uart_get_state() API can be helpful to check in run-time the state of the UART peripheral.
-   (+) uart_get_error() check in run-time errors that could be occurred during communication.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the UART state.
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @retval ALD state
-  */
-uart_state_t uart_get_state(uart_handle_t *hperh)
-{
-	return hperh->state;
-}
-
-/**
-  * @brief  Return the UART error code
-  * @param  hperh: Pointer to a uart_handle_t structure.
-  * @retval UART Error Code
-  */
-uint32_t uart_get_error(uart_handle_t *hperh)
-{
-	return hperh->err_code;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* ALD_UART */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

bsp/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_usart.c

@@ -1,2347 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_usart.c
-  * @brief   USART module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
-  *           + Initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Errors functions
-  *
-  * @version V1.0
-  * @date    25 Apr 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  * @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The USART ALD driver can be used as follows:
-
-    (#) Declare a usart_handle_t handle structure.
-
-    (#) Initialize the USART handle:
-        (##) Enable the USARTx interface clock.
-        (##) USART pins configuration:
-            (+++) Enable the clock for the USART GPIOs.
-            (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
-        (##) NVIC configuration if you need to use interrupt process (usart_send_by_it()
-             and usart_recv_by_it() APIs):
-            (+++) Configure the USARTx interrupt priority.
-            (+++) Enable the NVIC USART IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (usart_send_by_dma()
-             and usart_recv_by_dma() APIs):
-            (+++) Declare a DMA handle structure for the Tx/Rx channel.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required
-                  Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx channel.
-            (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
-
-    (#) Program the baud rate, word length, stop bit, parity, hardware
-        flow control and mode(Receiver/Transmitter) in the hperh Init structure.
-
-    (#) For the USART asynchronous mode, initialize the USART registers by calling
-        the usart_init() API.
-
-    (#) For the USART Half duplex mode, initialize the USART registers by calling
-        the usart_half_duplex_init() API.
-
-    (#) For the LIN mode, initialize the USART registers by calling the usart_lin_init() API.
-
-    (#) For the Multi-Processor mode, initialize the USART registers by calling
-        the usart_multi_processor_init() API.
-
-     [..]
-       (@) The specific USART interrupts (Transmission complete interrupt,
-            RXNE interrupt and Error Interrupts) will be managed using the function
-            usart_interrupt_config inside the transmit and receive process.
-
-     [..]
-        Three operation modes are available within this driver :
-
-     *** Polling mode IO operation ***
-     =================================
-     [..] Asynchronous:
-       (+) Send an amount of data in blocking mode using usart_send()
-       (+) Receive an amount of data in blocking mode using usart_recv()
-
-     [..] Synchronous:
-       (+) Send an amount of data in blocking mode using usart_send_sync()
-       (+) Receive an amount of data in blocking mode using usart_recv_sync()
-
-     *** Interrupt mode IO operation ***
-     ===================================
-     [..] Asynchronous:
-       (+) Send an amount of data in non blocking mode using usart_send_by_it()
-       (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can
-            add his own code by customization of function pointer hperh->tx_cplt_cbk()
-       (+) Receive an amount of data in non blocking mode using USART_recv_by_it()
-       (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can
-            add his own code by customization of function pointer hperh->rx_cplt_cbk()
-       (+) In case of transfer Error, hperh->error_cbk() function is executed and user can
-            add his own code by customization of function pointer hperh->error_cbk()
-     [..] Synchronous:
-       (+) Send an amount of data in non blocking mode using usart_send_by_it_sync()
-       (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can
-            add his own code by customization of function pointer hperh->tx_cplt_cbk()
-       (+) Receive an amount of data in non blocking mode using USART_recv_by_it_sync()
-       (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can
-            add his own code by customization of function pointer hperh->rx_cplt_cbk()
-       (+) In case of transfer Error, hperh->error_cbk() function is executed and user can
-            add his own code by customization of function pointer hperh->error_cbk()
-
-     *** DMA mode IO operation ***
-     ==============================
-     [..] Asynchronous:
-       (+) Send an amount of data in non blocking mode (DMA) using usart_send_by_dma()
-       (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can
-            add his own code by customization of function pointer hperh->tx_cplt_cbk()
-       (+) Receive an amount of data in non blocking mode (DMA) using usart_recv_by_dma()
-       (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can
-            add his own code by customization of function pointer hperh->rx_cplt_cbk()
-       (+) In case of transfer Error, hperh->error_cbk()() function is executed and user can
-            add his own code by customization of function pointer hperh->error_cbk()
-     [..] Synchronous:
-       (+) Send an amount of data in non blocking mode (DMA) using usart_send_by_dma_sync()
-       (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can
-            add his own code by customization of function pointer hperh->tx_cplt_cbk()
-       (+) Receive an amount of data in non blocking mode (DMA) using usart_recv_by_dma_sync()
-       (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can
-            add his own code by customization of function pointer hperh->rx_cplt_cbk()
-       (+) In case of transfer Error, hperh->error_cbk()() function is executed and user can
-            add his own code by customization of function pointer hperh->error_cbk()
-     [..] Utilities:
-       (+) Pause the DMA Transfer using usart_dma_pause()
-       (+) Resume the DMA Transfer using usart_dma_resume()
-       (+) Stop the DMA Transfer using usart_dma_stop()
-
-     *** USART ALD driver macros list ***
-     =============================================
-     [..]
-       Below the list of most used macros in USART ALD driver.
-
-      (+) USART_ENABLE: Enable the USART peripheral
-      (+) USART_DISABLE: Disable the USART peripheral
-      (+) USART_RESET_HANDLE_STATE : Reset USART handle
-      (+) USART_CLEAR_PEFLAG : Clear PE flag
-      (+) USART_CLEAR_FEFLAG: Clear FE flag
-      (+) USART_CLEAR_NEFLAG: Clear NE flag
-      (+) USART_CLEAR_OREFLAG: Clear voerrun flag
-      (+) USART_CLEAR_IDLEFLAG : Clear IDLE flag
-      (+) USART_HWCONTROL_CTS_ENABLE: Enable CTS flow control
-      (+) USART_HWCONTROL_CTS_DISABLE: Disable CTS flow control
-      (+) USART_HWCONTROL_RTS_ENABLE: Enable RTS flow control
-      (+) USART_HWCONTROL_RTS_DISABLE: Disable RTS flow control
-
-     [..]
-       (@) You can refer to the USART Library header file for more useful macros
-
-    @endverbatim
-  ******************************************************************************
-  */
-
-#include "ald_usart.h"
-#include "ald_cmu.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup USART USART
-  * @brief USART module driver
-  * @{
-  */
-#ifdef ALD_USART
-
-/** @defgroup USART_Private_Variables USART Private Variables
-  * @{
-  */
-uint8_t __frame_mode = 0;
-/**
-  * @}
-  */
-
-/** @addtogroup USART_Private_Functions   USART Private Functions
-  * @{
-  */
-static void usart_set_config (usart_handle_t *hperh);
-static ald_status_t __usart_send_by_it(usart_handle_t *hperh);
-static ald_status_t __usart_end_send_by_it(usart_handle_t *hperh);
-static ald_status_t __usart_recv_by_it(usart_handle_t *hperh);
-static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh);
-static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh);
-static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh);
-#ifdef ALD_DMA
-static void usart_dma_send_cplt(void *arg);
-static void usart_dma_recv_cplt(void *arg);
-static void usart_dma_error(void *arg);
-#endif
-static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout);
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Functions USART Public Functions
-  * @{
-  */
-
-/** @defgroup USART_Public_Functions_Group1 Initialization functions
-  * @brief    Initialization and Configuration functions
-  *
-  * @verbatim
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to initialize the USARTx or the USARTy
-    in asynchronous or synchronous mode.
-      (+) For the asynchronous mode only these parameters can be configured:
-        (++) Baud rate
-        (++) Word length
-        (++) Stop bit
-        (++) Parity
-        (++) Hardware flow control
-        (++) Receiver/transmitter modes
-    [..]
-    The usart_init(), usart_half_duplex_init(), usart_lin_init(), usart_multi_processor_init()
-    and usart_clock_init() APIs follow respectively the USART asynchronous, USART Half duplex,
-    LIN, Multi-Processor and synchronous configuration procedures.
-
-    @endverbatim
-  * @{
-  */
-
-/*
-  Additionnal remark: If the parity is enabled, then the MSB bit of the data written
-                      in the data register is transmitted but is changed by the parity bit.
-                      Depending on the frame length defined by the M bit (8-bits or 9-bits),
-                      the possible USART frame formats are as listed in the following table:
-    +-------------------------------------------------------------+
-    |   M bit |  PCE bit  |            USART frame                 |
-    |---------------------|---------------------------------------|
-    |    0    |    0      |    | SB | 8 bit data | STB |          |
-    |---------|-----------|---------------------------------------|
-    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
-    |---------|-----------|---------------------------------------|
-    |    1    |    0      |    | SB | 9 bit data | STB |          |
-    |---------|-----------|---------------------------------------|
-    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-    +-------------------------------------------------------------+
-*/
-
-
-/**
-  * @brief  Reset the USART peripheral.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval None
-  */
-void usart_reset(usart_handle_t *hperh)
-{
-	assert_param(IS_USART(hperh->perh));
-
-	hperh->state = USART_STATE_BUSY;
-	USART_DISABLE(hperh);
-
-	WRITE_REG(hperh->perh->CON0, 0x0);
-	WRITE_REG(hperh->perh->CON1, 0x0);
-	WRITE_REG(hperh->perh->CON2, 0x0);
-
-	hperh->err_code = USART_ERROR_NONE;
-	hperh->state    = USART_STATE_RESET;
-
-	__UNLOCK(hperh);
-	return;
-}
-
-/**
-  * @brief  Initializes the USART mode according to the specified parameters in
-  *         the usart_init_t and create the associated handle.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_init(usart_handle_t *hperh)
-{
-	assert_param(IS_USART(hperh->perh));
-	assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl));
-	assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length));
-	assert_param(IS_FUNC_STATE(hperh->init.over_sampling));
-
-	usart_reset(hperh);
-	hperh->state = USART_STATE_BUSY;
-	USART_DISABLE(hperh);
-	usart_set_config(hperh);
-
-	/* In asynchronous mode, the following bits must be kept cleared:
-	 *   - LINEN and CLKEN bits in the USART_CR2 register,
-	 *   - SCEN, HDSEL and IREN  bits in the USART_CR3 register.
-	 */
-	CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK);
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK);
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK);
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK);
-
-	hperh->err_code = USART_ERROR_NONE;
-	hperh->state    = USART_STATE_READY;
-	USART_ENABLE(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Initializes the half-duplex mode according to the specified
-  *         parameters in the usart_init_t and create the associated handle.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_half_duplex_init(usart_handle_t *hperh)
-{
-	assert_param(IS_USART(hperh->perh));
-	assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length));
- 	assert_param(IS_FUNC_STATE(hperh->init.over_sampling));
-
-	usart_reset(hperh);
-	hperh->state = USART_STATE_BUSY;
-	USART_DISABLE(hperh);
-	usart_set_config(hperh);
-
-	/* In half-duplex mode, the following bits must be kept cleared:
-	 *   - LINEN and CLKEN bits in the USART_CR2 register,
-	 *   - SCEN and IREN bits in the USART_CR3 register.*/
-	CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK);
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK);
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK);
-	SET_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK);
-
-	hperh->err_code = USART_ERROR_NONE;
-	hperh->state    = USART_STATE_READY;
-	USART_ENABLE(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Initializes the Multi-Processor mode according to the specified
-  *         parameters in the usart_init_t and create the associated handle.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  addr: USART node address
-  * @param  wakeup: specifies the USART wakeup method.
-  *         This parameter can be one of the following values:
-  *            @arg USART_WAKEUP_IDLE: Wakeup by an idle line detection
-  *            @arg USART_WAKEUP_ADDR: Wakeup by an address mark
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usart_wakeup_t wakeup)
-{
-	assert_param(IS_USART(hperh->perh));
-	assert_param(IS_USART_WAKEUP(wakeup));
-	assert_param(IS_USART_ADDRESS(addr));
-	assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length));
-	assert_param(IS_FUNC_STATE(hperh->init.over_sampling));
-
-	usart_reset(hperh);
-	hperh->state = USART_STATE_BUSY;
-	USART_DISABLE(hperh);
-	usart_set_config(hperh);
-
-	/* In Multi-Processor mode, the following bits must be kept cleared:
-	 *   - LINEN and CLKEN bits in the USART_CR2 register,
-	 *   - SCEN, HDSEL and IREN  bits in the USART_CR3 register */
-	CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK);
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK);
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK);
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK);
-	MODIFY_REG(hperh->perh->CON1, USART_CON1_ADDR_MSK, addr << USART_CON1_ADDR_POSS);
-	MODIFY_REG(hperh->perh->CON0, USART_CON0_WKMOD_MSK, wakeup << USART_CON0_WKMOD_POS);
-
-	hperh->err_code = USART_ERROR_NONE;
-	hperh->state    = USART_STATE_READY;
-	USART_ENABLE(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Initializes the synchronization mode according to the specified
-  *         parameters in the usart_init_t and usart_clock_init_t.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  init: USART Clock Init Structure.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init)
-{
-	assert_param(IS_USART(hperh->perh));
-	assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length));
-	assert_param(IS_FUNC_STATE(hperh->init.over_sampling));
-
-	usart_reset(hperh);
-	hperh->state = USART_STATE_BUSY;
-	USART_DISABLE(hperh);
-	usart_set_config(hperh);
-
-	/* In Multi-Processor mode, the following bits must be kept cleared:
-	 *   - LINEN and CLKEN bits in the USART_CR2 register,
-	 *   - SCEN, HDSEL and IREN  bits in the USART_CR3 register */
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK);
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK);
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK);
-	MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKEN_MSK, init->clk << USART_CON1_SCKEN_POS);
-	MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKPOL_MSK, init->polarity << USART_CON1_SCKPOL_POS);
-	MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKPHA_MSK, init->phase << USART_CON1_SCKPHA_POS);
-	MODIFY_REG(hperh->perh->CON1, USART_CON1_LBCP_MSK, init->last_bit << USART_CON1_LBCP_POS);
-
-	hperh->err_code = USART_ERROR_NONE;
-	hperh->state    = USART_STATE_READY;
-	USART_ENABLE(hperh);
-
-	return OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Functions_Group2 IO operation functions
-  * @brief USART Transmit and Receive functions
-  * @{
-  */
-
-/** @defgroup USART_Public_Functions_Group2_1 Asynchronization IO operation functions
-  * @brief Asynchronization IO operation functions
-  *
-  * @verbatim
-  ==============================================================================
-                      ##### IO operation functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to manage the USART asynchronous
-    and Half duplex data transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode.
-            The Status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) Non blocking mode: The communication is performed using Interrupts
-            or DMA, these APIs return the Status.
-            The end of the data processing will be indicated through the
-            dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-            The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks
-            will be executed respectively at the end of the transmit or receive process.
-            The hperh->error_cbk() user callback will be executed when
-            a communication error is detected.
-
-    (#) Blocking mode APIs are:
-        (++) usart_send()
-        (++) usart_recv()
-
-    (#) Non Blocking mode APIs with Interrupt are:
-        (++) usart_send_by_it()
-        (++) usart_recv_by_it()
-        (++) urart_irq_handle()
-
-    (#) Non Blocking mode functions with DMA are:
-        (++) usart_send_by_dma()
-        (++) usart_recv_by_dma()
-        (++) usart_dma_pause()
-        (++) usart_dma_resume()
-        (++) usart_dma_stop()
-
-    (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
-        (++) hperh->tx_cplt_cbk()
-        (++) hperh->rx_cplt_cbk()
-        (++) hperh->error_cbk()
-
-    [..]
-      (@) In the Half duplex communication, it is forbidden to run the transmit
-          and receive process in parallel, the USART state USART_STATE_BUSY_TX_RX
-          can't be useful.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sends an amount of data in blocking mode.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
-{
-	if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX))
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-	hperh->err_code = USART_ERROR_NONE;
-	SET_BIT(hperh->state, USART_STATE_TX_MASK);
-
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-
-	while (hperh->tx_count-- > 0) {
-		if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) {
-			__UNLOCK(hperh);
-			hperh->state = USART_STATE_READY;
-			return TIMEOUT;
-		}
-
-		if (hperh->init.word_length == USART_WORD_LENGTH_9B) {
-			if (hperh->init.parity == USART_PARITY_NONE) {
-				WRITE_REG(hperh->perh->DATA, (*(uint16_t *)buf & (uint16_t)0x01FF));
-				buf += 2;
-			}
-			else {
-				WRITE_REG(hperh->perh->DATA, *buf++);
-			}
-		}
-		else {
-			WRITE_REG(hperh->perh->DATA, *buf++);
-		}
-	}
-
-	if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) {
-		__UNLOCK(hperh);
-		hperh->state = USART_STATE_READY;
-		return TIMEOUT;
-	}
-
-	CLEAR_BIT(hperh->state, USART_STATE_TX_MASK);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Receives an amount of data in blocking mode.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be received
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
-{
-	if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX))
-		return BUSY;
-
-	if ((buf == NULL ) || (size == 0))
-		return  ERROR;
-
-	__LOCK(hperh);
-	hperh->err_code = USART_ERROR_NONE;
-	SET_BIT(hperh->state, USART_STATE_RX_MASK);
-
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-
-	while (hperh->rx_count-- > 0) {
-		if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) {
-			__UNLOCK(hperh);
-			hperh->state = USART_STATE_READY;
-			return TIMEOUT;
-		}
-
-		if (hperh->init.word_length == USART_WORD_LENGTH_9B) {
-			if (hperh->init.parity == USART_PARITY_NONE) {
-				*(uint16_t *)buf = (uint16_t)(hperh->perh->DATA & 0x1FF);
-				buf += 2;
-			}
-			else {
-				*buf = (uint8_t)(hperh->perh->DATA & 0xFF);
-				buf += 1;
-			}
-		}
-		else {
-			if (hperh->init.parity == USART_PARITY_NONE)
-				*buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
-			else
-				*buf++ = (uint8_t)(hperh->perh->DATA & 0x7F);
-		}
-	}
-
-	CLEAR_BIT(hperh->state, USART_STATE_RX_MASK);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size)
-{
-	if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX))
-		return BUSY;
-
-	if ((buf == NULL ) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-	SET_BIT(hperh->state, USART_STATE_TX_MASK);
-
-	hperh->tx_buf   = buf;
-	hperh->rx_size  = size;
-	hperh->tx_count = size;
-	hperh->err_code = USART_ERROR_NONE;
-
-	__UNLOCK(hperh);
-	usart_interrupt_config(hperh, USART_IT_TXE, ENABLE);
-
-	return OK;
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be received
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size)
-{
-	if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX))
-		return BUSY;
-
-	if ((buf == NULL ) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-	SET_BIT(hperh->state, USART_STATE_RX_MASK);
-
-	hperh->rx_buf   = buf;
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-	hperh->err_code = USART_ERROR_NONE;
-
-	__UNLOCK(hperh);
-	usart_interrupt_config(hperh, USART_IT_PE, ENABLE);
-	usart_interrupt_config(hperh, USART_IT_ERR, ENABLE);
-	usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE);
-
-	return OK;
-}
-
-/**
-  * @brief  Receives an frame in interrupt mode
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Maximum amount of data to be received
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size)
-{
-	if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX))
-		return BUSY;
-
-	if ((buf == NULL ) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-	SET_BIT(hperh->state, USART_STATE_RX_MASK);
-
-	hperh->rx_buf   = buf;
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-	hperh->err_code = USART_ERROR_NONE;
-
-	__UNLOCK(hperh);
-	usart_interrupt_config(hperh, USART_IT_PE, ENABLE);
-	usart_interrupt_config(hperh, USART_IT_ERR, ENABLE);
-	usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE);
-	__frame_mode = 1;
-
-	return OK;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  channel: DMA channel as USART transmit
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
-{
-	if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX))
-		return BUSY;
-
-	if ((buf == NULL ) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-	SET_BIT(hperh->state, USART_STATE_TX_MASK);
-
-	hperh->tx_buf   = buf;
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-	hperh->err_code = USART_ERROR_NONE;
-
-	if (hperh->hdmatx.perh == NULL)
-		hperh->hdmatx.perh = DMA0;
-
-	/* Configure callback function */
-	hperh->hdmatx.cplt_cbk = usart_dma_send_cplt;
-	hperh->hdmatx.cplt_arg = (void *)hperh;
-	hperh->hdmatx.err_cbk  = usart_dma_error;
-	hperh->hdmatx.err_arg  = (void *)hperh;
-
-	/* Configure USART DMA transmit */
-	dma_config_struct(&hperh->hdmatx.config);
-	hperh->hdmatx.config.src     = (void *)buf;
-	hperh->hdmatx.config.dst     = (void *)&hperh->perh->DATA;
-	hperh->hdmatx.config.size    = size;
-	hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE;
-	hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
-	hperh->hdmatx.config.msel    = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1;
-	hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY;
-	hperh->hdmatx.config.channel = channel;
-
-	if ((hperh->init.word_length == USART_WORD_LENGTH_9B)
-			&& (hperh->init.parity == USART_PARITY_NONE)) {
-		hperh->hdmatx.config.src_inc    = DMA_DATA_INC_HALFWORD;
-		hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
-	}
-
-	dma_config_basic(&hperh->hdmatx);
-
-	__UNLOCK(hperh);
-	usart_clear_flag_status(hperh, USART_FLAG_TC);
-	SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK);
-
-	return OK;
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be received
-  * @param  channel: DMA channel as USART receive
-  * @note   When the USART parity is enabled (PCE = 1), the received data contain
-  *         the parity bit (MSB position)
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
-{
-	if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX))
-		return BUSY;
-
-	if ((buf == NULL ) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-	SET_BIT(hperh->state, USART_STATE_RX_MASK);
-
-	hperh->rx_buf   = buf;
-	hperh->rx_size  = size;
-	hperh->err_code = USART_ERROR_NONE;
-
-	if (hperh->hdmarx.perh == NULL)
-		hperh->hdmarx.perh = DMA0;
-
-	/* Configure callback function */
-	hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt;
-	hperh->hdmarx.cplt_arg = (void *)hperh;
-	hperh->hdmarx.err_cbk  = usart_dma_error;
-	hperh->hdmarx.err_arg  = (void *)hperh;
-
-	/* Configure DMA Receive */
-	dma_config_struct(&hperh->hdmarx.config);
-	hperh->hdmarx.config.src     = (void *)&hperh->perh->DATA;
-	hperh->hdmarx.config.dst     = (void *)buf;
-	hperh->hdmarx.config.size    = size;
-	hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
-	hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE;
-	hperh->hdmarx.config.msel    = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1;
-	hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR;
-	hperh->hdmarx.config.channel = channel;
-
-	if ((hperh->init.word_length == USART_WORD_LENGTH_9B)
-			&& (hperh->init.parity == USART_PARITY_NONE)) {
-		hperh->hdmarx.config.dst_inc    = DMA_DATA_INC_HALFWORD;
-		hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD;
-	}
-
-	dma_config_basic(&hperh->hdmarx);
-
-	__UNLOCK(hperh);
-	SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK);
-
-	return OK;
-}
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Functions_Group2_2 Synchronization IO operation functions
-  *  @brief   Synchronization IO operation functions
-  *
-  * @verbatim
-  ==============================================================================
-                         ##### IO operation functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to manage the USART synchronous
-    data transfers.
-
-  [..]
-    The USART supports master mode only: it cannot receive or send data related to an input
-    clock (SCLK is always an output).
-
-    (#) There are two modes of transfer:
-        (++) Blocking mode: The communication is performed in polling mode.
-             The Status of all data processing is returned by the same function
-             after finishing transfer.
-        (++) No-Blocking mode: The communication is performed using Interrupts
-             or DMA, These API's return the Status.
-             The end of the data processing will be indicated through the
-             dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
-             using DMA mode.
-             The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() and hperh->tx_rx_cplt_cbk()
-             user callbacks will be executed respectively at the end of the transmit
-	     or Receive process. The hperh->error_cbk() user callback will be
-	     executed when a communication error is detected
-
-    (#) Blocking mode APIs are :
-        (++) usart_send_sync() in simplex mode
-        (++) usart_recv_sync() in full duplex receive only
-        (++) usart_send_recv_sync() in full duplex mode
-
-    (#) Non Blocking mode APIs with Interrupt are :
-        (++) usart_send_by_it_sync()in simplex mode
-        (++) usart_recv_by_it_sync() in full duplex receive only
-        (++) usart_send_recv_by_it_sync() in full duplex mode
-        (++) usart_irq_handle()
-
-    (#) Non Blocking mode functions with DMA are :
-        (++) usart_send_by_dma_sync()in simplex mode
-        (++) usart_recv_by_dma_sync() in full duplex receive only
-        (++) usart_send_recv_by_dma_symc() in full duplex mode
-        (++) usart_dma_pause()
-        (++) usart_dma_resume()
-        (++) usart_dma_stop()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) hperh->tx_cplt_cbk()
-        (++) hperh->rx_cplt_cbk()
-        (++) hperh->tx_rx_cplt_cbk()
-        (++) hperh->error_cbk()
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Simplex Send an amount of data in blocking mode.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
-{
-	if (hperh->state != USART_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	__LOCK(hperh);
-
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-	hperh->err_code = USART_ERROR_NONE;
-	hperh->state    = USART_STATE_BUSY_TX;
-
-	while (hperh->tx_count-- > 0) {
-		if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) {
-			__UNLOCK(hperh);
-			hperh->state = USART_STATE_READY;
-			return TIMEOUT;
-		}
-
-		if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE)) {
-			WRITE_REG(hperh->perh->DATA, (*(uint16_t *)buf & 0x1FF));
-			buf += 2;
-		}
-		else {
-			WRITE_REG(hperh->perh->DATA, *buf++);
-		}
-    	}
-
-	if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) {
-		__UNLOCK(hperh);
-		hperh->state = USART_STATE_READY;
-		return TIMEOUT;
-	}
-
-	hperh->state = USART_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Full-Duplex Receive an amount of data in blocking mode.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be received
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
-{
-	if (hperh->state != USART_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return  ERROR;
-
-	__LOCK(hperh);
-
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-	hperh->err_code = USART_ERROR_NONE;
-	hperh->state    = USART_STATE_BUSY_RX;
-
-	while (hperh->rx_count-- > 0) {
-		if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) {
-			__UNLOCK(hperh);
-			hperh->state = USART_STATE_READY;
-			return TIMEOUT;
-		}
-
-		if (hperh->init.word_length == USART_WORD_LENGTH_9B) {
-			WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0x1FF));
-
-			if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) {
-				__UNLOCK(hperh);
-				hperh->state = USART_STATE_READY;
-				return TIMEOUT;
-			}
-
-			if (hperh->init.parity == USART_PARITY_NONE) {
-				*(uint16_t *)buf = (uint16_t)(hperh->perh->DATA & 0x1FF);
-				buf += 2;
-			}
-			else {
-				*buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
-			}
-		}
-		else {
-			WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0xFF));
-
-			if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) {
-				__UNLOCK(hperh);
-				hperh->state = USART_STATE_READY;
-				return TIMEOUT;
-			}
-
-			if (hperh->init.parity == USART_PARITY_NONE)
-				*buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
-			else
-				*buf++ = (uint8_t)(hperh->perh->DATA & 0x7F);
-		}
-	}
-
-	hperh->state = USART_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  tx_buf: Pointer to data transmitted buffer
-  * @param  rx_buf: Pointer to data received buffer
-  * @param  size: Amount of data to be sent
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout)
-{
-	if (hperh->state != USART_STATE_READY)
-		return BUSY;
-
-	if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0))
-		return  ERROR;
-
-	__LOCK(hperh);
-
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-	hperh->err_code = USART_ERROR_NONE;
-	hperh->state    = USART_STATE_BUSY_RX;
-
-	while (hperh->tx_count-- > 0) {
-		--hperh->rx_count;
-
-		if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) {
-			__UNLOCK(hperh);
-			hperh->state = USART_STATE_READY;
-			return TIMEOUT;
-		}
-
-		if (hperh->init.word_length == USART_WORD_LENGTH_9B) {
-			if (hperh->init.parity == USART_PARITY_NONE) {
-				WRITE_REG(hperh->perh->DATA, (*(uint16_t *)tx_buf & 0x1FF));
-				tx_buf += 2;
-			}
-			else {
-				WRITE_REG(hperh->perh->DATA, *tx_buf++);
-			}
-
-			if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) {
-				__UNLOCK(hperh);
-				hperh->state = USART_STATE_READY;
-				return TIMEOUT;
-			}
-
-			if (hperh->init.parity == USART_PARITY_NONE) {
-				*(uint16_t *)rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF);
-				rx_buf += 2;
-			}
-			else {
-				*rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
-			}
-		}
-		else {
-			WRITE_REG(hperh->perh->DATA, *tx_buf++);
-
-			if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) {
-				__UNLOCK(hperh);
-				hperh->state = USART_STATE_READY;
-				return TIMEOUT;
-			}
-
-			if (hperh->init.parity == USART_PARITY_NONE)
-				*rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
-			else
-				*rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F);
-		}
-	}
-
-	hperh->state = USART_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Simplex Send an amount of data in non-blocking mode.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @retval Status, see @ref ald_status_t.
-  * @note   The USART errors are not managed to avoid the overrun error.
-  */
-ald_status_t usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size)
-{
-	if (hperh->state != USART_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-
-	hperh->tx_buf   = buf;
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-	hperh->err_code = USART_ERROR_NONE;
-	hperh->state    = USART_STATE_BUSY_TX;
-
-	/* The USART Error Interrupts: (Frame error, Noise error, Overrun error)
-	 * are not managed by the USART transmit process to avoid the overrun interrupt
-	 * when the USART mode is configured for transmit and receive "USART_MODE_TX_RX"
-	 * to benefit for the frame error and noise interrupts the USART mode should be
-	 * configured only for transmit "USART_MODE_TX"
-	 * The __ALD_USART_ENABLE_IT(hperh, USART_IT_ERR) can be used to enable the Frame error,
-	 * Noise error interrupt
-	 */
-
-	__UNLOCK(hperh);
-	usart_interrupt_config(hperh, USART_IT_TXE, ENABLE);
-
-	return OK;
-}
-
-/**
-  * @brief  Simplex Receive an amount of data in non-blocking mode.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be received
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size)
-{
-	if (hperh->state != USART_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-
-	hperh->rx_buf   = buf;
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-	hperh->err_code = USART_ERROR_NONE;
-	hperh->state    = USART_STATE_BUSY_RX;
-
-	__UNLOCK(hperh);
-	usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE);
-	usart_interrupt_config(hperh, USART_IT_PE, ENABLE);
-	usart_interrupt_config(hperh, USART_IT_ERR, ENABLE);
-
-	WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & (uint16_t)0x01FF));
-	return OK;
-}
-
-/**
-  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  tx_buf: Pointer to data transmitted buffer
-  * @param  rx_buf: Pointer to data received buffer
-  * @param  size: Amount of data to be received
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf,  uint16_t size)
-{
-	if (hperh->state != USART_STATE_READY)
-		return BUSY;
-
-	if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-
-	hperh->rx_buf   = rx_buf;
-	hperh->rx_size  = size;
-	hperh->rx_count = size;
-	hperh->tx_buf   = tx_buf;
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-	hperh->err_code = USART_ERROR_NONE;
-	hperh->state    = USART_STATE_BUSY_TX_RX;
-
-	__UNLOCK(hperh);
-	usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE);
-	usart_interrupt_config(hperh, USART_IT_PE, ENABLE);
-	usart_interrupt_config(hperh, USART_IT_ERR, ENABLE);
-	usart_interrupt_config(hperh, USART_IT_TXE, ENABLE);
-
-	return OK;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  Simplex Send an amount of data in non-blocking mode.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be sent
-  * @param  channel: DMA channel as USART transmit
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
-{
-	if (hperh->state != USART_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-
-	hperh->tx_buf   = buf;
-	hperh->tx_size  = size;
-	hperh->tx_count = size;
-	hperh->err_code = USART_ERROR_NONE;
-	hperh->state    = USART_STATE_BUSY_TX;
-
-	if (hperh->hdmatx.perh == NULL)
-		hperh->hdmatx.perh = DMA0;
-
-	/* Configure callback function */
-	hperh->hdmatx.cplt_cbk = usart_dma_send_cplt;
-	hperh->hdmatx.cplt_arg = (void *)hperh;
-	hperh->hdmatx.err_cbk  = usart_dma_error;
-	hperh->hdmatx.err_arg  = (void *)hperh;
-
-	/* Configure DMA transmit */
-	dma_config_struct(&hperh->hdmatx.config);
-	hperh->hdmatx.config.src     = (void *)buf;
-	hperh->hdmatx.config.dst     = (void *)&hperh->perh->DATA;
-	hperh->hdmatx.config.size    = size;
-	hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE;
-	hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
-	hperh->hdmatx.config.msel    = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1;
-	hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY;
-	hperh->hdmatx.config.channel = channel;
-
-	if ((hperh->init.word_length == USART_WORD_LENGTH_9B)
-			&& (hperh->init.parity == USART_PARITY_NONE)) {
-		hperh->hdmatx.config.src_inc    = DMA_DATA_INC_HALFWORD;
-		hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
-	}
-
-	dma_config_basic(&hperh->hdmatx);
-
-	__UNLOCK(hperh);
-	usart_clear_flag_status(hperh, USART_FLAG_TC);
-	SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK);
-
-	return OK;
-}
-
-/**
-  * @brief  Full-Duplex Receive an amount of data in non-blocking mode.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: Amount of data to be received
-  * @param  tx_channel: DMA channel as USART transmit
-  * @param  rx_channel: DMA channel as USART receive
-  * @retval Status, see @ref ald_status_t.
-  * @note   The USART DMA transmit channel must be configured in order to generate the clock for the slave.
-  * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
-  */
-ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel)
-{
-	if (hperh->state != USART_STATE_READY)
-		return BUSY;
-
-	if ((buf == NULL) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-
-	hperh->rx_buf   = buf;
-	hperh->rx_size  = size;
-	hperh->tx_buf   = buf;
-	hperh->tx_size  = size;
-	hperh->err_code = USART_ERROR_NONE;
-	hperh->state    = USART_STATE_BUSY_RX;
-
-	if (hperh->hdmatx.perh == NULL)
-		hperh->hdmatx.perh = DMA0;
-	if (hperh->hdmarx.perh == NULL)
-		hperh->hdmarx.perh = DMA0;
-
-	/* Configure DMA callback function */
-	hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt;
-	hperh->hdmarx.cplt_arg = (void *)hperh;
-	hperh->hdmarx.err_cbk  = usart_dma_error;
-	hperh->hdmarx.err_arg  = (void *)hperh;
-
-	/* Configure DMA receive*/
-	dma_config_struct(&hperh->hdmarx.config);
-	hperh->hdmarx.config.src     = (void *)&hperh->perh->DATA;
-	hperh->hdmarx.config.dst     = (void *)buf;
-	hperh->hdmarx.config.size    = size;
-	hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
-	hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE;
-	hperh->hdmarx.config.msel    = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1;
-	hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR;
-	hperh->hdmarx.config.channel = rx_channel;
-
-	if ((hperh->init.word_length == USART_WORD_LENGTH_9B)
-			&& (hperh->init.parity == USART_PARITY_NONE)) {
-		hperh->hdmarx.config.dst_inc    = DMA_DATA_INC_HALFWORD;
-		hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD;
-	}
-
-	dma_config_basic(&hperh->hdmarx);
-
-	/* Enable the USART transmit DMA channel: the transmit channel is used in order
-	 * to generate in the non-blocking mode the clock to the slave device,
-	 * this mode isn't a simplex receive mode but a full-duplex receive one
-	 */
-	dma_config_struct(&hperh->hdmatx.config);
-	hperh->hdmatx.config.src     = (void *)buf;
-	hperh->hdmatx.config.dst     = (void *)&hperh->perh->DATA;
-	hperh->hdmatx.config.size    = size;
-	hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE;
-	hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
-	hperh->hdmatx.config.msel    = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1;
-	hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY;
-	hperh->hdmatx.config.channel = tx_channel;
-
-	if ((hperh->init.word_length == USART_WORD_LENGTH_9B)
-			&& (hperh->init.parity == USART_PARITY_NONE)) {
-		hperh->hdmatx.config.src_inc    = DMA_DATA_INC_HALFWORD;
-		hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
-	}
-
-	dma_config_basic(&hperh->hdmatx);
-
-	USART_CLEAR_OREFLAG(hperh);
-	__UNLOCK(hperh);
-	SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK);
-	SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK);
-
-	return OK;
-}
-
-/**
-  * @brief  Full-Duplex Transmit Receive an amount of data in non-blocking mode.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  tx_buf: Pointer to data transmitted buffer
-  * @param  rx_buf: Pointer to data received buffer
-  * @param  size: Amount of data to be received
-  * @param  tx_channel: DMA channel as USART transmit
-  * @param  rx_channel: DMA channel as USART receive
-  * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf,
-                    uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel)
-{
-	if (hperh->state != USART_STATE_READY)
-		return BUSY;
-
-	if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0))
-		return ERROR;
-
-	__LOCK(hperh);
-
-	hperh->rx_buf   = rx_buf;
-	hperh->rx_size  = size;
-	hperh->tx_buf   = tx_buf;
-	hperh->tx_size  = size;
-	hperh->err_code = USART_ERROR_NONE;
-	hperh->state    = USART_STATE_BUSY_TX_RX;
-
-	if (hperh->hdmatx.perh == NULL)
-		hperh->hdmatx.perh = DMA0;
-	if (hperh->hdmarx.perh == NULL)
-		hperh->hdmarx.perh = DMA0;
-
-	/* Configure DMA callback function */
-	hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt;
-	hperh->hdmarx.cplt_arg = (void *)hperh;
-	hperh->hdmatx.cplt_cbk = usart_dma_send_cplt;
-	hperh->hdmatx.cplt_arg = (void *)hperh;
-	hperh->hdmatx.err_cbk  = usart_dma_error;
-	hperh->hdmatx.err_arg  = (void *)hperh;
-	hperh->hdmarx.err_cbk  = usart_dma_error;
-	hperh->hdmarx.err_arg  = (void *)hperh;
-
-	/* Configure DMA receive */
-	dma_config_struct(&hperh->hdmarx.config);
-	hperh->hdmarx.config.src     = (void *)&hperh->perh->DATA;
-	hperh->hdmarx.config.dst     = (void *)rx_buf;
-	hperh->hdmarx.config.size    = size;
-	hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
-	hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE;
-	hperh->hdmarx.config.msel    = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1;
-	hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR;
-	hperh->hdmarx.config.channel = rx_channel;
-
-	if ((hperh->init.word_length == USART_WORD_LENGTH_9B)
-			&& (hperh->init.parity == USART_PARITY_NONE)) {
-		hperh->hdmarx.config.dst_inc    = DMA_DATA_INC_HALFWORD;
-		hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD;
-	}
-
-	dma_config_basic(&hperh->hdmarx);
-
-	/* Configure DMA transmit*/
-	dma_config_struct(&hperh->hdmatx.config);
-	hperh->hdmatx.config.src     = (void *)tx_buf;
-	hperh->hdmatx.config.dst     = (void *)&hperh->perh->DATA;
-	hperh->hdmatx.config.size    = size;
-	hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE;
-	hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
-	hperh->hdmatx.config.msel    = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1;
-	hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY;
-	hperh->hdmatx.config.channel = tx_channel;
-
-	if ((hperh->init.word_length == USART_WORD_LENGTH_9B)
-			&& (hperh->init.parity == USART_PARITY_NONE)) {
-		hperh->hdmatx.config.src_inc    = DMA_DATA_INC_HALFWORD;
-		hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
-	}
-
-	dma_config_basic(&hperh->hdmatx);
-
-	usart_clear_flag_status(hperh, USART_FLAG_TC);
-	USART_CLEAR_OREFLAG(hperh);
-	__UNLOCK(hperh);
-	SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK);
-	SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK);
-
-	return OK;
-}
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Functions_Group2_3 Utilities functions
-  * @brief    Utilities functions
-  * @{
-  */
-#ifdef ALD_DMA
-/**
-  * @brief  Pauses the DMA Transfer.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_dma_pause(usart_handle_t *hperh)
-{
-	__LOCK(hperh);
-
-	if (hperh->state == USART_STATE_BUSY_TX) {
-		CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK);
-	}
-	else if (hperh->state == USART_STATE_BUSY_RX) {
-		CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK);
-	}
-	else if (hperh->state == USART_STATE_BUSY_TX_RX) {
-		CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK);
-		CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK);
-	}
-	else {
-		__UNLOCK(hperh);
-		return ERROR;
-	}
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Resumes the DMA Transfer.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_dma_resume(usart_handle_t *hperh)
-{
-	__LOCK(hperh);
-
-	if (hperh->state == USART_STATE_BUSY_TX) {
-		SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK);
-	}
-	else if (hperh->state == USART_STATE_BUSY_RX) {
-		USART_CLEAR_OREFLAG(hperh);
-		SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK);
-	}
-	else if (hperh->state == USART_STATE_BUSY_TX_RX) {
-		USART_CLEAR_OREFLAG(hperh);
-		SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK);
-		SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK);
-	}
-	else {
-		__UNLOCK(hperh);
-		return ERROR;
-	}
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Stops the DMA Transfer.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_dma_stop(usart_handle_t *hperh)
-{
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK);
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK);
-
-	hperh->state = USART_STATE_READY;
-	return OK;
-}
-#endif
-/**
-  * @brief  This function handles USART interrupt request.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval None
-  */
-void usart_irq_handle(usart_handle_t *hperh)
-{
-	uint32_t flag;
-	uint32_t source;
-
-	/* Handle parity error */
-	flag   = usart_get_flag_status(hperh, USART_FLAG_PE);
-	source = usart_get_it_status(hperh, USART_IT_PE);
-	if ((flag != RESET) && (source != RESET))
-		hperh->err_code |= USART_ERROR_PE;
-
-	/* Handle frame error */
-	flag   = usart_get_flag_status(hperh, USART_FLAG_FE);
-	source = usart_get_it_status(hperh, USART_IT_ERR);
-	if ((flag != RESET) && (source != RESET))
-		hperh->err_code |= USART_ERROR_FE;
-
-	/* Handle noise error */
-	flag = usart_get_flag_status(hperh, USART_FLAG_NE);
-	if ((flag != RESET) && (source != RESET))
-		hperh->err_code |= USART_ERROR_NE;
-
-	/* Handle overrun error */
-	flag = usart_get_flag_status(hperh, USART_FLAG_ORE);
-	if ((flag != RESET) && (source != RESET))
-		hperh->err_code |= USART_ERROR_ORE;
-
-	/* Handle idle error */
-	flag   = usart_get_flag_status(hperh, USART_FLAG_IDLE);
-	source = usart_get_it_status(hperh, USART_IT_IDLE);
-	if ((flag != RESET) && (source != RESET))
-		__usart_recv_frame_cplt(hperh);
-
-	/* Handle asynchronous */
-	if (READ_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK) == 0) {
-		/* Receiver */
-		flag   = usart_get_flag_status(hperh, USART_FLAG_RXNE);
-		source = usart_get_it_status(hperh, USART_IT_RXNE);
-		if ((flag != RESET) && (source != RESET))
-			__usart_recv_by_it(hperh);
-
-		/* Transmitter */
-		flag   = usart_get_flag_status(hperh, USART_FLAG_TXE);
-		source = usart_get_it_status(hperh, USART_IT_TXE);
-		if ((flag != RESET) && (source != RESET))
-			__usart_send_by_it(hperh);
-	}
-	else {	/* Handle synchronous */
-		/* Receiver */
-		flag   = usart_get_flag_status(hperh, USART_FLAG_RXNE);
-		source = usart_get_it_status(hperh, USART_IT_RXNE);
-		if ((flag != RESET) && (source != RESET)) {
-			if (hperh->state == USART_STATE_BUSY_RX)
-				__usart_recv_by_it_sync(hperh);
-			else
-				__usart_send_recv_by_it_sync(hperh);
-		}
-
-		/* Transmitter */
-		flag   = usart_get_flag_status(hperh, USART_FLAG_TXE);
-		source = usart_get_it_status(hperh, USART_IT_TXE);
-		if ((flag != RESET) && (source != RESET)) {
-			if (hperh->state == USART_STATE_BUSY_TX)
-				__usart_send_by_it(hperh);
-			else
-				__usart_send_recv_by_it_sync(hperh);
-		}
-	}
-
-	/* Handle transmitter end */
-	flag   = usart_get_flag_status(hperh, USART_FLAG_TC);
-	source = usart_get_it_status(hperh, USART_IT_TC);
-	if ((flag != RESET) && (source != RESET))
-		__usart_end_send_by_it(hperh);
-
-	/* Handle error */
-	if (hperh->err_code != USART_ERROR_NONE) {
-		USART_CLEAR_PEFLAG(hperh);
-		hperh->state = USART_STATE_READY;
-
-		if (hperh->error_cbk != NULL)
-			hperh->error_cbk(hperh);
-	}
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Functions_Group3 Peripheral Control functions
-  *  @brief   USART control functions
-  *
-  * @verbatim
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to control the USART:
-    (+) usart_lin_send_break() API can be helpful to transmit the break character.
-    (+) usart_multi_processor_enter_mute_mode() API can be helpful to enter the USART in mute mode.
-    (+) usart_multi_processor_exit_mute_mode() API can be helpful to exit the USART mute mode by software.
-    (+) usart_half_duplex_enable_send() API to enable the USART transmitter and disables the USART receiver in Half Duplex mode
-    (+) usart_half_duplex_enable_recv() API to enable the USART receiver and disables the USART transmitter in Half Duplex mode
-    (+) usart_interrupt_config() API to Enables/Disables the specified USART interrupts
-    (+) usart_get_flag_status() API to get USART flag status
-    (+) usart_clear_flag_status() API to clear USART flag status
-    (+) usart_get_it_status() API to Checks whether the specified USART interrupt has occurred or not
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enters the USART in mute mode.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_multi_processor_enter_mute_mode(usart_handle_t *hperh)
-{
-	assert_param(IS_USART(hperh->perh));
-
-	__LOCK(hperh);
-
-	hperh->state = USART_STATE_BUSY;
-	SET_BIT(hperh->perh->CON0, USART_CON0_RXWK_MSK);
-	hperh->state = USART_STATE_READY;
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Exits the USART mute mode: wake up software.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_multi_processor_exit_mute_mode(usart_handle_t *hperh)
-{
-	assert_param(IS_USART(hperh->perh));
-
-	__LOCK(hperh);
-
-	hperh->state = USART_STATE_BUSY;
-	CLEAR_BIT(hperh->perh->CON0, USART_CON0_RXWK_MSK);
-	hperh->state = USART_STATE_READY;
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Enables the USART transmitter and disables the USART receiver.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_half_duplex_enable_send(usart_handle_t *hperh)
-{
-	__LOCK(hperh);
-
-	hperh->state = USART_STATE_BUSY;
-	SET_BIT(hperh->perh->CON0, USART_CON0_RXEN_MSK);
-	SET_BIT(hperh->perh->CON0, USART_CON0_TXEN_MSK);
-	hperh->state = USART_STATE_READY;
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Enables the USART receiver and disables the USART transmitter.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t usart_half_duplex_enable_recv(usart_handle_t *hperh)
-{
-	__LOCK(hperh);
-
-	hperh->state = USART_STATE_BUSY;
-	SET_BIT(hperh->perh->CON0, USART_CON0_RXEN_MSK);
-	SET_BIT(hperh->perh->CON0, USART_CON0_TXEN_MSK);
-	hperh->state = USART_STATE_READY;
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Enables or disables the USART's DMA request.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  req: specifies the DMA request.
-  *	      @arg USART_dma_req_tx: USART DMA transmit request
-  *	      @arg USART_dma_req_rx: USART DMA receive request
-  * @param  state: New state of the DMA Request sources.
-  *	      @arg ENABLE
-  *           @arg DISABLE
-  * @return: None
-  */
-void usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_t state)
-{
-	assert_param(IS_USART(hperh->perh));
-	assert_param(IS_USART_DMAREQ(req));
-	assert_param(IS_FUNC_STATE(state));
-
-	if (state != DISABLE)
-		SET_BIT(hperh->perh->CON2, req);
-	else
-		CLEAR_BIT(hperh->perh->CON2, req);
-
-	return;
-}
-
-/**
-  * @brief  Enables or disables the specified USART interrupts.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  it: Specifies the USART interrupt sources to be enabled or disabled.
-  *           This parameter can be one of the following values:
-  *           @arg USART_IT_CTS:  CTS change interrupt
-  *           @arg USART_IT_LBD:  LIN Break detection interrupt
-  *           @arg USART_IT_TXE:  Transmit Data Register empty interrupt
-  *           @arg USART_IT_TC:   Transmission complete interrupt
-  *           @arg USART_IT_RXNE: Receive Data register not empty interrupt
-  *           @arg USART_IT_IDLE: Idle line detection interrupt
-  *           @arg USART_IT_PE:   Parity Error interrupt
-  *           @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @param  state: New status
-  *           - ENABLE
-  *           - DISABLE
-  * @retval None
-  */
-void usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t state)
-{
-	uint8_t idx;
-
-	assert_param(IS_USART(hperh->perh));
-	assert_param(IS_USART_CONFIG_IT(it));
-	assert_param(IS_FUNC_STATE(state));
-
-	idx = (it >> 16) & 0x7;
-	it &= 0xFFFF;
-
-	if (state) {
-		if (idx == 1)
-			SET_BIT(hperh->perh->CON0, it);
-		else if (idx == 2)
-			SET_BIT(hperh->perh->CON1, it);
-		else if (idx == 4)
-			SET_BIT(hperh->perh->CON2, it);
-		else
-			;
-	}
-	else {
-		if (idx == 1)
-			CLEAR_BIT(hperh->perh->CON0, it);
-		else if (idx == 2)
-			CLEAR_BIT(hperh->perh->CON1, it);
-		else if (idx == 4)
-			CLEAR_BIT(hperh->perh->CON2, it);
-		else
-			;
-	}
-
-	return;
-}
-
-/** @brief  Check whether the specified USART flag is set or not.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  flag: specifies the flag to check.
-  *         This parameter can be one of the @ref usart_flag_t.
-  * @retval Status
-  *           - SET
-  *           - RESET
-  */
-flag_status_t usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag)
-{
-	flag_status_t status = RESET;
-
-	assert_param(IS_USART(hperh->perh));
-	assert_param(IS_USART_FLAG(flag));
-
-	if (READ_BIT(hperh->perh->STAT, flag))
-		status = SET;
-
-	return status;
-}
-
-/** @brief  Clear the specified USART pending flags.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  flag: specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg USART_FLAG_TC:   Transmission Complete flag.
-  *            @arg USART_FLAG_RXNE: Receive data register not empty flag.
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
-  *          error) and IDLE (Idle line detected) flags are cleared by software
-  *          sequence: a read operation to USART_SR register followed by a read
-  *          operation to USART_DR register.
-  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to
-  *         USART_SR register followed by a write operation to USART_DR register.
-  * @note   TXE flag is cleared only by a write to the USART_DR register.
-  * @retval None
-  */
-void usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag)
-{
-	assert_param(IS_USART(hperh->perh));
-	assert_param(IS_USART_CLEAR_FLAG(flag));
-
-	CLEAR_BIT(hperh->perh->STAT, flag);
-}
-
-/**
-  * @brief  Checks whether the specified USART interrupt has occurred or not.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  it: Specifies the USART interrupt source to check.
-  *	       This parameter can be one of the following values:
-  *	       @arg USART_IT_CTS:  CTS change interrupt
-  *	       @arg USART_IT_LBD:  LIN Break detection interrupt
-  *	       @arg USART_IT_TXE:  Tansmit Data Register empty interrupt
-  *	       @arg USART_IT_TC:   Transmission complete interrupt
-  *	       @arg USART_IT_RXNE: Receive Data register not empty interrupt
-  *	       @arg USART_IT_IDLE: Idle line detection interrupt
-  *	       @arg USART_IT_ORE:  OverRun Error interrupt
-  *	       @arg USART_IT_NE:   Noise Error interrupt
-  *	       @arg USART_IT_FE:   Framing Error interrupt
-  *	       @arg USART_IT_PE:   Parity Error interrupt
-  * @retval Status
-  *           - SET
-  *           - RESET
-  */
-it_status_t usart_get_it_status(usart_handle_t *hperh, usart_it_t it)
-{
-	uint8_t idx;
-	it_status_t status = RESET;
-
-	/* Check the parameters */
-	assert_param(IS_USART(hperh->perh));
-	assert_param(IS_USART_GET_IT(it));
-
-	idx = (it >> 16) & 0x7;
-	it &= 0xFFFF;
-
-	if (idx == 0) {
-		if (READ_BIT(hperh->perh->STAT, it))
-			status = SET;
-	}
-	else if (idx == 1) {
-		if (READ_BIT(hperh->perh->CON0, it))
-			status = SET;
-	}
-	else if (idx == 2) {
-		if (READ_BIT(hperh->perh->CON1, it))
-			status = SET;
-	}
-	else if (idx == 4) {
-		if (READ_BIT(hperh->perh->CON2, it))
-			status = SET;
-	}
-	else {
-		/* do nothing */
-	}
-
-	return status;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Public_Functions_Group4 Peripheral State and Errors functions
-  *  @brief   USART State and Errors functions
-  *
-@verbatim
-  ==============================================================================
-                 ##### Peripheral State and Errors functions #####
-  ==============================================================================
- [..]
-   This subsection provides a set of functions allowing to return the State of
-   USART communication process, return Peripheral Errors occurred during communication
-   process
-   (+) usart_get_state() API can be helpful to check in run-time the state of the USART peripheral.
-   (+) usart_get_error() check in run-time errors that could be occurred during communication.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the USART state.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval USART state
-  */
-usart_state_t usart_get_state(usart_handle_t *hperh)
-{
-	return hperh->state;
-}
-
-/**
-  * @brief  Return the USART error code
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART.
-  * @retval USART Error Code
-  */
-uint32_t usart_get_error(usart_handle_t *hperh)
-{
-	return hperh->err_code;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Private_Functions   USART Private Functions
-  *  @brief   USART Private functions
-  * @{
-  */
-#ifdef ALD_DMA
-/**
-  * @brief  DMA USART transmit process complete callback.
-  * @param  arg: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval None
-  */
-static void usart_dma_send_cplt(void *arg)
-{
-	usart_handle_t *hperh = (usart_handle_t *)arg;
-
-	hperh->tx_count = 0;
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK);
-	usart_interrupt_config(hperh, USART_IT_TC, ENABLE);
-}
-
-/**
-  * @brief  DMA USART receive process complete callback.
-  * @param  arg: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval None
-  */
-static void usart_dma_recv_cplt(void *arg)
-{
-	usart_handle_t *hperh = (usart_handle_t *)arg;
-
-	hperh->rx_count = 0;
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK);
-	CLEAR_BIT(hperh->state, USART_STATE_RX_MASK);
-
-	if (hperh->rx_cplt_cbk != NULL)
-		hperh->rx_cplt_cbk(hperh);
-}
-
-/**
-  * @brief  DMA USART communication error callback.
-  * @param  arg: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval None
-  */
-static void usart_dma_error(void *arg)
-{
-	usart_handle_t *hperh = (usart_handle_t *)arg;
-
-	hperh->rx_count  = 0;
-	hperh->tx_count  = 0;
-	hperh->state     = USART_STATE_READY;
-	hperh->err_code |= USART_ERROR_DMA;
-
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK);
-	CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK);
-
-	if (hperh->error_cbk != NULL)
-		hperh->error_cbk(hperh);
-}
-#endif
-/**
-  * @brief  This function handles USART Communication Timeout.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @param  flag: specifies the USART flag to check.
-  * @param  status: The new Flag status (SET or RESET).
-  * @param  timeout: Timeout duration
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout)
-{
-	uint32_t tick;
-
-	if (timeout == 0)
-		return OK;
-
-	tick = __get_tick();
-
-	while ((usart_get_flag_status(hperh, flag)) != status) {
-		if (((__get_tick()) - tick) > timeout) {
-			usart_interrupt_config(hperh, USART_IT_TXE, DISABLE);
-			usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE);
-			usart_interrupt_config(hperh, USART_IT_PE, DISABLE);
-			usart_interrupt_config(hperh, USART_IT_ERR, DISABLE);
-
-			return TIMEOUT;
-		}
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t __usart_send_by_it(usart_handle_t *hperh)
-{
-	if ((hperh->state != USART_STATE_BUSY_TX) && (hperh->state != USART_STATE_BUSY_TX_RX))
-		return BUSY;
-
-	if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE)) {
-		WRITE_REG(hperh->perh->DATA, (uint16_t)(*(uint16_t *)hperh->tx_buf & (uint16_t)0x01FF));
-		hperh->tx_buf += 2;
-	}
-	else {
-		WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++);
-	}
-
-	if (--hperh->tx_count == 0) {
-		usart_interrupt_config(hperh, USART_IT_TXE, DISABLE);
-		usart_interrupt_config(hperh, USART_IT_TC, ENABLE);
-	}
-
-	return OK;
-}
-
-
-/**
-  * @brief  Wraps up transmission in non blocking mode.
-  * @param  hperh: pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t __usart_end_send_by_it(usart_handle_t *hperh)
-{
-	usart_interrupt_config(hperh, USART_IT_TC, DISABLE);
-	CLEAR_BIT(hperh->state, USART_STATE_TX_MASK);
-
-	if (hperh->tx_cplt_cbk != NULL)
-		hperh->tx_cplt_cbk(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t __usart_recv_by_it(usart_handle_t *hperh)
-{
-	if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX))
-		return BUSY;
-
-	if (hperh->init.word_length == USART_WORD_LENGTH_9B) {
-		if (hperh->init.parity == USART_PARITY_NONE) {
-			*(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & (uint16_t)0x01FF);
-			hperh->rx_buf += 2;
-		}
-		else {
-			*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
-		}
-    	}
-	else {
-		if (hperh->init.parity == USART_PARITY_NONE)
-			*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
-		else
-			*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F);
-	}
-
-	if (__frame_mode && ((usart_get_it_status(hperh, USART_IT_IDLE)) == RESET))
-		usart_interrupt_config(hperh, USART_IT_IDLE, ENABLE);
-
-	if (--hperh->rx_count == 0) {
-		usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE);
-		CLEAR_BIT(hperh->state, USART_STATE_RX_MASK);
-		__frame_mode = 0;
-
-		if (hperh->state == USART_STATE_READY) {
-			usart_interrupt_config(hperh, USART_IT_PE, DISABLE);
-			usart_interrupt_config(hperh, USART_IT_ERR, DISABLE);
-		}
-
-		if (hperh->rx_cplt_cbk != NULL)
-			hperh->rx_cplt_cbk(hperh);
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  Receives an frame complete in non blocking mode
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh)
-{
-	if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX))
-		return BUSY;
-
-	usart_interrupt_config(hperh, USART_IT_IDLE, DISABLE);
-	usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE);
-	CLEAR_BIT(hperh->state, USART_STATE_RX_MASK);
-
-	__frame_mode    = 0;
-	hperh->rx_size -= hperh->rx_count;
-
-	if (hperh->state == USART_STATE_READY) {
-		usart_interrupt_config(hperh, USART_IT_PE, DISABLE);
-		usart_interrupt_config(hperh, USART_IT_ERR, DISABLE);
-	}
-
-	if (hperh->rx_cplt_cbk != NULL)
-		hperh->rx_cplt_cbk(hperh);
-
-	return OK;
-}
-
-
-
-/**
-  * @brief  Simplex Receive an amount of data in non-blocking mode.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh)
-{
-	if (hperh->state != USART_STATE_BUSY_RX)
-		return BUSY;
-
-	if (hperh->init.word_length == USART_WORD_LENGTH_9B) {
-
-		if (hperh->init.parity == USART_PARITY_NONE) {
-			*(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF);
-			hperh->rx_buf += 2;
-		}
-		else {
-			*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
-		}
-
-		if (--hperh->rx_count != 0x00)
-			WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0x1FF));
-	}
-	else {
-		if (hperh->init.parity == USART_PARITY_NONE)
-			*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
-		else
-			*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F);
-
-		if (--hperh->rx_count != 0x00)
-			hperh->perh->DATA = (DUMMY_DATA & 0xFF);
-	}
-
-	if (hperh->rx_count == 0) {
-		usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE);
-		usart_interrupt_config(hperh, USART_IT_PE, DISABLE);
-		usart_interrupt_config(hperh, USART_IT_ERR, DISABLE);
-		hperh->state = USART_STATE_READY;
-
-		if (hperh->rx_cplt_cbk != NULL)
-			hperh->rx_cplt_cbk(hperh);
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval Status, see @ref ald_status_t.
-  */
-static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh)
-{
-	if (hperh->state != USART_STATE_BUSY_TX_RX)
-		return BUSY;
-
-	if (hperh->tx_count != 0) {
-		if (usart_get_flag_status(hperh, USART_FLAG_TXE) != RESET) {
- 			if (hperh->init.word_length == USART_WORD_LENGTH_9B) {
-				if (hperh->init.parity == USART_PARITY_NONE) {
-					WRITE_REG(hperh->perh->DATA, (uint16_t)(*(uint16_t *)hperh->tx_buf & 0x1FF));
-					hperh->tx_buf += 2;
-				}
-				else {
-					WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++);
-				}
-			}
-			else {
-				WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++);
-			}
-
-			if (--hperh->tx_count == 0)
-				usart_interrupt_config(hperh, USART_IT_TXE, DISABLE);
-		}
-	}
-
-	if (hperh->rx_count != 0) {
-		if (usart_get_flag_status(hperh, USART_FLAG_RXNE) != RESET) {
-			if (hperh->init.word_length == USART_WORD_LENGTH_9B) {
-				if (hperh->init.parity == USART_PARITY_NONE) {
-					*(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF);
-					hperh->rx_buf += 2;
-				}
-				else {
-					*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
-				}
-			}
-			else {
-				if (hperh->init.parity == USART_PARITY_NONE)
-					*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
-				else
-					*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F);
-			}
-
-			--hperh->rx_count;
-		}
-	}
-
-	if (hperh->rx_count == 0) {
-		usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE);
-		usart_interrupt_config(hperh, USART_IT_PE, DISABLE);
-		usart_interrupt_config(hperh, USART_IT_ERR, DISABLE);
-
-		hperh->state = USART_STATE_READY;
-
-		if (hperh->tx_rx_cplt_cbk != NULL)
-			hperh->tx_rx_cplt_cbk(hperh);
-	}
-
-	return OK;
-}
-
-/**
-  * @brief  Configures the USART peripheral.
-  * @param  hperh: Pointer to a usart_handle_t structure that contains
-  *         the configuration information for the specified USART module.
-  * @retval None
-  */
-static void usart_set_config (usart_handle_t *hperh)
-{
-	uint32_t tmp;
-	uint32_t integer;
-	uint32_t fractional;
-
-	/* Check the parameters */
-	assert_param(IS_USART(hperh->perh));
-	assert_param(IS_USART_BAUDRATE(hperh->init.baud));
-	assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length));
-	assert_param(IS_USART_STOPBITS(hperh->init.stop_bits));
-	assert_param(IS_USART_PARITY(hperh->init.parity));
-	assert_param(IS_USART_MODE(hperh->init.mode));
-	assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl));
-
-	MODIFY_REG(hperh->perh->CON1, USART_CON1_STPLEN_MSK, hperh->init.stop_bits << USART_CON1_STPLEN_POSS);
-	tmp = READ_REG(hperh->perh->CON0);
-	MODIFY_REG(tmp, USART_CON0_DLEN_MSK, hperh->init.word_length << USART_CON0_DLEN_POS);
-
-	if (hperh->init.parity == USART_PARITY_NONE)
-		CLEAR_BIT(tmp, USART_CON0_PEN_MSK);
-	else
-		SET_BIT(tmp, USART_CON0_PEN_MSK);
-
-	if (hperh->init.parity == USART_PARITY_ODD)
-		SET_BIT(tmp, USART_CON0_PSEL_MSK);
-	else
-		CLEAR_BIT(tmp, USART_CON0_PSEL_MSK);
-
-	WRITE_REG(hperh->perh->CON0, tmp);
-	MODIFY_REG(hperh->perh->CON2, USART_CON2_RTSEN_MSK, (hperh->init.fctl & 0x1) << USART_CON2_RTSEN_POS);
-	MODIFY_REG(hperh->perh->CON2, USART_CON2_CTSEN_MSK, ((hperh->init.fctl >> 1) & 0x1) << USART_CON2_CTSEN_POS);
-	MODIFY_REG(hperh->perh->CON0, USART_CON0_RXEN_MSK, (hperh->init.mode & 0x1) << USART_CON0_RXEN_POS);
-	MODIFY_REG(hperh->perh->CON0, USART_CON0_TXEN_MSK, ((hperh->init.mode >> 1) & 0x1) << USART_CON0_TXEN_POS);
-
-	if (hperh->init.over_sampling)
-		SET_BIT(hperh->perh->CON0, (1 << 15));
-
-	/* Determine the integer part */
-	if (READ_BIT(hperh->perh->CON0, (1 << 15))) {
-		/* Integer part computing in case Oversampling mode is 8 Samples */
-		integer = ((25 * cmu_get_pclk1_clock()) / (2 * (hperh->init.baud)));
-	}
-	else {
-		/* Integer part computing in case Oversampling mode is 16 Samples */
-		integer = ((25 * cmu_get_pclk1_clock()) / (4 * (hperh->init.baud)));
-	}
-	tmp = (integer / 100) << 4;
-
-	/* Determine the fractional part */
-	fractional = integer - (100 * (tmp >> 4));
-
-	/* Implement the fractional part in the register */
-	if (READ_BIT(hperh->perh->CON0, (1 << 15)))
-    		tmp |= ((((fractional * 8) + 50) / 100) & ((uint8_t)0x07));
-	else
-		tmp |= ((((fractional * 16) + 50) / 100) & ((uint8_t)0x0F));
-
-	WRITE_REG(hperh->perh->BAUDCON, (uint16_t)tmp);
-	return;
-}
-/**
-  * @}
-  */
-
-#endif /* ALD_USART */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

bsp/es32f0334/.config → bsp/essemi/es32f0334/.config

@@ -7,6 +7,7 @@
 # RT-Thread Kernel
 #
 CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
 # CONFIG_RT_USING_SMP is not set
 CONFIG_RT_ALIGN_SIZE=4
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
@@ -63,7 +64,8 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
-CONFIG_RT_VER_NUM=0x40001
+CONFIG_RT_VER_NUM=0x40002
+# CONFIG_RT_USING_CPU_FFS is not set
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
@@ -108,6 +110,7 @@ CONFIG_FINSH_ARG_MAX=10
 #
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
 # CONFIG_RT_SERIAL_USING_DMA is not set
 CONFIG_RT_SERIAL_RB_BUFSZ=64
@@ -120,7 +123,6 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
-# CONFIG_RT_USING_MTD is not set
 # CONFIG_RT_USING_PM is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
@@ -128,10 +130,10 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
-
-#
-# Using WiFi
-#
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
 # CONFIG_RT_USING_WIFI is not set
 
 #
@@ -145,6 +147,7 @@ CONFIG_RT_USING_PIN=y
 #
 # CONFIG_RT_USING_LIBC is not set
 # CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_LIBC_USING_TIME is not set
 
 #
 # Network
@@ -156,14 +159,14 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_SAL is not set
 
 #
-# light weight TCP/IP stack
+# Network interface device
 #
-# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_NETDEV is not set
 
 #
-# Modbus master and slave stack
+# light weight TCP/IP stack
 #
-# CONFIG_RT_USING_MODBUS is not set
+# CONFIG_RT_USING_LWIP is not set
 
 #
 # AT commands
@@ -178,7 +181,6 @@ CONFIG_RT_USING_PIN=y
 #
 # Utilities
 #
-# CONFIG_RT_USING_LOGTRACE is not set
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
@@ -192,10 +194,14 @@ CONFIG_RT_USING_PIN=y
 #
 # CONFIG_PKG_USING_PAHOMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
 # CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
 # CONFIG_PKG_USING_LJSON is not set
 # CONFIG_PKG_USING_EZXML is not set
 # CONFIG_PKG_USING_NANOPB is not set
@@ -213,10 +219,14 @@ CONFIG_RT_USING_PIN=y
 # Wiced WiFi
 #
 # CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
 # CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
 
 #
 # IoT Cloud
@@ -225,6 +235,22 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
 
 #
 # security packages
@@ -245,6 +271,9 @@ CONFIG_RT_USING_PIN=y
 #
 # CONFIG_PKG_USING_OPENMV is not set
 # CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
 
 #
 # tools packages
@@ -253,6 +282,13 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
 
 #
 # system packages
@@ -266,17 +302,43 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
 
 #
 # peripheral libraries and drivers
 #
-# CONFIG_PKG_USING_STM32F4_HAL is not set
-# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_SHT2X is not set
-# CONFIG_PKG_USING_AHT10 is not set
-# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_SHT3X is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_LCD_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
 
 #
 # miscellaneous packages
@@ -287,13 +349,15 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
 # CONFIG_PKG_USING_ZLIB is not set
 # CONFIG_PKG_USING_DSTR is not set
-
-#
-# sample package
-#
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
 
 #
 # samples: kernel and components samples
@@ -302,12 +366,15 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
 # CONFIG_PKG_USING_NETWORK_SAMPLES is not set
 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
-
-#
-# example package: hello
-#
 # CONFIG_PKG_USING_HELLO is not set
-CONFIG_SOC_ES32F0334LT=y
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
 
 #
 # Hardware Drivers Config
@@ -375,3 +442,4 @@ CONFIG_BSP_USING_UART1=y
 #
 # Offboard Peripheral Drivers
 #
+CONFIG_SOC_ES32F0334LT=y

bsp/es32f0334/Kconfig → bsp/essemi/es32f0334/Kconfig

@@ -8,7 +8,7 @@ config BSP_DIR
 config RTT_DIR
     string
     option env="RTT_ROOT"
-    default "../.."
+    default "../../.."
 
 config PKGS_DIR
     string
@@ -17,11 +17,10 @@ config PKGS_DIR
 
 source "$RTT_DIR/Kconfig"
 source "$PKGS_DIR/Kconfig"
+source "drivers/Kconfig"
 
 config SOC_ES32F0334LT
     bool
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
     default y
-
-source "drivers/Kconfig"

bsp/es32f0334/SConstruct → bsp/essemi/es32f0334/SConstruct

@@ -5,7 +5,7 @@ import rtconfig
 if os.getenv('RTT_ROOT'):
     RTT_ROOT = os.getenv('RTT_ROOT')
 else:
-    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
 
 sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
 try:

bsp/es32f0334/drivers/SConscript → bsp/essemi/es32f0334/drivers/SConscript

@@ -42,6 +42,7 @@ if GetDepend(['BSP_USING_RTC']):
 # add pm driver code
 if GetDepend(['BSP_USING_PM']):
     src += ['drv_pm.c']
+    src += ['drv_lptim.c']
 
 # add adc driver code
 if GetDepend(['BSP_USING_ADC']):

bsp/es32f0334/drivers/board.c → bsp/essemi/es32f0334/drivers/board.c

@@ -43,10 +43,10 @@ void NVIC_Configuration(void)
 void  SystemClock_Config(void)
 {
     /* hosc 12MHz, from hosc/3 pll to 48MHz */
-    cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_48M);
+    ald_cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_48M);
 
     /* MCLK 48MHz */
-    cmu_clock_config(CMU_CLOCK_PLL1, 48000000);
+    ald_cmu_clock_config(CMU_CLOCK_PLL1, 48000000);
 }
 
 /*******************************************************************************
@@ -59,14 +59,14 @@ void  SystemClock_Config(void)
 void  SysTick_Configuration(void)
 {
     /* ticks = sysclk / RT_TICK_PER_SECOND */
-    SysTick_Config(cmu_get_sys_clock() / RT_TICK_PER_SECOND);
+    SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND);
 }
 
 /**
  * This is the timer interrupt service routine.
  *
  */
-void systick_irq_cbk(void)
+void SysTick_Handler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
@@ -113,7 +113,7 @@ void rt_hw_us_delay(rt_uint32_t us)
     unsigned int start, now, delta, reload, us_tick;
     start = SysTick->VAL;
     reload = SysTick->LOAD;
-    us_tick = cmu_get_sys_clock() / 1000000UL;
+    us_tick = ald_cmu_get_sys_clock() / 1000000UL;
     do
     {
         now = SysTick->VAL;

bsp/es32f0334/drivers/board.h → bsp/essemi/es32f0334/drivers/board.h

@@ -12,6 +12,7 @@
 #ifndef __BOARD_H__
 #define __BOARD_H__
 
+#include <rtthread.h>
 #include <es32f033x.h>
 
 #define ES32F0_SRAM_SIZE    0x8000

bsp/es32f0334/drivers/drv_adc.c → bsp/essemi/es32f0334/drivers/drv_adc.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author        Notes
  * 2019-04-08     wangyq        the first version
+ * 2019-11-01     wangyq        update libraries
  */
 
 #include <rthw.h>
@@ -58,67 +59,67 @@ static adc_channel_t es32f0_adc_get_channel(rt_uint32_t channel)
     {
     case  0:
         es32f0_channel = ADC_CHANNEL_0;
-        gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct);
+        ald_gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct);
         break;
     case  1:
         es32f0_channel = ADC_CHANNEL_1;
-        gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct);
+        ald_gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct);
         break;
     case  2:
         es32f0_channel = ADC_CHANNEL_2;
-        gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct);
+        ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct);
         break;
     case  3:
         es32f0_channel = ADC_CHANNEL_3;
-        gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct);
+        ald_gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct);
         break;
     case  4:
         es32f0_channel = ADC_CHANNEL_4;
-        gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct);
+        ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct);
         break;
     case  5:
         es32f0_channel = ADC_CHANNEL_5;
-        gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct);
+        ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct);
         break;
     case  6:
         es32f0_channel = ADC_CHANNEL_6;
-        gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct);
+        ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct);
         break;
     case  7:
         es32f0_channel = ADC_CHANNEL_7;
-        gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct);
+        ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct);
         break;
     case  8:
         es32f0_channel = ADC_CHANNEL_8;
-        gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct);
+        ald_gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct);
         break;
     case  9:
         es32f0_channel = ADC_CHANNEL_9;
-        gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct);
+        ald_gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct);
         break;
     case 10:
         es32f0_channel = ADC_CHANNEL_10;
-        gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct);
+        ald_gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct);
         break;
     case 11:
         es32f0_channel = ADC_CHANNEL_11;
-        gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct);
+        ald_gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct);
         break;
     case 12:
         es32f0_channel = ADC_CHANNEL_12;
-        gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct);
+        ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct);
         break;
     case 13:
         es32f0_channel = ADC_CHANNEL_13;
-        gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct);
+        ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct);
         break;
     case 14:
         es32f0_channel = ADC_CHANNEL_14;
-        gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct);
+        ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct);
         break;
     case 15:
         es32f0_channel = ADC_CHANNEL_15;
-        gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct);
+        ald_gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct);
         break;
     case 16:
         es32f0_channel = ADC_CHANNEL_16;
@@ -139,21 +140,21 @@ static adc_channel_t es32f0_adc_get_channel(rt_uint32_t channel)
 static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
 {
     adc_handle_t *_hadc = (adc_handle_t *)device->parent.user_data;
-    adc_channel_conf_t nm_config;
+    adc_nch_conf_t nm_config;
 
     RT_ASSERT(device != RT_NULL);
     RT_ASSERT(value != RT_NULL);
 
     /* config adc channel */
     nm_config.channel       = es32f0_adc_get_channel(channel);
-    nm_config.rank          = ADC_NC_RANK_1;
-    nm_config.sampling_time = ADC_SAMPLETIME_4;
-    adc_normal_channel_config(_hadc, &nm_config);
+    nm_config.rank          = ADC_NCH_RANK_1;
+    nm_config.samp_time = ADC_SAMPLETIME_4;
+    ald_adc_normal_channel_config(_hadc, &nm_config);
 
-    adc_normal_start(_hadc);
+    ald_adc_normal_start(_hadc);
 
-    if (adc_normal_poll_for_conversion(_hadc, 5000) == OK)
-        *value = adc_normal_get_value(_hadc);
+    if (ald_adc_normal_poll_for_conversion(_hadc, 5000) == OK)
+        *value = ald_adc_normal_get_value(_hadc);
 
     return RT_EOK;
 }
@@ -172,17 +173,16 @@ int rt_hw_adc_init(void)
     /* adc function initialization */
     _h_adc0.perh = ADC0;
     _h_adc0.init.data_align = ADC_DATAALIGN_RIGHT;
-    _h_adc0.init.scan_mode = ADC_SCAN_DISABLE;
+    _h_adc0.init.scan_mode = DISABLE;
     _h_adc0.init.cont_mode = DISABLE;
-    _h_adc0.init.conv_nbr = ADC_NM_NBR_1;
-    _h_adc0.init.disc_mode = DISABLE;
+    _h_adc0.init.disc_mode = ADC_ALL_DISABLE;
     _h_adc0.init.disc_nbr = ADC_DISC_NBR_1;
     _h_adc0.init.conv_res = ADC_CONV_RES_10;
     _h_adc0.init.clk_div = ADC_CKDIV_128;
-    _h_adc0.init.nche_mode = ADC_NCHESEL_MODE_ALL;
+    _h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL;
     _h_adc0.init.neg_ref = ADC_NEG_REF_VSS;
     _h_adc0.init.pos_ref = ADC_POS_REF_VDD;
-    adc_init(&_h_adc0);
+    ald_adc_init(&_h_adc0);
 
     rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, &_h_adc0);
 

bsp/es32f0334/drivers/drv_gpio.c → bsp/essemi/es32f0334/drivers/drv_gpio.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author        Notes
  * 2019-03-01     wangyq        the first version
+ * 2019-11-01     wangyq        update libraries
  */
 
 #include <rthw.h>
@@ -167,7 +168,7 @@ void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     {
         return;
     }
-    gpio_write_pin(index->gpio, index->pin, value);
+    ald_gpio_write_pin(index->gpio, index->pin, value);
 }
 
 int es32f0_pin_read(rt_device_t dev, rt_base_t pin)
@@ -180,7 +181,7 @@ int es32f0_pin_read(rt_device_t dev, rt_base_t pin)
     {
         return value;
     }
-    value = gpio_read_pin(index->gpio, index->pin);
+    value = ald_gpio_read_pin(index->gpio, index->pin);
     return value;
 }
 
@@ -233,7 +234,7 @@ void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
         gpio_initstruct.pupd = GPIO_FLOATING;
         gpio_initstruct.odos = GPIO_OPEN_DRAIN;
     }
-    gpio_init(index->gpio, index->pin, &gpio_initstruct);
+    ald_gpio_init(index->gpio, index->pin, &gpio_initstruct);
 }
 
 rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
@@ -360,7 +361,7 @@ rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin,
             return RT_ENOSYS;
         }
         irqmap = &pin_irq_map[irqindex];
-        gpio_exti_init(index->gpio, index->pin, &exti_initstruct);
+        ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct);
         /* Configure GPIO_InitStructure */
         gpio_initstruct.mode = GPIO_MODE_INPUT;
         gpio_initstruct.func = GPIO_FUNC_1;
@@ -368,18 +369,18 @@ rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin,
         {
         case PIN_IRQ_MODE_RISING:
             gpio_initstruct.pupd = GPIO_PUSH_DOWN;
-            gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE);
+            ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE);
             break;
         case PIN_IRQ_MODE_FALLING:
             gpio_initstruct.pupd = GPIO_PUSH_UP;
-            gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE);
+            ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE);
             break;
         case PIN_IRQ_MODE_RISING_FALLING:
             gpio_initstruct.pupd = GPIO_FLOATING;
-            gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE);
+            ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE);
             break;
         }
-        gpio_init(index->gpio, index->pin, &gpio_initstruct);
+        ald_gpio_init(index->gpio, index->pin, &gpio_initstruct);
         NVIC_EnableIRQ(irqmap->irqno);
         rt_hw_interrupt_enable(level);
     }
@@ -412,7 +413,7 @@ const static struct rt_pin_ops _es32f0_pin_ops =
 int rt_hw_pin_init(void)
 {
     int result;
-    cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE);
+    ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE);
     result = rt_device_pin_register("pin", &_es32f0_pin_ops, RT_NULL);
     return result;
 }
@@ -439,9 +440,9 @@ rt_inline void pin_irq_hdr(uint16_t GPIO_Pin)
 
 void GPIO_EXTI_Callback(uint16_t GPIO_Pin)
 {
-    if (gpio_exti_get_flag_status(GPIO_Pin) != RESET)
+    if (ald_gpio_exti_get_flag_status(GPIO_Pin) != RESET)
     {
-        gpio_exti_clear_flag_status(GPIO_Pin);
+        ald_gpio_exti_clear_flag_status(GPIO_Pin);
         pin_irq_hdr(GPIO_Pin);
     }
 }

bsp/es32f0334/drivers/drv_hwtimer.c → bsp/essemi/es32f0334/drivers/drv_hwtimer.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2019-3-19      wangyq       the first version
+ * 2019-11-01     wangyq        update libraries
  */
 
 #include <rthw.h>
@@ -30,12 +31,12 @@ static struct es32f0_hwtimer_dev hwtimer0;
 
 void BS16T0_Handler(void)
 {
-    timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE);
+    ald_timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE);
     rt_device_hwtimer_isr(&hwtimer0.parent);
 
     if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode)
     {
-        timer_base_stop(hwtimer0.hwtimer_periph);
+        ald_timer_base_stop(hwtimer0.hwtimer_periph);
     }
 }
 #endif
@@ -45,15 +46,15 @@ static struct es32f0_hwtimer_dev hwtimer1;
 
 void BS16T1_UART2_Handler(void)
 {
-    if (timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) &&
-            timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE))
+    if (ald_timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) &&
+            ald_timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE))
     {
-        timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE);
+        ald_timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE);
         rt_device_hwtimer_isr(&hwtimer1.parent);
 
         if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode)
         {
-            timer_base_stop(hwtimer1.hwtimer_periph);
+            ald_timer_base_stop(hwtimer1.hwtimer_periph);
         }
     }
 }
@@ -64,15 +65,15 @@ static struct es32f0_hwtimer_dev hwtimer2;
 
 void BS16T2_UART3_Handler(void)
 {
-    if (timer_get_it_status(hwtimer2.hwtimer_periph, TIMER_IT_UPDATE) &&
-            timer_get_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE))
+    if (ald_timer_get_it_status(hwtimer2.hwtimer_periph, TIMER_IT_UPDATE) &&
+            ald_timer_get_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE))
     {
-        timer_clear_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE);
+        ald_timer_clear_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE);
         rt_device_hwtimer_isr(&hwtimer2.parent);
 
         if (HWTIMER_MODE_ONESHOT == hwtimer2.parent.mode)
         {
-            timer_base_stop(hwtimer2.hwtimer_periph);
+            ald_timer_base_stop(hwtimer2.hwtimer_periph);
         }
     }
 }
@@ -84,15 +85,15 @@ static struct es32f0_hwtimer_dev hwtimer3;
 void BS16T3_DAC0_Handler(void)
 {
     /* if BS16T3 it */
-    if (timer_get_it_status(hwtimer3.hwtimer_periph, TIMER_IT_UPDATE) &&
-            timer_get_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE))
+    if (ald_timer_get_it_status(hwtimer3.hwtimer_periph, TIMER_IT_UPDATE) &&
+            ald_timer_get_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE))
     {
-        timer_clear_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE);
+        ald_timer_clear_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE);
         rt_device_hwtimer_isr(&hwtimer3.parent);
 
         if (HWTIMER_MODE_ONESHOT == hwtimer3.parent.mode)
         {
-            timer_base_stop(hwtimer3.hwtimer_periph);
+            ald_timer_base_stop(hwtimer3.hwtimer_periph);
         }
     }
 }
@@ -114,13 +115,13 @@ static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
 
     if (1 == state)
     {
-        timer_base_init(hwtimer->hwtimer_periph);
-        timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE);
+        ald_timer_base_init(hwtimer->hwtimer_periph);
+        ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE);
         NVIC_EnableIRQ(hwtimer->IRQn);
     }
-    hwtimer->parent.freq = cmu_get_pclk1_clock();
-    es32f0_hwtimer_info.maxfreq = cmu_get_pclk1_clock();
-    es32f0_hwtimer_info.minfreq = cmu_get_pclk1_clock();
+    hwtimer->parent.freq = ald_cmu_get_pclk1_clock();
+    es32f0_hwtimer_info.maxfreq = ald_cmu_get_pclk1_clock();
+    es32f0_hwtimer_info.minfreq = ald_cmu_get_pclk1_clock();
 }
 
 static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer,
@@ -132,7 +133,7 @@ static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer,
     RT_ASSERT(hwtimer != RT_NULL);
 
     WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt);
-    timer_base_start(hwtimer->hwtimer_periph);
+    ald_timer_base_start(hwtimer->hwtimer_periph);
 
     return RT_EOK;
 }
@@ -143,7 +144,7 @@ static void es32f0_hwtimer_stop(rt_hwtimer_t *timer)
 
     RT_ASSERT(hwtimer != RT_NULL);
 
-    timer_base_stop(hwtimer->hwtimer_periph);
+    ald_timer_base_stop(hwtimer->hwtimer_periph);
 }
 
 static rt_uint32_t es32f0_hwtimer_count_get(rt_hwtimer_t *timer)
@@ -172,14 +173,14 @@ static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer,
     {
     case HWTIMER_CTRL_FREQ_SET:
         freq = *(rt_uint32_t *)args;
-        if (freq != cmu_get_pclk1_clock())
+        if (freq != ald_cmu_get_pclk1_clock())
         {
             ret = -RT_ERROR;
         }
         break;
 
     case HWTIMER_CTRL_STOP:
-        timer_base_stop(hwtimer->hwtimer_periph);
+        ald_timer_base_stop(hwtimer->hwtimer_periph);
         break;
 
     default:

bsp/es32f0334/drivers/drv_i2c.c → bsp/essemi/es32f0334/drivers/drv_i2c.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author        Notes
  * 2019-03-19     wangyq        the first version
+ * 2019-11-01     wangyq        update libraries
  */
 
 #include <rthw.h>
@@ -45,10 +46,10 @@ static void _i2c_init(void)
     _h_i2c0.init.general_call = I2C_GENERALCALL_DISABLE;
     _h_i2c0.init.no_stretch   = I2C_NOSTRETCH_ENABLE;
 
-    i2c_reset(&_h_i2c0);
-    i2c_init(&_h_i2c0);
+    ald_i2c_reset(&_h_i2c0);
+    ald_i2c_init(&_h_i2c0);
     /* I2C0_SCL->PB8,  I2C0_SDA->PB9 */
-    gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct);
+    ald_gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct);
 #endif
 
 #ifdef BSP_USING_I2C1
@@ -61,10 +62,10 @@ static void _i2c_init(void)
     _h_i2c1.init.general_call = I2C_GENERALCALL_DISABLE;
     _h_i2c1.init.no_stretch   = I2C_NOSTRETCH_ENABLE;
 
-    i2c_reset(&_h_i2c1);
-    i2c_init(&_h_i2c1);
+    ald_i2c_reset(&_h_i2c1);
+    ald_i2c_init(&_h_i2c1);
     /* I2C1_SCL->PB10, I2C1_SDA->PB11 */
-    gpio_init(GPIOB, GPIO_PIN_10 | GPIO_PIN_11, &gpio_instruct);
+    ald_gpio_init(GPIOB, GPIO_PIN_10 | GPIO_PIN_11, &gpio_instruct);
 #endif
 }
 
@@ -81,7 +82,7 @@ static rt_size_t es32f0_master_xfer(struct rt_i2c_bus_device *bus,
         msg = &msgs[i];
         if (msg->flags & RT_I2C_RD)
         {
-            if (i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
+            if (ald_i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
             {
                 i2c_dbg("i2c bus write failed,i2c bus stop!\n");
                 goto out;
@@ -89,7 +90,7 @@ static rt_size_t es32f0_master_xfer(struct rt_i2c_bus_device *bus,
         }
         else
         {
-            if (i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
+            if (ald_i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
             {
                 i2c_dbg("i2c bus write failed,i2c bus stop!\n");
                 goto out;

bsp/essemi/es32f0334/drivers/drv_lptim.c

@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author          Notes
+ * 2019-11-01     wangyq          first version
+ */
+
+#include <board.h>
+#include <drv_lptim.h>
+#include <ald_lptim.h>
+
+static lptim_handle_t h_lptim;
+
+void LPTIM0_SPI2_Handler(void)
+{
+    /* LPTIM Intetrupt */
+    if (ald_lptim_get_it_status(&h_lptim, LPTIM_IT_ARRMAT) &&
+            ald_lptim_get_flag_status(&h_lptim, LPTIM_FLAG_ARRMAT))
+    {
+        /* enter interrupt */
+        rt_interrupt_enter();
+
+        ald_lptim_clear_flag_status(&h_lptim, LPTIM_FLAG_ARRMAT);
+
+        /* leave interrupt */
+        rt_interrupt_leave();
+    }
+}
+
+/**
+ * This function get current count value of LPTIM
+ *
+ * @return the count vlaue
+ */
+rt_uint32_t es32f0_lptim_get_current_tick(void)
+{
+    return READ_REG(h_lptim.perh->CNT);
+}
+
+/**
+ * This function get the max value that LPTIM can count
+ *
+ * @return the max count
+ */
+rt_uint32_t es32f0_lptim_get_tick_max(void)
+{
+    return (0xFFFF);
+}
+
+/**
+ * This function start LPTIM with reload value
+ *
+ * @param reload The value that LPTIM count down from
+ *
+ * @return RT_EOK
+ */
+rt_err_t es32f0_lptim_start(rt_uint32_t reload)
+{
+    h_lptim.init.arr = reload;
+    ald_lptim_toggle_start_by_it(&h_lptim);
+
+    return (RT_EOK);
+}
+
+/**
+ * This function stop LPTIM
+ */
+void es32f0_lptim_stop(void)
+{
+    ald_lptim_toggle_stop_by_it(&h_lptim);
+}
+
+/**
+ * This function get the count clock of LPTIM
+ *
+ * @return the count clock frequency in Hz
+ */
+rt_uint32_t es32f0_lptim_get_countfreq(void)
+{
+    return 1000000;
+}
+
+/**
+ * This function initialize the lptim
+ */
+int es32f0_hw_lptim_init(void)
+{
+    lptim_clock_source_init_t clock_config;
+    lptim_trigger_init_t trigger_config;
+
+    /* Enable LPTIM clock */
+    ald_cmu_perh_clock_config(CMU_PERH_LPTIM0, ENABLE);
+
+    /* LPTIM Configuration */
+    h_lptim.perh       = LPTIM0;
+    h_lptim.init.psc   = LPTIM_PRESC_1;           // can not select other premeter
+    h_lptim.init.arr   = 0x0FFF;
+    h_lptim.init.clock = CMU_LP_PERH_CLOCK_SEL_HRC_1M;
+    h_lptim.init.mode  = LPTIM_MODE_SINGLE;
+
+    ald_lptim_toggle_init(&h_lptim);
+
+    /* Initialize clock source */
+    clock_config.sel      = LPTIM_CKSEL_INTERNAL;
+    clock_config.polarity = LPTIM_CKPOL_RISING;
+    ald_lptim_clock_source_config(&h_lptim, &clock_config);
+
+    /* Initialize toggle */
+    trigger_config.mode = LPTIM_TRIGEN_SW;
+    ald_lptim_trigger_config(&h_lptim, &trigger_config);
+
+    ald_lptim_interrupt_config(&h_lptim, LPTIM_IT_ARRMAT, ENABLE);
+
+    NVIC_ClearPendingIRQ(LPTIM0_SPI2_IRQn);
+    NVIC_SetPriority(LPTIM0_SPI2_IRQn, 0);
+    NVIC_EnableIRQ(LPTIM0_SPI2_IRQn);
+
+    return 0;
+}
+
+INIT_DEVICE_EXPORT(es32f0_hw_lptim_init);

bsp/essemi/es32f0334/drivers/drv_lptim.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author          Notes
+ * 2019-11-01     wangyq          first version
+ */
+
+#ifndef  __DRV_PMTIMER_H__
+#define  __DRV_PMTIMER_H__
+
+#include <rtthread.h>
+
+rt_uint32_t es32f0_lptim_get_countfreq(void);
+rt_uint32_t es32f0_lptim_get_tick_max(void);
+rt_uint32_t es32f0_lptim_get_current_tick(void);
+
+rt_err_t es32f0_lptim_start(rt_uint32_t load);
+void es32f0_lptim_stop(void);
+
+#endif /* __DRV_PMTIMER_H__ */

bsp/essemi/es32f0334/drivers/drv_pm.c

@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-04-08     wangyq        the first version
+ * 2019-11-01     wangyq        adapt to the new power management interface
+ */
+
+#include <board.h>
+#include <rtdevice.h>
+#include <drv_lptim.h>
+#include <ald_cmu.h>
+#include <ald_pmu.h>
+
+#ifdef RT_USING_PM
+
+static void uart_console_reconfig(void)
+{
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config);
+}
+
+/**
+ * This function will put ES32F033x into sleep mode.
+ *
+ * @param pm pointer to power manage structure
+ */
+static void sleep(struct rt_pm *pm, uint8_t mode)
+{
+    switch (mode)
+    {
+    case PM_SLEEP_MODE_NONE:
+        break;
+
+    case PM_SLEEP_MODE_IDLE:
+        //__WFI();
+        break;
+
+    case PM_SLEEP_MODE_LIGHT:
+        if (pm->run_mode == PM_RUN_MODE_LOW_SPEED)
+        {
+            /* Enter LP SLEEP Mode, Enable low-power regulator */
+            ald_pmu_lprun_config(PMU_LDO_LPMODE_OUTPUT_1_5, ENABLE);
+        }
+        else
+        {
+            /* Enter SLEEP Mode, Main regulator is ON */
+            ald_pmu_stop1_enter();
+        }
+        break;
+
+    case PM_SLEEP_MODE_DEEP:
+        /* Enter STOP 2 mode  */
+        ald_pmu_stop2_enter();
+        break;
+
+    case PM_SLEEP_MODE_STANDBY:
+        /* Enter STANDBY mode */
+        ald_pmu_stop2_enter();
+        break;
+
+    case PM_SLEEP_MODE_SHUTDOWN:
+        /* Enter SHUTDOWNN mode */
+        ald_pmu_stop2_enter();
+        break;
+
+    default:
+        RT_ASSERT(0);
+        break;
+    }
+}
+
+static uint8_t run_speed[PM_RUN_MODE_MAX][2] =
+{
+    {48, 0},
+    {48, 1},
+    {24, 2},
+    {2,  3},
+};
+
+static void run(struct rt_pm *pm, uint8_t mode)
+{
+    static uint8_t last_mode;
+    static char *run_str[] = PM_RUN_MODE_NAMES;
+    extern uint32_t __system_clock;
+
+    if (mode == last_mode)
+        return;
+    last_mode = mode;
+
+    ald_cmu_clock_config_default();
+    __system_clock = 24000000;
+    switch (mode)
+    {
+    case PM_RUN_MODE_HIGH_SPEED:
+    case PM_RUN_MODE_NORMAL_SPEED:
+        /* hosc 12MHz, from hosc/3 pll to 48MHz */
+        ald_cmu_pll1_config(CMU_PLL1_INPUT_HRC_6, CMU_PLL1_OUTPUT_48M);
+        /* MCLK 48MHz */
+        ald_cmu_clock_config(CMU_CLOCK_PLL1, 48000000);
+        break;
+    case PM_RUN_MODE_MEDIUM_SPEED:
+        break;
+    case PM_RUN_MODE_LOW_SPEED:
+        ald_cmu_clock_config(CMU_CLOCK_HRC, 2000000);
+        break;
+    default:
+        break;
+    }
+
+    /* 4. 更新外设时钟 */
+    uart_console_reconfig();
+    /* Re-Configure the Systick time */
+    SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND);
+
+    rt_kprintf("switch to %s mode, frequency = %d MHz\n", run_str[mode], run_speed[mode][0]);
+}
+
+/**
+ * This function caculate the PM tick from OS tick
+ *
+ * @param tick OS tick
+ *
+ * @return the PM tick
+ */
+static rt_tick_t es32f0_pm_tick_from_os_tick(rt_tick_t tick)
+{
+    rt_uint32_t freq = es32f0_lptim_get_countfreq();
+
+    return (freq * tick / RT_TICK_PER_SECOND);
+}
+
+/**
+ * This function caculate the OS tick from PM tick
+ *
+ * @param tick PM tick
+ *
+ * @return the OS tick
+ */
+static rt_tick_t es32f0_os_tick_from_pm_tick(rt_uint32_t tick)
+{
+    static rt_uint32_t os_tick_remain = 0;
+    rt_uint32_t ret, freq;
+
+    freq = es32f0_lptim_get_countfreq();
+    ret = (tick * RT_TICK_PER_SECOND + os_tick_remain) / freq;
+
+    os_tick_remain += (tick * RT_TICK_PER_SECOND);
+    os_tick_remain %= freq;
+
+    return ret;
+}
+
+/**
+ * This function start the timer of pm
+ *
+ * @param pm Pointer to power manage structure
+ * @param timeout How many OS Ticks that MCU can sleep
+ */
+static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout)
+{
+    RT_ASSERT(pm != RT_NULL);
+    RT_ASSERT(timeout > 0);
+
+    if (timeout != RT_TICK_MAX)
+    {
+        /* Convert OS Tick to pmtimer timeout value */
+        timeout = es32f0_pm_tick_from_os_tick(timeout);
+        /* MAX 0xFFFF */
+        if (timeout > es32f0_lptim_get_tick_max())
+        {
+            timeout = es32f0_lptim_get_tick_max();
+        }
+
+        /* Enter PM_TIMER_MODE */
+        es32f0_lptim_start(timeout);
+    }
+}
+
+/**
+ * This function stop the timer of pm
+ *
+ * @param pm Pointer to power manage structure
+ */
+static void pm_timer_stop(struct rt_pm *pm)
+{
+    RT_ASSERT(pm != RT_NULL);
+
+    /* Reset pmtimer status */
+    es32f0_lptim_stop();
+}
+
+/**
+ * This function calculate how many OS Ticks that MCU have suspended
+ *
+ * @param pm Pointer to power manage structure
+ *
+ * @return OS Ticks
+ */
+static rt_tick_t pm_timer_get_tick(struct rt_pm *pm)
+{
+    rt_uint32_t timer_tick;
+
+    RT_ASSERT(pm != RT_NULL);
+
+    timer_tick = es32f0_lptim_get_current_tick();
+
+    return es32f0_os_tick_from_pm_tick(timer_tick);
+}
+
+/**
+ * This function initialize the power manager
+ */
+int drv_pm_hw_init(void)
+{
+    static const struct rt_pm_ops _ops =
+    {
+        sleep,
+        run,
+        pm_timer_start,
+        pm_timer_stop,
+        pm_timer_get_tick
+    };
+
+    rt_uint8_t timer_mask = 0;
+
+    /* initialize timer mask */
+    timer_mask = 1UL << PM_SLEEP_MODE_DEEP;
+
+    /* initialize system pm module */
+    rt_system_pm_init(&_ops, timer_mask, RT_NULL);
+
+    return 0;
+}
+INIT_BOARD_EXPORT(drv_pm_hw_init);
+
+#endif

bsp/es32f0334/drivers/drv_pwm.c → bsp/essemi/es32f0334/drivers/drv_pwm.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2019-03-19     wangyq       the first version
+ * 2019-11-01     wangyq        update libraries
  */
 
 #include <rthw.h>
@@ -18,7 +19,7 @@
 
 static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns)
 {
-    uint64_t _arr = (uint64_t)cmu_get_pclk1_clock() * ns / 1000000000 /
+    uint64_t _arr = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 /
                     (timer_initstruct->init.prescaler + 1);
 
     WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr);
@@ -27,7 +28,7 @@ static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns)
 
 static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, uint32_t ns)
 {
-    uint64_t tmp = (uint64_t)cmu_get_pclk1_clock() * ns / 1000000000 /
+    uint64_t tmp = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 /
                    (timer_initstruct->init.prescaler + 1);
 
     if (ch == TIMER_CHANNEL_1)
@@ -88,11 +89,11 @@ static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *
     switch (cmd)
     {
     case PWM_CMD_ENABLE:
-        timer_pwm_start(timer_initstruct, pwm_channel);
+        ald_timer_pwm_start(timer_initstruct, pwm_channel);
         break;
 
     case PWM_CMD_DISABLE:
-        timer_pwm_stop(timer_initstruct, pwm_channel);
+        ald_timer_pwm_stop(timer_initstruct, pwm_channel);
         break;
 
     case PWM_CMD_SET:
@@ -106,13 +107,13 @@ static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *
         while (timer_initstruct->init.period > 0xFFFF);
         /* update prescaler */
         WRITE_REG(timer_initstruct->perh->PRES, --timer_initstruct->init.prescaler);
-        timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel);
+        ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel);
         pwm_set_duty(timer_initstruct, pwm_channel, cfg->pulse);
         timer_initstruct->perh->CCEP = _ccep;
         break;
 
     case PWM_CMD_GET:
-        cfg->pulse = timer_read_capture_value(timer_initstruct, pwm_channel) * 100 /
+        cfg->pulse = ald_timer_read_capture_value(timer_initstruct, pwm_channel) * 100 /
                      READ_REG(timer_initstruct->perh->AR);
         break;
 
@@ -143,15 +144,15 @@ int rt_hw_pwm_init(void)
     static struct rt_device_pwm pwm_dev0;
     static timer_handle_t timer_initstruct0;
 
-    timer_initstruct0.perh = AD16C4T0;
-    timer_pwm_init(&timer_initstruct0);
+    timer_initstruct0.perh = GP16C4T0;
+    ald_timer_pwm_init(&timer_initstruct0);
 
     /* gpio initialization */
     gpio_initstructure.func = GPIO_FUNC_2;
-    gpio_init(GPIOA, GPIO_PIN_8, &gpio_initstructure);
-    gpio_init(GPIOA, GPIO_PIN_9, &gpio_initstructure);
-    gpio_init(GPIOA, GPIO_PIN_10, &gpio_initstructure);
-    gpio_init(GPIOA, GPIO_PIN_11, &gpio_initstructure);
+    ald_gpio_init(GPIOA, GPIO_PIN_8, &gpio_initstructure);
+    ald_gpio_init(GPIOA, GPIO_PIN_9, &gpio_initstructure);
+    ald_gpio_init(GPIOA, GPIO_PIN_10, &gpio_initstructure);
+    ald_gpio_init(GPIOA, GPIO_PIN_11, &gpio_initstructure);
 
     ret = rt_device_pwm_register(&pwm_dev0, "pwm0", &es32f0_pwm_ops,
                                  &timer_initstruct0);
@@ -161,14 +162,14 @@ int rt_hw_pwm_init(void)
     static struct rt_device_pwm pwm_dev1;
     static timer_handle_t timer_initstruct1;
 
-    timer_initstruct1.perh = GP16C4T0;
-    timer_pwm_init(&timer_initstruct1);
+    timer_initstruct1.perh = GP16C4T1;
+    ald_timer_pwm_init(&timer_initstruct1);
 
     /* gpio initialization */
     gpio_initstructure.func = GPIO_FUNC_2;
-    gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure);
-    gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure);
-    gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure);
+    ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure);
+    ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure);
+    ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure);
 
     ret = rt_device_pwm_register(&pwm_dev1, "pwm1", &es32f0_pwm_ops,
                                  &timer_initstruct1);
@@ -179,12 +180,12 @@ int rt_hw_pwm_init(void)
     static timer_handle_t timer_initstruct2;
 
     timer_initstruct2.perh = GP16C2T0;
-    timer_pwm_init(&timer_initstruct2);
+    ald_timer_pwm_init(&timer_initstruct2);
 
     /* gpio initialization */
     gpio_initstructure.func = GPIO_FUNC_2;
-    gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure);
-    gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure);
+    ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure);
+    ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure);
 
     ret = rt_device_pwm_register(&pwm_dev2, "pwm2", &es32f0_pwm_ops,
                                  &timer_initstruct2);
@@ -195,12 +196,12 @@ int rt_hw_pwm_init(void)
     static timer_handle_t timer_initstruct3;
 
     timer_initstruct3.perh = GP16C2T1;
-    timer_pwm_init(&timer_initstruct3);
+    ald_timer_pwm_init(&timer_initstruct3);
 
     /* gpio initialization */
     gpio_initstructure.func = GPIO_FUNC_3;
-    gpio_init(GPIOC, GPIO_PIN_6, &gpio_initstructure);
-    gpio_init(GPIOC, GPIO_PIN_7, &gpio_initstructure);
+    ald_gpio_init(GPIOC, GPIO_PIN_6, &gpio_initstructure);
+    ald_gpio_init(GPIOC, GPIO_PIN_7, &gpio_initstructure);
 
     ret = rt_device_pwm_register(&pwm_dev3, "pwm3", &es32f0_pwm_ops,
                                  &timer_initstruct3);

bsp/es32f0334/drivers/drv_rtc.c → bsp/essemi/es32f0334/drivers/drv_rtc.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2019-04-01     wangyq       the first version
+ * 2019-11-01     wangyq        update libraries
  */
 
 #include <rthw.h>
@@ -25,7 +26,7 @@ static void __rtc_init(rtc_init_t *init)
     assert_param(IS_RTC_OUTPUT_SEL(init->output));
     assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity));
 
-    rtc_reset();
+    ald_rtc_reset();
     RTC_UNLOCK();
 
     MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS);
@@ -51,7 +52,7 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args)
     {
     case RT_DEVICE_CTRL_RTC_GET_TIME:
 
-        rtc_get_date_time(&date, &time, RTC_FORMAT_DEC);
+        ald_rtc_get_date_time(&date, &time, RTC_FORMAT_DEC);
         time_temp.tm_sec = time.second;
         time_temp.tm_min = time.minute;
         time_temp.tm_hour = time.hour;
@@ -77,8 +78,8 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args)
         date.year = time_temp.tm_year + 1900 - 2000;
         date.month = time_temp.tm_mon + 1;
         date.day = time_temp.tm_mday;
-        rtc_set_time(&time, RTC_FORMAT_DEC);
-        rtc_set_date(&date, RTC_FORMAT_DEC);
+        ald_rtc_set_time(&time, RTC_FORMAT_DEC);
+        ald_rtc_set_date(&date, RTC_FORMAT_DEC);
         /* start RTC */
         RTC_UNLOCK();
         SET_BIT(RTC->CON, RTC_CON_GO_MSK);
@@ -118,7 +119,7 @@ int rt_hw_rtc_init(void)
 
     /* enable external 32.768kHz */
     CMU_LOSC_ENABLE();
-    cmu_losc_safe_config(ENABLE);
+    ald_cmu_losc_safe_config(ENABLE);
     /* set default time */
     RTC_UNLOCK();
     WRITE_REG(RTC->TIME, 0x134251);

bsp/es32f0334/drivers/drv_spi.c → bsp/essemi/es32f0334/drivers/drv_spi.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author        Notes
  * 2019-03-19     wangyq        the first version
+ * 2019-11-01     wangyq        update libraries
  */
 
 #include <rtthread.h>
@@ -80,14 +81,14 @@ rt_err_t spi_configure(struct rt_spi_device *device,
     }
 
     /* config spi clock */
-    if (cfg->max_hz >= cmu_get_pclk1_clock() / 2)
+    if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 2)
     {
         /* pclk1 max speed 48MHz, spi master max speed 10MHz */
-        if (cmu_get_pclk1_clock() / 2 <= 10000000)
+        if (ald_cmu_get_pclk1_clock() / 2 <= 10000000)
         {
             hspi->init.baud = SPI_BAUD_2;
         }
-        else if (cmu_get_pclk1_clock() / 4 <= 10000000)
+        else if (ald_cmu_get_pclk1_clock() / 4 <= 10000000)
         {
             hspi->init.baud = SPI_BAUD_4;
         }
@@ -96,10 +97,10 @@ rt_err_t spi_configure(struct rt_spi_device *device,
             hspi->init.baud = SPI_BAUD_8;
         }
     }
-    else if (cfg->max_hz >= cmu_get_pclk1_clock() / 4)
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 4)
     {
         /* pclk1 max speed 48MHz, spi master max speed 10MHz */
-        if (cmu_get_pclk1_clock() / 4 <= 10000000)
+        if (ald_cmu_get_pclk1_clock() / 4 <= 10000000)
         {
             hspi->init.baud = SPI_BAUD_4;
         }
@@ -108,23 +109,23 @@ rt_err_t spi_configure(struct rt_spi_device *device,
             hspi->init.baud = SPI_BAUD_8;
         }
     }
-    else if (cfg->max_hz >= cmu_get_pclk1_clock() / 8)
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 8)
     {
         hspi->init.baud = SPI_BAUD_8;
     }
-    else if (cfg->max_hz >= cmu_get_pclk1_clock() / 16)
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 16)
     {
         hspi->init.baud = SPI_BAUD_16;
     }
-    else if (cfg->max_hz >= cmu_get_pclk1_clock() / 32)
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 32)
     {
         hspi->init.baud = SPI_BAUD_32;
     }
-    else if (cfg->max_hz >= cmu_get_pclk1_clock() / 64)
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 64)
     {
         hspi->init.baud = SPI_BAUD_64;
     }
-    else if (cfg->max_hz >= cmu_get_pclk1_clock() / 128)
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 128)
     {
         hspi->init.baud = SPI_BAUD_128;
     }
@@ -132,7 +133,7 @@ rt_err_t spi_configure(struct rt_spi_device *device,
     {
         hspi->init.baud = SPI_BAUD_256;
     }
-    spi_init(hspi);
+    ald_spi_init(hspi);
     return RT_EOK;
 }
 
@@ -157,7 +158,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
         {
             rt_pin_write(cs->pin, 0);
         }
-        res = spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
+        res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
         if (message->cs_release)
         {
             rt_pin_write(cs->pin, 1);
@@ -173,7 +174,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
         {
             rt_pin_write(cs->pin, 0);
         }
-        res = spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
+        res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
         if (message->cs_release)
         {
             rt_pin_write(cs->pin, 1);
@@ -189,8 +190,8 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
         {
             rt_pin_write(cs->pin, 0);
         }
-        res = spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
-                            (rt_int32_t)message->length, SPITIMEOUT);
+        res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
+                                (rt_int32_t)message->length, SPITIMEOUT);
         if (message->cs_release)
         {
             rt_pin_write(cs->pin, 1);
@@ -230,11 +231,11 @@ int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name)
         gpio_instruct.flt  = GPIO_FILTER_DISABLE;
 
         /* PB3->SPI0_SCK, PB5->SPI0_MOSI */
-        gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct);
+        ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct);
 
         /* PB4->SPI0_MISO */
         gpio_instruct.mode = GPIO_MODE_INPUT;
-        gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct);
+        ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct);
     }
     else if (SPIx == SPI1)
     {
@@ -250,11 +251,11 @@ int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name)
         gpio_instruct.flt  = GPIO_FILTER_DISABLE;
 
         /* PB13->SPI1_SCK, PB15->SPI1_MOSI */
-        gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct);
+        ald_gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct);
 
         /* PB14->SPI1_MISO */
         gpio_instruct.mode = GPIO_MODE_INPUT;
-        gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct);
+        ald_gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct);
     }
     else
     {

bsp/es32f0334/drivers/drv_spiflash.c → bsp/essemi/es32f0334/drivers/drv_spiflash.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author        Notes
  * 2019-03-19     wangyq        the first version
+ * 2019-11-01     wangyq        update libraries
  */
 
 #include <rtthread.h>

bsp/es32f0334/drivers/drv_uart.c → bsp/essemi/es32f0334/drivers/drv_uart.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author        Notes
  * 2019-03-01     wangyq        the first version
+ * 2019-11-01     wangyq        update libraries
  */
 
 #include <rthw.h>
@@ -43,21 +44,21 @@ static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial
 
 #ifdef BSP_USING_UART0
     gpio_init_initstructure.func = GPIO_FUNC_3;
-    gpio_init(GPIOB, GPIO_PIN_10, &gpio_init_initstructure);
+    ald_gpio_init(GPIOB, GPIO_PIN_10, &gpio_init_initstructure);
 
     /* Initialize rx pin ,the same as txpin except mode */
     gpio_init_initstructure.mode = GPIO_MODE_INPUT;
-    gpio_init(GPIOB, GPIO_PIN_11, &gpio_init_initstructure);
+    ald_gpio_init(GPIOB, GPIO_PIN_11, &gpio_init_initstructure);
 #endif
 
 #ifdef BSP_USING_UART1
     /* Initialize tx pin */
     gpio_init_initstructure.func = GPIO_FUNC_3;
-    gpio_init(GPIOC, GPIO_PIN_10, &gpio_init_initstructure);
+    ald_gpio_init(GPIOC, GPIO_PIN_10, &gpio_init_initstructure);
 
     /* Initialize rx pin ,the same as txpin except mode*/
     gpio_init_initstructure.mode = GPIO_MODE_INPUT;
-    gpio_init(GPIOC, GPIO_PIN_11, &gpio_init_initstructure);
+    ald_gpio_init(GPIOC, GPIO_PIN_11, &gpio_init_initstructure);
 #endif
 
     uart->huart.init.mode        = UART_MODE_UART;
@@ -65,7 +66,7 @@ static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial
     uart->huart.init.word_length = (uart_word_length_t)(cfg->data_bits - 5);
     uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity);
     uart->huart.init.fctl        = UART_HW_FLOW_CTL_DISABLE;
-    uart_init(&uart->huart);
+    ald_uart_init(&uart->huart);
 
     if (cfg->bit_order == BIT_ORDER_MSB)
     {
@@ -86,7 +87,7 @@ static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial
     }
 
     /* enable rx int */
-    uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE);
+    ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE);
 
     return RT_EOK;
 }
@@ -103,14 +104,14 @@ static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void *
         /* disable rx irq */
         NVIC_DisableIRQ(uart->irq);
         /* disable interrupt */
-        uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE);
+        ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE);
         break;
 
     case RT_DEVICE_CTRL_SET_INT:
         /* enable rx irq */
         NVIC_EnableIRQ(uart->irq);
         /* enable interrupt */
-        uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE);
+        ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE);
         break;
     }
 

bsp/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Include/es32f033x.h → bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Include/es32f033x.h

@@ -22,7 +22,10 @@
 #define __O	volatile	/* defines 'write only' permissions */
 #define __IO	volatile	/* defines 'read / write' permissions */
 
-#define __NVIC_PRIO_BITS	2
+#define  __CHECK_DEVICE_DEFINES
+#define  __NVIC_PRIO_BITS	2U
+#define  __CM0_REV		0x0000U
+#define __Vendor_SysTickConfig	0U
 
 typedef enum IRQn {
 	/* Cortex-M0 processor cxceptions index */
@@ -37,7 +40,7 @@ typedef enum IRQn {
 	/* es32f0xx specific interrupt index */
 	WWDG_IWDG_IRQn                = 0,
 	LVD_IRQn                      = 1,
-	RTC_TEMP_IRQn                 = 2,
+	RTC_TSENSE_IRQn                 = 2,
 	CRYPT_TRNG_IRQn               = 3,
 	CMU_IRQn                      = 4,
 	EXTI0_3_IRQn                  = 5,
@@ -48,14 +51,14 @@ typedef enum IRQn {
 	CAN0_IRQn                     = 10,
 	LPTIM0_SPI2_IRQn              = 11,
 	ADC_ACMP_IRQn                 = 12,
-	AD16C4T0_BRK_UP_TRIG_COM_IRQn = 13,
-	AD16C4T0_CC_IRQn              = 14,
+	GP16C4T0_BRK_UP_TRIG_COM_IRQn = 13,
+	GP16C4T0_CC_IRQn              = 14,
 	BS16T0_IRQn                   = 15,
 	GP16C2T0_IRQn                 = 17,
 	GP16C2T1_IRQn                 = 18,
 	BS16T1_UART2_IRQn             = 19,
 	BS16T2_UART3_IRQn             = 20,
-	GP16C4T0_LCD_IRQn             = 21,
+	GP16C4T1_LCD_IRQn             = 21,
 	BS16T3_DAC0_IRQn              = 22,
 	I2C0_IRQn                     = 23,
 	I2C1_IRQn                     = 24,
@@ -273,9 +276,9 @@ typedef struct
 
 /****************** Bit definition for BKPC_PCCR register ************************/
 
-#define	BKPC_PCCR_TEMPCS_POSS	4U 
-#define	BKPC_PCCR_TEMPCS_POSE	5U 
-#define	BKPC_PCCR_TEMPCS_MSK	BITS(BKPC_PCCR_TEMPCS_POSS,BKPC_PCCR_TEMPCS_POSE)
+#define	BKPC_PCCR_TSENSECS_POSS	4U 
+#define	BKPC_PCCR_TSENSECS_POSE	5U 
+#define	BKPC_PCCR_TSENSECS_MSK	BITS(BKPC_PCCR_TSENSECS_POSS,BKPC_PCCR_TSENSECS_POSE)
 
 #define	BKPC_PCCR_RTCCS_POSS	0U 
 #define	BKPC_PCCR_RTCCS_POSE	1U 
@@ -594,8 +597,8 @@ typedef struct
 #define	RMU_APB2RSTR_BKPCRST_POS	17U 
 #define	RMU_APB2RSTR_BKPCRST_MSK	BIT(RMU_APB2RSTR_BKPCRST_POS)
 
-#define	RMU_APB2RSTR_TEMPRST_POS	16U 
-#define	RMU_APB2RSTR_TEMPRST_MSK	BIT(RMU_APB2RSTR_TEMPRST_POS)
+#define	RMU_APB2RSTR_TSENSERST_POS	16U 
+#define	RMU_APB2RSTR_TSENSERST_MSK	BIT(RMU_APB2RSTR_TSENSERST_POS)
 
 #define	RMU_APB2RSTR_RTCRST_POS	15U 
 #define	RMU_APB2RSTR_RTCRST_MSK	BIT(RMU_APB2RSTR_RTCRST_POS)
@@ -977,8 +980,8 @@ typedef struct
 #define	CMU_APB2ENR_BKPCEN_POS	17U 
 #define	CMU_APB2ENR_BKPCEN_MSK	BIT(CMU_APB2ENR_BKPCEN_POS)
 
-#define	CMU_APB2ENR_TEMPEN_POS	16U 
-#define	CMU_APB2ENR_TEMPEN_MSK	BIT(CMU_APB2ENR_TEMPEN_POS)
+#define	CMU_APB2ENR_TSENSEEN_POS	16U 
+#define	CMU_APB2ENR_TSENSEEN_MSK	BIT(CMU_APB2ENR_TSENSEEN_POS)
 
 #define	CMU_APB2ENR_RTCEN_POS	15U 
 #define	CMU_APB2ENR_RTCEN_MSK	BIT(CMU_APB2ENR_RTCEN_POS)
@@ -6057,101 +6060,101 @@ typedef struct
 	__I uint32_t ISR;
 } TRNG_TypeDef;
 
-/****************** Bit definition for TEMP_WPR register ************************/
+/****************** Bit definition for TSENSE_WPR register ************************/
 
-#define	TEMP_WPR_WP_POS	0U 
-#define	TEMP_WPR_WP_MSK	BIT(TEMP_WPR_WP_POS)
+#define	TSENSE_WPR_WP_POS	0U 
+#define	TSENSE_WPR_WP_MSK	BIT(TSENSE_WPR_WP_POS)
 
-/****************** Bit definition for TEMP_CR register ************************/
+/****************** Bit definition for TSENSE_CR register ************************/
 
-#define	TEMP_CR_TSU_POSS	12U 
-#define	TEMP_CR_TSU_POSE	14U 
-#define	TEMP_CR_TSU_MSK	BITS(TEMP_CR_TSU_POSS,TEMP_CR_TSU_POSE)
+#define	TSENSE_CR_TSU_POSS	12U 
+#define	TSENSE_CR_TSU_POSE	14U 
+#define	TSENSE_CR_TSU_MSK	BITS(TSENSE_CR_TSU_POSS,TSENSE_CR_TSU_POSE)
 
-#define	TEMP_CR_TOM_POSS	8U 
-#define	TEMP_CR_TOM_POSE	10U 
-#define	TEMP_CR_TOM_MSK	BITS(TEMP_CR_TOM_POSS,TEMP_CR_TOM_POSE)
+#define	TSENSE_CR_TOM_POSS	8U 
+#define	TSENSE_CR_TOM_POSE	10U 
+#define	TSENSE_CR_TOM_MSK	BITS(TSENSE_CR_TOM_POSS,TSENSE_CR_TOM_POSE)
 
-#define	TEMP_CR_CTN_POS	4U 
-#define	TEMP_CR_CTN_MSK	BIT(TEMP_CR_CTN_POS)
+#define	TSENSE_CR_CTN_POS	4U 
+#define	TSENSE_CR_CTN_MSK	BIT(TSENSE_CR_CTN_POS)
 
-#define	TEMP_CR_RST_POS	3U 
-#define	TEMP_CR_RST_MSK	BIT(TEMP_CR_RST_POS)
+#define	TSENSE_CR_RST_POS	3U 
+#define	TSENSE_CR_RST_MSK	BIT(TSENSE_CR_RST_POS)
 
-#define	TEMP_CR_ENS_POS	2U 
-#define	TEMP_CR_ENS_MSK	BIT(TEMP_CR_ENS_POS)
+#define	TSENSE_CR_ENS_POS	2U 
+#define	TSENSE_CR_ENS_MSK	BIT(TSENSE_CR_ENS_POS)
 
-#define	TEMP_CR_REQEN_POS	1U 
-#define	TEMP_CR_REQEN_MSK	BIT(TEMP_CR_REQEN_POS)
+#define	TSENSE_CR_REQEN_POS	1U 
+#define	TSENSE_CR_REQEN_MSK	BIT(TSENSE_CR_REQEN_POS)
 
-#define	TEMP_CR_EN_POS	0U 
-#define	TEMP_CR_EN_MSK	BIT(TEMP_CR_EN_POS)
+#define	TSENSE_CR_EN_POS	0U 
+#define	TSENSE_CR_EN_MSK	BIT(TSENSE_CR_EN_POS)
 
-/****************** Bit definition for TEMP_DR register ************************/
+/****************** Bit definition for TSENSE_DR register ************************/
 
-#define	TEMP_DR_ERR_POS	31U 
-#define	TEMP_DR_ERR_MSK	BIT(TEMP_DR_ERR_POS)
+#define	TSENSE_DR_ERR_POS	31U 
+#define	TSENSE_DR_ERR_MSK	BIT(TSENSE_DR_ERR_POS)
 
-#define	TEMP_DR_DATA_POSS	0U 
-#define	TEMP_DR_DATA_POSE	15U 
-#define	TEMP_DR_DATA_MSK	BITS(TEMP_DR_DATA_POSS,TEMP_DR_DATA_POSE)
+#define	TSENSE_DR_DATA_POSS	0U 
+#define	TSENSE_DR_DATA_POSE	15U 
+#define	TSENSE_DR_DATA_MSK	BITS(TSENSE_DR_DATA_POSS,TSENSE_DR_DATA_POSE)
 
-/****************** Bit definition for TEMP_PSR register ************************/
+/****************** Bit definition for TSENSE_PSR register ************************/
 
-#define	TEMP_PSR_PRS_POSS	0U 
-#define	TEMP_PSR_PRS_POSE	7U 
-#define	TEMP_PSR_PRS_MSK	BITS(TEMP_PSR_PRS_POSS,TEMP_PSR_PRS_POSE)
+#define	TSENSE_PSR_PRS_POSS	0U 
+#define	TSENSE_PSR_PRS_POSE	7U 
+#define	TSENSE_PSR_PRS_MSK	BITS(TSENSE_PSR_PRS_POSS,TSENSE_PSR_PRS_POSE)
 
-/****************** Bit definition for TEMP_IE register ************************/
+/****************** Bit definition for TSENSE_IE register ************************/
 
-#define	TEMP_IE_TEMP_POS	0U 
-#define	TEMP_IE_TEMP_MSK	BIT(TEMP_IE_TEMP_POS)
+#define	TSENSE_IE_TSENSE_POS	0U 
+#define	TSENSE_IE_TSENSE_MSK	BIT(TSENSE_IE_TSENSE_POS)
 
-/****************** Bit definition for TEMP_IF register ************************/
+/****************** Bit definition for TSENSE_IF register ************************/
 
-#define	TEMP_IF_TEMP_POS	0U 
-#define	TEMP_IF_TEMP_MSK	BIT(TEMP_IF_TEMP_POS)
+#define	TSENSE_IF_TSENSE_POS	0U 
+#define	TSENSE_IF_TSENSE_MSK	BIT(TSENSE_IF_TSENSE_POS)
 
-/****************** Bit definition for TEMP_IFCR register ************************/
+/****************** Bit definition for TSENSE_IFCR register ************************/
 
-#define	TEMP_IFCR_TEMP_POS	0U 
-#define	TEMP_IFCR_TEMP_MSK	BIT(TEMP_IFCR_TEMP_POS)
+#define	TSENSE_IFCR_TSENSE_POS	0U 
+#define	TSENSE_IFCR_TSENSE_MSK	BIT(TSENSE_IFCR_TSENSE_POS)
 
-/****************** Bit definition for TEMP_LTGR register ************************/
+/****************** Bit definition for TSENSE_LTGR register ************************/
 
-#define	TEMP_LTGR_LTG_POSS	0U 
-#define	TEMP_LTGR_LTG_POSE	20U 
-#define	TEMP_LTGR_LTG_MSK	BITS(TEMP_LTGR_LTG_POSS,TEMP_LTGR_LTG_POSE)
+#define	TSENSE_LTGR_LTG_POSS	0U 
+#define	TSENSE_LTGR_LTG_POSE	20U 
+#define	TSENSE_LTGR_LTG_MSK	BITS(TSENSE_LTGR_LTG_POSS,TSENSE_LTGR_LTG_POSE)
 
-/****************** Bit definition for TEMP_HTGR register ************************/
+/****************** Bit definition for TSENSE_HTGR register ************************/
 
-#define	TEMP_HTGR_HTG_POSS	0U 
-#define	TEMP_HTGR_HTG_POSE	20U 
-#define	TEMP_HTGR_HTG_MSK	BITS(TEMP_HTGR_HTG_POSS,TEMP_HTGR_HTG_POSE)
+#define	TSENSE_HTGR_HTG_POSS	0U 
+#define	TSENSE_HTGR_HTG_POSE	20U 
+#define	TSENSE_HTGR_HTG_MSK	BITS(TSENSE_HTGR_HTG_POSS,TSENSE_HTGR_HTG_POSE)
 
-/****************** Bit definition for TEMP_TBDR register ************************/
+/****************** Bit definition for TSENSE_TBDR register ************************/
 
-#define	TEMP_TBDR_TBD_POSS	0U 
-#define	TEMP_TBDR_TBD_POSE	15U 
-#define	TEMP_TBDR_TBD_MSK	BITS(TEMP_TBDR_TBD_POSS,TEMP_TBDR_TBD_POSE)
+#define	TSENSE_TBDR_TBD_POSS	0U 
+#define	TSENSE_TBDR_TBD_POSE	15U 
+#define	TSENSE_TBDR_TBD_MSK	BITS(TSENSE_TBDR_TBD_POSS,TSENSE_TBDR_TBD_POSE)
 
-/****************** Bit definition for TEMP_TCALBDR register ************************/
+/****************** Bit definition for TSENSE_TCALBDR register ************************/
 
-#define	TEMP_TCALBDR_TCAL_POSS	0U 
-#define	TEMP_TCALBDR_TCAL_POSE	16U 
-#define	TEMP_TCALBDR_TCAL_MSK	BITS(TEMP_TCALBDR_TCAL_POSS,TEMP_TCALBDR_TCAL_POSE)
+#define	TSENSE_TCALBDR_TCAL_POSS	0U 
+#define	TSENSE_TCALBDR_TCAL_POSE	16U 
+#define	TSENSE_TCALBDR_TCAL_MSK	BITS(TSENSE_TCALBDR_TCAL_POSS,TSENSE_TCALBDR_TCAL_POSE)
 
-/****************** Bit definition for TEMP_SR register ************************/
+/****************** Bit definition for TSENSE_SR register ************************/
 
-#define	TEMP_SR_TSOUT_POS	31U 
-#define	TEMP_SR_TSOUT_MSK	BIT(TEMP_SR_TSOUT_POS)
+#define	TSENSE_SR_TSOUT_POS	31U 
+#define	TSENSE_SR_TSOUT_MSK	BIT(TSENSE_SR_TSOUT_POS)
 
-#define	TEMP_SR_NVLD_POS	25U 
-#define	TEMP_SR_NVLD_MSK	BIT(TEMP_SR_NVLD_POS)
+#define	TSENSE_SR_NVLD_POS	25U 
+#define	TSENSE_SR_NVLD_MSK	BIT(TSENSE_SR_NVLD_POS)
 
-#define	TEMP_SR_TCAL_POSS	0U 
-#define	TEMP_SR_TCAL_POSE	24U 
-#define	TEMP_SR_TCAL_MSK	BITS(TEMP_SR_TCAL_POSS,TEMP_SR_TCAL_POSE)
+#define	TSENSE_SR_TCAL_POSS	0U 
+#define	TSENSE_SR_TCAL_POSE	24U 
+#define	TSENSE_SR_TCAL_MSK	BITS(TSENSE_SR_TCAL_POSS,TSENSE_SR_TCAL_POSE)
 
 typedef struct
 {
@@ -6167,7 +6170,7 @@ typedef struct
 	__IO uint32_t TBDR;
 	__IO uint32_t TCALBDR;
 	__I uint32_t SR;
-} TEMP_TypeDef;
+} TSENSE_TypeDef;
 
 /****************** Bit definition for IWDT_LOAD register ************************/
 
@@ -6503,27 +6506,52 @@ typedef struct
 #define APB2_BASE	(0x40040000UL)
 #define AHB_BASE	(0x40080000UL)
 
-/* Timer memory map */
-#define TIMER0_BASE (APB1_BASE + 0x0000)
-#define TIMER1_BASE (APB1_BASE + 0x0400)
-#define TIMER2_BASE (APB1_BASE + 0x0800)
-#define TIMER3_BASE (APB1_BASE + 0x0C00)
-#define TIMER4_BASE (APB1_BASE + 0x1000)
-#define TIMER5_BASE (APB1_BASE + 0x1400)
-#define TIMER6_BASE (APB1_BASE + 0x1800)
-#define TIMER7_BASE (APB1_BASE + 0x1C00)
-
-/* SPI memory map */
-#define SPI0_BASE (APB1_BASE + 0x6000)
-#define SPI1_BASE (APB1_BASE + 0x6400)
-#define SPI2_BASE (APB1_BASE + 0x6800)
-
-/* I2C memory map */
-#define I2C0_BASE (APB1_BASE + 0x8000)
-#define I2C1_BASE (APB1_BASE + 0x8400)
+/* APB1 peripherals Base Address */
+#define GP16C4T0_BASE	(APB1_BASE + 0x0000)
+#define BS16T0_BASE	(APB1_BASE + 0x0400)
+#define GP16C2T0_BASE	(APB1_BASE + 0x0800)
+#define GP16C2T1_BASE	(APB1_BASE + 0x0C00)
+#define BS16T1_BASE	(APB1_BASE + 0x1000)
+#define BS16T2_BASE	(APB1_BASE + 0x1400)
+#define GP16C4T1_BASE	(APB1_BASE + 0x1800)
+#define BS16T3_BASE	(APB1_BASE + 0x1C00)
+#define UART0_BASE	(APB1_BASE + 0x4000)
+#define UART1_BASE	(APB1_BASE + 0x4400)
+#define UART2_BASE	(APB1_BASE + 0x4800)
+#define UART3_BASE	(APB1_BASE + 0x4C00)
+#define USART0_BASE	(APB1_BASE + 0x5000)
+#define USART1_BASE	(APB1_BASE + 0x5400)
+#define SPI0_BASE	(APB1_BASE + 0x6000)
+#define SPI1_BASE	(APB1_BASE + 0x6400)
+#define SPI2_BASE	(APB1_BASE + 0x6800)
+#define I2C0_BASE	(APB1_BASE + 0x8000)
+#define I2C1_BASE	(APB1_BASE + 0x8400)
+#define CAN0_BASE	(APB1_BASE + 0xB000)
+#define DMA0_BASE    	(APB1_BASE + 0xC000)
 
-/* AHB peripherals */
-#define SYSTEM_BASE	(AHB_BASE + 0x0000)
+/* APB2 peripherals Base Address */
+#define LPTIM0_BASE	(APB2_BASE + 0x0000)
+#define LPUART0_BASE	(APB2_BASE + 0x1000)
+#define ADC0_BASE	(APB2_BASE + 0x2000)
+#define ADC1_BASE	(APB2_BASE + 0x2400)
+#define ACMP0_BASE	(APB2_BASE + 0x3000)
+#define ACMP1_BASE	(APB2_BASE + 0x3400)
+#define OPAMP_BASE	(APB2_BASE + 0x4000)
+#define DAC0_BASE	(APB2_BASE + 0x5000)
+#define WWDT_BASE	(APB2_BASE + 0x6000)
+#define IWDT_BASE	(APB2_BASE + 0x6400)
+#define LCD_BASE        (APB2_BASE + 0x7000)
+#define BKPC_BASE	(APB2_BASE + 0x8000)
+#define RTC_BASE	(APB2_BASE + 0x8400)
+#define TSENSE_BASE	(APB2_BASE + 0x8800)
+#define DBGC_BASE	(APB2_BASE + 0xA000)
+
+/* AHB peripherals Base Address */
+#define SYSCFG_BASE	(AHB_BASE + 0x0000)
+#define CMU_BASE	(AHB_BASE + 0x0400)
+#define RMU_BASE	(AHB_BASE + 0x0800)
+#define PMU_BASE	(AHB_BASE + 0x0C00)
+#define MSC_BASE	(AHB_BASE + 0x1000)
 #define GPIOA_BASE	(AHB_BASE + 0x4000)
 #define GPIOB_BASE	(AHB_BASE + 0x4040)
 #define GPIOC_BASE	(AHB_BASE + 0x4080)
@@ -6535,131 +6563,69 @@ typedef struct
 #define EXTI_BASE	(AHB_BASE + 0x4300)
 #define CRC_BASE	(AHB_BASE + 0x5000)
 #define CALC_BASE	(AHB_BASE + 0x5400)
-#define TRNG_BASE	(AHB_BASE + 0x5C00)
 #define CRYPT_BASE	(AHB_BASE + 0x5800)
-
-#define SYSCFG_BASE	(SYSTEM_BASE + 0x0000)
-#define CMU_BASE	(SYSTEM_BASE + 0x0400)
-#define RMU_BASE	(SYSTEM_BASE + 0x0800)
-#define PMU_BASE	(SYSTEM_BASE + 0x0C00)
-#define MSC_BASE	(SYSTEM_BASE + 0x1000)
-#define PIS_BASE	(SYSTEM_BASE + 0x6000)
+#define TRNG_BASE	(AHB_BASE + 0x5C00)
+#define PIS_BASE	(AHB_BASE + 0x6000)
 
 /* APB1 peripherals */
-#define CAN0_BASE	(APB1_BASE + 0xB000)
-#define USART0_BASE	(APB1_BASE + 0x5000)
-#define USART1_BASE	(APB1_BASE + 0x5400)
-#define UART0_BASE	(APB1_BASE + 0x4000)
-#define UART1_BASE	(APB1_BASE + 0x4400)
-#define UART2_BASE	(APB1_BASE + 0x4800)
-#define UART3_BASE	(APB1_BASE + 0x4C00)
-#define DMA0_BASE    	(APB1_BASE + 0xC000)
+#define GP16C4T0	((TIMER_TypeDef *)GP16C4T0_BASE)
+#define BS16T0		((TIMER_TypeDef *)BS16T0_BASE)
+#define GP16C2T0	((TIMER_TypeDef *)GP16C2T0_BASE)
+#define GP16C2T1	((TIMER_TypeDef *)GP16C2T1_BASE)
+#define BS16T1		((TIMER_TypeDef *)BS16T1_BASE)
+#define BS16T2		((TIMER_TypeDef *)BS16T2_BASE)
+#define GP16C4T1	((TIMER_TypeDef *)GP16C4T1_BASE)
+#define BS16T3		((TIMER_TypeDef *)BS16T3_BASE)
+#define UART0		((UART_TypeDef *)UART0_BASE)
+#define UART1		((UART_TypeDef *)UART1_BASE)
+#define UART2		((UART_TypeDef *)UART2_BASE)
+#define UART3		((UART_TypeDef *)UART3_BASE)
+#define USART0		((USART_TypeDef *)USART0_BASE)
+#define USART1		((USART_TypeDef *)USART1_BASE)
+#define SPI0		((SPI_TypeDef *)SPI0_BASE)
+#define SPI1		((SPI_TypeDef *)SPI1_BASE)
+#define SPI2		((SPI_TypeDef *)SPI2_BASE)
+#define I2C0		((I2C_TypeDef *)I2C0_BASE)
+#define I2C1		((I2C_TypeDef *)I2C1_BASE)
+#define CAN0		((CAN_TypeDef *)CAN0_BASE)
+#define DMA0		((DMA_TypeDef *)DMA0_BASE)
 
 /* APB2 peripherals */
-#define LPTIM0_BASE	(APB2_BASE + 0x0000)
-#define LPUART0_BASE	(APB2_BASE + 0x1000)
-#define DBGC_BASE	(APB2_BASE + 0xA000)
-#define WWDT_BASE	(APB2_BASE + 0x6000)
-#define IWDT_BASE	(APB2_BASE + 0x6400)
-#define RTC_BASE	(APB2_BASE + 0x8400)
-#define LCD_BASE        (APB2_BASE + 0x7000)
-#define ADC0_BASE	(APB2_BASE + 0x2000)
-#define ADC1_BASE	(APB2_BASE + 0x2400)
-#define ACMP0_BASE	(APB2_BASE + 0x3000)
-#define ACMP1_BASE	(APB2_BASE + 0x3400)
-#define OPAMP_BASE	(APB2_BASE + 0x4000)
-#define DAC0_BASE	(APB2_BASE + 0x5000)
-#define BKPC_BASE	(APB2_BASE + 0x8000)
-#define TEMP_BASE	(APB2_BASE + 0x8800)
-
-/* RTC Peripheral declaration */
-#define RTC	((RTC_TypeDef *)RTC_BASE)
-
-/* GPIO Peripheral_declaration */
-#define GPIOA	((GPIO_TypeDef *)GPIOA_BASE)
-#define GPIOB	((GPIO_TypeDef *)GPIOB_BASE)
-#define GPIOC	((GPIO_TypeDef *)GPIOC_BASE)
-#define GPIOD	((GPIO_TypeDef *)GPIOD_BASE)
-#define GPIOE	((GPIO_TypeDef *)GPIOE_BASE)
-#define GPIOF	((GPIO_TypeDef *)GPIOF_BASE)
-#define GPIOG	((GPIO_TypeDef *)GPIOG_BASE)
-#define GPIOH	((GPIO_TypeDef *)GPIOH_BASE)
-#define EXTI 	((EXTI_TypeDef *)EXTI_BASE)
-
-#define CRC	((CRC_TypeDef  *)CRC_BASE)
-#define TRNG	((TRNG_TypeDef *)TRNG_BASE)
-#define CALC	((CALC_TypeDef *)CALC_BASE)
-#define CRYPT	((CRYPT_TypeDef *)CRYPT_BASE)
-#define PIS	((PIS_TypeDef *)PIS_BASE)
-
-/* LCD Peripheral declaration */
-#define LCD     ((LCD_TypeDef *)LCD_BASE)
-/* ADC Peripheral declaration */
-#define ADC0	((ADC_TypeDef *)ADC0_BASE)
-#define ADC1	((ADC_TypeDef *)ADC1_BASE)
-/* ACMP Peripheral declaration */
-#define ACMP0	((ACMP_TypeDef *)ACMP0_BASE)
-#define ACMP1	((ACMP_TypeDef *)ACMP1_BASE)
-/* OPAMP Peripheral declaration */
-#define OPAMP	((OPAMP_TypeDef *)OPAMP_BASE)
-/* DAC Peripheral declaration */
-#define DAC0	((DAC_TypeDef *)DAC0_BASE)
-/* TEMP Peripheral declaration */
-#define TEMP	((TEMP_TypeDef *)TEMP_BASE)
-/* BKPC Peripheral declaration */
-#define BKPC	((BKPC_TypeDef *)BKPC_BASE)
-
-/* Timer Peripheral_declaration */
-#define TIMER0	((TIMER_TypeDef *)TIMER0_BASE)
-#define TIMER1	((TIMER_TypeDef *)TIMER1_BASE)
-#define TIMER2	((TIMER_TypeDef *)TIMER2_BASE)
-#define TIMER3	((TIMER_TypeDef *)TIMER3_BASE)
-#define TIMER4	((TIMER_TypeDef *)TIMER4_BASE)
-#define TIMER5	((TIMER_TypeDef *)TIMER5_BASE)
-#define TIMER6	((TIMER_TypeDef *)TIMER6_BASE)
-#define TIMER7	((TIMER_TypeDef *)TIMER7_BASE)
-
-#define AD16C4T0	TIMER0
-#define GP16C4T0	TIMER6
-#define GP16C2T0	TIMER2
-#define GP16C2T1	TIMER3
-#define BS16T0		TIMER1
-#define BS16T1		TIMER4
-#define BS16T2		TIMER5
-#define BS16T3		TIMER7
-
-/* SPI Peripheral_declaration */
-#define SPI0	((SPI_TypeDef *)SPI0_BASE)
-#define SPI1	((SPI_TypeDef *)SPI1_BASE)
-#define SPI2	((SPI_TypeDef *)SPI2_BASE)
-
-/* I2C Peripheral_declaration */
-#define I2C0	((I2C_TypeDef *)I2C0_BASE)
-#define I2C1	((I2C_TypeDef *)I2C1_BASE)
-
-/* CAN Peripheral_declaration */
-#define CAN0	((CAN_TypeDef *)CAN0_BASE)
-
-/* DMA Peripheral_declaration */
-#define DMA0	((DMA_TypeDef *)DMA0_BASE)
-
-/* UART Peripheral_declaration */
-#define USART0	((USART_TypeDef *)USART0_BASE)
-#define USART1	((USART_TypeDef *)USART1_BASE)
-#define UART0	((UART_TypeDef *)UART0_BASE)
-#define UART1	((UART_TypeDef *)UART1_BASE)
-#define UART2	((UART_TypeDef *)UART2_BASE)
-#define UART3	((UART_TypeDef *)UART3_BASE)
-#define LPTIM0	((LPTIM_TypeDef *)LPTIM0_BASE)
-#define LPUART0	((LPUART_TypeDef *)LPUART0_BASE)
-#define DBGC	((DBGC_TypeDef *)DBGC_BASE)
-#define WWDT	((WWDT_TypeDef *)WWDT_BASE)
-#define IWDT	((IWDT_TypeDef *)IWDT_BASE)
-
-#define SYSCFG	((SYSCFG_TypeDef *)SYSCFG_BASE)
-#define CMU	((CMU_TypeDef *)CMU_BASE)
-#define RMU	((RMU_TypeDef *)RMU_BASE)
-#define PMU	((PMU_TypeDef *)PMU_BASE)
-#define MSC	((MSC_TypeDef *)MSC_BASE)
+#define LPTIM0		((LPTIM_TypeDef *)LPTIM0_BASE)
+#define LPUART0		((LPUART_TypeDef *)LPUART0_BASE)
+#define ADC0		((ADC_TypeDef *)ADC0_BASE)
+#define ADC1		((ADC_TypeDef *)ADC1_BASE)
+#define ACMP0		((ACMP_TypeDef *)ACMP0_BASE)
+#define ACMP1		((ACMP_TypeDef *)ACMP1_BASE)
+#define OPAMP		((OPAMP_TypeDef *)OPAMP_BASE)
+#define DAC0		((DAC_TypeDef *)DAC0_BASE)
+#define WWDT		((WWDT_TypeDef *)WWDT_BASE)
+#define IWDT		((IWDT_TypeDef *)IWDT_BASE)
+#define LCD     	((LCD_TypeDef *)LCD_BASE)
+#define BKPC		((BKPC_TypeDef *)BKPC_BASE)
+#define RTC		((RTC_TypeDef *)RTC_BASE)
+#define TSENSE		((TSENSE_TypeDef *)TSENSE_BASE)
+#define DBGC		((DBGC_TypeDef *)DBGC_BASE)
+
+/* AHB peripherals */
+#define SYSCFG		((SYSCFG_TypeDef *)SYSCFG_BASE)
+#define CMU		((CMU_TypeDef *)CMU_BASE)
+#define RMU		((RMU_TypeDef *)RMU_BASE)
+#define PMU		((PMU_TypeDef *)PMU_BASE)
+#define MSC		((MSC_TypeDef *)MSC_BASE)
+#define GPIOA		((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB		((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC		((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD		((GPIO_TypeDef *)GPIOD_BASE)
+#define GPIOE		((GPIO_TypeDef *)GPIOE_BASE)
+#define GPIOF		((GPIO_TypeDef *)GPIOF_BASE)
+#define GPIOG		((GPIO_TypeDef *)GPIOG_BASE)
+#define GPIOH		((GPIO_TypeDef *)GPIOH_BASE)
+#define EXTI 		((EXTI_TypeDef *)EXTI_BASE)
+#define CRC		((CRC_TypeDef  *)CRC_BASE)
+#define CALC		((CALC_TypeDef *)CALC_BASE)
+#define CRYPT		((CRYPT_TypeDef *)CRYPT_BASE)
+#define TRNG		((TRNG_TypeDef *)TRNG_BASE)
+#define PIS		((PIS_TypeDef *)PIS_BASE)
 
 #endif