[bsp/renesas][drivers] Added adaptation for ra8p1.

bsp/renesas/libraries/HAL_Drivers/drivers/SConscript

@@ -62,6 +62,9 @@ if GetDepend(['BSP_USING_SDHI']):
 if GetDepend(['BSP_USING_LCD']):
     src += ['drv_lcd.c']
 
+if GetDepend(['BSP_USING_RS485']):
+    src += ['drv_rs485.c']
+
 path =  [cwd]
 path += [cwd + '/config']
 

bsp/renesas/libraries/HAL_Drivers/drivers/config/drv_config.h

@@ -195,6 +195,32 @@ extern "C"
 
 #endif /* SOC_SERIES_R7FA8M85 */
 
+#ifdef SOC_SERIES_R7KA8P1
+
+#include "ra8/uart_config.h"
+
+#ifdef BSP_USING_PWM
+#include "ra8/pwm_config.h"
+#endif
+
+#ifdef BSP_USING_ADC
+#include "ra8/adc_config.h"
+#endif
+
+#ifdef BSP_USING_DAC
+#include "ra8/dac_config.h"
+#endif
+
+#ifdef BSP_USING_TIM
+#include "ra8/timer_config.h"
+#endif
+
+#ifdef BSP_USING_CANFD
+#include "ra8/canfd_config.h"
+#endif
+
+#endif /* SOC_SERIES_R7KA8P1 */
+
 #ifdef SOC_SERIES_R9A07G0
 #include "rzt/uart_config.h"
 #include "rzt/timer_config.h"

bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/adc_config.h

@@ -31,7 +31,11 @@ struct ra_adc_map
     const char *device_name;
     const adc_cfg_t *g_cfg;
     const adc_ctrl_t *g_ctrl;
-    const adc_channel_cfg_t   *g_channel_cfg;
+#ifdef SOC_SERIES_R7KA8P1
+    const adc_b_scan_cfg_t	*g_channel_cfg;
+#else
+    const adc_channel_cfg_t	*g_channel_cfg;
+#endif
 };
 #endif
 #endif

bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/canfd_config.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2025-02-11     kurisaW           first version
+ */
+
+#ifndef __CAN_CONFIG_H__
+#define __CAN_CONFIG_H__
+
+#include <rtthread.h>
+#include "hal_data.h"
+
+#if defined(BSP_USING_CANFD)
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if defined(BSP_USING_CAN0)
+#ifndef CAN0_CONFIG
+#define CAN0_CONFIG                   \
+    {                                 \
+        .name = "canfd0",             \
+        .num_of_mailboxs = 48,        \
+        .p_api_ctrl = &g_canfd0_ctrl, \
+        .p_cfg = &g_canfd0_cfg,       \
+    }
+#endif /* CAN0_CONFIG */
+#endif /* BSP_USING_CAN0 */
+
+#if defined(BSP_USING_CAN1)
+#ifndef CAN1_CONFIG
+#define CAN1_CONFIG                   \
+    {                                 \
+        .name = "canfd1",             \
+        .num_of_mailboxs = 48,        \
+        .p_api_ctrl = &g_canfd1_ctrl, \
+        .p_cfg = &g_canfd1_cfg,       \
+    }
+#endif /* CAN1_CONFIG */
+#endif /* BSP_USING_CAN1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BSP_USING_CANFD */
+
+#endif /* __CAN_CONFIG_H__ */

bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/pwm_config.h

@@ -58,6 +58,9 @@ enum
 #endif
 #ifdef BSP_USING_PWM12
     BSP_PWM12_INDEX,
+#endif
+#ifdef BSP_USING_PWM13
+    BSP_PWM13_INDEX,
 #endif
     BSP_PWMS_NUM
 };

bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/timer_config.h

@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-09-04     Rbb666       first version
+ */
+
+#ifndef __TIMER_CONFIG_H__
+#define __TIMER_CONFIG_H__
+
+#include <rtthread.h>
+#include "hal_data.h"
+
+#ifdef SOC_SERIES_R7KA8P1
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define PLCKD_PRESCALER_MAX_SELECT	9
+#define PLCKD_PRESCALER_250M    	(250000000U)
+#define PLCKD_PRESCALER_200M    	(200000000U)
+#define PLCKD_PRESCALER_100M    	(100000000U)
+#define PLCKD_PRESCALER_50M     	(50000000U)
+#define PLCKD_PRESCALER_25M     	(25000000U)
+#define PLCKD_PRESCALER_12_5M   	(12500000U)
+#define PLCKD_PRESCALER_6_25M   	(6250000U)
+#define PLCKD_PRESCALER_3_125M  	(3125000U)
+#define PLCKD_PRESCALER_1_5625M 	(1562500U)
+
+#ifndef TMR_DEV_INFO_CONFIG
+#define TMR_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 250000000,                   \
+        .minfreq = 1562500,                     \
+        .maxcnt  = 0XFFFFFFFF,                  \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+enum
+{
+#ifdef BSP_USING_TIM0
+    BSP_TIMER0_INDEX,
+#endif
+#ifdef BSP_USING_TIM1
+    BSP_TIMER1_INDEX,
+#endif
+    BSP_TIMERS_NUM
+};
+
+#define TIMER_DRV_INITIALIZER(num)      \
+    {                                   \
+        .name = "timer" #num,           \
+        .g_cfg = &g_timer##num##_cfg,   \
+        .g_ctrl = &g_timer##num##_ctrl, \
+        .g_timer = &g_timer##num,       \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SOC_SERIES_R7KA8P1 */
+
+#endif /* __TIMER_CONFIG_H__ */

bsp/renesas/libraries/HAL_Drivers/drivers/drv_adc.c

@@ -20,6 +20,17 @@
 #endif /* DRV_DEBUG */
 #include <rtdbg.h>
 
+#if defined(SOC_SERIES_R7KA8P1)
+
+#define R_ADC_Open      R_ADC_B_Open
+#define R_ADC_ScanCfg   R_ADC_B_ScanCfg
+#define R_ADC_ScanStart R_ADC_B_ScanStart
+#define R_ADC_Read32    R_ADC_B_Read32
+#define R_ADC_Read    	R_ADC_B_Read
+#define R_ADC_ScanStop  R_ADC_B_ScanStop
+
+#endif
+
 struct ra_adc_map ra_adc[] =
 {
 #ifdef BSP_USING_ADC0
@@ -27,7 +38,11 @@ struct ra_adc_map ra_adc[] =
       .device_name = "adc0",
       .g_cfg = &g_adc0_cfg,
       .g_ctrl = &g_adc0_ctrl,
+#ifdef SOC_SERIES_R7KA8P1
+      .g_channel_cfg = &g_adc0_scan_cfg,
+#else
       .g_channel_cfg = &g_adc0_channel_cfg,
+#endif
     },
 #endif
 #ifdef BSP_USING_ADC1

bsp/renesas/libraries/HAL_Drivers/drivers/drv_can.c

@@ -58,6 +58,45 @@ static const struct ra_baud_rate_tab can_baud_rate_tab[] =
 #define R_CAN_InfoGet               R_CANFD_InfoGet
 #define R_CAN_Write                 R_CANFD_Write
 
+#define can0_callback               canfd0_callback
+#define can1_callback               canfd1_callback
+
+const canfd_afl_entry_t p_canfd0_afl[CANFD_CFG_AFL_CH0_RULE_NUM] =
+{
+    {
+        .id =
+        {
+            .id         = 0x00,
+            .frame_type = CAN_FRAME_TYPE_DATA,
+            .id_mode    = CAN_ID_MODE_STANDARD
+        },
+        .destination =
+        {
+            .minimum_dlc       = CANFD_MINIMUM_DLC_0,
+            .rx_buffer         = CANFD_RX_MB_NONE,
+            .fifo_select_flags = CANFD_RX_FIFO_0
+        }
+    },
+};
+
+const canfd_afl_entry_t p_canfd1_afl[CANFD_CFG_AFL_CH1_RULE_NUM] =
+{
+    {
+        .id =
+        {
+            .id         = 0x01,
+            .frame_type = CAN_FRAME_TYPE_DATA,
+            .id_mode    = CAN_ID_MODE_STANDARD
+        },
+        .destination =
+        {
+            .minimum_dlc       = CANFD_MINIMUM_DLC_1,
+            .rx_buffer         = CANFD_RX_MB_NONE,
+            .fifo_select_flags = CANFD_RX_FIFO_1
+        }
+    },
+};
+
 #endif
 
 static rt_uint32_t get_can_baud_index(rt_uint32_t baud)
@@ -193,7 +232,7 @@ rt_ssize_t ra_can_sendmsg(struct rt_can_device *can_dev, const void *buf, rt_uin
     g_can_tx_frame.id_mode = msg_rt->ide;
     g_can_tx_frame.type = msg_rt->rtr;
     g_can_tx_frame.data_length_code = msg_rt->len;
-#if defined(BSP_USING_CANFD) && defined(BSP_USING_CAN_RZ)
+#if defined(BSP_USING_CANFD) && (defined(BSP_USING_CAN_RZ) || defined(BSP_USING_CAN_RA))
     g_can_tx_frame.options = 0;
 #elif defined(BSP_USING_CANFD)
     g_can_tx_frame.options = CANFD_FRAME_OPTION_FD | CANFD_FRAME_OPTION_BRS;

bsp/renesas/libraries/HAL_Drivers/drivers/drv_dac.c

@@ -21,6 +21,15 @@
 #endif /* DRV_DEBUG */
 #include <rtdbg.h>
 
+#if defined(SOC_SERIES_R7KA8P1)
+
+#define R_DAC_Open  R_DAC_B_Open
+#define R_DAC_Write R_DAC_B_Write
+#define R_DAC_Start R_DAC_B_Start
+#define R_DAC_Stop  R_DAC_B_Stop
+
+#endif
+
 struct ra_dac_map ra_dac[] =
 {
 #ifdef BSP_USING_DAC0

bsp/renesas/libraries/HAL_Drivers/drivers/drv_eth.c

@@ -10,6 +10,7 @@
 * 2019-06-10     SummerGift   optimize PHY state detection process
 * 2019-09-03     xiaofan      optimize link change detection process
 * 2025-02-11     kurisaW      adaptation for RZ Ethernet driver
+* 2025-12-01     yans         adaptation for RA8P1 Ethernet driver
 */
 
 #include "drv_config.h"
@@ -22,7 +23,11 @@
 // #define ETH_RX_DUMP
 // #define ETH_TX_DUMP
 #define MINIMUM_ETHERNET_FRAME_SIZE (60U)
+#ifdef SOC_SERIES_R7KA8P1
+#define ETH_MAX_PACKET_SIZE (1514U)
+#else
 #define ETH_MAX_PACKET_SIZE (2048U)
+#endif
 #define ETHER_GMAC_INTERRUPT_FACTOR_RECEPTION (0x000000C0)
 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
@@ -52,6 +57,34 @@ static uint8_t g_link_change = 0; ///< Link change (bit0:port0, bit1:port1, bit2
 static uint8_t g_link_status = 0; ///< Link status (bit0:port0, bit1:port1, bit2:port2)
 static uint8_t previous_link_status = 0;
 
+/* Multi-PHY support structures */
+typedef struct
+{
+#if defined(SOC_SERIES_R7KA8P1)
+    rmac_phy_instance_ctrl_t *p_ctrl;
+#else
+    ether_phy_instance_ctrl_t *p_ctrl;
+#endif
+    uint8_t port_bit;
+    const char *name;
+} phy_port_info_t;
+
+static const phy_port_info_t phy_ports[] =
+{
+#if defined(SOC_SERIES_R7KA8P1)
+    { &g_rmac_phy0_ctrl,  0x01, "PHY0" },
+    { &g_rmac_phy1_ctrl,  0x02, "PHY1" },
+#elif defined(SOC_SERIES_R9A07G0)
+    { &g_ether_phy0_ctrl, 0x01, "PHY0" },
+    { &g_ether_phy1_ctrl, 0x02, "PHY1" },
+    { &g_ether_phy2_ctrl, 0x04, "PHY2" },
+#else
+    { &g_ether_phy0_ctrl, 0x01, "PHY"  },
+#endif
+};
+
+#define PHY_PORTS_COUNT (sizeof(phy_ports) / sizeof(phy_ports[0]))
+
 #if defined(SOC_SERIES_R9A07G0)
 
 #define status_ecsr             status_link
@@ -62,6 +95,14 @@ static uint8_t previous_link_status = 0;
 #define R_ETHER_Read        R_GMAC_Read
 #define R_ETHER_LinkProcess R_GMAC_LinkProcess
 
+#elif defined(SOC_SERIES_R7KA8P1)
+
+#define R_ETHER_Open                R_RMAC_Open
+#define R_ETHER_Write               R_RMAC_Write
+#define R_ETHER_Read                R_RMAC_Read
+#define R_ETHER_LinkProcess         R_RMAC_LinkProcess
+#define R_ETHER_PHY_LinkStatusGet   R_RMAC_PHY_LinkStatusGet
+
 #endif
 
 #if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP)
@@ -90,7 +131,6 @@ static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
 }
 #endif
 
-extern void phy_reset(void);
 /* EMAC initialization function */
 static rt_err_t rt_ra_eth_init(void)
 {
@@ -139,6 +179,8 @@ static rt_err_t rt_ra_eth_control(rt_device_t dev, int cmd, void *args)
         {
 #if defined(SOC_SERIES_R9A07G0)
             SMEMCPY(args, g_ether0_ctrl.p_gmac_cfg->p_mac_address, 6);
+#elif defined(SOC_SERIES_R7KA8P1)
+            SMEMCPY(args, g_ether0_ctrl.p_cfg->p_mac_address, 6);
 #else
             SMEMCPY(args, g_ether0_ctrl.p_ether_cfg->p_mac_address, 6);
 #endif
@@ -209,9 +251,15 @@ rt_err_t rt_ra_eth_tx(rt_device_t dev, struct pbuf *p)
         }
     }
 #endif
-    res = R_ETHER_Write(&g_ether0_ctrl, buffer, p->tot_len);//>MINIMUM_ETHERNET_FRAME_SIZE?p->tot_len:MINIMUM_ETHERNET_FRAME_SIZE);
+#if defined(__DCACHE_PRESENT)
+    SCB_CleanInvalidateDCache();
+#endif
+    res = R_ETHER_Write(&g_ether0_ctrl, buffer, p->tot_len < MINIMUM_ETHERNET_FRAME_SIZE ?  MINIMUM_ETHERNET_FRAME_SIZE : p->tot_len);
     if (res != FSP_SUCCESS)
+    {
         LOG_W("R_ETHER_Write failed!, res = %d", res);
+        return (err_t)ERR_USE;
+    }
     return RT_EOK;
 }
 
@@ -234,10 +282,19 @@ struct pbuf *rt_ra_eth_rx(rt_device_t dev)
 
     LOG_D("receive frame len : %d", len);
 
+#if defined(__DCACHE_PRESENT)
+    SCB_CleanInvalidateDCache();
+#endif
+
     if (len > 0)
     {
         /* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
         p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
+        if (p == NULL)
+        {
+            LOG_E("Failed to allocate pbuf for %d bytes", len);
+            return NULL;
+        }
     }
 
 #ifdef ETH_RX_DUMP
@@ -290,61 +347,77 @@ static void phy_linkchange()
     fsp_err_t res;
     uint8_t port = 0;
     uint8_t port_bit = 0;
-
-#if defined(SOC_SERIES_R9A07G0)
-    gmac_link_status_t port_status;
-#endif
+    uint8_t status_change;
+    uint8_t current_link_status = 0;
+    uint8_t i;
 
     res = R_ETHER_LinkProcess(&g_ether0_ctrl);
     if (res != FSP_SUCCESS)
         LOG_D("R_ETHER_LinkProcess failed!, res = %d", res);
 
+#if !defined(SOC_SERIES_R7KA8P1) && !defined(SOC_SERIES_R7FA6M3)
     if (0 == g_ether0.p_cfg->p_callback)
+#endif
     {
-        for (port = 0; port < PING_PORT_COUNT; port++)
+        /* Check link status for all PHY ports */
+        for (i = 0; i < PHY_PORTS_COUNT; i++)
         {
-#if defined(SOC_SERIES_R9A07G0)
-            res = R_GMAC_GetLinkStatus(&g_ether0_ctrl, port, &port_status);
-#else
-            res = R_ETHER_PHY_LinkStatusGet(&g_ether_phy0_ctrl);
-#endif
-            if (FSP_SUCCESS != res)
+            res = R_ETHER_PHY_LinkStatusGet(phy_ports[i].p_ctrl);
+
+            // ETHER_PHY successfully get link partner ability.
+            if (res == FSP_SUCCESS)
             {
-                /* An error has occurred */
-                LOG_E("PHY_LinkStatus get failed!, res = %d", res);
-                break;
+                current_link_status |= phy_ports[i].port_bit; /* Port link up */
+
+                status_change = previous_link_status ^ current_link_status;
+                if (status_change & phy_ports[i].port_bit)
+                {
+                    g_link_change |= phy_ports[i].port_bit;
+                    LOG_I("%s Manual Link status changed: UP", phy_ports[i].name);
+                }
             }
-
-            /* Set link up */
-            g_link_status |= (uint8_t)(1U << port);
-        }
-        if (FSP_SUCCESS == res)
-        {
-            /* Set changed link status */
-            g_link_change = previous_link_status ^ g_link_status;
+            // PHY-LSI is not link up.
+            else if (res == FSP_ERR_ETHER_PHY_ERROR_LINK)
+            {
+                current_link_status &= ~(phy_ports[i].port_bit); /* Port link down */
+
+                status_change = previous_link_status ^ current_link_status;
+                if (status_change & phy_ports[i].port_bit)
+                {
+                    g_link_change |= phy_ports[i].port_bit;
+                    LOG_I("%s Manual Link status changed: DOWN", phy_ports[i].name);
+                }
+            }
+            else
+            {
+                LOG_E("%s PHY_Read failed!, res = %d", phy_ports[i].name, res);
+            }
+            /* Update global link status */
+            g_link_status = current_link_status;
         }
     }
 
-    for (port = 0; port < PING_PORT_COUNT; port++)
+    /* Process link changes for all ports */
+    for (port = 0; port < PHY_PORTS_COUNT; port++)
     {
-        port_bit = (uint8_t)(1U << port);
+        port_bit = phy_ports[port].port_bit;
 
         if (g_link_change & port_bit)
         {
             /* Link status changed */
-            g_link_change &= (uint8_t)(~port_bit); // change bit clear
+            g_link_change &= (uint8_t)(~port_bit); /* change bit clear */
 
             if (g_link_status & port_bit)
             {
                 /* Changed to Link-up */
                 eth_device_linkchange(&ra_eth_device.parent, RT_TRUE);
-                LOG_I("link up");
+                LOG_I("%s link up", phy_ports[port].name);
             }
             else
             {
                 /* Changed to Link-down */
                 eth_device_linkchange(&ra_eth_device.parent, RT_FALSE);
-                LOG_I("link down");
+                LOG_I("%s link down", phy_ports[port].name);
             }
         }
     }
@@ -371,7 +444,11 @@ void user_ether0_callback(ether_callback_args_t *p_args)
     case ETHER_EVENT_WAKEON_LAN:    ///< Magic packet detection event
     /* If EDMAC FR (Frame Receive Event) or FDE (Receive Descriptor Empty Event)
         * interrupt occurs, send rx mailbox. */
+#if defined(SOC_SERIES_R7KA8P1)
+    case ETHER_EVENT_RX_COMPLETE: ///< BSD Interrupt event
+#else
     case ETHER_EVENT_INTERRUPT: ///< BSD Interrupt event
+#endif
     {
         rt_err_t result;
         result = eth_device_ready(&(ra_eth_device.parent));

bsp/renesas/libraries/HAL_Drivers/drivers/drv_eth.h

@@ -105,6 +105,5 @@
 
 #define PHY_LINK (1 << 0)
 #define PHY_100M (1 << 1)
-#define PING_PORT_COUNT (3) ///< Count of port
 
 #endif /* __DRV_ETH_H__ */

bsp/renesas/libraries/HAL_Drivers/drivers/drv_gpio.c

@@ -109,6 +109,58 @@ static void ra_pin_map_init(void)
     pin_irq_map[15].irq_ctrl = &g_external_irq15_ctrl;
     pin_irq_map[15].irq_cfg = &g_external_irq15_cfg;
 #endif
+#if defined(VECTOR_NUMBER_ICU_IRQ16) || (VECTOR_NUMBER_IRQ016)
+    pin_irq_map[16].irq_ctrl = &g_external_irq16_ctrl;
+    pin_irq_map[16].irq_cfg = &g_external_irq16_cfg;
+#endif
+#if defined(VECTOR_NUMBER_ICU_IRQ17) || (VECTOR_NUMBER_IRQ017)
+    pin_irq_map[17].irq_ctrl = &g_external_irq17_ctrl;
+    pin_irq_map[17].irq_cfg = &g_external_irq17_cfg;
+#endif
+#if defined(VECTOR_NUMBER_ICU_IRQ18) || (VECTOR_NUMBER_IRQ018)
+    pin_irq_map[18].irq_ctrl = &g_external_irq18_ctrl;
+    pin_irq_map[18].irq_cfg = &g_external_irq18_cfg;
+#endif
+#if defined(VECTOR_NUMBER_ICU_IRQ19) || (VECTOR_NUMBER_IRQ019)
+    pin_irq_map[19].irq_ctrl = &g_external_irq19_ctrl;
+    pin_irq_map[19].irq_cfg = &g_external_irq19_cfg;
+#endif
+#if defined(VECTOR_NUMBER_ICU_IRQ20) || (VECTOR_NUMBER_IRQ020)
+    pin_irq_map[20].irq_ctrl = &g_external_irq20_ctrl;
+    pin_irq_map[20].irq_cfg = &g_external_irq20_cfg;
+#endif
+#if defined(VECTOR_NUMBER_ICU_IRQ21) || (VECTOR_NUMBER_IRQ021)
+    pin_irq_map[21].irq_ctrl = &g_external_irq21_ctrl;
+    pin_irq_map[21].irq_cfg = &g_external_irq21_cfg;
+#endif
+#if defined(VECTOR_NUMBER_ICU_IRQ22) || (VECTOR_NUMBER_IRQ022)
+    pin_irq_map[22].irq_ctrl = &g_external_irq22_ctrl;
+    pin_irq_map[22].irq_cfg = &g_external_irq22_cfg;
+#endif
+#if defined(VECTOR_NUMBER_ICU_IRQ23) || (VECTOR_NUMBER_IRQ023)
+    pin_irq_map[23].irq_ctrl = &g_external_irq23_ctrl;
+    pin_irq_map[23].irq_cfg = &g_external_irq23_cfg;
+#endif
+#if defined(VECTOR_NUMBER_ICU_IRQ24) || (VECTOR_NUMBER_IRQ024)
+    pin_irq_map[24].irq_ctrl = &g_external_irq24_ctrl;
+    pin_irq_map[24].irq_cfg = &g_external_irq24_cfg;
+#endif
+#if defined(VECTOR_NUMBER_ICU_IRQ25) || (VECTOR_NUMBER_IRQ025)
+    pin_irq_map[25].irq_ctrl = &g_external_irq25_ctrl;
+    pin_irq_map[25].irq_cfg = &g_external_irq25_cfg;
+#endif
+#if defined(VECTOR_NUMBER_ICU_IRQ26) || (VECTOR_NUMBER_IRQ026)
+    pin_irq_map[26].irq_ctrl = &g_external_irq26_ctrl;
+    pin_irq_map[26].irq_cfg = &g_external_irq26_cfg;
+#endif
+#if defined(VECTOR_NUMBER_ICU_IRQ27) || (VECTOR_NUMBER_IRQ027)
+    pin_irq_map[27].irq_ctrl = &g_external_irq27_ctrl;
+    pin_irq_map[27].irq_cfg = &g_external_irq27_cfg;
+#endif
+#if defined(VECTOR_NUMBER_ICU_IRQ28) || (VECTOR_NUMBER_IRQ028)
+    pin_irq_map[28].irq_ctrl = &g_external_irq28_ctrl;
+    pin_irq_map[28].irq_cfg = &g_external_irq28_cfg;
+#endif
 }
 #endif  /* R_ICU_H */
 

bsp/renesas/libraries/HAL_Drivers/drivers/drv_hwtimer.c

@@ -47,6 +47,16 @@ const rt_uint32_t PLCKD_FREQ_PRESCALER[PLCKD_PRESCALER_MAX_SELECT] =
     PLCKD_PRESCALER_6_25M,
     PLCKD_PRESCALER_3_125M,
     PLCKD_PRESCALER_1_5625M
+#elif defined(SOC_SERIES_R7KA8P1)
+    PLCKD_PRESCALER_250M,
+    PLCKD_PRESCALER_200M,
+    PLCKD_PRESCALER_100M,
+    PLCKD_PRESCALER_50M,
+    PLCKD_PRESCALER_25M,
+    PLCKD_PRESCALER_12_5M,
+    PLCKD_PRESCALER_6_25M,
+    PLCKD_PRESCALER_3_125M,
+    PLCKD_PRESCALER_1_5625M
 #endif
 };
 
@@ -117,11 +127,19 @@ static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
 
     tim = (struct ra_hwtimer *)timer->parent.user_data;
 
+#if defined(SOC_SERIES_R7KA8P1)
+    timer_info_t info;
+    if (R_GPT_InfoGet(tim->g_ctrl, &info) != FSP_SUCCESS)
+        return -RT_ERROR;
+
+    return info.period_counts;
+#else
     timer_status_t status;
     if (R_GPT_StatusGet(tim->g_ctrl, &status) != FSP_SUCCESS)
         return -RT_ERROR;
 
     return status.counter;
+#endif
 }
 
 static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)

bsp/renesas/libraries/HAL_Drivers/drivers/drv_lcd.c

@@ -14,6 +14,8 @@
 #ifdef BSP_USING_LCD
 #ifdef SOC_SERIES_R7FA8M85
 #include <ra8/lcd_config.h>
+#elif defined(SOC_SERIES_R7KA8P1)
+#include <lcd_port.h>
 #else
 #include <ra6m3/lcd_config.h>
 #endif
@@ -24,6 +26,7 @@
 #define DRV_DEBUG
 #define LOG_TAG             "drv_lcd"
 #include <drv_log.h>
+
 struct drv_lcd_device
 {
     struct rt_device parent;
@@ -39,7 +42,7 @@ static uint16_t *gp_double_buffer = NULL;
 static uint16_t *lcd_current_working_buffer = (uint16_t *) &fb_background[0];
 
 #ifdef SOC_SERIES_R7FA8M85
-static uint8_t lcd_framebuffer[LCD_BUF_SIZE] BSP_ALIGN_VARIABLE(64) BSP_PLACE_IN_SECTION(".sdram");
+static uint8_t lcd_framebuffer[LCD_BUF_SIZE] rt_align(64) rt_section(".sdram") rt_used;
 #endif
 
 // G2D
@@ -47,7 +50,7 @@ extern d2_device *d2_handle0;
 static d2_device **_d2_handle_user = &d2_handle0;
 static d2_renderbuffer *renderbuffer;
 
-#ifdef SOC_SERIES_R7FA8M85
+#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1)
 extern void ra8_mipi_lcd_init(void);
 #endif
 
@@ -85,7 +88,7 @@ static void turn_on_lcd_backlight(void)
 
 static void ra_bsp_lcd_clear(uint16_t color)
 {
-    for (uint32_t i = 0; i < LCD_BUF_SIZE; i++)
+    for (uint32_t i = 0; i <= LCD_BUF_SIZE / sizeof(uint16_t); i++)
     {
         lcd_current_working_buffer[i] = color;
     }
@@ -262,7 +265,7 @@ static rt_err_t ra_lcd_control(rt_device_t device, int cmd, void *args)
     {
     case RTGRAPHIC_CTRL_RECT_UPDATE:
     {
-#ifdef SOC_SERIES_R7FA8M85
+#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1)
         struct rt_device_rect_info *info = (struct rt_device_rect_info *)args;
 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
         SCB_CleanInvalidateDCache_by_Addr((uint32_t *)lcd->lcd_info.framebuffer, sizeof(fb_background[0]));
@@ -279,7 +282,7 @@ static rt_err_t ra_lcd_control(rt_device_t device, int cmd, void *args)
         fsp_err_t err = R_GLCDC_BufferChange(&g_display0_ctrl, (uint8_t *) lcd_current_working_buffer, DISPLAY_FRAME_LAYER_1);
         RT_ASSERT(err == 0);
 #endif
-#endif  /* SOC_SERIES_R7FA8M85 */
+#endif  /* SOC_SERIES_R7FA8M85 | SOC_SERIES_R7KA8P1 */
         /* wait for vsync interrupt */
         vsync_wait();
     }
@@ -340,7 +343,7 @@ static rt_err_t ra_bsp_lcd_init(void)
     error = R_GLCDC_Open(&g_display0_ctrl, &g_display0_cfg);
     if (FSP_SUCCESS == error)
     {
-#ifdef SOC_SERIES_R7FA8M85
+#if (defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1)) && defined(BSP_USING_MIPI_LCD)
         /* config mipi */
         ra8_mipi_lcd_init();
 #endif
@@ -408,7 +411,7 @@ int rt_hw_lcd_init(void)
 }
 INIT_DEVICE_EXPORT(rt_hw_lcd_init);
 
-#ifdef SOC_SERIES_R7FA8M85
+#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1)
 rt_weak void ra8_mipi_lcd_init(void)
 {
     LOG_E("please Implementation function %s", __func__);

bsp/renesas/libraries/HAL_Drivers/drivers/drv_pwm.c

@@ -51,6 +51,18 @@ static struct ra_pwm ra6m4_pwm_obj[BSP_PWMS_NUM] =
 #ifdef BSP_USING_PWM9
     [BSP_PWM9_INDEX] = PWM_DRV_INITIALIZER(9),
 #endif
+#ifdef BSP_USING_PWM10
+    [BSP_PWM10_INDEX] = PWM_DRV_INITIALIZER(10),
+#endif
+#ifdef BSP_USING_PWM11
+    [BSP_PWM11_INDEX] = PWM_DRV_INITIALIZER(11),
+#endif
+#ifdef BSP_USING_PWM12
+    [BSP_PWM12_INDEX] = PWM_DRV_INITIALIZER(12),
+#endif
+#ifdef BSP_USING_PWM13
+    [BSP_PWM13_INDEX] = PWM_DRV_INITIALIZER(13),
+#endif
 };
 
 #ifdef SOC_SERIES_R9A07G0

bsp/renesas/libraries/HAL_Drivers/drivers/drv_rs485.c

@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2025-07-22     kurisaw           first version
+ */
+
+#include <rtdevice.h>
+#include <hal_data.h>
+#include "drv_rs485.h"
+
+#define DBG_TAG "drv.rs485"
+#define DBG_LVL DBG_LOG
+#include <rtdbg.h>
+
+#ifdef BSP_USING_RS485
+
+#define RS485_OUT       rt_pin_write((rt_base_t)RS485_DE_PIN, PIN_HIGH)
+#define RS485_IN        rt_pin_write((rt_base_t)RS485_DE_PIN, PIN_LOW)
+
+static rt_device_t rs485_serial = RT_NULL;
+static struct rt_semaphore rs485_rx_sem;
+static struct rt_ringbuffer rs485_rx_rb;
+static rt_uint8_t rs485_rx_buffer[RS485_RX_BUFFER_SIZE];
+
+/* uart receive data callback function */
+static rt_err_t rs485_input(rt_device_t dev, rt_size_t size)
+{
+    if (size > 0)
+    {
+        rt_uint8_t ch;
+        while (rt_device_read(dev, 0, &ch, 1) == 1)
+        {
+            rt_ringbuffer_put_force(&rs485_rx_rb, &ch, 1);
+        }
+        rt_sem_release(&rs485_rx_sem);
+    }
+    return RT_EOK;
+}
+
+/* send data */
+int rs485_send_data(const void *tbuf, rt_uint16_t t_len)
+{
+    RT_ASSERT(tbuf != RT_NULL);
+
+    /* change rs485 mode to transmit */
+    RS485_OUT;
+
+    /* send data */
+    rt_size_t sent = rt_device_write(rs485_serial, 0, tbuf, t_len);
+
+    if (sent != t_len)
+    {
+        /* Transmission failed, switch back to receive mode */
+        RS485_IN;
+        return -RT_ERROR;
+    }
+
+    /* Note: We don't switch back to receive mode here -
+       that will be done in the tx_complete callback (rs485_output) */
+
+    LOG_I("send==>>");
+    for (int i = 0; i < t_len; i++)
+    {
+        LOG_I("   %d:   %c ", i, ((rt_uint8_t *)tbuf)[i]);
+    }
+    RS485_IN;
+
+    return RT_EOK;
+}
+
+#ifndef BSP_USING_LED_MATRIX_RS485_DEMO
+static void rs485_thread_entry(void *parameter)
+{
+    rt_uint8_t ch;
+    rt_size_t length;
+
+    while (1)
+    {
+        /* Wait for data */
+        rt_sem_take(&rs485_rx_sem, RT_WAITING_FOREVER);
+
+        /* Process all available data in the ring buffer */
+        while (length = rt_ringbuffer_get(&rs485_rx_rb, &ch, 1))
+        {
+            if (length == 1)
+            {
+                LOG_I("recv data:%c", ch);
+            }
+        }
+    }
+}
+#endif
+
+/* rs485 rts pin init */
+int rs485_init(void)
+{
+    /* Initialize ring buffer */
+    rt_ringbuffer_init(&rs485_rx_rb, rs485_rx_buffer, RS485_RX_BUFFER_SIZE);
+
+    /* find uart device */
+    rs485_serial = rt_device_find(RS485_UART_DEVICE_NAME);
+    if (!rs485_serial)
+    {
+        LOG_E("find %s failed!", RS485_UART_DEVICE_NAME);
+        return -RT_ERROR;
+    }
+
+    /* Open device in interrupt mode with DMA support if available */
+    rt_device_open(rs485_serial, RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX);
+
+    /* set receive data callback function */
+    rt_device_set_rx_indicate(rs485_serial, rs485_input);
+
+    /* Initialize RTS pin */
+    rt_pin_mode((rt_base_t)RS485_DE_PIN, PIN_MODE_OUTPUT);
+    RS485_IN;
+
+    /* Initialize semaphore */
+    rt_sem_init(&rs485_rx_sem, "rs485_rx_sem", 0, RT_IPC_FLAG_FIFO);
+
+    rt_thread_t thread = rt_thread_create("rs485", rs485_thread_entry, RT_NULL,
+                                        1024, 25, 10);
+
+    if (thread != RT_NULL)
+    {
+        rt_thread_startup(thread);
+    }
+    else
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rs485_init);
+
+void rs485_cmd(int argc, char **argv)
+{
+    if (argc == 1)
+    {
+        LOG_I("Usage:");
+        LOG_I("rs485_cmd -t <message>  -- send message via RS485");
+    }
+    else if (argc == 3 && rt_strcmp(argv[1], "-t") == 0)
+    {
+        char *str = argv[2];
+        rs485_send_data(str, rt_strnlen(str, 32));
+    }
+
+    return;
+}
+MSH_CMD_EXPORT(rs485_cmd, rs485 transmission cmd);
+
+#endif /* BSP_USING_RS485 */

bsp/renesas/libraries/HAL_Drivers/drivers/drv_rs485.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2025-07-22     kurisaw           first version
+ */
+
+#ifndef __DRV_RS485_H__
+#define __DRV_RS485_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RS485_SEND_MODE      0
+#define RS485_RECV_MODE      1
+
+extern int rs485_send_data(const void *tbuf, rt_uint16_t t_len);
+extern int rs485_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* drv_rs485.h */

bsp/renesas/libraries/HAL_Drivers/drivers/drv_sci.c

@@ -461,7 +461,7 @@ static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
         {
             //LOG_E("10Bit not support");
             //break;
-#ifdef SOC_SERIES_R7FA8M85
+#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1)
             R_SCI_B_I2C_SlaveAddressSet(master_ctrl, msg->addr, I2C_MASTER_ADDR_MODE_10BIT);
 #else
             R_SCI_I2C_SlaveAddressSet(master_ctrl, msg->addr, I2C_MASTER_ADDR_MODE_10BIT);
@@ -470,7 +470,7 @@ static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
         else
         {
             //master_ctrl->slave = msg->addr;
-#ifdef SOC_SERIES_R7FA8M85
+#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1)
             R_SCI_B_I2C_SlaveAddressSet(master_ctrl, msg->addr, I2C_MASTER_ADDR_MODE_7BIT);
 #else
             R_SCI_I2C_SlaveAddressSet(master_ctrl, msg->addr, I2C_MASTER_ADDR_MODE_7BIT);
@@ -479,7 +479,7 @@ static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
 
         if (msg->flags & RT_I2C_RD)
         {
-#ifdef SOC_SERIES_R7FA8M85
+#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1)
             err = R_SCI_B_I2C_Read(master_ctrl, msg->buf, msg->len, restart);
 #else
             err = R_SCI_I2C_Read(master_ctrl, msg->buf, msg->len, restart);
@@ -487,7 +487,7 @@ static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
         }
         else
         {
-#ifdef SOC_SERIES_R7FA8M85
+#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1)
             err = R_SCI_B_I2C_Write(master_ctrl, msg->buf, msg->len, restart);
 #else
             err = R_SCI_I2C_Write(master_ctrl, msg->buf, msg->len, restart);
@@ -783,7 +783,7 @@ static int ra_hw_sci_init(void)
                 obj->ibus.ops = param->ops;
                 obj->ibus.priv = 0;
                 /* opening IIC master module */
-#ifdef SOC_SERIES_R7FA8M85
+#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1)
                 err = R_SCI_B_I2C_Open((i2c_master_ctrl_t *)param->sci_ctrl, param->sci_cfg);
 #else
                 err = R_SCI_I2C_Open((i2c_master_ctrl_t *)param->sci_ctrl, param->sci_cfg);
@@ -793,7 +793,7 @@ static int ra_hw_sci_init(void)
                     LOG_E("R_IIC_MASTER_Open API failed,%d", err);
                     continue;
                 }
-#ifdef SOC_SERIES_R7FA8M85
+#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1)
                 err = R_SCI_B_I2C_CallbackSet((i2c_master_ctrl_t *)param->sci_ctrl, sci_i2c_irq_callback, obj, NULL);
 #else
                 err = R_SCI_I2C_CallbackSet((i2c_master_ctrl_t *)param->sci_ctrl, sci_i2c_irq_callback, obj, NULL);

bsp/renesas/libraries/HAL_Drivers/drivers/drv_sdhi.c

@@ -9,7 +9,6 @@
  */
 
 #include <drv_sdhi.h>
-struct ra_sdhi sdhi;
 
 #define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER)
 #define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex);
@@ -20,12 +19,18 @@ struct rthw_sdio
     struct ra_sdhi sdhi_des;
     struct rt_event event;
     struct rt_mutex mutex;
+    rt_uint8_t *cache_buf;
 };
 
-static struct rt_mmcsd_host *host;
+#ifdef BSP_USING_SDHI0
+    static struct rt_mmcsd_host *host0;
+#endif
+#ifdef BSP_USING_SDHI1
+    static struct rt_mmcsd_host *host1;
+#endif
 
 rt_align(SDIO_ALIGN_LEN)
-static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
+static rt_uint8_t cache_buf1[SDIO_BUFF_SIZE], cache_buf2[SDIO_BUFF_SIZE];
 
 rt_err_t command_send(sdhi_instance_ctrl_t *p_ctrl, struct rt_mmcsd_cmd *cmd)
 {
@@ -302,14 +307,20 @@ void ra_sdhi_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
             rt_uint32_t size = data->blks * data->blksize;
 
             RT_ASSERT(size <= SDIO_BUFF_SIZE);
-
+            /* 使用 SDIO WiFi(cyw43438) 时不使用数据流模式 */
+#if defined(SOC_SERIES_R7KA8P1)
+            if (data->flags & DATA_STREAM)
+            {
+                data->flags &= ~DATA_STREAM;
+            }
+#endif
             buffer = (rt_uint8_t *)data->buf;
             if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))
             {
-                buffer = cache_buf;
+                buffer = sdio->cache_buf;
                 if (data->flags & DATA_DIR_WRITE)
                 {
-                    rt_memcpy(cache_buf, data->buf, size);
+                    rt_memcpy(sdio->cache_buf, data->buf, size);
                 }
             }
             if (data->flags & DATA_DIR_WRITE)
@@ -319,6 +330,9 @@ void ra_sdhi_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
             else if (data->flags & DATA_DIR_READ)
             {
                 transfer_read(sdio->sdhi_des.instance->p_ctrl, data->blks, data->blksize, buffer);
+#if defined(__DCACHE_PRESENT)
+                SCB_CleanInvalidateDCache();
+#endif
             }
             /* Set the sector count. */
             if (data->blks > 1U)
@@ -337,7 +351,10 @@ void ra_sdhi_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
         rt_exit_critical();
         if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)))
         {
-            rt_memcpy(data->buf, cache_buf, data->blksize * data->blks);
+#if defined(__DCACHE_PRESENT)
+            SCB_CleanInvalidateDCache_by_Addr((uint32_t*)((uint32_t)sdio->cache_buf & ~(32U - 1U)), data->blks * data->blksize + 32U);
+#endif
+            rt_memcpy(data->buf, sdio->cache_buf, data->blksize * data->blks);
         }
     }
 
@@ -384,7 +401,11 @@ static rt_err_t clock_rate_set(sdhi_instance_ctrl_t *p_ctrl, uint32_t max_rate)
                     /* Set the calculated divider and enable clock output to start the 74 clocks required before
                      * initialization. Do not change the automatic clock control setting. */
                     uint32_t clkctrlen = p_ctrl->p_reg->SD_CLK_CTRL & (1U << 9);
-                    p_ctrl->p_reg->SD_CLK_CTRL = setting | clkctrlen | (1U << 8);
+#if defined(SOC_SERIES_R7KA8P1)
+                    p_ctrl->p_reg->SD_CLK_CTRL = 0x0100 | 0x00FF;
+#else
+                   p_ctrl->p_reg->SD_CLK_CTRL = setting | clkctrlen | (1U << 8);
+#endif
                     p_ctrl->device.clock_rate = frequency >> divisor_shift;
 
                     return RT_EOK;
@@ -445,11 +466,52 @@ struct rt_mmcsd_host_ops ra_sdhi_ops =
     .enable_sdio_irq = ra_sdhi_enable_sdio_irq
 };
 
-void sdhi_callback(sdmmc_callback_args_t *p_args)
+/**
+  * @brief  This function interrupt process function.
+  * @param  host  rt_mmcsd_host
+  * @retval None
+  */
+void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
+{
+    struct rthw_sdio *sdio = host->private_data;
+    rt_event_send(&sdio->event, 0xffffffff);
+}
+
+#ifdef BSP_USING_SDHI0
+void sdhi0_callback(sdmmc_callback_args_t *p_args)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if ((SDMMC_EVENT_ERASE_COMPLETE | SDMMC_EVENT_TRANSFER_COMPLETE) & p_args->event)
+    {
+       /* Process All SDIO Interrupt Sources */
+        rthw_sdio_irq_process(host0);
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_SDHI1
+void sdhi1_callback(sdmmc_callback_args_t *p_args)
 {
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if ((SDMMC_EVENT_ERASE_COMPLETE | SDMMC_EVENT_TRANSFER_COMPLETE) & p_args->event)
+    {
+       /* Process All SDIO Interrupt Sources */
+        rthw_sdio_irq_process(host1);
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
 }
+#endif
 
-struct rt_mmcsd_host *sdio_host_create(struct ra_sdhi *sdhi_des)
+struct rt_mmcsd_host *sdio_host_create(struct ra_sdhi *sdhi_des, rt_uint8_t cache_buf[SDIO_BUFF_SIZE])
 {
     struct rt_mmcsd_host *host;
     struct rthw_sdio *sdio = RT_NULL;
@@ -461,6 +523,7 @@ struct rt_mmcsd_host *sdio_host_create(struct ra_sdhi *sdhi_des)
     if (sdio == RT_NULL)
         return RT_NULL;
     rt_memset(sdio, 0, sizeof(struct rthw_sdio));
+    sdio->cache_buf = cache_buf;
 
     host = mmcsd_alloc_host();
     if (host == RT_NULL)
@@ -472,17 +535,17 @@ struct rt_mmcsd_host *sdio_host_create(struct ra_sdhi *sdhi_des)
     rt_memcpy(&sdio->sdhi_des, sdhi_des, sizeof(struct ra_sdhi));
 
     rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO);
-    rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO);
+    rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_PRIO);
 
-    /* set host defautl attributes */
+    /* set host default attributes */
     host->ops = &ra_sdhi_ops;
     host->freq_min = 400 * 1000;
     host->freq_max = SDIO_MAX_FREQ;
     host->valid_ocr = 0X00FFFF80; /* The voltage range supported is 1.65v-3.6v */
 #ifndef SDHI_USING_1_BIT
-    host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
+    host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ | MMCSD_SUP_HIGHSPEED;
 #else
-    host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
+    host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ | MMCSD_SUP_HIGHSPEED;
 #endif
     host->max_seg_size = SDIO_BUFF_SIZE;
     host->max_dma_segs = 1;
@@ -496,7 +559,9 @@ struct rt_mmcsd_host *sdio_host_create(struct ra_sdhi *sdhi_des)
     ra_sdhi_enable_sdio_irq(host, 1);
 
     /* ready to change */
-//    mmcsd_change(host);
+#if defined (SOC_SERIES_R7KA8P1)
+    mmcsd_change(host);
+#endif
 
     return host;
 }
@@ -504,24 +569,44 @@ struct rt_mmcsd_host *sdio_host_create(struct ra_sdhi *sdhi_des)
 int rt_hw_sdhi_init(void)
 {
 #if defined(BSP_USING_SDHI0)
-    sdhi.instance = &g_sdmmc0;
-#elif defined(BSP_USING_SDHI1)
-    sdhi.instance = &g_sdmmc1;
+    struct ra_sdhi sdhi0;
+    sdhi0.instance = &g_sdmmc0;
+#ifndef SDHI_USING_1_BIT
+    sdhi0.bus_width = MMCSD_BUS_WIDTH_4;
 #else
-#error "please defined the g_sdmmc handle"
+    sdhi0.bus_width = MMCSD_BUS_WIDTH_1;
 #endif
-
-    sdhi.instance->p_api->open(sdhi.instance->p_ctrl, sdhi.instance->p_cfg);
-    host = sdio_host_create(&sdhi);
-    if (host == RT_NULL)
+    sdhi0.instance->p_api->open(sdhi0.instance->p_ctrl, sdhi0.instance->p_cfg);
+    host0 = sdio_host_create(&sdhi0, cache_buf1);
+    if (host0 == RT_NULL)
     {
         return -1;
     }
+#endif
+#if defined(BSP_USING_SDHI1)
+    struct ra_sdhi sdhi1;
+    sdhi1.instance = &g_sdmmc1;
+#ifndef SDHI_USING_1_BIT
+    sdhi1.bus_width = MMCSD_BUS_WIDTH_4;
+#else
+    sdhi1.bus_width = MMCSD_BUS_WIDTH_1;
+#endif
+    sdhi1.instance->p_api->open(sdhi1.instance->p_ctrl, sdhi1.instance->p_cfg);
+    host1 = sdio_host_create(&sdhi1, cache_buf2);
+    if (host1 == RT_NULL)
+    {
+        return -1;
+    }
+#endif
     return 0;
 }
 INIT_DEVICE_EXPORT(rt_hw_sdhi_init);
 
 void sdcard_change(void)
 {
-    mmcsd_change(host);
+#if (defined(SOC_SERIES_R7KA8P1) || defined(SOC_SERIES_R7FA6M4)) && defined(BSP_USING_SDHI0)
+    mmcsd_change(host0);
+#elif (defined(SOC_SERIES_R7FA6M3) || defined(SOC_SERIES_R7FA8M85)) && defined(BSP_USING_SDHI1)
+    mmcsd_change(host1);
+#endif
 }

bsp/renesas/libraries/HAL_Drivers/drivers/drv_sdhi.h

@@ -46,7 +46,11 @@
 #define SDHI_BLK_TRANSFER (1 << 13)
 #define SDHI_BLK_NOT_AUTO_STOP (1 << 14)
 
-#define SDIO_MAX_FREQ 25000000
+#if defined(SOC_SERIES_R7KA8P1)
+#define SDIO_MAX_FREQ (50 * 1000 * 1000)
+#else
+#define SDIO_MAX_FREQ (25 * 1000 * 1000)
+#endif
 
 #define HW_SDHI_ERR_CRCE (0x01U << 17)
 #define HW_SDHI_ERR_RTIMEOUT (0x01U << 22)
@@ -61,6 +65,7 @@ struct ra_sdhi
 {
     const sdmmc_instance_t *instance;
     sdmmc_device_t *media_device;
+    rt_uint8_t bus_width; /* Store bus width (1 or 4) for each SDHI instance */
 };
 
 extern void sdcard_change(void);

bsp/renesas/libraries/HAL_Drivers/drivers/drv_spi.c

@@ -30,7 +30,7 @@
 #define RA_SPI2_EVENT 0x03
 static struct rt_event complete_event = {0};
 
-#ifdef SOC_SERIES_R7FA8M85
+#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1)
 #define R_SPI_Write R_SPI_B_Write
 #define R_SPI_Read  R_SPI_B_Read
 #define R_SPI_WriteRead R_SPI_B_WriteRead
@@ -218,7 +218,7 @@ static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device,
     rt_pin_write(device->cs_pin, PIN_HIGH);
 
     /**< config bitrate */
-#ifdef SOC_SERIES_R7FA8M85
+#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1)
     R_SPI_B_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, SPI_B_CLOCK_SOURCE_PCLK, &spi_cfg.spck_div);
 #elif defined(SOC_SERIES_R9A07G0)
     R_SPI_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, SPI_CLOCK_SOURCE_PCLKM, &spi_cfg.spck_div);

bsp/renesas/libraries/HAL_Drivers/drivers/drv_usart_v2.c

@@ -211,7 +211,7 @@ static rt_err_t ra_uart_configure(struct rt_serial_device *serial, struct serial
     uart = rt_container_of(serial, struct ra_uart, serial);
     RT_ASSERT(uart != RT_NULL);
 
-#ifdef SOC_SERIES_R7FA8M85
+#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1)
     err = R_SCI_B_UART_Open(uart->config->p_api_ctrl, uart->config->p_cfg);
 #else
     err = R_SCI_UART_Open(uart->config->p_api_ctrl, uart->config->p_cfg);
@@ -237,7 +237,7 @@ static int ra_uart_putc(struct rt_serial_device *serial, char c)
     uart = rt_container_of(serial, struct ra_uart, serial);
     RT_ASSERT(uart != RT_NULL);
 
-#ifdef SOC_SERIES_R7FA8M85
+#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1)
     sci_b_uart_instance_ctrl_t *p_ctrl = (sci_b_uart_instance_ctrl_t *)uart->config->p_api_ctrl;
 #else
     sci_uart_instance_ctrl_t *p_ctrl = (sci_uart_instance_ctrl_t *)uart->config->p_api_ctrl;
@@ -245,7 +245,7 @@ static int ra_uart_putc(struct rt_serial_device *serial, char c)
 
     p_ctrl->p_reg->TDR = c;
 
-#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R9A07G0)
+#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R9A07G0) || defined(SOC_SERIES_R7KA8P1)
     while ((p_ctrl->p_reg->CSR_b.TEND) == 0);
 #else
     while ((p_ctrl->p_reg->SSR_b.TEND) == 0);