Add psoc6-cy8cproto-062S3-4343W BSP and update doc

bsp/Infineon/docs/PSOC6系列BSP制作教程.md

@@ -73,7 +73,7 @@ BSP 的制作过程分为如下四个步骤：
 
 ### 3.2 修改芯片基本配置
 
-在 **board.h** 文件中配置了 FLASH 和 RAM 的相关参数，这个文件中需要修改的是 `IFX_FLASH_START_ADRESS` 、`IFX_EFLASH_START_ADRESS` 和 `IFX_SRAM_SIZE` 这两个宏控制的参数。本次制作的 BSP 所用的 CY8CKIT-062S2-43012 芯片的 flash 大小为 2M，ram 的大小为 1M，因此对该文件作出如下的修改：
+在 **board.h** 文件中配置了 FLASH 和 RAM 的相关参数，`IFX_SRAM_SIZE` 这个宏控制的参数。本次制作的 BSP 所用的 CY8CKIT-062S2-43012 芯片 RAM 的大小为 1M，因此对该文件作出如下的修改：
 
 ![](./figures/board_h.png)
 
@@ -107,94 +107,104 @@ BSP 的制作过程分为如下四个步骤：
 
 #### 3.4.1 添加底层外设库
 
-接下来为 BSP 添加底层外设库文件，下图的文件是从 Modus 生成的文件夹中拷贝而来。
+接下来为 BSP 添加底层外设库文件，下图的文件是从 Modus 生成的文件夹中拷贝而来。**（只有移植新的系列才需要做此步骤，同 PSOC6 系列无需此步骤）**
 
 ![](./figures/hal_config2.png)
 
-Modus 生成的源库文件路径如下图，在 Modus 工作空间下的 `mtb_shared` 文件夹下：
+Modus 生成的源库文件路径如下图，在 Modus 工作空间下的 `mtb_shared` 文件夹下：**（只有移植新的系列才需要做此步骤，同 PSOC6 系列无需此步骤）**
 
 ![](./figures/hal_config3.png)
 
-将以上文件拷贝至 BSP 的 `libraries/IFX_PSOC6_HAL` 文件夹下。
+将以上文件拷贝至 BSP 的 `libraries/IFX_PSOC6_HAL` 文件夹下。**（只有移植新的系列才需要做此步骤，同 PSOC6 系列无需此步骤）**
 
 ![](./figures/hal_config1.png)
 
-同时复制 **TARGET_CY8CKIT-062S2-43012** 文件（需根据不同芯片型号拷贝不同名称的文件夹），该文件夹路径如下。
+同时下载 [TARGET_CY8CKIT-062S2-43012](https://github.com/Infineon/TARGET_CY8CKIT-062S2-43012/releases)  **V3.0.0** 发行版本（需根据不同芯片型号下载），至具体 BSP 的 libs 文件夹下。
 
 ![](./figures/hal_config4.png)
 
-拷贝至具体 BSP 的 libs 文件夹下，例如下图：
+下载至具体 BSP 的 libs 文件夹下，例如下图：
 
 ![](./figures/hal_config4-1.png)
 
-#### 3.4.1 修改外设配置脚本
+### 3.5 修改工程构建相关文件
 
-根据具体的路径添加通用外设配置（只有移植新的系列才需要做此步骤）
+接下来需要修改用于构建工程相关的文件。
 
-![](./figures/hal_config5.png)
+#### 3.5.1 修改链接脚本
 
-添加专有芯片相关文件，如下图：
+**linker_scripts** 链接文件如下图所示：
 
-![](./figures/hal_config5-1.png)
+![](./figures/linker_scripts.png)
 
-首次移植，需要使用串口外设（只有移植新的系列才需要做此步骤）:
+以 **GCC** 工具链使用的链接脚本 link.ld 为例，演示如何修改链接脚本：
 
-![](./figures/hal_config6.png)
+![](./figures/link_lds.png)
 
-添加库所使用到的头文件路径，如下图：
+**方式一（推荐）：**
 
-![](./figures/hal_config7.png)
+**FLASH** 和 **RAM** 大小信息可以参考上述拷贝的 **TARGET_CY8CKIT-062S2-43012** 文件夹下的链接脚本，进行修改，其路径在 TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM（TOOLCHAIN_GCC_ARM）/cy8c6xxa_cm4_dual.sct（.ld）：
 
-### 3.5 修改工程构建相关文件
+![](./figures/link_ifx1.png)
 
-接下来需要修改用于构建工程相关的文件。
+![](./figures/link_ifx2.png)
 
-#### 3.5.1 修改链接脚本
+**方式二：**
 
-**linker_scripts** 链接文件如下图所示：
+本次制作 BSP 使用的芯片为  `CY8CKIT-062S2-43012` ，FLASH 为 **2M**，因此修改 FLASH_SIZE 的参数为 `0x00020000`。RAM 的大小为 **1M**， 因此修改 RAM_SIZE 的参数为 `0x000FD800`。修改链接脚本时，可以参考 [**3.2.1 堆内存配置讲解**](# 3.2.1 堆内存配置讲解) 章节来确定 BSP 的内存分配。
 
-![](./figures/linker_scripts.png)
+---
 
-**linker_scripts** 链接文件是从 Modus 生成的示例工程中拷贝而来，需要修改其名称为 link.ld/.icf/.sct ，源文件路径如下：
+MDK 编译器使用的 link.sct，修改的方式也是类似的，如下图所示：
 
-ARMCC/ARMClang 使用:
+* link.sct 修改内容
 
-![](./figures/linker_scripts2.png)
+![](./figures/linkscripts_change.png)
 
-GCC 使用：
+####  3.5.2 修改构建脚本
 
-![](./figures/linker_scripts1.png)
+**SConscript** 脚本决定 **MDK/IAR/RT-Thread Studio** 工程的生成以及编译过程中要添加文件。
 
-下面以 MDK 使用的链接脚本 link.sct 为例，演示如何修改链接脚本：
+根据具体的路径添加通用外设配置**（只有移植新的系列才需要做此步骤，同 PSOC6 系列无需此步骤）**
 
-![](./figures/linkscripts_change.png)
+![](./figures/hal_config5.png)
 
-本次制作 BSP 使用的芯片为  `CY8CKIT-062S2-43012` ，FLASH 为 2M，因此修改 FLASH_SIZE 的参数为 `0x00020000`。RAM 的大小为 1M， 因此修改 RAM_SIZE 的参数为 `0x000FD800`。这样的修改方式在一般的应用下就够用了，后续如果有特殊要求，则需要按照链接脚本的语法来根据需求修改。修改链接脚本时，可以参考 [**3.2.1 堆内存配置讲解**](# 3.2.1 堆内存配置讲解) 章节来确定 BSP 的内存分配。
+添加专有芯片相关文件，如下图：
 
-其他两个链接脚本的文件为 iar 使用的 link.icf 和 gcc 编译器使用的 link.lds，修改的方式也是类似的，如下图所示：
+![](./figures/hal_config5-1.png)
 
-* link.ld 修改内容
+首次移植，需要使用串口外设**（只有移植新的系列才需要做此步骤，同 PSOC6 系列无需此步骤）**
 
-![](./figures/link_lds.png)
+![](./figures/hal_config6.png)
 
-####  3.5.2 修改构建脚本
+添加库所使用到的头文件路径，如下图：
 
-**SConscript** 脚本决定 MDK/IAR/RT-Thread Studio 工程的生成以及编译过程中要添加文件。
+![](./figures/hal_config7.png)
+
+在这一步中需要修改芯片型号以及芯片启动文件的地址，修改内容如下图所示：其中 **CPPDEFINES**  的参数要根据芯片底层库中定义的芯片型号去填写。
 
-在这一步中需要修改芯片型号以及芯片启动文件的地址，修改内容如下图所示：其中 **CPPDEFINES**  的参数要根据芯片的 low level（hal)  库中定义的芯片型号去填写。
+![](./figures/SConscript2.png)
+
+BSP 下的 lib/SConscript 中需要根据不同编译器选择不同的启动文件。
 
 ![](./figures/SConscript1.png)
 
-![](./figures/SConscript2.png)
+**注意：**
+
+需要特别注意的是，假如使用的是 GCC 工具链，那么需要对启动文件做如下修改：将原有的 **main** 改成 **entry**
+
+![](./figures/entry.png)
 
 #### 3.5.3 修改编译选项
 
-rtconfig.py 用于选择编译工具链，可以自行在 **CROSS_TOOL** 后面选择修改编译工程所需要的工具链，目前 PSCOC6 支持 gcc 和 armclang。
+rtconfig.py 用于选择编译工具链，可以自行在 **CROSS_TOOL** 后面选择修改编译工程所需要的工具链，目前 PSCOC6 支持 GCC 和 ArmClang 两种工具链。
 
 ![](./figures/rt_configpy.png)
 
 #### 3.5.4 修改工程模板
 
+MDK 为例：
+
 **template** 文件是生成 MDK/IAR 工程的模板文件，通过修改该文件可以设置工程中使用的芯片型号以及下载方式。MDK4/MDK5/IAR 的工程模板文件，如下图所示：
 
 ![](./figures/template_1.png)
@@ -209,7 +219,7 @@ rtconfig.py 用于选择编译工具链，可以自行在 **CROSS_TOOL** 后面
 
 ---
 
-以 RT-Thread Studio 为例，介绍如何导入，修改模板配置：
+**RT-Thread Studio** 为例，介绍如何导入，修改模板配置：
 
 1、打开 ENV 工具，在工程目录使用 `scons --dist` 命令将工程打包。（整个过程需要保证没有错误）
 
@@ -267,7 +277,7 @@ RT-Thread Settings 中硬件相关配置是在 board/Kconfig 中描述的。移
 
 **RT-Thread Studio：**
 
-使用上述方法/点击同步 scons 配置至项目
+使用上述方法/点击同步 scons 配置至项目。
 
 #### 3.6.2 重新生成 MDK 工程
 
@@ -287,6 +297,20 @@ RT-Thread Settings 中硬件相关配置是在 board/Kconfig 中描述的。移
 
 感谢每一位贡献代码的开发者，RT-Thread 将与你一同成长。
 
+### 3.7 RT-Thread Studio 下载配置
+
+1、点击 Studio 顶部导航栏中的配置按钮：
+
+![](./figures/studio_cfg1.png)
+
+2、确保可执行文件选择配置如下图：
+
+![](./figures/studio_cfg2.png)
+
+3、Debugger 配置项，需按照不同的芯片选择目标文件，OpenOCD 会根据此文件进行烧录：
+
+![](./figures/studio_cfg3.png)
+
 ## 4. 规范
 
 本章节介绍 RT-Thread PSOC6 系列 BSP 制作与提交时应当遵守的规范 。开发人员在 BSP 制作完成后，可以根据本规范提出的检查点对制作的 BSP 进行检查，确保 BSP 在提交前有较高的质量 。

bsp/Infineon/libraries/HAL_Drivers/drv_gpio.c

@@ -22,10 +22,14 @@
 static const struct pin_irq_map pin_irq_map[] =
 {
     {CYHAL_PORT_0,  ioss_interrupts_gpio_0_IRQn},
+#ifndef SOC_CY8C6245LQI_S3D72
     {CYHAL_PORT_1,  ioss_interrupts_gpio_1_IRQn},
+#endif
     {CYHAL_PORT_2,  ioss_interrupts_gpio_2_IRQn},
     {CYHAL_PORT_3,  ioss_interrupts_gpio_3_IRQn},
+#ifndef SOC_CY8C6245LQI_S3D72
     {CYHAL_PORT_4,  ioss_interrupts_gpio_4_IRQn},
+#endif
     {CYHAL_PORT_5,  ioss_interrupts_gpio_5_IRQn},
     {CYHAL_PORT_6,  ioss_interrupts_gpio_6_IRQn},
     {CYHAL_PORT_7,  ioss_interrupts_gpio_7_IRQn},
@@ -34,7 +38,9 @@ static const struct pin_irq_map pin_irq_map[] =
     {CYHAL_PORT_10,  ioss_interrupts_gpio_10_IRQn},
     {CYHAL_PORT_11,  ioss_interrupts_gpio_11_IRQn},
     {CYHAL_PORT_12,  ioss_interrupts_gpio_12_IRQn},
+#ifndef SOC_CY8C6245LQI_S3D72
     {CYHAL_PORT_13,  ioss_interrupts_gpio_13_IRQn},
+#endif
     {CYHAL_PORT_14,  ioss_interrupts_gpio_14_IRQn},
 };
 

bsp/Infineon/libraries/IFX_PSOC6_HAL/SConscript

@@ -42,6 +42,12 @@ if GetDepend(['SOC_CY8C624ABZI_S2D44']):
     src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_124_bga.c']
     src += Glob('psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')
 
+if GetDepend(['SOC_CY8C6245LQI_S3D72']):
+    src += ['mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/cy_device.c']
+    src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_03.c']
+    src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_03_68_qfn.c']
+    src += Glob('psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')
+
 if GetDepend(['RT_USING_SERIAL']):
     src += ['retarget-io/cy_retarget_io.c']
     src += ['mtb-hal-cat1/source/cyhal_uart.c']
@@ -125,6 +131,12 @@ if GetDepend(['SOC_CY8C624ABZI_S2D44']):
     path += [cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include']
     path += [cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include']
 
+if GetDepend(['SOC_CY8C6245LQI_S3D72']):
+    path += [cwd + '/psoc6cm0p']
+    path += [cwd + '/capsense']
+    path += [cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include']
+    path += [cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include']
+
 group = DefineGroup('Libraries', src, depend=[''], CPPPATH=path)
 
 Return('group')

bsp/Infineon/libraries/templates/PSOC62/board/board.h

@@ -27,18 +27,6 @@
     #include "cycfg_usbdev.h"
 #endif
 
-/*FLASH CONFIG*/
-#define IFX_FLASH_START_ADRESS          ((uint32_t)0x10000000)
-#define IFX_FLASH_PAGE_SIZE             (256 * 1024)
-#define IFX_FLASH_SIZE                  (2 * 1024 * 1024)
-#define IFX_FLASH_END_ADDRESS           ((uint32_t)(IFX_FLASH_START_ADRESS + IFX_FLASH_SIZE))
-
-/*EFLASH CONFIG*/
-#define IFX_EFLASH_START_ADRESS         ((uint32_t)0x14000000)
-#define IFX_EFLASH_PAGE_SIZE            (32 * 1024)
-#define IFX_EFLASH_SIZE                 (32 * 1024)
-#define IFX_EFLASH_END_ADDRESS          ((uint32_t)(IFX_EFLASH_START_ADRESS + IFX_EFLASH_SIZE))
-
 /*SRAM CONFIG*/
 #define IFX_SRAM_SIZE                   (1014)
 #define IFX_SRAM_END                    (0x08002000 + IFX_SRAM_SIZE * 1024)

bsp/Infineon/libraries/templates/PSOC62/libs/SConscript

@@ -11,8 +11,8 @@ if rtconfig.PLATFORM in ['iccarm']:
     print("\nThe current project does not support IAR build\n")
     Return('group')
 elif rtconfig.PLATFORM in ['gcc', 'armclang']:
-    src += [cwd + '/TARGET_CY8CKIT-062S2-43012/cybsp.c']
-    src += [cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c']
+    src += Glob(cwd + '/TARGET_CY8CKIT-062S2-43012/*.c')
+    src += Glob(cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/*.c')
     src += Glob(cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/*.c')
 
     CPPPATH = [ cwd + '/TARGET_CY8CKIT-062S2-43012',

bsp/Infineon/psoc6-cy8ckit-062S2-43012/.config

@@ -141,7 +141,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_NULL is not set
 # CONFIG_RT_USING_ZERO is not set
 # CONFIG_RT_USING_RANDOM is not set
-CONFIG_RT_USING_PWM=y
+# CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
@@ -729,11 +729,7 @@ CONFIG_BSP_USING_UART=y
 # CONFIG_BSP_USING_UART3 is not set
 # CONFIG_BSP_USING_UART4 is not set
 CONFIG_BSP_USING_UART5=y
-CONFIG_BSP_USING_PWM=y
-CONFIG_BSP_USING_PWM0=y
-CONFIG_BSP_USING_PWM0_CH3=y
-CONFIG_BSP_USING_PWM0_PORT13=y
-# CONFIG_BSP_USING_PWM0_CH7 is not set
+# CONFIG_BSP_USING_PWM is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_ADC is not set
 # CONFIG_BSP_USING_SDMMC is not set

bsp/Infineon/psoc6-cy8ckit-062S2-43012/.settings/.OpenOCD.Debug.rttlaunch

@@ -1,58 +0,0 @@
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-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${debugger_install_path}/${openocd-infineon_debugger_relative_path}/bin/openocd.exe"/>
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-<listEntry value="/1111"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#13;&#10;"/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>

bsp/Infineon/psoc6-cy8ckit-062S2-43012/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+toolchain.path.1287942917=${toolchain_install_path}/ARM/GNU_Tools_for_ARM_Embedded_Processors/10.2.1/bin

bsp/Infineon/psoc6-cy8ckit-062S2-43012/.settings/local_temp_storage.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+temp.toolchain.exec.path=D\:\\IDE\\RT-ThreadStudio\\repo\\Extract\\ToolChain_Support_Packages\\ARM\\GNU_Tools_for_ARM_Embedded_Processors\\10.2.1/bin

bsp/Infineon/psoc6-cy8ckit-062S2-43012/.settings/org.eclipse.core.runtime.prefs

@@ -0,0 +1,3 @@
+content-types/enabled=true
+content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
+eclipse.preferences.version=1

bsp/Infineon/psoc6-cy8ckit-062S2-43012/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/SConscript

@@ -11,8 +11,8 @@ if rtconfig.PLATFORM in ['iccarm']:
     print("\nThe current project does not support IAR build\n")
     Return('group')
 elif rtconfig.PLATFORM in ['gcc', 'armclang']:
-    src += [cwd + '/TARGET_CY8CKIT-062S2-43012/cybsp.c']
-    src += [cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c']
+    src += Glob(cwd + '/TARGET_CY8CKIT-062S2-43012/*.c')
+    src += Glob(cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/*.c')
     src += Glob(cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/*.c')
 
     CPPPATH = [ cwd + '/TARGET_CY8CKIT-062S2-43012',

bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvoptx

@@ -73,7 +73,7 @@
         <LExpSel>0</LExpSel>
       </OPTXL>
       <OPTFL>
-        <tvExp>0</tvExp>
+        <tvExp>1</tvExp>
         <tvExpOptDlg>0</tvExpOptDlg>
         <IsCurrentTarget>1</IsCurrentTarget>
       </OPTFL>
@@ -502,18 +502,6 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\..\components\drivers\misc\rt_drv_pwm.c</PathWithFileName>
-      <FilenameWithoutPath>rt_drv_pwm.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>5</GroupNumber>
-      <FileNumber>25</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
       <PathWithFileName>..\..\..\components\drivers\serial\serial.c</PathWithFileName>
       <FilenameWithoutPath>serial.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
@@ -529,7 +517,7 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>26</FileNumber>
+      <FileNumber>25</FileNumber>
       <FileType>2</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -541,7 +529,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>27</FileNumber>
+      <FileNumber>26</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -553,7 +541,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>28</FileNumber>
+      <FileNumber>27</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -565,7 +553,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>29</FileNumber>
+      <FileNumber>28</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -577,19 +565,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>30</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\HAL_Drivers\drv_pwm.c</PathWithFileName>
-      <FilenameWithoutPath>drv_pwm.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>6</GroupNumber>
-      <FileNumber>31</FileNumber>
+      <FileNumber>29</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -609,7 +585,7 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>7</GroupNumber>
-      <FileNumber>32</FileNumber>
+      <FileNumber>30</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -621,7 +597,7 @@
     </File>
     <File>
       <GroupNumber>7</GroupNumber>
-      <FileNumber>33</FileNumber>
+      <FileNumber>31</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -633,7 +609,7 @@
     </File>
     <File>
       <GroupNumber>7</GroupNumber>
-      <FileNumber>34</FileNumber>
+      <FileNumber>32</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -645,7 +621,7 @@
     </File>
     <File>
       <GroupNumber>7</GroupNumber>
-      <FileNumber>35</FileNumber>
+      <FileNumber>33</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -665,7 +641,7 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>36</FileNumber>
+      <FileNumber>34</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -677,7 +653,7 @@
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>37</FileNumber>
+      <FileNumber>35</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -689,7 +665,7 @@
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>38</FileNumber>
+      <FileNumber>36</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -701,7 +677,7 @@
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>39</FileNumber>
+      <FileNumber>37</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -713,7 +689,7 @@
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>40</FileNumber>
+      <FileNumber>38</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -725,7 +701,7 @@
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>41</FileNumber>
+      <FileNumber>39</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -737,7 +713,7 @@
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>42</FileNumber>
+      <FileNumber>40</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -749,7 +725,7 @@
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>43</FileNumber>
+      <FileNumber>41</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -761,7 +737,7 @@
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>44</FileNumber>
+      <FileNumber>42</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -773,7 +749,7 @@
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>45</FileNumber>
+      <FileNumber>43</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -785,7 +761,7 @@
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>46</FileNumber>
+      <FileNumber>44</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -797,7 +773,7 @@
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>47</FileNumber>
+      <FileNumber>45</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -809,7 +785,7 @@
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>48</FileNumber>
+      <FileNumber>46</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -829,7 +805,7 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>49</FileNumber>
+      <FileNumber>47</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -841,7 +817,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>50</FileNumber>
+      <FileNumber>48</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -853,7 +829,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>51</FileNumber>
+      <FileNumber>49</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -865,7 +841,19 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>52</FileNumber>
+      <FileNumber>50</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c</PathWithFileName>
+      <FilenameWithoutPath>psoc6_04_cm0p_sleep.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>9</GroupNumber>
+      <FileNumber>51</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -877,7 +865,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>53</FileNumber>
+      <FileNumber>52</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -889,7 +877,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>54</FileNumber>
+      <FileNumber>53</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -901,7 +889,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>55</FileNumber>
+      <FileNumber>54</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -913,7 +901,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>56</FileNumber>
+      <FileNumber>55</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -925,7 +913,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>57</FileNumber>
+      <FileNumber>56</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -937,7 +925,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>58</FileNumber>
+      <FileNumber>57</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -949,7 +937,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>59</FileNumber>
+      <FileNumber>58</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -961,7 +949,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>60</FileNumber>
+      <FileNumber>59</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -973,7 +961,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>61</FileNumber>
+      <FileNumber>60</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -985,7 +973,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>62</FileNumber>
+      <FileNumber>61</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -997,19 +985,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>63</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c</PathWithFileName>
-      <FilenameWithoutPath>psoc6_01_cm0p_sleep.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>9</GroupNumber>
-      <FileNumber>64</FileNumber>
+      <FileNumber>62</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1021,19 +997,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>65</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c</PathWithFileName>
-      <FilenameWithoutPath>psoc6_03_cm0p_sleep.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>9</GroupNumber>
-      <FileNumber>66</FileNumber>
+      <FileNumber>63</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1045,31 +1009,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>67</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_tcpwm_counter.c</PathWithFileName>
-      <FilenameWithoutPath>cy_tcpwm_counter.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>9</GroupNumber>
-      <FileNumber>68</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_pwm.c</PathWithFileName>
-      <FilenameWithoutPath>cyhal_pwm.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>9</GroupNumber>
-      <FileNumber>69</FileNumber>
+      <FileNumber>64</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1081,7 +1021,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>70</FileNumber>
+      <FileNumber>65</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1093,7 +1033,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>71</FileNumber>
+      <FileNumber>66</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1105,31 +1045,31 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>72</FileNumber>
+      <FileNumber>67</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c</PathWithFileName>
-      <FilenameWithoutPath>psoc6_02_cm0p_sleep.c</FilenameWithoutPath>
+      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c</PathWithFileName>
+      <FilenameWithoutPath>psoc6_01_cm0p_sleep.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>73</FileNumber>
+      <FileNumber>68</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syspm.c</PathWithFileName>
-      <FilenameWithoutPath>cy_syspm.c</FilenameWithoutPath>
+      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_pipe.c</PathWithFileName>
+      <FilenameWithoutPath>cy_ipc_pipe.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>74</FileNumber>
+      <FileNumber>69</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1141,19 +1081,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>75</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_tcpwm_pwm.c</PathWithFileName>
-      <FilenameWithoutPath>cy_tcpwm_pwm.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>9</GroupNumber>
-      <FileNumber>76</FileNumber>
+      <FileNumber>70</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1165,7 +1093,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>77</FileNumber>
+      <FileNumber>71</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1177,7 +1105,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>78</FileNumber>
+      <FileNumber>72</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1189,19 +1117,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>79</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c</PathWithFileName>
-      <FilenameWithoutPath>psoc6_04_cm0p_sleep.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
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-    <File>
-      <GroupNumber>9</GroupNumber>
-      <FileNumber>80</FileNumber>
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       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1213,7 +1129,7 @@
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@@ -1225,19 +1141,19 @@
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     <File>
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       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_timer.c</PathWithFileName>
-      <FilenameWithoutPath>cyhal_timer.c</FilenameWithoutPath>
+      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c</PathWithFileName>
+      <FilenameWithoutPath>psoc6_03_cm0p_sleep.c</FilenameWithoutPath>
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       <bShared>0</bShared>
     </File>
     <File>
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       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1249,7 +1165,7 @@
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     <File>
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       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1261,7 +1177,7 @@
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     <File>
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-      <FileNumber>85</FileNumber>
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       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1273,7 +1189,7 @@
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     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>86</FileNumber>
+      <FileNumber>79</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1285,25 +1201,25 @@
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     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>87</FileNumber>
+      <FileNumber>80</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_pipe.c</PathWithFileName>
-      <FilenameWithoutPath>cy_ipc_pipe.c</FilenameWithoutPath>
+      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syspm.c</PathWithFileName>
+      <FilenameWithoutPath>cy_syspm.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>88</FileNumber>
+      <FileNumber>81</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_tcpwm_common.c</PathWithFileName>
-      <FilenameWithoutPath>cyhal_tcpwm_common.c</FilenameWithoutPath>
+      <PathWithFileName>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c</PathWithFileName>
+      <FilenameWithoutPath>psoc6_02_cm0p_sleep.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -1317,157 +1233,157 @@
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     <File>
       <GroupNumber>10</GroupNumber>
-      <FileNumber>89</FileNumber>
+      <FileNumber>82</FileNumber>
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       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_dmas.c</PathWithFileName>
-      <FilenameWithoutPath>cycfg_dmas.c</FilenameWithoutPath>
+      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_peripherals.c</PathWithFileName>
+      <FilenameWithoutPath>cycfg_peripherals.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>10</GroupNumber>
-      <FileNumber>90</FileNumber>
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       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_routing.c</PathWithFileName>
-      <FilenameWithoutPath>cycfg_routing.c</FilenameWithoutPath>
+      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_clocks.c</PathWithFileName>
+      <FilenameWithoutPath>cycfg_clocks.c</FilenameWithoutPath>
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       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>10</GroupNumber>
-      <FileNumber>91</FileNumber>
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       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\cybsp.c</PathWithFileName>
-      <FilenameWithoutPath>cybsp.c</FilenameWithoutPath>
+      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\system_psoc6_cm4.c</PathWithFileName>
+      <FilenameWithoutPath>system_psoc6_cm4.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>10</GroupNumber>
-      <FileNumber>92</FileNumber>
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       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_qspi_memslot.c</PathWithFileName>
-      <FilenameWithoutPath>cycfg_qspi_memslot.c</FilenameWithoutPath>
+      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_routing.c</PathWithFileName>
+      <FilenameWithoutPath>cycfg_routing.c</FilenameWithoutPath>
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       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>10</GroupNumber>
-      <FileNumber>93</FileNumber>
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       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_pins.c</PathWithFileName>
-      <FilenameWithoutPath>cycfg_pins.c</FilenameWithoutPath>
+      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg.c</PathWithFileName>
+      <FilenameWithoutPath>cycfg.c</FilenameWithoutPath>
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     </File>
     <File>
       <GroupNumber>10</GroupNumber>
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       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_clocks.c</PathWithFileName>
-      <FilenameWithoutPath>cycfg_clocks.c</FilenameWithoutPath>
+      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_capsense.c</PathWithFileName>
+      <FilenameWithoutPath>cycfg_capsense.c</FilenameWithoutPath>
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       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>10</GroupNumber>
-      <FileNumber>95</FileNumber>
-      <FileType>2</FileType>
+      <FileNumber>88</FileNumber>
+      <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S</PathWithFileName>
-      <FilenameWithoutPath>startup_psoc6_02_cm4.S</FilenameWithoutPath>
+      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_connectivity_bt.c</PathWithFileName>
+      <FilenameWithoutPath>cycfg_connectivity_bt.c</FilenameWithoutPath>
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       <bShared>0</bShared>
     </File>
     <File>
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       <bDave2>0</bDave2>
-      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_connectivity_bt.c</PathWithFileName>
-      <FilenameWithoutPath>cycfg_connectivity_bt.c</FilenameWithoutPath>
+      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_dmas.c</PathWithFileName>
+      <FilenameWithoutPath>cycfg_dmas.c</FilenameWithoutPath>
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       <bShared>0</bShared>
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     <File>
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-      <FilenameWithoutPath>cycfg_system.c</FilenameWithoutPath>
+      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_pins.c</PathWithFileName>
+      <FilenameWithoutPath>cycfg_pins.c</FilenameWithoutPath>
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       <bShared>0</bShared>
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       <bDave2>0</bDave2>
-      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\system_psoc6_cm4.c</PathWithFileName>
-      <FilenameWithoutPath>system_psoc6_cm4.c</FilenameWithoutPath>
+      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_system.c</PathWithFileName>
+      <FilenameWithoutPath>cycfg_system.c</FilenameWithoutPath>
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-      <FilenameWithoutPath>cycfg.c</FilenameWithoutPath>
+      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\cybsp.c</PathWithFileName>
+      <FilenameWithoutPath>cybsp.c</FilenameWithoutPath>
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-      <FilenameWithoutPath>cycfg_peripherals.c</FilenameWithoutPath>
+      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_qspi_memslot.c</PathWithFileName>
+      <FilenameWithoutPath>cycfg_qspi_memslot.c</FilenameWithoutPath>
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       <bShared>0</bShared>
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       <GroupNumber>10</GroupNumber>
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-      <FilenameWithoutPath>cycfg_capsense.c</FilenameWithoutPath>
+      <PathWithFileName>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S</PathWithFileName>
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bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvprojx

@@ -11,6 +11,7 @@
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
       <pArmCC>6160000::V6.16::ARMCLANG</pArmCC>
+      <pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
       <uAC6>1</uAC6>
       <TargetOption>
         <TargetCommonOption>
@@ -337,9 +338,9 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls></MiscControls>
-              <Define>CY_USING_HAL, __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, COMPONENT_CAT1A, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, COMPONENT_BSP_DESIGN_MODUS, IFX_PSOC6_43012, __RTTHREAD__, COMPONENT_CAT1, CY8C624ABZI_S2D44</Define>
+              <Define>COMPONENT_CAT1A, RT_USING_LIBC, RT_USING_ARMLIBC, CY_USING_HAL, __CLK_TCK=RT_TICK_PER_SECOND, COMPONENT_BSP_DESIGN_MODUS, __STDC_LIMIT_MACROS, __RTTHREAD__, COMPONENT_CAT1, CY8C624ABZI_S2D44</Define>
               <Undefine></Undefine>
-              <IncludePath>..\..\..\components\finsh;board\ports;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\psoc6cm0p;..\..\..\components\utilities\libadt;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers;libs\TARGET_CY8CKIT-062S2-43012;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\include;..\..\..\include;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include_pvt;..\..\..\components\libc\posix\io\poll;..\libraries\IFX_PSOC6_HAL\core-lib\include;libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource;..\libraries\IFX_PSOC6_HAL\capsense;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include;..\..\..\libcpu\arm\common;board;..\libraries\IFX_PSOC6_HAL\retarget-io;..\..\..\components\libc\posix\io\stdio;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\libraries\IFX_PSOC6_HAL\mtb_shared\serial-flash;..\libraries\HAL_Drivers\config;..\libraries\IFX_PSOC6_HAL\mtb_shared\usbdev;.;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\include;..\libraries\IFX_PSOC6_HAL\mtb_shared\csdidac;applications;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\include;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\cmsis\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\include</IncludePath>
+              <IncludePath>..\..\..\components\finsh;board\ports;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\psoc6cm0p;..\..\..\components\utilities\libadt;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers;libs\TARGET_CY8CKIT-062S2-43012;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\include;..\..\..\include;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include_pvt;..\..\..\components\libc\posix\io\poll;..\libraries\IFX_PSOC6_HAL\core-lib\include;libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource;..\libraries\IFX_PSOC6_HAL\mtb_shared\usbdev;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include;..\..\..\libcpu\arm\common;board;..\libraries\IFX_PSOC6_HAL\retarget-io;..\..\..\components\libc\posix\io\stdio;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\libraries\IFX_PSOC6_HAL\mtb_shared\serial-flash;..\libraries\HAL_Drivers\config;..\libraries\IFX_PSOC6_HAL\capsense;.;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\include;..\libraries\IFX_PSOC6_HAL\mtb_shared\csdidac;applications;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\include;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\cmsis\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\include</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -518,11 +519,6 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
             </File>
-            <File>
-              <FileName>rt_drv_pwm.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\misc\rt_drv_pwm.c</FilePath>
-            </File>
             <File>
               <FileName>serial.c</FileName>
               <FileType>1</FileType>
@@ -553,11 +549,6 @@
               <FileType>1</FileType>
               <FilePath>..\libraries\HAL_Drivers\drv_gpio.c</FilePath>
             </File>
-            <File>
-              <FileName>drv_pwm.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\HAL_Drivers\drv_pwm.c</FilePath>
-            </File>
             <File>
               <FileName>drv_uart.c</FileName>
               <FileType>1</FileType>
@@ -678,6 +669,11 @@
               <FileType>1</FileType>
               <FilePath>..\libraries\IFX_PSOC6_HAL\retarget-io\cy_retarget_io.c</FilePath>
             </File>
+            <File>
+              <FileName>psoc6_04_cm0p_sleep.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c</FilePath>
+            </File>
             <File>
               <FileName>cy_scb_i2c.c</FileName>
               <FileType>1</FileType>
@@ -733,36 +729,16 @@
               <FileType>1</FileType>
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_sema.c</FilePath>
             </File>
-            <File>
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-              <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c</FilePath>
-            </File>
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               <FileType>1</FileType>
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils_psoc.c</FilePath>
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-            <File>
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-              <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c</FilePath>
-            </File>
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               <FileType>1</FileType>
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils.c</FilePath>
             </File>
-            <File>
-              <FileName>cy_tcpwm_counter.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_tcpwm_counter.c</FilePath>
-            </File>
-            <File>
-              <FileName>cyhal_pwm.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_pwm.c</FilePath>
-            </File>
             <File>
               <FileName>cy_ipc_drv.c</FileName>
               <FileType>1</FileType>
@@ -779,25 +755,20 @@
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syslib.c</FilePath>
             </File>
             <File>
-              <FileName>psoc6_02_cm0p_sleep.c</FileName>
+              <FileName>psoc6_01_cm0p_sleep.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c</FilePath>
+              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c</FilePath>
             </File>
             <File>
-              <FileName>cy_syspm.c</FileName>
+              <FileName>cy_ipc_pipe.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syspm.c</FilePath>
+              <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_pipe.c</FilePath>
             </File>
             <File>
               <FileName>cyhal_lptimer.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_lptimer.c</FilePath>
             </File>
-            <File>
-              <FileName>cy_tcpwm_pwm.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_tcpwm_pwm.c</FilePath>
-            </File>
             <File>
               <FileName>cyhal_irq_psoc.c</FileName>
               <FileType>1</FileType>
@@ -813,11 +784,6 @@
               <FileType>1</FileType>
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysclk.c</FilePath>
             </File>
-            <File>
-              <FileName>psoc6_04_cm0p_sleep.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c</FilePath>
-            </File>
             <File>
               <FileName>cyhal_syspm.c</FileName>
               <FileType>1</FileType>
@@ -829,9 +795,9 @@
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_uart.c</FilePath>
             </File>
             <File>
-              <FileName>cyhal_timer.c</FileName>
+              <FileName>psoc6_03_cm0p_sleep.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_timer.c</FilePath>
+              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c</FilePath>
             </File>
             <File>
               <FileName>cy_systick.c</FileName>
@@ -854,14 +820,14 @@
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\source\cy_device.c</FilePath>
             </File>
             <File>
-              <FileName>cy_ipc_pipe.c</FileName>
+              <FileName>cy_syspm.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_pipe.c</FilePath>
+              <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syspm.c</FilePath>
             </File>
             <File>
-              <FileName>cyhal_tcpwm_common.c</FileName>
+              <FileName>psoc6_02_cm0p_sleep.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_tcpwm_common.c</FilePath>
+              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c</FilePath>
             </File>
           </Files>
         </Group>
@@ -869,39 +835,34 @@
           <GroupName>libs</GroupName>
           <Files>
             <File>
-              <FileName>cycfg_dmas.c</FileName>
+              <FileName>cycfg_peripherals.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_dmas.c</FilePath>
+              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_peripherals.c</FilePath>
             </File>
             <File>
-              <FileName>cycfg_routing.c</FileName>
+              <FileName>cycfg_clocks.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_routing.c</FilePath>
+              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_clocks.c</FilePath>
             </File>
             <File>
-              <FileName>cybsp.c</FileName>
+              <FileName>system_psoc6_cm4.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\cybsp.c</FilePath>
+              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\system_psoc6_cm4.c</FilePath>
             </File>
             <File>
-              <FileName>cycfg_qspi_memslot.c</FileName>
+              <FileName>cycfg_routing.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_qspi_memslot.c</FilePath>
+              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_routing.c</FilePath>
             </File>
             <File>
-              <FileName>cycfg_pins.c</FileName>
+              <FileName>cycfg.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_pins.c</FilePath>
+              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg.c</FilePath>
             </File>
             <File>
-              <FileName>cycfg_clocks.c</FileName>
+              <FileName>cycfg_capsense.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_clocks.c</FilePath>
-            </File>
-            <File>
-              <FileName>startup_psoc6_02_cm4.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S</FilePath>
+              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_capsense.c</FilePath>
             </File>
             <File>
               <FileName>cycfg_connectivity_bt.c</FileName>
@@ -909,29 +870,34 @@
               <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_connectivity_bt.c</FilePath>
             </File>
             <File>
-              <FileName>cycfg_system.c</FileName>
+              <FileName>cycfg_dmas.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_system.c</FilePath>
+              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_dmas.c</FilePath>
             </File>
             <File>
-              <FileName>system_psoc6_cm4.c</FileName>
+              <FileName>cycfg_pins.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\system_psoc6_cm4.c</FilePath>
+              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_pins.c</FilePath>
             </File>
             <File>
-              <FileName>cycfg.c</FileName>
+              <FileName>cycfg_system.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg.c</FilePath>
+              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_system.c</FilePath>
             </File>
             <File>
-              <FileName>cycfg_peripherals.c</FileName>
+              <FileName>cybsp.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_peripherals.c</FilePath>
+              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\cybsp.c</FilePath>
             </File>
             <File>
-              <FileName>cycfg_capsense.c</FileName>
+              <FileName>cycfg_qspi_memslot.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_capsense.c</FilePath>
+              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_qspi_memslot.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_psoc6_02_cm4.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S</FilePath>
             </File>
           </Files>
         </Group>

bsp/Infineon/psoc6-cy8ckit-062S2-43012/rtconfig_preinc.h

@@ -0,0 +1,18 @@
+
+#ifndef RTCONFIG_PREINC_H__
+#define RTCONFIG_PREINC_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread pre-include file */
+
+#define COMPONENT_BSP_DESIGN_MODUS
+#define COMPONENT_CAT1
+#define COMPONENT_CAT1A
+#define CY8C624ABZI_S2D44
+#define CY_USING_HAL
+#define RT_USING_LIBC
+#define RT_USING_NEWLIBC
+#define _POSIX_C_SOURCE 1
+#define __RTTHREAD__
+
+#endif /*RTCONFIG_PREINC_H__*/

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/.config

@@ -0,0 +1,750 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMART is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart5"
+CONFIG_RT_VER_NUM=0x50000
+# CONFIG_RT_USING_CACHE is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M4=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Sensor libraries
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+
+#
+# Display libraries
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+
+#
+# Timing libraries
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Project libraries
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+CONFIG_SOC_FAMILY_IFX=y
+CONFIG_SOC_SERIES_IFX_PSOC62=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_CY8C6245LQI_S3D72=y
+
+#
+# Onboard Peripheral Drivers
+#
+CONFIG_BSP_USING_USB_TO_USART=y
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+# CONFIG_BSP_USING_UART0 is not set
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+# CONFIG_BSP_USING_UART4 is not set
+CONFIG_BSP_USING_UART5=y
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_SDMMC is not set
+# CONFIG_BSP_USING_QSPI_FLASH is not set
+# CONFIG_BSP_USING_HW_I2C is not set
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_USBD is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_DAC is not set
+# CONFIG_BSP_USING_TIM is not set
+
+#
+# Board extended module Drivers
+#
+# CONFIG_BSP_USING_SLIDER is not set
+# CONFIG_BSP_USING_RW007 is not set

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/.gitignore

@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/.project

@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+  <name>project</name>
+  <comment />
+  <projects>
+	</projects>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>com.cypress.studio.app.cymodusnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <linkedResources />
+</projectDescription>

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/.settings/language.settings.xml

@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1522148012290462689" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/.settings/projcfg.ini

@@ -0,0 +1,20 @@
+#RT-Thread Studio Project Configuration
+#Thu Jan 12 11:11:44 CST 2023
+project_type=rt-thread
+chip_name=CY8C624ABZI
+os_branch=full
+example_name=
+os_version=latest
+selected_rtt_version=latest
+cfg_version=v3.0
+board_base_nano_proj=False
+is_use_scons_build=True
+output_project_path=E\:/software/RT-ThreadStudio/workspace
+project_base_bsp=true
+hardware_adapter=KitProg3
+project_name=1111
+is_base_example_project=False
+board_name=psoc6-cy8ckit-062S2-43012
+device_vendor=Infineon 
+bsp_version=1.0.0
+bsp_path=repo/Extract/Board_Support_Packages/Infineon/PSOC62-IFX-PROTO-KIT/1.0.0

bsp/Infineon/libraries/templates/PSOC62/.settings/.OpenOCD.Debug.rttlaunch → bsp/Infineon/psoc6-cy8cproto-062S3-4343W/.settings/project.OpenOCD.Debug.rttlaunch

@@ -12,7 +12,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set remotetimeout 15"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${debugger_install_path}/${openocd-infineon_debugger_relative_path}/bin/openocd.exe"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${debugger_install_path}/${openocd_debugger_relative_path}openocd/bin/openocd.exe"/>
 <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s ../scripts -f interface/kitprog3.cfg -f target/psoc6_2m.cfg -c &quot;psoc6.cpu.cm4 configure -rtos auto -rtos-wipe-on-reset-halt 1&quot; -c &quot;gdb_port 3332&quot; -c &quot;psoc6 sflash_restrictions 1&quot; -c &quot;init; reset init&quot;"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
@@ -21,7 +21,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value="mon psoc6 reset_halt sysresetreq&#13;&#10;flushregs&#13;&#10;mon gdb_sync&#13;&#10;stepi"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="run"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="${workspace_loc:\dist_ide_project\Debug\rtthread.elf}"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="${workspace_loc:\dist_ide_project\Debug\rtthread.hex}"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
@@ -34,20 +34,20 @@
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="${workspace_loc:\dist_ide_project\Debug\rtthread.elf}"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="false"/>
 <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${rtt_gnu_gcc}/arm-none-eabi-gdb.exe"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="E:\software\RT-ThreadStudio\repo\Extract\ToolChain_Support_Packages\ARM\GNU_Tools_for_ARM_Embedded_Processors\10.2.1\bin\arm-none-eabi-gdb.exe"/>
 <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
 <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
 <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="1111"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="dist_ide_project"/>
 <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
 <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
 <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/1111"/>
+<listEntry value="/dist_ide_project"/>
 </listAttribute>
 <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
 <listEntry value="4"/>

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/.settings/project.rttlaunch

@@ -0,0 +1,65 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.pyocd.launchConfigurationType">
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.adapterName" value="DAP-LINK"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.binFlashStartAddress" value=""/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doDebugInRam" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.enableSemihosting" value="true"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbClientOtherOptions" value=""/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerBusSpeed" value="12000000"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerConnectionAddress" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerDeviceName" value="cy8c64xA_cm4"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerEnableSemihosting" value="false"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerExecutable" value="E:\software\RT-ThreadStudio\repo\Extract\Debugger_Support_Packages\openocd\bin\openocd.exe"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerFlashMode" value="0"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerOther" value=""/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.programMode" value="HEX"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU PyOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${rtt_gnu_gcc}/arm-none-eabi-gdb.exe"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="dist_ide_project"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/dist_ide_project"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
+<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;sourceLookupDirector&gt;&#13;&#10;&lt;sourceContainers duplicates=&quot;false&quot;&gt;&#13;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#13;&amp;#10;&amp;lt;default/&amp;gt;&amp;#13;&amp;#10;&quot; typeId=&quot;org.eclipse.debug.core.containerType.default&quot;/&gt;&#13;&#10;&lt;/sourceContainers&gt;&#13;&#10;&lt;/sourceLookupDirector&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/Kconfig

@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/LICENSE

@@ -0,0 +1,210 @@
+CYPRESS END USER LICENSE AGREEMENT
+
+PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE
+DOWNLOADING, INSTALLING, COPYING, OR USING THIS SOFTWARE AND ACCOMPANYING
+DOCUMENTATION.  BY DOWNLOADING, INSTALLING, COPYING OR USING THE SOFTWARE,
+YOU ARE AGREEING TO BE BOUND BY THIS AGREEMENT.  IF YOU DO NOT AGREE TO ALL
+OF THE TERMS OF THIS AGREEMENT, PROMPTLY RETURN AND DO NOT USE THE SOFTWARE.
+IF YOU HAVE PURCHASED THIS LICENSE TO THE SOFTWARE, YOUR RIGHT TO RETURN THE
+SOFTWARE EXPIRES 30 DAYS AFTER YOUR PURCHASE AND APPLIES ONLY TO THE ORIGINAL
+PURCHASER.
+
+1. Definitions.
+
+    "Software" means this software and any accompanying documentation,
+      including any upgrades, updates, bug fixes or modified versions provided
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+LIABILITY TO YOU, WHETHER IN CONTRACT, TORT (INCLUDING NEGLIGENCE), OR
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+SOFTWARE.  THE FOREGOING LIMITATIONS SHALL APPLY EVEN IF THE ABOVE-STATED
+WARRANTY FAILS OF ITS ESSENTIAL PURPOSE.  BECAUSE SOME STATES OR JURISDICTIONS
+DO NOT ALLOW LIMITATION OR EXCLUSION OF CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ALL OR PORTIONS OF THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+
+10. Restricted Rights.  The Software is commercial computer software as that
+term is described in 48 C.F.R. 252.227-7014(a)(1).  If the Software is being
+acquired by or on behalf of the U.S. Government or by a U.S. Government prime
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+11. Personal Information.  You agree that information you provide through your
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+party's successors and assigns, provided that you may not assign or transfer
+this Agreement, in whole or in part, without Cypress' written consent.  This
+Agreement shall be governed by and construed in accordance with the laws of
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+law.  The parties consent to personal and exclusive jurisdiction of and venue
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+(both written and oral) regarding such subject matter.  Any notice to Cypress
+will be deemed effective when actually received and must be sent to Cypress
+Semiconductor Corporation, ATTN: Chief Legal Officer, 198 Champion Court, San
+Jose, CA 95134 USA.

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/SConscript

@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/SConstruct

@@ -0,0 +1,60 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+IFX_library = 'IFX_PSOC6_HAL'
+rtconfig.BSP_LIBRARY_TYPE = IFX_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, IFX_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/applications/SConscript

@@ -0,0 +1,16 @@
+import rtconfig
+from building import *
+import os
+
+cwd  = GetCurrentDir()
+path = [cwd]
+src  = Glob('*.c')
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = path)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/applications/main.c

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-01-16     Rbb666       first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "drv_gpio.h"
+
+#define LED_PIN     GET_PIN(11, 1)
+
+int main(void)
+{
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    for (;;)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/Kconfig

@@ -0,0 +1,323 @@
+menu "Hardware Drivers Config"
+
+config SOC_CY8C6245LQI_S3D72
+    bool
+    select SOC_SERIES_IFX_PSOC62
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "Onboard Peripheral Drivers"
+
+    config BSP_USING_USB_TO_USART
+        bool "Enable USB TO USART (uart5)"
+        select BSP_USING_UART
+        select BSP_USING_UART5
+        default y
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "Enable UART0"
+                default n
+            config BSP_USING_UART1
+                bool "Enable UART1"
+                default n
+            config BSP_USING_UART2
+                bool "Enable UART2"
+                default n
+            config BSP_USING_UART3
+                bool "Enable UART3"
+                default n
+            config BSP_USING_UART4
+                bool "Enable UART4"
+                default n
+            config BSP_USING_UART5
+                bool "Enable UART5"
+                default y
+        endif
+
+    menuconfig BSP_USING_PWM
+        bool "Enable PWM"
+        default n
+        select RT_USING_PWM
+        if BSP_USING_PWM
+        menuconfig BSP_USING_PWM0
+            bool "Enable timer0 output pwm"
+            default n
+            if BSP_USING_PWM0
+                menuconfig BSP_USING_PWM0_CH3
+                    bool "Enable PWM0 channel3"
+                    default n
+                    if BSP_USING_PWM0_CH3
+                        config BSP_USING_PWM0_PORT13
+                        bool "Enable PWM0-PORT13 output pwm"
+                        default n
+                    endif
+                menuconfig BSP_USING_PWM0_CH7
+                    bool "Enable PWM0 channel7"
+                    default n
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT2
+                        bool "Enable PWM0-PORT2 output pwm"
+                        default n
+                    endif
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT5
+                        bool "Enable PWM0-PORT5 output pwm"
+                        default n
+                    endif
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT7
+                        bool "Enable PWM0-PORT7 output pwm"
+                        default n
+                    endif
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT9
+                        bool "Enable PWM0-PORT9 output pwm"
+                        default n
+                    endif
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT10
+                        bool "Enable PWM0-PORT10 output pwm"
+                        default n
+                    endif
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT12
+                        bool "Enable PWM0-PORT12 output pwm"
+                        default n
+                    endif
+            endif
+        endif
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI BUS"
+        select RT_USING_SPI
+        default n
+        if BSP_USING_SPI
+            menuconfig BSP_USING_SPI3
+                bool "Enable SPI3 BUS"
+                default n
+                if BSP_USING_SPI3
+                    config BSP_USING_SPI3_SAMPLE
+                        bool "Enable SPI3 BUS Sample"
+                        default n
+                endif
+        endif
+
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC
+        if BSP_USING_ADC
+            config BSP_USING_ADC1
+                bool "Enable ADC1"
+                default n
+        endif
+
+    config BSP_USING_SDMMC
+        bool "Enable SDMMC (sd card)"
+        default n
+        select RT_USING_SDIO
+        select RT_USING_DFS
+        select RT_USING_DFS_ELMFAT
+        if BSP_USING_SDMMC
+            config BSP_USING_SDIO1
+                bool "Enable SDIO1 (sd card)"
+                default n
+        endif
+
+    config BSP_USING_QSPI_FLASH
+        bool "Enable QSPI BUS"
+        select RT_USING_QSPI
+        select RT_USING_SFUD
+        select RT_SFUD_USING_QSPI
+        default n
+
+    menuconfig BSP_USING_HW_I2C
+        bool "Enable Hardware I2C Bus"
+        default n
+        select RT_USING_I2C
+        select RT_USING_PIN
+        if BSP_USING_HW_I2C
+            config BSP_USING_HW_I2C3
+                bool "Enable I2C3 Bus (User I2C)"
+                default n
+                if BSP_USING_HW_I2C3
+                    comment "Notice: P6_0 --> 48; P6_1 --> 49"
+                    config BSP_I2C3_SCL_PIN
+                        int "i2c3 SCL pin number"
+                        range 1 113
+                        default 48
+                    config BSP_I2C3_SDA_PIN
+                        int "i2c3 SDA pin number"
+                        range 1 113
+                        default 49
+                endif
+            config BSP_USING_HW_I2C6
+                bool "Enable I2C6 Bus (User I2C)"
+                default n
+                if BSP_USING_HW_I2C6
+                    comment "Notice: P13_0 --> 48; P13_1 --> 49"
+                    config BSP_I2C6_SCL_PIN
+                        int "i2c6 SCL pin number"
+                        range 1 113
+                        default 104
+                    config BSP_I2C6_SDA_PIN
+                        int "i2c6 SDA pin number"
+                        range 1 113
+                        default 105
+                endif
+        endif
+
+    menuconfig BSP_USING_I2C
+        bool "Enable Software I2C Bus"
+        default n
+        select RT_USING_I2C
+        select RT_USING_I2C_BITOPS
+        select RT_USING_PIN
+        if BSP_USING_I2C
+            config BSP_USING_I2C1
+                bool "Enable I2C1 Bus (User I2C)"
+                default n
+                if BSP_USING_I2C1
+                    comment "Notice: P13_1 --> 105; P13_2 --> 106"
+                    config BSP_I2C1_SCL_PIN
+                        int "i2c1 SCL pin number"
+                        range 1 113
+                        default 105
+                    config BSP_I2C1_SDA_PIN
+                        int "i2c1 SDA pin number"
+                        range 1 113
+                        default 106
+                endif
+        endif
+
+    config BSP_USING_USBD
+        bool "Enable USB Device"
+        select RT_USING_USB_DEVICE
+        default n
+
+    menuconfig BSP_USING_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default n
+        if BSP_USING_RTC
+            choice
+                prompt "Select clock source"
+                default BSP_RTC_USING_LSE
+
+                config BSP_RTC_USING_LSE
+                    bool "RTC USING LSE"
+
+                config BSP_RTC_USING_LSI
+                    bool "RTC USING LSI"
+            endchoice
+        endif
+
+    config BSP_USING_ON_CHIP_FLASH
+        bool "Enable on-chip FLASH"
+        default n
+
+    config BSP_USING_WDT
+        bool "Enable Watchdog Timer"
+        select RT_USING_WDT
+        default n
+
+    menuconfig BSP_USING_DAC
+        bool "Enable DAC"
+        default n
+        select RT_USING_DAC
+        if BSP_USING_DAC
+            config BSP_USING_DAC1
+                bool "Enable DAC1"
+                default n
+            config BSP_USING_DAC2
+                bool "Enable DAC2"
+                default n
+        endif
+
+    menuconfig BSP_USING_TIM
+        bool "Enable timer"
+        default n
+        select RT_USING_HWTIMER
+        if BSP_USING_TIM
+            config BSP_USING_TIM1
+                bool "Enable TIM1"
+                default n
+            config BSP_USING_TIM2
+                bool "Enable TIM2"
+                default n
+        endif
+endmenu
+
+menu "Board extended module Drivers"
+
+    config BSP_USING_SLIDER
+        bool "Enable Slider Demo"
+        select BSP_USING_PWM
+        select BSP_USING_PWM0
+        select BSP_USING_PWM0_CH3
+        select BSP_USING_PWM0_PORT13
+        default n
+
+        menuconfig BSP_USING_RW007
+            bool "Enable RW007"
+            default n
+            select PKG_USING_RW007
+            select BSP_USING_SPI
+            select RW007_NOT_USE_EXAMPLE_DRIVERS
+
+        if BSP_USING_RW007
+            comment "Notice: P5_7 --> 47; P6_2 -->50; P6_5 --> 53; P12_0 --> 96"
+            config IFX_RW007_SPI_BUS_NAME
+                string "RW007 BUS NAME"
+                default "spi3"
+
+            config IFX_RW007_WIFI_SSID
+                string "Wi-Fi SSID"
+                default "realthread_VIP"
+
+            config IFX_RW007_WIFI_PASSWORD
+                string "Wi-Fi Password"
+                default "your wifi password"
+
+            config IFX_RW007_CS_PIN
+                int "(INT)CS pin index"
+                range 1 113
+                default 96
+
+            config IFX_RW007_BOOT0_PIN
+                int "(INT)BOOT0 pin index (same as spi clk pin)"
+                range 1 113
+                default 50
+
+            config IFX_RW007_BOOT1_PIN
+                int "(INT)BOOT1 pin index (same as spi cs pin)"
+                range 1 113
+                default 96
+
+            config IFX_RW007_INT_BUSY_PIN
+                int "(INT)INT/BUSY pin index"
+                range 1 113
+                default 47
+
+            config IFX_RW007_RST_PIN
+                int "(INT)RESET pin index"
+                range 1 113
+                default 53
+        endif
+endmenu
+
+endmenu

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/SConscript

@@ -0,0 +1,40 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+objs = []
+cwd = GetCurrentDir()
+list = os.listdir(cwd)
+
+# add general drivers
+src = Split('''
+board.c
+''')
+
+if GetDepend(['BSP_USING_SPI3_SAMPLE']):
+    src += Glob('ports/spi_sample.c')
+
+if GetDepend(['BSP_USING_RW007']):
+    src += Glob('ports/drv_rw007.c')
+
+if GetDepend(['BSP_USING_SLIDER']):
+    src += Glob('ports/slider_sample.c')
+
+path = [cwd]
+path += [cwd + '/ports']
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.PLATFORM in ['gcc']:
+    src += [startup_path_prefix +
+            '/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S']
+elif rtconfig.PLATFORM in ['armclang']:
+    src += [startup_path_prefix +
+            '/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S']
+
+CPPDEFINES = ['CY8C6245LQI_S3D72', 'CY_USING_HAL', 'COMPONENT_CAT1A', 'COMPONENT_CAT1', 'COMPONENT_BSP_DESIGN_MODUS']
+group = DefineGroup('Drivers', src, depend=[''], CPPPATH=path, CPPDEFINES=CPPDEFINES)
+
+Return('group')

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/board.c

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-06-29     Rbb666       first version
+ */
+
+#include "board.h"
+
+void cy_bsp_all_init(void)
+{
+    cy_rslt_t result;
+
+    /* Initialize the device and board peripherals */
+    result = cybsp_init();
+
+    /* Board init failed. Stop program execution */
+    if (result != CY_RSLT_SUCCESS)
+    {
+        CY_ASSERT(0);
+    }
+}

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/board.h

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-01-16     Rbb666       first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include "drv_common.h"
+#include "drv_gpio.h"
+
+#include "cy_result.h"
+#include "cybsp_types.h"
+#include "cyhal.h"
+#include "cybsp.h"
+
+#ifdef BSP_USING_USBD
+    #include "cy_usb_dev.h"
+    #include "cy_usb_dev_hid.h"
+    #include "cycfg_usbdev.h"
+#endif
+
+/*SRAM CONFIG*/
+#define IFX_SRAM_SIZE                   (246)
+#define IFX_SRAM_END                    (0x08002000 + IFX_SRAM_SIZE * 1024)
+
+#ifdef __ARMCC_VERSION
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+    #define HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+    #define HEAP_END        IFX_SRAM_END
+#elif __ICCARM__
+    #pragma section="HEAP"
+    #define HEAP_BEGIN    (__segment_end("HEAP"))
+#else
+    extern unsigned int __end__;
+    extern unsigned int __HeapLimit;
+    #define HEAP_BEGIN    (void*)&__end__
+    #define HEAP_END      (void*)&__HeapLimit
+#endif
+
+void cy_bsp_all_init(void);
+
+#endif
+

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/linker_scripts/link.icf

@@ -0,0 +1,247 @@
+/*******************************************************************************
+* \file cy8c6xx5_cm4_dual.icf
+* \version 2.91
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x0803F7FF;
+
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x1007FFFF;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+  define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+    define symbol __ICFEDIT_size_heap__ = 0x0400;
+} else {
+  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+ * More about CM0+ prebuilt images, see here:
+ * https://github.com/cypresssemiconductorco/psoc6cm0p
+ */
+/* The size of the Cortex-M0+ application image */
+define symbol FLASH_CM0P_SIZE  = 0x2000;
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block CM0P_RO with size = FLASH_CM0P_SIZE  { readonly section .cy_m0p_image };
+define block RO     {first section .intvec, readonly};
+
+define block cy_xip { section .cy_xip };
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize  { section .noinit, section .intvec_ram };
+
+/*-Placement-*/
+
+/* Flash - Cortex-M0+ application image */
+place at start of IROM1_region  { block CM0P_RO };
+
+/* Flash - Cortex-M4 application */
+place in          IROM1_region  { block RO };
+
+/* Used for the digital signature of the secure application and the Bootloader SDK application. */
+".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+"cy_xip" : place at start of EROM1_region  { block cy_xip };
+
+/* RAM */
+place at start of IRAM1_region  { readwrite section .intvec_ram};
+place in          IRAM1_region  { readwrite };
+place at end   of IRAM1_region  { block HSTACK };
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep {  section .cy_m0p_image,
+        section .cy_app_signature,
+        section .cy_em_eeprom,
+        section .cy_sflash_user_data,
+        section .cy_sflash_nar,
+        section .cy_sflash_public_key,
+        section .cy_toc_part2,
+        section .cy_rtoc_part2,
+        section .cy_efuse,
+        section .cy_xip,
+        section .cymeta,
+         };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start    = 0x10000000;
+define exported symbol __cy_memory_0_length   = 0x00080000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start    = 0x14000000;
+define exported symbol __cy_memory_1_length   = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start    = 0x16000000;
+define exported symbol __cy_memory_2_length   = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start    = 0x18000000;
+define exported symbol __cy_memory_3_length   = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start    = 0x90700000;
+define exported symbol __cy_memory_4_length   = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/linker_scripts/link.ld

@@ -0,0 +1,487 @@
+/***************************************************************************//**
+* \file cy8c6xx5_cm4_dual.ld
+* \version 2.91
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+/* The size of the stack section at the end of CM4 SRAM */
+STACK_SIZE = 0x1000;
+
+/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+* More about CM0+ prebuilt images, see here:
+* https://github.com/cypresssemiconductorco/psoc6cm0p
+*/
+/* The size of the Cortex-M0+ application image at the start of FLASH */
+FLASH_CM0P_SIZE  = 0x2000;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+    /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
+     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+     * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+     * Using this memory region for other purposes will lead to unexpected behavior.
+     * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
+     * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
+     */
+    ram               (rwx)   : ORIGIN = 0x08002000, LENGTH = 0x3D800
+    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x80000
+
+    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+     * You can assign sections to this memory region for only one of the cores.
+     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+     * Therefore, repurposing this memory region will prevent such middleware from operation.
+     */
+    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */
+
+    /* The following regions define device specific memory regions and must not be changed. */
+    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
+    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
+    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
+    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
+    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
+    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
+    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+
+
+SECTIONS
+{
+     /* Cortex-M0+ application flash image area */
+    .cy_m0p_image ORIGIN(flash) :
+    {
+        . = ALIGN(4);
+        __cy_m0p_code_start = . ;
+        KEEP(*(.cy_m0p_image))
+        __cy_m0p_code_end = . ;
+    } > flash
+
+    /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
+    ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
+
+    /* Cortex-M4 application flash area */
+    .text ORIGIN(flash) + FLASH_CM0P_SIZE :
+    {
+        . = ALIGN(4);
+        __Vectors = . ;
+        KEEP(*(.vectors))
+        . = ALIGN(4);
+        __Vectors_End = .;
+        __Vectors_Size = __Vectors_End - __Vectors;
+        __end__ = .;
+
+        . = ALIGN(4);
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        . = ALIGN(4);
+        /* Read-only code (constants). */
+        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+        KEEP(*(.eh_frame*))
+
+        /* section information for utest */
+        . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+    } > flash
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > flash
+
+    __exidx_start = .;
+
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > flash
+    __exidx_end = .;
+
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm4.S */
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+
+        /* Copy interrupt vectors from flash to RAM */
+        LONG (__Vectors)                                    /* From */
+        LONG (__ram_vectors_start__)                        /* To   */
+        LONG (__Vectors_End - __Vectors)                    /* Size */
+
+        /* Copy data section to RAM */
+        LONG (__etext)                                      /* From */
+        LONG (__data_start__)                               /* To   */
+        LONG (__data_end__ - __data_start__)                /* Size */
+
+        __copy_table_end__ = .;
+    } > flash
+
+    . = ALIGN(4);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+    } > flash
+
+    . = ALIGN(4);
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    } > flash
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm4.S */
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        __zero_table_end__ = .;
+    } > flash
+
+    __etext =  . ;
+
+    .ramVectors (NOLOAD) : ALIGN(8)
+    {
+        __ram_vectors_start__ = .;
+        KEEP(*(.ram_vectors))
+        __ram_vectors_end__   = .;
+    } > ram
+
+
+    .data __ram_vectors_end__ :
+    {
+        . = ALIGN(4);
+        __data_start__ = .;
+
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+
+        KEEP(*(.cy_ramfunc*))
+        . = ALIGN(4);
+
+        __data_end__ = .;
+
+    } > ram AT>flash
+
+
+    /* Place variables in the section that should not be initialized during the
+    *  device startup.
+    */
+    .noinit (NOLOAD) : ALIGN(8)
+    {
+      KEEP(*(.noinit))
+    } > ram
+
+
+    /* The uninitialized global or static variables are placed in this section.
+    *
+    * The NOLOAD attribute tells linker that .bss section does not consume
+    * any space in the image. The NOLOAD attribute changes the .bss type to
+    * NOBITS, and that  makes linker to A) not allocate section in memory, and
+    * A) put information to clear the section with all zeros during application
+    * loading.
+    *
+    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+    * This  makes linker to A) allocate zeroed section in memory, and B) copy
+    * this section to RAM during application loading.
+    */
+    .bss (NOLOAD):
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > ram
+
+
+    .heap (NOLOAD):
+    {
+        __HeapBase = .;
+        __end__ = .;
+        end = __end__;
+        KEEP(*(.heap*))
+        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+        __HeapLimit = .;
+    } > ram
+
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (NOLOAD):
+    {
+        KEEP(*(.stack*))
+    } > ram
+
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(ram) + LENGTH(ram);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+    /* Used for the digital signature of the secure application and the Bootloader SDK application.
+    * The size of the section depends on the required data size. */
+    .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
+    {
+        KEEP(*(.cy_app_signature))
+    } > flash
+
+
+    /* Emulated EEPROM Flash area */
+    .cy_em_eeprom :
+    {
+        KEEP(*(.cy_em_eeprom))
+    } > em_eeprom
+
+
+    /* Supervisory Flash: User data */
+    .cy_sflash_user_data :
+    {
+        KEEP(*(.cy_sflash_user_data))
+    } > sflash_user_data
+
+    /* Supervisory Flash: Normal Access Restrictions (NAR) */
+    .cy_sflash_nar :
+    {
+        KEEP(*(.cy_sflash_nar))
+    } > sflash_nar
+
+
+    /* Supervisory Flash: Public Key */
+    .cy_sflash_public_key :
+    {
+        KEEP(*(.cy_sflash_public_key))
+    } > sflash_public_key
+
+
+    /* Supervisory Flash: Table of Content # 2 */
+    .cy_toc_part2 :
+    {
+        KEEP(*(.cy_toc_part2))
+    } > sflash_toc_2
+
+
+    /* Supervisory Flash: Table of Content # 2 Copy */
+    .cy_rtoc_part2 :
+    {
+        KEEP(*(.cy_rtoc_part2))
+    } > sflash_rtoc_2
+
+
+    /* Places the code in the Execute in Place (XIP) section. See the smif driver
+    *  documentation for details.
+    */
+    cy_xip :
+    {
+        __cy_xip_start = .;
+        KEEP(*(.cy_xip))
+        __cy_xip_end = .;
+    } > xip
+
+
+    /* eFuse */
+    .cy_efuse :
+    {
+        KEEP(*(.cy_efuse))
+    } > efuse
+
+
+    /* These sections are used for additional metadata (silicon revision,
+    *  Silicon/JTAG ID, etc.) storage.
+    */
+    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start    = 0x10000000;
+__cy_memory_0_length   = 0x00080000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start    = 0x14000000;
+__cy_memory_1_length   = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start    = 0x16000000;
+__cy_memory_2_length   = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start    = 0x18000000;
+__cy_memory_3_length   = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start    = 0x90700000;
+__cy_memory_4_length   = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/linker_scripts/link.sct

@@ -0,0 +1,277 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx5_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08002000
+#define RAM_SIZE                0x0003D800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00080000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE         0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    { 
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/ports/drv_rw007.c

@@ -0,0 +1,67 @@
+#include <rtthread.h>
+#include <rtdbg.h>
+#ifdef BSP_USING_RW007
+#include <rtdevice.h>
+#include <drv_spi.h>
+#include <board.h>
+#include <spi_wifi_rw007.h>
+
+extern void spi_wifi_isr(int vector);
+
+static void rw007_gpio_init(void)
+{
+    /* Configure IO */
+    rt_pin_mode(IFX_RW007_RST_PIN, PIN_MODE_OUTPUT);
+    rt_pin_mode(IFX_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLDOWN);
+
+    /* Reset rw007 and config mode */
+    rt_pin_write(IFX_RW007_RST_PIN, PIN_LOW);
+    rt_thread_delay(rt_tick_from_millisecond(100));
+    rt_pin_write(IFX_RW007_RST_PIN, PIN_HIGH);
+
+    /* Wait rw007 ready(exit busy stat) */
+    while (!rt_pin_read(IFX_RW007_INT_BUSY_PIN))
+    {
+        rt_thread_delay(5);
+    }
+
+    rt_thread_delay(rt_tick_from_millisecond(200));
+    rt_pin_mode(IFX_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP);
+}
+
+static struct rt_spi_device rw007_dev;
+
+int wifi_spi_device_init(void)
+{
+    char sn_version[32];
+    uint32_t cs_pin = IFX_RW007_CS_PIN;
+
+    rw007_gpio_init();
+    rt_hw_spi_device_attach(IFX_RW007_SPI_BUS_NAME, "wspi", cs_pin);
+    rt_hw_wifi_init("wspi");
+
+    rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION);
+    rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP);
+
+    rw007_sn_get(sn_version);
+    rt_kprintf("\nrw007  sn: [%s]\n", sn_version);
+    rw007_version_get(sn_version);
+    rt_kprintf("rw007 ver: [%s]\n\n", sn_version);
+
+    return 0;
+}
+INIT_APP_EXPORT(wifi_spi_device_init);
+
+static void int_wifi_irq(void *p)
+{
+    ((void)p);
+    spi_wifi_isr(0);
+}
+
+void spi_wifi_hw_init(void)
+{
+    rt_pin_attach_irq(IFX_RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0);
+    rt_pin_irq_enable(IFX_RW007_INT_BUSY_PIN, RT_TRUE);
+}
+
+#endif /* BSP_USING_RW007 */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/ports/fal_cfg.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-27     Rbb666       first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+extern const struct fal_flash_dev ifx_onchip_flash_32k;
+extern const struct fal_flash_dev ifx_onchip_flash_256k;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE         \
+    {                               \
+        &ifx_onchip_flash_32k,      \
+        &ifx_onchip_flash_256k,     \
+    }
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+
+/* partition table */
+#define FAL_PART_TABLE                                                                  \
+    {                                                                                   \
+        {FAL_PART_MAGIC_WROD, "param", "onchip_flash_32k", 0, IFX_EFLASH_SIZE, 0},      \
+        {FAL_PART_MAGIC_WROD, "app", "onchip_flash_256k", 0, IFX_FLASH_SIZE, 0},        \
+    }
+
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* _FAL_CFG_H_ */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/ports/slider_sample.c

@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-28     Rbb666       first version
+ */
+
+#include <rtthread.h>
+#include "drv_common.h"
+
+#ifdef BSP_USING_SLIDER
+#include "cycfg_capsense.h"
+
+#define CAPSENSE_INTR_PRIORITY      (7u)
+#define EZI2C_INTR_PRIORITY         (6u)
+
+/* Allowed duty cycle for maximum brightness */
+#define LED_MAX_BRIGHTNESS      (100u)
+
+/* Allowed duty cycle for minimum brightness*/
+#define LED_MIN_BRIGHTNESS      (0u)
+
+#define GET_DUTY_CYCLE(x)       (1 * 1000 * 1000 - x * 10 * 1000)
+
+typedef enum
+{
+    LED_OFF,
+    LED_ON
+} led_state_t;
+
+typedef struct
+{
+    led_state_t state;
+    uint32_t brightness;
+} led_data_t;
+
+static rt_sem_t trans_done_semphr = RT_NULL;
+
+#ifndef RT_USING_PWM
+    #error You need enable PWM to use this sample
+#else
+    #define PWM_DEV_NAME "pwm0"
+    #define PWM_DEV_CHANNEL 3
+    static struct rt_device_pwm *pwm_dev;
+#endif
+
+static void capsense_isr(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    Cy_CapSense_InterruptHandler(CYBSP_CSD_HW, &cy_capsense_context);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void capsense_callback(cy_stc_active_scan_sns_t *ptrActiveScan)
+{
+    rt_sem_release(trans_done_semphr);
+}
+
+static uint32_t initialize_capsense(void)
+{
+    uint32_t status = CYRET_SUCCESS;
+
+    /* CapSense interrupt configuration parameters */
+    static const cy_stc_sysint_t capSense_intr_config =
+    {
+        .intrSrc = csd_interrupt_IRQn,
+        .intrPriority = CAPSENSE_INTR_PRIORITY,
+    };
+
+    /* Capture the CSD HW block and initialize it to the default state. */
+    status = Cy_CapSense_Init(&cy_capsense_context);
+    if (CYRET_SUCCESS != status)
+    {
+        return status;
+    }
+
+    /* Initialize CapSense interrupt */
+    cyhal_system_set_isr(csd_interrupt_IRQn, csd_interrupt_IRQn, CAPSENSE_INTR_PRIORITY, &capsense_isr);
+    NVIC_ClearPendingIRQ(capSense_intr_config.intrSrc);
+    NVIC_EnableIRQ(capSense_intr_config.intrSrc);
+
+    /* Initialize the CapSense firmware modules. */
+    status = Cy_CapSense_Enable(&cy_capsense_context);
+    if (CYRET_SUCCESS != status)
+    {
+        return status;
+    }
+
+    /* Assign a callback function to indicate end of CapSense scan. */
+    status = Cy_CapSense_RegisterCallback(CY_CAPSENSE_END_OF_SCAN_E,
+                                          capsense_callback, &cy_capsense_context);
+    if (CYRET_SUCCESS != status)
+    {
+        return status;
+    }
+
+    return status;
+}
+
+void Slider_Init(void)
+{
+    cy_rslt_t result;
+
+    result = initialize_capsense();
+
+    if (CYRET_SUCCESS != result)
+    {
+        /* Halt the CPU if CapSense initialization failed */
+        RT_ASSERT(0);
+    }
+
+    /* Initiate first scan */
+    Cy_CapSense_ScanAllWidgets(&cy_capsense_context);
+
+    trans_done_semphr = rt_sem_create("slider_sem", 1, RT_IPC_FLAG_PRIO);
+    if (trans_done_semphr == RT_NULL)
+    {
+        rt_kprintf("create transform done semphr failed.\n");
+        RT_ASSERT(0);
+        return;
+    }
+
+#ifdef BSP_USING_PWM0_PORT13
+    /* Initiate PWM*/
+    pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
+
+    if (pwm_dev == RT_NULL)
+    {
+        rt_kprintf("PWM init failed! can't find %s device!\n", PWM_DEV_NAME);
+        RT_ASSERT(0);
+    }
+
+    /*default   period:1ms    pulse:0*/
+    rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, 1 * 1000 * 1000, 1 * 1000 * 1000);
+    rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL);
+#endif
+}
+
+void update_led_state(led_data_t *ledData)
+{
+    if (ledData->brightness >= 0)
+    {
+        uint32_t brightness = (ledData->brightness < LED_MIN_BRIGHTNESS) ? LED_MIN_BRIGHTNESS : ledData->brightness;
+
+        /* Drive the LED with brightness */
+        rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, 1 * 1000 * 1000, GET_DUTY_CYCLE(brightness));
+    }
+}
+
+static void process_touch(void)
+{
+    cy_stc_capsense_touch_t *slider_touch_info;
+    uint16_t slider_pos;
+    uint8_t slider_touch_status;
+    bool led_update_req = false;
+
+    static uint16_t slider_pos_prev;
+    static led_data_t led_data = {LED_ON, LED_MAX_BRIGHTNESS};
+
+    /* Get slider status */
+    slider_touch_info = Cy_CapSense_GetTouchInfo(
+                            CY_CAPSENSE_LINEARSLIDER0_WDGT_ID, &cy_capsense_context);
+    slider_touch_status = slider_touch_info->numPosition;
+    slider_pos = slider_touch_info->ptrPosition->x;
+
+    /* Detect the new touch on slider */
+    if ((RT_NULL != slider_touch_status) &&
+            (slider_pos != slider_pos_prev))
+    {
+        led_data.brightness = (slider_pos * 100)
+                              / cy_capsense_context.ptrWdConfig[CY_CAPSENSE_LINEARSLIDER0_WDGT_ID].xResolution;
+
+        led_update_req = true;
+    }
+
+#ifndef RT_USING_PWM
+#error You need enable PWM to use this sample
+#else
+    /* Update the LED state if requested */
+    if (led_update_req)
+    {
+        update_led_state(&led_data);
+    }
+#endif
+    slider_pos_prev = slider_pos;
+}
+
+static void Slider_thread_entry(void *parameter)
+{
+    Slider_Init();
+
+    for (;;)
+    {
+        rt_sem_take(trans_done_semphr, RT_WAITING_FOREVER);
+
+        /* Process all widgets */
+        Cy_CapSense_ProcessAllWidgets(&cy_capsense_context);
+
+        /* Process touch input */
+        process_touch();
+
+        /* Establishes synchronized operation between the CapSense
+         * middleware and the CapSense Tuner tool.
+         */
+        Cy_CapSense_RunTuner(&cy_capsense_context);
+
+        /* Initiate next scan */
+        Cy_CapSense_ScanAllWidgets(&cy_capsense_context);
+
+        rt_thread_mdelay(50);
+    }
+}
+
+int Slider_ctrl_sample(void)
+{
+    rt_err_t ret = RT_EOK;
+
+    rt_thread_t thread = rt_thread_create("slider_th",
+                                          Slider_thread_entry,
+                                          RT_NULL,
+                                          1024,
+                                          25,
+                                          10);
+    if (thread != RT_NULL)
+    {
+        rt_thread_startup(thread);
+    }
+    else
+    {
+        ret = RT_ERROR;
+    }
+
+    return ret;
+}
+MSH_CMD_EXPORT(Slider_ctrl_sample, Slider sample to ctrl led);
+#endif

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/ports/spi_sample.c

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-19     Rbbb666      first version
+ */
+
+#include "board.h"
+
+#if defined(BSP_USING_SPI3_SAMPLE)
+#include <drv_spi.h>
+
+#define SPI_NAME     "spi30"
+static struct rt_spi_device *spi_dev = RT_NULL;
+
+/* attach spi5 device */
+static int rt_spi_device_init(void)
+{
+    struct rt_spi_configuration cfg;
+
+    rt_hw_spi_device_attach("spi3", "spi30", NULL);
+
+    cfg.data_width = 8;
+    cfg.mode   = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB | RT_SPI_NO_CS;
+    cfg.max_hz = 1 *1000 *1000;
+
+    spi_dev = (struct rt_spi_device *)rt_device_find(SPI_NAME);
+
+    if (RT_NULL == spi_dev)
+    {
+        rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_NAME);
+        return RT_ERROR;
+    }
+
+    rt_spi_configure(spi_dev, &cfg);
+
+    return RT_EOK;
+}
+INIT_APP_EXPORT(rt_spi_device_init);
+
+/* spi5 loopback mode test case */
+static int spi_sample(int argc, char **argv)
+{
+    rt_uint8_t t_buf[8], r_buf[8];
+    int i = 0;
+    static struct rt_spi_message msg1;
+
+    if (argc != 9)
+    {
+        rt_kprintf("Please Usage:\n");
+        rt_kprintf("spi_sample 1 2 3 4 5 6 7 8\n");
+        return -RT_ERROR;
+    }
+
+    for (i = 0; i < 8; i++)
+    {
+        t_buf[i] = atoi(argv[i+1]);
+    }
+
+    msg1.send_buf   = &t_buf;
+    msg1.recv_buf   = &r_buf;
+    msg1.length     = sizeof(t_buf);
+    msg1.cs_take    = 1;
+    msg1.cs_release = 0;
+    msg1.next       = RT_NULL;
+
+    rt_spi_transfer_message(spi_dev, &msg1);
+
+    rt_kprintf("spi rbuf : ");
+    for (i = 0; i < sizeof(t_buf); i++)
+    {
+        rt_kprintf("%x ", r_buf[i]);
+    }
+
+    rt_kprintf("\nspi loopback mode test over!\n");
+
+    return RT_EOK;
+}
+MSH_CMD_EXPORT(spi_sample, spi loopback test);
+
+#endif /* BSP_USING_SPI3 */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/SConscript

@@ -0,0 +1,26 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = []
+group = []
+CPPPATH = []
+
+if rtconfig.PLATFORM in ['iccarm']:
+    print("\nThe current project does not support IAR build\n")
+    Return('group')
+elif rtconfig.PLATFORM in ['gcc', 'armclang']:
+    src += Glob(cwd + '/TARGET_CY8CPROTO-062S3-4343W/*.c')
+    src += Glob(cwd + '/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM4/*.c')
+    src += Glob(cwd + '/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/*.c')
+
+    CPPPATH = [ cwd + '/TARGET_CY8CPROTO-062S3-4343W',
+                cwd + '/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource']
+    if rtconfig.PLATFORM in ['gcc']:
+        src += [cwd + '/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S']
+    elif rtconfig.PLATFORM in ['armclang']:
+        src += [cwd + '/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S']
+
+group = DefineGroup('libs', src, depend = [''], CPPPATH = CPPPATH)
+Return('group')

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/.cyignore

@@ -0,0 +1,9 @@
+docs
+
+# Exclude old firmware resources that were not flexible enough for custom BSPs (Flow version 2)
+$(SEARCH_wifi-host-driver)/WiFi_Host_Driver/resources/nvram_deprecated/
+$(SEARCH_bluetooth-freertos)/firmware_deprecated/
+
+# Exclude old firmware resources that were not flexible enough for custom BSPs (Flow version 1)
+../wifi-host-driver/WiFi_Host_Driver/resources/nvram_deprecated/
+../bluetooth-freertos/firmware_deprecated/

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

@@ -0,0 +1,39 @@
+/*******************************************************************************
+* File Name: cycfg.c
+*
+* Description:
+* Wrapper function to initialize all generated code.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg.h"
+
+void init_cycfg_all(void)
+{
+    init_cycfg_system();
+    init_cycfg_clocks();
+    init_cycfg_routing();
+    init_cycfg_peripherals();
+    init_cycfg_pins();
+}

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

@@ -0,0 +1,53 @@
+/*******************************************************************************
+* File Name: cycfg.h
+*
+* Description:
+* Simple wrapper header containing all generated files.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_H)
+#define CYCFG_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+#include "cycfg_system.h"
+#include "cycfg_connectivity_bt.h"
+#include "cycfg_clocks.h"
+#include "cycfg_routing.h"
+#include "cycfg_peripherals.h"
+#include "cycfg_pins.h"
+
+void init_cycfg_all(void);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_H */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

@@ -0,0 +1,29 @@
+/*******************************************************************************
+* File Name: cycfg.timestamp
+*
+* Description:
+* Sentinel file for determining if generated source is up to date.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c

@@ -0,0 +1,859 @@
+/*******************************************************************************
+* File Name: cycfg_capsense.c
+*
+* Description:
+* CapSense Middleware configuration
+* This file should not be modified. It was automatically generated by
+* CapSense Configurator 4.0.0.5943
+*
+********************************************************************************
+* Copyright 2021, Cypress Semiconductor Corporation (an Infineon company)
+* or an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cycfg_capsense.h"
+
+#if !defined(CY_DISABLE_CAPSENSE)
+
+#if (CY_CAPSENSE_CORE == __CORTEX_M)
+
+#ifndef CSD_CMODPADS_PORT
+#define CSD_CMODPADS_PORT 0xFF
+#endif
+#ifndef CSD_CMODPADS_PIN
+#define CSD_CMODPADS_PIN 0xFF
+#endif
+#ifndef CSD_CSH_TANKPADS_PORT
+#define CSD_CSH_TANKPADS_PORT 0xFF
+#endif
+#ifndef CSD_CSH_TANKPADS_PIN
+#define CSD_CSH_TANKPADS_PIN 0xFF
+#endif
+#ifndef CSD_CSHIELDPADS_PORT
+#define CSD_CSHIELDPADS_PORT 0xFF
+#endif
+#ifndef CSD_CSHIELDPADS_PIN
+#define CSD_CSHIELDPADS_PIN 0xFF
+#endif
+#ifndef CSD_VREF_EXT_PORT
+#define CSD_VREF_EXT_PORT 0xFF
+#endif
+#ifndef CSD_VREF_EXT_PIN
+#define CSD_VREF_EXT_PIN 0xFF
+#endif
+
+static cy_stc_capsense_internal_context_t cy_capsense_internalContext;
+static cy_stc_active_scan_sns_t cy_capsense_activeScanSns;
+
+#if (CY_CAPSENSE_DEBOUNCE_SIZE > 0)
+    static uint8_t cy_capsense_debounce[CY_CAPSENSE_DEBOUNCE_SIZE] = {0};
+#endif
+
+#if (CY_CAPSENSE_NOISE_ENVELOPE_SIZE > 0)
+    static cy_stc_capsense_smartsense_csd_noise_envelope_t cy_capsense_noiseEnvelope[CY_CAPSENSE_NOISE_ENVELOPE_SIZE];
+#endif
+
+#if (CY_CAPSENSE_RAW_HISTORY_SIZE > 0)
+    static uint16_t cy_capsense_rawFilterHistory[CY_CAPSENSE_RAW_HISTORY_SIZE] = {0};
+#endif
+
+#if (CY_CAPSENSE_IIR_HISTORY_LOW_SIZE > 0)
+    static uint8_t cy_capsense_iirHistoryLow[CY_CAPSENSE_IIR_HISTORY_LOW_SIZE] = {0};
+#endif
+
+#if (CY_CAPSENSE_POSITION_FILTER_HISTORY_SIZE > 0)
+    static cy_stc_capsense_position_t cy_capsense_positionFilterHistory[CY_CAPSENSE_POSITION_FILTER_HISTORY_SIZE];
+#endif
+
+#if (CY_CAPSENSE_TOUCH_FILTER_HISTORY_SIZE > 0)
+    static cy_stc_capsense_touch_t cy_capsense_touchFilterHistory[CY_CAPSENSE_TOUCH_FILTER_HISTORY_SIZE] =
+    {
+    };
+#endif
+
+#if (CY_CAPSENSE_DIPLEX_SIZE > 0)
+    static const uint8_t cy_capsense_diplexTable[CY_CAPSENSE_DIPLEX_SIZE] =
+    {
+    };
+#endif
+
+#if (CY_CAPSENSE_CSD_TOUCHPAD_MAX_SENSORS_SIZE > 0)
+    static uint16_t cy_capsense_csdTouchBuffer[CY_CAPSENSE_CSD_TOUCHPAD_MAX_SENSORS_SIZE] = {0};
+#endif
+
+#if (CY_CAPSENSE_CSX_TOUCH_BUFFER_ENABLE > 0)
+    static cy_stc_capsense_csx_touch_buffer_t cy_capsense_csxTouchBuffer;
+#endif
+
+#if (CY_CAPSENSE_CSX_TOUCH_HISTORY_SIZE > 0)
+    static cy_stc_capsense_csx_touch_history_t cy_capsense_csxTouchHistory[CY_CAPSENSE_CSX_TOUCH_HISTORY_SIZE] =
+    {
+    };
+#endif
+
+#if (CY_CAPSENSE_BALLISTIC_WIDGET_COUNT > 0)
+    static cy_stc_capsense_ballistic_context_t cy_capsense_ballisticContext[CY_CAPSENSE_BALLISTIC_WIDGET_COUNT];
+#endif
+
+#if (CY_CAPSENSE_GESTURE_WIDGET_COUNT > 0)
+    static cy_stc_capsense_gesture_context_t cy_capsense_gestureContext[CY_CAPSENSE_GESTURE_WIDGET_COUNT];
+#endif
+
+#if (CY_CAPSENSE_BIST_SUPPORTED)
+#if (CY_CAPSENSE_BIST_EN != 0)
+    uint16_t cy_capsense_bslnInv[CY_CAPSENSE_SENSOR_COUNT * CY_CAPSENSE_MFS_CH_NUMBER];
+    uint32_t cy_capsense_eltdCap[CY_CAPSENSE_ELTD_COUNT];
+    #if (CY_CAPSENSE_MW_VERSION >= 300)
+        uint32_t cy_capsense_snsCap[CY_CAPSENSE_SENSOR_COUNT];
+    #endif
+    uint16_t cy_capsense_wdgtCrc[CY_CAPSENSE_WIDGET_COUNT];
+#endif
+#endif
+
+static const cy_stc_capsense_common_config_t cy_capsense_commonConfig =
+{
+    .cpuClkHz = CY_CAPSENSE_CPU_CLK,
+    .periClkHz = CY_CAPSENSE_PERI_CLK,
+    .vdda = CY_CAPSENSE_VDDA_MV,
+    .numPin = CY_CAPSENSE_PIN_COUNT,
+    .numSns = CY_CAPSENSE_SENSOR_COUNT,
+    .numWd = CY_CAPSENSE_WIDGET_COUNT,
+    .csdEn = CY_CAPSENSE_ENABLE,
+    .csxEn = CY_CAPSENSE_DISABLE,
+    #if (CY_CAPSENSE_MW_VERSION < 300)
+        .mfsEn = CY_CAPSENSE_DISABLE,
+    #endif
+    #if (CY_CAPSENSE_BIST_SUPPORTED)
+        .bistEn = CY_CAPSENSE_DISABLE,
+    #endif
+    .positionFilterEn = CY_CAPSENSE_DISABLE,
+    .periDividerType = CY_CAPSENSE_PERI_DIV_TYPE,
+    .periDividerIndex = CY_CAPSENSE_PERI_DIV_INDEX,
+    .analogWakeupDelay = 25u,
+    .ssIrefSource = CY_CAPSENSE_IREF_SRSS,
+    .ssVrefSource = CY_CAPSENSE_VREF_SRSS,
+    .proxTouchCoeff = 300u,
+    .swSensorAutoResetEn = CY_CAPSENSE_DISABLE,
+    .portCmodPadNum = CSD_CMODPADS_PORT,
+    .pinCmodPad = CSD_CMODPADS_PIN,
+    .portCshPadNum = CSD_CSH_TANKPADS_PORT,
+    .pinCshPad = CSD_CSH_TANKPADS_PIN,
+    .portShieldPadNum = CSD_CSHIELDPADS_PORT,
+    .pinShieldPad = CSD_CSHIELDPADS_PIN,
+    .portVrefExtPadNum = CSD_VREF_EXT_PORT,
+    .pinVrefExtPad = CSD_VREF_EXT_PIN,
+    .portCmodNum = Cmod_PORT_NUM,
+    .idacGainTable = {
+        {0x01000000u,   37500u},
+        {0x03000000u,   75000u},
+        {0x01400000u,  300000u},
+        {0x03400000u,  600000u},
+        {0x01800000u, 2400000u},
+        {0x03800000u, 4800000u},
+    },
+    .ptrCsdBase = CSD0,
+    .ptrCsdContext = &cy_csd_0_context,
+    .portCmod = Cmod_PORT,
+    .portCsh = NULL,
+    .portCintA = NULL,
+    .portCintB = NULL,
+    .pinCmod = Cmod_PIN,
+    .portCshNum = 0u,
+    .pinCsh = 0u,
+    .pinCintA = 0u,
+    .pinCintB = 0u,
+    .csdShieldEn = CY_CAPSENSE_DISABLE,
+    .csdInactiveSnsConnection = CY_CAPSENSE_SNS_CONNECTION_GROUND,
+    #if (CY_CAPSENSE_MW_VERSION >= 300)
+        .csxInactiveSnsConnection = CY_CAPSENSE_SNS_CONNECTION_GROUND,
+    #endif
+    .csdShieldDelay = CY_CAPSENSE_SH_DELAY_0NS,
+    .csdVref = 0u,
+    .csdRConst = 1000u,
+    .csdCTankShieldEn = CY_CAPSENSE_DISABLE,
+    .csdShieldNumPin = 0u,
+    .csdShieldSwRes = CY_CAPSENSE_SHIELD_SW_RES_MEDIUM,
+    .csdInitSwRes = CY_CAPSENSE_INIT_SW_RES_MEDIUM,
+    .csdChargeTransfer = CY_CAPSENSE_IDAC_SOURCING,
+    .csdRawTarget = 85u,
+    .csdAutotuneEn = CY_CAPSENSE_CSD_SS_HWTH_EN,
+    .csdIdacAutocalEn = CY_CAPSENSE_ENABLE,
+    .csdIdacAutoGainEn = CY_CAPSENSE_ENABLE,
+    .csdCalibrationError = 10u,
+    .csdIdacGainInitIndex = 4u,
+    .csdIdacMin = 20u,
+    .csdIdacCompEn = CY_CAPSENSE_ENABLE,
+    .csdFineInitTime = 10u,
+    .csdIdacRowColAlignEn = CY_CAPSENSE_ENABLE,
+    .csdMfsDividerOffsetF1 = 1u,
+    .csdMfsDividerOffsetF2 = 2u,
+    .csxRawTarget = 40u,
+    .csxIdacGainInitIndex = 2u,
+    .csxIdacAutocalEn = CY_CAPSENSE_DISABLE,
+    .csxCalibrationError = 20u,
+    .csxFineInitTime = 10u,
+    .csxInitSwRes = CY_CAPSENSE_INIT_SW_RES_MEDIUM,
+    .csxScanSwRes = CY_CAPSENSE_INIT_SW_RES_LOW,
+    .csxInitShieldSwRes = CY_CAPSENSE_SHIELD_SW_RES_MEDIUM,
+    .csxScanShieldSwRes = CY_CAPSENSE_SHIELD_SW_RES_LOW,
+    .csxMfsDividerOffsetF1 = 1u,
+    .csxMfsDividerOffsetF2 = 2u,
+};
+
+#if (CY_CAPSENSE_MW_VERSION < 300)
+    static const cy_stc_capsense_fptr_config_t cy_capsense_fptrConfig =
+    {
+    #if (CY_CAPSENSE_CSD_EN == 0)
+        .fptrCSDSetupWidget = NULL,
+        .fptrCSDScan = NULL,
+        .fptrDpProcessCsdWidgetRawCounts = NULL,
+        .fptrDpProcessCsdWidgetStatus = NULL,
+        .fptrCSDDisableMode = NULL,
+        .fptrCSDInitialize = NULL,
+        .fptrCSDScanISR = NULL,
+    #else
+        .fptrCSDSetupWidget = &Cy_CapSense_CSDSetupWidget,
+        .fptrCSDScan = &Cy_CapSense_CSDScan,
+        .fptrDpProcessCsdWidgetRawCounts = &Cy_CapSense_DpProcessCsdWidgetRawCounts,
+        .fptrDpProcessCsdWidgetStatus = &Cy_CapSense_DpProcessCsdWidgetStatus,
+        .fptrCSDDisableMode = &Cy_CapSense_CSDDisableMode,
+        .fptrCSDInitialize = &Cy_CapSense_CSDInitialize,
+        .fptrCSDScanISR = &Cy_CapSense_CSDScanISR,
+    #endif
+
+    #if (CY_CAPSENSE_CSX_EN == 0)
+        .fptrCSXSetupWidget = NULL,
+        .fptrCSXScan = NULL,
+        .fptrDpProcessCsxWidgetRawCounts = NULL,
+        .fptrDpProcessCsxWidgetStatus = NULL,
+        .fptrCSXInitialize = NULL,
+        .fptrCSXDisableMode = NULL,
+        .fptrCSXScanISR = NULL,
+    #else
+        .fptrCSXSetupWidget = &Cy_CapSense_CSXSetupWidget,
+        .fptrCSXScan = &Cy_CapSense_CSXScan,
+        .fptrDpProcessCsxWidgetRawCounts = &Cy_CapSense_DpProcessCsxWidgetRawCounts,
+        .fptrDpProcessCsxWidgetStatus = &Cy_CapSense_DpProcessCsxWidgetStatus,
+        .fptrCSXInitialize = &Cy_CapSense_CSXInitialize,
+        .fptrCSXDisableMode = &Cy_CapSense_CSXDisableMode,
+        .fptrCSXScanISR = &Cy_CapSense_CSXScanISR,
+    #endif
+
+    #if (CY_CAPSENSE_ADAPTIVE_FILTER_EN == 0)
+        .fptrAdaptiveFilterInitializeLib = NULL,
+        .fptrAdaptiveFilterRunLib = NULL,
+    #else
+        .fptrAdaptiveFilterInitializeLib = &Cy_CapSense_AdaptiveFilterInitialize_Lib,
+        .fptrAdaptiveFilterRunLib = &Cy_CapSense_AdaptiveFilterRun_Lib,
+    #endif
+
+    #if (CY_CAPSENSE_BALLISTIC_MULTIPLIER_EN == 0)
+        .fptrBallisticMultiplierLib = NULL,
+    #else
+        .fptrBallisticMultiplierLib = &Cy_CapSense_BallisticMultiplier_Lib,
+    #endif
+
+    #if (CY_CAPSENSE_RAWCOUNT_FILTER_EN == 0)
+        .fptrInitializeAllFilters = NULL,
+        .fptrFtRunEnabledFiltersInternal = NULL,
+    #else
+        .fptrInitializeAllFilters = &Cy_CapSense_InitializeAllFilters,
+        .fptrFtRunEnabledFiltersInternal = &Cy_CapSense_FtRunEnabledFiltersInternal,
+    #endif
+
+    #if (CY_CAPSENSE_CSD_POSITION_FILTER_EN == 0)
+        .fptrProcessPositionFilters = NULL,
+    #else
+        .fptrProcessPositionFilters = &Cy_CapSense_ProcessPositionFilters,
+    #endif
+
+    #if ((CY_CAPSENSE_CSX_POSITION_FILTER_EN == 0) && (CY_CAPSENSE_CSD_POSITION_FILTER_EN == 0))
+        .fptrRunPositionFilters = NULL,
+        .fptrInitPositionFilters = NULL,
+    #else
+        .fptrRunPositionFilters = &Cy_CapSense_RunPositionFilters,
+        .fptrInitPositionFilters = &Cy_CapSense_InitPositionFilters,
+    #endif
+
+    #if ((CY_CAPSENSE_CSD_BUTTON_EN == 0) && \
+         (CY_CAPSENSE_CSX_BUTTON_EN == 0) && (CY_CAPSENSE_CSX_MATRIX_EN == 0))
+        .fptrDpProcessButton = NULL,
+    #else
+        .fptrDpProcessButton = &Cy_CapSense_DpProcessButton,
+    #endif
+
+    #if ((CY_CAPSENSE_CSD_SLIDER_EN == 0) && \
+         (CY_CAPSENSE_CSX_SLIDER_EN == 0))
+        .fptrDpProcessSlider = NULL,
+    #else
+        .fptrDpProcessSlider = &Cy_CapSense_DpProcessSlider,
+    #endif
+
+    #if (CY_CAPSENSE_CSD_MATRIX_EN == 0)
+        .fptrDpProcessCsdMatrix = NULL,
+    #else
+        .fptrDpProcessCsdMatrix = &Cy_CapSense_DpProcessCsdMatrix,
+    #endif
+
+    #if (CY_CAPSENSE_CSD_TOUCHPAD_EN == 0)
+        .fptrDpProcessCsdTouchpad = NULL,
+    #else
+        .fptrDpProcessCsdTouchpad = &Cy_CapSense_DpProcessCsdTouchpad,
+    #endif
+
+    #if (CY_CAPSENSE_CSD_PROXIMITY_EN == 0)
+        .fptrDpProcessProximity = NULL,
+    #else
+        .fptrDpProcessProximity = &Cy_CapSense_DpProcessProximity,
+    #endif
+
+    #if (CY_CAPSENSE_CSX_TOUCHPAD_EN == 0)
+        .fptrDpProcessCsxTouchpad = NULL,
+    #else
+        .fptrDpProcessCsxTouchpad = &Cy_CapSense_DpProcessCsxTouchpad,
+    #endif
+
+    #if (CY_CAPSENSE_ADVANCED_CENTROID_5X5_EN == 0)
+        .fptrDpAdvancedCentroidTouchpad = NULL,
+    #else
+        .fptrDpAdvancedCentroidTouchpad = &Cy_CapSense_DpAdvancedCentroidTouchpad,
+    #endif
+
+    #if ((CY_CAPSENSE_CSD_CALIBRATION_EN == 0) && (CY_CAPSENSE_SMARTSENSE_FULL_EN == 0))
+        .fptrCSDCalibrateWidget = NULL,
+        .fptrCalibrateAllCsdWidgets = NULL,
+    #else
+        .fptrCSDCalibrateWidget = &Cy_CapSense_CSDCalibrateWidget,
+        .fptrCalibrateAllCsdWidgets = &Cy_CapSense_CalibrateAllCsdWidgets,
+    #endif
+
+    #if (CY_CAPSENSE_CSX_CALIBRATION_EN == 0)
+        .fptrCalibrateAllCsxWidgets = NULL,
+    #else
+        .fptrCalibrateAllCsxWidgets = &Cy_CapSense_CalibrateAllCsxWidgets,
+    #endif
+
+    #if (CY_CAPSENSE_SMARTSENSE_FULL_EN == 0)
+        .fptrRunNoiseEnvelopeLib = NULL,
+        .fptrDpUpdateThresholds = NULL,
+        .fptrInitializeNoiseEnvelopeLib = NULL,
+    #else
+        .fptrRunNoiseEnvelopeLib = &Cy_CapSense_RunNoiseEnvelope_Lib,
+        .fptrDpUpdateThresholds = &Cy_CapSense_DpUpdateThresholds,
+        .fptrInitializeNoiseEnvelopeLib = &Cy_CapSense_InitializeNoiseEnvelope_Lib,
+    #endif
+
+    #if ((CY_CAPSENSE_SMARTSENSE_HW_EN == 0) && (CY_CAPSENSE_SMARTSENSE_FULL_EN == 0))
+        .fptrSsAutoTune = NULL,
+    #else
+        .fptrSsAutoTune = &Cy_CapSense_SsAutoTune,
+    #endif
+
+    #if (CY_CAPSENSE_BIST_SUPPORTED)
+    #if (CY_CAPSENSE_BIST_EN == 0)
+        .fptrBistInitialize = NULL,
+        .fptrBistDisableMode = NULL,
+        .fptrBistDsInitialize = NULL,
+    #else
+        .fptrBistInitialize = &Cy_CapSense_BistInitialize,
+        .fptrBistDisableMode = &Cy_CapSense_BistDisableMode,
+        .fptrBistDsInitialize = &Cy_CapSense_BistDsInitialize,
+    #endif
+    #endif
+    };
+#endif
+
+static const cy_stc_capsense_pin_config_t cy_capsense_pinConfig[CY_CAPSENSE_PIN_COUNT] =
+{
+    { /* Button0_Sns0 */
+        Button0_Sns0_PORT,
+        Button0_Sns0_PIN,
+    },
+    { /* Button1_Sns0 */
+        Button1_Sns0_PORT,
+        Button1_Sns0_PIN,
+    },
+    { /* LinearSlider0_Sns0 */
+        LinearSlider0_Sns0_PORT,
+        LinearSlider0_Sns0_PIN,
+    },
+    { /* LinearSlider0_Sns1 */
+        LinearSlider0_Sns1_PORT,
+        LinearSlider0_Sns1_PIN,
+    },
+    { /* LinearSlider0_Sns2 */
+        LinearSlider0_Sns2_PORT,
+        LinearSlider0_Sns2_PIN,
+    },
+    { /* LinearSlider0_Sns3 */
+        LinearSlider0_Sns3_PORT,
+        LinearSlider0_Sns3_PIN,
+    },
+    { /* LinearSlider0_Sns4 */
+        LinearSlider0_Sns4_PORT,
+        LinearSlider0_Sns4_PIN,
+    },
+};
+
+#if (CY_CAPSENSE_SHIELD_PIN_COUNT > 0)
+    static const cy_stc_capsense_pin_config_t cy_capsense_shieldPinConfig[CY_CAPSENSE_SHIELD_PIN_COUNT] =
+    {
+    };
+#endif
+
+#if (CY_CAPSENSE_ELTD_COUNT > 0)
+    static const cy_stc_capsense_electrode_config_t cy_capsense_electrodeConfig[CY_CAPSENSE_ELTD_COUNT] =
+    {
+        { /* Button0_Sns0 */
+            .ptrPin = &cy_capsense_pinConfig[0u],
+            .type = CY_CAPSENSE_ELTD_TYPE_SELF_E,
+            .numPins = 1u,
+        },
+        { /* Button1_Sns0 */
+            .ptrPin = &cy_capsense_pinConfig[1u],
+            .type = CY_CAPSENSE_ELTD_TYPE_SELF_E,
+            .numPins = 1u,
+        },
+        { /* LinearSlider0_Sns0 */
+            .ptrPin = &cy_capsense_pinConfig[2u],
+            .type = CY_CAPSENSE_ELTD_TYPE_SELF_E,
+            .numPins = 1u,
+        },
+        { /* LinearSlider0_Sns1 */
+            .ptrPin = &cy_capsense_pinConfig[3u],
+            .type = CY_CAPSENSE_ELTD_TYPE_SELF_E,
+            .numPins = 1u,
+        },
+        { /* LinearSlider0_Sns2 */
+            .ptrPin = &cy_capsense_pinConfig[4u],
+            .type = CY_CAPSENSE_ELTD_TYPE_SELF_E,
+            .numPins = 1u,
+        },
+        { /* LinearSlider0_Sns3 */
+            .ptrPin = &cy_capsense_pinConfig[5u],
+            .type = CY_CAPSENSE_ELTD_TYPE_SELF_E,
+            .numPins = 1u,
+        },
+        { /* LinearSlider0_Sns4 */
+            .ptrPin = &cy_capsense_pinConfig[6u],
+            .type = CY_CAPSENSE_ELTD_TYPE_SELF_E,
+            .numPins = 1u,
+        },
+    };
+#endif
+
+static const cy_stc_capsense_widget_config_t cy_capsense_widgetConfig[CY_CAPSENSE_WIDGET_COUNT] =
+{
+    { /* Button0 */
+        .ptrWdContext = &cy_capsense_tuner.widgetContext[0u],
+        .ptrSnsContext = &cy_capsense_tuner.sensorContext[0u],
+        .ptrEltdConfig = &cy_capsense_electrodeConfig[0u],
+#if (CY_CAPSENSE_BIST_SUPPORTED)
+        .ptrEltdCapacitance = NULL,
+        .ptrBslnInv = NULL,
+#endif
+        .ptrNoiseEnvelope = &cy_capsense_noiseEnvelope[0u],
+        .ptrRawFilterHistory = NULL,
+        .ptrRawFilterHistoryLow = NULL,
+        .iirCoeff = 128u,
+        .ptrDebounceArr = &cy_capsense_debounce[0u],
+        .ptrDiplexTable = NULL,
+        .centroidConfig = 0u,
+        .xResolution = 0u,
+        .yResolution = 0u,
+        .numSns = 1u,
+        .numCols = 1u,
+        .numRows = 0u,
+        .ptrPosFilterHistory = NULL,
+        .ptrCsxTouchHistory = NULL,
+        .ptrCsxTouchBuffer = NULL,
+        .ptrCsdTouchBuffer = NULL,
+        .ptrGestureConfig = NULL,
+        .ptrGestureContext = NULL,
+        .ballisticConfig = {
+            .accelCoeff = 9u,
+            .speedCoeff = 2u,
+            .divisorValue = 4u,
+            .speedThresholdX = 3u,
+            .speedThresholdY = 4u,
+        },
+        .ptrBallisticContext = NULL,
+        .aiirConfig = {
+            .maxK = 60u,
+            .minK = 1u,
+            .noMovTh = 3u,
+            .littleMovTh = 7u,
+            .largeMovTh = 12u,
+            .divVal = 64u,
+        },
+        .advConfig = {
+            .penultimateTh = 100u,
+            .virtualSnsTh = 100u,
+            .crossCouplingTh = 5u,
+        },
+        .posFilterConfig = 0u,
+        .rawFilterConfig = 0u,
+        #if (CY_CAPSENSE_MW_VERSION >= 300)
+            .senseMethod = CY_CAPSENSE_CSD_GROUP,
+        #else
+            .senseMethod = CY_CAPSENSE_SENSE_METHOD_CSD_E,
+        #endif
+        .wdType = CY_CAPSENSE_WD_BUTTON_E,
+    },
+    { /* Button1 */
+        .ptrWdContext = &cy_capsense_tuner.widgetContext[1u],
+        .ptrSnsContext = &cy_capsense_tuner.sensorContext[1u],
+        .ptrEltdConfig = &cy_capsense_electrodeConfig[1u],
+#if (CY_CAPSENSE_BIST_SUPPORTED)
+        .ptrEltdCapacitance = NULL,
+        .ptrBslnInv = NULL,
+#endif
+        .ptrNoiseEnvelope = &cy_capsense_noiseEnvelope[1u],
+        .ptrRawFilterHistory = NULL,
+        .ptrRawFilterHistoryLow = NULL,
+        .iirCoeff = 128u,
+        .ptrDebounceArr = &cy_capsense_debounce[1u],
+        .ptrDiplexTable = NULL,
+        .centroidConfig = 0u,
+        .xResolution = 0u,
+        .yResolution = 0u,
+        .numSns = 1u,
+        .numCols = 1u,
+        .numRows = 0u,
+        .ptrPosFilterHistory = NULL,
+        .ptrCsxTouchHistory = NULL,
+        .ptrCsxTouchBuffer = NULL,
+        .ptrCsdTouchBuffer = NULL,
+        .ptrGestureConfig = NULL,
+        .ptrGestureContext = NULL,
+        .ballisticConfig = {
+            .accelCoeff = 9u,
+            .speedCoeff = 2u,
+            .divisorValue = 4u,
+            .speedThresholdX = 3u,
+            .speedThresholdY = 4u,
+        },
+        .ptrBallisticContext = NULL,
+        .aiirConfig = {
+            .maxK = 60u,
+            .minK = 1u,
+            .noMovTh = 3u,
+            .littleMovTh = 7u,
+            .largeMovTh = 12u,
+            .divVal = 64u,
+        },
+        .advConfig = {
+            .penultimateTh = 100u,
+            .virtualSnsTh = 100u,
+            .crossCouplingTh = 5u,
+        },
+        .posFilterConfig = 0u,
+        .rawFilterConfig = 0u,
+        #if (CY_CAPSENSE_MW_VERSION >= 300)
+            .senseMethod = CY_CAPSENSE_CSD_GROUP,
+        #else
+            .senseMethod = CY_CAPSENSE_SENSE_METHOD_CSD_E,
+        #endif
+        .wdType = CY_CAPSENSE_WD_BUTTON_E,
+    },
+    { /* LinearSlider0 */
+        .ptrWdContext = &cy_capsense_tuner.widgetContext[2u],
+        .ptrSnsContext = &cy_capsense_tuner.sensorContext[2u],
+        .ptrEltdConfig = &cy_capsense_electrodeConfig[2u],
+#if (CY_CAPSENSE_BIST_SUPPORTED)
+        .ptrEltdCapacitance = NULL,
+        .ptrBslnInv = NULL,
+#endif
+        .ptrNoiseEnvelope = &cy_capsense_noiseEnvelope[2u],
+        .ptrRawFilterHistory = NULL,
+        .ptrRawFilterHistoryLow = NULL,
+        .iirCoeff = 128u,
+        .ptrDebounceArr = &cy_capsense_debounce[2u],
+        .ptrDiplexTable = NULL,
+        .centroidConfig = 1u,
+        .xResolution = 100u,
+        .yResolution = 0u,
+        .numSns = 5u,
+        .numCols = 5u,
+        .numRows = 0u,
+        .ptrPosFilterHistory = NULL,
+        .ptrCsxTouchHistory = NULL,
+        .ptrCsxTouchBuffer = NULL,
+        .ptrCsdTouchBuffer = NULL,
+        .ptrGestureConfig = NULL,
+        .ptrGestureContext = NULL,
+        .ballisticConfig = {
+            .accelCoeff = 9u,
+            .speedCoeff = 2u,
+            .divisorValue = 4u,
+            .speedThresholdX = 3u,
+            .speedThresholdY = 4u,
+        },
+        .ptrBallisticContext = NULL,
+        .aiirConfig = {
+            .maxK = 60u,
+            .minK = 1u,
+            .noMovTh = 3u,
+            .littleMovTh = 7u,
+            .largeMovTh = 12u,
+            .divVal = 64u,
+        },
+        .advConfig = {
+            .penultimateTh = 100u,
+            .virtualSnsTh = 100u,
+            .crossCouplingTh = 5u,
+        },
+        .posFilterConfig = 0u,
+        .rawFilterConfig = 0u,
+        #if (CY_CAPSENSE_MW_VERSION >= 300)
+            .senseMethod = CY_CAPSENSE_CSD_GROUP,
+        #else
+            .senseMethod = CY_CAPSENSE_SENSE_METHOD_CSD_E,
+        #endif
+        .wdType = CY_CAPSENSE_WD_LINEAR_SLIDER_E,
+    },
+};
+
+cy_stc_capsense_tuner_t cy_capsense_tuner =
+{
+    .commonContext = {
+        #if (CY_CAPSENSE_MW_VERSION < 300)
+            .configId = 0xa368,
+        #else
+            .configId = 0xa369,
+        #endif
+
+        .tunerCmd = 0u,
+        .scanCounter = 0u,
+        .tunerSt = 0u,
+        .initDone = 0u,
+        #if (CY_CAPSENSE_MW_VERSION < 300)
+            .ptrSSCallback = NULL,
+            .ptrEOSCallback = NULL,
+            .ptrTunerSendCallback = NULL,
+            .ptrTunerReceiveCallback = NULL,
+        #endif
+        .status = 0u,
+        .timestampInterval = 1u,
+        .timestamp = 0u,
+        .modCsdClk = 2u,
+        .modCsxClk = 2u,
+        .tunerCnt = 0u,
+    },
+    .widgetContext = {
+        { /* Button0 */
+            .fingerCap = 160u,
+            .sigPFC = 0u,
+            .resolution = 12u,
+            .maxRawCount = 0u,
+            #if (CY_CAPSENSE_MW_VERSION >= 300)
+                .maxRawCountRow = 0u,
+            #endif
+            .fingerTh = 100u,
+            .proxTh = 200u,
+            .lowBslnRst = 30u,
+            .snsClk = 16u,
+            .rowSnsClk = 16u,
+            .gestureDetected = 0u,
+            .gestureDirection = 0u,
+            .xDelta = 0u,
+            .yDelta = 0u,
+            .noiseTh = 40u,
+            .nNoiseTh = 40u,
+            .hysteresis = 10u,
+            .onDebounce = 3u,
+            .snsClkSource = CY_CAPSENSE_CLK_SOURCE_AUTO_MASK,
+            .idacMod = { 32u, 32u, 32u, },
+            .idacGainIndex = 4u,
+            .rowIdacMod = { 32u, 32u, 32u, },
+            .bslnCoeff = 1u,
+            .status = 0u,
+            .wdTouch = {
+                .ptrPosition = NULL,
+                .numPosition = 0,
+            },
+        },
+        { /* Button1 */
+            .fingerCap = 160u,
+            .sigPFC = 0u,
+            .resolution = 12u,
+            .maxRawCount = 0u,
+            #if (CY_CAPSENSE_MW_VERSION >= 300)
+                .maxRawCountRow = 0u,
+            #endif
+            .fingerTh = 100u,
+            .proxTh = 200u,
+            .lowBslnRst = 30u,
+            .snsClk = 16u,
+            .rowSnsClk = 16u,
+            .gestureDetected = 0u,
+            .gestureDirection = 0u,
+            .xDelta = 0u,
+            .yDelta = 0u,
+            .noiseTh = 40u,
+            .nNoiseTh = 40u,
+            .hysteresis = 10u,
+            .onDebounce = 3u,
+            .snsClkSource = CY_CAPSENSE_CLK_SOURCE_AUTO_MASK,
+            .idacMod = { 32u, 32u, 32u, },
+            .idacGainIndex = 4u,
+            .rowIdacMod = { 32u, 32u, 32u, },
+            .bslnCoeff = 1u,
+            .status = 0u,
+            .wdTouch = {
+                .ptrPosition = NULL,
+                .numPosition = 0,
+            },
+        },
+        { /* LinearSlider0 */
+            .fingerCap = 160u,
+            .sigPFC = 0u,
+            .resolution = 12u,
+            .maxRawCount = 0u,
+            #if (CY_CAPSENSE_MW_VERSION >= 300)
+                .maxRawCountRow = 0u,
+            #endif
+            .fingerTh = 100u,
+            .proxTh = 200u,
+            .lowBslnRst = 30u,
+            .snsClk = 16u,
+            .rowSnsClk = 16u,
+            .gestureDetected = 0u,
+            .gestureDirection = 0u,
+            .xDelta = 0u,
+            .yDelta = 0u,
+            .noiseTh = 40u,
+            .nNoiseTh = 40u,
+            .hysteresis = 10u,
+            .onDebounce = 3u,
+            .snsClkSource = CY_CAPSENSE_CLK_SOURCE_AUTO_MASK,
+            .idacMod = { 32u, 32u, 32u, },
+            .idacGainIndex = 4u,
+            .rowIdacMod = { 32u, 32u, 32u, },
+            .bslnCoeff = 1u,
+            .status = 0u,
+            .wdTouch = {
+                .ptrPosition = &cy_capsense_tuner.position[0u],
+                .numPosition = 1,
+            },
+        },
+    },
+    .sensorContext = {
+        { /* Button0_Sns0 */
+            .raw = 0u,
+            .bsln = 0u,
+            .diff = 0u,
+            .status = 0u,
+            .negBslnRstCnt = 0u,
+            .idacComp = 32u,
+            .bslnExt = 0u,
+        },
+        { /* Button1_Sns0 */
+            .raw = 0u,
+            .bsln = 0u,
+            .diff = 0u,
+            .status = 0u,
+            .negBslnRstCnt = 0u,
+            .idacComp = 32u,
+            .bslnExt = 0u,
+        },
+        { /* LinearSlider0_Sns0 */
+            .raw = 0u,
+            .bsln = 0u,
+            .diff = 0u,
+            .status = 0u,
+            .negBslnRstCnt = 0u,
+            .idacComp = 32u,
+            .bslnExt = 0u,
+        },
+        { /* LinearSlider0_Sns1 */
+            .raw = 0u,
+            .bsln = 0u,
+            .diff = 0u,
+            .status = 0u,
+            .negBslnRstCnt = 0u,
+            .idacComp = 32u,
+            .bslnExt = 0u,
+        },
+        { /* LinearSlider0_Sns2 */
+            .raw = 0u,
+            .bsln = 0u,
+            .diff = 0u,
+            .status = 0u,
+            .negBslnRstCnt = 0u,
+            .idacComp = 32u,
+            .bslnExt = 0u,
+        },
+        { /* LinearSlider0_Sns3 */
+            .raw = 0u,
+            .bsln = 0u,
+            .diff = 0u,
+            .status = 0u,
+            .negBslnRstCnt = 0u,
+            .idacComp = 32u,
+            .bslnExt = 0u,
+        },
+        { /* LinearSlider0_Sns4 */
+            .raw = 0u,
+            .bsln = 0u,
+            .diff = 0u,
+            .status = 0u,
+            .negBslnRstCnt = 0u,
+            .idacComp = 32u,
+            .bslnExt = 0u,
+        },
+    },
+    .position = {
+        { /* LinearSlider0 */
+            .x = 0u,
+            .y = 0u,
+            .z = 0u,
+            .id = 0u,
+        },
+    },
+};
+
+#if (CY_CAPSENSE_BIST_SUPPORTED)
+#if (CY_CAPSENSE_BIST_EN != 0)
+cy_stc_capsense_bist_context_t cy_capsense_bist_context =
+{
+};
+#endif
+#endif
+
+cy_stc_capsense_context_t cy_capsense_context =
+{
+    .ptrCommonConfig = &cy_capsense_commonConfig,
+    .ptrCommonContext = &cy_capsense_tuner.commonContext,
+    .ptrInternalContext = &cy_capsense_internalContext,
+    .ptrWdConfig = &cy_capsense_widgetConfig[0u],
+    .ptrWdContext = &cy_capsense_tuner.widgetContext[0u],
+    .ptrPinConfig = &cy_capsense_pinConfig[0u],
+    .ptrShieldPinConfig = NULL,
+    .ptrActiveScanSns = &cy_capsense_activeScanSns,
+    #if (CY_CAPSENSE_MW_VERSION < 300)
+        .ptrFptrConfig = (const void *) &cy_capsense_fptrConfig,
+    #endif
+    #if (CY_CAPSENSE_BIST_SUPPORTED)
+        .ptrBistContext = NULL,
+    #endif
+};
+
+#endif /* CY_CAPSENSE_CORE == __CORTEX_M */
+
+#endif /* !defined(CY_DISABLE_CAPSENSE) */
+
+/* [] END OF FILE */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h

@@ -0,0 +1,2264 @@
+/*******************************************************************************
+* File Name: cycfg_capsense.h
+*
+* Description:
+* CapSense Middleware configuration
+* This file should not be modified. It was automatically generated by
+* CapSense Configurator 4.0.0.5943
+*
+********************************************************************************
+* Copyright 2021, Cypress Semiconductor Corporation (an Infineon company)
+* or an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#if !defined(CYCFG_CAPSENSE_H)
+#define CYCFG_CAPSENSE_H
+
+#include <stddef.h>
+#include "cy_device_headers.h"
+#include "cycfg_peripherals.h"
+#include "cycfg_capsense_defines.h"
+
+#define CY_CAPSENSE_CFG_TOOL_VERSION              (400)
+
+#if !defined(CY_DISABLE_CAPSENSE)
+
+#if (CY_CAPSENSE_CORE == __CORTEX_M)
+
+
+#if !defined(Cmod_PORT) || !defined(Cmod_PIN) || !defined(Cmod_PORT_NUM)
+#error Cmod Capacitor is not assigned: missing #define Cmod_PORT, #define Cmod_PIN, #define Cmod_PORT_NUM
+#endif
+
+#if !defined(Button0_Sns0_PORT) || !defined(Button0_Sns0_PIN)
+#error Button0_Sns0 Sensor is not assigned: missing #define Button0_Sns0_PORT, #define Button0_Sns0_PIN
+#endif
+
+#if !defined(Button1_Sns0_PORT) || !defined(Button1_Sns0_PIN)
+#error Button1_Sns0 Sensor is not assigned: missing #define Button1_Sns0_PORT, #define Button1_Sns0_PIN
+#endif
+
+#if !defined(LinearSlider0_Sns0_PORT) || !defined(LinearSlider0_Sns0_PIN)
+#error LinearSlider0_Sns0 Sensor is not assigned: missing #define LinearSlider0_Sns0_PORT, #define LinearSlider0_Sns0_PIN
+#endif
+
+#if !defined(LinearSlider0_Sns1_PORT) || !defined(LinearSlider0_Sns1_PIN)
+#error LinearSlider0_Sns1 Sensor is not assigned: missing #define LinearSlider0_Sns1_PORT, #define LinearSlider0_Sns1_PIN
+#endif
+
+#if !defined(LinearSlider0_Sns2_PORT) || !defined(LinearSlider0_Sns2_PIN)
+#error LinearSlider0_Sns2 Sensor is not assigned: missing #define LinearSlider0_Sns2_PORT, #define LinearSlider0_Sns2_PIN
+#endif
+
+#if !defined(LinearSlider0_Sns3_PORT) || !defined(LinearSlider0_Sns3_PIN)
+#error LinearSlider0_Sns3 Sensor is not assigned: missing #define LinearSlider0_Sns3_PORT, #define LinearSlider0_Sns3_PIN
+#endif
+
+#if !defined(LinearSlider0_Sns4_PORT) || !defined(LinearSlider0_Sns4_PIN)
+#error LinearSlider0_Sns4 Sensor is not assigned: missing #define LinearSlider0_Sns4_PORT, #define LinearSlider0_Sns4_PIN
+#endif
+
+#if !defined(CY_CAPSENSE_CPU_CLK)
+#error CPU clock frequency is not set: missing #define CY_CAPSENSE_CPU_CLK
+#endif
+
+#if !defined(CY_CAPSENSE_PERI_CLK)
+#error Peripheral clock core is not set: missing #define CY_CAPSENSE_PERI_CLK
+#endif
+
+#if !defined(CY_CAPSENSE_VDDA_MV)
+#error VDDA voltage is not set: missing #define CY_CAPSENSE_VDDA_MV
+#endif
+
+#if !defined(CY_CAPSENSE_PERI_DIV_TYPE)
+#error Peripheral clock divider type is not set: missing #define CY_CAPSENSE_PERI_DIV_TYPE
+#endif
+
+#if !defined(CY_CAPSENSE_PERI_DIV_INDEX)
+#error Peripheral clock divider index is not set: missing #define CY_CAPSENSE_PERI_DIV_INDEX
+#endif
+
+
+
+#include "cy_capsense.h"
+
+/* Supported CapSense Middleware version */
+#define CY_CAPSENSE_MW_VERSION_REQUIRED           (200)
+
+#if !defined (CY_CAPSENSE_MW_VERSION)
+    #if (CY_CAPSENSE_MW_VERSION_MAJOR == 2)
+        #define CY_CAPSENSE_MW_VERSION            (200)
+    #elif (CY_CAPSENSE_MW_VERSION_MAJOR == 1)
+        #define CY_CAPSENSE_MW_VERSION            (100)
+    #else
+        #define CY_CAPSENSE_MW_VERSION            (100)
+    #endif
+#endif
+
+/* Check the used Middleware version */
+#if (CY_CAPSENSE_MW_VERSION_REQUIRED > CY_CAPSENSE_MW_VERSION)
+    #error The CapSense Configurator requires a newer version of the CapSense Middleware. Update the CapSense Middleware in your project.
+#endif
+
+#define CY_CAPSENSE_BIST_SUPPORTED                (CY_CAPSENSE_MW_VERSION >= 210)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/* Widget names */
+#define CY_CAPSENSE_BUTTON0_WDGT_ID                                              (0u)
+#define CY_CAPSENSE_BUTTON1_WDGT_ID                                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_WDGT_ID                                        (2u)
+
+/* Button0 sensor names */
+#define CY_CAPSENSE_BUTTON0_SNS0_ID                                              (0u)
+
+/* Button1 sensor names */
+#define CY_CAPSENSE_BUTTON1_SNS0_ID                                              (0u)
+
+/* LinearSlider0 sensor names */
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_ID                                        (0u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_ID                                        (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_ID                                        (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_ID                                        (3u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_ID                                        (4u)
+
+
+typedef struct {
+    cy_stc_capsense_common_context_t commonContext;
+    cy_stc_capsense_widget_context_t widgetContext[3];
+    cy_stc_capsense_sensor_context_t sensorContext[7];
+    cy_stc_capsense_position_t position[1];
+} cy_stc_capsense_tuner_t;
+
+extern cy_stc_capsense_tuner_t cy_capsense_tuner;
+
+extern cy_stc_capsense_context_t cy_capsense_context;
+
+/* RAM Data structure register definitions */
+#if (CY_CAPSENSE_MW_VERSION < 300)
+#define CY_CAPSENSE_CONFIG_ID_VALUE                                              (cy_capsense_tuner.commonContext.configId)
+#define CY_CAPSENSE_CONFIG_ID_OFFSET                                             (0u)
+#define CY_CAPSENSE_CONFIG_ID_SIZE                                               (2u)
+#define CY_CAPSENSE_CONFIG_ID_PARAM_ID                                           (0x02000000u)
+
+#define CY_CAPSENSE_TUNER_CMD_VALUE                                              (cy_capsense_tuner.commonContext.tunerCmd)
+#define CY_CAPSENSE_TUNER_CMD_OFFSET                                             (2u)
+#define CY_CAPSENSE_TUNER_CMD_SIZE                                               (2u)
+#define CY_CAPSENSE_TUNER_CMD_PARAM_ID                                           (0x02000002u)
+
+#define CY_CAPSENSE_SCAN_COUNTER_VALUE                                           (cy_capsense_tuner.commonContext.scanCounter)
+#define CY_CAPSENSE_SCAN_COUNTER_OFFSET                                          (4u)
+#define CY_CAPSENSE_SCAN_COUNTER_SIZE                                            (2u)
+#define CY_CAPSENSE_SCAN_COUNTER_PARAM_ID                                        (0x02000004u)
+
+#define CY_CAPSENSE_TUNER_ST_VALUE                                               (cy_capsense_tuner.commonContext.tunerSt)
+#define CY_CAPSENSE_TUNER_ST_OFFSET                                              (6u)
+#define CY_CAPSENSE_TUNER_ST_SIZE                                                (1u)
+#define CY_CAPSENSE_TUNER_ST_PARAM_ID                                            (0x01000006u)
+
+#define CY_CAPSENSE_INITDONE_VALUE                                               (cy_capsense_tuner.commonContext.initDone)
+#define CY_CAPSENSE_INITDONE_OFFSET                                              (7u)
+#define CY_CAPSENSE_INITDONE_SIZE                                                (1u)
+#define CY_CAPSENSE_INITDONE_PARAM_ID                                            (0x01000007u)
+
+#define CY_CAPSENSE_PTRSSCALLBACK_VALUE                                          (cy_capsense_tuner.commonContext.ptrSSCallback)
+#define CY_CAPSENSE_PTRSSCALLBACK_OFFSET                                         (8u)
+#define CY_CAPSENSE_PTRSSCALLBACK_SIZE                                           (4u)
+#define CY_CAPSENSE_PTRSSCALLBACK_PARAM_ID                                       (0x03000008u)
+
+#define CY_CAPSENSE_PTREOSCALLBACK_VALUE                                         (cy_capsense_tuner.commonContext.ptrEOSCallback)
+#define CY_CAPSENSE_PTREOSCALLBACK_OFFSET                                        (12u)
+#define CY_CAPSENSE_PTREOSCALLBACK_SIZE                                          (4u)
+#define CY_CAPSENSE_PTREOSCALLBACK_PARAM_ID                                      (0x0300000cu)
+
+#define CY_CAPSENSE_PTRTUNERSENDCALLBACK_VALUE                                   (cy_capsense_tuner.commonContext.ptrTunerSendCallback)
+#define CY_CAPSENSE_PTRTUNERSENDCALLBACK_OFFSET                                  (16u)
+#define CY_CAPSENSE_PTRTUNERSENDCALLBACK_SIZE                                    (4u)
+#define CY_CAPSENSE_PTRTUNERSENDCALLBACK_PARAM_ID                                (0x03000010u)
+
+#define CY_CAPSENSE_PTRTUNERRECEIVECALLBACK_VALUE                                (cy_capsense_tuner.commonContext.ptrTunerReceiveCallback)
+#define CY_CAPSENSE_PTRTUNERRECEIVECALLBACK_OFFSET                               (20u)
+#define CY_CAPSENSE_PTRTUNERRECEIVECALLBACK_SIZE                                 (4u)
+#define CY_CAPSENSE_PTRTUNERRECEIVECALLBACK_PARAM_ID                             (0x03000014u)
+
+#define CY_CAPSENSE_STATUS_VALUE                                                 (cy_capsense_tuner.commonContext.status)
+#define CY_CAPSENSE_STATUS_OFFSET                                                (24u)
+#define CY_CAPSENSE_STATUS_SIZE                                                  (4u)
+#define CY_CAPSENSE_STATUS_PARAM_ID                                              (0x03000018u)
+
+#define CY_CAPSENSE_TIMESTAMPINTERVAL_VALUE                                      (cy_capsense_tuner.commonContext.timestampInterval)
+#define CY_CAPSENSE_TIMESTAMPINTERVAL_OFFSET                                     (28u)
+#define CY_CAPSENSE_TIMESTAMPINTERVAL_SIZE                                       (4u)
+#define CY_CAPSENSE_TIMESTAMPINTERVAL_PARAM_ID                                   (0x0300001cu)
+
+#define CY_CAPSENSE_TIMESTAMP_VALUE                                              (cy_capsense_tuner.commonContext.timestamp)
+#define CY_CAPSENSE_TIMESTAMP_OFFSET                                             (32u)
+#define CY_CAPSENSE_TIMESTAMP_SIZE                                               (4u)
+#define CY_CAPSENSE_TIMESTAMP_PARAM_ID                                           (0x03000020u)
+
+#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_VALUE                                    (cy_capsense_tuner.commonContext.modCsdClk)
+#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_OFFSET                                   (36u)
+#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_SIZE                                     (1u)
+#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_PARAM_ID                                 (0x01000024u)
+
+#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_VALUE                                    (cy_capsense_tuner.commonContext.modCsxClk)
+#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_OFFSET                                   (37u)
+#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_SIZE                                     (1u)
+#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_PARAM_ID                                 (0x01000025u)
+
+#define CY_CAPSENSE_TUNER_CNT_VALUE                                              (cy_capsense_tuner.commonContext.tunerCnt)
+#define CY_CAPSENSE_TUNER_CNT_OFFSET                                             (38u)
+#define CY_CAPSENSE_TUNER_CNT_SIZE                                               (1u)
+#define CY_CAPSENSE_TUNER_CNT_PARAM_ID                                           (0x01000026u)
+
+#define CY_CAPSENSE_BUTTON0_FINGER_CP_VALUE                                      (cy_capsense_tuner.widgetContext[0].fingerCap)
+#define CY_CAPSENSE_BUTTON0_FINGER_CP_OFFSET                                     (40u)
+#define CY_CAPSENSE_BUTTON0_FINGER_CP_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON0_FINGER_CP_PARAM_ID                                   (0x06000028u)
+
+#define CY_CAPSENSE_BUTTON0_SIGPFC_VALUE                                         (cy_capsense_tuner.widgetContext[0].sigPFC)
+#define CY_CAPSENSE_BUTTON0_SIGPFC_OFFSET                                        (42u)
+#define CY_CAPSENSE_BUTTON0_SIGPFC_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON0_SIGPFC_PARAM_ID                                      (0x0600002au)
+
+#define CY_CAPSENSE_BUTTON0_RESOLUTION_VALUE                                     (cy_capsense_tuner.widgetContext[0].resolution)
+#define CY_CAPSENSE_BUTTON0_RESOLUTION_OFFSET                                    (44u)
+#define CY_CAPSENSE_BUTTON0_RESOLUTION_SIZE                                      (2u)
+#define CY_CAPSENSE_BUTTON0_RESOLUTION_PARAM_ID                                  (0x0600002cu)
+
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_VALUE                                    (cy_capsense_tuner.widgetContext[0].maxRawCount)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_OFFSET                                   (46u)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_SIZE                                     (2u)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_PARAM_ID                                 (0x0200002eu)
+
+#define CY_CAPSENSE_BUTTON0_FINGER_TH_VALUE                                      (cy_capsense_tuner.widgetContext[0].fingerTh)
+#define CY_CAPSENSE_BUTTON0_FINGER_TH_OFFSET                                     (48u)
+#define CY_CAPSENSE_BUTTON0_FINGER_TH_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON0_FINGER_TH_PARAM_ID                                   (0x02000030u)
+
+#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_VALUE                                  (cy_capsense_tuner.widgetContext[0].proxTh)
+#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_OFFSET                                 (50u)
+#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_SIZE                                   (2u)
+#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_PARAM_ID                               (0x02000032u)
+
+#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_VALUE                                   (cy_capsense_tuner.widgetContext[0].lowBslnRst)
+#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_OFFSET                                  (52u)
+#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_SIZE                                    (2u)
+#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_PARAM_ID                                (0x06000034u)
+
+#define CY_CAPSENSE_BUTTON0_SNS_CLK_VALUE                                        (cy_capsense_tuner.widgetContext[0].snsClk)
+#define CY_CAPSENSE_BUTTON0_SNS_CLK_OFFSET                                       (54u)
+#define CY_CAPSENSE_BUTTON0_SNS_CLK_SIZE                                         (2u)
+#define CY_CAPSENSE_BUTTON0_SNS_CLK_PARAM_ID                                     (0x06000036u)
+
+#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_VALUE                                    (cy_capsense_tuner.widgetContext[0].rowSnsClk)
+#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_OFFSET                                   (56u)
+#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_SIZE                                     (2u)
+#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_PARAM_ID                                 (0x06000038u)
+
+#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_VALUE                               (cy_capsense_tuner.widgetContext[0].gestureDetected)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_OFFSET                              (58u)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_SIZE                                (2u)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_PARAM_ID                            (0x0200003au)
+
+#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_VALUE                              (cy_capsense_tuner.widgetContext[0].gestureDirection)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_OFFSET                             (60u)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_SIZE                               (2u)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_PARAM_ID                           (0x0200003cu)
+
+#define CY_CAPSENSE_BUTTON0_XDELTA_VALUE                                         (cy_capsense_tuner.widgetContext[0].xDelta)
+#define CY_CAPSENSE_BUTTON0_XDELTA_OFFSET                                        (62u)
+#define CY_CAPSENSE_BUTTON0_XDELTA_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON0_XDELTA_PARAM_ID                                      (0x0200003eu)
+
+#define CY_CAPSENSE_BUTTON0_YDELTA_VALUE                                         (cy_capsense_tuner.widgetContext[0].yDelta)
+#define CY_CAPSENSE_BUTTON0_YDELTA_OFFSET                                        (64u)
+#define CY_CAPSENSE_BUTTON0_YDELTA_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON0_YDELTA_PARAM_ID                                      (0x02000040u)
+
+#define CY_CAPSENSE_BUTTON0_NOISE_TH_VALUE                                       (cy_capsense_tuner.widgetContext[0].noiseTh)
+#define CY_CAPSENSE_BUTTON0_NOISE_TH_OFFSET                                      (66u)
+#define CY_CAPSENSE_BUTTON0_NOISE_TH_SIZE                                        (1u)
+#define CY_CAPSENSE_BUTTON0_NOISE_TH_PARAM_ID                                    (0x01000042u)
+
+#define CY_CAPSENSE_BUTTON0_NNOISE_TH_VALUE                                      (cy_capsense_tuner.widgetContext[0].nNoiseTh)
+#define CY_CAPSENSE_BUTTON0_NNOISE_TH_OFFSET                                     (67u)
+#define CY_CAPSENSE_BUTTON0_NNOISE_TH_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON0_NNOISE_TH_PARAM_ID                                   (0x01000043u)
+
+#define CY_CAPSENSE_BUTTON0_HYSTERESIS_VALUE                                     (cy_capsense_tuner.widgetContext[0].hysteresis)
+#define CY_CAPSENSE_BUTTON0_HYSTERESIS_OFFSET                                    (68u)
+#define CY_CAPSENSE_BUTTON0_HYSTERESIS_SIZE                                      (1u)
+#define CY_CAPSENSE_BUTTON0_HYSTERESIS_PARAM_ID                                  (0x01000044u)
+
+#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_VALUE                                    (cy_capsense_tuner.widgetContext[0].onDebounce)
+#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_OFFSET                                   (69u)
+#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_SIZE                                     (1u)
+#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_PARAM_ID                                 (0x05000045u)
+
+#define CY_CAPSENSE_BUTTON0_SNS_CLK_SOURCE_VALUE                                 (cy_capsense_tuner.widgetContext[0].snsClkSource)
+#define CY_CAPSENSE_BUTTON0_SNS_CLK_SOURCE_OFFSET                                (70u)
+#define CY_CAPSENSE_BUTTON0_SNS_CLK_SOURCE_SIZE                                  (1u)
+#define CY_CAPSENSE_BUTTON0_SNS_CLK_SOURCE_PARAM_ID                              (0x05000046u)
+
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_VALUE                                      (cy_capsense_tuner.widgetContext[0].idacMod[0])
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_OFFSET                                     (71u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_PARAM_ID                                   (0x05000047u)
+
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_VALUE                                      (cy_capsense_tuner.widgetContext[0].idacMod[1])
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_OFFSET                                     (72u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_PARAM_ID                                   (0x05000048u)
+
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_VALUE                                      (cy_capsense_tuner.widgetContext[0].idacMod[2])
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_OFFSET                                     (73u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_PARAM_ID                                   (0x05000049u)
+
+#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_VALUE                                (cy_capsense_tuner.widgetContext[0].idacGainIndex)
+#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_OFFSET                               (74u)
+#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_SIZE                                 (1u)
+#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_PARAM_ID                             (0x0500004au)
+
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_VALUE                                  (cy_capsense_tuner.widgetContext[0].rowIdacMod[0])
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_OFFSET                                 (75u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_PARAM_ID                               (0x0500004bu)
+
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_VALUE                                  (cy_capsense_tuner.widgetContext[0].rowIdacMod[1])
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_OFFSET                                 (76u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_PARAM_ID                               (0x0500004cu)
+
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_VALUE                                  (cy_capsense_tuner.widgetContext[0].rowIdacMod[2])
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_OFFSET                                 (77u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_PARAM_ID                               (0x0500004du)
+
+#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_VALUE                               (cy_capsense_tuner.widgetContext[0].bslnCoeff)
+#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_OFFSET                              (78u)
+#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_SIZE                                (1u)
+#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_PARAM_ID                            (0x0100004eu)
+
+#define CY_CAPSENSE_BUTTON0_STATUS_VALUE                                         (cy_capsense_tuner.widgetContext[0].status)
+#define CY_CAPSENSE_BUTTON0_STATUS_OFFSET                                        (79u)
+#define CY_CAPSENSE_BUTTON0_STATUS_SIZE                                          (1u)
+#define CY_CAPSENSE_BUTTON0_STATUS_PARAM_ID                                      (0x0100004fu)
+
+#define CY_CAPSENSE_BUTTON0_PTRPOSITION_VALUE                                    (cy_capsense_tuner.widgetContext[0].wdTouch.ptrPosition)
+#define CY_CAPSENSE_BUTTON0_PTRPOSITION_OFFSET                                   (80u)
+#define CY_CAPSENSE_BUTTON0_PTRPOSITION_SIZE                                     (4u)
+#define CY_CAPSENSE_BUTTON0_PTRPOSITION_PARAM_ID                                 (0x03000050u)
+
+#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_VALUE                                  (cy_capsense_tuner.widgetContext[0].wdTouch.numPosition)
+#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_OFFSET                                 (84u)
+#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_PARAM_ID                               (0x01000054u)
+
+#define CY_CAPSENSE_BUTTON1_FINGER_CP_VALUE                                      (cy_capsense_tuner.widgetContext[1].fingerCap)
+#define CY_CAPSENSE_BUTTON1_FINGER_CP_OFFSET                                     (88u)
+#define CY_CAPSENSE_BUTTON1_FINGER_CP_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON1_FINGER_CP_PARAM_ID                                   (0x06010058u)
+
+#define CY_CAPSENSE_BUTTON1_SIGPFC_VALUE                                         (cy_capsense_tuner.widgetContext[1].sigPFC)
+#define CY_CAPSENSE_BUTTON1_SIGPFC_OFFSET                                        (90u)
+#define CY_CAPSENSE_BUTTON1_SIGPFC_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON1_SIGPFC_PARAM_ID                                      (0x0601005au)
+
+#define CY_CAPSENSE_BUTTON1_RESOLUTION_VALUE                                     (cy_capsense_tuner.widgetContext[1].resolution)
+#define CY_CAPSENSE_BUTTON1_RESOLUTION_OFFSET                                    (92u)
+#define CY_CAPSENSE_BUTTON1_RESOLUTION_SIZE                                      (2u)
+#define CY_CAPSENSE_BUTTON1_RESOLUTION_PARAM_ID                                  (0x0601005cu)
+
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_VALUE                                    (cy_capsense_tuner.widgetContext[1].maxRawCount)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_OFFSET                                   (94u)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_SIZE                                     (2u)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_PARAM_ID                                 (0x0201005eu)
+
+#define CY_CAPSENSE_BUTTON1_FINGER_TH_VALUE                                      (cy_capsense_tuner.widgetContext[1].fingerTh)
+#define CY_CAPSENSE_BUTTON1_FINGER_TH_OFFSET                                     (96u)
+#define CY_CAPSENSE_BUTTON1_FINGER_TH_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON1_FINGER_TH_PARAM_ID                                   (0x02010060u)
+
+#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_VALUE                                  (cy_capsense_tuner.widgetContext[1].proxTh)
+#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_OFFSET                                 (98u)
+#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_SIZE                                   (2u)
+#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_PARAM_ID                               (0x02010062u)
+
+#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_VALUE                                   (cy_capsense_tuner.widgetContext[1].lowBslnRst)
+#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_OFFSET                                  (100u)
+#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_SIZE                                    (2u)
+#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_PARAM_ID                                (0x06010064u)
+
+#define CY_CAPSENSE_BUTTON1_SNS_CLK_VALUE                                        (cy_capsense_tuner.widgetContext[1].snsClk)
+#define CY_CAPSENSE_BUTTON1_SNS_CLK_OFFSET                                       (102u)
+#define CY_CAPSENSE_BUTTON1_SNS_CLK_SIZE                                         (2u)
+#define CY_CAPSENSE_BUTTON1_SNS_CLK_PARAM_ID                                     (0x06010066u)
+
+#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_VALUE                                    (cy_capsense_tuner.widgetContext[1].rowSnsClk)
+#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_OFFSET                                   (104u)
+#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_SIZE                                     (2u)
+#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_PARAM_ID                                 (0x06010068u)
+
+#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_VALUE                               (cy_capsense_tuner.widgetContext[1].gestureDetected)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_OFFSET                              (106u)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_SIZE                                (2u)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_PARAM_ID                            (0x0201006au)
+
+#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_VALUE                              (cy_capsense_tuner.widgetContext[1].gestureDirection)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_OFFSET                             (108u)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_SIZE                               (2u)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_PARAM_ID                           (0x0201006cu)
+
+#define CY_CAPSENSE_BUTTON1_XDELTA_VALUE                                         (cy_capsense_tuner.widgetContext[1].xDelta)
+#define CY_CAPSENSE_BUTTON1_XDELTA_OFFSET                                        (110u)
+#define CY_CAPSENSE_BUTTON1_XDELTA_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON1_XDELTA_PARAM_ID                                      (0x0201006eu)
+
+#define CY_CAPSENSE_BUTTON1_YDELTA_VALUE                                         (cy_capsense_tuner.widgetContext[1].yDelta)
+#define CY_CAPSENSE_BUTTON1_YDELTA_OFFSET                                        (112u)
+#define CY_CAPSENSE_BUTTON1_YDELTA_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON1_YDELTA_PARAM_ID                                      (0x02010070u)
+
+#define CY_CAPSENSE_BUTTON1_NOISE_TH_VALUE                                       (cy_capsense_tuner.widgetContext[1].noiseTh)
+#define CY_CAPSENSE_BUTTON1_NOISE_TH_OFFSET                                      (114u)
+#define CY_CAPSENSE_BUTTON1_NOISE_TH_SIZE                                        (1u)
+#define CY_CAPSENSE_BUTTON1_NOISE_TH_PARAM_ID                                    (0x01010072u)
+
+#define CY_CAPSENSE_BUTTON1_NNOISE_TH_VALUE                                      (cy_capsense_tuner.widgetContext[1].nNoiseTh)
+#define CY_CAPSENSE_BUTTON1_NNOISE_TH_OFFSET                                     (115u)
+#define CY_CAPSENSE_BUTTON1_NNOISE_TH_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON1_NNOISE_TH_PARAM_ID                                   (0x01010073u)
+
+#define CY_CAPSENSE_BUTTON1_HYSTERESIS_VALUE                                     (cy_capsense_tuner.widgetContext[1].hysteresis)
+#define CY_CAPSENSE_BUTTON1_HYSTERESIS_OFFSET                                    (116u)
+#define CY_CAPSENSE_BUTTON1_HYSTERESIS_SIZE                                      (1u)
+#define CY_CAPSENSE_BUTTON1_HYSTERESIS_PARAM_ID                                  (0x01010074u)
+
+#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_VALUE                                    (cy_capsense_tuner.widgetContext[1].onDebounce)
+#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_OFFSET                                   (117u)
+#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_SIZE                                     (1u)
+#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_PARAM_ID                                 (0x05010075u)
+
+#define CY_CAPSENSE_BUTTON1_SNS_CLK_SOURCE_VALUE                                 (cy_capsense_tuner.widgetContext[1].snsClkSource)
+#define CY_CAPSENSE_BUTTON1_SNS_CLK_SOURCE_OFFSET                                (118u)
+#define CY_CAPSENSE_BUTTON1_SNS_CLK_SOURCE_SIZE                                  (1u)
+#define CY_CAPSENSE_BUTTON1_SNS_CLK_SOURCE_PARAM_ID                              (0x05010076u)
+
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_VALUE                                      (cy_capsense_tuner.widgetContext[1].idacMod[0])
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_OFFSET                                     (119u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_PARAM_ID                                   (0x05010077u)
+
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_VALUE                                      (cy_capsense_tuner.widgetContext[1].idacMod[1])
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_OFFSET                                     (120u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_PARAM_ID                                   (0x05010078u)
+
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_VALUE                                      (cy_capsense_tuner.widgetContext[1].idacMod[2])
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_OFFSET                                     (121u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_PARAM_ID                                   (0x05010079u)
+
+#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_VALUE                                (cy_capsense_tuner.widgetContext[1].idacGainIndex)
+#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_OFFSET                               (122u)
+#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_SIZE                                 (1u)
+#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_PARAM_ID                             (0x0501007au)
+
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_VALUE                                  (cy_capsense_tuner.widgetContext[1].rowIdacMod[0])
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_OFFSET                                 (123u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_PARAM_ID                               (0x0501007bu)
+
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_VALUE                                  (cy_capsense_tuner.widgetContext[1].rowIdacMod[1])
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_OFFSET                                 (124u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_PARAM_ID                               (0x0501007cu)
+
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_VALUE                                  (cy_capsense_tuner.widgetContext[1].rowIdacMod[2])
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_OFFSET                                 (125u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_PARAM_ID                               (0x0501007du)
+
+#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_VALUE                               (cy_capsense_tuner.widgetContext[1].bslnCoeff)
+#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_OFFSET                              (126u)
+#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_SIZE                                (1u)
+#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_PARAM_ID                            (0x0101007eu)
+
+#define CY_CAPSENSE_BUTTON1_STATUS_VALUE                                         (cy_capsense_tuner.widgetContext[1].status)
+#define CY_CAPSENSE_BUTTON1_STATUS_OFFSET                                        (127u)
+#define CY_CAPSENSE_BUTTON1_STATUS_SIZE                                          (1u)
+#define CY_CAPSENSE_BUTTON1_STATUS_PARAM_ID                                      (0x0101007fu)
+
+#define CY_CAPSENSE_BUTTON1_PTRPOSITION_VALUE                                    (cy_capsense_tuner.widgetContext[1].wdTouch.ptrPosition)
+#define CY_CAPSENSE_BUTTON1_PTRPOSITION_OFFSET                                   (128u)
+#define CY_CAPSENSE_BUTTON1_PTRPOSITION_SIZE                                     (4u)
+#define CY_CAPSENSE_BUTTON1_PTRPOSITION_PARAM_ID                                 (0x03010080u)
+
+#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_VALUE                                  (cy_capsense_tuner.widgetContext[1].wdTouch.numPosition)
+#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_OFFSET                                 (132u)
+#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_PARAM_ID                               (0x01010084u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_VALUE                                (cy_capsense_tuner.widgetContext[2].fingerCap)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_OFFSET                               (136u)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_PARAM_ID                             (0x06020088u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_VALUE                                   (cy_capsense_tuner.widgetContext[2].sigPFC)
+#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_OFFSET                                  (138u)
+#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_SIZE                                    (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_PARAM_ID                                (0x0602008au)
+
+#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_VALUE                               (cy_capsense_tuner.widgetContext[2].resolution)
+#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_OFFSET                              (140u)
+#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_PARAM_ID                            (0x0602008cu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_VALUE                              (cy_capsense_tuner.widgetContext[2].maxRawCount)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_OFFSET                             (142u)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_SIZE                               (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_PARAM_ID                           (0x0202008eu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_VALUE                                (cy_capsense_tuner.widgetContext[2].fingerTh)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_OFFSET                               (144u)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_PARAM_ID                             (0x02020090u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_VALUE                            (cy_capsense_tuner.widgetContext[2].proxTh)
+#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_OFFSET                           (146u)
+#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_SIZE                             (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_PARAM_ID                         (0x02020092u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_VALUE                             (cy_capsense_tuner.widgetContext[2].lowBslnRst)
+#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_OFFSET                            (148u)
+#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_SIZE                              (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_PARAM_ID                          (0x06020094u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_VALUE                                  (cy_capsense_tuner.widgetContext[2].snsClk)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_OFFSET                                 (150u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SIZE                                   (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_PARAM_ID                               (0x06020096u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_VALUE                              (cy_capsense_tuner.widgetContext[2].rowSnsClk)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_OFFSET                             (152u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_SIZE                               (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_PARAM_ID                           (0x06020098u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_VALUE                         (cy_capsense_tuner.widgetContext[2].gestureDetected)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_OFFSET                        (154u)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_SIZE                          (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_PARAM_ID                      (0x0202009au)
+
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_VALUE                        (cy_capsense_tuner.widgetContext[2].gestureDirection)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_OFFSET                       (156u)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_SIZE                         (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_PARAM_ID                     (0x0202009cu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_VALUE                                   (cy_capsense_tuner.widgetContext[2].xDelta)
+#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_OFFSET                                  (158u)
+#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_SIZE                                    (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_PARAM_ID                                (0x0202009eu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_VALUE                                   (cy_capsense_tuner.widgetContext[2].yDelta)
+#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_OFFSET                                  (160u)
+#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_SIZE                                    (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_PARAM_ID                                (0x020200a0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_VALUE                                 (cy_capsense_tuner.widgetContext[2].noiseTh)
+#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_OFFSET                                (162u)
+#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_SIZE                                  (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_PARAM_ID                              (0x010200a2u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_VALUE                                (cy_capsense_tuner.widgetContext[2].nNoiseTh)
+#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_OFFSET                               (163u)
+#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_SIZE                                 (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_PARAM_ID                             (0x010200a3u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_VALUE                               (cy_capsense_tuner.widgetContext[2].hysteresis)
+#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_OFFSET                              (164u)
+#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_PARAM_ID                            (0x010200a4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_VALUE                              (cy_capsense_tuner.widgetContext[2].onDebounce)
+#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_OFFSET                             (165u)
+#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_SIZE                               (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_PARAM_ID                           (0x050200a5u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_VALUE                           (cy_capsense_tuner.widgetContext[2].snsClkSource)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_OFFSET                          (166u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_PARAM_ID                        (0x050200a6u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_VALUE                                (cy_capsense_tuner.widgetContext[2].idacMod[0])
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_OFFSET                               (167u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_SIZE                                 (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_PARAM_ID                             (0x050200a7u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_VALUE                                (cy_capsense_tuner.widgetContext[2].idacMod[1])
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_OFFSET                               (168u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_SIZE                                 (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_PARAM_ID                             (0x050200a8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_VALUE                                (cy_capsense_tuner.widgetContext[2].idacMod[2])
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_OFFSET                               (169u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_SIZE                                 (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_PARAM_ID                             (0x050200a9u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_VALUE                          (cy_capsense_tuner.widgetContext[2].idacGainIndex)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_OFFSET                         (170u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_SIZE                           (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_PARAM_ID                       (0x050200aau)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_VALUE                            (cy_capsense_tuner.widgetContext[2].rowIdacMod[0])
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_OFFSET                           (171u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_SIZE                             (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_PARAM_ID                         (0x050200abu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_VALUE                            (cy_capsense_tuner.widgetContext[2].rowIdacMod[1])
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_OFFSET                           (172u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_SIZE                             (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_PARAM_ID                         (0x050200acu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_VALUE                            (cy_capsense_tuner.widgetContext[2].rowIdacMod[2])
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_OFFSET                           (173u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_SIZE                             (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_PARAM_ID                         (0x050200adu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_VALUE                         (cy_capsense_tuner.widgetContext[2].bslnCoeff)
+#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_OFFSET                        (174u)
+#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_SIZE                          (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_PARAM_ID                      (0x010200aeu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_STATUS_VALUE                                   (cy_capsense_tuner.widgetContext[2].status)
+#define CY_CAPSENSE_LINEARSLIDER0_STATUS_OFFSET                                  (175u)
+#define CY_CAPSENSE_LINEARSLIDER0_STATUS_SIZE                                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_STATUS_PARAM_ID                                (0x010200afu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_VALUE                              (cy_capsense_tuner.widgetContext[2].wdTouch.ptrPosition)
+#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_OFFSET                             (176u)
+#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_SIZE                               (4u)
+#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_PARAM_ID                           (0x030200b0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_VALUE                            (cy_capsense_tuner.widgetContext[2].wdTouch.numPosition)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_OFFSET                           (180u)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_SIZE                             (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_PARAM_ID                         (0x010200b4u)
+
+#define CY_CAPSENSE_BUTTON0_SNS0_RAW0_VALUE                                      (cy_capsense_tuner.sensorContext[0].raw)
+#define CY_CAPSENSE_BUTTON0_SNS0_RAW0_OFFSET                                     (184u)
+#define CY_CAPSENSE_BUTTON0_SNS0_RAW0_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON0_SNS0_RAW0_PARAM_ID                                   (0x020000b8u)
+
+#define CY_CAPSENSE_BUTTON0_SNS0_BSLN0_VALUE                                     (cy_capsense_tuner.sensorContext[0].bsln)
+#define CY_CAPSENSE_BUTTON0_SNS0_BSLN0_OFFSET                                    (186u)
+#define CY_CAPSENSE_BUTTON0_SNS0_BSLN0_SIZE                                      (2u)
+#define CY_CAPSENSE_BUTTON0_SNS0_BSLN0_PARAM_ID                                  (0x020000bau)
+
+#define CY_CAPSENSE_BUTTON0_SNS0_DIFF0_VALUE                                     (cy_capsense_tuner.sensorContext[0].diff)
+#define CY_CAPSENSE_BUTTON0_SNS0_DIFF0_OFFSET                                    (188u)
+#define CY_CAPSENSE_BUTTON0_SNS0_DIFF0_SIZE                                      (2u)
+#define CY_CAPSENSE_BUTTON0_SNS0_DIFF0_PARAM_ID                                  (0x020000bcu)
+
+#define CY_CAPSENSE_BUTTON0_SNS0_STATUS0_VALUE                                   (cy_capsense_tuner.sensorContext[0].status)
+#define CY_CAPSENSE_BUTTON0_SNS0_STATUS0_OFFSET                                  (190u)
+#define CY_CAPSENSE_BUTTON0_SNS0_STATUS0_SIZE                                    (1u)
+#define CY_CAPSENSE_BUTTON0_SNS0_STATUS0_PARAM_ID                                (0x010000beu)
+
+#define CY_CAPSENSE_BUTTON0_SNS0_NEG_BSLN_RST_CNT0_VALUE                         (cy_capsense_tuner.sensorContext[0].negBslnRstCnt)
+#define CY_CAPSENSE_BUTTON0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                        (191u)
+#define CY_CAPSENSE_BUTTON0_SNS0_NEG_BSLN_RST_CNT0_SIZE                          (1u)
+#define CY_CAPSENSE_BUTTON0_SNS0_NEG_BSLN_RST_CNT0_PARAM_ID                      (0x010000bfu)
+
+#define CY_CAPSENSE_BUTTON0_SNS0_IDAC0_VALUE                                     (cy_capsense_tuner.sensorContext[0].idacComp)
+#define CY_CAPSENSE_BUTTON0_SNS0_IDAC0_OFFSET                                    (192u)
+#define CY_CAPSENSE_BUTTON0_SNS0_IDAC0_SIZE                                      (1u)
+#define CY_CAPSENSE_BUTTON0_SNS0_IDAC0_PARAM_ID                                  (0x010000c0u)
+
+#define CY_CAPSENSE_BUTTON0_SNS0_BSLN_EXT0_VALUE                                 (cy_capsense_tuner.sensorContext[0].bslnExt)
+#define CY_CAPSENSE_BUTTON0_SNS0_BSLN_EXT0_OFFSET                                (193u)
+#define CY_CAPSENSE_BUTTON0_SNS0_BSLN_EXT0_SIZE                                  (1u)
+#define CY_CAPSENSE_BUTTON0_SNS0_BSLN_EXT0_PARAM_ID                              (0x010000c1u)
+
+#define CY_CAPSENSE_BUTTON1_SNS0_RAW0_VALUE                                      (cy_capsense_tuner.sensorContext[1].raw)
+#define CY_CAPSENSE_BUTTON1_SNS0_RAW0_OFFSET                                     (194u)
+#define CY_CAPSENSE_BUTTON1_SNS0_RAW0_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON1_SNS0_RAW0_PARAM_ID                                   (0x020100c2u)
+
+#define CY_CAPSENSE_BUTTON1_SNS0_BSLN0_VALUE                                     (cy_capsense_tuner.sensorContext[1].bsln)
+#define CY_CAPSENSE_BUTTON1_SNS0_BSLN0_OFFSET                                    (196u)
+#define CY_CAPSENSE_BUTTON1_SNS0_BSLN0_SIZE                                      (2u)
+#define CY_CAPSENSE_BUTTON1_SNS0_BSLN0_PARAM_ID                                  (0x020100c4u)
+
+#define CY_CAPSENSE_BUTTON1_SNS0_DIFF0_VALUE                                     (cy_capsense_tuner.sensorContext[1].diff)
+#define CY_CAPSENSE_BUTTON1_SNS0_DIFF0_OFFSET                                    (198u)
+#define CY_CAPSENSE_BUTTON1_SNS0_DIFF0_SIZE                                      (2u)
+#define CY_CAPSENSE_BUTTON1_SNS0_DIFF0_PARAM_ID                                  (0x020100c6u)
+
+#define CY_CAPSENSE_BUTTON1_SNS0_STATUS0_VALUE                                   (cy_capsense_tuner.sensorContext[1].status)
+#define CY_CAPSENSE_BUTTON1_SNS0_STATUS0_OFFSET                                  (200u)
+#define CY_CAPSENSE_BUTTON1_SNS0_STATUS0_SIZE                                    (1u)
+#define CY_CAPSENSE_BUTTON1_SNS0_STATUS0_PARAM_ID                                (0x010100c8u)
+
+#define CY_CAPSENSE_BUTTON1_SNS0_NEG_BSLN_RST_CNT0_VALUE                         (cy_capsense_tuner.sensorContext[1].negBslnRstCnt)
+#define CY_CAPSENSE_BUTTON1_SNS0_NEG_BSLN_RST_CNT0_OFFSET                        (201u)
+#define CY_CAPSENSE_BUTTON1_SNS0_NEG_BSLN_RST_CNT0_SIZE                          (1u)
+#define CY_CAPSENSE_BUTTON1_SNS0_NEG_BSLN_RST_CNT0_PARAM_ID                      (0x010100c9u)
+
+#define CY_CAPSENSE_BUTTON1_SNS0_IDAC0_VALUE                                     (cy_capsense_tuner.sensorContext[1].idacComp)
+#define CY_CAPSENSE_BUTTON1_SNS0_IDAC0_OFFSET                                    (202u)
+#define CY_CAPSENSE_BUTTON1_SNS0_IDAC0_SIZE                                      (1u)
+#define CY_CAPSENSE_BUTTON1_SNS0_IDAC0_PARAM_ID                                  (0x010100cau)
+
+#define CY_CAPSENSE_BUTTON1_SNS0_BSLN_EXT0_VALUE                                 (cy_capsense_tuner.sensorContext[1].bslnExt)
+#define CY_CAPSENSE_BUTTON1_SNS0_BSLN_EXT0_OFFSET                                (203u)
+#define CY_CAPSENSE_BUTTON1_SNS0_BSLN_EXT0_SIZE                                  (1u)
+#define CY_CAPSENSE_BUTTON1_SNS0_BSLN_EXT0_PARAM_ID                              (0x010100cbu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[2].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_OFFSET                               (204u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_PARAM_ID                             (0x020200ccu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[2].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_OFFSET                              (206u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_PARAM_ID                            (0x020200ceu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[2].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_OFFSET                              (208u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_PARAM_ID                            (0x020200d0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[2].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_OFFSET                            (210u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_PARAM_ID                          (0x010200d2u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[2].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                  (211u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200d3u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[2].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_OFFSET                              (212u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_PARAM_ID                            (0x010200d4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[2].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_OFFSET                          (213u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_PARAM_ID                        (0x010200d5u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[3].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_OFFSET                               (214u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_PARAM_ID                             (0x020200d6u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[3].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_OFFSET                              (216u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_PARAM_ID                            (0x020200d8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[3].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_OFFSET                              (218u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_PARAM_ID                            (0x020200dau)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[3].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_OFFSET                            (220u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_PARAM_ID                          (0x010200dcu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[3].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_OFFSET                  (221u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200ddu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[3].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_OFFSET                              (222u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_PARAM_ID                            (0x010200deu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[3].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_OFFSET                          (223u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_PARAM_ID                        (0x010200dfu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[4].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_OFFSET                               (224u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_PARAM_ID                             (0x020200e0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[4].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_OFFSET                              (226u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_PARAM_ID                            (0x020200e2u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[4].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_OFFSET                              (228u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_PARAM_ID                            (0x020200e4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[4].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_OFFSET                            (230u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_PARAM_ID                          (0x010200e6u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[4].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_OFFSET                  (231u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200e7u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[4].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_OFFSET                              (232u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_PARAM_ID                            (0x010200e8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[4].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_OFFSET                          (233u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_PARAM_ID                        (0x010200e9u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[5].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_OFFSET                               (234u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_PARAM_ID                             (0x020200eau)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[5].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_OFFSET                              (236u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_PARAM_ID                            (0x020200ecu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[5].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_OFFSET                              (238u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_PARAM_ID                            (0x020200eeu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[5].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_OFFSET                            (240u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_PARAM_ID                          (0x010200f0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[5].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_OFFSET                  (241u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200f1u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[5].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_OFFSET                              (242u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_PARAM_ID                            (0x010200f2u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[5].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_OFFSET                          (243u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_PARAM_ID                        (0x010200f3u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[6].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_OFFSET                               (244u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_PARAM_ID                             (0x020200f4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[6].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_OFFSET                              (246u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_PARAM_ID                            (0x020200f6u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[6].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_OFFSET                              (248u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_PARAM_ID                            (0x020200f8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[6].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_OFFSET                            (250u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_PARAM_ID                          (0x010200fau)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[6].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_OFFSET                  (251u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200fbu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[6].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_OFFSET                              (252u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_PARAM_ID                            (0x010200fcu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[6].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_OFFSET                          (253u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_PARAM_ID                        (0x010200fdu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_X0_VALUE                                       (cy_capsense_tuner.position[0].x)
+#define CY_CAPSENSE_LINEARSLIDER0_X0_OFFSET                                      (254u)
+#define CY_CAPSENSE_LINEARSLIDER0_X0_SIZE                                        (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_X0_PARAM_ID                                    (0x020200feu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_Y0_VALUE                                       (cy_capsense_tuner.position[0].y)
+#define CY_CAPSENSE_LINEARSLIDER0_Y0_OFFSET                                      (256u)
+#define CY_CAPSENSE_LINEARSLIDER0_Y0_SIZE                                        (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_Y0_PARAM_ID                                    (0x02020100u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_Z0_VALUE                                       (cy_capsense_tuner.position[0].z)
+#define CY_CAPSENSE_LINEARSLIDER0_Z0_OFFSET                                      (258u)
+#define CY_CAPSENSE_LINEARSLIDER0_Z0_SIZE                                        (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_Z0_PARAM_ID                                    (0x02020102u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ID0_VALUE                                      (cy_capsense_tuner.position[0].id)
+#define CY_CAPSENSE_LINEARSLIDER0_ID0_OFFSET                                     (260u)
+#define CY_CAPSENSE_LINEARSLIDER0_ID0_SIZE                                       (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_ID0_PARAM_ID                                   (0x02020104u)
+
+#else /* CY_CAPSENSE_MW_VERSION >= 300 */
+#define CY_CAPSENSE_CONFIG_ID_VALUE                                              (cy_capsense_tuner.commonContext.configId)
+#define CY_CAPSENSE_CONFIG_ID_OFFSET                                             (0u)
+#define CY_CAPSENSE_CONFIG_ID_SIZE                                               (2u)
+#define CY_CAPSENSE_CONFIG_ID_PARAM_ID                                           (0x02000000u)
+
+#define CY_CAPSENSE_TUNER_CMD_VALUE                                              (cy_capsense_tuner.commonContext.tunerCmd)
+#define CY_CAPSENSE_TUNER_CMD_OFFSET                                             (2u)
+#define CY_CAPSENSE_TUNER_CMD_SIZE                                               (2u)
+#define CY_CAPSENSE_TUNER_CMD_PARAM_ID                                           (0x02000002u)
+
+#define CY_CAPSENSE_SCAN_COUNTER_VALUE                                           (cy_capsense_tuner.commonContext.scanCounter)
+#define CY_CAPSENSE_SCAN_COUNTER_OFFSET                                          (4u)
+#define CY_CAPSENSE_SCAN_COUNTER_SIZE                                            (2u)
+#define CY_CAPSENSE_SCAN_COUNTER_PARAM_ID                                        (0x02000004u)
+
+#define CY_CAPSENSE_TUNER_ST_VALUE                                               (cy_capsense_tuner.commonContext.tunerSt)
+#define CY_CAPSENSE_TUNER_ST_OFFSET                                              (6u)
+#define CY_CAPSENSE_TUNER_ST_SIZE                                                (1u)
+#define CY_CAPSENSE_TUNER_ST_PARAM_ID                                            (0x01000006u)
+
+#define CY_CAPSENSE_INITDONE_VALUE                                               (cy_capsense_tuner.commonContext.initDone)
+#define CY_CAPSENSE_INITDONE_OFFSET                                              (7u)
+#define CY_CAPSENSE_INITDONE_SIZE                                                (1u)
+#define CY_CAPSENSE_INITDONE_PARAM_ID                                            (0x01000007u)
+
+#define CY_CAPSENSE_STATUS_VALUE                                                 (cy_capsense_tuner.commonContext.status)
+#define CY_CAPSENSE_STATUS_OFFSET                                                (8u)
+#define CY_CAPSENSE_STATUS_SIZE                                                  (4u)
+#define CY_CAPSENSE_STATUS_PARAM_ID                                              (0x03000008u)
+
+#define CY_CAPSENSE_TIMESTAMPINTERVAL_VALUE                                      (cy_capsense_tuner.commonContext.timestampInterval)
+#define CY_CAPSENSE_TIMESTAMPINTERVAL_OFFSET                                     (12u)
+#define CY_CAPSENSE_TIMESTAMPINTERVAL_SIZE                                       (4u)
+#define CY_CAPSENSE_TIMESTAMPINTERVAL_PARAM_ID                                   (0x0300000cu)
+
+#define CY_CAPSENSE_TIMESTAMP_VALUE                                              (cy_capsense_tuner.commonContext.timestamp)
+#define CY_CAPSENSE_TIMESTAMP_OFFSET                                             (16u)
+#define CY_CAPSENSE_TIMESTAMP_SIZE                                               (4u)
+#define CY_CAPSENSE_TIMESTAMP_PARAM_ID                                           (0x03000010u)
+
+#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_VALUE                                    (cy_capsense_tuner.commonContext.modCsdClk)
+#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_OFFSET                                   (20u)
+#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_SIZE                                     (1u)
+#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_PARAM_ID                                 (0x01000014u)
+
+#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_VALUE                                    (cy_capsense_tuner.commonContext.modCsxClk)
+#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_OFFSET                                   (21u)
+#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_SIZE                                     (1u)
+#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_PARAM_ID                                 (0x01000015u)
+
+#define CY_CAPSENSE_TUNER_CNT_VALUE                                              (cy_capsense_tuner.commonContext.tunerCnt)
+#define CY_CAPSENSE_TUNER_CNT_OFFSET                                             (22u)
+#define CY_CAPSENSE_TUNER_CNT_SIZE                                               (1u)
+#define CY_CAPSENSE_TUNER_CNT_PARAM_ID                                           (0x01000016u)
+
+#define CY_CAPSENSE_BUTTON0_FINGER_CP_VALUE                                      (cy_capsense_tuner.widgetContext[0].fingerCap)
+#define CY_CAPSENSE_BUTTON0_FINGER_CP_OFFSET                                     (24u)
+#define CY_CAPSENSE_BUTTON0_FINGER_CP_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON0_FINGER_CP_PARAM_ID                                   (0x06000018u)
+
+#define CY_CAPSENSE_BUTTON0_SIGPFC_VALUE                                         (cy_capsense_tuner.widgetContext[0].sigPFC)
+#define CY_CAPSENSE_BUTTON0_SIGPFC_OFFSET                                        (26u)
+#define CY_CAPSENSE_BUTTON0_SIGPFC_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON0_SIGPFC_PARAM_ID                                      (0x0600001au)
+
+#define CY_CAPSENSE_BUTTON0_RESOLUTION_VALUE                                     (cy_capsense_tuner.widgetContext[0].resolution)
+#define CY_CAPSENSE_BUTTON0_RESOLUTION_OFFSET                                    (28u)
+#define CY_CAPSENSE_BUTTON0_RESOLUTION_SIZE                                      (2u)
+#define CY_CAPSENSE_BUTTON0_RESOLUTION_PARAM_ID                                  (0x0600001cu)
+
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_VALUE                                    (cy_capsense_tuner.widgetContext[0].maxRawCount)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_OFFSET                                   (30u)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_SIZE                                     (2u)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_PARAM_ID                                 (0x0200001eu)
+
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNTROW_VALUE                                 (cy_capsense_tuner.widgetContext[0].maxRawCountRow)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNTROW_OFFSET                                (32u)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNTROW_SIZE                                  (2u)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNTROW_PARAM_ID                              (0x02000020u)
+
+#define CY_CAPSENSE_BUTTON0_FINGER_TH_VALUE                                      (cy_capsense_tuner.widgetContext[0].fingerTh)
+#define CY_CAPSENSE_BUTTON0_FINGER_TH_OFFSET                                     (34u)
+#define CY_CAPSENSE_BUTTON0_FINGER_TH_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON0_FINGER_TH_PARAM_ID                                   (0x02000022u)
+
+#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_VALUE                                  (cy_capsense_tuner.widgetContext[0].proxTh)
+#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_OFFSET                                 (36u)
+#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_SIZE                                   (2u)
+#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_PARAM_ID                               (0x02000024u)
+
+#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_VALUE                                   (cy_capsense_tuner.widgetContext[0].lowBslnRst)
+#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_OFFSET                                  (38u)
+#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_SIZE                                    (2u)
+#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_PARAM_ID                                (0x06000026u)
+
+#define CY_CAPSENSE_BUTTON0_SNS_CLK_VALUE                                        (cy_capsense_tuner.widgetContext[0].snsClk)
+#define CY_CAPSENSE_BUTTON0_SNS_CLK_OFFSET                                       (40u)
+#define CY_CAPSENSE_BUTTON0_SNS_CLK_SIZE                                         (2u)
+#define CY_CAPSENSE_BUTTON0_SNS_CLK_PARAM_ID                                     (0x06000028u)
+
+#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_VALUE                                    (cy_capsense_tuner.widgetContext[0].rowSnsClk)
+#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_OFFSET                                   (42u)
+#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_SIZE                                     (2u)
+#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_PARAM_ID                                 (0x0600002au)
+
+#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_VALUE                               (cy_capsense_tuner.widgetContext[0].gestureDetected)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_OFFSET                              (44u)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_SIZE                                (2u)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_PARAM_ID                            (0x0200002cu)
+
+#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_VALUE                              (cy_capsense_tuner.widgetContext[0].gestureDirection)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_OFFSET                             (46u)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_SIZE                               (2u)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_PARAM_ID                           (0x0200002eu)
+
+#define CY_CAPSENSE_BUTTON0_XDELTA_VALUE                                         (cy_capsense_tuner.widgetContext[0].xDelta)
+#define CY_CAPSENSE_BUTTON0_XDELTA_OFFSET                                        (48u)
+#define CY_CAPSENSE_BUTTON0_XDELTA_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON0_XDELTA_PARAM_ID                                      (0x02000030u)
+
+#define CY_CAPSENSE_BUTTON0_YDELTA_VALUE                                         (cy_capsense_tuner.widgetContext[0].yDelta)
+#define CY_CAPSENSE_BUTTON0_YDELTA_OFFSET                                        (50u)
+#define CY_CAPSENSE_BUTTON0_YDELTA_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON0_YDELTA_PARAM_ID                                      (0x02000032u)
+
+#define CY_CAPSENSE_BUTTON0_NOISE_TH_VALUE                                       (cy_capsense_tuner.widgetContext[0].noiseTh)
+#define CY_CAPSENSE_BUTTON0_NOISE_TH_OFFSET                                      (52u)
+#define CY_CAPSENSE_BUTTON0_NOISE_TH_SIZE                                        (2u)
+#define CY_CAPSENSE_BUTTON0_NOISE_TH_PARAM_ID                                    (0x02000034u)
+
+#define CY_CAPSENSE_BUTTON0_NNOISE_TH_VALUE                                      (cy_capsense_tuner.widgetContext[0].nNoiseTh)
+#define CY_CAPSENSE_BUTTON0_NNOISE_TH_OFFSET                                     (54u)
+#define CY_CAPSENSE_BUTTON0_NNOISE_TH_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON0_NNOISE_TH_PARAM_ID                                   (0x02000036u)
+
+#define CY_CAPSENSE_BUTTON0_HYSTERESIS_VALUE                                     (cy_capsense_tuner.widgetContext[0].hysteresis)
+#define CY_CAPSENSE_BUTTON0_HYSTERESIS_OFFSET                                    (56u)
+#define CY_CAPSENSE_BUTTON0_HYSTERESIS_SIZE                                      (2u)
+#define CY_CAPSENSE_BUTTON0_HYSTERESIS_PARAM_ID                                  (0x02000038u)
+
+#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_VALUE                                    (cy_capsense_tuner.widgetContext[0].onDebounce)
+#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_OFFSET                                   (58u)
+#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_SIZE                                     (1u)
+#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_PARAM_ID                                 (0x0500003au)
+
+#define CY_CAPSENSE_BUTTON0_SNS_CLK_SOURCE_VALUE                                 (cy_capsense_tuner.widgetContext[0].snsClkSource)
+#define CY_CAPSENSE_BUTTON0_SNS_CLK_SOURCE_OFFSET                                (59u)
+#define CY_CAPSENSE_BUTTON0_SNS_CLK_SOURCE_SIZE                                  (1u)
+#define CY_CAPSENSE_BUTTON0_SNS_CLK_SOURCE_PARAM_ID                              (0x0500003bu)
+
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_VALUE                                      (cy_capsense_tuner.widgetContext[0].idacMod[0])
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_OFFSET                                     (60u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_PARAM_ID                                   (0x0500003cu)
+
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_VALUE                                      (cy_capsense_tuner.widgetContext[0].idacMod[1])
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_OFFSET                                     (61u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_PARAM_ID                                   (0x0500003du)
+
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_VALUE                                      (cy_capsense_tuner.widgetContext[0].idacMod[2])
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_OFFSET                                     (62u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_PARAM_ID                                   (0x0500003eu)
+
+#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_VALUE                                (cy_capsense_tuner.widgetContext[0].idacGainIndex)
+#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_OFFSET                               (63u)
+#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_SIZE                                 (1u)
+#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_PARAM_ID                             (0x0500003fu)
+
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_VALUE                                  (cy_capsense_tuner.widgetContext[0].rowIdacMod[0])
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_OFFSET                                 (64u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_PARAM_ID                               (0x05000040u)
+
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_VALUE                                  (cy_capsense_tuner.widgetContext[0].rowIdacMod[1])
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_OFFSET                                 (65u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_PARAM_ID                               (0x05000041u)
+
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_VALUE                                  (cy_capsense_tuner.widgetContext[0].rowIdacMod[2])
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_OFFSET                                 (66u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_PARAM_ID                               (0x05000042u)
+
+#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_VALUE                               (cy_capsense_tuner.widgetContext[0].bslnCoeff)
+#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_OFFSET                              (67u)
+#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_SIZE                                (1u)
+#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_PARAM_ID                            (0x01000043u)
+
+#define CY_CAPSENSE_BUTTON0_STATUS_VALUE                                         (cy_capsense_tuner.widgetContext[0].status)
+#define CY_CAPSENSE_BUTTON0_STATUS_OFFSET                                        (68u)
+#define CY_CAPSENSE_BUTTON0_STATUS_SIZE                                          (1u)
+#define CY_CAPSENSE_BUTTON0_STATUS_PARAM_ID                                      (0x01000044u)
+
+#define CY_CAPSENSE_BUTTON0_PTRPOSITION_VALUE                                    (cy_capsense_tuner.widgetContext[0].wdTouch.ptrPosition)
+#define CY_CAPSENSE_BUTTON0_PTRPOSITION_OFFSET                                   (72u)
+#define CY_CAPSENSE_BUTTON0_PTRPOSITION_SIZE                                     (4u)
+#define CY_CAPSENSE_BUTTON0_PTRPOSITION_PARAM_ID                                 (0x03000048u)
+
+#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_VALUE                                  (cy_capsense_tuner.widgetContext[0].wdTouch.numPosition)
+#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_OFFSET                                 (76u)
+#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_PARAM_ID                               (0x0100004cu)
+
+#define CY_CAPSENSE_BUTTON1_FINGER_CP_VALUE                                      (cy_capsense_tuner.widgetContext[1].fingerCap)
+#define CY_CAPSENSE_BUTTON1_FINGER_CP_OFFSET                                     (80u)
+#define CY_CAPSENSE_BUTTON1_FINGER_CP_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON1_FINGER_CP_PARAM_ID                                   (0x06010050u)
+
+#define CY_CAPSENSE_BUTTON1_SIGPFC_VALUE                                         (cy_capsense_tuner.widgetContext[1].sigPFC)
+#define CY_CAPSENSE_BUTTON1_SIGPFC_OFFSET                                        (82u)
+#define CY_CAPSENSE_BUTTON1_SIGPFC_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON1_SIGPFC_PARAM_ID                                      (0x06010052u)
+
+#define CY_CAPSENSE_BUTTON1_RESOLUTION_VALUE                                     (cy_capsense_tuner.widgetContext[1].resolution)
+#define CY_CAPSENSE_BUTTON1_RESOLUTION_OFFSET                                    (84u)
+#define CY_CAPSENSE_BUTTON1_RESOLUTION_SIZE                                      (2u)
+#define CY_CAPSENSE_BUTTON1_RESOLUTION_PARAM_ID                                  (0x06010054u)
+
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_VALUE                                    (cy_capsense_tuner.widgetContext[1].maxRawCount)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_OFFSET                                   (86u)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_SIZE                                     (2u)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_PARAM_ID                                 (0x02010056u)
+
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNTROW_VALUE                                 (cy_capsense_tuner.widgetContext[1].maxRawCountRow)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNTROW_OFFSET                                (88u)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNTROW_SIZE                                  (2u)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNTROW_PARAM_ID                              (0x02010058u)
+
+#define CY_CAPSENSE_BUTTON1_FINGER_TH_VALUE                                      (cy_capsense_tuner.widgetContext[1].fingerTh)
+#define CY_CAPSENSE_BUTTON1_FINGER_TH_OFFSET                                     (90u)
+#define CY_CAPSENSE_BUTTON1_FINGER_TH_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON1_FINGER_TH_PARAM_ID                                   (0x0201005au)
+
+#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_VALUE                                  (cy_capsense_tuner.widgetContext[1].proxTh)
+#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_OFFSET                                 (92u)
+#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_SIZE                                   (2u)
+#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_PARAM_ID                               (0x0201005cu)
+
+#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_VALUE                                   (cy_capsense_tuner.widgetContext[1].lowBslnRst)
+#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_OFFSET                                  (94u)
+#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_SIZE                                    (2u)
+#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_PARAM_ID                                (0x0601005eu)
+
+#define CY_CAPSENSE_BUTTON1_SNS_CLK_VALUE                                        (cy_capsense_tuner.widgetContext[1].snsClk)
+#define CY_CAPSENSE_BUTTON1_SNS_CLK_OFFSET                                       (96u)
+#define CY_CAPSENSE_BUTTON1_SNS_CLK_SIZE                                         (2u)
+#define CY_CAPSENSE_BUTTON1_SNS_CLK_PARAM_ID                                     (0x06010060u)
+
+#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_VALUE                                    (cy_capsense_tuner.widgetContext[1].rowSnsClk)
+#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_OFFSET                                   (98u)
+#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_SIZE                                     (2u)
+#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_PARAM_ID                                 (0x06010062u)
+
+#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_VALUE                               (cy_capsense_tuner.widgetContext[1].gestureDetected)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_OFFSET                              (100u)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_SIZE                                (2u)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_PARAM_ID                            (0x02010064u)
+
+#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_VALUE                              (cy_capsense_tuner.widgetContext[1].gestureDirection)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_OFFSET                             (102u)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_SIZE                               (2u)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_PARAM_ID                           (0x02010066u)
+
+#define CY_CAPSENSE_BUTTON1_XDELTA_VALUE                                         (cy_capsense_tuner.widgetContext[1].xDelta)
+#define CY_CAPSENSE_BUTTON1_XDELTA_OFFSET                                        (104u)
+#define CY_CAPSENSE_BUTTON1_XDELTA_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON1_XDELTA_PARAM_ID                                      (0x02010068u)
+
+#define CY_CAPSENSE_BUTTON1_YDELTA_VALUE                                         (cy_capsense_tuner.widgetContext[1].yDelta)
+#define CY_CAPSENSE_BUTTON1_YDELTA_OFFSET                                        (106u)
+#define CY_CAPSENSE_BUTTON1_YDELTA_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON1_YDELTA_PARAM_ID                                      (0x0201006au)
+
+#define CY_CAPSENSE_BUTTON1_NOISE_TH_VALUE                                       (cy_capsense_tuner.widgetContext[1].noiseTh)
+#define CY_CAPSENSE_BUTTON1_NOISE_TH_OFFSET                                      (108u)
+#define CY_CAPSENSE_BUTTON1_NOISE_TH_SIZE                                        (2u)
+#define CY_CAPSENSE_BUTTON1_NOISE_TH_PARAM_ID                                    (0x0201006cu)
+
+#define CY_CAPSENSE_BUTTON1_NNOISE_TH_VALUE                                      (cy_capsense_tuner.widgetContext[1].nNoiseTh)
+#define CY_CAPSENSE_BUTTON1_NNOISE_TH_OFFSET                                     (110u)
+#define CY_CAPSENSE_BUTTON1_NNOISE_TH_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON1_NNOISE_TH_PARAM_ID                                   (0x0201006eu)
+
+#define CY_CAPSENSE_BUTTON1_HYSTERESIS_VALUE                                     (cy_capsense_tuner.widgetContext[1].hysteresis)
+#define CY_CAPSENSE_BUTTON1_HYSTERESIS_OFFSET                                    (112u)
+#define CY_CAPSENSE_BUTTON1_HYSTERESIS_SIZE                                      (2u)
+#define CY_CAPSENSE_BUTTON1_HYSTERESIS_PARAM_ID                                  (0x02010070u)
+
+#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_VALUE                                    (cy_capsense_tuner.widgetContext[1].onDebounce)
+#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_OFFSET                                   (114u)
+#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_SIZE                                     (1u)
+#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_PARAM_ID                                 (0x05010072u)
+
+#define CY_CAPSENSE_BUTTON1_SNS_CLK_SOURCE_VALUE                                 (cy_capsense_tuner.widgetContext[1].snsClkSource)
+#define CY_CAPSENSE_BUTTON1_SNS_CLK_SOURCE_OFFSET                                (115u)
+#define CY_CAPSENSE_BUTTON1_SNS_CLK_SOURCE_SIZE                                  (1u)
+#define CY_CAPSENSE_BUTTON1_SNS_CLK_SOURCE_PARAM_ID                              (0x05010073u)
+
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_VALUE                                      (cy_capsense_tuner.widgetContext[1].idacMod[0])
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_OFFSET                                     (116u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_PARAM_ID                                   (0x05010074u)
+
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_VALUE                                      (cy_capsense_tuner.widgetContext[1].idacMod[1])
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_OFFSET                                     (117u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_PARAM_ID                                   (0x05010075u)
+
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_VALUE                                      (cy_capsense_tuner.widgetContext[1].idacMod[2])
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_OFFSET                                     (118u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_PARAM_ID                                   (0x05010076u)
+
+#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_VALUE                                (cy_capsense_tuner.widgetContext[1].idacGainIndex)
+#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_OFFSET                               (119u)
+#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_SIZE                                 (1u)
+#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_PARAM_ID                             (0x05010077u)
+
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_VALUE                                  (cy_capsense_tuner.widgetContext[1].rowIdacMod[0])
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_OFFSET                                 (120u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_PARAM_ID                               (0x05010078u)
+
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_VALUE                                  (cy_capsense_tuner.widgetContext[1].rowIdacMod[1])
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_OFFSET                                 (121u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_PARAM_ID                               (0x05010079u)
+
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_VALUE                                  (cy_capsense_tuner.widgetContext[1].rowIdacMod[2])
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_OFFSET                                 (122u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_PARAM_ID                               (0x0501007au)
+
+#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_VALUE                               (cy_capsense_tuner.widgetContext[1].bslnCoeff)
+#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_OFFSET                              (123u)
+#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_SIZE                                (1u)
+#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_PARAM_ID                            (0x0101007bu)
+
+#define CY_CAPSENSE_BUTTON1_STATUS_VALUE                                         (cy_capsense_tuner.widgetContext[1].status)
+#define CY_CAPSENSE_BUTTON1_STATUS_OFFSET                                        (124u)
+#define CY_CAPSENSE_BUTTON1_STATUS_SIZE                                          (1u)
+#define CY_CAPSENSE_BUTTON1_STATUS_PARAM_ID                                      (0x0101007cu)
+
+#define CY_CAPSENSE_BUTTON1_PTRPOSITION_VALUE                                    (cy_capsense_tuner.widgetContext[1].wdTouch.ptrPosition)
+#define CY_CAPSENSE_BUTTON1_PTRPOSITION_OFFSET                                   (128u)
+#define CY_CAPSENSE_BUTTON1_PTRPOSITION_SIZE                                     (4u)
+#define CY_CAPSENSE_BUTTON1_PTRPOSITION_PARAM_ID                                 (0x03010080u)
+
+#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_VALUE                                  (cy_capsense_tuner.widgetContext[1].wdTouch.numPosition)
+#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_OFFSET                                 (132u)
+#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_PARAM_ID                               (0x01010084u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_VALUE                                (cy_capsense_tuner.widgetContext[2].fingerCap)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_OFFSET                               (136u)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_PARAM_ID                             (0x06020088u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_VALUE                                   (cy_capsense_tuner.widgetContext[2].sigPFC)
+#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_OFFSET                                  (138u)
+#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_SIZE                                    (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_PARAM_ID                                (0x0602008au)
+
+#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_VALUE                               (cy_capsense_tuner.widgetContext[2].resolution)
+#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_OFFSET                              (140u)
+#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_PARAM_ID                            (0x0602008cu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_VALUE                              (cy_capsense_tuner.widgetContext[2].maxRawCount)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_OFFSET                             (142u)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_SIZE                               (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_PARAM_ID                           (0x0202008eu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNTROW_VALUE                           (cy_capsense_tuner.widgetContext[2].maxRawCountRow)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNTROW_OFFSET                          (144u)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNTROW_SIZE                            (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNTROW_PARAM_ID                        (0x02020090u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_VALUE                                (cy_capsense_tuner.widgetContext[2].fingerTh)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_OFFSET                               (146u)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_PARAM_ID                             (0x02020092u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_VALUE                            (cy_capsense_tuner.widgetContext[2].proxTh)
+#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_OFFSET                           (148u)
+#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_SIZE                             (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_PARAM_ID                         (0x02020094u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_VALUE                             (cy_capsense_tuner.widgetContext[2].lowBslnRst)
+#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_OFFSET                            (150u)
+#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_SIZE                              (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_PARAM_ID                          (0x06020096u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_VALUE                                  (cy_capsense_tuner.widgetContext[2].snsClk)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_OFFSET                                 (152u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SIZE                                   (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_PARAM_ID                               (0x06020098u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_VALUE                              (cy_capsense_tuner.widgetContext[2].rowSnsClk)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_OFFSET                             (154u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_SIZE                               (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_PARAM_ID                           (0x0602009au)
+
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_VALUE                         (cy_capsense_tuner.widgetContext[2].gestureDetected)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_OFFSET                        (156u)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_SIZE                          (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_PARAM_ID                      (0x0202009cu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_VALUE                        (cy_capsense_tuner.widgetContext[2].gestureDirection)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_OFFSET                       (158u)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_SIZE                         (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_PARAM_ID                     (0x0202009eu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_VALUE                                   (cy_capsense_tuner.widgetContext[2].xDelta)
+#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_OFFSET                                  (160u)
+#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_SIZE                                    (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_PARAM_ID                                (0x020200a0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_VALUE                                   (cy_capsense_tuner.widgetContext[2].yDelta)
+#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_OFFSET                                  (162u)
+#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_SIZE                                    (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_PARAM_ID                                (0x020200a2u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_VALUE                                 (cy_capsense_tuner.widgetContext[2].noiseTh)
+#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_OFFSET                                (164u)
+#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_SIZE                                  (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_PARAM_ID                              (0x020200a4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_VALUE                                (cy_capsense_tuner.widgetContext[2].nNoiseTh)
+#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_OFFSET                               (166u)
+#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_PARAM_ID                             (0x020200a6u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_VALUE                               (cy_capsense_tuner.widgetContext[2].hysteresis)
+#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_OFFSET                              (168u)
+#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_PARAM_ID                            (0x020200a8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_VALUE                              (cy_capsense_tuner.widgetContext[2].onDebounce)
+#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_OFFSET                             (170u)
+#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_SIZE                               (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_PARAM_ID                           (0x050200aau)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_VALUE                           (cy_capsense_tuner.widgetContext[2].snsClkSource)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_OFFSET                          (171u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_PARAM_ID                        (0x050200abu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_VALUE                                (cy_capsense_tuner.widgetContext[2].idacMod[0])
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_OFFSET                               (172u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_SIZE                                 (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_PARAM_ID                             (0x050200acu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_VALUE                                (cy_capsense_tuner.widgetContext[2].idacMod[1])
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_OFFSET                               (173u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_SIZE                                 (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_PARAM_ID                             (0x050200adu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_VALUE                                (cy_capsense_tuner.widgetContext[2].idacMod[2])
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_OFFSET                               (174u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_SIZE                                 (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_PARAM_ID                             (0x050200aeu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_VALUE                          (cy_capsense_tuner.widgetContext[2].idacGainIndex)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_OFFSET                         (175u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_SIZE                           (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_PARAM_ID                       (0x050200afu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_VALUE                            (cy_capsense_tuner.widgetContext[2].rowIdacMod[0])
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_OFFSET                           (176u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_SIZE                             (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_PARAM_ID                         (0x050200b0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_VALUE                            (cy_capsense_tuner.widgetContext[2].rowIdacMod[1])
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_OFFSET                           (177u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_SIZE                             (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_PARAM_ID                         (0x050200b1u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_VALUE                            (cy_capsense_tuner.widgetContext[2].rowIdacMod[2])
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_OFFSET                           (178u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_SIZE                             (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_PARAM_ID                         (0x050200b2u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_VALUE                         (cy_capsense_tuner.widgetContext[2].bslnCoeff)
+#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_OFFSET                        (179u)
+#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_SIZE                          (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_PARAM_ID                      (0x010200b3u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_STATUS_VALUE                                   (cy_capsense_tuner.widgetContext[2].status)
+#define CY_CAPSENSE_LINEARSLIDER0_STATUS_OFFSET                                  (180u)
+#define CY_CAPSENSE_LINEARSLIDER0_STATUS_SIZE                                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_STATUS_PARAM_ID                                (0x010200b4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_VALUE                              (cy_capsense_tuner.widgetContext[2].wdTouch.ptrPosition)
+#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_OFFSET                             (184u)
+#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_SIZE                               (4u)
+#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_PARAM_ID                           (0x030200b8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_VALUE                            (cy_capsense_tuner.widgetContext[2].wdTouch.numPosition)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_OFFSET                           (188u)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_SIZE                             (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_PARAM_ID                         (0x010200bcu)
+
+#define CY_CAPSENSE_BUTTON0_SNS0_RAW0_VALUE                                      (cy_capsense_tuner.sensorContext[0].raw)
+#define CY_CAPSENSE_BUTTON0_SNS0_RAW0_OFFSET                                     (192u)
+#define CY_CAPSENSE_BUTTON0_SNS0_RAW0_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON0_SNS0_RAW0_PARAM_ID                                   (0x020000c0u)
+
+#define CY_CAPSENSE_BUTTON0_SNS0_BSLN0_VALUE                                     (cy_capsense_tuner.sensorContext[0].bsln)
+#define CY_CAPSENSE_BUTTON0_SNS0_BSLN0_OFFSET                                    (194u)
+#define CY_CAPSENSE_BUTTON0_SNS0_BSLN0_SIZE                                      (2u)
+#define CY_CAPSENSE_BUTTON0_SNS0_BSLN0_PARAM_ID                                  (0x020000c2u)
+
+#define CY_CAPSENSE_BUTTON0_SNS0_DIFF0_VALUE                                     (cy_capsense_tuner.sensorContext[0].diff)
+#define CY_CAPSENSE_BUTTON0_SNS0_DIFF0_OFFSET                                    (196u)
+#define CY_CAPSENSE_BUTTON0_SNS0_DIFF0_SIZE                                      (2u)
+#define CY_CAPSENSE_BUTTON0_SNS0_DIFF0_PARAM_ID                                  (0x020000c4u)
+
+#define CY_CAPSENSE_BUTTON0_SNS0_STATUS0_VALUE                                   (cy_capsense_tuner.sensorContext[0].status)
+#define CY_CAPSENSE_BUTTON0_SNS0_STATUS0_OFFSET                                  (198u)
+#define CY_CAPSENSE_BUTTON0_SNS0_STATUS0_SIZE                                    (1u)
+#define CY_CAPSENSE_BUTTON0_SNS0_STATUS0_PARAM_ID                                (0x010000c6u)
+
+#define CY_CAPSENSE_BUTTON0_SNS0_NEG_BSLN_RST_CNT0_VALUE                         (cy_capsense_tuner.sensorContext[0].negBslnRstCnt)
+#define CY_CAPSENSE_BUTTON0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                        (199u)
+#define CY_CAPSENSE_BUTTON0_SNS0_NEG_BSLN_RST_CNT0_SIZE                          (1u)
+#define CY_CAPSENSE_BUTTON0_SNS0_NEG_BSLN_RST_CNT0_PARAM_ID                      (0x010000c7u)
+
+#define CY_CAPSENSE_BUTTON0_SNS0_IDAC0_VALUE                                     (cy_capsense_tuner.sensorContext[0].idacComp)
+#define CY_CAPSENSE_BUTTON0_SNS0_IDAC0_OFFSET                                    (200u)
+#define CY_CAPSENSE_BUTTON0_SNS0_IDAC0_SIZE                                      (1u)
+#define CY_CAPSENSE_BUTTON0_SNS0_IDAC0_PARAM_ID                                  (0x010000c8u)
+
+#define CY_CAPSENSE_BUTTON0_SNS0_BSLN_EXT0_VALUE                                 (cy_capsense_tuner.sensorContext[0].bslnExt)
+#define CY_CAPSENSE_BUTTON0_SNS0_BSLN_EXT0_OFFSET                                (201u)
+#define CY_CAPSENSE_BUTTON0_SNS0_BSLN_EXT0_SIZE                                  (1u)
+#define CY_CAPSENSE_BUTTON0_SNS0_BSLN_EXT0_PARAM_ID                              (0x010000c9u)
+
+#define CY_CAPSENSE_BUTTON1_SNS0_RAW0_VALUE                                      (cy_capsense_tuner.sensorContext[1].raw)
+#define CY_CAPSENSE_BUTTON1_SNS0_RAW0_OFFSET                                     (202u)
+#define CY_CAPSENSE_BUTTON1_SNS0_RAW0_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON1_SNS0_RAW0_PARAM_ID                                   (0x020100cau)
+
+#define CY_CAPSENSE_BUTTON1_SNS0_BSLN0_VALUE                                     (cy_capsense_tuner.sensorContext[1].bsln)
+#define CY_CAPSENSE_BUTTON1_SNS0_BSLN0_OFFSET                                    (204u)
+#define CY_CAPSENSE_BUTTON1_SNS0_BSLN0_SIZE                                      (2u)
+#define CY_CAPSENSE_BUTTON1_SNS0_BSLN0_PARAM_ID                                  (0x020100ccu)
+
+#define CY_CAPSENSE_BUTTON1_SNS0_DIFF0_VALUE                                     (cy_capsense_tuner.sensorContext[1].diff)
+#define CY_CAPSENSE_BUTTON1_SNS0_DIFF0_OFFSET                                    (206u)
+#define CY_CAPSENSE_BUTTON1_SNS0_DIFF0_SIZE                                      (2u)
+#define CY_CAPSENSE_BUTTON1_SNS0_DIFF0_PARAM_ID                                  (0x020100ceu)
+
+#define CY_CAPSENSE_BUTTON1_SNS0_STATUS0_VALUE                                   (cy_capsense_tuner.sensorContext[1].status)
+#define CY_CAPSENSE_BUTTON1_SNS0_STATUS0_OFFSET                                  (208u)
+#define CY_CAPSENSE_BUTTON1_SNS0_STATUS0_SIZE                                    (1u)
+#define CY_CAPSENSE_BUTTON1_SNS0_STATUS0_PARAM_ID                                (0x010100d0u)
+
+#define CY_CAPSENSE_BUTTON1_SNS0_NEG_BSLN_RST_CNT0_VALUE                         (cy_capsense_tuner.sensorContext[1].negBslnRstCnt)
+#define CY_CAPSENSE_BUTTON1_SNS0_NEG_BSLN_RST_CNT0_OFFSET                        (209u)
+#define CY_CAPSENSE_BUTTON1_SNS0_NEG_BSLN_RST_CNT0_SIZE                          (1u)
+#define CY_CAPSENSE_BUTTON1_SNS0_NEG_BSLN_RST_CNT0_PARAM_ID                      (0x010100d1u)
+
+#define CY_CAPSENSE_BUTTON1_SNS0_IDAC0_VALUE                                     (cy_capsense_tuner.sensorContext[1].idacComp)
+#define CY_CAPSENSE_BUTTON1_SNS0_IDAC0_OFFSET                                    (210u)
+#define CY_CAPSENSE_BUTTON1_SNS0_IDAC0_SIZE                                      (1u)
+#define CY_CAPSENSE_BUTTON1_SNS0_IDAC0_PARAM_ID                                  (0x010100d2u)
+
+#define CY_CAPSENSE_BUTTON1_SNS0_BSLN_EXT0_VALUE                                 (cy_capsense_tuner.sensorContext[1].bslnExt)
+#define CY_CAPSENSE_BUTTON1_SNS0_BSLN_EXT0_OFFSET                                (211u)
+#define CY_CAPSENSE_BUTTON1_SNS0_BSLN_EXT0_SIZE                                  (1u)
+#define CY_CAPSENSE_BUTTON1_SNS0_BSLN_EXT0_PARAM_ID                              (0x010100d3u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[2].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_OFFSET                               (212u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_PARAM_ID                             (0x020200d4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[2].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_OFFSET                              (214u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_PARAM_ID                            (0x020200d6u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[2].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_OFFSET                              (216u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_PARAM_ID                            (0x020200d8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[2].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_OFFSET                            (218u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_PARAM_ID                          (0x010200dau)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[2].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                  (219u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200dbu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[2].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_OFFSET                              (220u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_PARAM_ID                            (0x010200dcu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[2].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_OFFSET                          (221u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_PARAM_ID                        (0x010200ddu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[3].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_OFFSET                               (222u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_PARAM_ID                             (0x020200deu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[3].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_OFFSET                              (224u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_PARAM_ID                            (0x020200e0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[3].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_OFFSET                              (226u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_PARAM_ID                            (0x020200e2u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[3].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_OFFSET                            (228u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_PARAM_ID                          (0x010200e4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[3].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_OFFSET                  (229u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200e5u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[3].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_OFFSET                              (230u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_PARAM_ID                            (0x010200e6u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[3].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_OFFSET                          (231u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_PARAM_ID                        (0x010200e7u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[4].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_OFFSET                               (232u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_PARAM_ID                             (0x020200e8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[4].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_OFFSET                              (234u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_PARAM_ID                            (0x020200eau)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[4].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_OFFSET                              (236u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_PARAM_ID                            (0x020200ecu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[4].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_OFFSET                            (238u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_PARAM_ID                          (0x010200eeu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[4].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_OFFSET                  (239u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200efu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[4].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_OFFSET                              (240u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_PARAM_ID                            (0x010200f0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[4].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_OFFSET                          (241u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_PARAM_ID                        (0x010200f1u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[5].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_OFFSET                               (242u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_PARAM_ID                             (0x020200f2u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[5].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_OFFSET                              (244u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_PARAM_ID                            (0x020200f4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[5].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_OFFSET                              (246u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_PARAM_ID                            (0x020200f6u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[5].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_OFFSET                            (248u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_PARAM_ID                          (0x010200f8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[5].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_OFFSET                  (249u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200f9u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[5].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_OFFSET                              (250u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_PARAM_ID                            (0x010200fau)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[5].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_OFFSET                          (251u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_PARAM_ID                        (0x010200fbu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[6].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_OFFSET                               (252u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_PARAM_ID                             (0x020200fcu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[6].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_OFFSET                              (254u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_PARAM_ID                            (0x020200feu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[6].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_OFFSET                              (256u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_PARAM_ID                            (0x02020100u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[6].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_OFFSET                            (258u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_PARAM_ID                          (0x01020102u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[6].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_OFFSET                  (259u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_PARAM_ID                (0x01020103u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[6].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_OFFSET                              (260u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_PARAM_ID                            (0x01020104u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[6].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_OFFSET                          (261u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_PARAM_ID                        (0x01020105u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_X0_VALUE                                       (cy_capsense_tuner.position[0].x)
+#define CY_CAPSENSE_LINEARSLIDER0_X0_OFFSET                                      (262u)
+#define CY_CAPSENSE_LINEARSLIDER0_X0_SIZE                                        (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_X0_PARAM_ID                                    (0x02020106u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_Y0_VALUE                                       (cy_capsense_tuner.position[0].y)
+#define CY_CAPSENSE_LINEARSLIDER0_Y0_OFFSET                                      (264u)
+#define CY_CAPSENSE_LINEARSLIDER0_Y0_SIZE                                        (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_Y0_PARAM_ID                                    (0x02020108u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_Z0_VALUE                                       (cy_capsense_tuner.position[0].z)
+#define CY_CAPSENSE_LINEARSLIDER0_Z0_OFFSET                                      (266u)
+#define CY_CAPSENSE_LINEARSLIDER0_Z0_SIZE                                        (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_Z0_PARAM_ID                                    (0x0202010au)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ID0_VALUE                                      (cy_capsense_tuner.position[0].id)
+#define CY_CAPSENSE_LINEARSLIDER0_ID0_OFFSET                                     (268u)
+#define CY_CAPSENSE_LINEARSLIDER0_ID0_SIZE                                       (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_ID0_PARAM_ID                                   (0x0202010cu)
+
+#endif
+/* cy_capsense_context */
+#define CY_CAPSENSE_COMMON_CONFIG_PTR_VALUE                                      (cy_capsense_context.ptrCommonConfig)
+#define CY_CAPSENSE_COMMON_CONFIG_PTR_SIZE                                       (sizeof(cy_capsense_context.ptrCommonConfig))
+
+#define CY_CAPSENSE_COMMON_CONTEXT_PTR_VALUE                                     (cy_capsense_context.ptrCommonContext)
+#define CY_CAPSENSE_COMMON_CONTEXT_PTR_SIZE                                      (sizeof(cy_capsense_context.ptrCommonContext))
+
+#define CY_CAPSENSE_INTERNAL_CONTEXT_PTR_VALUE                                   (cy_capsense_context.ptrInternalContext)
+#define CY_CAPSENSE_INTERNAL_CONTEXT_PTR_SIZE                                    (sizeof(cy_capsense_context.ptrInternalContext))
+
+#define CY_CAPSENSE_WD_CONFIG_PTR_VALUE                                          (cy_capsense_context.ptrWdConfig)
+#define CY_CAPSENSE_WD_CONFIG_PTR_SIZE                                           (sizeof(cy_capsense_context.ptrWdConfig))
+
+#define CY_CAPSENSE_WD_CONTEXT_PTR_VALUE                                         (cy_capsense_context.ptrWdContext)
+#define CY_CAPSENSE_WD_CONTEXT_PTR_SIZE                                          (sizeof(cy_capsense_context.ptrWdContext))
+
+#define CY_CAPSENSE_PIN_CONFIG_PTR_VALUE                                         (cy_capsense_context.ptrPinConfig)
+#define CY_CAPSENSE_PIN_CONFIG_PTR_SIZE                                          (sizeof(cy_capsense_context.ptrPinConfig))
+
+#define CY_CAPSENSE_SHIELD_PIN_CONFIG_PTR_VALUE                                  (cy_capsense_context.ptrShieldPinConfig)
+#define CY_CAPSENSE_SHIELD_PIN_CONFIG_PTR_SIZE                                   (sizeof(cy_capsense_context.ptrShieldPinConfig))
+
+#define CY_CAPSENSE_ACTIVE_SCAN_SNS_PTR_VALUE                                    (cy_capsense_context.ptrActiveScanSns)
+#define CY_CAPSENSE_ACTIVE_SCAN_SNS_PTR_SIZE                                     (sizeof(cy_capsense_context.ptrActiveScanSns))
+
+#if (CY_CAPSENSE_MW_VERSION < 300)
+#define CY_CAPSENSE_FPTR_CONFIG_PTR_VALUE                                        (cy_capsense_context.ptrFptrConfig)
+#define CY_CAPSENSE_FPTR_CONFIG_PTR_SIZE                                         (sizeof(cy_capsense_context.ptrFptrConfig))
+#endif
+
+#define CY_CAPSENSE_BIST_CONTEXT_PTR_VALUE                                       (cy_capsense_context.ptrBistContext)
+#define CY_CAPSENSE_BIST_CONTEXT_PTR_SIZE                                        (sizeof(cy_capsense_context.ptrBistContext))
+
+/* cy_capsense_commonConfig */
+#define CY_CAPSENSE_CPU_CLK_HZ_VALUE                                             (cy_capsense_context.ptrCommonConfig->cpuClkHz)
+#define CY_CAPSENSE_CPU_CLK_HZ_SIZE                                              (sizeof(cy_capsense_context.ptrCommonConfig->cpuClkHz))
+
+#define CY_CAPSENSE_PERI_CLK_HZ_VALUE                                            (cy_capsense_context.ptrCommonConfig->periClkHz)
+#define CY_CAPSENSE_PERI_CLK_HZ_SIZE                                             (sizeof(cy_capsense_context.ptrCommonConfig->periClkHz))
+
+#define CY_CAPSENSE_VDDA_VALUE                                                   (cy_capsense_context.ptrCommonConfig->vdda)
+#define CY_CAPSENSE_VDDA_SIZE                                                    (sizeof(cy_capsense_context.ptrCommonConfig->vdda))
+
+#define CY_CAPSENSE_NUM_PIN_VALUE                                                (cy_capsense_context.ptrCommonConfig->numPin)
+#define CY_CAPSENSE_NUM_PIN_SIZE                                                 (sizeof(cy_capsense_context.ptrCommonConfig->numPin))
+
+#define CY_CAPSENSE_NUM_SNS_VALUE                                                (cy_capsense_context.ptrCommonConfig->numSns)
+#define CY_CAPSENSE_NUM_SNS_SIZE                                                 (sizeof(cy_capsense_context.ptrCommonConfig->numSns))
+
+#define CY_CAPSENSE_NUM_WD_VALUE                                                 (cy_capsense_context.ptrCommonConfig->numWd)
+#define CY_CAPSENSE_NUM_WD_SIZE                                                  (sizeof(cy_capsense_context.ptrCommonConfig->numWd))
+
+#define CY_CAPSENSE_CSD_EN_VALUE                                                 (cy_capsense_context.ptrCommonConfig->csdEn)
+#define CY_CAPSENSE_CSD_EN_SIZE                                                  (sizeof(cy_capsense_context.ptrCommonConfig->csdEn))
+
+#define CY_CAPSENSE_CSX_EN_VALUE                                                 (cy_capsense_context.ptrCommonConfig->csxEn)
+#define CY_CAPSENSE_CSX_EN_SIZE                                                  (sizeof(cy_capsense_context.ptrCommonConfig->csxEn))
+
+#if (CY_CAPSENSE_MW_VERSION < 300)
+#define CY_CAPSENSE_MFS_EN_VALUE                                                 (cy_capsense_context.ptrCommonConfig->mfsEn)
+#define CY_CAPSENSE_MFS_EN_SIZE                                                  (sizeof(cy_capsense_context.ptrCommonConfig->mfsEn))
+#endif
+
+#define CY_CAPSENSE_BIST_EN_VALUE                                                (cy_capsense_context.ptrCommonConfig->bistEn)
+#define CY_CAPSENSE_BIST_EN_SIZE                                                 (sizeof(cy_capsense_context.ptrCommonConfig->bistEn))
+
+#define CY_CAPSENSE_POSITION_FILTER_EN_VALUE                                     (cy_capsense_context.ptrCommonConfig->positionFilterEn)
+#define CY_CAPSENSE_POSITION_FILTER_EN_SIZE                                      (sizeof(cy_capsense_context.ptrCommonConfig->positionFilterEn))
+
+#define CY_CAPSENSE_PERI_DIVIDER_TYPE_VALUE                                      (cy_capsense_context.ptrCommonConfig->periDividerType)
+#define CY_CAPSENSE_PERI_DIVIDER_TYPE_SIZE                                       (sizeof(cy_capsense_context.ptrCommonConfig->periDividerType))
+
+#define CY_CAPSENSE_PERI_DIVIDER_INDEX_VALUE                                     (cy_capsense_context.ptrCommonConfig->periDividerIndex)
+#define CY_CAPSENSE_PERI_DIVIDER_INDEX_SIZE                                      (sizeof(cy_capsense_context.ptrCommonConfig->periDividerIndex))
+
+#define CY_CAPSENSE_ANALOG_WAKEUP_DELAY_VALUE                                    (cy_capsense_context.ptrCommonConfig->analogWakeupDelay)
+#define CY_CAPSENSE_ANALOG_WAKEUP_DELAY_SIZE                                     (sizeof(cy_capsense_context.ptrCommonConfig->analogWakeupDelay))
+
+#define CY_CAPSENSE_SS_IREF_SOURCE_VALUE                                         (cy_capsense_context.ptrCommonConfig->ssIrefSource)
+#define CY_CAPSENSE_SS_IREF_SOURCE_SIZE                                          (sizeof(cy_capsense_context.ptrCommonConfig->ssIrefSource))
+
+#define CY_CAPSENSE_SS_VREF_SOURCE_VALUE                                         (cy_capsense_context.ptrCommonConfig->ssVrefSource)
+#define CY_CAPSENSE_SS_VREF_SOURCE_SIZE                                          (sizeof(cy_capsense_context.ptrCommonConfig->ssVrefSource))
+
+#define CY_CAPSENSE_PROX_TOUCH_COEFF_VALUE                                       (cy_capsense_context.ptrCommonConfig->proxTouchCoeff)
+#define CY_CAPSENSE_PROX_TOUCH_COEFF_SIZE                                        (sizeof(cy_capsense_context.ptrCommonConfig->proxTouchCoeff))
+
+#define CY_CAPSENSE_SW_SENSOR_AUTO_RESET_EN_VALUE                                (cy_capsense_context.ptrCommonConfig->swSensorAutoResetEn)
+#define CY_CAPSENSE_SW_SENSOR_AUTO_RESET_EN_SIZE                                 (sizeof(cy_capsense_context.ptrCommonConfig->swSensorAutoResetEn))
+
+#define CY_CAPSENSE_PORT_CMOD_PAD_NUM_VALUE                                      (cy_capsense_context.ptrCommonConfig->portCmodPadNum)
+#define CY_CAPSENSE_PORT_CMOD_PAD_NUM_SIZE                                       (sizeof(cy_capsense_context.ptrCommonConfig->portCmodPadNum))
+
+#define CY_CAPSENSE_PIN_CMOD_PAD_VALUE                                           (cy_capsense_context.ptrCommonConfig->pinCmodPad)
+#define CY_CAPSENSE_PIN_CMOD_PAD_SIZE                                            (sizeof(cy_capsense_context.ptrCommonConfig->pinCmodPad))
+
+#define CY_CAPSENSE_PORT_CSH_PAD_NUM_VALUE                                       (cy_capsense_context.ptrCommonConfig->portCshPadNum)
+#define CY_CAPSENSE_PORT_CSH_PAD_NUM_SIZE                                        (sizeof(cy_capsense_context.ptrCommonConfig->portCshPadNum))
+
+#define CY_CAPSENSE_PIN_CSH_PAD_VALUE                                            (cy_capsense_context.ptrCommonConfig->pinCshPad)
+#define CY_CAPSENSE_PIN_CSH_PAD_SIZE                                             (sizeof(cy_capsense_context.ptrCommonConfig->pinCshPad))
+
+#define CY_CAPSENSE_PORT_SHIELD_PAD_NUM_VALUE                                    (cy_capsense_context.ptrCommonConfig->portShieldPadNum)
+#define CY_CAPSENSE_PORT_SHIELD_PAD_NUM_SIZE                                     (sizeof(cy_capsense_context.ptrCommonConfig->portShieldPadNum))
+
+#define CY_CAPSENSE_PIN_SHIELD_PAD_VALUE                                         (cy_capsense_context.ptrCommonConfig->pinShieldPad)
+#define CY_CAPSENSE_PIN_SHIELD_PAD_SIZE                                          (sizeof(cy_capsense_context.ptrCommonConfig->pinShieldPad))
+
+#define CY_CAPSENSE_PORT_VREF_EXT_PAD_NUM_VALUE                                  (cy_capsense_context.ptrCommonConfig->portVrefExtPadNum)
+#define CY_CAPSENSE_PORT_VREF_EXT_PAD_NUM_SIZE                                   (sizeof(cy_capsense_context.ptrCommonConfig->portVrefExtPadNum))
+
+#define CY_CAPSENSE_PIN_VREF_EXT_PAD_VALUE                                       (cy_capsense_context.ptrCommonConfig->pinVrefExtPad)
+#define CY_CAPSENSE_PIN_VREF_EXT_PAD_SIZE                                        (sizeof(cy_capsense_context.ptrCommonConfig->pinVrefExtPad))
+
+#define CY_CAPSENSE_PORT_CMOD_NUM_VALUE                                          (cy_capsense_context.ptrCommonConfig->portCmodNum)
+#define CY_CAPSENSE_PORT_CMOD_NUM_SIZE                                           (sizeof(cy_capsense_context.ptrCommonConfig->portCmodNum))
+
+#define CY_CAPSENSE_IDAC_GAIN_TABLE_PTR_VALUE                                    (&cy_capsense_context.ptrCommonConfig->idacGainTable[0u])
+#define CY_CAPSENSE_IDAC_GAIN_TABLE_PTR_SIZE                                     (sizeof(&cy_capsense_context.ptrCommonConfig->idacGainTable[0u]))
+
+#define CY_CAPSENSE_PTR_CSD_BASE_VALUE                                           (cy_capsense_context.ptrCommonConfig->ptrCsdBase)
+#define CY_CAPSENSE_PTR_CSD_BASE_SIZE                                            (sizeof(cy_capsense_context.ptrCommonConfig->ptrCsdBase))
+
+#define CY_CAPSENSE_PTR_CSD_CONTEXT_VALUE                                        (cy_capsense_context.ptrCommonConfig->ptrCsdContext)
+#define CY_CAPSENSE_PTR_CSD_CONTEXT_SIZE                                         (sizeof(cy_capsense_context.ptrCommonConfig->ptrCsdContext))
+
+#define CY_CAPSENSE_PORT_CMOD_VALUE                                              (cy_capsense_context.ptrCommonConfig->portCmod)
+#define CY_CAPSENSE_PORT_CMOD_SIZE                                               (sizeof(cy_capsense_context.ptrCommonConfig->portCmod))
+
+#define CY_CAPSENSE_PORT_CSH_VALUE                                               (cy_capsense_context.ptrCommonConfig->portCsh)
+#define CY_CAPSENSE_PORT_CSH_SIZE                                                (sizeof(cy_capsense_context.ptrCommonConfig->portCsh))
+
+#define CY_CAPSENSE_PORT_CINT_A_VALUE                                            (cy_capsense_context.ptrCommonConfig->portCintA)
+#define CY_CAPSENSE_PORT_CINT_A_SIZE                                             (sizeof(cy_capsense_context.ptrCommonConfig->portCintA))
+
+#define CY_CAPSENSE_PORT_CINT_B_VALUE                                            (cy_capsense_context.ptrCommonConfig->portCintB)
+#define CY_CAPSENSE_PORT_CINT_B_SIZE                                             (sizeof(cy_capsense_context.ptrCommonConfig->portCintB))
+
+#define CY_CAPSENSE_PIN_CMOD_VALUE                                               (cy_capsense_context.ptrCommonConfig->pinCmod)
+#define CY_CAPSENSE_PIN_CMOD_SIZE                                                (sizeof(cy_capsense_context.ptrCommonConfig->pinCmod))
+
+#define CY_CAPSENSE_PORT_CSH_NUM_VALUE                                           (cy_capsense_context.ptrCommonConfig->portCshNum)
+#define CY_CAPSENSE_PORT_CSH_NUM_SIZE                                            (sizeof(cy_capsense_context.ptrCommonConfig->portCshNum))
+
+#define CY_CAPSENSE_PIN_CSH_VALUE                                                (cy_capsense_context.ptrCommonConfig->pinCsh)
+#define CY_CAPSENSE_PIN_CSH_SIZE                                                 (sizeof(cy_capsense_context.ptrCommonConfig->pinCsh))
+
+#define CY_CAPSENSE_PIN_CINT_A_VALUE                                             (cy_capsense_context.ptrCommonConfig->pinCintA)
+#define CY_CAPSENSE_PIN_CINT_A_SIZE                                              (sizeof(cy_capsense_context.ptrCommonConfig->pinCintA))
+
+#define CY_CAPSENSE_PIN_CINT_B_VALUE                                             (cy_capsense_context.ptrCommonConfig->pinCintB)
+#define CY_CAPSENSE_PIN_CINT_B_SIZE                                              (sizeof(cy_capsense_context.ptrCommonConfig->pinCintB))
+
+#define CY_CAPSENSE_CSD_SHIELD_EN_VALUE                                          (cy_capsense_context.ptrCommonConfig->csdShieldEn)
+#define CY_CAPSENSE_CSD_SHIELD_EN_SIZE                                           (sizeof(cy_capsense_context.ptrCommonConfig->csdShieldEn))
+
+#define CY_CAPSENSE_CSD_INACTIVE_SNS_CONNECTION_VALUE                            (cy_capsense_context.ptrCommonConfig->csdInactiveSnsConnection)
+#define CY_CAPSENSE_CSD_INACTIVE_SNS_CONNECTION_SIZE                             (sizeof(cy_capsense_context.ptrCommonConfig->csdInactiveSnsConnection))
+
+#if (CY_CAPSENSE_MW_VERSION >= 300)
+#define CY_CAPSENSE_CSX_INACTIVE_SNS_CONNECTION_VALUE                            (cy_capsense_context.ptrCommonConfig->csxInactiveSnsConnection)
+#define CY_CAPSENSE_CSX_INACTIVE_SNS_CONNECTION_SIZE                             (sizeof(cy_capsense_context.ptrCommonConfig->csxInactiveSnsConnection))
+#endif
+
+#define CY_CAPSENSE_CSD_SHIELD_DELAY_VALUE                                       (cy_capsense_context.ptrCommonConfig->csdShieldDelay)
+#define CY_CAPSENSE_CSD_SHIELD_DELAY_SIZE                                        (sizeof(cy_capsense_context.ptrCommonConfig->csdShieldDelay))
+
+#define CY_CAPSENSE_CSD_VREF_VALUE                                               (cy_capsense_context.ptrCommonConfig->csdVref)
+#define CY_CAPSENSE_CSD_VREF_SIZE                                                (sizeof(cy_capsense_context.ptrCommonConfig->csdVref))
+
+#define CY_CAPSENSE_CSD_R_CONST_VALUE                                            (cy_capsense_context.ptrCommonConfig->csdRConst)
+#define CY_CAPSENSE_CSD_R_CONST_SIZE                                             (sizeof(cy_capsense_context.ptrCommonConfig->csdRConst))
+
+#define CY_CAPSENSE_CSD_C_TANK_SHIELD_EN_VALUE                                   (cy_capsense_context.ptrCommonConfig->csdCTankShieldEn)
+#define CY_CAPSENSE_CSD_C_TANK_SHIELD_EN_SIZE                                    (sizeof(cy_capsense_context.ptrCommonConfig->csdCTankShieldEn))
+
+#define CY_CAPSENSE_CSD_SHIELD_NUM_PIN_VALUE                                     (cy_capsense_context.ptrCommonConfig->csdShieldNumPin)
+#define CY_CAPSENSE_CSD_SHIELD_NUM_PIN_SIZE                                      (sizeof(cy_capsense_context.ptrCommonConfig->csdShieldNumPin))
+
+#define CY_CAPSENSE_CSD_SHIELD_SW_RES_VALUE                                      (cy_capsense_context.ptrCommonConfig->csdShieldSwRes)
+#define CY_CAPSENSE_CSD_SHIELD_SW_RES_SIZE                                       (sizeof(cy_capsense_context.ptrCommonConfig->csdShieldSwRes))
+
+#define CY_CAPSENSE_CSD_INIT_SW_RES_VALUE                                        (cy_capsense_context.ptrCommonConfig->csdInitSwRes)
+#define CY_CAPSENSE_CSD_INIT_SW_RES_SIZE                                         (sizeof(cy_capsense_context.ptrCommonConfig->csdInitSwRes))
+
+#define CY_CAPSENSE_CSD_CHARGE_TRANSFER_VALUE                                    (cy_capsense_context.ptrCommonConfig->csdChargeTransfer)
+#define CY_CAPSENSE_CSD_CHARGE_TRANSFER_SIZE                                     (sizeof(cy_capsense_context.ptrCommonConfig->csdChargeTransfer))
+
+#define CY_CAPSENSE_CSD_RAW_TARGET_VALUE                                         (cy_capsense_context.ptrCommonConfig->csdRawTarget)
+#define CY_CAPSENSE_CSD_RAW_TARGET_SIZE                                          (sizeof(cy_capsense_context.ptrCommonConfig->csdRawTarget))
+
+#define CY_CAPSENSE_CSD_AUTOTUNE_EN_VALUE                                        (cy_capsense_context.ptrCommonConfig->csdAutotuneEn)
+#define CY_CAPSENSE_CSD_AUTOTUNE_EN_SIZE                                         (sizeof(cy_capsense_context.ptrCommonConfig->csdAutotuneEn))
+
+#define CY_CAPSENSE_CSD_IDAC_AUTOCAL_EN_VALUE                                    (cy_capsense_context.ptrCommonConfig->csdIdacAutocalEn)
+#define CY_CAPSENSE_CSD_IDAC_AUTOCAL_EN_SIZE                                     (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacAutocalEn))
+
+#define CY_CAPSENSE_CSD_IDAC_AUTO_GAIN_EN_VALUE                                  (cy_capsense_context.ptrCommonConfig->csdIdacAutoGainEn)
+#define CY_CAPSENSE_CSD_IDAC_AUTO_GAIN_EN_SIZE                                   (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacAutoGainEn))
+
+#define CY_CAPSENSE_CSD_CALIBRATION_ERROR_VALUE                                  (cy_capsense_context.ptrCommonConfig->csdCalibrationError)
+#define CY_CAPSENSE_CSD_CALIBRATION_ERROR_SIZE                                   (sizeof(cy_capsense_context.ptrCommonConfig->csdCalibrationError))
+
+#define CY_CAPSENSE_CSD_IDAC_GAIN_INIT_INDEX_VALUE                               (cy_capsense_context.ptrCommonConfig->csdIdacGainInitIndex)
+#define CY_CAPSENSE_CSD_IDAC_GAIN_INIT_INDEX_SIZE                                (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacGainInitIndex))
+
+#define CY_CAPSENSE_CSD_IDAC_MIN_VALUE                                           (cy_capsense_context.ptrCommonConfig->csdIdacMin)
+#define CY_CAPSENSE_CSD_IDAC_MIN_SIZE                                            (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacMin))
+
+#define CY_CAPSENSE_CSD_IDAC_COMP_EN_VALUE                                       (cy_capsense_context.ptrCommonConfig->csdIdacCompEn)
+#define CY_CAPSENSE_CSD_IDAC_COMP_EN_SIZE                                        (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacCompEn))
+
+#define CY_CAPSENSE_CSD_FINE_INIT_TIME_VALUE                                     (cy_capsense_context.ptrCommonConfig->csdFineInitTime)
+#define CY_CAPSENSE_CSD_FINE_INIT_TIME_SIZE                                      (sizeof(cy_capsense_context.ptrCommonConfig->csdFineInitTime))
+
+#define CY_CAPSENSE_CSD_IDAC_ROW_COL_ALIGN_EN_VALUE                              (cy_capsense_context.ptrCommonConfig->csdIdacRowColAlignEn)
+#define CY_CAPSENSE_CSD_IDAC_ROW_COL_ALIGN_EN_SIZE                               (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacRowColAlignEn))
+
+#define CY_CAPSENSE_CSD_MFS_DIVIDER_OFFSET_F1_VALUE                              (cy_capsense_context.ptrCommonConfig->csdMfsDividerOffsetF1)
+#define CY_CAPSENSE_CSD_MFS_DIVIDER_OFFSET_F1_SIZE                               (sizeof(cy_capsense_context.ptrCommonConfig->csdMfsDividerOffsetF1))
+
+#define CY_CAPSENSE_CSD_MFS_DIVIDER_OFFSET_F2_VALUE                              (cy_capsense_context.ptrCommonConfig->csdMfsDividerOffsetF2)
+#define CY_CAPSENSE_CSD_MFS_DIVIDER_OFFSET_F2_SIZE                               (sizeof(cy_capsense_context.ptrCommonConfig->csdMfsDividerOffsetF2))
+
+#define CY_CAPSENSE_CSX_RAW_TARGET_VALUE                                         (cy_capsense_context.ptrCommonConfig->csxRawTarget)
+#define CY_CAPSENSE_CSX_RAW_TARGET_SIZE                                          (sizeof(cy_capsense_context.ptrCommonConfig->csxRawTarget))
+
+#define CY_CAPSENSE_CSX_IDAC_GAIN_INIT_INDEX_VALUE                               (cy_capsense_context.ptrCommonConfig->csxIdacGainInitIndex)
+#define CY_CAPSENSE_CSX_IDAC_GAIN_INIT_INDEX_SIZE                                (sizeof(cy_capsense_context.ptrCommonConfig->csxIdacGainInitIndex))
+
+#define CY_CAPSENSE_CSX_REF_GAIN_VALUE                                           (cy_capsense_context.ptrCommonConfig->csxRefGain)
+#define CY_CAPSENSE_CSX_REF_GAIN_SIZE                                            (sizeof(cy_capsense_context.ptrCommonConfig->csxRefGain))
+
+#define CY_CAPSENSE_CSX_IDAC_AUTOCAL_EN_VALUE                                    (cy_capsense_context.ptrCommonConfig->csxIdacAutocalEn)
+#define CY_CAPSENSE_CSX_IDAC_AUTOCAL_EN_SIZE                                     (sizeof(cy_capsense_context.ptrCommonConfig->csxIdacAutocalEn))
+
+#define CY_CAPSENSE_CSX_CALIBRATION_ERROR_VALUE                                  (cy_capsense_context.ptrCommonConfig->csxCalibrationError)
+#define CY_CAPSENSE_CSX_CALIBRATION_ERROR_SIZE                                   (sizeof(cy_capsense_context.ptrCommonConfig->csxCalibrationError))
+
+#define CY_CAPSENSE_CSX_FINE_INIT_TIME_VALUE                                     (cy_capsense_context.ptrCommonConfig->csxFineInitTime)
+#define CY_CAPSENSE_CSX_FINE_INIT_TIME_SIZE                                      (sizeof(cy_capsense_context.ptrCommonConfig->csxFineInitTime))
+
+#define CY_CAPSENSE_CSX_INIT_SW_RES_VALUE                                        (cy_capsense_context.ptrCommonConfig->csxInitSwRes)
+#define CY_CAPSENSE_CSX_INIT_SW_RES_SIZE                                         (sizeof(cy_capsense_context.ptrCommonConfig->csxInitSwRes))
+
+#define CY_CAPSENSE_CSX_SCAN_SW_RES_VALUE                                        (cy_capsense_context.ptrCommonConfig->csxScanSwRes)
+#define CY_CAPSENSE_CSX_SCAN_SW_RES_SIZE                                         (sizeof(cy_capsense_context.ptrCommonConfig->csxScanSwRes))
+
+#define CY_CAPSENSE_CSX_INIT_SHIELD_SW_RES_VALUE                                 (cy_capsense_context.ptrCommonConfig->csxInitShieldSwRes)
+#define CY_CAPSENSE_CSX_INIT_SHIELD_SW_RES_SIZE                                  (sizeof(cy_capsense_context.ptrCommonConfig->csxInitShieldSwRes))
+
+#define CY_CAPSENSE_CSX_SCAN_SHIELD_SW_RES_VALUE                                 (cy_capsense_context.ptrCommonConfig->csxScanShieldSwRes)
+#define CY_CAPSENSE_CSX_SCAN_SHIELD_SW_RES_SIZE                                  (sizeof(cy_capsense_context.ptrCommonConfig->csxScanShieldSwRes))
+
+#define CY_CAPSENSE_CSX_MFS_DIVIDER_OFFSET_F1_VALUE                              (cy_capsense_context.ptrCommonConfig->csxMfsDividerOffsetF1)
+#define CY_CAPSENSE_CSX_MFS_DIVIDER_OFFSET_F1_SIZE                               (sizeof(cy_capsense_context.ptrCommonConfig->csxMfsDividerOffsetF1))
+
+#define CY_CAPSENSE_CSX_MFS_DIVIDER_OFFSET_F2_VALUE                              (cy_capsense_context.ptrCommonConfig->csxMfsDividerOffsetF2)
+#define CY_CAPSENSE_CSX_MFS_DIVIDER_OFFSET_F2_SIZE                               (sizeof(cy_capsense_context.ptrCommonConfig->csxMfsDividerOffsetF2))
+
+/* cy_capsense_widgetConfig */
+#define CY_CAPSENSE_BUTTON0_PTR_WD_CONTEXT_VALUE                                 (cy_capsense_context.ptrWdConfig[0u].ptrWdContext)
+#define CY_CAPSENSE_BUTTON0_PTR_WD_CONTEXT_SIZE                                  (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrWdContext))
+#define CY_CAPSENSE_BUTTON0_PTR_SNS_CONTEXT_VALUE                                (cy_capsense_context.ptrWdConfig[0u].ptrSnsContext)
+#define CY_CAPSENSE_BUTTON0_PTR_SNS_CONTEXT_SIZE                                 (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrSnsContext))
+#define CY_CAPSENSE_BUTTON0_PTR_ELTD_CONTEXT_VALUE                               (cy_capsense_context.ptrWdConfig[0u].ptrEltdConfig)
+#define CY_CAPSENSE_BUTTON0_PTR_ELTD_CONTEXT_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrEltdConfig))
+#define CY_CAPSENSE_BUTTON0_PTR_ELTD_CAPACITANCE_VALUE                           (cy_capsense_context.ptrWdConfig[0u].ptrEltdCapacitance)
+#define CY_CAPSENSE_BUTTON0_PTR_ELTD_CAPACITANCE_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrEltdCapacitance))
+#define CY_CAPSENSE_BUTTON0_PTR_BSLN_INV_VALUE                                   (cy_capsense_context.ptrWdConfig[0u].ptrBslnInv)
+#define CY_CAPSENSE_BUTTON0_PTR_BSLN_INV_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrBslnInv))
+#define CY_CAPSENSE_BUTTON0_PTR_NOISE_ENVELOPE_VALUE                             (cy_capsense_context.ptrWdConfig[0u].ptrNoiseEnvelope)
+#define CY_CAPSENSE_BUTTON0_PTR_NOISE_ENVELOPE_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrNoiseEnvelope))
+#define CY_CAPSENSE_BUTTON0_PTR_RAW_FILTER_HISTORY_VALUE                         (cy_capsense_context.ptrWdConfig[0u].ptrRawFilterHistory)
+#define CY_CAPSENSE_BUTTON0_PTR_RAW_FILTER_HISTORY_SIZE                          (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrRawFilterHistory))
+#define CY_CAPSENSE_BUTTON0_PTR_RAW_FILTER_HISTORY_LOW_VALUE                     (cy_capsense_context.ptrWdConfig[0u].ptrRawFilterHistoryLow)
+#define CY_CAPSENSE_BUTTON0_PTR_RAW_FILTER_HISTORY_LOW_SIZE                      (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrRawFilterHistoryLow))
+#define CY_CAPSENSE_BUTTON0_IIR_COEFF_VALUE                                      (cy_capsense_context.ptrWdConfig[0u].iirCoeff)
+#define CY_CAPSENSE_BUTTON0_IIR_COEFF_SIZE                                       (sizeof(cy_capsense_context.ptrWdConfig[0u].iirCoeff))
+#define CY_CAPSENSE_BUTTON0_PTR_DEBOUNCE_ARR_VALUE                               (cy_capsense_context.ptrWdConfig[0u].ptrDebounceArr)
+#define CY_CAPSENSE_BUTTON0_PTR_DEBOUNCE_ARR_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrDebounceArr))
+#define CY_CAPSENSE_BUTTON0_PTR_DIPLEX_TABLE_VALUE                               (cy_capsense_context.ptrWdConfig[0u].ptrDiplexTable)
+#define CY_CAPSENSE_BUTTON0_PTR_DIPLEX_TABLE_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrDiplexTable))
+#define CY_CAPSENSE_BUTTON0_CENTROID_CONFIG_VALUE                                (cy_capsense_context.ptrWdConfig[0u].centroidConfig)
+#define CY_CAPSENSE_BUTTON0_CENTROID_CONFIG_SIZE                                 (sizeof(cy_capsense_context.ptrWdConfig[0u].centroidConfig))
+#define CY_CAPSENSE_BUTTON0_X_RESOLUTION_VALUE                                   (cy_capsense_context.ptrWdConfig[0u].xResolution)
+#define CY_CAPSENSE_BUTTON0_X_RESOLUTION_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[0u].xResolution))
+#define CY_CAPSENSE_BUTTON0_Y_RESOLUTION_VALUE                                   (cy_capsense_context.ptrWdConfig[0u].yResolution)
+#define CY_CAPSENSE_BUTTON0_Y_RESOLUTION_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[0u].yResolution))
+#define CY_CAPSENSE_BUTTON0_NUM_SNS_VALUE                                        (cy_capsense_context.ptrWdConfig[0u].numSns)
+#define CY_CAPSENSE_BUTTON0_NUM_SNS_SIZE                                         (sizeof(cy_capsense_context.ptrWdConfig[0u].numSns))
+#define CY_CAPSENSE_BUTTON0_NUM_COLS_VALUE                                       (cy_capsense_context.ptrWdConfig[0u].numCols)
+#define CY_CAPSENSE_BUTTON0_NUM_COLS_SIZE                                        (sizeof(cy_capsense_context.ptrWdConfig[0u].numCols))
+#define CY_CAPSENSE_BUTTON0_NUM_ROWS_VALUE                                       (cy_capsense_context.ptrWdConfig[0u].numRows)
+#define CY_CAPSENSE_BUTTON0_NUM_ROWS_SIZE                                        (sizeof(cy_capsense_context.ptrWdConfig[0u].numRows))
+#define CY_CAPSENSE_BUTTON0_PTR_POS_FILTER_HISTORY_VALUE                         (cy_capsense_context.ptrWdConfig[0u].ptrPosFilterHistory)
+#define CY_CAPSENSE_BUTTON0_PTR_POS_FILTER_HISTORY_SIZE                          (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrPosFilterHistory))
+#define CY_CAPSENSE_BUTTON0_PTR_CSX_TOUCH_HISTORY_VALUE                          (cy_capsense_context.ptrWdConfig[0u].ptrCsxTouchHistory)
+#define CY_CAPSENSE_BUTTON0_PTR_CSX_TOUCH_HISTORY_SIZE                           (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrCsxTouchHistory))
+#define CY_CAPSENSE_BUTTON0_PTR_CSX_TOUCH_BUFFER_VALUE                           (cy_capsense_context.ptrWdConfig[0u].ptrCsxTouchBuffer)
+#define CY_CAPSENSE_BUTTON0_PTR_CSX_TOUCH_BUFFER_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrCsxTouchBuffer))
+#define CY_CAPSENSE_BUTTON0_PTR_CSD_TOUCH_BUFFER_VALUE                           (cy_capsense_context.ptrWdConfig[0u].ptrCsdTouchBuffer)
+#define CY_CAPSENSE_BUTTON0_PTR_CSD_TOUCH_BUFFER_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrCsdTouchBuffer))
+#define CY_CAPSENSE_BUTTON0_PTR_GESTURE_CONFIG_VALUE                             (cy_capsense_context.ptrWdConfig[0u].ptrGestureConfig)
+#define CY_CAPSENSE_BUTTON0_PTR_GESTURE_CONFIG_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrGestureConfig))
+#define CY_CAPSENSE_BUTTON0_PTR_GESTURE_CONTEXT_VALUE                            (cy_capsense_context.ptrWdConfig[0u].ptrGestureContext)
+#define CY_CAPSENSE_BUTTON0_PTR_GESTURE_CONTEXT_SIZE                             (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrGestureContext))
+#define CY_CAPSENSE_BUTTON0_BALLISTIC_CONFIG_VALUE                               (cy_capsense_context.ptrWdConfig[0u].ballisticConfig)
+#define CY_CAPSENSE_BUTTON0_BALLISTIC_CONFIG_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[0u].ballisticConfig))
+#define CY_CAPSENSE_BUTTON0_PTR_BALLISTIC_CONTEXT_VALUE                          (cy_capsense_context.ptrWdConfig[0u].ptrBallisticContext)
+#define CY_CAPSENSE_BUTTON0_PTR_BALLISTIC_CONTEXT_SIZE                           (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrBallisticContext))
+#define CY_CAPSENSE_BUTTON0_AIIR_CONFIG_VALUE                                    (cy_capsense_context.ptrWdConfig[0u].aiirConfig)
+#define CY_CAPSENSE_BUTTON0_AIIR_CONFIG_SIZE                                     (sizeof(cy_capsense_context.ptrWdConfig[0u].aiirConfig))
+#define CY_CAPSENSE_BUTTON0_ADV_CONFIG_VALUE                                     (cy_capsense_context.ptrWdConfig[0u].advConfig)
+#define CY_CAPSENSE_BUTTON0_ADV_CONFIG_SIZE                                      (sizeof(cy_capsense_context.ptrWdConfig[0u].advConfig))
+#define CY_CAPSENSE_BUTTON0_POS_FILTER_CONFIG_VALUE                              (cy_capsense_context.ptrWdConfig[0u].posFilterConfig)
+#define CY_CAPSENSE_BUTTON0_POS_FILTER_CONFIG_SIZE                               (sizeof(cy_capsense_context.ptrWdConfig[0u].posFilterConfig))
+#define CY_CAPSENSE_BUTTON0_RAW_FILTER_CONFIG_VALUE                              (cy_capsense_context.ptrWdConfig[0u].rawFilterConfig)
+#define CY_CAPSENSE_BUTTON0_RAW_FILTER_CONFIG_SIZE                               (sizeof(cy_capsense_context.ptrWdConfig[0u].rawFilterConfig))
+#define CY_CAPSENSE_BUTTON0_SENSE_METHOD_VALUE                                   (cy_capsense_context.ptrWdConfig[0u].senseMethod)
+#define CY_CAPSENSE_BUTTON0_SENSE_METHOD_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[0u].senseMethod))
+#define CY_CAPSENSE_BUTTON0_WD_TYPE_VALUE                                        (cy_capsense_context.ptrWdConfig[0u].wdType)
+#define CY_CAPSENSE_BUTTON0_WD_TYPE_SIZE                                         (sizeof(cy_capsense_context.ptrWdConfig[0u].wdType))
+
+#define CY_CAPSENSE_BUTTON1_PTR_WD_CONTEXT_VALUE                                 (cy_capsense_context.ptrWdConfig[1u].ptrWdContext)
+#define CY_CAPSENSE_BUTTON1_PTR_WD_CONTEXT_SIZE                                  (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrWdContext))
+#define CY_CAPSENSE_BUTTON1_PTR_SNS_CONTEXT_VALUE                                (cy_capsense_context.ptrWdConfig[1u].ptrSnsContext)
+#define CY_CAPSENSE_BUTTON1_PTR_SNS_CONTEXT_SIZE                                 (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrSnsContext))
+#define CY_CAPSENSE_BUTTON1_PTR_ELTD_CONTEXT_VALUE                               (cy_capsense_context.ptrWdConfig[1u].ptrEltdConfig)
+#define CY_CAPSENSE_BUTTON1_PTR_ELTD_CONTEXT_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrEltdConfig))
+#define CY_CAPSENSE_BUTTON1_PTR_ELTD_CAPACITANCE_VALUE                           (cy_capsense_context.ptrWdConfig[1u].ptrEltdCapacitance)
+#define CY_CAPSENSE_BUTTON1_PTR_ELTD_CAPACITANCE_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrEltdCapacitance))
+#define CY_CAPSENSE_BUTTON1_PTR_BSLN_INV_VALUE                                   (cy_capsense_context.ptrWdConfig[1u].ptrBslnInv)
+#define CY_CAPSENSE_BUTTON1_PTR_BSLN_INV_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrBslnInv))
+#define CY_CAPSENSE_BUTTON1_PTR_NOISE_ENVELOPE_VALUE                             (cy_capsense_context.ptrWdConfig[1u].ptrNoiseEnvelope)
+#define CY_CAPSENSE_BUTTON1_PTR_NOISE_ENVELOPE_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrNoiseEnvelope))
+#define CY_CAPSENSE_BUTTON1_PTR_RAW_FILTER_HISTORY_VALUE                         (cy_capsense_context.ptrWdConfig[1u].ptrRawFilterHistory)
+#define CY_CAPSENSE_BUTTON1_PTR_RAW_FILTER_HISTORY_SIZE                          (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrRawFilterHistory))
+#define CY_CAPSENSE_BUTTON1_PTR_RAW_FILTER_HISTORY_LOW_VALUE                     (cy_capsense_context.ptrWdConfig[1u].ptrRawFilterHistoryLow)
+#define CY_CAPSENSE_BUTTON1_PTR_RAW_FILTER_HISTORY_LOW_SIZE                      (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrRawFilterHistoryLow))
+#define CY_CAPSENSE_BUTTON1_IIR_COEFF_VALUE                                      (cy_capsense_context.ptrWdConfig[1u].iirCoeff)
+#define CY_CAPSENSE_BUTTON1_IIR_COEFF_SIZE                                       (sizeof(cy_capsense_context.ptrWdConfig[1u].iirCoeff))
+#define CY_CAPSENSE_BUTTON1_PTR_DEBOUNCE_ARR_VALUE                               (cy_capsense_context.ptrWdConfig[1u].ptrDebounceArr)
+#define CY_CAPSENSE_BUTTON1_PTR_DEBOUNCE_ARR_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrDebounceArr))
+#define CY_CAPSENSE_BUTTON1_PTR_DIPLEX_TABLE_VALUE                               (cy_capsense_context.ptrWdConfig[1u].ptrDiplexTable)
+#define CY_CAPSENSE_BUTTON1_PTR_DIPLEX_TABLE_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrDiplexTable))
+#define CY_CAPSENSE_BUTTON1_CENTROID_CONFIG_VALUE                                (cy_capsense_context.ptrWdConfig[1u].centroidConfig)
+#define CY_CAPSENSE_BUTTON1_CENTROID_CONFIG_SIZE                                 (sizeof(cy_capsense_context.ptrWdConfig[1u].centroidConfig))
+#define CY_CAPSENSE_BUTTON1_X_RESOLUTION_VALUE                                   (cy_capsense_context.ptrWdConfig[1u].xResolution)
+#define CY_CAPSENSE_BUTTON1_X_RESOLUTION_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[1u].xResolution))
+#define CY_CAPSENSE_BUTTON1_Y_RESOLUTION_VALUE                                   (cy_capsense_context.ptrWdConfig[1u].yResolution)
+#define CY_CAPSENSE_BUTTON1_Y_RESOLUTION_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[1u].yResolution))
+#define CY_CAPSENSE_BUTTON1_NUM_SNS_VALUE                                        (cy_capsense_context.ptrWdConfig[1u].numSns)
+#define CY_CAPSENSE_BUTTON1_NUM_SNS_SIZE                                         (sizeof(cy_capsense_context.ptrWdConfig[1u].numSns))
+#define CY_CAPSENSE_BUTTON1_NUM_COLS_VALUE                                       (cy_capsense_context.ptrWdConfig[1u].numCols)
+#define CY_CAPSENSE_BUTTON1_NUM_COLS_SIZE                                        (sizeof(cy_capsense_context.ptrWdConfig[1u].numCols))
+#define CY_CAPSENSE_BUTTON1_NUM_ROWS_VALUE                                       (cy_capsense_context.ptrWdConfig[1u].numRows)
+#define CY_CAPSENSE_BUTTON1_NUM_ROWS_SIZE                                        (sizeof(cy_capsense_context.ptrWdConfig[1u].numRows))
+#define CY_CAPSENSE_BUTTON1_PTR_POS_FILTER_HISTORY_VALUE                         (cy_capsense_context.ptrWdConfig[1u].ptrPosFilterHistory)
+#define CY_CAPSENSE_BUTTON1_PTR_POS_FILTER_HISTORY_SIZE                          (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrPosFilterHistory))
+#define CY_CAPSENSE_BUTTON1_PTR_CSX_TOUCH_HISTORY_VALUE                          (cy_capsense_context.ptrWdConfig[1u].ptrCsxTouchHistory)
+#define CY_CAPSENSE_BUTTON1_PTR_CSX_TOUCH_HISTORY_SIZE                           (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrCsxTouchHistory))
+#define CY_CAPSENSE_BUTTON1_PTR_CSX_TOUCH_BUFFER_VALUE                           (cy_capsense_context.ptrWdConfig[1u].ptrCsxTouchBuffer)
+#define CY_CAPSENSE_BUTTON1_PTR_CSX_TOUCH_BUFFER_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrCsxTouchBuffer))
+#define CY_CAPSENSE_BUTTON1_PTR_CSD_TOUCH_BUFFER_VALUE                           (cy_capsense_context.ptrWdConfig[1u].ptrCsdTouchBuffer)
+#define CY_CAPSENSE_BUTTON1_PTR_CSD_TOUCH_BUFFER_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrCsdTouchBuffer))
+#define CY_CAPSENSE_BUTTON1_PTR_GESTURE_CONFIG_VALUE                             (cy_capsense_context.ptrWdConfig[1u].ptrGestureConfig)
+#define CY_CAPSENSE_BUTTON1_PTR_GESTURE_CONFIG_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrGestureConfig))
+#define CY_CAPSENSE_BUTTON1_PTR_GESTURE_CONTEXT_VALUE                            (cy_capsense_context.ptrWdConfig[1u].ptrGestureContext)
+#define CY_CAPSENSE_BUTTON1_PTR_GESTURE_CONTEXT_SIZE                             (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrGestureContext))
+#define CY_CAPSENSE_BUTTON1_BALLISTIC_CONFIG_VALUE                               (cy_capsense_context.ptrWdConfig[1u].ballisticConfig)
+#define CY_CAPSENSE_BUTTON1_BALLISTIC_CONFIG_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[1u].ballisticConfig))
+#define CY_CAPSENSE_BUTTON1_PTR_BALLISTIC_CONTEXT_VALUE                          (cy_capsense_context.ptrWdConfig[1u].ptrBallisticContext)
+#define CY_CAPSENSE_BUTTON1_PTR_BALLISTIC_CONTEXT_SIZE                           (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrBallisticContext))
+#define CY_CAPSENSE_BUTTON1_AIIR_CONFIG_VALUE                                    (cy_capsense_context.ptrWdConfig[1u].aiirConfig)
+#define CY_CAPSENSE_BUTTON1_AIIR_CONFIG_SIZE                                     (sizeof(cy_capsense_context.ptrWdConfig[1u].aiirConfig))
+#define CY_CAPSENSE_BUTTON1_ADV_CONFIG_VALUE                                     (cy_capsense_context.ptrWdConfig[1u].advConfig)
+#define CY_CAPSENSE_BUTTON1_ADV_CONFIG_SIZE                                      (sizeof(cy_capsense_context.ptrWdConfig[1u].advConfig))
+#define CY_CAPSENSE_BUTTON1_POS_FILTER_CONFIG_VALUE                              (cy_capsense_context.ptrWdConfig[1u].posFilterConfig)
+#define CY_CAPSENSE_BUTTON1_POS_FILTER_CONFIG_SIZE                               (sizeof(cy_capsense_context.ptrWdConfig[1u].posFilterConfig))
+#define CY_CAPSENSE_BUTTON1_RAW_FILTER_CONFIG_VALUE                              (cy_capsense_context.ptrWdConfig[1u].rawFilterConfig)
+#define CY_CAPSENSE_BUTTON1_RAW_FILTER_CONFIG_SIZE                               (sizeof(cy_capsense_context.ptrWdConfig[1u].rawFilterConfig))
+#define CY_CAPSENSE_BUTTON1_SENSE_METHOD_VALUE                                   (cy_capsense_context.ptrWdConfig[1u].senseMethod)
+#define CY_CAPSENSE_BUTTON1_SENSE_METHOD_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[1u].senseMethod))
+#define CY_CAPSENSE_BUTTON1_WD_TYPE_VALUE                                        (cy_capsense_context.ptrWdConfig[1u].wdType)
+#define CY_CAPSENSE_BUTTON1_WD_TYPE_SIZE                                         (sizeof(cy_capsense_context.ptrWdConfig[1u].wdType))
+
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_WD_CONTEXT_VALUE                           (cy_capsense_context.ptrWdConfig[2u].ptrWdContext)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_WD_CONTEXT_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrWdContext))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_SNS_CONTEXT_VALUE                          (cy_capsense_context.ptrWdConfig[2u].ptrSnsContext)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_SNS_CONTEXT_SIZE                           (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrSnsContext))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_ELTD_CONTEXT_VALUE                         (cy_capsense_context.ptrWdConfig[2u].ptrEltdConfig)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_ELTD_CONTEXT_SIZE                          (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrEltdConfig))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_ELTD_CAPACITANCE_VALUE                     (cy_capsense_context.ptrWdConfig[2u].ptrEltdCapacitance)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_ELTD_CAPACITANCE_SIZE                      (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrEltdCapacitance))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_BSLN_INV_VALUE                             (cy_capsense_context.ptrWdConfig[2u].ptrBslnInv)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_BSLN_INV_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrBslnInv))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_NOISE_ENVELOPE_VALUE                       (cy_capsense_context.ptrWdConfig[2u].ptrNoiseEnvelope)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_NOISE_ENVELOPE_SIZE                        (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrNoiseEnvelope))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_RAW_FILTER_HISTORY_VALUE                   (cy_capsense_context.ptrWdConfig[2u].ptrRawFilterHistory)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_RAW_FILTER_HISTORY_SIZE                    (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrRawFilterHistory))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_RAW_FILTER_HISTORY_LOW_VALUE               (cy_capsense_context.ptrWdConfig[2u].ptrRawFilterHistoryLow)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_RAW_FILTER_HISTORY_LOW_SIZE                (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrRawFilterHistoryLow))
+#define CY_CAPSENSE_LINEARSLIDER0_IIR_COEFF_VALUE                                (cy_capsense_context.ptrWdConfig[2u].iirCoeff)
+#define CY_CAPSENSE_LINEARSLIDER0_IIR_COEFF_SIZE                                 (sizeof(cy_capsense_context.ptrWdConfig[2u].iirCoeff))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_DEBOUNCE_ARR_VALUE                         (cy_capsense_context.ptrWdConfig[2u].ptrDebounceArr)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_DEBOUNCE_ARR_SIZE                          (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrDebounceArr))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_DIPLEX_TABLE_VALUE                         (cy_capsense_context.ptrWdConfig[2u].ptrDiplexTable)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_DIPLEX_TABLE_SIZE                          (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrDiplexTable))
+#define CY_CAPSENSE_LINEARSLIDER0_CENTROID_CONFIG_VALUE                          (cy_capsense_context.ptrWdConfig[2u].centroidConfig)
+#define CY_CAPSENSE_LINEARSLIDER0_CENTROID_CONFIG_SIZE                           (sizeof(cy_capsense_context.ptrWdConfig[2u].centroidConfig))
+#define CY_CAPSENSE_LINEARSLIDER0_X_RESOLUTION_VALUE                             (cy_capsense_context.ptrWdConfig[2u].xResolution)
+#define CY_CAPSENSE_LINEARSLIDER0_X_RESOLUTION_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2u].xResolution))
+#define CY_CAPSENSE_LINEARSLIDER0_Y_RESOLUTION_VALUE                             (cy_capsense_context.ptrWdConfig[2u].yResolution)
+#define CY_CAPSENSE_LINEARSLIDER0_Y_RESOLUTION_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2u].yResolution))
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_SNS_VALUE                                  (cy_capsense_context.ptrWdConfig[2u].numSns)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_SNS_SIZE                                   (sizeof(cy_capsense_context.ptrWdConfig[2u].numSns))
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_COLS_VALUE                                 (cy_capsense_context.ptrWdConfig[2u].numCols)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_COLS_SIZE                                  (sizeof(cy_capsense_context.ptrWdConfig[2u].numCols))
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_ROWS_VALUE                                 (cy_capsense_context.ptrWdConfig[2u].numRows)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_ROWS_SIZE                                  (sizeof(cy_capsense_context.ptrWdConfig[2u].numRows))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_POS_FILTER_HISTORY_VALUE                   (cy_capsense_context.ptrWdConfig[2u].ptrPosFilterHistory)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_POS_FILTER_HISTORY_SIZE                    (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrPosFilterHistory))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSX_TOUCH_HISTORY_VALUE                    (cy_capsense_context.ptrWdConfig[2u].ptrCsxTouchHistory)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSX_TOUCH_HISTORY_SIZE                     (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrCsxTouchHistory))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSX_TOUCH_BUFFER_VALUE                     (cy_capsense_context.ptrWdConfig[2u].ptrCsxTouchBuffer)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSX_TOUCH_BUFFER_SIZE                      (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrCsxTouchBuffer))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSD_TOUCH_BUFFER_VALUE                     (cy_capsense_context.ptrWdConfig[2u].ptrCsdTouchBuffer)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSD_TOUCH_BUFFER_SIZE                      (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrCsdTouchBuffer))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_GESTURE_CONFIG_VALUE                       (cy_capsense_context.ptrWdConfig[2u].ptrGestureConfig)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_GESTURE_CONFIG_SIZE                        (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrGestureConfig))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_GESTURE_CONTEXT_VALUE                      (cy_capsense_context.ptrWdConfig[2u].ptrGestureContext)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_GESTURE_CONTEXT_SIZE                       (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrGestureContext))
+#define CY_CAPSENSE_LINEARSLIDER0_BALLISTIC_CONFIG_VALUE                         (cy_capsense_context.ptrWdConfig[2u].ballisticConfig)
+#define CY_CAPSENSE_LINEARSLIDER0_BALLISTIC_CONFIG_SIZE                          (sizeof(cy_capsense_context.ptrWdConfig[2u].ballisticConfig))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_BALLISTIC_CONTEXT_VALUE                    (cy_capsense_context.ptrWdConfig[2u].ptrBallisticContext)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_BALLISTIC_CONTEXT_SIZE                     (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrBallisticContext))
+#define CY_CAPSENSE_LINEARSLIDER0_AIIR_CONFIG_VALUE                              (cy_capsense_context.ptrWdConfig[2u].aiirConfig)
+#define CY_CAPSENSE_LINEARSLIDER0_AIIR_CONFIG_SIZE                               (sizeof(cy_capsense_context.ptrWdConfig[2u].aiirConfig))
+#define CY_CAPSENSE_LINEARSLIDER0_ADV_CONFIG_VALUE                               (cy_capsense_context.ptrWdConfig[2u].advConfig)
+#define CY_CAPSENSE_LINEARSLIDER0_ADV_CONFIG_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[2u].advConfig))
+#define CY_CAPSENSE_LINEARSLIDER0_POS_FILTER_CONFIG_VALUE                        (cy_capsense_context.ptrWdConfig[2u].posFilterConfig)
+#define CY_CAPSENSE_LINEARSLIDER0_POS_FILTER_CONFIG_SIZE                         (sizeof(cy_capsense_context.ptrWdConfig[2u].posFilterConfig))
+#define CY_CAPSENSE_LINEARSLIDER0_RAW_FILTER_CONFIG_VALUE                        (cy_capsense_context.ptrWdConfig[2u].rawFilterConfig)
+#define CY_CAPSENSE_LINEARSLIDER0_RAW_FILTER_CONFIG_SIZE                         (sizeof(cy_capsense_context.ptrWdConfig[2u].rawFilterConfig))
+#define CY_CAPSENSE_LINEARSLIDER0_SENSE_METHOD_VALUE                             (cy_capsense_context.ptrWdConfig[2u].senseMethod)
+#define CY_CAPSENSE_LINEARSLIDER0_SENSE_METHOD_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2u].senseMethod))
+#define CY_CAPSENSE_LINEARSLIDER0_WD_TYPE_VALUE                                  (cy_capsense_context.ptrWdConfig[2u].wdType)
+#define CY_CAPSENSE_LINEARSLIDER0_WD_TYPE_SIZE                                   (sizeof(cy_capsense_context.ptrWdConfig[2u].wdType))
+
+/* cy_capsense_pinConfig */
+#define CY_CAPSENSE_BUTTON0_SNS0_PIN0_PC_PTR_VALUE                               (cy_capsense_context.ptrPinConfig[0].pcPtr)
+#define CY_CAPSENSE_BUTTON0_SNS0_PIN0_PC_PTR_SIZE                                (sizeof(cy_capsense_context.ptrPinConfig[0].pcPtr))
+#define CY_CAPSENSE_BUTTON0_SNS0_PIN0_NUMBER_VALUE                               (cy_capsense_context.ptrPinConfig[0].pinNumber)
+#define CY_CAPSENSE_BUTTON0_SNS0_PIN0_NUMBER_SIZE                                (sizeof(cy_capsense_context.ptrPinConfig[0].pinNumber))
+
+#define CY_CAPSENSE_BUTTON1_SNS0_PIN0_PC_PTR_VALUE                               (cy_capsense_context.ptrPinConfig[1].pcPtr)
+#define CY_CAPSENSE_BUTTON1_SNS0_PIN0_PC_PTR_SIZE                                (sizeof(cy_capsense_context.ptrPinConfig[1].pcPtr))
+#define CY_CAPSENSE_BUTTON1_SNS0_PIN0_NUMBER_VALUE                               (cy_capsense_context.ptrPinConfig[1].pinNumber)
+#define CY_CAPSENSE_BUTTON1_SNS0_PIN0_NUMBER_SIZE                                (sizeof(cy_capsense_context.ptrPinConfig[1].pinNumber))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_PIN0_PC_PTR_VALUE                         (cy_capsense_context.ptrPinConfig[2].pcPtr)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_PIN0_PC_PTR_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[2].pcPtr))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_PIN0_NUMBER_VALUE                         (cy_capsense_context.ptrPinConfig[2].pinNumber)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_PIN0_NUMBER_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[2].pinNumber))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_PIN0_PC_PTR_VALUE                         (cy_capsense_context.ptrPinConfig[3].pcPtr)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_PIN0_PC_PTR_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[3].pcPtr))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_PIN0_NUMBER_VALUE                         (cy_capsense_context.ptrPinConfig[3].pinNumber)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_PIN0_NUMBER_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[3].pinNumber))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_PIN0_PC_PTR_VALUE                         (cy_capsense_context.ptrPinConfig[4].pcPtr)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_PIN0_PC_PTR_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[4].pcPtr))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_PIN0_NUMBER_VALUE                         (cy_capsense_context.ptrPinConfig[4].pinNumber)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_PIN0_NUMBER_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[4].pinNumber))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_PIN0_PC_PTR_VALUE                         (cy_capsense_context.ptrPinConfig[5].pcPtr)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_PIN0_PC_PTR_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[5].pcPtr))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_PIN0_NUMBER_VALUE                         (cy_capsense_context.ptrPinConfig[5].pinNumber)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_PIN0_NUMBER_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[5].pinNumber))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_PIN0_PC_PTR_VALUE                         (cy_capsense_context.ptrPinConfig[6].pcPtr)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_PIN0_PC_PTR_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[6].pcPtr))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_PIN0_NUMBER_VALUE                         (cy_capsense_context.ptrPinConfig[6].pinNumber)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_PIN0_NUMBER_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[6].pinNumber))
+
+/* cy_capsense_electrodeConfig */
+#define CY_CAPSENSE_BUTTON0_SNS0_CFG_PTR_VALUE                                   (cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].ptrPin)
+#define CY_CAPSENSE_BUTTON0_SNS0_CFG_PTR_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].ptrPin))
+#define CY_CAPSENSE_BUTTON0_SNS0_ELTD_TYPE_VALUE                                 (cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].type)
+#define CY_CAPSENSE_BUTTON0_SNS0_ELTD_TYPE_SIZE                                  (sizeof(cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].type))
+#define CY_CAPSENSE_BUTTON0_SNS0_NUM_PINS_VALUE                                  (cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].numPins)
+#define CY_CAPSENSE_BUTTON0_SNS0_NUM_PINS_SIZE                                   (sizeof(cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].numPins))
+
+#define CY_CAPSENSE_BUTTON1_SNS0_CFG_PTR_VALUE                                   (cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].ptrPin)
+#define CY_CAPSENSE_BUTTON1_SNS0_CFG_PTR_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].ptrPin))
+#define CY_CAPSENSE_BUTTON1_SNS0_ELTD_TYPE_VALUE                                 (cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].type)
+#define CY_CAPSENSE_BUTTON1_SNS0_ELTD_TYPE_SIZE                                  (sizeof(cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].type))
+#define CY_CAPSENSE_BUTTON1_SNS0_NUM_PINS_VALUE                                  (cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].numPins)
+#define CY_CAPSENSE_BUTTON1_SNS0_NUM_PINS_SIZE                                   (sizeof(cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].numPins))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_CFG_PTR_VALUE                             (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].ptrPin)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_CFG_PTR_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].ptrPin))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_ELTD_TYPE_VALUE                           (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].type)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_ELTD_TYPE_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].type))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NUM_PINS_VALUE                            (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].numPins)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NUM_PINS_SIZE                             (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].numPins))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_CFG_PTR_VALUE                             (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].ptrPin)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_CFG_PTR_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].ptrPin))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_ELTD_TYPE_VALUE                           (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].type)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_ELTD_TYPE_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].type))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NUM_PINS_VALUE                            (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].numPins)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NUM_PINS_SIZE                             (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].numPins))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_CFG_PTR_VALUE                             (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].ptrPin)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_CFG_PTR_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].ptrPin))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_ELTD_TYPE_VALUE                           (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].type)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_ELTD_TYPE_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].type))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NUM_PINS_VALUE                            (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].numPins)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NUM_PINS_SIZE                             (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].numPins))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_CFG_PTR_VALUE                             (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].ptrPin)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_CFG_PTR_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].ptrPin))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_ELTD_TYPE_VALUE                           (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].type)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_ELTD_TYPE_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].type))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NUM_PINS_VALUE                            (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].numPins)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NUM_PINS_SIZE                             (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].numPins))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_CFG_PTR_VALUE                             (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].ptrPin)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_CFG_PTR_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].ptrPin))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_ELTD_TYPE_VALUE                           (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].type)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_ELTD_TYPE_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].type))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NUM_PINS_VALUE                            (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].numPins)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NUM_PINS_SIZE                             (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].numPins))
+
+
+#if ((CY_CAPSENSE_PERI_CLK / 2) > 50000000)
+    #warning The maximum CSD modulator clock frequency is 50 MHz: increase CSD modulator clock divider to meet the valid operation conditions
+#endif
+
+
+
+#if (CY_CAPSENSE_BIST_SUPPORTED)
+#if (CY_CAPSENSE_BIST_EN != 0)
+    extern uint32_t cy_capsense_eltdCap[];
+    #if (CY_CAPSENSE_MW_VERSION >= 300)
+        extern uint32_t cy_capsense_snsCap[];
+    #endif
+    extern uint16_t cy_capsense_bslnInv[];
+#endif
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_CAPSENSE_CORE == __CORTEX_M */
+
+#endif /* !defined(CY_DISABLE_CAPSENSE) */
+
+#endif /* CYCFG_CAPSENSE_H */
+
+/* [] END OF FILE */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_defines.h

@@ -0,0 +1,136 @@
+/*******************************************************************************
+* File Name: cycfg_capsense_defines.h
+*
+* Description:
+* CapSense configuration defines.
+* This file should not be modified. It was automatically generated by
+* CapSense Configurator 4.0.0.5943
+*
+********************************************************************************
+* Copyright 2021, Cypress Semiconductor Corporation (an Infineon company)
+* or an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#if !defined(CYCFG_CAPSENSE_DEFINES_H)
+#define CYCFG_CAPSENSE_DEFINES_H
+
+#include <stddef.h>
+
+/* General */
+#define CY_CAPSENSE_WIDGET_COUNT                                                 (3u)
+#define CY_CAPSENSE_SENSOR_COUNT                                                 (7u)
+#define CY_CAPSENSE_ELTD_COUNT                                                   (7u)
+#define CY_CAPSENSE_PIN_COUNT                                                    (7u)
+#define CY_CAPSENSE_SHIELD_PIN_COUNT                                             (0u)
+#define CY_CAPSENSE_POSITION_SIZE                                                (1u)
+#define CY_CAPSENSE_DEBOUNCE_SIZE                                                (3u)
+#define CY_CAPSENSE_NOISE_ENVELOPE_SIZE                                          (7u)
+#define CY_CAPSENSE_MFS_CH_NUMBER                                                (1u)
+#define CY_CAPSENSE_RAW_HISTORY_SIZE                                             (0u)
+#define CY_CAPSENSE_IIR_HISTORY_LOW_SIZE                                         (0u)
+#define CY_CAPSENSE_POSITION_FILTER_HISTORY_SIZE                                 (0u)
+#define CY_CAPSENSE_TOUCH_FILTER_HISTORY_SIZE                                    (0u)
+#define CY_CAPSENSE_DIPLEX_SIZE                                                  (0u)
+#define CY_CAPSENSE_CSD_TOUCHPAD_MAX_SENSORS_SIZE                                (0u)
+#define CY_CAPSENSE_CSX_TOUCH_BUFFER_ENABLE                                      (0u)
+#define CY_CAPSENSE_CSX_TOUCH_HISTORY_SIZE                                       (0u)
+#define CY_CAPSENSE_BALLISTIC_WIDGET_COUNT                                       (0u)
+#define CY_CAPSENSE_GESTURE_WIDGET_COUNT                                         (0u)
+
+/* Sensing Methods */
+#define CY_CAPSENSE_CSD_EN                                                       (1u)
+#define CY_CAPSENSE_CSX_EN                                                       (0u)
+#define CY_CAPSENSE_CSD_CALIBRATION_EN                                           (1u)
+#define CY_CAPSENSE_CSX_CALIBRATION_EN                                           (0u)
+#define CY_CAPSENSE_SMARTSENSE_FULL_EN                                           (1u)
+#define CY_CAPSENSE_SMARTSENSE_HW_EN                                             (0u)
+#define CY_CAPSENSE_SMARTSENSE_DISABLED                                          (0u)
+#define CY_CAPSENSE_CSD_AUTOTUNE_EN                                              (CY_CAPSENSE_SMARTSENSE_FULL_EN || CY_CAPSENSE_SMARTSENSE_HW_EN)
+#define CY_CAPSENSE_CSD_SHIELD_EN                                                (0u)
+#define CY_CAPSENSE_CSD_SHIELD_CAP_EN                                            (0u)
+#define CY_CAPSENSE_CSD_CHARGE_TRANSFER                                          (CY_CAPSENSE_IDAC_SOURCING)
+#define CY_CAPSENSE_CSD_IDAC_COMP_EN                                             (1u)
+#define CY_CAPSENSE_CSD_IDAC_AUTO_GAIN_EN                                        (1u)
+#define CY_CAPSENSE_CSD_IDAC_ROW_COL_ALIGN_EN                                    (1u)
+#define CY_CAPSENSE_LFSR_EN                                                      (1u)
+#define CY_CAPSENSE_LFSR_AUTO_EN                                                 (1u)
+#define CY_CAPSENSE_CLOCK_SOURCE_AUTO_EN                                         (1u)
+
+/* Filtering */
+#define CY_CAPSENSE_ADAPTIVE_FILTER_EN                                           (0u)
+#define CY_CAPSENSE_BALLISTIC_MULTIPLIER_EN                                      (0u)
+#define CY_CAPSENSE_RAWCOUNT_FILTER_EN                                           (0u)
+#define CY_CAPSENSE_REGULAR_RC_IIR_FILTER_EN                                     (0u)
+#define CY_CAPSENSE_REGULAR_RC_MEDIAN_FILTER_EN                                  (0u)
+#define CY_CAPSENSE_REGULAR_RC_AVERAGE_FILTER_EN                                 (0u)
+#define CY_CAPSENSE_REGULAR_RC_FILTER_EN                                         (CY_CAPSENSE_REGULAR_RC_IIR_FILTER_EN || CY_CAPSENSE_REGULAR_RC_MEDIAN_FILTER_EN || CY_CAPSENSE_REGULAR_RC_AVERAGE_FILTER_EN)
+#define CY_CAPSENSE_PROX_RC_IIR_FILTER_EN                                        (0u)
+#define CY_CAPSENSE_PROX_RC_MEDIAN_FILTER_EN                                     (0u)
+#define CY_CAPSENSE_PROX_RC_AVERAGE_FILTER_EN                                    (0u)
+#define CY_CAPSENSE_PROX_RC_FILTER_EN                                            (CY_CAPSENSE_PROX_RC_IIR_FILTER_EN || CY_CAPSENSE_PROX_RC_MEDIAN_FILTER_EN || CY_CAPSENSE_PROX_RC_AVERAGE_FILTER_EN)
+#define CY_CAPSENSE_POSITION_FILTER_EN                                           (0u)
+#define CY_CAPSENSE_CSD_POSITION_FILTER_EN                                       (0u)
+#define CY_CAPSENSE_CSX_POSITION_FILTER_EN                                       (0u)
+#define CY_CAPSENSE_POS_IIR_FILTER_EN                                            (0u)
+#define CY_CAPSENSE_POS_MEDIAN_FILTER_EN                                         (0u)
+#define CY_CAPSENSE_POS_AVERAGE_FILTER_EN                                        (0u)
+#define CY_CAPSENSE_POS_JITTER_FILTER_EN                                         (0u)
+
+/* Widgets */
+#define CY_CAPSENSE_CSD_BUTTON_EN                                                (1u)
+#define CY_CAPSENSE_CSD_MATRIX_EN                                                (0u)
+#define CY_CAPSENSE_CSD_SLIDER_EN                                                (1u)
+#define CY_CAPSENSE_CSD_TOUCHPAD_EN                                              (0u)
+#define CY_CAPSENSE_CSD_PROXIMITY_EN                                             (0u)
+#define CY_CAPSENSE_CSX_BUTTON_EN                                                (0u)
+#define CY_CAPSENSE_CSX_SLIDER_EN                                                (0u)
+#define CY_CAPSENSE_CSX_MATRIX_EN                                                (0u)
+#define CY_CAPSENSE_CSX_TOUCHPAD_EN                                              (0u)
+#define CY_CAPSENSE_ADVANCED_CENTROID_5X5_EN                                     (0u)
+#define CY_CAPSENSE_CSD_LINEAR_SLIDER_EN                                         (1u)
+#define CY_CAPSENSE_CSD_RADIAL_SLIDER_EN                                         (0u)
+#define CY_CAPSENSE_CSD_DIPLEX_SLIDER_EN                                         (0u)
+#define CY_CAPSENSE_CSX_LINEAR_SLIDER_EN                                         (0u)
+#define CY_CAPSENSE_CSX_DIPLEX_SLIDER_EN                                         (0u)
+#define CY_CAPSENSE_GANGED_SNS_EN                                                (0u)
+#define CY_CAPSENSE_CSD_GANGED_SNS_EN                                            (0u)
+#define CY_CAPSENSE_CSX_GANGED_SNS_EN                                            (0u)
+#define CY_CAPSENSE_BUTTON_EN                                                    (1u)
+#define CY_CAPSENSE_MATRIX_EN                                                    (0u)
+#define CY_CAPSENSE_SLIDER_EN                                                    (1u)
+#define CY_CAPSENSE_TOUCHPAD_EN                                                  (0u)
+
+/* Features */
+#define CY_CAPSENSE_GESTURE_EN                                                   (0u)
+#define CY_CAPSENSE_MULTI_FREQUENCY_SCAN_EN                                      (0u)
+#define CY_CAPSENSE_MULTI_FREQUENCY_WIDGET_EN                                    (0u)
+#define CY_CAPSENSE_SNS_AUTO_RESET_EN                                            (0u)
+
+/* Self-test */
+#define CY_CAPSENSE_BIST_EN                                                      (0u)
+#define CY_CAPSENSE_TST_WDGT_CRC_EN                                              (0u)
+#define CY_CAPSENSE_TST_BSLN_INTEGRITY_EN                                        (0u)
+#define CY_CAPSENSE_TST_RAW_INTEGRITY_EN                                         (0u)
+#define CY_CAPSENSE_TST_SNS_SHORT_EN                                             (0u)
+#define CY_CAPSENSE_TST_SNS_CAP_EN                                               (0u)
+#define CY_CAPSENSE_TST_SH_CAP_EN                                                (0u)
+#define CY_CAPSENSE_TST_EXTERNAL_CAP_EN                                          (0u)
+#define CY_CAPSENSE_TST_VDDA_EN                                                  (0u)
+
+
+#endif /* CYCFG_CAPSENSE_DEFINES_H */
+
+/* [] END OF FILE */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_tuner_regmap.h

@@ -0,0 +1,973 @@
+/*******************************************************************************
+* File Name: cycfg_capsense_tuner_regmap.h
+*
+* Description:
+* CapSense Tuner register map configuration.
+* This file should not be modified. It was automatically generated by
+* CapSense Configurator 4.0.0.5943
+*
+********************************************************************************
+* Copyright 2021, Cypress Semiconductor Corporation (an Infineon company)
+* or an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#if !defined(CYCFG_CAPSENSE_TUNER_REGMAP_H)
+#define CYCFG_CAPSENSE_TUNER_REGMAP_H
+
+#include "cy_capsense_common.h"
+
+#if !defined(CY_CAPSENSE_MW_VERSION)
+    #define CY_CAPSENSE_TUNER_MW_VERSION (200)
+#else
+    #define CY_CAPSENSE_TUNER_MW_VERSION (CY_CAPSENSE_MW_VERSION)
+#endif
+
+/* RAM Data structure register definitions */
+#if (CY_CAPSENSE_TUNER_MW_VERSION < 300)
+#define CY_CAPSENSE_TUNER_CONFIG_ID_OFFSET                                             (0u)
+#define CY_CAPSENSE_TUNER_CONFIG_ID_SIZE                                               (2u)
+
+#define CY_CAPSENSE_TUNER_TUNER_CMD_OFFSET                                             (2u)
+#define CY_CAPSENSE_TUNER_TUNER_CMD_SIZE                                               (2u)
+
+#define CY_CAPSENSE_TUNER_SCAN_COUNTER_OFFSET                                          (4u)
+#define CY_CAPSENSE_TUNER_SCAN_COUNTER_SIZE                                            (2u)
+
+#define CY_CAPSENSE_TUNER_TUNER_ST_OFFSET                                              (6u)
+#define CY_CAPSENSE_TUNER_TUNER_ST_SIZE                                                (1u)
+
+#define CY_CAPSENSE_TUNER_INITDONE_OFFSET                                              (7u)
+#define CY_CAPSENSE_TUNER_INITDONE_SIZE                                                (1u)
+
+#define CY_CAPSENSE_TUNER_PTRSSCALLBACK_OFFSET                                         (8u)
+#define CY_CAPSENSE_TUNER_PTRSSCALLBACK_SIZE                                           (4u)
+
+#define CY_CAPSENSE_TUNER_PTREOSCALLBACK_OFFSET                                        (12u)
+#define CY_CAPSENSE_TUNER_PTREOSCALLBACK_SIZE                                          (4u)
+
+#define CY_CAPSENSE_TUNER_PTRTUNERSENDCALLBACK_OFFSET                                  (16u)
+#define CY_CAPSENSE_TUNER_PTRTUNERSENDCALLBACK_SIZE                                    (4u)
+
+#define CY_CAPSENSE_TUNER_PTRTUNERRECEIVECALLBACK_OFFSET                               (20u)
+#define CY_CAPSENSE_TUNER_PTRTUNERRECEIVECALLBACK_SIZE                                 (4u)
+
+#define CY_CAPSENSE_TUNER_STATUS_OFFSET                                                (24u)
+#define CY_CAPSENSE_TUNER_STATUS_SIZE                                                  (4u)
+
+#define CY_CAPSENSE_TUNER_TIMESTAMPINTERVAL_OFFSET                                     (28u)
+#define CY_CAPSENSE_TUNER_TIMESTAMPINTERVAL_SIZE                                       (4u)
+
+#define CY_CAPSENSE_TUNER_TIMESTAMP_OFFSET                                             (32u)
+#define CY_CAPSENSE_TUNER_TIMESTAMP_SIZE                                               (4u)
+
+#define CY_CAPSENSE_TUNER_CSD_MOD_CLK_DIVIDER_OFFSET                                   (36u)
+#define CY_CAPSENSE_TUNER_CSD_MOD_CLK_DIVIDER_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_CSX_MOD_CLK_DIVIDER_OFFSET                                   (37u)
+#define CY_CAPSENSE_TUNER_CSX_MOD_CLK_DIVIDER_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_TUNER_CNT_OFFSET                                             (38u)
+#define CY_CAPSENSE_TUNER_TUNER_CNT_SIZE                                               (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_CP_OFFSET                                     (40u)
+#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_CP_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SIGPFC_OFFSET                                        (42u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SIGPFC_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_RESOLUTION_OFFSET                                    (44u)
+#define CY_CAPSENSE_TUNER_BUTTON0_RESOLUTION_SIZE                                      (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNT_OFFSET                                   (46u)
+#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNT_SIZE                                     (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_TH_OFFSET                                     (48u)
+#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_TH_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_PROX_TOUCH_TH_OFFSET                                 (50u)
+#define CY_CAPSENSE_TUNER_BUTTON0_PROX_TOUCH_TH_SIZE                                   (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_LOW_BSLN_RST_OFFSET                                  (52u)
+#define CY_CAPSENSE_TUNER_BUTTON0_LOW_BSLN_RST_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS_CLK_OFFSET                                       (54u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS_CLK_SIZE                                         (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_SNS_CLK_OFFSET                                   (56u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_SNS_CLK_SIZE                                     (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DETECTED_OFFSET                              (58u)
+#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DETECTED_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DIRECTION_OFFSET                             (60u)
+#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DIRECTION_SIZE                               (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_XDELTA_OFFSET                                        (62u)
+#define CY_CAPSENSE_TUNER_BUTTON0_XDELTA_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_YDELTA_OFFSET                                        (64u)
+#define CY_CAPSENSE_TUNER_BUTTON0_YDELTA_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_NOISE_TH_OFFSET                                      (66u)
+#define CY_CAPSENSE_TUNER_BUTTON0_NOISE_TH_SIZE                                        (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_NNOISE_TH_OFFSET                                     (67u)
+#define CY_CAPSENSE_TUNER_BUTTON0_NNOISE_TH_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_HYSTERESIS_OFFSET                                    (68u)
+#define CY_CAPSENSE_TUNER_BUTTON0_HYSTERESIS_SIZE                                      (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ON_DEBOUNCE_OFFSET                                   (69u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ON_DEBOUNCE_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS_CLK_SOURCE_OFFSET                                (70u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS_CLK_SOURCE_SIZE                                  (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD0_OFFSET                                     (71u)
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD0_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD1_OFFSET                                     (72u)
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD1_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD2_OFFSET                                     (73u)
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD2_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_GAIN_INDEX_OFFSET                               (74u)
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_GAIN_INDEX_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD0_OFFSET                                 (75u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD0_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD1_OFFSET                                 (76u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD1_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD2_OFFSET                                 (77u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD2_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_REGULAR_IIR_BL_N_OFFSET                              (78u)
+#define CY_CAPSENSE_TUNER_BUTTON0_REGULAR_IIR_BL_N_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_STATUS_OFFSET                                        (79u)
+#define CY_CAPSENSE_TUNER_BUTTON0_STATUS_SIZE                                          (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_PTRPOSITION_OFFSET                                   (80u)
+#define CY_CAPSENSE_TUNER_BUTTON0_PTRPOSITION_SIZE                                     (4u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_NUM_POSITIONS_OFFSET                                 (84u)
+#define CY_CAPSENSE_TUNER_BUTTON0_NUM_POSITIONS_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_CP_OFFSET                                     (88u)
+#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_CP_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SIGPFC_OFFSET                                        (90u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SIGPFC_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_RESOLUTION_OFFSET                                    (92u)
+#define CY_CAPSENSE_TUNER_BUTTON1_RESOLUTION_SIZE                                      (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNT_OFFSET                                   (94u)
+#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNT_SIZE                                     (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_TH_OFFSET                                     (96u)
+#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_TH_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_PROX_TOUCH_TH_OFFSET                                 (98u)
+#define CY_CAPSENSE_TUNER_BUTTON1_PROX_TOUCH_TH_SIZE                                   (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_LOW_BSLN_RST_OFFSET                                  (100u)
+#define CY_CAPSENSE_TUNER_BUTTON1_LOW_BSLN_RST_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS_CLK_OFFSET                                       (102u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS_CLK_SIZE                                         (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_SNS_CLK_OFFSET                                   (104u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_SNS_CLK_SIZE                                     (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DETECTED_OFFSET                              (106u)
+#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DETECTED_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DIRECTION_OFFSET                             (108u)
+#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DIRECTION_SIZE                               (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_XDELTA_OFFSET                                        (110u)
+#define CY_CAPSENSE_TUNER_BUTTON1_XDELTA_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_YDELTA_OFFSET                                        (112u)
+#define CY_CAPSENSE_TUNER_BUTTON1_YDELTA_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_NOISE_TH_OFFSET                                      (114u)
+#define CY_CAPSENSE_TUNER_BUTTON1_NOISE_TH_SIZE                                        (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_NNOISE_TH_OFFSET                                     (115u)
+#define CY_CAPSENSE_TUNER_BUTTON1_NNOISE_TH_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_HYSTERESIS_OFFSET                                    (116u)
+#define CY_CAPSENSE_TUNER_BUTTON1_HYSTERESIS_SIZE                                      (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ON_DEBOUNCE_OFFSET                                   (117u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ON_DEBOUNCE_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS_CLK_SOURCE_OFFSET                                (118u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS_CLK_SOURCE_SIZE                                  (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD0_OFFSET                                     (119u)
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD0_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD1_OFFSET                                     (120u)
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD1_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD2_OFFSET                                     (121u)
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD2_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_GAIN_INDEX_OFFSET                               (122u)
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_GAIN_INDEX_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD0_OFFSET                                 (123u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD0_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD1_OFFSET                                 (124u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD1_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD2_OFFSET                                 (125u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD2_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_REGULAR_IIR_BL_N_OFFSET                              (126u)
+#define CY_CAPSENSE_TUNER_BUTTON1_REGULAR_IIR_BL_N_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_STATUS_OFFSET                                        (127u)
+#define CY_CAPSENSE_TUNER_BUTTON1_STATUS_SIZE                                          (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_PTRPOSITION_OFFSET                                   (128u)
+#define CY_CAPSENSE_TUNER_BUTTON1_PTRPOSITION_SIZE                                     (4u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_NUM_POSITIONS_OFFSET                                 (132u)
+#define CY_CAPSENSE_TUNER_BUTTON1_NUM_POSITIONS_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_OFFSET                               (136u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_OFFSET                                  (138u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_OFFSET                              (140u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNT_OFFSET                             (142u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNT_SIZE                               (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_OFFSET                               (144u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_OFFSET                           (146u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_SIZE                             (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_OFFSET                            (148u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_SIZE                              (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_OFFSET                                 (150u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SIZE                                   (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_OFFSET                             (152u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_SIZE                               (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_OFFSET                        (154u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_SIZE                          (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_OFFSET                       (156u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_SIZE                         (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_OFFSET                                  (158u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_OFFSET                                  (160u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_OFFSET                                (162u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_SIZE                                  (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_OFFSET                               (163u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_OFFSET                              (164u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_OFFSET                             (165u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_SIZE                               (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_OFFSET                          (166u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_OFFSET                               (167u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_OFFSET                               (168u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_OFFSET                               (169u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_OFFSET                         (170u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_SIZE                           (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_OFFSET                           (171u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_SIZE                             (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_OFFSET                           (172u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_SIZE                             (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_OFFSET                           (173u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_SIZE                             (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_OFFSET                        (174u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_SIZE                          (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_OFFSET                                  (175u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_SIZE                                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_OFFSET                             (176u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_SIZE                               (4u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_OFFSET                           (180u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_SIZE                             (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_RAW0_OFFSET                                     (184u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_RAW0_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_BSLN0_OFFSET                                    (186u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_BSLN0_SIZE                                      (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_DIFF0_OFFSET                                    (188u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_DIFF0_SIZE                                      (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_STATUS0_OFFSET                                  (190u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_STATUS0_SIZE                                    (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                        (191u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_NEG_BSLN_RST_CNT0_SIZE                          (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_IDAC0_OFFSET                                    (192u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_IDAC0_SIZE                                      (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_BSLN_EXT0_OFFSET                                (193u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_BSLN_EXT0_SIZE                                  (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_RAW0_OFFSET                                     (194u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_RAW0_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_BSLN0_OFFSET                                    (196u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_BSLN0_SIZE                                      (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_DIFF0_OFFSET                                    (198u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_DIFF0_SIZE                                      (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_STATUS0_OFFSET                                  (200u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_STATUS0_SIZE                                    (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_NEG_BSLN_RST_CNT0_OFFSET                        (201u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_NEG_BSLN_RST_CNT0_SIZE                          (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_IDAC0_OFFSET                                    (202u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_IDAC0_SIZE                                      (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_BSLN_EXT0_OFFSET                                (203u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_BSLN_EXT0_SIZE                                  (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_OFFSET                               (204u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_OFFSET                              (206u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_OFFSET                              (208u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_OFFSET                            (210u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                  (211u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_OFFSET                              (212u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_OFFSET                          (213u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_OFFSET                               (214u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_OFFSET                              (216u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_OFFSET                              (218u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_OFFSET                            (220u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_OFFSET                  (221u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_OFFSET                              (222u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_OFFSET                          (223u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_OFFSET                               (224u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_OFFSET                              (226u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_OFFSET                              (228u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_OFFSET                            (230u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_OFFSET                  (231u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_OFFSET                              (232u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_OFFSET                          (233u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_OFFSET                               (234u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_OFFSET                              (236u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_OFFSET                              (238u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_OFFSET                            (240u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_OFFSET                  (241u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_OFFSET                              (242u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_OFFSET                          (243u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_OFFSET                               (244u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_OFFSET                              (246u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_OFFSET                              (248u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_OFFSET                            (250u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_OFFSET                  (251u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_OFFSET                              (252u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_OFFSET                          (253u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_OFFSET                                      (254u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_OFFSET                                      (256u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_OFFSET                                      (258u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_OFFSET                                     (260u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_SIZE                                       (2u)
+
+#else /* CY_CAPSENSE_TUNER_MW_VERSION >= 300 */
+#define CY_CAPSENSE_TUNER_CONFIG_ID_OFFSET                                             (0u)
+#define CY_CAPSENSE_TUNER_CONFIG_ID_SIZE                                               (2u)
+
+#define CY_CAPSENSE_TUNER_TUNER_CMD_OFFSET                                             (2u)
+#define CY_CAPSENSE_TUNER_TUNER_CMD_SIZE                                               (2u)
+
+#define CY_CAPSENSE_TUNER_SCAN_COUNTER_OFFSET                                          (4u)
+#define CY_CAPSENSE_TUNER_SCAN_COUNTER_SIZE                                            (2u)
+
+#define CY_CAPSENSE_TUNER_TUNER_ST_OFFSET                                              (6u)
+#define CY_CAPSENSE_TUNER_TUNER_ST_SIZE                                                (1u)
+
+#define CY_CAPSENSE_TUNER_INITDONE_OFFSET                                              (7u)
+#define CY_CAPSENSE_TUNER_INITDONE_SIZE                                                (1u)
+
+#define CY_CAPSENSE_TUNER_STATUS_OFFSET                                                (8u)
+#define CY_CAPSENSE_TUNER_STATUS_SIZE                                                  (4u)
+
+#define CY_CAPSENSE_TUNER_TIMESTAMPINTERVAL_OFFSET                                     (12u)
+#define CY_CAPSENSE_TUNER_TIMESTAMPINTERVAL_SIZE                                       (4u)
+
+#define CY_CAPSENSE_TUNER_TIMESTAMP_OFFSET                                             (16u)
+#define CY_CAPSENSE_TUNER_TIMESTAMP_SIZE                                               (4u)
+
+#define CY_CAPSENSE_TUNER_CSD_MOD_CLK_DIVIDER_OFFSET                                   (20u)
+#define CY_CAPSENSE_TUNER_CSD_MOD_CLK_DIVIDER_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_CSX_MOD_CLK_DIVIDER_OFFSET                                   (21u)
+#define CY_CAPSENSE_TUNER_CSX_MOD_CLK_DIVIDER_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_TUNER_CNT_OFFSET                                             (22u)
+#define CY_CAPSENSE_TUNER_TUNER_CNT_SIZE                                               (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_CP_OFFSET                                     (24u)
+#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_CP_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SIGPFC_OFFSET                                        (26u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SIGPFC_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_RESOLUTION_OFFSET                                    (28u)
+#define CY_CAPSENSE_TUNER_BUTTON0_RESOLUTION_SIZE                                      (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNT_OFFSET                                   (30u)
+#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNT_SIZE                                     (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNTROW_OFFSET                                (32u)
+#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNTROW_SIZE                                  (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_TH_OFFSET                                     (34u)
+#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_TH_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_PROX_TOUCH_TH_OFFSET                                 (36u)
+#define CY_CAPSENSE_TUNER_BUTTON0_PROX_TOUCH_TH_SIZE                                   (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_LOW_BSLN_RST_OFFSET                                  (38u)
+#define CY_CAPSENSE_TUNER_BUTTON0_LOW_BSLN_RST_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS_CLK_OFFSET                                       (40u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS_CLK_SIZE                                         (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_SNS_CLK_OFFSET                                   (42u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_SNS_CLK_SIZE                                     (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DETECTED_OFFSET                              (44u)
+#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DETECTED_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DIRECTION_OFFSET                             (46u)
+#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DIRECTION_SIZE                               (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_XDELTA_OFFSET                                        (48u)
+#define CY_CAPSENSE_TUNER_BUTTON0_XDELTA_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_YDELTA_OFFSET                                        (50u)
+#define CY_CAPSENSE_TUNER_BUTTON0_YDELTA_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_NOISE_TH_OFFSET                                      (52u)
+#define CY_CAPSENSE_TUNER_BUTTON0_NOISE_TH_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_NNOISE_TH_OFFSET                                     (54u)
+#define CY_CAPSENSE_TUNER_BUTTON0_NNOISE_TH_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_HYSTERESIS_OFFSET                                    (56u)
+#define CY_CAPSENSE_TUNER_BUTTON0_HYSTERESIS_SIZE                                      (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ON_DEBOUNCE_OFFSET                                   (58u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ON_DEBOUNCE_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS_CLK_SOURCE_OFFSET                                (59u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS_CLK_SOURCE_SIZE                                  (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD0_OFFSET                                     (60u)
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD0_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD1_OFFSET                                     (61u)
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD1_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD2_OFFSET                                     (62u)
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD2_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_GAIN_INDEX_OFFSET                               (63u)
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_GAIN_INDEX_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD0_OFFSET                                 (64u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD0_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD1_OFFSET                                 (65u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD1_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD2_OFFSET                                 (66u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD2_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_REGULAR_IIR_BL_N_OFFSET                              (67u)
+#define CY_CAPSENSE_TUNER_BUTTON0_REGULAR_IIR_BL_N_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_STATUS_OFFSET                                        (68u)
+#define CY_CAPSENSE_TUNER_BUTTON0_STATUS_SIZE                                          (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_PTRPOSITION_OFFSET                                   (72u)
+#define CY_CAPSENSE_TUNER_BUTTON0_PTRPOSITION_SIZE                                     (4u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_NUM_POSITIONS_OFFSET                                 (76u)
+#define CY_CAPSENSE_TUNER_BUTTON0_NUM_POSITIONS_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_CP_OFFSET                                     (80u)
+#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_CP_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SIGPFC_OFFSET                                        (82u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SIGPFC_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_RESOLUTION_OFFSET                                    (84u)
+#define CY_CAPSENSE_TUNER_BUTTON1_RESOLUTION_SIZE                                      (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNT_OFFSET                                   (86u)
+#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNT_SIZE                                     (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNTROW_OFFSET                                (88u)
+#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNTROW_SIZE                                  (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_TH_OFFSET                                     (90u)
+#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_TH_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_PROX_TOUCH_TH_OFFSET                                 (92u)
+#define CY_CAPSENSE_TUNER_BUTTON1_PROX_TOUCH_TH_SIZE                                   (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_LOW_BSLN_RST_OFFSET                                  (94u)
+#define CY_CAPSENSE_TUNER_BUTTON1_LOW_BSLN_RST_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS_CLK_OFFSET                                       (96u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS_CLK_SIZE                                         (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_SNS_CLK_OFFSET                                   (98u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_SNS_CLK_SIZE                                     (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DETECTED_OFFSET                              (100u)
+#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DETECTED_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DIRECTION_OFFSET                             (102u)
+#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DIRECTION_SIZE                               (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_XDELTA_OFFSET                                        (104u)
+#define CY_CAPSENSE_TUNER_BUTTON1_XDELTA_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_YDELTA_OFFSET                                        (106u)
+#define CY_CAPSENSE_TUNER_BUTTON1_YDELTA_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_NOISE_TH_OFFSET                                      (108u)
+#define CY_CAPSENSE_TUNER_BUTTON1_NOISE_TH_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_NNOISE_TH_OFFSET                                     (110u)
+#define CY_CAPSENSE_TUNER_BUTTON1_NNOISE_TH_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_HYSTERESIS_OFFSET                                    (112u)
+#define CY_CAPSENSE_TUNER_BUTTON1_HYSTERESIS_SIZE                                      (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ON_DEBOUNCE_OFFSET                                   (114u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ON_DEBOUNCE_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS_CLK_SOURCE_OFFSET                                (115u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS_CLK_SOURCE_SIZE                                  (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD0_OFFSET                                     (116u)
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD0_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD1_OFFSET                                     (117u)
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD1_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD2_OFFSET                                     (118u)
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD2_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_GAIN_INDEX_OFFSET                               (119u)
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_GAIN_INDEX_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD0_OFFSET                                 (120u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD0_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD1_OFFSET                                 (121u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD1_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD2_OFFSET                                 (122u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD2_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_REGULAR_IIR_BL_N_OFFSET                              (123u)
+#define CY_CAPSENSE_TUNER_BUTTON1_REGULAR_IIR_BL_N_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_STATUS_OFFSET                                        (124u)
+#define CY_CAPSENSE_TUNER_BUTTON1_STATUS_SIZE                                          (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_PTRPOSITION_OFFSET                                   (128u)
+#define CY_CAPSENSE_TUNER_BUTTON1_PTRPOSITION_SIZE                                     (4u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_NUM_POSITIONS_OFFSET                                 (132u)
+#define CY_CAPSENSE_TUNER_BUTTON1_NUM_POSITIONS_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_OFFSET                               (136u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_OFFSET                                  (138u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_OFFSET                              (140u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNT_OFFSET                             (142u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNT_SIZE                               (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNTROW_OFFSET                          (144u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNTROW_SIZE                            (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_OFFSET                               (146u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_OFFSET                           (148u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_SIZE                             (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_OFFSET                            (150u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_SIZE                              (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_OFFSET                                 (152u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SIZE                                   (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_OFFSET                             (154u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_SIZE                               (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_OFFSET                        (156u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_SIZE                          (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_OFFSET                       (158u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_SIZE                         (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_OFFSET                                  (160u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_OFFSET                                  (162u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_OFFSET                                (164u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_SIZE                                  (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_OFFSET                               (166u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_OFFSET                              (168u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_OFFSET                             (170u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_SIZE                               (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_OFFSET                          (171u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_OFFSET                               (172u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_OFFSET                               (173u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_OFFSET                               (174u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_OFFSET                         (175u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_SIZE                           (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_OFFSET                           (176u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_SIZE                             (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_OFFSET                           (177u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_SIZE                             (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_OFFSET                           (178u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_SIZE                             (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_OFFSET                        (179u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_SIZE                          (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_OFFSET                                  (180u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_SIZE                                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_OFFSET                             (184u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_SIZE                               (4u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_OFFSET                           (188u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_SIZE                             (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_RAW0_OFFSET                                     (192u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_RAW0_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_BSLN0_OFFSET                                    (194u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_BSLN0_SIZE                                      (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_DIFF0_OFFSET                                    (196u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_DIFF0_SIZE                                      (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_STATUS0_OFFSET                                  (198u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_STATUS0_SIZE                                    (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                        (199u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_NEG_BSLN_RST_CNT0_SIZE                          (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_IDAC0_OFFSET                                    (200u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_IDAC0_SIZE                                      (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_BSLN_EXT0_OFFSET                                (201u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_BSLN_EXT0_SIZE                                  (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_RAW0_OFFSET                                     (202u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_RAW0_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_BSLN0_OFFSET                                    (204u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_BSLN0_SIZE                                      (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_DIFF0_OFFSET                                    (206u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_DIFF0_SIZE                                      (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_STATUS0_OFFSET                                  (208u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_STATUS0_SIZE                                    (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_NEG_BSLN_RST_CNT0_OFFSET                        (209u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_NEG_BSLN_RST_CNT0_SIZE                          (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_IDAC0_OFFSET                                    (210u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_IDAC0_SIZE                                      (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_BSLN_EXT0_OFFSET                                (211u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_BSLN_EXT0_SIZE                                  (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_OFFSET                               (212u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_OFFSET                              (214u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_OFFSET                              (216u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_OFFSET                            (218u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                  (219u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_OFFSET                              (220u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_OFFSET                          (221u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_OFFSET                               (222u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_OFFSET                              (224u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_OFFSET                              (226u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_OFFSET                            (228u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_OFFSET                  (229u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_OFFSET                              (230u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_OFFSET                          (231u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_OFFSET                               (232u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_OFFSET                              (234u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_OFFSET                              (236u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_OFFSET                            (238u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_OFFSET                  (239u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_OFFSET                              (240u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_OFFSET                          (241u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_OFFSET                               (242u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_OFFSET                              (244u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_OFFSET                              (246u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_OFFSET                            (248u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_OFFSET                  (249u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_OFFSET                              (250u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_OFFSET                          (251u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_OFFSET                               (252u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_OFFSET                              (254u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_OFFSET                              (256u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_OFFSET                            (258u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_OFFSET                  (259u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_OFFSET                              (260u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_OFFSET                          (261u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_OFFSET                                      (262u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_OFFSET                                      (264u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_OFFSET                                      (266u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_OFFSET                                     (268u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_SIZE                                       (2u)
+
+#endif
+
+
+#endif /* CYCFG_CAPSENSE_TUNER_REGMAP_H */
+
+/* [] END OF FILE */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

@@ -0,0 +1,50 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.c
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_clocks.h"
+
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
+    {
+        .type = CYHAL_RSC_CLOCK,
+        .block_num = CYBSP_CSD_CLK_DIV_HW,
+        .channel_num = CYBSP_CSD_CLK_DIV_NUM,
+    };
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_clocks(void)
+{
+    Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+    Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U);
+    Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+}

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

@@ -0,0 +1,62 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.h
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_CLOCKS_H)
+#define CYCFG_CLOCKS_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+    #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_CSD_CLK_DIV_ENABLED 1U
+#define CYBSP_CS_CLK_DIV_ENABLED CYBSP_CSD_CLK_DIV_ENABLED
+#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CS_CLK_DIV_HW CYBSP_CSD_CLK_DIV_HW
+#define CYBSP_CSD_CLK_DIV_NUM 0U
+#define CYBSP_CS_CLK_DIV_NUM CYBSP_CSD_CLK_DIV_NUM
+
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
+    #define CYBSP_CS_CLK_DIV_obj CYBSP_CSD_CLK_DIV_obj
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_clocks(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_CLOCKS_H */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c

@@ -0,0 +1,31 @@
+/*******************************************************************************
+* File Name: cycfg_connectivity_bt.c
+*
+* Description:
+* Connectivity BT configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_connectivity_bt.h"
+

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h

@@ -0,0 +1,55 @@
+/*******************************************************************************
+* File Name: cycfg_connectivity_bt.h
+*
+* Description:
+* Connectivity BT configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_CONNECTIVITY_BT_H)
+#define CYCFG_CONNECTIVITY_BT_H
+
+#include "cycfg_notices.h"
+#include "cycfg_pins.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define bt_0_power_0_ENABLED 1U
+#define CYCFG_BT_LP_ENABLED (1u)
+#define CYCFG_BT_WAKE_EVENT_ACTIVE_LOW (0)
+#define CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH (1)
+#define CYCFG_BT_HOST_WAKE_GPIO CYBSP_BT_HOST_WAKE
+#define CYCFG_BT_HOST_WAKE_IRQ_EVENT CYBT_WAKE_ACTIVE_LOW
+#define CYCFG_BT_DEV_WAKE_GPIO CYBSP_BT_DEVICE_WAKE
+#define CYCFG_BT_DEV_WAKE_POLARITY CYBT_WAKE_ACTIVE_LOW
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_CONNECTIVITY_BT_H */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

@@ -0,0 +1,41 @@
+/*******************************************************************************
+* File Name: cycfg_notices.h
+*
+* Description:
+* Contains warnings and errors that occurred while generating code for the
+* design.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_NOTICES_H)
+#define CYCFG_NOTICES_H
+
+#ifdef CY_SUPPORTS_DEVICE_VALIDATION
+#ifndef CY8C6245LQI_S3D72
+    #error "Unexpected target MCU; expected CY8C6245LQI-S3D72. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
+#endif
+#endif
+
+
+#endif /* CYCFG_NOTICES_H */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

@@ -0,0 +1,41 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.c
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_peripherals.h"
+
+cy_stc_csd_context_t cy_csd_0_context =
+{
+    .lockKey = CY_CSD_NONE_KEY,
+};
+
+
+void init_cycfg_peripherals(void)
+{
+    Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
+}

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

@@ -0,0 +1,77 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.h
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PERIPHERALS_H)
+#define CYCFG_PERIPHERALS_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_csd.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_CSD_ENABLED 1U
+#define CY_CAPSENSE_CORE 4u
+#define CY_CAPSENSE_CPU_CLK 100000000u
+#define CY_CAPSENSE_PERI_CLK 100000000u
+#define CY_CAPSENSE_VDDA_MV 3300u
+#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
+#define CY_CAPSENSE_PERI_DIV_INDEX 0u
+#define Cmod_PORT GPIO_PRT7
+#define Button0_Sns0_PORT GPIO_PRT8
+#define Button1_Sns0_PORT GPIO_PRT8
+#define LinearSlider0_Sns0_PORT GPIO_PRT7
+#define LinearSlider0_Sns1_PORT GPIO_PRT7
+#define LinearSlider0_Sns2_PORT GPIO_PRT7
+#define LinearSlider0_Sns3_PORT GPIO_PRT7
+#define LinearSlider0_Sns4_PORT GPIO_PRT9
+#define Cmod_PIN 7u
+#define Button0_Sns0_PIN 0u
+#define Button1_Sns0_PIN 1u
+#define LinearSlider0_Sns0_PIN 0u
+#define LinearSlider0_Sns1_PIN 1u
+#define LinearSlider0_Sns2_PIN 2u
+#define LinearSlider0_Sns3_PIN 3u
+#define LinearSlider0_Sns4_PIN 0u
+#define Cmod_PORT_NUM 7u
+#define CYBSP_CSD_HW CSD0
+#define CYBSP_CSD_IRQ csd_interrupt_IRQn
+
+extern cy_stc_csd_context_t cy_csd_0_context;
+
+void init_cycfg_peripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PERIPHERALS_H */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c

@@ -0,0 +1,375 @@
+/*******************************************************************************
+* File Name: cycfg_pins.c
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_pins.h"
+
+const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_WCO_IN_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_WCO_IN_PORT_NUM,
+        .channel_num = CYBSP_WCO_IN_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_WCO_OUT_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_WCO_OUT_PORT_NUM,
+        .channel_num = CYBSP_WCO_OUT_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_PULLUP,
+    .hsiom = CYBSP_SWDIO_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_SWDIO_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_SWDIO_PORT_NUM,
+        .channel_num = CYBSP_SWDIO_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_PULLDOWN,
+    .hsiom = CYBSP_SWDCK_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_SWDCK_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_SWDCK_PORT_NUM,
+        .channel_num = CYBSP_SWDCK_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_SLD0_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_SLD0_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD0_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_SLD1_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_SLD1_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD1_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_SLD2_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_SLD2_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD2_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_SLD3_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_SLD3_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD3_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CMOD_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CMOD_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CMOD_PORT_NUM,
+        .channel_num = CYBSP_CMOD_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_BTN0_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_BTN0_PORT_NUM,
+        .channel_num = CYBSP_CSD_BTN0_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_BTN1_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_BTN1_PORT_NUM,
+        .channel_num = CYBSP_CSD_BTN1_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_SLD4_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_SLD4_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD4_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_pins(void)
+{
+    Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
+#endif //defined (CY_USING_HAL)
+
+    Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
+#endif //defined (CY_USING_HAL)
+
+    Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
+#endif //defined (CY_USING_HAL)
+
+    Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
+#endif //defined (CY_USING_HAL)
+}

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h

@@ -0,0 +1,622 @@
+/*******************************************************************************
+* File Name: cycfg_pins.h
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PINS_H)
+#define CYCFG_PINS_H
+
+#include "cycfg_notices.h"
+#include "cy_gpio.h"
+#if defined (CY_USING_HAL)
+    #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cycfg_routing.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_WCO_IN_ENABLED 1U
+#define CYBSP_WCO_IN_PORT GPIO_PRT0
+#define CYBSP_WCO_IN_PORT_NUM 0U
+#define CYBSP_WCO_IN_PIN 0U
+#define CYBSP_WCO_IN_NUM 0U
+#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_0_HSIOM
+    #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
+#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_IN P0_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WCO_OUT_ENABLED 1U
+#define CYBSP_WCO_OUT_PORT GPIO_PRT0
+#define CYBSP_WCO_OUT_PORT_NUM 0U
+#define CYBSP_WCO_OUT_PIN 1U
+#define CYBSP_WCO_OUT_NUM 1U
+#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_1_HSIOM
+    #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
+#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_OUT P0_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_BT_POWER (P0_2)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_BT_DEVICE_WAKE (P0_3)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SW2 (P0_4)
+    #define CYBSP_USER_BTN1 CYBSP_SW2
+    #define CYBSP_USER_BTN CYBSP_SW2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_BT_HOST_WAKE (P0_5)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_DEBUG_UART_RX (P10_0)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_DEBUG_UART_TX (P10_1)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_LED4 (P11_1)
+    #define CYBSP_USER_LED1 CYBSP_LED4
+    #define CYBSP_USER_LED CYBSP_LED4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_QSPI_SS (P11_2)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_QSPI_D3 (P11_3)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_QSPI_D2 (P11_4)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_QSPI_D1 (P11_5)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_QSPI_D0 (P11_6)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_QSPI_SCK (P11_7)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WIFI_SDIO_D0 (P2_0)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WIFI_SDIO_D1 (P2_1)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WIFI_SDIO_D2 (P2_2)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WIFI_SDIO_D3 (P2_3)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WIFI_SDIO_CMD (P2_4)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WIFI_SDIO_CLK (P2_5)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WIFI_WL_REG_ON (P2_6)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WIFI_HOST_WAKE (P2_7)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_BT_UART_RX (P3_0)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_BT_UART_TX (P3_1)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_I2C_SCL (P6_4)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_I2C_SDA (P6_5)
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PORT_NUM 6U
+#define CYBSP_SWDIO_PIN 6U
+#define CYBSP_SWDIO_NUM 6U
+#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_6_HSIOM
+    #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDIO_HAL_PORT_PIN P6_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDIO P6_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDCK_ENABLED 1U
+#define CYBSP_SWDCK_PORT GPIO_PRT6
+#define CYBSP_SWDCK_PORT_NUM 6U
+#define CYBSP_SWDCK_PIN 7U
+#define CYBSP_SWDCK_NUM 7U
+#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWDCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_7_HSIOM
+    #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDCK_HAL_PORT_PIN P6_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDCK P6_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD0_ENABLED 1U
+#define CYBSP_CS_SLD0_ENABLED CYBSP_CSD_SLD0_ENABLED
+#define CYBSP_CSD_SLD0_PORT GPIO_PRT7
+#define CYBSP_CS_SLD0_PORT CYBSP_CSD_SLD0_PORT
+#define CYBSP_CSD_SLD0_PORT_NUM 7U
+#define CYBSP_CS_SLD0_PORT_NUM CYBSP_CSD_SLD0_PORT_NUM
+#define CYBSP_CSD_SLD0_PIN 0U
+#define CYBSP_CS_SLD0_PIN CYBSP_CSD_SLD0_PIN
+#define CYBSP_CSD_SLD0_NUM 0U
+#define CYBSP_CS_SLD0_NUM CYBSP_CSD_SLD0_NUM
+#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_SLD0_DRIVEMODE CYBSP_CSD_SLD0_DRIVEMODE
+#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
+#define CYBSP_CS_SLD0_INIT_DRIVESTATE CYBSP_CSD_SLD0_INIT_DRIVESTATE
+#ifndef ioss_0_port_7_pin_0_HSIOM
+    #define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_7_pin_0_HSIOM
+#define CYBSP_CS_SLD0_HSIOM CYBSP_CSD_SLD0_HSIOM
+#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CS_SLD0_IRQ CYBSP_CSD_SLD0_IRQ
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD0_HAL_PORT_PIN P7_0
+    #define CYBSP_CS_SLD0_HAL_PORT_PIN CYBSP_CSD_SLD0_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD0 P7_0
+    #define CYBSP_CS_SLD0 CYBSP_CSD_SLD0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_SLD0_HAL_IRQ CYBSP_CSD_SLD0_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_CS_SLD0_HAL_DIR CYBSP_CSD_SLD0_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_SLD0_HAL_DRIVEMODE CYBSP_CSD_SLD0_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD1_ENABLED 1U
+#define CYBSP_CS_SLD1_ENABLED CYBSP_CSD_SLD1_ENABLED
+#define CYBSP_CSD_SLD1_PORT GPIO_PRT7
+#define CYBSP_CS_SLD1_PORT CYBSP_CSD_SLD1_PORT
+#define CYBSP_CSD_SLD1_PORT_NUM 7U
+#define CYBSP_CS_SLD1_PORT_NUM CYBSP_CSD_SLD1_PORT_NUM
+#define CYBSP_CSD_SLD1_PIN 1U
+#define CYBSP_CS_SLD1_PIN CYBSP_CSD_SLD1_PIN
+#define CYBSP_CSD_SLD1_NUM 1U
+#define CYBSP_CS_SLD1_NUM CYBSP_CSD_SLD1_NUM
+#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_SLD1_DRIVEMODE CYBSP_CSD_SLD1_DRIVEMODE
+#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
+#define CYBSP_CS_SLD1_INIT_DRIVESTATE CYBSP_CSD_SLD1_INIT_DRIVESTATE
+#ifndef ioss_0_port_7_pin_1_HSIOM
+    #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_7_pin_1_HSIOM
+#define CYBSP_CS_SLD1_HSIOM CYBSP_CSD_SLD1_HSIOM
+#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CS_SLD1_IRQ CYBSP_CSD_SLD1_IRQ
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD1_HAL_PORT_PIN P7_1
+    #define CYBSP_CS_SLD1_HAL_PORT_PIN CYBSP_CSD_SLD1_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD1 P7_1
+    #define CYBSP_CS_SLD1 CYBSP_CSD_SLD1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_SLD1_HAL_IRQ CYBSP_CSD_SLD1_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_CS_SLD1_HAL_DIR CYBSP_CSD_SLD1_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_SLD1_HAL_DRIVEMODE CYBSP_CSD_SLD1_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD2_ENABLED 1U
+#define CYBSP_CS_SLD2_ENABLED CYBSP_CSD_SLD2_ENABLED
+#define CYBSP_CSD_SLD2_PORT GPIO_PRT7
+#define CYBSP_CS_SLD2_PORT CYBSP_CSD_SLD2_PORT
+#define CYBSP_CSD_SLD2_PORT_NUM 7U
+#define CYBSP_CS_SLD2_PORT_NUM CYBSP_CSD_SLD2_PORT_NUM
+#define CYBSP_CSD_SLD2_PIN 2U
+#define CYBSP_CS_SLD2_PIN CYBSP_CSD_SLD2_PIN
+#define CYBSP_CSD_SLD2_NUM 2U
+#define CYBSP_CS_SLD2_NUM CYBSP_CSD_SLD2_NUM
+#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_SLD2_DRIVEMODE CYBSP_CSD_SLD2_DRIVEMODE
+#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
+#define CYBSP_CS_SLD2_INIT_DRIVESTATE CYBSP_CSD_SLD2_INIT_DRIVESTATE
+#ifndef ioss_0_port_7_pin_2_HSIOM
+    #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_7_pin_2_HSIOM
+#define CYBSP_CS_SLD2_HSIOM CYBSP_CSD_SLD2_HSIOM
+#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CS_SLD2_IRQ CYBSP_CSD_SLD2_IRQ
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD2_HAL_PORT_PIN P7_2
+    #define CYBSP_CS_SLD2_HAL_PORT_PIN CYBSP_CSD_SLD2_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD2 P7_2
+    #define CYBSP_CS_SLD2 CYBSP_CSD_SLD2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_SLD2_HAL_IRQ CYBSP_CSD_SLD2_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_CS_SLD2_HAL_DIR CYBSP_CSD_SLD2_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_SLD2_HAL_DRIVEMODE CYBSP_CSD_SLD2_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD3_ENABLED 1U
+#define CYBSP_CS_SLD3_ENABLED CYBSP_CSD_SLD3_ENABLED
+#define CYBSP_CSD_SLD3_PORT GPIO_PRT7
+#define CYBSP_CS_SLD3_PORT CYBSP_CSD_SLD3_PORT
+#define CYBSP_CSD_SLD3_PORT_NUM 7U
+#define CYBSP_CS_SLD3_PORT_NUM CYBSP_CSD_SLD3_PORT_NUM
+#define CYBSP_CSD_SLD3_PIN 3U
+#define CYBSP_CS_SLD3_PIN CYBSP_CSD_SLD3_PIN
+#define CYBSP_CSD_SLD3_NUM 3U
+#define CYBSP_CS_SLD3_NUM CYBSP_CSD_SLD3_NUM
+#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_SLD3_DRIVEMODE CYBSP_CSD_SLD3_DRIVEMODE
+#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
+#define CYBSP_CS_SLD3_INIT_DRIVESTATE CYBSP_CSD_SLD3_INIT_DRIVESTATE
+#ifndef ioss_0_port_7_pin_3_HSIOM
+    #define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_7_pin_3_HSIOM
+#define CYBSP_CS_SLD3_HSIOM CYBSP_CSD_SLD3_HSIOM
+#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CS_SLD3_IRQ CYBSP_CSD_SLD3_IRQ
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD3_HAL_PORT_PIN P7_3
+    #define CYBSP_CS_SLD3_HAL_PORT_PIN CYBSP_CSD_SLD3_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD3 P7_3
+    #define CYBSP_CS_SLD3 CYBSP_CSD_SLD3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_SLD3_HAL_IRQ CYBSP_CSD_SLD3_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_CS_SLD3_HAL_DIR CYBSP_CSD_SLD3_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_SLD3_HAL_DRIVEMODE CYBSP_CSD_SLD3_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CMOD_ENABLED 1U
+#define CYBSP_CMOD_PORT GPIO_PRT7
+#define CYBSP_CMOD_PORT_NUM 7U
+#define CYBSP_CMOD_PIN 7U
+#define CYBSP_CMOD_NUM 7U
+#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CMOD_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_7_HSIOM
+    #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
+#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_CMOD_HAL_PORT_PIN P7_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CMOD P7_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN0_ENABLED 1U
+#define CYBSP_CS_BTN0_ENABLED CYBSP_CSD_BTN0_ENABLED
+#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
+#define CYBSP_CS_BTN0_PORT CYBSP_CSD_BTN0_PORT
+#define CYBSP_CSD_BTN0_PORT_NUM 8U
+#define CYBSP_CS_BTN0_PORT_NUM CYBSP_CSD_BTN0_PORT_NUM
+#define CYBSP_CSD_BTN0_PIN 0U
+#define CYBSP_CS_BTN0_PIN CYBSP_CSD_BTN0_PIN
+#define CYBSP_CSD_BTN0_NUM 0U
+#define CYBSP_CS_BTN0_NUM CYBSP_CSD_BTN0_NUM
+#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_BTN0_DRIVEMODE CYBSP_CSD_BTN0_DRIVEMODE
+#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
+#define CYBSP_CS_BTN0_INIT_DRIVESTATE CYBSP_CSD_BTN0_INIT_DRIVESTATE
+#ifndef ioss_0_port_8_pin_0_HSIOM
+    #define ioss_0_port_8_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_0_HSIOM
+#define CYBSP_CS_BTN0_HSIOM CYBSP_CSD_BTN0_HSIOM
+#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CS_BTN0_IRQ CYBSP_CSD_BTN0_IRQ
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_0
+    #define CYBSP_CS_BTN0_HAL_PORT_PIN CYBSP_CSD_BTN0_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN0 P8_0
+    #define CYBSP_CS_BTN0 CYBSP_CSD_BTN0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_BTN0_HAL_IRQ CYBSP_CSD_BTN0_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_CS_BTN0_HAL_DIR CYBSP_CSD_BTN0_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_BTN0_HAL_DRIVEMODE CYBSP_CSD_BTN0_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN1_ENABLED 1U
+#define CYBSP_CS_BTN1_ENABLED CYBSP_CSD_BTN1_ENABLED
+#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
+#define CYBSP_CS_BTN1_PORT CYBSP_CSD_BTN1_PORT
+#define CYBSP_CSD_BTN1_PORT_NUM 8U
+#define CYBSP_CS_BTN1_PORT_NUM CYBSP_CSD_BTN1_PORT_NUM
+#define CYBSP_CSD_BTN1_PIN 1U
+#define CYBSP_CS_BTN1_PIN CYBSP_CSD_BTN1_PIN
+#define CYBSP_CSD_BTN1_NUM 1U
+#define CYBSP_CS_BTN1_NUM CYBSP_CSD_BTN1_NUM
+#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_BTN1_DRIVEMODE CYBSP_CSD_BTN1_DRIVEMODE
+#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
+#define CYBSP_CS_BTN1_INIT_DRIVESTATE CYBSP_CSD_BTN1_INIT_DRIVESTATE
+#ifndef ioss_0_port_8_pin_1_HSIOM
+    #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_1_HSIOM
+#define CYBSP_CS_BTN1_HSIOM CYBSP_CSD_BTN1_HSIOM
+#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CS_BTN1_IRQ CYBSP_CSD_BTN1_IRQ
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_1
+    #define CYBSP_CS_BTN1_HAL_PORT_PIN CYBSP_CSD_BTN1_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN1 P8_1
+    #define CYBSP_CS_BTN1 CYBSP_CSD_BTN1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_BTN1_HAL_IRQ CYBSP_CSD_BTN1_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_CS_BTN1_HAL_DIR CYBSP_CSD_BTN1_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_BTN1_HAL_DRIVEMODE CYBSP_CSD_BTN1_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD4_ENABLED 1U
+#define CYBSP_CS_SLD4_ENABLED CYBSP_CSD_SLD4_ENABLED
+#define CYBSP_CSD_SLD4_PORT GPIO_PRT9
+#define CYBSP_CS_SLD4_PORT CYBSP_CSD_SLD4_PORT
+#define CYBSP_CSD_SLD4_PORT_NUM 9U
+#define CYBSP_CS_SLD4_PORT_NUM CYBSP_CSD_SLD4_PORT_NUM
+#define CYBSP_CSD_SLD4_PIN 0U
+#define CYBSP_CS_SLD4_PIN CYBSP_CSD_SLD4_PIN
+#define CYBSP_CSD_SLD4_NUM 0U
+#define CYBSP_CS_SLD4_NUM CYBSP_CSD_SLD4_NUM
+#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_SLD4_DRIVEMODE CYBSP_CSD_SLD4_DRIVEMODE
+#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
+#define CYBSP_CS_SLD4_INIT_DRIVESTATE CYBSP_CSD_SLD4_INIT_DRIVESTATE
+#ifndef ioss_0_port_9_pin_0_HSIOM
+    #define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_9_pin_0_HSIOM
+#define CYBSP_CS_SLD4_HSIOM CYBSP_CSD_SLD4_HSIOM
+#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_9_IRQn
+#define CYBSP_CS_SLD4_IRQ CYBSP_CSD_SLD4_IRQ
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD4_HAL_PORT_PIN P9_0
+    #define CYBSP_CS_SLD4_HAL_PORT_PIN CYBSP_CSD_SLD4_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD4 P9_0
+    #define CYBSP_CS_SLD4 CYBSP_CSD_SLD4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_SLD4_HAL_IRQ CYBSP_CSD_SLD4_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_CS_SLD4_HAL_DIR CYBSP_CSD_SLD4_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_SLD4_HAL_DRIVEMODE CYBSP_CSD_SLD4_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_BT_UART_RTS (P9_2)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_BT_UART_CTS (P9_3)
+#endif //defined (CY_USING_HAL)
+
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
+#define CYBSP_CS_SLD0_config CYBSP_CSD_SLD0_config
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
+    #define CYBSP_CS_SLD0_obj CYBSP_CSD_SLD0_obj
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
+#define CYBSP_CS_SLD1_config CYBSP_CSD_SLD1_config
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
+    #define CYBSP_CS_SLD1_obj CYBSP_CSD_SLD1_obj
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
+#define CYBSP_CS_SLD2_config CYBSP_CSD_SLD2_config
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
+    #define CYBSP_CS_SLD2_obj CYBSP_CSD_SLD2_obj
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
+#define CYBSP_CS_SLD3_config CYBSP_CSD_SLD3_config
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
+    #define CYBSP_CS_SLD3_obj CYBSP_CSD_SLD3_obj
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
+#define CYBSP_CS_BTN0_config CYBSP_CSD_BTN0_config
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
+    #define CYBSP_CS_BTN0_obj CYBSP_CSD_BTN0_obj
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
+#define CYBSP_CS_BTN1_config CYBSP_CSD_BTN1_config
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj;
+    #define CYBSP_CS_BTN1_obj CYBSP_CSD_BTN1_obj
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
+#define CYBSP_CS_SLD4_config CYBSP_CSD_SLD4_config
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
+    #define CYBSP_CS_SLD4_obj CYBSP_CSD_SLD4_obj
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_pins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PINS_H */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c

@@ -0,0 +1,271 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.c
+*
+* Description:
+* Provides definitions of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+* QSPI Configurator 2.20.0.2857
+*
+********************************************************************************
+* Copyright 2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_qspi_memslot.h"
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0xECU,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_QUAD,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0x01U,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_QUAD,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 4U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_QUAD
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x06U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x04U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0xDCU,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x60U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x34U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_QUAD,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_QUAD
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x35U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x05U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x01U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
+{
+    /* Specifies the number of address bytes used by the memory slave device. */
+    .numOfAddrBytes = 0x04U,
+    /* The size of the memory. */
+    .memSize = 0x04000000U,
+    /* Specifies the Read command. */
+    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd,
+    /* Specifies the Write Enable command. */
+    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd,
+    /* Specifies the Write Disable command. */
+    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd,
+    /* Specifies the Erase command. */
+    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd,
+    /* Specifies the sector size of each erase. */
+    .eraseSize = 0x00040000U,
+    /* Specifies the Chip Erase command. */
+    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd,
+    /* Specifies the Program command. */
+    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd,
+    /* Specifies the page size for programming. */
+    .programSize = 0x00000200U,
+    /* Specifies the command to read the QE-containing status register. */
+    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd,
+    /* Specifies the command to read the WIP-containing status register. */
+    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd,
+    /* Specifies the command to write into the QE-containing status register. */
+    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
+    /* The mask for the status register. */
+    .stsRegBusyMask = 0x01U,
+    /* The mask for the status register. */
+    .stsRegQuadEnableMask = 0x02U,
+    /* The max time for the erase type-1 cycle-time in ms. */
+    .eraseTime = 2600U,
+    /* The max time for the chip-erase cycle-time in ms. */
+    .chipEraseTime = 460000U,
+    /* The max time for the page-program cycle-time in us. */
+    .programTime = 1300U,
+#if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50)
+    /* Points to NULL or to structure with info about sectors for hybrid memory. */
+    .hybridRegionCount = 0U,
+    .hybridRegionInfo = NULL
+#endif
+};
+
+const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
+{
+    /* Determines the slot number where the memory device is placed. */
+    .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
+    /* Flags. */
+    .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
+    /* The data-line selection options for a slave device. */
+    .dataSelect = CY_SMIF_DATA_SEL0,
+    /* The base address the memory slave is mapped to in the PSoC memory map.
+    Valid when the memory-mapped mode is enabled. */
+    .baseAddress = 0x18000000U,
+    /* The size allocated in the PSoC memory map, for the memory slave device.
+    The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
+    .memMappedSize = 0x4000000U,
+    /* If this memory device is one of the devices in the dual quad SPI configuration.
+    Valid when the memory mapped mode is enabled. */
+    .dualQuadSlots = 0,
+    /* The configuration of the device. */
+    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0
+};
+
+const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
+   &S25FL512S_SlaveSlot_0
+};
+
+const cy_stc_smif_block_config_t smifBlockConfig =
+{
+    /* The number of SMIF memories defined. */
+    .memCount = CY_SMIF_DEVICE_NUM,
+    /* The pointer to the array of memory config structures of size memCount. */
+    .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
+    /* The version of the SMIF driver. */
+    .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
+    /* The version of the SMIF driver. */
+    .minorVersion = CY_SMIF_DRV_VERSION_MINOR
+};
+

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h

@@ -0,0 +1,65 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.h
+*
+* Description:
+* Provides declarations of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+* QSPI Configurator 2.20.0.2857
+*
+********************************************************************************
+* Copyright 2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#ifndef CYCFG_QSPI_MEMSLOT_H
+#define CYCFG_QSPI_MEMSLOT_H
+#include "cy_smif_memslot.h"
+
+#define CY_SMIF_CFG_TOOL_VERSION           (220)
+
+/* Supported QSPI Driver version */
+#define CY_SMIF_DRV_VERSION_REQUIRED       (100)
+
+#if !defined(CY_SMIF_DRV_VERSION)
+    #define CY_SMIF_DRV_VERSION            (100)
+#endif
+
+/* Check the used Driver version */
+#if (CY_SMIF_DRV_VERSION_REQUIRED > CY_SMIF_DRV_VERSION)
+   #error The QSPI Configurator requires a newer version of the PDL. Update the PDL in your project.
+#endif
+
+#define CY_SMIF_DEVICE_NUM 1
+
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
+
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
+
+extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
+
+extern const cy_stc_smif_block_config_t smifBlockConfig;
+
+
+#endif /*CYCFG_QSPI_MEMSLOT_H*/
+

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c

@@ -0,0 +1,44 @@
+/*******************************************************************************
+* File Name: cycfg_routing.c
+*
+* Description:
+* Establishes all necessary connections between hardware elements.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_routing.h"
+
+#include "cy_device_headers.h"
+
+void init_cycfg_routing(void)
+{
+    HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
+    HSIOM->AMUX_SPLIT_CTL[3] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
+}

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h

@@ -0,0 +1,58 @@
+/*******************************************************************************
+* File Name: cycfg_routing.h
+*
+* Description:
+* Establishes all necessary connections between hardware elements.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_ROUTING_H)
+#define CYCFG_ROUTING_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+void init_cycfg_routing(void);
+#define init_cycfg_connectivity() init_cycfg_routing()
+#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
+#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
+#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
+#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
+#define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_0_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_AMUXA
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_ROUTING_H */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c

@@ -0,0 +1,1157 @@
+/*******************************************************************************
+* File Name: cycfg_system.c
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_system.h"
+
+#define CY_CFG_SYSCLK_ECO_ERROR 1
+#define CY_CFG_SYSCLK_ALTHF_ERROR 2
+#define CY_CFG_SYSCLK_PLL_ERROR 3
+#define CY_CFG_SYSCLK_FLL_ERROR 4
+#define CY_CFG_SYSCLK_WCO_ERROR 5
+#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_WCO
+#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
+#define CY_CFG_SYSCLK_CLKFAST_DIVIDER 0
+#define CY_CFG_SYSCLK_FLL_ENABLED 1
+#define CY_CFG_SYSCLK_FLL_MULT 500U
+#define CY_CFG_SYSCLK_FLL_REFDIV 20U
+#define CY_CFG_SYSCLK_FLL_CCO_RANGE CY_SYSCLK_FLL_CCO_RANGE4
+#define CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV true
+#define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 10U
+#define CY_CFG_SYSCLK_FLL_IGAIN 9U
+#define CY_CFG_SYSCLK_FLL_PGAIN 5U
+#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 8U
+#define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT
+#define CY_CFG_SYSCLK_FLL_CCO_FREQ 355U
+#define CY_CFG_SYSCLK_FLL_OUT_FREQ 100000000
+#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
+#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_ILO_ENABLED 1
+#define CY_CFG_SYSCLK_ILO_HIBERNATE true
+#define CY_CFG_SYSCLK_IMO_ENABLED 1
+#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 0
+#define CY_CFG_SYSCLK_PLL0_ENABLED 1
+#define CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV 30
+#define CY_CFG_SYSCLK_PLL0_REFERENCE_DIV 1
+#define CY_CFG_SYSCLK_PLL0_OUTPUT_DIV 5
+#define CY_CFG_SYSCLK_PLL0_LF_MODE false
+#define CY_CFG_SYSCLK_PLL0_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
+#define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 48000000
+#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
+#define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 0
+#define CY_CFG_SYSCLK_WCO_ENABLED 1
+#define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT0
+#define CY_CFG_SYSCLK_WCO_IN_PIN 0U
+#define CY_CFG_SYSCLK_WCO_OUT_PRT GPIO_PRT0
+#define CY_CFG_SYSCLK_WCO_OUT_PIN 1U
+#define CY_CFG_SYSCLK_WCO_BYPASS CY_SYSCLK_WCO_NOT_BYPASSED
+#define CY_CFG_PWR_ENABLED 1
+#define CY_CFG_PWR_INIT 1
+#define CY_CFG_PWR_USING_PMIC 0
+#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
+#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
+#define CY_CFG_PWR_USING_ULP 0
+#define CY_CFG_PWR_REGULATOR_MODE_MIN false
+#define CY_CFG_PWR_BKP_ERROR 6
+
+#if defined (CY_DEVICE_SECURE)
+    static cy_stc_pra_system_config_t srss_0_clock_0_secureConfig;
+#endif //defined (CY_DEVICE_SECURE)
+#if (!defined(CY_DEVICE_SECURE))
+    static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
+    {
+        .fllMult = 500U,
+        .refDiv = 20U,
+        .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
+        .enableOutputDiv = true,
+        .lockTolerance = 10U,
+        .igain = 9U,
+        .pgain = 5U,
+        .settlingCount = 8U,
+        .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
+        .cco_Freq = 355U,
+    };
+#endif //(!defined(CY_DEVICE_SECURE))
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 0U,
+        .channel_num = 0U,
+    };
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 1U,
+        .channel_num = 0U,
+    };
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 2U,
+        .channel_num = 0U,
+    };
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 3U,
+        .channel_num = 0U,
+    };
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 4U,
+        .channel_num = 0U,
+    };
+#endif //defined (CY_USING_HAL)
+#if (!defined(CY_DEVICE_SECURE))
+    static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
+    {
+        .feedbackDiv = 30,
+        .referenceDiv = 1,
+        .outputDiv = 5,
+        .lfMode = false,
+        .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+    };
+#endif //(!defined(CY_DEVICE_SECURE))
+
+__WEAK void __NO_RETURN cycfg_ClockStartupError(uint32_t error)
+{
+    (void)error; /* Suppress the compiler warning */
+    while(1);
+}
+#if defined (CY_DEVICE_SECURE)
+    void init_cycfg_secure_struct(cy_stc_pra_system_config_t * secure_config)
+    {
+        #ifdef CY_CFG_PWR_ENABLED
+            secure_config->powerEnable = CY_CFG_PWR_ENABLED;
+        #endif /* CY_CFG_PWR_ENABLED */
+
+        #ifdef CY_CFG_PWR_USING_LDO
+            secure_config->ldoEnable = CY_CFG_PWR_USING_LDO;
+        #endif /* CY_CFG_PWR_USING_LDO */
+
+        #ifdef CY_CFG_PWR_USING_PMIC
+            secure_config->pmicEnable = CY_CFG_PWR_USING_PMIC;
+        #endif /* CY_CFG_PWR_USING_PMIC */
+
+        #ifdef CY_CFG_PWR_VBACKUP_USING_VDDD
+            secure_config->vBackupVDDDEnable = CY_CFG_PWR_VBACKUP_USING_VDDD;
+        #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
+
+        #ifdef CY_CFG_PWR_USING_ULP
+            secure_config->ulpEnable = CY_CFG_PWR_USING_ULP;
+        #endif /* CY_CFG_PWR_USING_ULP */
+
+        #ifdef CY_CFG_SYSCLK_ECO_ENABLED
+            secure_config->ecoEnable = CY_CFG_SYSCLK_ECO_ENABLED;
+        #endif /* CY_CFG_SYSCLK_ECO_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
+            secure_config->extClkEnable = CY_CFG_SYSCLK_EXTCLK_ENABLED;
+        #endif /* CY_CFG_SYSCLK_EXTCLK_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+            secure_config->iloEnable = CY_CFG_SYSCLK_ILO_ENABLED;
+        #endif /* CY_CFG_SYSCLK_ILO_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_WCO_ENABLED
+            secure_config->wcoEnable = CY_CFG_SYSCLK_WCO_ENABLED;
+        #endif /* CY_CFG_SYSCLK_WCO_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_FLL_ENABLED
+            secure_config->fllEnable = CY_CFG_SYSCLK_FLL_ENABLED;
+        #endif /* CY_CFG_SYSCLK_FLL_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_PLL0_ENABLED
+            secure_config->pll0Enable = CY_CFG_SYSCLK_PLL0_ENABLED;
+        #endif /* CY_CFG_SYSCLK_PLL0_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_PLL1_ENABLED
+            secure_config->pll1Enable = CY_CFG_SYSCLK_PLL1_ENABLED;
+        #endif /* CY_CFG_SYSCLK_PLL1_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
+            secure_config->path0Enable = CY_CFG_SYSCLK_CLKPATH0_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKPATH0_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+            secure_config->path1Enable = CY_CFG_SYSCLK_CLKPATH1_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKPATH1_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
+            secure_config->path2Enable = CY_CFG_SYSCLK_CLKPATH2_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKPATH2_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
+            secure_config->path3Enable = CY_CFG_SYSCLK_CLKPATH3_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKPATH3_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
+            secure_config->path4Enable = CY_CFG_SYSCLK_CLKPATH4_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKPATH4_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
+            secure_config->path5Enable = CY_CFG_SYSCLK_CLKPATH5_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKPATH5_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
+            secure_config->clkFastEnable = CY_CFG_SYSCLK_CLKFAST_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKFAST_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
+            secure_config->clkPeriEnable = CY_CFG_SYSCLK_CLKPERI_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKPERI_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
+            secure_config->clkSlowEnable = CY_CFG_SYSCLK_CLKSLOW_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKSLOW_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF0_ENABLED
+            secure_config->clkHF0Enable = CY_CFG_SYSCLK_CLKHF0_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKHF0_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
+            secure_config->clkHF1Enable = CY_CFG_SYSCLK_CLKHF1_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKHF1_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
+            secure_config->clkHF2Enable = CY_CFG_SYSCLK_CLKHF2_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKHF2_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
+            secure_config->clkHF3Enable = CY_CFG_SYSCLK_CLKHF3_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKHF3_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
+            secure_config->clkHF4Enable = CY_CFG_SYSCLK_CLKHF4_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKHF4_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
+            secure_config->clkHF5Enable = CY_CFG_SYSCLK_CLKHF5_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKHF5_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
+            secure_config->clkPumpEnable = CY_CFG_SYSCLK_CLKPUMP_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKPUMP_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+            secure_config->clkLFEnable = CY_CFG_SYSCLK_CLKLF_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKLF_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
+            secure_config->clkBakEnable = CY_CFG_SYSCLK_CLKBAK_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKBAK_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
+            secure_config->clkTimerEnable = CY_CFG_SYSCLK_CLKTIMER_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKTIMER_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
+            #error Configuration Error : ALT SYSTICK cannot be enabled for Secure devices.
+        #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_PILO_ENABLED
+            secure_config->piloEnable = CY_CFG_SYSCLK_PILO_ENABLED;
+        #endif /* CY_CFG_SYSCLK_PILO_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
+            secure_config->clkAltHfEnable = CY_CFG_SYSCLK_ALTHF_ENABLED;
+        #endif /* CY_CFG_SYSCLK_ALTHF_ENABLED */
+
+        #ifdef CY_CFG_PWR_LDO_VOLTAGE
+            secure_config->ldoVoltage = CY_CFG_PWR_LDO_VOLTAGE;
+        #endif /* CY_CFG_PWR_LDO_VOLTAGE */
+
+        #ifdef CY_CFG_PWR_REGULATOR_MODE_MIN
+            secure_config->pwrCurrentModeMin = CY_CFG_PWR_REGULATOR_MODE_MIN;
+        #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */
+
+        #ifdef CY_CFG_PWR_BUCK_VOLTAGE
+            secure_config->buckVoltage = CY_CFG_PWR_BUCK_VOLTAGE;
+        #endif /* CY_CFG_PWR_BUCK_VOLTAGE */
+
+        #ifdef CY_CFG_SYSCLK_ECO_FREQ
+            secure_config->ecoFreqHz = CY_CFG_SYSCLK_ECO_FREQ;
+        #endif /* CY_CFG_SYSCLK_ECO_FREQ */
+
+        #ifdef CY_CFG_SYSCLK_ECO_CLOAD
+            secure_config->ecoLoad = CY_CFG_SYSCLK_ECO_CLOAD;
+        #endif /* CY_CFG_SYSCLK_ECO_CLOAD */
+
+        #ifdef CY_CFG_SYSCLK_ECO_ESR
+            secure_config->ecoEsr = CY_CFG_SYSCLK_ECO_ESR;
+        #endif /* CY_CFG_SYSCLK_ECO_ESR */
+
+        #ifdef CY_CFG_SYSCLK_ECO_DRIVE_LEVEL
+            secure_config->ecoDriveLevel = CY_CFG_SYSCLK_ECO_DRIVE_LEVEL;
+        #endif /* CY_CFG_SYSCLK_ECO_DRIVE_LEVEL */
+
+        #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PRT
+            secure_config->ecoInPort = CY_CFG_SYSCLK_ECO_GPIO_IN_PRT;
+        #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PRT */
+
+        #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT
+            secure_config->ecoOutPort = CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT;
+        #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT */
+
+        #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PIN
+            secure_config->ecoInPinNum = CY_CFG_SYSCLK_ECO_GPIO_IN_PIN;
+        #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PIN */
+
+        #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN
+            secure_config->ecoOutPinNum = CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN;
+        #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN */
+
+        #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ
+            secure_config->extClkFreqHz = CY_CFG_SYSCLK_EXTCLK_FREQ;
+        #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */
+
+        #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PRT
+            secure_config->extClkPort = CY_CFG_SYSCLK_EXTCLK_GPIO_PRT;
+        #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PRT */
+
+        #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PIN
+            secure_config->extClkPinNum = CY_CFG_SYSCLK_EXTCLK_GPIO_PIN;
+        #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PIN */
+
+        #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM
+            secure_config->extClkHsiom = CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM;
+        #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM */
+
+        #ifdef CY_CFG_SYSCLK_ILO_HIBERNATE
+            secure_config->iloHibernateON = CY_CFG_SYSCLK_ILO_HIBERNATE;
+        #endif /* CY_CFG_SYSCLK_ILO_HIBERNATE */
+
+        #ifdef CY_CFG_SYSCLK_WCO_BYPASS
+            secure_config->bypassEnable = CY_CFG_SYSCLK_WCO_BYPASS;
+        #endif /* CY_CFG_SYSCLK_WCO_BYPASS */
+
+        #ifdef CY_CFG_SYSCLK_WCO_IN_PRT
+            secure_config->wcoInPort = CY_CFG_SYSCLK_WCO_IN_PRT;
+        #endif /* CY_CFG_SYSCLK_WCO_IN_PRT */
+
+        #ifdef CY_CFG_SYSCLK_WCO_OUT_PRT
+            secure_config->wcoOutPort = CY_CFG_SYSCLK_WCO_OUT_PRT;
+        #endif /* CY_CFG_SYSCLK_WCO_OUT_PRT */
+
+        #ifdef CY_CFG_SYSCLK_WCO_IN_PIN
+            secure_config->wcoInPinNum = CY_CFG_SYSCLK_WCO_IN_PIN;
+        #endif /* CY_CFG_SYSCLK_WCO_IN_PIN */
+
+        #ifdef CY_CFG_SYSCLK_WCO_OUT_PIN
+            secure_config->wcoOutPinNum = CY_CFG_SYSCLK_WCO_OUT_PIN;
+        #endif /* CY_CFG_SYSCLK_WCO_OUT_PIN */
+
+        #ifdef CY_CFG_SYSCLK_FLL_OUT_FREQ
+            secure_config->fllOutFreqHz = CY_CFG_SYSCLK_FLL_OUT_FREQ;
+        #endif /* CY_CFG_SYSCLK_FLL_OUT_FREQ */
+
+        #ifdef CY_CFG_SYSCLK_FLL_MULT
+            secure_config->fllMult = CY_CFG_SYSCLK_FLL_MULT;
+        #endif /* CY_CFG_SYSCLK_FLL_MULT */
+
+        #ifdef CY_CFG_SYSCLK_FLL_REFDIV
+            secure_config->fllRefDiv = CY_CFG_SYSCLK_FLL_REFDIV;
+        #endif /* CY_CFG_SYSCLK_FLL_REFDIV */
+
+        #ifdef CY_CFG_SYSCLK_FLL_CCO_RANGE
+            secure_config->fllCcoRange = CY_CFG_SYSCLK_FLL_CCO_RANGE;
+        #endif /* CY_CFG_SYSCLK_FLL_CCO_RANGE */
+
+        #ifdef CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV
+            secure_config->enableOutputDiv = CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV;
+        #endif /* CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV */
+
+        #ifdef CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE
+            secure_config->lockTolerance = CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE;
+        #endif /* CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE */
+
+        #ifdef CY_CFG_SYSCLK_FLL_IGAIN
+            secure_config->igain = CY_CFG_SYSCLK_FLL_IGAIN;
+        #endif /* CY_CFG_SYSCLK_FLL_IGAIN */
+
+        #ifdef CY_CFG_SYSCLK_FLL_PGAIN
+            secure_config->pgain = CY_CFG_SYSCLK_FLL_PGAIN;
+        #endif /* CY_CFG_SYSCLK_FLL_PGAIN */
+
+        #ifdef CY_CFG_SYSCLK_FLL_SETTLING_COUNT
+            secure_config->settlingCount = CY_CFG_SYSCLK_FLL_SETTLING_COUNT;
+        #endif /* CY_CFG_SYSCLK_FLL_SETTLING_COUNT */
+
+        #ifdef CY_CFG_SYSCLK_FLL_OUTPUT_MODE
+            secure_config->outputMode = CY_CFG_SYSCLK_FLL_OUTPUT_MODE;
+        #endif /* CY_CFG_SYSCLK_FLL_OUTPUT_MODE */
+
+        #ifdef CY_CFG_SYSCLK_FLL_CCO_FREQ
+            secure_config->ccoFreq = CY_CFG_SYSCLK_FLL_CCO_FREQ;
+        #endif /* CY_CFG_SYSCLK_FLL_CCO_FREQ */
+
+        #ifdef CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV
+            secure_config->pll0FeedbackDiv = CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV;
+        #endif /* CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV */
+
+        #ifdef CY_CFG_SYSCLK_PLL0_REFERENCE_DIV
+            secure_config->pll0ReferenceDiv = CY_CFG_SYSCLK_PLL0_REFERENCE_DIV;
+        #endif /* CY_CFG_SYSCLK_PLL0_REFERENCE_DIV */
+
+        #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_DIV
+            secure_config->pll0OutputDiv = CY_CFG_SYSCLK_PLL0_OUTPUT_DIV;
+        #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_DIV */
+
+        #ifdef CY_CFG_SYSCLK_PLL0_LF_MODE
+            secure_config->pll0LfMode = CY_CFG_SYSCLK_PLL0_LF_MODE;
+        #endif /* CY_CFG_SYSCLK_PLL0_LF_MODE */
+
+        #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_MODE
+            secure_config->pll0OutputMode = CY_CFG_SYSCLK_PLL0_OUTPUT_MODE;
+        #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_MODE */
+
+        #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ
+            secure_config->pll0OutFreqHz = CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ;
+        #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ */
+
+        #ifdef CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV
+            secure_config->pll1FeedbackDiv = CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV;
+        #endif /* CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV */
+
+        #ifdef CY_CFG_SYSCLK_PLL1_REFERENCE_DIV
+            secure_config->pll1ReferenceDiv = CY_CFG_SYSCLK_PLL1_REFERENCE_DIV;
+        #endif /* CY_CFG_SYSCLK_PLL1_REFERENCE_DIV */
+
+        #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_DIV
+            secure_config->pll1OutputDiv = CY_CFG_SYSCLK_PLL1_OUTPUT_DIV;
+        #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_DIV */
+
+        #ifdef CY_CFG_SYSCLK_PLL1_LF_MODE
+            secure_config->pll1LfMode = CY_CFG_SYSCLK_PLL1_LF_MODE;
+        #endif /* CY_CFG_SYSCLK_PLL1_LF_MODE */
+
+        #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_MODE
+            secure_config->pll1OutputMode = CY_CFG_SYSCLK_PLL1_OUTPUT_MODE;
+        #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_MODE */
+
+        #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ
+            secure_config->pll1OutFreqHz = CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ;
+        #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH0_SOURCE
+            secure_config->path0Src = CY_CFG_SYSCLK_CLKPATH0_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKPATH0_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH1_SOURCE
+            secure_config->path1Src = CY_CFG_SYSCLK_CLKPATH1_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKPATH1_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH2_SOURCE
+            secure_config->path2Src = CY_CFG_SYSCLK_CLKPATH2_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKPATH2_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH3_SOURCE
+            secure_config->path3Src = CY_CFG_SYSCLK_CLKPATH3_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKPATH3_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH4_SOURCE
+            secure_config->path4Src = CY_CFG_SYSCLK_CLKPATH4_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKPATH4_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH5_SOURCE
+            secure_config->path5Src = CY_CFG_SYSCLK_CLKPATH5_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKPATH5_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKFAST_DIVIDER
+            secure_config->clkFastDiv = CY_CFG_SYSCLK_CLKFAST_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKFAST_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKPERI_DIVIDER
+            secure_config->clkPeriDiv = CY_CFG_SYSCLK_CLKPERI_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKPERI_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKSLOW_DIVIDER
+            secure_config->clkSlowDiv = CY_CFG_SYSCLK_CLKSLOW_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKSLOW_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF0_CLKPATH
+            secure_config->hf0Source = CY_CFG_SYSCLK_CLKHF0_CLKPATH;
+        #endif /* CY_CFG_SYSCLK_CLKHF0_CLKPATH */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF0_DIVIDER
+            secure_config->hf0Divider = CY_CFG_SYSCLK_CLKHF0_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKHF0_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ
+            secure_config->hf0OutFreqMHz = CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ;
+        #endif /* CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF1_CLKPATH
+            secure_config->hf1Source = CY_CFG_SYSCLK_CLKHF1_CLKPATH;
+        #endif /* CY_CFG_SYSCLK_CLKHF1_CLKPATH */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF1_DIVIDER
+            secure_config->hf1Divider = CY_CFG_SYSCLK_CLKHF1_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKHF1_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ
+            secure_config->hf1OutFreqMHz = CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ;
+        #endif /* CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF2_CLKPATH
+            secure_config->hf2Source = CY_CFG_SYSCLK_CLKHF2_CLKPATH;
+        #endif /* CY_CFG_SYSCLK_CLKHF2_CLKPATH */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF2_DIVIDER
+            secure_config->hf2Divider = CY_CFG_SYSCLK_CLKHF2_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKHF2_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ
+            secure_config->hf2OutFreqMHz = CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ;
+        #endif /* CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF3_CLKPATH
+            secure_config->hf3Source = CY_CFG_SYSCLK_CLKHF3_CLKPATH;
+        #endif /* CY_CFG_SYSCLK_CLKHF3_CLKPATH */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF3_DIVIDER
+            secure_config->hf3Divider = CY_CFG_SYSCLK_CLKHF3_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKHF3_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ
+            secure_config->hf3OutFreqMHz = CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ;
+        #endif /* CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF4_CLKPATH
+            secure_config->hf4Source = CY_CFG_SYSCLK_CLKHF4_CLKPATH;
+        #endif /* CY_CFG_SYSCLK_CLKHF4_CLKPATH */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF4_DIVIDER
+            secure_config->hf4Divider = CY_CFG_SYSCLK_CLKHF4_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKHF4_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ
+            secure_config->hf4OutFreqMHz = CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ;
+        #endif /* CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF5_CLKPATH
+            secure_config->hf5Source = CY_CFG_SYSCLK_CLKHF5_CLKPATH;
+        #endif /* CY_CFG_SYSCLK_CLKHF5_CLKPATH */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF5_DIVIDER
+            secure_config->hf5Divider = CY_CFG_SYSCLK_CLKHF5_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKHF5_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ
+            secure_config->hf5OutFreqMHz = CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ;
+        #endif /* CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ */
+
+        #ifdef CY_CFG_SYSCLK_CLKPUMP_SOURCE
+            secure_config->pumpSource = CY_CFG_SYSCLK_CLKPUMP_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKPUMP_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKPUMP_DIVIDER
+            secure_config->pumpDivider = CY_CFG_SYSCLK_CLKPUMP_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKPUMP_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKLF_SOURCE
+            secure_config->clkLfSource = CY_CFG_SYSCLK_CLKLF_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKLF_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKBAK_SOURCE
+            secure_config->clkBakSource = CY_CFG_SYSCLK_CLKBAK_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKBAK_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKTIMER_SOURCE
+            secure_config->clkTimerSource = CY_CFG_SYSCLK_CLKTIMER_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKTIMER_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKTIMER_DIVIDER
+            secure_config->clkTimerDivider = CY_CFG_SYSCLK_CLKTIMER_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKTIMER_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE
+            secure_config->clkSrcAltSysTick = CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD
+            secure_config->altHFcLoad = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD;
+        #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD */
+
+        #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME
+            secure_config->altHFxtalStartUpTime = CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME;
+        #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME */
+
+        #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ
+            secure_config->altHFclkFreq = CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ;
+        #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ */
+
+        #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV
+            secure_config->altHFsysClkDiv = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV;
+        #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV */
+
+        #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR
+            secure_config->altHFvoltageReg = CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR;
+        #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR */
+    }
+#endif //defined (CY_DEVICE_SECURE)
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkBakInit()
+    {
+        Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkFastInit()
+    {
+        Cy_SysClk_ClkFastSetDivider(0U);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_FllInit()
+    {
+        if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
+        {
+            cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+        }
+        if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
+        {
+            cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+        }
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkHf0Init()
+    {
+        Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
+        Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_IloInit()
+    {
+        /* The WDT is unlocked in the default startup code */
+        Cy_SysClk_IloEnable();
+        Cy_SysClk_IloHibernateOn(true);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkLfInit()
+    {
+        /* The WDT is unlocked in the default startup code */
+        Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkPath0Init()
+    {
+        Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkPath1Init()
+    {
+        Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkPath2Init()
+    {
+        Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkPath3Init()
+    {
+        Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkPath4Init()
+    {
+        Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkPeriInit()
+    {
+        Cy_SysClk_ClkPeriSetDivider(0U);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_Pll0Init()
+    {
+        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
+        {
+            cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+        }
+        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
+        {
+            cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+        }
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkSlowInit()
+    {
+        Cy_SysClk_ClkSlowSetDivider(0U);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_WcoInit()
+    {
+        (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+        (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+        if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
+        {
+            cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
+        }
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void init_cycfg_power(void)
+    {
+        /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
+        #if (CY_CFG_PWR_VBACKUP_USING_VDDD)
+            #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+                if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
+                {
+                    Cy_SysLib_ResetBackupDomain();
+                    Cy_SysClk_IloDisable();
+                    Cy_SysClk_IloInit();
+                }
+            #endif /* CY_CFG_SYSCLK_ILO_ENABLED */
+        #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
+        /* Configure core regulator */
+        #if !(defined(CY_DEVICE_SECURE))
+            #if defined (CY_IP_M4CPUSS)
+                #if CY_CFG_PWR_USING_LDO
+                    Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
+                #else
+                    Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
+                #endif /* CY_CFG_PWR_USING_LDO */
+            #endif /* defined (CY_IP_M4CPUSS) */
+            #if CY_CFG_PWR_REGULATOR_MODE_MIN
+                Cy_SysPm_SystemSetMinRegulatorCurrent();
+            #else
+                Cy_SysPm_SystemSetNormalRegulatorCurrent();
+            #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */
+        #endif /* !(defined(CY_DEVICE_SECURE)) */
+        /* Configure PMIC */
+        Cy_SysPm_UnlockPmic();
+        #if CY_CFG_PWR_USING_PMIC
+            Cy_SysPm_PmicEnableOutput();
+        #else
+            Cy_SysPm_PmicDisableOutput();
+        #endif /* CY_CFG_PWR_USING_PMIC */
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+
+
+void init_cycfg_system(void)
+{
+    #if defined(CY_DEVICE_SECURE)
+        cy_en_pra_status_t configStatus;
+        init_cycfg_secure_struct(&srss_0_clock_0_secureConfig);
+        #if (((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM <= 5UL))  && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0UL))
+            #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+        #endif
+        #if (((CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 1UL))
+            #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+        #endif
+        #if (((CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 2UL))
+            #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+        #endif
+        #if (((CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 3UL))
+            #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+        #endif
+        #if (((CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 4UL))
+            #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+        #endif
+        #if (((CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 5UL))
+            #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+        #endif
+
+        configStatus = CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_SYS_CFG_FUNC,
+                                    CY_PRA_FUNC_INIT_CYCFG_DEVICE,
+                                    &srss_0_clock_0_secureConfig);
+        if ( configStatus != CY_PRA_STATUS_SUCCESS )
+        {
+            cycfg_ClockStartupError(configStatus);
+        }
+
+        #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ
+            Cy_SysClk_ExtClkSetFrequency(CY_CFG_SYSCLK_EXTCLK_FREQ);
+        #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */
+    #else /* defined(CY_DEVICE_SECURE) */
+
+        /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
+        Cy_SysLib_SetWaitStates(false, 150UL);
+        #ifdef CY_CFG_PWR_ENABLED
+            #ifdef CY_CFG_PWR_INIT
+                init_cycfg_power();
+            #else
+                #warning Power system will not be configured. Update power personality to v1.20 or later.
+            #endif /* CY_CFG_PWR_INIT */
+        #endif /* CY_CFG_PWR_ENABLED */
+
+        /* Reset the core clock path to default and disable all the FLLs/PLLs */
+        Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+        Cy_SysClk_ClkFastSetDivider(0U);
+        Cy_SysClk_ClkPeriSetDivider(1U);
+        Cy_SysClk_ClkSlowSetDivider(0U);
+        for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
+        {
+            (void)Cy_SysClk_PllDisable(pll);
+        }
+        Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
+
+        if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
+            (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
+        {
+            Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+        }
+
+        Cy_SysClk_FllDisable();
+        Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
+        Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
+        #ifdef CY_IP_MXBLESS
+            (void)Cy_BLE_EcoReset();
+        #endif
+
+
+        /* Enable all source clocks */
+        #ifdef CY_CFG_SYSCLK_PILO_ENABLED
+            Cy_SysClk_PiloInit();
+        #endif
+
+        #ifdef CY_CFG_SYSCLK_WCO_ENABLED
+            Cy_SysClk_WcoInit();
+        #endif
+
+        #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+            Cy_SysClk_ClkLfInit();
+        #endif
+
+        #if (defined(CY_IP_M4CPUSS) && CY_CFG_SYSCLK_ALTHF_ENABLED)
+
+            Cy_SysClk_AltHfInit();
+        #endif /* (defined(CY_IP_M4CPUSS) && CY_CFG_SYSCLK_ALTHF_ENABLED */
+
+
+        #ifdef CY_CFG_SYSCLK_ECO_ENABLED
+            Cy_SysClk_EcoInit();
+        #endif
+
+        #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
+            Cy_SysClk_ExtClkInit();
+        #endif
+
+        /* Configure CPU clock dividers */
+        #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
+            Cy_SysClk_ClkFastInit();
+        #endif
+
+        #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
+            Cy_SysClk_ClkPeriInit();
+        #endif
+
+        #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
+            Cy_SysClk_ClkSlowInit();
+        #endif
+
+        #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U))
+            /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
+            Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
+            Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+        #else
+            #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+                Cy_SysClk_ClkPath1Init();
+            #endif
+        #endif
+
+        /* Configure Path Clocks */
+        #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
+            Cy_SysClk_ClkPath0Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
+            Cy_SysClk_ClkPath2Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
+            Cy_SysClk_ClkPath3Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
+            Cy_SysClk_ClkPath4Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
+            Cy_SysClk_ClkPath5Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
+            Cy_SysClk_ClkPath6Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
+            Cy_SysClk_ClkPath7Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
+            Cy_SysClk_ClkPath8Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
+            Cy_SysClk_ClkPath9Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
+            Cy_SysClk_ClkPath10Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
+            Cy_SysClk_ClkPath11Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
+            Cy_SysClk_ClkPath12Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
+            Cy_SysClk_ClkPath13Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
+            Cy_SysClk_ClkPath14Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
+            Cy_SysClk_ClkPath15Init();
+        #endif
+
+        /* Configure and enable FLL */
+        #ifdef CY_CFG_SYSCLK_FLL_ENABLED
+            Cy_SysClk_FllInit();
+        #endif
+
+        Cy_SysClk_ClkHf0Init();
+
+        #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U))
+            #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+                /* Apply the ClkPath1 user setting */
+                Cy_SysClk_ClkPath1Init();
+            #endif
+        #endif
+
+        /* Configure and enable PLLs */
+        #ifdef CY_CFG_SYSCLK_PLL0_ENABLED
+            Cy_SysClk_Pll0Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL1_ENABLED
+            Cy_SysClk_Pll1Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL2_ENABLED
+            Cy_SysClk_Pll2Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL3_ENABLED
+            Cy_SysClk_Pll3Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL4_ENABLED
+            Cy_SysClk_Pll4Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL5_ENABLED
+            Cy_SysClk_Pll5Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL6_ENABLED
+            Cy_SysClk_Pll6Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL7_ENABLED
+            Cy_SysClk_Pll7Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL8_ENABLED
+            Cy_SysClk_Pll8Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL9_ENABLED
+            Cy_SysClk_Pll9Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL10_ENABLED
+            Cy_SysClk_Pll10Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL11_ENABLED
+            Cy_SysClk_Pll11Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL12_ENABLED
+            Cy_SysClk_Pll12Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL13_ENABLED
+            Cy_SysClk_Pll13Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL14_ENABLED
+            Cy_SysClk_Pll14Init();
+        #endif
+
+        /* Configure HF clocks */
+        #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
+            Cy_SysClk_ClkHf1Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
+            Cy_SysClk_ClkHf2Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
+            Cy_SysClk_ClkHf3Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
+            Cy_SysClk_ClkHf4Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
+            Cy_SysClk_ClkHf5Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
+            Cy_SysClk_ClkHf6Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
+            Cy_SysClk_ClkHf7Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
+            Cy_SysClk_ClkHf8Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
+            Cy_SysClk_ClkHf9Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
+            Cy_SysClk_ClkHf10Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
+            Cy_SysClk_ClkHf11Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
+            Cy_SysClk_ClkHf12Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
+            Cy_SysClk_ClkHf13Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
+            Cy_SysClk_ClkHf14Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
+            Cy_SysClk_ClkHf15Init();
+        #endif
+
+        /* Configure miscellaneous clocks */
+        #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
+            Cy_SysClk_ClkTimerInit();
+        #endif
+
+        #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
+            Cy_SysClk_ClkAltSysTickInit();
+        #endif
+
+        #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
+            Cy_SysClk_ClkPumpInit();
+        #endif
+
+        #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
+            Cy_SysClk_ClkBakInit();
+        #endif
+
+        /* Configure default enabled clocks */
+        #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+            Cy_SysClk_IloInit();
+        #endif
+
+        #ifndef CY_CFG_SYSCLK_IMO_ENABLED
+            #error the IMO must be enabled for proper chip operation
+        #endif
+
+        #ifndef CY_CFG_SYSCLK_CLKHF0_ENABLED
+            #error the CLKHF0 must be enabled for proper chip operation
+        #endif
+
+    #endif /* defined(CY_DEVICE_SECURE) */
+
+    #ifdef CY_CFG_SYSCLK_MFO_ENABLED
+        Cy_SysClk_MfoInit();
+    #endif
+
+    #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
+        Cy_SysClk_ClkMfInit();
+    #endif
+
+    #if (!defined(CY_DEVICE_SECURE))
+        /* Set accurate flash wait states */
+        #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
+            Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
+        #endif
+
+        /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
+        SystemCoreClockUpdate();
+        #ifndef CY_CFG_SYSCLK_ILO_ENABLED
+            #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+            /* Wait 4 ILO cycles in case of unfinished CLKLF clock source transition */
+            Cy_SysLib_DelayUs(200U);
+            #endif
+        Cy_SysClk_IloDisable();
+        Cy_SysClk_IloHibernateOn(false);
+        #endif
+
+    #endif /* (!defined(CY_DEVICE_SECURE)) */
+
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
+#endif //defined (CY_USING_HAL)
+}

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h

@@ -0,0 +1,109 @@
+/*******************************************************************************
+* File Name: cycfg_system.h
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_SYSTEM_H)
+#define CYCFG_SYSTEM_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_pra.h"
+#include "cy_pra_cfg.h"
+#if defined (CY_USING_HAL)
+    #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cy_gpio.h"
+#include "cy_syspm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define cpuss_0_dap_0_ENABLED 1U
+#define srss_0_clock_0_ENABLED 1U
+#define srss_0_clock_0_bakclk_0_ENABLED 1U
+#define srss_0_clock_0_fastclk_0_ENABLED 1U
+#define srss_0_clock_0_fll_0_ENABLED 1U
+#define srss_0_clock_0_hfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF0 0UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
+#define srss_0_clock_0_ilo_0_ENABLED 1U
+#define srss_0_clock_0_imo_0_ENABLED 1U
+#define srss_0_clock_0_lfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO
+#define srss_0_clock_0_pathmux_0_ENABLED 1U
+#define srss_0_clock_0_pathmux_1_ENABLED 1U
+#define srss_0_clock_0_pathmux_2_ENABLED 1U
+#define srss_0_clock_0_pathmux_3_ENABLED 1U
+#define srss_0_clock_0_pathmux_4_ENABLED 1U
+#define srss_0_clock_0_periclk_0_ENABLED 1U
+#define srss_0_clock_0_pll_0_ENABLED 1U
+#define srss_0_clock_0_slowclk_0_ENABLED 1U
+#define srss_0_clock_0_wco_0_ENABLED 1U
+#define srss_0_power_0_ENABLED 1U
+#define CY_CFG_PWR_MODE_LP 0x01UL
+#define CY_CFG_PWR_MODE_ULP 0x02UL
+#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
+#define CY_CFG_PWR_MODE_SLEEP 0x08UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
+#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
+#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
+#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
+#define CY_CFG_PWR_USING_LDO 1
+#define CY_CFG_PWR_VDDA_MV 3300
+#define CY_CFG_PWR_VDDD_MV 3300
+#define CY_CFG_PWR_VBACKUP_MV 3300
+#define CY_CFG_PWR_VDD_NS_MV 3300
+#define CY_CFG_PWR_VDDIO0_MV 3300
+#define CY_CFG_PWR_VDDIO1_MV 3300
+
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_system(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_SYSTEM_H */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg

@@ -0,0 +1,29 @@
+################################################################################
+# File Name: qspi_config.cfg
+#
+# Description:
+# This file contains a SMIF Bank layout for use with OpenOCD.
+# This file was automatically generated and should not be modified.
+# QSPI Configurator: 2.20.0.2857
+#
+################################################################################
+# Copyright 2020 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+set SMIF_BANKS {
+  0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
+}
+

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -0,0 +1,20 @@
+[Device=CY8C6245LQI-S3D72]
+ 
+[Blocks]
+# WIFI
+# CYBSP_WIFI_SDIO
+sdhc[0]
+# CYBSP_WIFI_SDIO_D0
+ioss[0].port[2].pin[0]
+# CYBSP_WIFI_SDIO_D1
+ioss[0].port[2].pin[1]
+# CYBSP_WIFI_SDIO_D2
+ioss[0].port[2].pin[2]
+# CYBSP_WIFI_SDIO_D3
+ioss[0].port[2].pin[3]
+# CYBSP_WIFI_SDIO_CMD
+ioss[0].port[2].pin[4]
+# CYBSP_WIFI_SDIO_CLK
+ioss[0].port[2].pin[5]
+# CYBSP_WIFI_WL_REG_ON
+ioss[0].port[2].pin[6]

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense

@@ -0,0 +1,405 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by CapSense Configurator 4.0.0.5470-->
+<Configuration app="Capsense" major="4" minor="0" lastSavedWithToolName="CapSense Configurator" formatVersion="1">
+    <DesignProperties>
+        <Property id="DEVICE_TYPE" value="P6_CSDV2"/>
+    </DesignProperties>
+    <GeneralProperties>
+        <Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="REGULAR_IIR_RC_N" value="128"/>
+        <Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="PROX_IIR_RC_N" value="128"/>
+        <Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="REGULAR_IIR_BL_N" value="1"/>
+        <Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="PROX_IIR_BL_N" value="1"/>
+        <Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="MULTI_FREQ_SCAN_EN" value="false"/>
+        <Property id="SENSOR_AUTO_RESET_EN" value="false"/>
+        <Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
+        <Property id="VREF_SOURCE" value="SRSS"/>
+        <Property id="IREF_SOURCE" value="SRSS"/>
+        <Property id="PROX_TOUCH_COEFF" value="300"/>
+        <Property id="BIST_EN" value="false"/>
+        <Property id="BIST_SHIELD_CAP_ISC" value="BIST_IO_STRONG"/>
+        <Property id="BIST_SNS_CAP_CSD_ISC" value="BIST_IO_STRONG"/>
+        <Property id="BIST_SNS_CAP_CSX_ISC" value="BIST_IO_STRONG"/>
+        <Property id="BIST_FINE_INIT_TIME" value="10"/>
+        <Property id="BIST_ELTD_CAP_MOD_CLC_DIVIDER" value="2"/>
+        <Property id="BIST_ELTD_CAP_SNS_CLC_DIVIDER" value="0"/>
+        <Property id="BIST_ELTD_CAP_RESOLUTION" value="12"/>
+        <Property id="BIST_ELTD_CAP_VREF_MV" value="1200"/>
+        <Property id="BIST_SHORT_SETTLING_TIME" value="2"/>
+        <Property id="VDDA_MOD_CLK" value="2"/>
+        <Property id="VDDA_VREF_MV" value="1200"/>
+        <Property id="EXT_CAP_MOD_CLK" value="2"/>
+        <Property id="EXT_CAP_SNS_CLK" value="1024"/>
+        <Property id="EXT_CAP_VREF_MV" value="1200"/>
+        <Property id="NUM_CENTROIDS" value="1"/>
+    </GeneralProperties>
+    <CsdProperties>
+        <Property id="CSD_AUTOTUNE" value="HWTH"/>
+        <Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
+        <Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
+        <Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
+        <Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
+        <Property id="CSD_IDAC_MIN" value="20"/>
+        <Property id="CSD_IDAC_COMP_EN" value="true"/>
+        <Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
+        <Property id="CSD_VREF_CUSTOM" value="false"/>
+        <Property id="CSD_VREF" value="1219"/>
+        <Property id="CSD_SHIELD_EN" value="false"/>
+        <Property id="CSD_SHIELD_TANK_EN" value="false"/>
+        <Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
+        <Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
+        <Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_FINE_INIT_TIME" value="10"/>
+        <Property id="CSD_CALIBRATION_ERROR" value="10"/>
+        <Property id="CSD_R_CONST" value="1000"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsdProperties>
+    <CsxProperties>
+        <Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSX_INACTIVE_SNS_CONNECTION" value="GROUND"/>
+        <Property id="CSX_MAX_FINGERS" value="3"/>
+        <Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
+        <Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
+        <Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_FINE_INIT_TIME" value="10"/>
+        <Property id="CSX_CALIBRATION_ERROR" value="20"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsxProperties>
+    <Widgets>
+        <Widget id="Button0" type="CSD_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Sns0" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="Button1" type="CSD_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Sns0" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="LinearSlider0" type="LINEAR_SLIDER">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="100"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Sns0" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns1" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns2" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns3" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns4" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+    </Widgets>
+</Configuration>

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi

@@ -0,0 +1,63 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.20.0.2857-->
+<Configuration app="QSPI" major="2" minor="20">
+    <DevicePath>PSoC 6.xml</DevicePath>
+    <SlotConfigs>
+        <SlotConfig>
+            <SlaveSlot>0</SlaveSlot>
+            <MemoryId>S25FL512S-4byteaddr</MemoryId>
+            <MemoryMapped>true</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18000000</StartAddress>
+            <Size>0x4000000</Size>
+            <EndAddress>0x1BFFFFFF</EndAddress>
+            <WriteEnable>true</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
+            <MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>1</SlaveSlot>
+            <MemoryId>Not used</MemoryId>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18010000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1801FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>2</SlaveSlot>
+            <MemoryId>Not used</MemoryId>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18020000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1802FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>3</SlaveSlot>
+            <MemoryId>Not used</MemoryId>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18030000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1803FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+    </SlotConfigs>
+</Configuration>

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus

@@ -0,0 +1,480 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Design version="12" xmlns="http://cypress.com/xsd/cydesignfile_v3">
+    <ToolInfo version="2.4.0.5721"/>
+    <Devices>
+        <Device mpn="CY8C6245LQI-S3D72">
+            <BlockConfig>
+                <Block location="cpuss[0].dap[0]">
+                    <Personality template="mxs40dap" version="1.0">
+                        <Param id="dbgMode" value="SWD"/>
+                        <Param id="traceEnable" value="false"/>
+                    </Personality>
+                </Block>
+                <Block location="csd[0].csd[0]">
+                    <Alias value="CYBSP_CSD"/>
+                    <Personality template="mxs40csd" version="2.0">
+                        <Param id="CapSenseEnable" value="true"/>
+                        <Param id="CapSenseCore" value="4"/>
+                        <Param id="SensorCount" value="8"/>
+                        <Param id="CapacitorCount" value="1"/>
+                        <Param id="SensorName0" value="Cmod"/>
+                        <Param id="SensorName1" value="Button0_Sns0"/>
+                        <Param id="SensorName2" value="Button1_Sns0"/>
+                        <Param id="SensorName3" value="LinearSlider0_Sns0"/>
+                        <Param id="SensorName4" value="LinearSlider0_Sns1"/>
+                        <Param id="SensorName5" value="LinearSlider0_Sns2"/>
+                        <Param id="SensorName6" value="LinearSlider0_Sns3"/>
+                        <Param id="SensorName7" value="LinearSlider0_Sns4"/>
+                        <Param id="CapSenseConfigurator" value="0"/>
+                        <Param id="CapSenseTuner" value="0"/>
+                        <Param id="CsdAdcEnable" value="false"/>
+                        <Param id="numChannels" value="1"/>
+                        <Param id="resolution" value="CY_CSDADC_RESOLUTION_10BIT"/>
+                        <Param id="range" value="CY_CSDADC_RANGE_VDDA"/>
+                        <Param id="acqTime" value="10"/>
+                        <Param id="autoCalibrInterval" value="30"/>
+                        <Param id="vref" value="-1"/>
+                        <Param id="operClkDivider" value="1"/>
+                        <Param id="azTime" value="5"/>
+                        <Param id="csdInitTime" value="25"/>
+                        <Param id="inFlash" value="true"/>
+                        <Param id="CsdIdacEnable" value="false"/>
+                        <Param id="CsdIdacAselect" value="CY_CSDIDAC_GPIO"/>
+                        <Param id="CsdIdacBselect" value="CY_CSDIDAC_DISABLED"/>
+                        <Param id="csdIdacInitTime" value="25"/>
+                        <Param id="idacInFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[0].pin[0]">
+                    <Alias value="CYBSP_WCO_IN"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[0].pin[1]">
+                    <Alias value="CYBSP_WCO_OUT"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[0].pin[2]">
+                    <Alias value="CYBSP_BT_POWER"/>
+                </Block>
+                <Block location="ioss[0].port[0].pin[3]">
+                    <Alias value="CYBSP_BT_DEVICE_WAKE"/>
+                </Block>
+                <Block location="ioss[0].port[0].pin[4]">
+                    <Alias value="CYBSP_SW2"/>
+                    <Alias value="CYBSP_USER_BTN1"/>
+                    <Alias value="CYBSP_USER_BTN"/>
+                </Block>
+                <Block location="ioss[0].port[0].pin[5]">
+                    <Alias value="CYBSP_BT_HOST_WAKE"/>
+                </Block>
+                <Block location="ioss[0].port[10].pin[0]">
+                    <Alias value="CYBSP_DEBUG_UART_RX"/>
+                </Block>
+                <Block location="ioss[0].port[10].pin[1]">
+                    <Alias value="CYBSP_DEBUG_UART_TX"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[1]">
+                    <Alias value="CYBSP_LED4"/>
+                    <Alias value="CYBSP_USER_LED1"/>
+                    <Alias value="CYBSP_USER_LED"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[2]">
+                    <Alias value="CYBSP_QSPI_SS"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[3]">
+                    <Alias value="CYBSP_QSPI_D3"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[4]">
+                    <Alias value="CYBSP_QSPI_D2"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[5]">
+                    <Alias value="CYBSP_QSPI_D1"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[6]">
+                    <Alias value="CYBSP_QSPI_D0"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[7]">
+                    <Alias value="CYBSP_QSPI_SCK"/>
+                </Block>
+                <Block location="ioss[0].port[2].pin[0]">
+                    <Alias value="CYBSP_WIFI_SDIO_D0"/>
+                </Block>
+                <Block location="ioss[0].port[2].pin[1]">
+                    <Alias value="CYBSP_WIFI_SDIO_D1"/>
+                </Block>
+                <Block location="ioss[0].port[2].pin[2]">
+                    <Alias value="CYBSP_WIFI_SDIO_D2"/>
+                </Block>
+                <Block location="ioss[0].port[2].pin[3]">
+                    <Alias value="CYBSP_WIFI_SDIO_D3"/>
+                </Block>
+                <Block location="ioss[0].port[2].pin[4]">
+                    <Alias value="CYBSP_WIFI_SDIO_CMD"/>
+                </Block>
+                <Block location="ioss[0].port[2].pin[5]">
+                    <Alias value="CYBSP_WIFI_SDIO_CLK"/>
+                </Block>
+                <Block location="ioss[0].port[2].pin[6]">
+                    <Alias value="CYBSP_WIFI_WL_REG_ON"/>
+                </Block>
+                <Block location="ioss[0].port[2].pin[7]">
+                    <Alias value="CYBSP_WIFI_HOST_WAKE"/>
+                </Block>
+                <Block location="ioss[0].port[3].pin[0]">
+                    <Alias value="CYBSP_BT_UART_RX"/>
+                </Block>
+                <Block location="ioss[0].port[3].pin[1]">
+                    <Alias value="CYBSP_BT_UART_TX"/>
+                </Block>
+                <Block location="ioss[0].port[6].pin[4]">
+                    <Alias value="CYBSP_I2C_SCL"/>
+                </Block>
+                <Block location="ioss[0].port[6].pin[5]">
+                    <Alias value="CYBSP_I2C_SDA"/>
+                </Block>
+                <Block location="ioss[0].port[6].pin[6]">
+                    <Alias value="CYBSP_SWDIO"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[6].pin[7]">
+                    <Alias value="CYBSP_SWDCK"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[7].pin[0]">
+                    <Alias value="CYBSP_CSD_SLD0"/>
+                    <Alias value="CYBSP_CS_SLD0"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[7].pin[1]">
+                    <Alias value="CYBSP_CSD_SLD1"/>
+                    <Alias value="CYBSP_CS_SLD1"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[7].pin[2]">
+                    <Alias value="CYBSP_CSD_SLD2"/>
+                    <Alias value="CYBSP_CS_SLD2"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[7].pin[3]">
+                    <Alias value="CYBSP_CSD_SLD3"/>
+                    <Alias value="CYBSP_CS_SLD3"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[7].pin[7]">
+                    <Alias value="CYBSP_CMOD"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[8].pin[0]">
+                    <Alias value="CYBSP_CSD_BTN0"/>
+                    <Alias value="CYBSP_CS_BTN0"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[8].pin[1]">
+                    <Alias value="CYBSP_CSD_BTN1"/>
+                    <Alias value="CYBSP_CS_BTN1"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[9].pin[0]">
+                    <Alias value="CYBSP_CSD_SLD4"/>
+                    <Alias value="CYBSP_CS_SLD4"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[9].pin[2]">
+                    <Alias value="CYBSP_BT_UART_RTS"/>
+                </Block>
+                <Block location="ioss[0].port[9].pin[3]">
+                    <Alias value="CYBSP_BT_UART_CTS"/>
+                </Block>
+                <Block location="peri[0].div_8[0]">
+                    <Alias value="CYBSP_CSD_CLK_DIV"/>
+                    <Alias value="CYBSP_CS_CLK_DIV"/>
+                    <Personality template="mxs40peripheralclock" version="1.0">
+                        <Param id="intDivider" value="256"/>
+                        <Param id="fracDivider" value="0"/>
+                        <Param id="startOnReset" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0]">
+                    <Personality template="mxs40sysclocks" version="1.2"/>
+                </Block>
+                <Block location="srss[0].clock[0].bakclk[0]">
+                    <Personality template="mxs40bakclk" version="1.0">
+                        <Param id="sourceClock" value="wco"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].fastclk[0]">
+                    <Personality template="mxs40fastclk" version="1.0">
+                        <Param id="divider" value="1"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].fll[0]">
+                    <Personality template="mxs40fll" version="2.0">
+                        <Param id="configuration" value="auto"/>
+                        <Param id="desiredFrequency" value="100.000"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].hfclk[0]">
+                    <Personality template="mxs40hfclk" version="1.1">
+                        <Param id="sourceClockNumber" value="0"/>
+                        <Param id="divider" value="1"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].ilo[0]">
+                    <Personality template="mxs40ilo" version="1.0">
+                        <Param id="hibernate" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].imo[0]">
+                    <Personality template="mxs40imo" version="1.0">
+                        <Param id="trim" value="1"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].lfclk[0]">
+                    <Personality template="mxs40lfclk" version="1.1">
+                        <Param id="sourceClock" value="wco"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[0]">
+                    <Personality template="mxs40pathmux" version="1.0">
+                        <Param id="sourceClock" value="imo"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[1]">
+                    <Personality template="mxs40pathmux" version="1.0">
+                        <Param id="sourceClock" value="imo"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[2]">
+                    <Personality template="mxs40pathmux" version="1.0">
+                        <Param id="sourceClock" value="imo"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[3]">
+                    <Personality template="mxs40pathmux" version="1.0">
+                        <Param id="sourceClock" value="imo"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[4]">
+                    <Personality template="mxs40pathmux" version="1.0">
+                        <Param id="sourceClock" value="imo"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].periclk[0]">
+                    <Personality template="mxs40periclk" version="1.0">
+                        <Param id="divider" value="1"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].pll[0]">
+                    <Personality template="mxs40pll" version="2.0">
+                        <Param id="lowFrequencyMode" value="false"/>
+                        <Param id="configuration" value="auto"/>
+                        <Param id="desiredFrequency" value="48.000"/>
+                        <Param id="optimization" value="MinPower"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].slowclk[0]">
+                    <Personality template="mxs40slowclk" version="1.0">
+                        <Param id="divider" value="1"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].wco[0]">
+                    <Personality template="mxs40wco" version="1.0">
+                        <Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
+                        <Param id="clockLostDetection" value="false"/>
+                        <Param id="clockSupervisor" value="CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO"/>
+                        <Param id="lossWindow" value="CY_SYSCLK_CSV_LOSS_4_CYCLES"/>
+                        <Param id="lossAction" value="CY_SYSCLK_CSV_ERROR_FAULT"/>
+                        <Param id="accuracyPpm" value="150"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].power[0]">
+                    <Personality template="mxs40power" version="1.3">
+                        <Param id="pwrMode" value="LDO_1_1"/>
+                        <Param id="actPwrMode" value="LP"/>
+                        <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
+                        <Param id="pmicEnable" value="false"/>
+                        <Param id="backupSrc" value="VDDD"/>
+                        <Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
+                        <Param id="deepsleepLatency" value="0"/>
+                        <Param id="vddaMv" value="3300"/>
+                        <Param id="vdddMv" value="3300"/>
+                        <Param id="vBackupMv" value="3300"/>
+                        <Param id="vddNsMv" value="3300"/>
+                        <Param id="vddio0Mv" value="3300"/>
+                        <Param id="vddio1Mv" value="3300"/>
+                    </Personality>
+                </Block>
+            </BlockConfig>
+            <Netlist>
+                <Net>
+                    <Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
+                    <Port name="ioss[0].port[6].pin[7].digital_in[0]"/>
+                </Net>
+                <Net>
+                    <Port name="cpuss[0].dap[0].swj_swdio_tms[0]"/>
+                    <Port name="ioss[0].port[6].pin[6].digital_inout[0]"/>
+                </Net>
+                <Net>
+                    <Port name="csd[0].csd[0].clock[0]"/>
+                    <Port name="peri[0].div_8[0].clk[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[0].pin[0].analog[0]"/>
+                    <Port name="srss[0].clock[0].wco[0].wco_in[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[0].pin[1].analog[0]"/>
+                    <Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
+                </Net>
+                <Mux name="sense" location="csd[0].csd[0]">
+                    <Arm>
+                        <Port name="ioss[0].port[7].pin[7].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[0].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[1].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[7].pin[0].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[7].pin[1].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[7].pin[2].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[7].pin[3].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[9].pin[0].analog[0]"/>
+                    </Arm>
+                </Mux>
+            </Netlist>
+        </Device>
+        <Device mpn="CYW4343WKUBG">
+            <BlockConfig>
+                <Block location="bt[0].power[0]">
+                    <Personality template="connectivity_bt" version="1.0">
+                        <Param id="hostWakePin" value=""/>
+                        <Param id="hostWakeIrqEvent" value="CYCFG_BT_WAKE_EVENT_ACTIVE_LOW"/>
+                        <Param id="devWakePin" value=""/>
+                        <Param id="devWakePolarity" value="CYCFG_BT_WAKE_EVENT_ACTIVE_LOW"/>
+                    </Personality>
+                </Block>
+            </BlockConfig>
+            <Netlist/>
+        </Device>
+    </Devices>
+    <ConfiguratorData/>
+</Design>

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct

@@ -0,0 +1,272 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx5_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               0x08000000
+#define RAM_SIZE                0x00002000
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00002000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE              0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+; Public RAM 
+; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+; This region is used to place objects that require full access from both cores.
+; Uncomment the following lines, define the region size and uncomment placement of
+; .cy_sharedmem section below.
+; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
+; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    .cy_app_header +0
+    {
+        * (.cy_app_header)
+    }
+
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
+    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
+    ;{
+    ;    * (.cy_sharedmem)
+    ;}
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    { 
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.s

@@ -0,0 +1,223 @@
+;/**************************************************************************//**
+; * @file     startup_psoc6_03_cm0plus.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM0plus Device Series
+; * @version  V5.00
+; * @date     02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+                IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base|
+                IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length|
+                
+__Vectors       DCD    |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack
+
+                DCD     Reset_Handler             ; Reset Handler
+
+                DCD     0x0000000D                ; NMI Handler located at ROM code
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External interrupts                           Description
+                DCD     NvicMux0_IRQHandler                   ; CPU User Interrupt #0 
+                DCD     NvicMux1_IRQHandler                   ; CPU User Interrupt #1 
+                DCD     NvicMux2_IRQHandler                   ; CPU User Interrupt #2 
+                DCD     NvicMux3_IRQHandler                   ; CPU User Interrupt #3 
+                DCD     NvicMux4_IRQHandler                   ; CPU User Interrupt #4 
+                DCD     NvicMux5_IRQHandler                   ; CPU User Interrupt #5 
+                DCD     NvicMux6_IRQHandler                   ; CPU User Interrupt #6 
+                DCD     NvicMux7_IRQHandler                   ; CPU User Interrupt #7 
+                DCD     Internal0_IRQHandler                  ; Internal SW Interrupt #0 
+                DCD     Internal1_IRQHandler                  ; Internal SW Interrupt #1 
+                DCD     Internal2_IRQHandler                  ; Internal SW Interrupt #2 
+                DCD     Internal3_IRQHandler                  ; Internal SW Interrupt #3 
+                DCD     Internal4_IRQHandler                  ; Internal SW Interrupt #4 
+                DCD     Internal5_IRQHandler                  ; Internal SW Interrupt #5 
+                DCD     Internal6_IRQHandler                  ; Internal SW Interrupt #6 
+                DCD     Internal7_IRQHandler                  ; Internal SW Interrupt #7 
+
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+                EXPORT __ramVectors
+                AREA    RESET_RAM, READWRITE, NOINIT
+__ramVectors    SPACE   __Vectors_Size
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Weak function for startup customization
+;
+; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
+; because this function is executed as the first instruction in the ResetHandler.
+; The PDL is also not initialized to use the proper register offsets.
+; The user of this function is responsible for initializing the PDL and resources before using them.
+;
+Cy_OnResetUser  PROC
+                EXPORT  Cy_OnResetUser            [WEAK]
+                BX      LR
+                ENDP
+
+; Reset Handler
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  __main
+
+                ; Define strong function for startup customization
+                BL      Cy_OnResetUser
+
+                ; Disable global interrupts
+                CPSID I
+
+                ; Copy vectors from ROM to RAM
+                LDR r1, =__Vectors
+                LDR r0, =__ramVectors
+                LDR r2, =__Vectors_Size
+Vectors_Copy
+                LDR r3, [r1]
+                STR r3, [r0]
+                ADDS r0, r0, #4
+                ADDS r1, r1, #4
+                SUBS r2, r2, #1
+                CMP r2, #0
+                BNE Vectors_Copy
+
+                ; Update Vector Table Offset Register. */
+                LDR r0, =__ramVectors
+                LDR r1, =0xE000ED08
+                STR r0, [r1]
+                dsb 0xF
+
+                LDR     R0, =__main
+                BLX     R0
+
+                ; Should never get here
+                B       .
+
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+NMI_Handler         PROC
+                    EXPORT  NMI_Handler               [WEAK]
+                    B       .
+                    ENDP
+
+Cy_SysLib_FaultHandler PROC
+                    EXPORT  Cy_SysLib_FaultHandler    [WEAK]
+                    B       .
+                    ENDP
+
+HardFault_Handler   PROC
+                    EXPORT HardFault_Handler          [WEAK]
+                    movs r0, #4
+                    mov r1, LR
+                    tst r0, r1
+                    beq L_MSP
+                    mrs r0, PSP
+                    bl L_API_call
+L_MSP
+                    mrs r0, MSP
+L_API_call
+                    bl Cy_SysLib_FaultHandler
+                    ENDP
+
+SVC_Handler         PROC
+                    EXPORT  SVC_Handler               [WEAK]
+                    B       .
+                    ENDP
+PendSV_Handler      PROC
+                    EXPORT  PendSV_Handler            [WEAK]
+                    B       .
+                    ENDP
+SysTick_Handler     PROC
+                    EXPORT  SysTick_Handler           [WEAK]
+                    B       .
+                    ENDP
+
+Default_Handler     PROC
+                    EXPORT  Default_Handler                       [WEAK]
+                    EXPORT  NvicMux0_IRQHandler                   [WEAK]
+                    EXPORT  NvicMux1_IRQHandler                   [WEAK]
+                    EXPORT  NvicMux2_IRQHandler                   [WEAK]
+                    EXPORT  NvicMux3_IRQHandler                   [WEAK]
+                    EXPORT  NvicMux4_IRQHandler                   [WEAK]
+                    EXPORT  NvicMux5_IRQHandler                   [WEAK]
+                    EXPORT  NvicMux6_IRQHandler                   [WEAK]
+                    EXPORT  NvicMux7_IRQHandler                   [WEAK]
+                    EXPORT  Internal0_IRQHandler                  [WEAK]
+                    EXPORT  Internal1_IRQHandler                  [WEAK]
+                    EXPORT  Internal2_IRQHandler                  [WEAK]
+                    EXPORT  Internal3_IRQHandler                  [WEAK]
+                    EXPORT  Internal4_IRQHandler                  [WEAK]
+                    EXPORT  Internal5_IRQHandler                  [WEAK]
+                    EXPORT  Internal6_IRQHandler                  [WEAK]
+                    EXPORT  Internal7_IRQHandler                  [WEAK]
+
+NvicMux0_IRQHandler
+NvicMux1_IRQHandler
+NvicMux2_IRQHandler
+NvicMux3_IRQHandler
+NvicMux4_IRQHandler
+NvicMux5_IRQHandler
+NvicMux6_IRQHandler
+NvicMux7_IRQHandler
+Internal0_IRQHandler
+Internal1_IRQHandler
+Internal2_IRQHandler
+Internal3_IRQHandler
+Internal4_IRQHandler
+Internal5_IRQHandler
+Internal6_IRQHandler
+Internal7_IRQHandler
+
+                B       .
+                ENDP
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+                IMPORT   __use_two_region_memory
+
+                END
+
+
+; [] END OF FILE

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_03_cm0plus.S

@@ -0,0 +1,253 @@
+/**************************************************************************//**
+ * @file     startup_psoc6_03_cm0plus.S
+ * @brief    CMSIS Core Device Startup File for
+ *           ARMCM0plus Device Series
+ * @version  V5.00
+ * @date     02. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+    /* Address of the NMI handler */
+    #define CY_NMI_HANLDER_ADDR         0x0000000D
+
+    /* The CPU VTOR register */
+    #define CY_CPU_VTOR_ADDR            0xE000ED08
+
+    .syntax    unified
+
+    .section __STACK, __stack
+    .align    3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0x00001000
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+
+__StackLimit:
+    .space    Stack_Size
+    .equ    __StackTop, . - Stack_Size
+
+    .section __HEAP, __heap
+    .align    3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x00000400
+#endif
+    .globl    __HeapBase
+__HeapBase:
+    .if    Heap_Size
+    .space    Heap_Size
+    .endif
+
+    .section __VECT, ___Vectors
+    .align 2
+    .globl    ___Vectors
+___Vectors:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    CY_NMI_HANLDER_ADDR   /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+     /* External interrupts                             Description */
+    .long    NvicMux0_IRQHandler                     /* CPU User Interrupt #0 */
+    .long    NvicMux1_IRQHandler                     /* CPU User Interrupt #1 */
+    .long    NvicMux2_IRQHandler                     /* CPU User Interrupt #2 */
+    .long    NvicMux3_IRQHandler                     /* CPU User Interrupt #3 */
+    .long    NvicMux4_IRQHandler                     /* CPU User Interrupt #4 */
+    .long    NvicMux5_IRQHandler                     /* CPU User Interrupt #5 */
+    .long    NvicMux6_IRQHandler                     /* CPU User Interrupt #6 */
+    .long    NvicMux7_IRQHandler                     /* CPU User Interrupt #7 */
+    .long    Internal0_IRQHandler                    /* Internal SW Interrupt #0 */
+    .long    Internal1_IRQHandler                    /* Internal SW Interrupt #1 */
+    .long    Internal2_IRQHandler                    /* Internal SW Interrupt #2 */
+    .long    Internal3_IRQHandler                    /* Internal SW Interrupt #3 */
+    .long    Internal4_IRQHandler                    /* Internal SW Interrupt #4 */
+    .long    Internal5_IRQHandler                    /* Internal SW Interrupt #5 */
+    .long    Internal6_IRQHandler                    /* Internal SW Interrupt #6 */
+    .long    Internal7_IRQHandler                    /* Internal SW Interrupt #7 */
+
+    .equ    __VectorsSize, . - ___Vectors
+
+    .section __RAMVECTORS, ___ramVectors
+    .align 2
+    .globl ___ramVectors
+
+___ramVectors:
+    .space  __VectorsSize
+
+
+    .text
+    .thumb_func
+    .align 2
+    /* Reset handler */
+    .globl Reset_Handler
+
+Reset_Handler:
+    bl Cy_OnResetUser
+    cpsid i
+
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr    r0, =___ramVectors
+    ldr    r1, =___Vectors
+    ldr    r2, =__VectorsSize
+    bl     _memcpy
+
+    ldr    r0, =segment$start$__DATA
+    ldr    r1, =segment$end$__TEXT
+    ldr    r2, =section$start$__DATA$__zerofill
+    sub    r2, r0
+    bl     _memcpy
+
+    ldr    r0, =section$start$__DATA$__zerofill
+    eor    r1, r1
+    ldr    r2, =section$end$__DATA$__zerofill
+    sub    r2, r0
+    bl     _memset
+
+    /* Update Vector Table Offset Register. */
+    ldr r0, =___ramVectors
+    ldr r1, =CY_CPU_VTOR_ADDR
+    str r0, [r1]
+    dsb 0xF
+
+    bl _HeapInit
+#ifndef __NO_SYSTEM_INIT
+    bl  _SystemInit
+#endif
+
+    bl  _main
+
+    /* Should never get here */
+    b   .
+
+    .pool
+
+    .text
+    .thumb
+    .thumb_func
+    .align 2
+
+    /* Device startup customization */
+    .weak_definition   Cy_OnResetUser
+    .global Cy_OnResetUser, Cy_OnResetUser
+Cy_OnResetUser:
+    bx lr
+
+    .text
+    .align    1
+    .thumb_func
+    .weak_reference    Default_Handler
+
+Default_Handler:
+    b    .
+
+    .text
+    .thumb_func
+    .align  2
+    .weak_definition    Cy_SysLib_FaultHandler
+
+Cy_SysLib_FaultHandler:
+    b    .
+
+    .text
+    .thumb_func
+    .align  2
+
+Fault_Handler:
+    /* Storing LR content for Creator call stack trace */
+    push {LR}
+    movs r0, #4
+    mov r1, LR
+    tst r0, r1
+    beq .L_MSP
+    mrs r0, PSP
+    b .L_API_call
+.L_MSP:
+    mrs r0, MSP
+.L_API_call:
+    /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+    adds r0, r0, #4
+    bl Cy_SysLib_FaultHandler
+    b   .
+
+.macro    def_fault_Handler    fault_handler_name
+    .weak_definition    \fault_handler_name
+    .set    \fault_handler_name, Fault_Handler
+    .endm
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_irq_handler    handler_name
+    .weak_definition    \handler_name
+    .set    \handler_name, Default_Handler
+    .endm
+
+    def_irq_handler    NMI_Handler
+
+    def_fault_Handler  HardFault_Handler
+
+    def_irq_handler    SVC_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+
+    def_irq_handler  NvicMux0_IRQHandler                     /* CPU User Interrupt #0 */
+    def_irq_handler  NvicMux1_IRQHandler                     /* CPU User Interrupt #1 */
+    def_irq_handler  NvicMux2_IRQHandler                     /* CPU User Interrupt #2 */
+    def_irq_handler  NvicMux3_IRQHandler                     /* CPU User Interrupt #3 */
+    def_irq_handler  NvicMux4_IRQHandler                     /* CPU User Interrupt #4 */
+    def_irq_handler  NvicMux5_IRQHandler                     /* CPU User Interrupt #5 */
+    def_irq_handler  NvicMux6_IRQHandler                     /* CPU User Interrupt #6 */
+    def_irq_handler  NvicMux7_IRQHandler                     /* CPU User Interrupt #7 */
+    def_irq_handler  Internal0_IRQHandler                    /* Internal SW Interrupt #0 */
+    def_irq_handler  Internal1_IRQHandler                    /* Internal SW Interrupt #1 */
+    def_irq_handler  Internal2_IRQHandler                    /* Internal SW Interrupt #2 */
+    def_irq_handler  Internal3_IRQHandler                    /* Internal SW Interrupt #3 */
+    def_irq_handler  Internal4_IRQHandler                    /* Internal SW Interrupt #4 */
+    def_irq_handler  Internal5_IRQHandler                    /* Internal SW Interrupt #5 */
+    def_irq_handler  Internal6_IRQHandler                    /* Internal SW Interrupt #6 */
+    def_irq_handler  Internal7_IRQHandler                    /* Internal SW Interrupt #7 */
+
+    .end
+
+
+/* [] END OF FILE */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld

@@ -0,0 +1,441 @@
+/***************************************************************************//**
+* \file cy8c6xx5_cm0plus.ld
+* \version 2.91
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+/* The size of the stack section at the end of CM0+ SRAM */
+STACK_SIZE = 0x1000;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+    /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
+     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+     * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+     * Using this memory region for other purposes will lead to unexpected behavior.
+     * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
+     * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
+     */
+    ram               (rwx)   : ORIGIN = 0x08000000, LENGTH = 0x2000
+    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x2000
+
+
+    /* This is an unprotected public RAM region, with the placed .cy_sharedmem.
+     * This region is used to place objects that require full access from both cores.
+     * Uncomment the following line, define the region origin and length, and uncomment the placement of
+     * the .cy_sharedmem section below.
+     */
+    /* public_ram        (rw)    : ORIGIN = %REGION_START_ADDRESS%, LENGTH = %REGION_SIZE% */
+
+    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+     * You can assign sections to this memory region for only one of the cores.
+     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+     * Therefore, repurposing this memory region will prevent such middleware from operation.
+     */
+    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */
+
+    /* The following regions define device specific memory regions and must not be changed. */
+    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
+    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
+    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
+    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
+    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
+    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
+    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+
+
+SECTIONS
+{
+    .cy_app_header :
+    {
+        KEEP(*(.cy_app_header))
+    } > flash
+
+    /* Cortex-M0+ application flash area */
+    .text :
+    {
+        . = ALIGN(4);
+        __Vectors = . ;
+        KEEP(*(.vectors))
+        . = ALIGN(4);
+        __Vectors_End = .;
+        __Vectors_Size = __Vectors_End - __Vectors;
+        __end__ = .;
+
+        . = ALIGN(4);
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        /* Read-only code (constants). */
+        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+        KEEP(*(.eh_frame*))
+    } > flash
+
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > flash
+
+    __exidx_start = .;
+
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > flash
+    __exidx_end = .;
+
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_03_cm0plus.S */
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+
+        /* Copy interrupt vectors from flash to RAM */
+        LONG (__Vectors)                                    /* From */
+        LONG (__ram_vectors_start__)                        /* To   */
+        LONG (__Vectors_End - __Vectors)                    /* Size */
+
+        /* Copy data section to RAM */
+        LONG (__etext)                                      /* From */
+        LONG (__data_start__)                               /* To   */
+        LONG (__data_end__ - __data_start__)                /* Size */
+
+        __copy_table_end__ = .;
+    } > flash
+
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_03_cm0plus.S */
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        __zero_table_end__ = .;
+    } > flash
+
+    __etext =  . ;
+
+
+    .ramVectors (NOLOAD) : ALIGN(8)
+    {
+        __ram_vectors_start__ = .;
+        KEEP(*(.ram_vectors))
+        __ram_vectors_end__   = .;
+    } > ram
+
+
+    .data __ram_vectors_end__ :
+    {
+        . = ALIGN(4);
+        __data_start__ = .;
+
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+
+        KEEP(*(.cy_ramfunc*))
+        . = ALIGN(4);
+
+        __data_end__ = .;
+
+    } > ram AT>flash
+
+
+    /* Place variables in the section that should not be initialized during the
+    *  device startup.
+    */
+    .noinit (NOLOAD) : ALIGN(8)
+    {
+      KEEP(*(.noinit))
+    } > ram
+
+
+    /* The uninitialized global or static variables are placed in this section.
+    *
+    * The NOLOAD attribute tells linker that .bss section does not consume
+    * any space in the image. The NOLOAD attribute changes the .bss type to
+    * NOBITS, and that  makes linker to A) not allocate section in memory, and
+    * A) put information to clear the section with all zeros during application
+    * loading.
+    *
+    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+    * This  makes linker to A) allocate zeroed section in memory, and B) copy
+    * this section to RAM during application loading.
+    */
+    .bss (NOLOAD):
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > ram
+
+
+    .heap (NOLOAD):
+    {
+        __HeapBase = .;
+        __end__ = .;
+        end = __end__;
+        KEEP(*(.heap*))
+        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+        __HeapLimit = .;
+    } > ram
+
+
+    /* To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.*/
+    /*
+    .cy_sharedmem (NOLOAD):
+    {
+        . = ALIGN(4);
+        __public_ram_start__ = .;
+        KEEP(*(.cy_sharedmem))
+        . = ALIGN(4);
+        __public_ram_end__ = .;
+    } > public_ram
+    */
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (NOLOAD):
+    {
+        KEEP(*(.stack*))
+    } > ram
+
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(ram) + LENGTH(ram);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+    /* Emulated EEPROM Flash area */
+    .cy_em_eeprom :
+    {
+        KEEP(*(.cy_em_eeprom))
+    } > em_eeprom
+
+
+    /* Supervisory Flash: User data */
+    .cy_sflash_user_data :
+    {
+        KEEP(*(.cy_sflash_user_data))
+    } > sflash_user_data
+
+
+    /* Supervisory Flash: Normal Access Restrictions (NAR) */
+    .cy_sflash_nar :
+    {
+        KEEP(*(.cy_sflash_nar))
+    } > sflash_nar
+
+
+    /* Supervisory Flash: Public Key */
+    .cy_sflash_public_key :
+    {
+        KEEP(*(.cy_sflash_public_key))
+    } > sflash_public_key
+
+
+    /* Supervisory Flash: Table of Content # 2 */
+    .cy_toc_part2 :
+    {
+        KEEP(*(.cy_toc_part2))
+    } > sflash_toc_2
+
+
+    /* Supervisory Flash: Table of Content # 2 Copy */
+    .cy_rtoc_part2 :
+    {
+        KEEP(*(.cy_rtoc_part2))
+    } > sflash_rtoc_2
+
+
+    /* Places the code in the Execute in Place (XIP) section. See the smif driver
+    *  documentation for details.
+    */
+    cy_xip :
+    {
+        __cy_xip_start = .;
+        KEEP(*(.cy_xip))
+        __cy_xip_end = .;
+    } > xip
+
+
+    /* eFuse */
+    .cy_efuse :
+    {
+        KEEP(*(.cy_efuse))
+    } > efuse
+
+
+    /* These sections are used for additional metadata (silicon revision,
+    *  Silicon/JTAG ID, etc.) storage.
+    */
+    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start    = 0x10000000;
+__cy_memory_0_length   = 0x00080000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start    = 0x14000000;
+__cy_memory_1_length   = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start    = 0x16000000;
+__cy_memory_2_length   = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start    = 0x18000000;
+__cy_memory_3_length   = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start    = 0x90700000;
+__cy_memory_4_length   = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S

@@ -0,0 +1,372 @@
+/**************************************************************************//**
+ * @file     startup_psoc6_03_cm0plus.S
+ * @brief    CMSIS Core Device Startup File for
+ *           ARMCM0plus Device Series
+ * @version  V5.00
+ * @date     02. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+    /* Address of the NMI handler */
+    #define CY_NMI_HANLDER_ADDR         0x0000000D
+
+    /* The CPU VTOR register */
+    #define CY_CPU_VTOR_ADDR            0xE000ED08
+
+    /* Copy flash vectors and data section to RAM */
+    #define __STARTUP_COPY_MULTIPLE
+
+    /* Clear single BSS section */
+    #define __STARTUP_CLEAR_BSS
+
+    .syntax    unified
+    .arch    armv6-m
+
+    .section .stack
+    .align    3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0x00001000
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size    __StackLimit, . - __StackLimit
+__StackTop:
+    .size    __StackTop, . - __StackTop
+
+    .section .heap
+    .align    3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x00000400
+#endif
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .if    Heap_Size
+    .space    Heap_Size
+    .endif
+    .size    __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size    __HeapLimit, . - __HeapLimit
+
+    .section .vectors
+    .align 2
+    .globl    __Vectors
+__Vectors:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    CY_NMI_HANLDER_ADDR   /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+     /* External interrupts                             Description */
+    .long    NvicMux0_IRQHandler                     /* CPU User Interrupt #0 */
+    .long    NvicMux1_IRQHandler                     /* CPU User Interrupt #1 */
+    .long    NvicMux2_IRQHandler                     /* CPU User Interrupt #2 */
+    .long    NvicMux3_IRQHandler                     /* CPU User Interrupt #3 */
+    .long    NvicMux4_IRQHandler                     /* CPU User Interrupt #4 */
+    .long    NvicMux5_IRQHandler                     /* CPU User Interrupt #5 */
+    .long    NvicMux6_IRQHandler                     /* CPU User Interrupt #6 */
+    .long    NvicMux7_IRQHandler                     /* CPU User Interrupt #7 */
+    .long    Internal0_IRQHandler                    /* Internal SW Interrupt #0 */
+    .long    Internal1_IRQHandler                    /* Internal SW Interrupt #1 */
+    .long    Internal2_IRQHandler                    /* Internal SW Interrupt #2 */
+    .long    Internal3_IRQHandler                    /* Internal SW Interrupt #3 */
+    .long    Internal4_IRQHandler                    /* Internal SW Interrupt #4 */
+    .long    Internal5_IRQHandler                    /* Internal SW Interrupt #5 */
+    .long    Internal6_IRQHandler                    /* Internal SW Interrupt #6 */
+    .long    Internal7_IRQHandler                    /* Internal SW Interrupt #7 */
+
+    .size    __Vectors, . - __Vectors
+    .equ    __VectorsSize, . - __Vectors
+
+    .section .ram_vectors
+    .align 2
+    .globl __ramVectors
+__ramVectors:
+    .space  __VectorsSize
+    .size   __ramVectors, . - __ramVectors
+
+
+    .text
+    .thumb
+    .thumb_func
+    .align  2
+
+    /* 
+     * Device startup customization 
+     *
+     * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 
+     * because this function is executed as the first instruction in the ResetHandler.
+     * The PDL is also not initialized to use the proper register offsets.
+     * The user of this function is responsible for initializing the PDL and resources before using them.
+     */
+    .weak   Cy_OnResetUser
+    .func   Cy_OnResetUser, Cy_OnResetUser
+    .type   Cy_OnResetUser, %function
+
+Cy_OnResetUser:
+    bx lr
+    .size   Cy_OnResetUser, . - Cy_OnResetUser
+    .endfunc
+
+    /* Reset handler */
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+
+Reset_Handler:
+    bl Cy_OnResetUser
+    cpsid i
+
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr    r4, =__copy_table_start__
+    ldr    r5, =__copy_table_end__
+
+.L_loop0:
+    cmp    r4, r5
+    bge    .L_loop0_done
+    ldr    r1, [r4]
+    ldr    r2, [r4, #4]
+    ldr    r3, [r4, #8]
+
+.L_loop0_0:
+    subs    r3, #4
+    blt    .L_loop0_0_done
+    ldr    r0, [r1, r3]
+    str    r0, [r2, r3]
+    b    .L_loop0_0
+
+.L_loop0_0_done:
+    adds    r4, #12
+    b    .L_loop0
+
+.L_loop0_done:
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+    subs    r3, r2
+    ble    .L_loop1_done
+
+.L_loop1:
+    subs    r3, #4
+    ldr    r0, [r1,r3]
+    str    r0, [r2,r3]
+    bgt    .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+    ldr    r3, =__zero_table_start__
+    ldr    r4, =__zero_table_end__
+
+.L_loop2:
+    cmp    r3, r4
+    bge    .L_loop2_done
+    ldr    r1, [r3]
+    ldr    r2, [r3, #4]
+    movs    r0, 0
+
+.L_loop2_0:
+    subs    r2, #4
+    blt    .L_loop2_0_done
+    str    r0, [r1, r2]
+    b    .L_loop2_0
+.L_loop2_0_done:
+
+    adds    r3, #8
+    b    .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+    ldr    r1, =__bss_start__
+    ldr    r2, =__bss_end__
+
+    movs    r0, 0
+
+    subs    r2, r1
+    ble    .L_loop3_done
+
+.L_loop3:
+    subs    r2, #4
+    str    r0, [r1, r2]
+    bgt    .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+    /* Update Vector Table Offset Register. */
+    ldr r0, =__ramVectors
+    ldr r1, =CY_CPU_VTOR_ADDR
+    str r0, [r1]
+    dsb 0xF
+
+#ifndef __NO_SYSTEM_INIT
+    bl    SystemInit
+#endif
+
+    bl    main
+
+    /* Should never get here */
+    b   .
+
+    .pool
+    .size    Reset_Handler, . - Reset_Handler
+
+    .align    1
+    .thumb_func
+    .weak    Default_Handler
+    .type    Default_Handler, %function
+Default_Handler:
+    b    .
+    .size    Default_Handler, . - Default_Handler
+    .weak    Cy_SysLib_FaultHandler
+    .type    Cy_SysLib_FaultHandler, %function
+
+Cy_SysLib_FaultHandler:
+    b    .
+    .size    Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+    .type Fault_Handler, %function
+
+Fault_Handler:
+    /* Storing LR content for Creator call stack trace */
+    push {LR}
+    movs r0, #4
+    mov r1, LR
+    tst r0, r1
+    beq .L_MSP
+    mrs r0, PSP
+    b .L_API_call
+.L_MSP:
+    mrs r0, MSP
+.L_API_call:
+    /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+    adds r0, r0, #4
+    bl Cy_SysLib_FaultHandler
+    b   .
+    .size    Fault_Handler, . - Fault_Handler
+
+.macro    def_fault_Handler    fault_handler_name
+    .weak    \fault_handler_name
+    .set    \fault_handler_name, Fault_Handler
+    .endm
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_irq_handler    handler_name
+    .weak    \handler_name
+    .set    \handler_name, Default_Handler
+    .endm
+
+    def_irq_handler    NMI_Handler
+
+    def_fault_Handler  HardFault_Handler
+
+    def_irq_handler    SVC_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+
+    def_irq_handler  NvicMux0_IRQHandler                     /* CPU User Interrupt #0 */
+    def_irq_handler  NvicMux1_IRQHandler                     /* CPU User Interrupt #1 */
+    def_irq_handler  NvicMux2_IRQHandler                     /* CPU User Interrupt #2 */
+    def_irq_handler  NvicMux3_IRQHandler                     /* CPU User Interrupt #3 */
+    def_irq_handler  NvicMux4_IRQHandler                     /* CPU User Interrupt #4 */
+    def_irq_handler  NvicMux5_IRQHandler                     /* CPU User Interrupt #5 */
+    def_irq_handler  NvicMux6_IRQHandler                     /* CPU User Interrupt #6 */
+    def_irq_handler  NvicMux7_IRQHandler                     /* CPU User Interrupt #7 */
+    def_irq_handler  Internal0_IRQHandler                    /* Internal SW Interrupt #0 */
+    def_irq_handler  Internal1_IRQHandler                    /* Internal SW Interrupt #1 */
+    def_irq_handler  Internal2_IRQHandler                    /* Internal SW Interrupt #2 */
+    def_irq_handler  Internal3_IRQHandler                    /* Internal SW Interrupt #3 */
+    def_irq_handler  Internal4_IRQHandler                    /* Internal SW Interrupt #4 */
+    def_irq_handler  Internal5_IRQHandler                    /* Internal SW Interrupt #5 */
+    def_irq_handler  Internal6_IRQHandler                    /* Internal SW Interrupt #6 */
+    def_irq_handler  Internal7_IRQHandler                    /* Internal SW Interrupt #7 */
+
+    .end
+
+
+/* [] END OF FILE */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf

@@ -0,0 +1,253 @@
+/*******************************************************************************
+* \file cy8c6xx5_cm0plus.icf
+* \version 2.91
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+  define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+    define symbol __ICFEDIT_size_heap__ = 0x0400;
+} else {
+  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM0+ core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x08001FFF;
+
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x10001FFF;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+/* Public RAM 
+ * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+ * This region is used to place objects that require full access from both cores.
+ * Uncomment the following lines, define region size, and uncomment the placement of
+ * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__
+ *  and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region.
+ */
+/*
+define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+*/
+
+define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block RO     {first section .intvec, readonly};
+
+define block cy_xip { section .cy_xip };
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize  { section .noinit, section .intvec_ram };
+
+/*-Placement-*/
+
+/* Flash - Cortex-M0+ application */
+".cy_app_header" : place at start of IROM1_region  { section .cy_app_header };
+place in          IROM1_region  { block RO };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+"cy_xip" : place at start of EROM1_region  { block cy_xip };
+
+/* RAM */
+place at start of IRAM1_region  { readwrite section .intvec_ram};
+place in          IRAM1_region  { readwrite };
+place at end   of IRAM1_region  { block HSTACK };
+
+/* Public RAM 
+ *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
+ */
+/*
+place at start of IRAM2_region  { section .cy_sharedmem };
+*/
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep {  section .cy_app_header,
+        section .cy_em_eeprom,
+        section .cy_sflash_user_data,
+        section .cy_sflash_nar,
+        section .cy_sflash_public_key,
+        section .cy_toc_part2,
+        section .cy_rtoc_part2,
+        section .cy_efuse,
+        section .cy_xip,
+        section .cymeta,
+         };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start    = 0x10000000;
+define exported symbol __cy_memory_0_length   = 0x00080000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start    = 0x14000000;
+define exported symbol __cy_memory_1_length   = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start    = 0x16000000;
+define exported symbol __cy_memory_2_length   = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start    = 0x18000000;
+define exported symbol __cy_memory_3_length   = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start    = 0x90700000;
+define exported symbol __cy_memory_4_length   = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.s

@@ -0,0 +1,331 @@
+;/**************************************************************************//**
+; * @file     startup_psoc6_03_cm0plus.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM0plus Device Series
+; * @version  V5.00
+; * @date     08. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+        SECTION .intvec_ram:DATA:NOROOT(2)
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        EXTERN __iar_data_init3
+        EXTERN __iar_dynamic_initialization        
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+        PUBLIC  __ramVectors
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     0x0000000D      ; NMI_Handler is defined in ROM code
+        DCD     HardFault_Handler
+        DCD     0
+        DCD     0
+        DCD     0
+__vector_table_0x1c
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     0
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External interrupts                           Description
+        DCD     NvicMux0_IRQHandler                   ; CPU User Interrupt #0
+        DCD     NvicMux1_IRQHandler                   ; CPU User Interrupt #1
+        DCD     NvicMux2_IRQHandler                   ; CPU User Interrupt #2
+        DCD     NvicMux3_IRQHandler                   ; CPU User Interrupt #3
+        DCD     NvicMux4_IRQHandler                   ; CPU User Interrupt #4
+        DCD     NvicMux5_IRQHandler                   ; CPU User Interrupt #5
+        DCD     NvicMux6_IRQHandler                   ; CPU User Interrupt #6
+        DCD     NvicMux7_IRQHandler                   ; CPU User Interrupt #7
+        DCD     Internal0_IRQHandler                  ; Internal SW Interrupt #0
+        DCD     Internal1_IRQHandler                  ; Internal SW Interrupt #1
+        DCD     Internal2_IRQHandler                  ; Internal SW Interrupt #2
+        DCD     Internal3_IRQHandler                  ; Internal SW Interrupt #3
+        DCD     Internal4_IRQHandler                  ; Internal SW Interrupt #4
+        DCD     Internal5_IRQHandler                  ; Internal SW Interrupt #5
+        DCD     Internal6_IRQHandler                  ; Internal SW Interrupt #6
+        DCD     Internal7_IRQHandler                  ; Internal SW Interrupt #7
+
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+        SECTION .intvec_ram:DATA:REORDER:NOROOT(2)
+__ramVectors
+        DS32     __Vectors_Size
+
+
+        THUMB
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default handlers
+;;
+        PUBWEAK Default_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Default_Handler
+        B Default_Handler
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Weak function for startup customization
+;;
+;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 
+;; because this function is executed as the first instruction in the ResetHandler.
+;; The PDL is also not initialized to use the proper register offsets.
+;; The user of this function is responsible for initializing the PDL and resources before using them.
+;;
+        PUBWEAK Cy_OnResetUser
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Cy_OnResetUser
+        BX LR
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Define strong version to return zero for
+;; __iar_program_start to skip data sections
+;; initialization.
+;;
+        PUBLIC __low_level_init
+        SECTION .text:CODE:REORDER:NOROOT(2)
+__low_level_init
+        MOVS R0, #0
+        BX LR
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+
+        ; Define strong function for startup customization
+        LDR     R0, =Cy_OnResetUser
+        BLX     R0
+
+        ; Disable global interrupts
+        CPSID I
+
+        ; Copy vectors from ROM to RAM
+        LDR r1, =__vector_table
+        LDR r0, =__ramVectors
+        LDR r2, =__Vectors_Size
+intvec_copy
+        LDR r3, [r1]
+        STR r3, [r0]
+        ADDS r0, r0, #4
+        ADDS r1, r1, #4
+        SUBS r2, r2, #1
+        CMP r2, #0
+        BNE intvec_copy
+
+        ; Update Vector Table Offset Register
+        LDR r0, =__ramVectors
+        LDR r1, =0xE000ED08
+        STR r0, [r1]
+        dsb
+
+        ; Initialize data sections
+        LDR     R0, =__iar_data_init3
+        BLX     R0
+
+        ; --manual_dynamic_initialization
+        BL      __iar_dynamic_initialization
+
+        LDR     R0, =SystemInit
+        BLX     R0
+
+        LDR     R0, =__iar_program_start
+        BLX     R0
+
+; Should never get here
+Cy_Main_Exited
+        B Cy_Main_Exited
+
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B NMI_Handler
+
+
+        PUBWEAK Cy_SysLib_FaultHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Cy_SysLib_FaultHandler
+        B Cy_SysLib_FaultHandler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        IMPORT Cy_SysLib_FaultHandler
+        movs r0, #4
+        mov r1, LR
+        tst r0, r1
+        beq L_MSP
+        mrs r0, PSP
+        b L_API_call
+L_MSP
+        mrs r0, MSP
+L_API_call
+        ; Storing LR content for Creator call stack trace
+        push {LR}
+        bl Cy_SysLib_FaultHandler
+
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B SysTick_Handler
+
+
+        ; External interrupts
+        PUBWEAK NvicMux0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux0_IRQHandler
+        B       NvicMux0_IRQHandler
+
+        PUBWEAK NvicMux1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux1_IRQHandler
+        B       NvicMux1_IRQHandler
+
+        PUBWEAK NvicMux2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux2_IRQHandler
+        B       NvicMux2_IRQHandler
+
+        PUBWEAK NvicMux3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux3_IRQHandler
+        B       NvicMux3_IRQHandler
+
+        PUBWEAK NvicMux4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux4_IRQHandler
+        B       NvicMux4_IRQHandler
+
+        PUBWEAK NvicMux5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux5_IRQHandler
+        B       NvicMux5_IRQHandler
+
+        PUBWEAK NvicMux6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux6_IRQHandler
+        B       NvicMux6_IRQHandler
+
+        PUBWEAK NvicMux7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux7_IRQHandler
+        B       NvicMux7_IRQHandler
+
+        PUBWEAK Internal0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Internal0_IRQHandler
+        B       Internal0_IRQHandler
+
+        PUBWEAK Internal1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Internal1_IRQHandler
+        B       Internal1_IRQHandler
+
+        PUBWEAK Internal2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Internal2_IRQHandler
+        B       Internal2_IRQHandler
+
+        PUBWEAK Internal3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Internal3_IRQHandler
+        B       Internal3_IRQHandler
+
+        PUBWEAK Internal4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Internal4_IRQHandler
+        B       Internal4_IRQHandler
+
+        PUBWEAK Internal5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Internal5_IRQHandler
+        B       Internal5_IRQHandler
+
+        PUBWEAK Internal6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Internal6_IRQHandler
+        B       Internal6_IRQHandler
+
+        PUBWEAK Internal7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Internal7_IRQHandler
+        B       Internal7_IRQHandler
+
+
+        END
+
+
+; [] END OF FILE

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM0P/system_psoc6_cm0plus.c

@@ -0,0 +1,536 @@
+/***************************************************************************//**
+* \file system_psoc6_cm0plus.c
+* \version 2.91
+*
+* The device system-source file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdbool.h>
+#include "system_psoc6.h"
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+#include "cy_sysclk.h"
+#include "cy_wdt.h"
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+    #include "cy_ipc_sema.h"
+    #include "cy_ipc_pipe.h"
+    #include "cy_ipc_drv.h"
+
+    #if defined(CY_DEVICE_PSOC6ABLE2)
+        #include "cy_flash.h"
+    #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate()
+*******************************************************************************/
+
+/** Default HFClk frequency in Hz */
+#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT       (8000000UL)
+
+/** Default PeriClk frequency in Hz */
+#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT      (4000000UL)
+
+/** Default SlowClk system core frequency in Hz */
+#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT       (4000000UL)
+
+
+/**
+* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
+* which is the system clock frequency supplied to the SysTick timer and the
+* processor core clock.
+* This variable implements CMSIS Core global variable.
+* Refer to the [CMSIS documentation]
+* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
+* for more details.
+* This variable can be used by debuggers to query the frequency
+* of the debug timer or to configure the trace clock speed.
+*
+* \attention Compilers must be configured to avoid removing this variable in case
+* the application program is not using it. Debugging systems require the variable
+* to be physically present in memory so that it can be examined to configure the debugger. */
+uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_Hfclk0FreqHz  = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
+
+/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
+
+/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
+uint32_t cy_BleEcoClockFreqHz = 0UL;
+
+
+/*******************************************************************************
+* SystemInit()
+*******************************************************************************/
+
+/* CLK_FLL_CONFIG default values */
+#define CY_FB_CLK_FLL_CONFIG_VALUE      (0x01000000u)
+#define CY_FB_CLK_FLL_CONFIG2_VALUE     (0x00020001u)
+#define CY_FB_CLK_FLL_CONFIG3_VALUE     (0x00002800u)
+#define CY_FB_CLK_FLL_CONFIG4_VALUE     (0x000000FFu)
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate (void)
+*******************************************************************************/
+
+/* Do not use these definitions directly in your application */
+#define CY_DELAY_MS_OVERFLOW_THRESHOLD  (0x8000u)
+#define CY_DELAY_1K_THRESHOLD           (1000u)
+#define CY_DELAY_1M_THRESHOLD           (1000000u)
+
+uint32_t cy_delayFreqKhz  = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
+
+uint8_t cy_delayFreqMhz  = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
+
+uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
+                            CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
+
+
+/*******************************************************************************
+* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4()
+*******************************************************************************/
+#define CY_SYS_CM4_PWR_CTL_KEY_OPEN  (0x05FAUL)
+#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
+#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR  (0x000003FFUL)
+
+
+/*******************************************************************************
+* Function Name: SystemInit
+****************************************************************************//**
+*
+* Initializes the system:
+* - Restores FLL registers to the default state.
+* - Unlocks and disables WDT.
+* - Calls Cy_PDL_Init() function to define the driver library.
+* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref Cy_PRA_Init() for PSoC 64 devices.
+* - Calls \ref SystemCoreClockUpdate().
+*
+*******************************************************************************/
+void SystemInit(void)
+{
+    Cy_PDL_Init(CY_DEVICE_CFG);
+
+    /* Restore FLL registers to the default state as they are not restored by the ROM code */
+    uint32_t copy = SRSS->CLK_FLL_CONFIG;
+    copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
+    SRSS->CLK_FLL_CONFIG = copy;
+
+    copy = SRSS->CLK_ROOT_SELECT[0u];
+    copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
+    SRSS->CLK_ROOT_SELECT[0u] = copy;
+
+    SRSS->CLK_FLL_CONFIG  = CY_FB_CLK_FLL_CONFIG_VALUE;
+    SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
+    SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
+    SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
+
+    /* Unlock and disable WDT */
+    Cy_WDT_Unlock();
+    Cy_WDT_Disable();
+
+    Cy_SystemInit();
+    SystemCoreClockUpdate();
+
+    /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
+    REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
+
+    /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
+    REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+    /* Allocate and initialize semaphores for the system operations. */
+    CY_SECTION_SHAREDMEM
+    static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
+
+    (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
+
+
+    /********************************************************************************
+    *
+    * Initializes the system pipes. The system pipes are used by BLE and Flash.
+    *
+    * If the default startup file is not used, or SystemInit() is not called in your
+    * project, call the following three functions prior to executing any flash or
+    * EmEEPROM write or erase operation:
+    *  -# Cy_IPC_Sema_Init()
+    *  -# Cy_IPC_Pipe_Config()
+    *  -# Cy_IPC_Pipe_Init()
+    *  -# Cy_Flash_Init()
+    *
+    *******************************************************************************/
+
+    /* Create an array of endpoint structures */
+    static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
+
+    Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
+
+    static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
+
+    static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 =
+    {
+    /* .ep0ConfigData */
+        {
+            /* .ipcNotifierNumber    */  CY_IPC_INTR_CYPIPE_EP0,
+            /* .ipcNotifierPriority  */  CY_SYS_INTR_CYPIPE_PRIOR_EP0,
+            /* .ipcNotifierMuxNumber */  CY_SYS_INTR_CYPIPE_MUX_EP0,
+            /* .epAddress            */  CY_IPC_EP_CYPIPE_CM0_ADDR,
+            /* .epConfig             */  CY_SYS_CYPIPE_CONFIG_EP0
+        },
+    /* .ep1ConfigData */
+        {
+            /* .ipcNotifierNumber    */  CY_IPC_INTR_CYPIPE_EP1,
+            /* .ipcNotifierPriority  */  CY_SYS_INTR_CYPIPE_PRIOR_EP1,
+            /* .ipcNotifierMuxNumber */  0u,
+            /* .epAddress            */  CY_IPC_EP_CYPIPE_CM4_ADDR,
+            /* .epConfig             */  CY_SYS_CYPIPE_CONFIG_EP1
+        },
+    /* .endpointClientsCount     */  CY_SYS_CYPIPE_CLIENT_CNT,
+    /* .endpointsCallbacksArray  */  systemIpcPipeSysCbArray,
+    /* .userPipeIsrHandler       */  &Cy_SysIpcPipeIsrCm0
+    };
+
+    Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
+
+#if defined(CY_DEVICE_PSOC6ABLE2)
+    Cy_Flash_Init();
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+
+#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+    #if defined(CY_DEVICE_SECURE)
+        /* Initialize Protected Regsiter Access driver. */
+        Cy_PRA_Init();
+    #endif /* defined(CY_DEVICE_SECURE) */
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SystemInit
+****************************************************************************//**
+*
+* The function is called during device startup. Once project compiled as part of
+* the PSoC Creator project, the Cy_SystemInit() function is generated by the
+* PSoC Creator.
+*
+* The function generated by PSoC Creator performs all of the necessary device
+* configuration based on the design settings.  This includes settings from the
+* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
+* configuration that is necessary.
+*
+*******************************************************************************/
+__WEAK void Cy_SystemInit(void)
+{
+     /* Empty weak function. The actual implementation to be in the PSoC Creator
+      * generated strong function.
+     */
+}
+
+
+/*******************************************************************************
+* Function Name: SystemCoreClockUpdate
+****************************************************************************//**
+*
+* Gets core clock frequency and updates \ref SystemCoreClock.
+*
+* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
+* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
+*
+*******************************************************************************/
+void SystemCoreClockUpdate (void)
+{
+    uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
+
+    if (0UL != locHf0Clock)
+    {
+        cy_Hfclk0FreqHz = locHf0Clock;
+        cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
+        SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider());
+
+        /* Sets clock frequency for Delay API */
+        cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
+        cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
+        cy_delay32kMs   = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
+    }
+}
+
+
+#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
+/*******************************************************************************
+* Function Name: Cy_SysGetCM4Status
+****************************************************************************//**
+*
+* Returns the Cortex-M4 core power mode.
+*
+* \return \ref group_system_config_cm4_status_macro
+*
+*******************************************************************************/
+uint32_t Cy_SysGetCM4Status(void)
+{
+    uint32_t regValue;
+
+    /* Get current power mode */
+    regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk;
+
+    return (regValue);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysEnableCM4
+****************************************************************************//**
+*
+* Sets vector table base address and enables the Cortex-M4 core.
+*
+* \note If the CPU is already enabled, it is reset and then enabled.
+*
+* \param vectorTableOffset The offset of the vector table base address from
+* memory address 0x00000000. The offset should be multiple to 1024 bytes.
+*
+*******************************************************************************/
+void Cy_SysEnableCM4(uint32_t vectorTableOffset)
+{
+    uint32_t regValue;
+    uint32_t interruptState;
+    uint32_t cpuState;
+
+    CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL);
+
+    interruptState = Cy_SysLib_EnterCriticalSection();
+
+    cpuState = Cy_SysGetCM4Status();
+    if (CY_SYS_CM4_STATUS_ENABLED == cpuState)
+    {
+        Cy_SysResetCM4();
+    }
+
+    CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset;
+
+    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+    regValue |= CY_SYS_CM4_STATUS_ENABLED;
+    CPUSS->CM4_PWR_CTL = regValue;
+
+    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+    {
+        /* Wait for the power mode to take effect */
+    }
+
+    Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysDisableCM4
+****************************************************************************//**
+*
+* Disables the Cortex-M4 core and waits for the mode to take the effect.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the
+* CPU.
+*
+*******************************************************************************/
+void Cy_SysDisableCM4(void)
+{
+    uint32_t interruptState;
+    uint32_t regValue;
+
+    interruptState = Cy_SysLib_EnterCriticalSection();
+
+    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+    regValue |= CY_SYS_CM4_STATUS_DISABLED;
+    CPUSS->CM4_PWR_CTL = regValue;
+
+    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+    {
+        /* Wait for the power mode to take effect */
+    }
+
+    Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysRetainCM4
+****************************************************************************//**
+*
+* Retains the Cortex-M4 core and exists without waiting for the mode to take
+* effect.
+*
+* \note The retained mode can be entered only from the enabled mode.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+void Cy_SysRetainCM4(void)
+{
+    uint32_t interruptState;
+    uint32_t regValue;
+
+    interruptState = Cy_SysLib_EnterCriticalSection();
+
+    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+    regValue |= CY_SYS_CM4_STATUS_RETAINED;
+    CPUSS->CM4_PWR_CTL = regValue;
+
+    Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysResetCM4
+****************************************************************************//**
+*
+* Resets the Cortex-M4 core and waits for the mode to take the effect.
+*
+* \note The reset mode can not be entered from the retained mode.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+void Cy_SysResetCM4(void)
+{
+    uint32_t interruptState;
+    uint32_t regValue;
+
+    interruptState = Cy_SysLib_EnterCriticalSection();
+
+    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+    regValue |= CY_SYS_CM4_STATUS_RESET;
+    CPUSS->CM4_PWR_CTL = regValue;
+
+    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+    {
+        /* Wait for the power mode to take effect */
+    }
+
+    Cy_SysLib_ExitCriticalSection(interruptState);
+}
+#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+/*******************************************************************************
+* Function Name: Cy_SysIpcPipeIsrCm0
+****************************************************************************//**
+*
+* This is the interrupt service routine for the system pipe.
+*
+*******************************************************************************/
+void Cy_SysIpcPipeIsrCm0(void)
+{
+    Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR);
+}
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_MemorySymbols
+****************************************************************************//**
+*
+* The intention of the function is to declare boundaries of the memories for the
+* MDK compilers. For the rest of the supported compilers, this is done using
+* linker configuration files. The following symbols used by the cymcuelftool.
+*
+*******************************************************************************/
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
+__asm void Cy_MemorySymbols(void)
+{
+    /* Flash */
+    EXPORT __cy_memory_0_start
+    EXPORT __cy_memory_0_length
+    EXPORT __cy_memory_0_row_size
+
+    /* Working Flash */
+    EXPORT __cy_memory_1_start
+    EXPORT __cy_memory_1_length
+    EXPORT __cy_memory_1_row_size
+
+    /* Supervisory Flash */
+    EXPORT __cy_memory_2_start
+    EXPORT __cy_memory_2_length
+    EXPORT __cy_memory_2_row_size
+
+    /* XIP */
+    EXPORT __cy_memory_3_start
+    EXPORT __cy_memory_3_length
+    EXPORT __cy_memory_3_row_size
+
+    /* eFuse */
+    EXPORT __cy_memory_4_start
+    EXPORT __cy_memory_4_length
+    EXPORT __cy_memory_4_row_size
+
+    /* Flash */
+__cy_memory_0_start     EQU __cpp(CY_FLASH_BASE)
+__cy_memory_0_length    EQU __cpp(CY_FLASH_SIZE)
+__cy_memory_0_row_size  EQU 0x200
+
+    /* Flash region for EEPROM emulation */
+__cy_memory_1_start     EQU __cpp(CY_EM_EEPROM_BASE)
+__cy_memory_1_length    EQU __cpp(CY_EM_EEPROM_SIZE)
+__cy_memory_1_row_size  EQU 0x200
+
+    /* Supervisory Flash */
+__cy_memory_2_start     EQU __cpp(CY_SFLASH_BASE)
+__cy_memory_2_length    EQU __cpp(CY_SFLASH_SIZE)
+__cy_memory_2_row_size  EQU 0x200
+
+    /* XIP */
+__cy_memory_3_start     EQU __cpp(CY_XIP_BASE)
+__cy_memory_3_length    EQU __cpp(CY_XIP_SIZE)
+__cy_memory_3_row_size  EQU 0x200
+
+    /* eFuse */
+__cy_memory_4_start     EQU __cpp(0x90700000)
+__cy_memory_4_length    EQU __cpp(0x100000)
+__cy_memory_4_row_size  EQU __cpp(1)
+}
+#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
+
+
+/* [] END OF FILE */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct

@@ -0,0 +1,277 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx5_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08002000
+#define RAM_SIZE                0x0003D800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00080000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE         0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    { 
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.s

@@ -0,0 +1,652 @@
+;/**************************************************************************//**
+; * @file     startup_psoc6_03_cm4.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM4 Device Series
+; * @version  V5.00
+; * @date     02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+                IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base|
+                IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length|
+                
+__Vectors       DCD    |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack
+
+                DCD     Reset_Handler             ; Reset Handler
+
+                DCD     0x0000000D                            ; NMI Handler located at ROM code
+                DCD     HardFault_Handler                     ; Hard Fault Handler
+                DCD     MemManage_Handler                     ; MPU Fault Handler
+                DCD     BusFault_Handler                      ; Bus Fault Handler
+                DCD     UsageFault_Handler                    ; Usage Fault Handler
+                DCD     0                                     ; Reserved
+                DCD     0                                     ; Reserved
+                DCD     0                                     ; Reserved
+                DCD     0                                     ; Reserved
+                DCD     SVC_Handler                           ; SVCall Handler
+                DCD     DebugMon_Handler                      ; Debug Monitor Handler
+                DCD     0                                     ; Reserved
+                DCD     PendSV_Handler                        ; PendSV Handler
+                DCD     SysTick_Handler                       ; SysTick Handler
+
+                ; External interrupts                           Description
+                DCD     ioss_interrupts_gpio_0_IRQHandler     ; GPIO Port Interrupt #0 
+                DCD     0                                     ; Reserved 
+                DCD     ioss_interrupts_gpio_2_IRQHandler     ; GPIO Port Interrupt #2 
+                DCD     ioss_interrupts_gpio_3_IRQHandler     ; GPIO Port Interrupt #3 
+                DCD     0                                     ; Reserved 
+                DCD     ioss_interrupts_gpio_5_IRQHandler     ; GPIO Port Interrupt #5 
+                DCD     ioss_interrupts_gpio_6_IRQHandler     ; GPIO Port Interrupt #6 
+                DCD     ioss_interrupts_gpio_7_IRQHandler     ; GPIO Port Interrupt #7 
+                DCD     ioss_interrupts_gpio_8_IRQHandler     ; GPIO Port Interrupt #8 
+                DCD     ioss_interrupts_gpio_9_IRQHandler     ; GPIO Port Interrupt #9 
+                DCD     ioss_interrupts_gpio_10_IRQHandler    ; GPIO Port Interrupt #10 
+                DCD     ioss_interrupts_gpio_11_IRQHandler    ; GPIO Port Interrupt #11 
+                DCD     ioss_interrupts_gpio_12_IRQHandler    ; GPIO Port Interrupt #12 
+                DCD     0                                     ; Reserved 
+                DCD     ioss_interrupts_gpio_14_IRQHandler    ; GPIO Port Interrupt #14 
+                DCD     ioss_interrupt_gpio_IRQHandler        ; GPIO All Ports 
+                DCD     ioss_interrupt_vdd_IRQHandler         ; GPIO Supply Detect Interrupt 
+                DCD     lpcomp_interrupt_IRQHandler           ; Low Power Comparator Interrupt 
+                DCD     scb_6_interrupt_IRQHandler            ; Serial Communication Block #6 (DeepSleep capable) 
+                DCD     srss_interrupt_mcwdt_0_IRQHandler     ; Multi Counter Watchdog Timer interrupt 
+                DCD     srss_interrupt_mcwdt_1_IRQHandler     ; Multi Counter Watchdog Timer interrupt 
+                DCD     srss_interrupt_backup_IRQHandler      ; Backup domain interrupt 
+                DCD     srss_interrupt_IRQHandler             ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) 
+                DCD     cpuss_interrupts_ipc_0_IRQHandler     ; CPUSS Inter Process Communication Interrupt #0 
+                DCD     cpuss_interrupts_ipc_1_IRQHandler     ; CPUSS Inter Process Communication Interrupt #1 
+                DCD     cpuss_interrupts_ipc_2_IRQHandler     ; CPUSS Inter Process Communication Interrupt #2 
+                DCD     cpuss_interrupts_ipc_3_IRQHandler     ; CPUSS Inter Process Communication Interrupt #3 
+                DCD     cpuss_interrupts_ipc_4_IRQHandler     ; CPUSS Inter Process Communication Interrupt #4 
+                DCD     cpuss_interrupts_ipc_5_IRQHandler     ; CPUSS Inter Process Communication Interrupt #5 
+                DCD     cpuss_interrupts_ipc_6_IRQHandler     ; CPUSS Inter Process Communication Interrupt #6 
+                DCD     cpuss_interrupts_ipc_7_IRQHandler     ; CPUSS Inter Process Communication Interrupt #7 
+                DCD     cpuss_interrupts_ipc_8_IRQHandler     ; CPUSS Inter Process Communication Interrupt #8 
+                DCD     cpuss_interrupts_ipc_9_IRQHandler     ; CPUSS Inter Process Communication Interrupt #9 
+                DCD     cpuss_interrupts_ipc_10_IRQHandler    ; CPUSS Inter Process Communication Interrupt #10 
+                DCD     cpuss_interrupts_ipc_11_IRQHandler    ; CPUSS Inter Process Communication Interrupt #11 
+                DCD     cpuss_interrupts_ipc_12_IRQHandler    ; CPUSS Inter Process Communication Interrupt #12 
+                DCD     cpuss_interrupts_ipc_13_IRQHandler    ; CPUSS Inter Process Communication Interrupt #13 
+                DCD     cpuss_interrupts_ipc_14_IRQHandler    ; CPUSS Inter Process Communication Interrupt #14 
+                DCD     cpuss_interrupts_ipc_15_IRQHandler    ; CPUSS Inter Process Communication Interrupt #15 
+                DCD     scb_0_interrupt_IRQHandler            ; Serial Communication Block #0 
+                DCD     scb_1_interrupt_IRQHandler            ; Serial Communication Block #1 
+                DCD     scb_2_interrupt_IRQHandler            ; Serial Communication Block #2 
+                DCD     scb_3_interrupt_IRQHandler            ; Serial Communication Block #3 
+                DCD     scb_4_interrupt_IRQHandler            ; Serial Communication Block #4 
+                DCD     scb_5_interrupt_IRQHandler            ; Serial Communication Block #5 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     csd_interrupt_IRQHandler              ; CSD (Capsense) interrupt 
+                DCD     cpuss_interrupts_dmac_0_IRQHandler    ; CPUSS DMAC, Channel #0 
+                DCD     cpuss_interrupts_dmac_1_IRQHandler    ; CPUSS DMAC, Channel #1 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     cpuss_interrupts_dw0_0_IRQHandler     ; CPUSS DataWire #0, Channel #0 
+                DCD     cpuss_interrupts_dw0_1_IRQHandler     ; CPUSS DataWire #0, Channel #1 
+                DCD     cpuss_interrupts_dw0_2_IRQHandler     ; CPUSS DataWire #0, Channel #2 
+                DCD     cpuss_interrupts_dw0_3_IRQHandler     ; CPUSS DataWire #0, Channel #3 
+                DCD     cpuss_interrupts_dw0_4_IRQHandler     ; CPUSS DataWire #0, Channel #4 
+                DCD     cpuss_interrupts_dw0_5_IRQHandler     ; CPUSS DataWire #0, Channel #5 
+                DCD     cpuss_interrupts_dw0_6_IRQHandler     ; CPUSS DataWire #0, Channel #6 
+                DCD     cpuss_interrupts_dw0_7_IRQHandler     ; CPUSS DataWire #0, Channel #7 
+                DCD     cpuss_interrupts_dw0_8_IRQHandler     ; CPUSS DataWire #0, Channel #8 
+                DCD     cpuss_interrupts_dw0_9_IRQHandler     ; CPUSS DataWire #0, Channel #9 
+                DCD     cpuss_interrupts_dw0_10_IRQHandler    ; CPUSS DataWire #0, Channel #10 
+                DCD     cpuss_interrupts_dw0_11_IRQHandler    ; CPUSS DataWire #0, Channel #11 
+                DCD     cpuss_interrupts_dw0_12_IRQHandler    ; CPUSS DataWire #0, Channel #12 
+                DCD     cpuss_interrupts_dw0_13_IRQHandler    ; CPUSS DataWire #0, Channel #13 
+                DCD     cpuss_interrupts_dw0_14_IRQHandler    ; CPUSS DataWire #0, Channel #14 
+                DCD     cpuss_interrupts_dw0_15_IRQHandler    ; CPUSS DataWire #0, Channel #15 
+                DCD     cpuss_interrupts_dw0_16_IRQHandler    ; CPUSS DataWire #0, Channel #16 
+                DCD     cpuss_interrupts_dw0_17_IRQHandler    ; CPUSS DataWire #0, Channel #17 
+                DCD     cpuss_interrupts_dw0_18_IRQHandler    ; CPUSS DataWire #0, Channel #18 
+                DCD     cpuss_interrupts_dw0_19_IRQHandler    ; CPUSS DataWire #0, Channel #19 
+                DCD     cpuss_interrupts_dw0_20_IRQHandler    ; CPUSS DataWire #0, Channel #20 
+                DCD     cpuss_interrupts_dw0_21_IRQHandler    ; CPUSS DataWire #0, Channel #21 
+                DCD     cpuss_interrupts_dw0_22_IRQHandler    ; CPUSS DataWire #0, Channel #22 
+                DCD     cpuss_interrupts_dw0_23_IRQHandler    ; CPUSS DataWire #0, Channel #23 
+                DCD     cpuss_interrupts_dw0_24_IRQHandler    ; CPUSS DataWire #0, Channel #24 
+                DCD     cpuss_interrupts_dw0_25_IRQHandler    ; CPUSS DataWire #0, Channel #25 
+                DCD     cpuss_interrupts_dw0_26_IRQHandler    ; CPUSS DataWire #0, Channel #26 
+                DCD     cpuss_interrupts_dw0_27_IRQHandler    ; CPUSS DataWire #0, Channel #27 
+                DCD     cpuss_interrupts_dw0_28_IRQHandler    ; CPUSS DataWire #0, Channel #28 
+                DCD     cpuss_interrupts_dw1_0_IRQHandler     ; CPUSS DataWire #1, Channel #0 
+                DCD     cpuss_interrupts_dw1_1_IRQHandler     ; CPUSS DataWire #1, Channel #1 
+                DCD     cpuss_interrupts_dw1_2_IRQHandler     ; CPUSS DataWire #1, Channel #2 
+                DCD     cpuss_interrupts_dw1_3_IRQHandler     ; CPUSS DataWire #1, Channel #3 
+                DCD     cpuss_interrupts_dw1_4_IRQHandler     ; CPUSS DataWire #1, Channel #4 
+                DCD     cpuss_interrupts_dw1_5_IRQHandler     ; CPUSS DataWire #1, Channel #5 
+                DCD     cpuss_interrupts_dw1_6_IRQHandler     ; CPUSS DataWire #1, Channel #6 
+                DCD     cpuss_interrupts_dw1_7_IRQHandler     ; CPUSS DataWire #1, Channel #7 
+                DCD     cpuss_interrupts_dw1_8_IRQHandler     ; CPUSS DataWire #1, Channel #8 
+                DCD     cpuss_interrupts_dw1_9_IRQHandler     ; CPUSS DataWire #1, Channel #9 
+                DCD     cpuss_interrupts_dw1_10_IRQHandler    ; CPUSS DataWire #1, Channel #10 
+                DCD     cpuss_interrupts_dw1_11_IRQHandler    ; CPUSS DataWire #1, Channel #11 
+                DCD     cpuss_interrupts_dw1_12_IRQHandler    ; CPUSS DataWire #1, Channel #12 
+                DCD     cpuss_interrupts_dw1_13_IRQHandler    ; CPUSS DataWire #1, Channel #13 
+                DCD     cpuss_interrupts_dw1_14_IRQHandler    ; CPUSS DataWire #1, Channel #14 
+                DCD     cpuss_interrupts_dw1_15_IRQHandler    ; CPUSS DataWire #1, Channel #15 
+                DCD     cpuss_interrupts_dw1_16_IRQHandler    ; CPUSS DataWire #1, Channel #16 
+                DCD     cpuss_interrupts_dw1_17_IRQHandler    ; CPUSS DataWire #1, Channel #17 
+                DCD     cpuss_interrupts_dw1_18_IRQHandler    ; CPUSS DataWire #1, Channel #18 
+                DCD     cpuss_interrupts_dw1_19_IRQHandler    ; CPUSS DataWire #1, Channel #19 
+                DCD     cpuss_interrupts_dw1_20_IRQHandler    ; CPUSS DataWire #1, Channel #20 
+                DCD     cpuss_interrupts_dw1_21_IRQHandler    ; CPUSS DataWire #1, Channel #21 
+                DCD     cpuss_interrupts_dw1_22_IRQHandler    ; CPUSS DataWire #1, Channel #22 
+                DCD     cpuss_interrupts_dw1_23_IRQHandler    ; CPUSS DataWire #1, Channel #23 
+                DCD     cpuss_interrupts_dw1_24_IRQHandler    ; CPUSS DataWire #1, Channel #24 
+                DCD     cpuss_interrupts_dw1_25_IRQHandler    ; CPUSS DataWire #1, Channel #25 
+                DCD     cpuss_interrupts_dw1_26_IRQHandler    ; CPUSS DataWire #1, Channel #26 
+                DCD     cpuss_interrupts_dw1_27_IRQHandler    ; CPUSS DataWire #1, Channel #27 
+                DCD     cpuss_interrupts_dw1_28_IRQHandler    ; CPUSS DataWire #1, Channel #28 
+                DCD     cpuss_interrupts_fault_0_IRQHandler   ; CPUSS Fault Structure Interrupt #0 
+                DCD     cpuss_interrupts_fault_1_IRQHandler   ; CPUSS Fault Structure Interrupt #1 
+                DCD     cpuss_interrupt_crypto_IRQHandler     ; CRYPTO Accelerator Interrupt 
+                DCD     cpuss_interrupt_fm_IRQHandler         ; FLASH Macro Interrupt 
+                DCD     cpuss_interrupts_cm4_fp_IRQHandler    ; Floating Point operation fault 
+                DCD     cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 
+                DCD     cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 
+                DCD     cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 
+                DCD     cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 
+                DCD     tcpwm_0_interrupts_0_IRQHandler       ; TCPWM #0, Counter #0 
+                DCD     tcpwm_0_interrupts_1_IRQHandler       ; TCPWM #0, Counter #1 
+                DCD     tcpwm_0_interrupts_2_IRQHandler       ; TCPWM #0, Counter #2 
+                DCD     tcpwm_0_interrupts_3_IRQHandler       ; TCPWM #0, Counter #3 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     tcpwm_1_interrupts_0_IRQHandler       ; TCPWM #1, Counter #0 
+                DCD     tcpwm_1_interrupts_1_IRQHandler       ; TCPWM #1, Counter #1 
+                DCD     tcpwm_1_interrupts_2_IRQHandler       ; TCPWM #1, Counter #2 
+                DCD     tcpwm_1_interrupts_3_IRQHandler       ; TCPWM #1, Counter #3 
+                DCD     tcpwm_1_interrupts_4_IRQHandler       ; TCPWM #1, Counter #4 
+                DCD     tcpwm_1_interrupts_5_IRQHandler       ; TCPWM #1, Counter #5 
+                DCD     tcpwm_1_interrupts_6_IRQHandler       ; TCPWM #1, Counter #6 
+                DCD     tcpwm_1_interrupts_7_IRQHandler       ; TCPWM #1, Counter #7 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     pass_interrupt_sar_IRQHandler         ; SAR ADC interrupt 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     smif_interrupt_IRQHandler             ; Serial Memory Interface interrupt 
+                DCD     usb_interrupt_hi_IRQHandler           ; USB Interrupt 
+                DCD     usb_interrupt_med_IRQHandler          ; USB Interrupt 
+                DCD     usb_interrupt_lo_IRQHandler           ; USB Interrupt 
+                DCD     sdhc_0_interrupt_wakeup_IRQHandler    ; SDIO wakeup interrupt for mxsdhc 
+                DCD     sdhc_0_interrupt_general_IRQHandler   ; Consolidated interrupt for mxsdhc for everything else 
+                DCD     0                                     ; Reserved 
+                DCD     0                                     ; Reserved 
+                DCD     canfd_0_interrupt0_IRQHandler         ; Can #0, Consolidated interrupt #0 
+                DCD     canfd_0_interrupts0_0_IRQHandler      ; CAN #0, Interrupt #0, Channel #0 
+                DCD     canfd_0_interrupts1_0_IRQHandler      ; CAN #0, Interrupt #1, Channel #0 
+                DCD     cpuss_interrupts_dw1_29_IRQHandler    ; CPUSS DataWire #1, Channel #29 
+                DCD     cpuss_interrupts_dw1_30_IRQHandler    ; CPUSS DataWire #1, Channel #30 
+                DCD     cpuss_interrupts_dw1_31_IRQHandler    ; CPUSS DataWire #1, Channel #31 
+
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+                EXPORT __ramVectors
+                AREA    RESET_RAM, READWRITE, NOINIT
+__ramVectors    SPACE   __Vectors_Size
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Weak function for startup customization
+;
+; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 
+; because this function is executed as the first instruction in the ResetHandler.
+; The PDL is also not initialized to use the proper register offsets.
+; The user of this function is responsible for initializing the PDL and resources before using them.
+;
+Cy_OnResetUser  PROC
+                EXPORT  Cy_OnResetUser            [WEAK]
+                BX      LR
+                ENDP
+
+; Reset Handler
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  Cy_SystemInitFpuEnable
+                IMPORT  __main
+
+                ; Define strong function for startup customization
+                BL      Cy_OnResetUser
+
+                ; Disable global interrupts
+                CPSID I
+
+                ; Copy vectors from ROM to RAM
+                LDR r1, =__Vectors
+                LDR r0, =__ramVectors
+                LDR r2, =__Vectors_Size
+Vectors_Copy
+                LDR r3, [r1]
+                STR r3, [r0]
+                ADDS r0, r0, #4
+                ADDS r1, r1, #4
+                SUBS r2, r2, #1
+                CMP r2, #0
+                BNE Vectors_Copy
+
+                ; Update Vector Table Offset Register. */
+                LDR r0, =__ramVectors
+                LDR r1, =0xE000ED08
+                STR r0, [r1]
+                dsb 0xF
+
+                ; Enable the FPU if used
+                LDR     R0, =Cy_SystemInitFpuEnable
+                BLX     R0
+                
+                LDR     R0, =__main
+                BLX     R0
+
+                ; Should never get here
+                B       .
+
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+NMI_Handler         PROC
+                    EXPORT  NMI_Handler               [WEAK]
+                    B       .
+                    ENDP
+
+Cy_SysLib_FaultHandler PROC
+                    EXPORT  Cy_SysLib_FaultHandler   [WEAK]
+                    B       .
+                    ENDP
+HardFault_Wrapper\
+                    PROC
+                    EXPORT HardFault_Wrapper         [WEAK]
+                    movs r0, #4
+                    mov r1, LR
+                    tst r0, r1
+                    beq L_MSP
+                    mrs r0, PSP
+                    bl L_API_call
+L_MSP
+                    mrs r0, MSP
+L_API_call
+                    bl Cy_SysLib_FaultHandler
+                    ENDP
+HardFault_Handler\
+                    PROC
+                    EXPORT  HardFault_Handler         [WEAK]
+                    B       HardFault_Wrapper
+                    ENDP
+MemManage_Handler\
+                    PROC
+                    EXPORT  MemManage_Handler         [WEAK]
+                    B       HardFault_Wrapper
+                    ENDP
+BusFault_Handler\
+                    PROC
+                    EXPORT  BusFault_Handler          [WEAK]
+                    B       HardFault_Wrapper
+                    ENDP
+UsageFault_Handler\
+                    PROC
+                    EXPORT  UsageFault_Handler        [WEAK]
+                    B       HardFault_Wrapper
+                    ENDP
+SVC_Handler         PROC
+                    EXPORT  SVC_Handler               [WEAK]
+                    B       .
+                    ENDP
+DebugMon_Handler\
+                    PROC
+                    EXPORT  DebugMon_Handler          [WEAK]
+                    B       .
+                    ENDP
+PendSV_Handler      PROC
+                    EXPORT  PendSV_Handler            [WEAK]
+                    B       .
+                    ENDP
+SysTick_Handler     PROC
+                    EXPORT  SysTick_Handler           [WEAK]
+                    B       .
+                    ENDP
+
+Default_Handler     PROC
+                    EXPORT  Default_Handler                       [WEAK]
+                    EXPORT  ioss_interrupts_gpio_0_IRQHandler     [WEAK]
+                    EXPORT  ioss_interrupts_gpio_2_IRQHandler     [WEAK]
+                    EXPORT  ioss_interrupts_gpio_3_IRQHandler     [WEAK]
+                    EXPORT  ioss_interrupts_gpio_5_IRQHandler     [WEAK]
+                    EXPORT  ioss_interrupts_gpio_6_IRQHandler     [WEAK]
+                    EXPORT  ioss_interrupts_gpio_7_IRQHandler     [WEAK]
+                    EXPORT  ioss_interrupts_gpio_8_IRQHandler     [WEAK]
+                    EXPORT  ioss_interrupts_gpio_9_IRQHandler     [WEAK]
+                    EXPORT  ioss_interrupts_gpio_10_IRQHandler    [WEAK]
+                    EXPORT  ioss_interrupts_gpio_11_IRQHandler    [WEAK]
+                    EXPORT  ioss_interrupts_gpio_12_IRQHandler    [WEAK]
+                    EXPORT  ioss_interrupts_gpio_14_IRQHandler    [WEAK]
+                    EXPORT  ioss_interrupt_gpio_IRQHandler        [WEAK]
+                    EXPORT  ioss_interrupt_vdd_IRQHandler         [WEAK]
+                    EXPORT  lpcomp_interrupt_IRQHandler           [WEAK]
+                    EXPORT  scb_6_interrupt_IRQHandler            [WEAK]
+                    EXPORT  srss_interrupt_mcwdt_0_IRQHandler     [WEAK]
+                    EXPORT  srss_interrupt_mcwdt_1_IRQHandler     [WEAK]
+                    EXPORT  srss_interrupt_backup_IRQHandler      [WEAK]
+                    EXPORT  srss_interrupt_IRQHandler             [WEAK]
+                    EXPORT  cpuss_interrupts_ipc_0_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_ipc_1_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_ipc_2_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_ipc_3_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_ipc_4_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_ipc_5_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_ipc_6_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_ipc_7_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_ipc_8_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_ipc_9_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_ipc_10_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_ipc_11_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_ipc_12_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_ipc_13_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_ipc_14_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_ipc_15_IRQHandler    [WEAK]
+                    EXPORT  scb_0_interrupt_IRQHandler            [WEAK]
+                    EXPORT  scb_1_interrupt_IRQHandler            [WEAK]
+                    EXPORT  scb_2_interrupt_IRQHandler            [WEAK]
+                    EXPORT  scb_3_interrupt_IRQHandler            [WEAK]
+                    EXPORT  scb_4_interrupt_IRQHandler            [WEAK]
+                    EXPORT  scb_5_interrupt_IRQHandler            [WEAK]
+                    EXPORT  csd_interrupt_IRQHandler              [WEAK]
+                    EXPORT  cpuss_interrupts_dmac_0_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dmac_1_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_0_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_1_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_2_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_3_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_4_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_5_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_6_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_7_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_8_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_9_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_10_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_11_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_12_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_13_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_14_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_15_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_16_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_17_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_18_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_19_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_20_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_21_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_22_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_23_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_24_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_25_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_26_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_27_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw0_28_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_0_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_1_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_2_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_3_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_4_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_5_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_6_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_7_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_8_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_9_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_10_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_11_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_12_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_13_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_14_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_15_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_16_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_17_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_18_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_19_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_20_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_21_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_22_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_23_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_24_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_25_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_26_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_27_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_28_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_fault_0_IRQHandler   [WEAK]
+                    EXPORT  cpuss_interrupts_fault_1_IRQHandler   [WEAK]
+                    EXPORT  cpuss_interrupt_crypto_IRQHandler     [WEAK]
+                    EXPORT  cpuss_interrupt_fm_IRQHandler         [WEAK]
+                    EXPORT  cpuss_interrupts_cm4_fp_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK]
+                    EXPORT  cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK]
+                    EXPORT  cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK]
+                    EXPORT  cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK]
+                    EXPORT  tcpwm_0_interrupts_0_IRQHandler       [WEAK]
+                    EXPORT  tcpwm_0_interrupts_1_IRQHandler       [WEAK]
+                    EXPORT  tcpwm_0_interrupts_2_IRQHandler       [WEAK]
+                    EXPORT  tcpwm_0_interrupts_3_IRQHandler       [WEAK]
+                    EXPORT  tcpwm_1_interrupts_0_IRQHandler       [WEAK]
+                    EXPORT  tcpwm_1_interrupts_1_IRQHandler       [WEAK]
+                    EXPORT  tcpwm_1_interrupts_2_IRQHandler       [WEAK]
+                    EXPORT  tcpwm_1_interrupts_3_IRQHandler       [WEAK]
+                    EXPORT  tcpwm_1_interrupts_4_IRQHandler       [WEAK]
+                    EXPORT  tcpwm_1_interrupts_5_IRQHandler       [WEAK]
+                    EXPORT  tcpwm_1_interrupts_6_IRQHandler       [WEAK]
+                    EXPORT  tcpwm_1_interrupts_7_IRQHandler       [WEAK]
+                    EXPORT  pass_interrupt_sar_IRQHandler         [WEAK]
+                    EXPORT  smif_interrupt_IRQHandler             [WEAK]
+                    EXPORT  usb_interrupt_hi_IRQHandler           [WEAK]
+                    EXPORT  usb_interrupt_med_IRQHandler          [WEAK]
+                    EXPORT  usb_interrupt_lo_IRQHandler           [WEAK]
+                    EXPORT  sdhc_0_interrupt_wakeup_IRQHandler    [WEAK]
+                    EXPORT  sdhc_0_interrupt_general_IRQHandler   [WEAK]
+                    EXPORT  canfd_0_interrupt0_IRQHandler         [WEAK]
+                    EXPORT  canfd_0_interrupts0_0_IRQHandler      [WEAK]
+                    EXPORT  canfd_0_interrupts1_0_IRQHandler      [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_29_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_30_IRQHandler    [WEAK]
+                    EXPORT  cpuss_interrupts_dw1_31_IRQHandler    [WEAK]
+
+ioss_interrupts_gpio_0_IRQHandler
+ioss_interrupts_gpio_2_IRQHandler
+ioss_interrupts_gpio_3_IRQHandler
+ioss_interrupts_gpio_5_IRQHandler
+ioss_interrupts_gpio_6_IRQHandler
+ioss_interrupts_gpio_7_IRQHandler
+ioss_interrupts_gpio_8_IRQHandler
+ioss_interrupts_gpio_9_IRQHandler
+ioss_interrupts_gpio_10_IRQHandler
+ioss_interrupts_gpio_11_IRQHandler
+ioss_interrupts_gpio_12_IRQHandler
+ioss_interrupts_gpio_14_IRQHandler
+ioss_interrupt_gpio_IRQHandler
+ioss_interrupt_vdd_IRQHandler
+lpcomp_interrupt_IRQHandler
+scb_6_interrupt_IRQHandler
+srss_interrupt_mcwdt_0_IRQHandler
+srss_interrupt_mcwdt_1_IRQHandler
+srss_interrupt_backup_IRQHandler
+srss_interrupt_IRQHandler
+cpuss_interrupts_ipc_0_IRQHandler
+cpuss_interrupts_ipc_1_IRQHandler
+cpuss_interrupts_ipc_2_IRQHandler
+cpuss_interrupts_ipc_3_IRQHandler
+cpuss_interrupts_ipc_4_IRQHandler
+cpuss_interrupts_ipc_5_IRQHandler
+cpuss_interrupts_ipc_6_IRQHandler
+cpuss_interrupts_ipc_7_IRQHandler
+cpuss_interrupts_ipc_8_IRQHandler
+cpuss_interrupts_ipc_9_IRQHandler
+cpuss_interrupts_ipc_10_IRQHandler
+cpuss_interrupts_ipc_11_IRQHandler
+cpuss_interrupts_ipc_12_IRQHandler
+cpuss_interrupts_ipc_13_IRQHandler
+cpuss_interrupts_ipc_14_IRQHandler
+cpuss_interrupts_ipc_15_IRQHandler
+scb_0_interrupt_IRQHandler
+scb_1_interrupt_IRQHandler
+scb_2_interrupt_IRQHandler
+scb_3_interrupt_IRQHandler
+scb_4_interrupt_IRQHandler
+scb_5_interrupt_IRQHandler
+csd_interrupt_IRQHandler
+cpuss_interrupts_dmac_0_IRQHandler
+cpuss_interrupts_dmac_1_IRQHandler
+cpuss_interrupts_dw0_0_IRQHandler
+cpuss_interrupts_dw0_1_IRQHandler
+cpuss_interrupts_dw0_2_IRQHandler
+cpuss_interrupts_dw0_3_IRQHandler
+cpuss_interrupts_dw0_4_IRQHandler
+cpuss_interrupts_dw0_5_IRQHandler
+cpuss_interrupts_dw0_6_IRQHandler
+cpuss_interrupts_dw0_7_IRQHandler
+cpuss_interrupts_dw0_8_IRQHandler
+cpuss_interrupts_dw0_9_IRQHandler
+cpuss_interrupts_dw0_10_IRQHandler
+cpuss_interrupts_dw0_11_IRQHandler
+cpuss_interrupts_dw0_12_IRQHandler
+cpuss_interrupts_dw0_13_IRQHandler
+cpuss_interrupts_dw0_14_IRQHandler
+cpuss_interrupts_dw0_15_IRQHandler
+cpuss_interrupts_dw0_16_IRQHandler
+cpuss_interrupts_dw0_17_IRQHandler
+cpuss_interrupts_dw0_18_IRQHandler
+cpuss_interrupts_dw0_19_IRQHandler
+cpuss_interrupts_dw0_20_IRQHandler
+cpuss_interrupts_dw0_21_IRQHandler
+cpuss_interrupts_dw0_22_IRQHandler
+cpuss_interrupts_dw0_23_IRQHandler
+cpuss_interrupts_dw0_24_IRQHandler
+cpuss_interrupts_dw0_25_IRQHandler
+cpuss_interrupts_dw0_26_IRQHandler
+cpuss_interrupts_dw0_27_IRQHandler
+cpuss_interrupts_dw0_28_IRQHandler
+cpuss_interrupts_dw1_0_IRQHandler
+cpuss_interrupts_dw1_1_IRQHandler
+cpuss_interrupts_dw1_2_IRQHandler
+cpuss_interrupts_dw1_3_IRQHandler
+cpuss_interrupts_dw1_4_IRQHandler
+cpuss_interrupts_dw1_5_IRQHandler
+cpuss_interrupts_dw1_6_IRQHandler
+cpuss_interrupts_dw1_7_IRQHandler
+cpuss_interrupts_dw1_8_IRQHandler
+cpuss_interrupts_dw1_9_IRQHandler
+cpuss_interrupts_dw1_10_IRQHandler
+cpuss_interrupts_dw1_11_IRQHandler
+cpuss_interrupts_dw1_12_IRQHandler
+cpuss_interrupts_dw1_13_IRQHandler
+cpuss_interrupts_dw1_14_IRQHandler
+cpuss_interrupts_dw1_15_IRQHandler
+cpuss_interrupts_dw1_16_IRQHandler
+cpuss_interrupts_dw1_17_IRQHandler
+cpuss_interrupts_dw1_18_IRQHandler
+cpuss_interrupts_dw1_19_IRQHandler
+cpuss_interrupts_dw1_20_IRQHandler
+cpuss_interrupts_dw1_21_IRQHandler
+cpuss_interrupts_dw1_22_IRQHandler
+cpuss_interrupts_dw1_23_IRQHandler
+cpuss_interrupts_dw1_24_IRQHandler
+cpuss_interrupts_dw1_25_IRQHandler
+cpuss_interrupts_dw1_26_IRQHandler
+cpuss_interrupts_dw1_27_IRQHandler
+cpuss_interrupts_dw1_28_IRQHandler
+cpuss_interrupts_fault_0_IRQHandler
+cpuss_interrupts_fault_1_IRQHandler
+cpuss_interrupt_crypto_IRQHandler
+cpuss_interrupt_fm_IRQHandler
+cpuss_interrupts_cm4_fp_IRQHandler
+cpuss_interrupts_cm0_cti_0_IRQHandler
+cpuss_interrupts_cm0_cti_1_IRQHandler
+cpuss_interrupts_cm4_cti_0_IRQHandler
+cpuss_interrupts_cm4_cti_1_IRQHandler
+tcpwm_0_interrupts_0_IRQHandler
+tcpwm_0_interrupts_1_IRQHandler
+tcpwm_0_interrupts_2_IRQHandler
+tcpwm_0_interrupts_3_IRQHandler
+tcpwm_1_interrupts_0_IRQHandler
+tcpwm_1_interrupts_1_IRQHandler
+tcpwm_1_interrupts_2_IRQHandler
+tcpwm_1_interrupts_3_IRQHandler
+tcpwm_1_interrupts_4_IRQHandler
+tcpwm_1_interrupts_5_IRQHandler
+tcpwm_1_interrupts_6_IRQHandler
+tcpwm_1_interrupts_7_IRQHandler
+pass_interrupt_sar_IRQHandler
+smif_interrupt_IRQHandler
+usb_interrupt_hi_IRQHandler
+usb_interrupt_med_IRQHandler
+usb_interrupt_lo_IRQHandler
+sdhc_0_interrupt_wakeup_IRQHandler
+sdhc_0_interrupt_general_IRQHandler
+canfd_0_interrupt0_IRQHandler
+canfd_0_interrupts0_0_IRQHandler
+canfd_0_interrupts1_0_IRQHandler
+cpuss_interrupts_dw1_29_IRQHandler
+cpuss_interrupts_dw1_30_IRQHandler
+cpuss_interrupts_dw1_31_IRQHandler
+
+                B       .
+                ENDP
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+                IMPORT   __use_two_region_memory
+
+                END
+
+
+; [] END OF FILE