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@@ -6,15 +6,21 @@
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* Change Logs:
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* Date Author Notes
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* 2023-06-05 zengjianwei first version
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- * 2025-06-23 Yucai Liu Support for non-complementary PWM output with advanced timers
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+ * 2025-06-23 Yucai Liu Support for non-complementary PWM output with
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+ * advanced timers
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+ * 2025-12-26 shihongchao Optimize the timer clock frequency acquisition
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+ * method; optimize the gd32_pwm structure to make
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+ * it easier to configure; optimize the RCU enable
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+ * logic; optimize GPIO configuration to maintain
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+ * floating input mode when channels are disabled,
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+ * reducing power consumption.
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*/
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#include <board.h>
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-#include <gd32f30x.h>
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#include <rtdevice.h>
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#include <rtthread.h>
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-#ifdef RT_USING_PWM
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+#ifdef BSP_USING_PWM
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/* #define DRV_DEBUG */
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#define LOG_TAG "drv.pwm"
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@@ -24,208 +30,186 @@
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#define MIN_PERIOD 3
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#define MIN_PULSE 2
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-typedef struct
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-{
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- rt_int8_t TimerIndex; /* timer index:0~13 */
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- rt_uint32_t Port; /* gpio port:GPIOA/GPIOB/GPIOC/... */
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- rt_uint32_t pin; /* gpio pin:GPIO_PIN_0~GPIO_PIN_15 */
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- /* timer channel: -2 is ch_1n, -1 is ch_0n, 0 is ch0, 1 is ch1 */
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- rt_int16_t channel;
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- char *name;
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-} TIMER_PORT_CHANNEL_MAP_S;
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+typedef struct{
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+ uint32_t gpio_port;
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+ uint32_t gpio_af;
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+ uint16_t gpio_pin;
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+}channel_type;
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struct gd32_pwm
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{
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- struct rt_device_pwm pwm_device;
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- TIMER_PORT_CHANNEL_MAP_S tim_handle;
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+ struct rt_device_pwm pwm_device; /* Inherit PWM device */
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+ char *name; /* Device name */
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+ uint32_t timerx; /* Hardware timer dependent on PWM */
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+ rcu_clock_freq_enum apb_of; /* APB bus to which TIMER belongs */
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+ channel_type channels[4]; /* PWM channels */
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+ channel_type nchannels[3]; /* PWM complementary channels, only supported by advanced timers */
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};
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static struct gd32_pwm gd32_pwm_obj[] = {
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-#ifdef RT_USING_PWM1
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- {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm1"}},
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-#endif
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-
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-#ifdef RT_USING_PWM2
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- {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm2"}},
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-#endif
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-
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-#ifdef RT_USING_PWM3
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- {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm3"}},
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+#ifdef BSP_USING_PWM0
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+ {
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+ .name = "pwm0",
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+ .timerx = TIMER0,
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+ .apb_of = CK_APB2,
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+ .channels = {
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+ {GPIOC, GPIO_AF_1, GPIO_PIN_0},
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_1},
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_2},
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_3},
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+ },
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+ .nchannels = {
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+ {GPIOB, GPIO_AF_1, GPIO_PIN_13},
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+ {GPIOB, GPIO_AF_1, GPIO_PIN_14},
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+ {GPIOB, GPIO_AF_1, GPIO_PIN_15},
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+ }
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+ },
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#endif
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-#ifdef RT_USING_PWM4
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- {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm4"}},
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+#ifdef BSP_USING_PWM1
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+ {
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+ .name = "pwm1",
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+ .timerx = TIMER1,
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+ .apb_of = CK_APB1,
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+ .channels = {
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_0},
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_1},
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_2},
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+ {GPIOB, GPIO_AF_1, GPIO_PIN_2},
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+ },
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+ },
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#endif
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-#ifdef RT_USING_PWM5
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- {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm5"}},
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+#ifdef BSP_USING_PWM2
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+ {
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+ .name = "pwm2",
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+ .timerx = TIMER2,
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+ .apb_of = CK_APB1,
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+ .channels = {
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_6},
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_7},
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+ {GPIOB, GPIO_AF_2, GPIO_PIN_0},
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+ {GPIOB, GPIO_AF_2, GPIO_PIN_1},
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+ },
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+ },
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#endif
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-#ifdef RT_USING_PWM6
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- {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm6"}},
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+#ifdef BSP_USING_PWM3
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+ {
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+ .name = "pwm3",
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+ .timerx = TIMER3,
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+ .apb_of = CK_APB1,
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+ .channels = {
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_0},
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_1},
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_2},
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_3},
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+ },
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+ },
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#endif
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-#ifdef RT_USING_PWM7
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- {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm7"}},
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+#ifdef BSP_USING_PWM4
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+ {
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+ .name = "pwm4",
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+ .timerx = TIMER4,
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+ .apb_of = CK_APB1,
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+ .channels = {
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+ {GPIOA, GPIO_AF_2, GPIO_PIN_0},
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+ {GPIOA, GPIO_AF_2, GPIO_PIN_1},
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_2},
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_3},
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+ },
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+ },
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#endif
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-#ifdef RT_USING_PWM8
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- {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm8"}},
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+#ifdef BSP_USING_PWM7
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+ {
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+ .name = "pwm7",
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+ .timerx = TIMER7,
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+ .apb_of = CK_APB2,
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+ .channels = {
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_0},
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_1},
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+ {GPIOC, GPIO_AF_1, GPIO_PIN_8},
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_3},
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+ },
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+ .nchannels = {
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_5},
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+ {GPIOB, GPIO_AF_1, GPIO_PIN_0},
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+ {GPIOB, GPIO_AF_1, GPIO_PIN_1},
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+ }
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+ },
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#endif
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-#ifdef RT_USING_PWM9
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- {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm9"}},
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+#ifdef BSP_USING_PWM8
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+ {
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+ .name = "pwm8",
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+ .timerx = TIMER8,
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+ .apb_of = CK_APB2,
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+ .channels = {
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_2},
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+ {GPIOA, GPIO_AF_3, GPIO_PIN_3},
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+ }, // L1 general-purpose timer is a two-channel timer
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+ },
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#endif
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-#ifdef RT_USING_PWM10
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- {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm10"}},
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+#ifdef BSP_USING_PWM9
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+ {
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+ .name = "pwm9",
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+ .timerx = TIMER9,
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+ .apb_of = CK_APB2,
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+ .channels = {
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_0},
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+ }, // L2 general-purpose timer is a single-channel timer
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+ },
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#endif
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-#ifdef RT_USING_PWM11
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- {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm11"}},
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+#ifdef BSP_USING_PWM10
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+ {
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+ .name = "pwm10",
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+ .timerx = TIMER10,
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+ .apb_of = CK_APB2,
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+ .channels = {
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_0},
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+ }, // L2 general-purpose timer is a single-channel timer
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+ },
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#endif
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-#ifdef RT_USING_PWM12
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- {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm12"}},
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+#ifdef BSP_USING_PWM11
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+ {
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+ .name = "pwm11",
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+ .timerx = TIMER11,
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+ .apb_of = CK_APB1,
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+ .channels = {
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_0},
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_1},
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+ }, // L1 general-purpose timer is a two-channel timer
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+ },
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#endif
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-#ifdef RT_USING_PWM13
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- {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm13"}},
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+#ifdef BSP_USING_PWM12
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+ {
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+ .name = "pwm12",
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+ .timerx = TIMER12,
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+ .apb_of = CK_APB1,
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+ .channels = {
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_0},
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+ }, // L2 general-purpose timer is a single-channel timer
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+ },
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#endif
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-#ifdef RT_USING_PWM14
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- {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm14"}},
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+#ifdef BSP_USING_PWM13
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+ {
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+ .name = "pwm13",
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+ .timerx = TIMER13,
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+ .apb_of = CK_APB1,
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+ .channels = {
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+ {GPIOA, GPIO_AF_1, GPIO_PIN_7},
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+ }, // L2 general-purpose timer is a single-channel timer
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+ },
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#endif
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};
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-typedef struct
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-{
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- rt_uint32_t Port[7];
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- rt_int8_t TimerIndex[14];
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-} TIMER_PERIPH_LIST_S;
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-
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-static TIMER_PERIPH_LIST_S gd32_timer_periph_list = {
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- .Port = {0, 0, 0, 0, 0, 0, 0},
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- .TimerIndex = {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},
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-};
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-
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-/*
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- * 将所有用到的 gpio port 和 timer 不重复地列举出来，以方便后面不重复地初始化
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- */
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-static rt_err_t pwm_find_timer_periph(void)
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-{
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- rt_int16_t i, j, k;
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-
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- /* find gpio port of defined table */
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- for (i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); ++i)
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- {
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- /* find -1 of gd32_periph_list's member of Port */
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- for (j = 0; j < sizeof(gd32_timer_periph_list.Port) / sizeof(gd32_timer_periph_list.Port[0]); ++j)
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- {
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- if (0 == gd32_timer_periph_list.Port[j])
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- {
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- break;
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- }
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- }
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-
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- if (j >= sizeof(gd32_timer_periph_list.Port) / sizeof(gd32_timer_periph_list.Port[0]))
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- {
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- LOG_E("Can not find -1 of gd32_periph_list's member of Port!\n");
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- break;
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- }
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-
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- /* find the different of Port */
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- for (k = 0; k < j; ++k)
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- {
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- if (gd32_pwm_obj[i].tim_handle.Port == gd32_timer_periph_list.Port[k])
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- {
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- break;
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- }
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- }
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-
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- /* if can not find the same Port */
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- if (k == j)
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- {
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- gd32_timer_periph_list.Port[j] = gd32_pwm_obj[i].tim_handle.Port;
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- }
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- }
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-
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- /* find timer periph of defined table */
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- for (i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); ++i)
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- {
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- /* find -1 of gd32_periph_list's member of TimerIndex */
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- for (j = 0; j < sizeof(gd32_timer_periph_list.TimerIndex) / sizeof(gd32_timer_periph_list.TimerIndex[0]); ++j)
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- {
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- if (-1 == gd32_timer_periph_list.TimerIndex[j])
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- {
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- break;
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- }
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- }
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-
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- if (j >= sizeof(gd32_timer_periph_list.TimerIndex) / sizeof(gd32_timer_periph_list.TimerIndex[0]))
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- {
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- LOG_E("Can not find -1 of gd32_periph_list's member of TimerIndex!\n");
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- break;
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- }
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-
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- /* find the different of TimerIndex */
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- for (k = 0; k < j; ++k)
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- {
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- if (gd32_pwm_obj[i].tim_handle.TimerIndex == gd32_timer_periph_list.TimerIndex[k])
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- {
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- break;
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- }
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- }
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-
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- /* if can not find the same TimerIndex */
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- if (k == j)
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- {
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- gd32_timer_periph_list.TimerIndex[j] = gd32_pwm_obj[i].tim_handle.TimerIndex;
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- }
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- }
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-
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- return RT_EOK;
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-}
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-
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-static rt_uint32_t index_to_timer(rt_int8_t TimerIndex)
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-{
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- switch (TimerIndex)
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- {
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- case 0:
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- return TIMER0;
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- case 1:
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- return TIMER1;
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- case 2:
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- return TIMER2;
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- case 3:
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- return TIMER3;
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- case 4:
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- return TIMER4;
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- case 5:
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- return TIMER5;
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- case 6:
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- return TIMER6;
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- case 7:
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- return TIMER7;
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- case 8:
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- return TIMER8;
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- case 9:
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- return TIMER9;
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- case 10:
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- return TIMER10;
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- case 11:
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- return TIMER11;
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- case 12:
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- return TIMER12;
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- case 13:
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- return TIMER13;
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-
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- default:
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- LOG_E("Unsport timer periph!\n");
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- }
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- return TIMER0;
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-}
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-
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static void gpio_clock_enable(rt_uint32_t Port)
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{
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switch (Port)
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@@ -257,54 +241,52 @@ static void gpio_clock_enable(rt_uint32_t Port)
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}
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}
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-static void timer_clock_enable(rt_int8_t TimerIndex)
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+static void timer_clock_enable(uint32_t timer)
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{
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- switch (TimerIndex)
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+ switch (timer)
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{
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- case 0:
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+ case TIMER0:
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rcu_periph_clock_enable(RCU_TIMER0);
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break;
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- case 1:
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+ case TIMER1:
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rcu_periph_clock_enable(RCU_TIMER1);
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break;
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|
- case 2:
|
|
|
+ case TIMER2:
|
|
|
rcu_periph_clock_enable(RCU_TIMER2);
|
|
|
break;
|
|
|
- case 3:
|
|
|
+ case TIMER3:
|
|
|
rcu_periph_clock_enable(RCU_TIMER3);
|
|
|
break;
|
|
|
- case 4:
|
|
|
+ case TIMER4:
|
|
|
rcu_periph_clock_enable(RCU_TIMER4);
|
|
|
break;
|
|
|
- case 5:
|
|
|
+ case TIMER5:
|
|
|
rcu_periph_clock_enable(RCU_TIMER5);
|
|
|
break;
|
|
|
- case 6:
|
|
|
+ case TIMER6:
|
|
|
rcu_periph_clock_enable(RCU_TIMER6);
|
|
|
break;
|
|
|
- case 7:
|
|
|
+ case TIMER7:
|
|
|
rcu_periph_clock_enable(RCU_TIMER7);
|
|
|
break;
|
|
|
-#ifndef GD32F30X_HD
|
|
|
- case 8:
|
|
|
+ case TIMER8:
|
|
|
rcu_periph_clock_enable(RCU_TIMER8);
|
|
|
break;
|
|
|
- case 9:
|
|
|
+ case TIMER9:
|
|
|
rcu_periph_clock_enable(RCU_TIMER9);
|
|
|
break;
|
|
|
- case 10:
|
|
|
+ case TIMER10:
|
|
|
rcu_periph_clock_enable(RCU_TIMER10);
|
|
|
break;
|
|
|
- case 11:
|
|
|
+ case TIMER11:
|
|
|
rcu_periph_clock_enable(RCU_TIMER11);
|
|
|
break;
|
|
|
- case 12:
|
|
|
+ case TIMER12:
|
|
|
rcu_periph_clock_enable(RCU_TIMER12);
|
|
|
break;
|
|
|
- case 13:
|
|
|
+ case TIMER13:
|
|
|
rcu_periph_clock_enable(RCU_TIMER13);
|
|
|
break;
|
|
|
-#endif
|
|
|
default:
|
|
|
LOG_E("Unsport timer periph!\n");
|
|
|
}
|
|
|
@@ -314,96 +296,191 @@ static void rcu_config(void)
|
|
|
{
|
|
|
rt_int16_t i;
|
|
|
|
|
|
- for (i = 0; i < sizeof(gd32_timer_periph_list.Port) / sizeof(gd32_timer_periph_list.Port[0]); ++i)
|
|
|
+ for (i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); ++i)
|
|
|
{
|
|
|
- if (0 == gd32_timer_periph_list.Port[i])
|
|
|
+ /* enable GPIO clock */
|
|
|
+ switch (gd32_pwm_obj[i].timerx)
|
|
|
{
|
|
|
+ /* Advanced timer */
|
|
|
+ case TIMER0:
|
|
|
+ case TIMER7:
|
|
|
+ gpio_clock_enable(gd32_pwm_obj[i].nchannels[0].gpio_port);
|
|
|
+ gpio_clock_enable(gd32_pwm_obj[i].nchannels[1].gpio_port);
|
|
|
+ gpio_clock_enable(gd32_pwm_obj[i].nchannels[2].gpio_port);
|
|
|
+
|
|
|
+ /* L0 general-purpose timer */
|
|
|
+ case TIMER1:
|
|
|
+ case TIMER2:
|
|
|
+ case TIMER3:
|
|
|
+ case TIMER4:
|
|
|
+ gpio_clock_enable(gd32_pwm_obj[i].channels[2].gpio_port);
|
|
|
+ gpio_clock_enable(gd32_pwm_obj[i].channels[3].gpio_port);
|
|
|
+
|
|
|
+ /* L1 general-purpose timer */
|
|
|
+ case TIMER8:
|
|
|
+ case TIMER11:
|
|
|
+ gpio_clock_enable(gd32_pwm_obj[i].channels[1].gpio_port);
|
|
|
+
|
|
|
+ /* L2 general-purpose timer */
|
|
|
+ case TIMER9:
|
|
|
+ case TIMER10:
|
|
|
+ case TIMER12:
|
|
|
+ case TIMER13:
|
|
|
+ gpio_clock_enable(gd32_pwm_obj[i].channels[0].gpio_port);
|
|
|
break;
|
|
|
- }
|
|
|
-
|
|
|
- /* enable GPIO clock */
|
|
|
- gpio_clock_enable(gd32_timer_periph_list.Port[i]);
|
|
|
- }
|
|
|
-
|
|
|
- rcu_periph_clock_enable(RCU_AF);
|
|
|
|
|
|
- for (i = 0; i < sizeof(gd32_timer_periph_list.TimerIndex) / sizeof(gd32_timer_periph_list.TimerIndex[0]); ++i)
|
|
|
- {
|
|
|
- if (-1 == gd32_timer_periph_list.TimerIndex[i])
|
|
|
- {
|
|
|
+ default:
|
|
|
+ LOG_E("Unsport timer periph at rcu_config!\n");
|
|
|
break;
|
|
|
}
|
|
|
+ }
|
|
|
|
|
|
+ for (i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); ++i)
|
|
|
+ {
|
|
|
/* enable timer clock */
|
|
|
- timer_clock_enable(gd32_timer_periph_list.TimerIndex[i]);
|
|
|
- timer_deinit(index_to_timer(gd32_timer_periph_list.TimerIndex[i]));
|
|
|
+ timer_clock_enable(gd32_pwm_obj[i].timerx);
|
|
|
+ timer_deinit(gd32_pwm_obj[i].timerx);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
-static void gpio_config(void)
|
|
|
+/**
|
|
|
+ * @brief Configure PWM output pin to PWM output mode
|
|
|
+ * @param pwm PWM object
|
|
|
+ * @param configuration Configuration information passed by PWM driver framework
|
|
|
+ */
|
|
|
+static void gpio_config_pwmout(const struct gd32_pwm *pwm,
|
|
|
+ const struct rt_pwm_configuration *configuration)
|
|
|
{
|
|
|
- rt_int16_t i;
|
|
|
-
|
|
|
- /* config the GPIO as analog mode */
|
|
|
- for (i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); ++i)
|
|
|
+ channel_type channel;
|
|
|
+ uint8_t channel_num = configuration->channel;
|
|
|
+ if(channel_num == 0)
|
|
|
+ {
|
|
|
+ LOG_E("PWM channel starts from 1!\n");
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ if(configuration->complementary)
|
|
|
+ {
|
|
|
+ if(channel_num > 3)
|
|
|
+ {
|
|
|
+ LOG_E("GD32 PWM complementary channel max 3!\n");
|
|
|
+ return;
|
|
|
+ };
|
|
|
+ channel = pwm->nchannels[channel_num-1];
|
|
|
+ }
|
|
|
+ else
|
|
|
{
|
|
|
- gpio_init(gd32_pwm_obj[i].tim_handle.Port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, gd32_pwm_obj[i].tim_handle.pin);
|
|
|
+ if(channel_num > 4)
|
|
|
+ {
|
|
|
+ LOG_E("GD32 PWM complementary channel max 4!\n");
|
|
|
+ return;
|
|
|
+ };
|
|
|
+ channel = pwm->channels[channel_num-1];
|
|
|
}
|
|
|
+ gpio_mode_set(channel.gpio_port, GPIO_MODE_AF, GPIO_PUPD_NONE, channel.gpio_pin);
|
|
|
+ gpio_output_options_set(channel.gpio_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, channel.gpio_pin);
|
|
|
+ gpio_af_set(channel.gpio_port, channel.gpio_af, channel.gpio_pin);
|
|
|
}
|
|
|
|
|
|
-static void timer_init_para(timer_parameter_struct *initpara)
|
|
|
+/**
|
|
|
+ * @brief Configure PWM output pin to PWM floating input mode
|
|
|
+ * @param pwm PWM object
|
|
|
+ * @param configuration Configuration information passed by PWM driver framework
|
|
|
+ */
|
|
|
+static void gpio_config_input(const struct gd32_pwm *pwm,
|
|
|
+ const struct rt_pwm_configuration *configuration)
|
|
|
{
|
|
|
- rt_int16_t i;
|
|
|
-
|
|
|
- for (i = 0; i < sizeof(gd32_timer_periph_list.TimerIndex) / sizeof(gd32_timer_periph_list.TimerIndex[0]); ++i)
|
|
|
+ channel_type channel = {0};
|
|
|
+ uint8_t channel_num = configuration->channel;
|
|
|
+ if(channel_num == 0)
|
|
|
{
|
|
|
- /* config timer */
|
|
|
- if (-1 != gd32_timer_periph_list.TimerIndex[i])
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ if(configuration->complementary)
|
|
|
+ {
|
|
|
+ if(channel_num > 3)
|
|
|
{
|
|
|
- timer_init(index_to_timer(gd32_timer_periph_list.TimerIndex[i]), initpara);
|
|
|
- }
|
|
|
+ LOG_E("GD32 PWM complementary channel max 3!\n");
|
|
|
+ return;
|
|
|
+ };
|
|
|
+ channel = pwm->nchannels[channel_num-1];
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ if(channel_num > 4)
|
|
|
+ {
|
|
|
+ LOG_E("GD32 PWM complementary channel max 4!\n");
|
|
|
+ return;
|
|
|
+ };
|
|
|
+ channel = pwm->channels[channel_num-1];
|
|
|
}
|
|
|
+ gpio_mode_set(channel.gpio_port, GPIO_MODE_INPUT, GPIO_PUPD_NONE, channel.gpio_pin);
|
|
|
}
|
|
|
|
|
|
-static void channel_output_config(timer_oc_parameter_struct *ocpara)
|
|
|
+static void channel_output_config(rt_uint32_t timer_periph, timer_oc_parameter_struct *ocpara)
|
|
|
{
|
|
|
- rt_int16_t i;
|
|
|
- rt_uint32_t timer_periph;
|
|
|
-
|
|
|
- /* config the channel config */
|
|
|
- for (i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); ++i)
|
|
|
+ switch (timer_periph)
|
|
|
{
|
|
|
- if (gd32_pwm_obj[i].tim_handle.channel < 0)
|
|
|
- {
|
|
|
- ocpara->outputstate = TIMER_CCX_DISABLE;
|
|
|
- ocpara->outputnstate = TIMER_CCXN_ENABLE;
|
|
|
- gd32_pwm_obj[i].tim_handle.channel = -(gd32_pwm_obj[i].tim_handle.channel + 1);
|
|
|
- }
|
|
|
- timer_periph = index_to_timer(gd32_pwm_obj[i].tim_handle.TimerIndex);
|
|
|
- timer_channel_output_config(timer_periph, gd32_pwm_obj[i].tim_handle.channel, ocpara);
|
|
|
+ /* Advanced timer */
|
|
|
+ case TIMER0:
|
|
|
+ case TIMER7:
|
|
|
+ timer_primary_output_config(timer_periph, ENABLE);
|
|
|
+
|
|
|
+ /* L0 general-purpose timer */
|
|
|
+ case TIMER1:
|
|
|
+ case TIMER2:
|
|
|
+ case TIMER3:
|
|
|
+ case TIMER4:
|
|
|
+ timer_channel_output_config(timer_periph, TIMER_CH_2, ocpara);
|
|
|
+ timer_channel_output_pulse_value_config(timer_periph, TIMER_CH_2, 7999);
|
|
|
+ timer_channel_output_mode_config(timer_periph, TIMER_CH_2, TIMER_OC_MODE_PWM0);
|
|
|
+ timer_channel_output_shadow_config(timer_periph, TIMER_CH_2, TIMER_OC_SHADOW_DISABLE);
|
|
|
+ /* auto-reload preload shadow reg enable */
|
|
|
+ /* timer_auto_reload_shadow_enable(timer_periph); */
|
|
|
+ timer_channel_output_state_config(timer_periph, TIMER_CH_2, TIMER_CCX_DISABLE);
|
|
|
+ timer_channel_complementary_output_state_config(timer_periph, TIMER_CH_2, TIMER_CCXN_DISABLE);
|
|
|
|
|
|
- timer_channel_output_pulse_value_config(timer_periph, gd32_pwm_obj[i].tim_handle.channel, 7999);
|
|
|
- timer_channel_output_mode_config(timer_periph, gd32_pwm_obj[i].tim_handle.channel, TIMER_OC_MODE_PWM0);
|
|
|
- timer_channel_output_shadow_config(timer_periph, gd32_pwm_obj[i].tim_handle.channel, TIMER_OC_SHADOW_DISABLE);
|
|
|
+ timer_channel_output_config(timer_periph, TIMER_CH_3, ocpara);
|
|
|
+ timer_channel_output_pulse_value_config(timer_periph, TIMER_CH_3, 7999);
|
|
|
+ timer_channel_output_mode_config(timer_periph, TIMER_CH_3, TIMER_OC_MODE_PWM0);
|
|
|
+ timer_channel_output_shadow_config(timer_periph, TIMER_CH_3, TIMER_OC_SHADOW_DISABLE);
|
|
|
/* auto-reload preload shadow reg enable */
|
|
|
/* timer_auto_reload_shadow_enable(timer_periph); */
|
|
|
- timer_channel_output_state_config(timer_periph, gd32_pwm_obj[i].tim_handle.channel, TIMER_CCX_DISABLE);
|
|
|
- timer_channel_complementary_output_state_config(timer_periph, gd32_pwm_obj[i].tim_handle.channel, TIMER_CCXN_DISABLE);
|
|
|
- }
|
|
|
+ timer_channel_output_state_config(timer_periph, TIMER_CH_3, TIMER_CCX_DISABLE);
|
|
|
+ timer_channel_complementary_output_state_config(timer_periph, TIMER_CH_3, TIMER_CCXN_DISABLE);
|
|
|
+
|
|
|
+ /* L1 general-purpose timer */
|
|
|
+ case TIMER8:
|
|
|
+ case TIMER11:
|
|
|
+ timer_channel_output_config(timer_periph, TIMER_CH_1, ocpara);
|
|
|
+ timer_channel_output_pulse_value_config(timer_periph, TIMER_CH_1, 7999);
|
|
|
+ timer_channel_output_mode_config(timer_periph, TIMER_CH_1, TIMER_OC_MODE_PWM0);
|
|
|
+ timer_channel_output_shadow_config(timer_periph, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE);
|
|
|
+ /* auto-reload preload shadow reg enable */
|
|
|
+ /* timer_auto_reload_shadow_enable(timer_periph); */
|
|
|
+ timer_channel_output_state_config(timer_periph, TIMER_CH_1, TIMER_CCX_DISABLE);
|
|
|
+ timer_channel_complementary_output_state_config(timer_periph, TIMER_CH_1, TIMER_CCXN_DISABLE);
|
|
|
+
|
|
|
+ /* L2 general-purpose timer */
|
|
|
+ case TIMER9:
|
|
|
+ case TIMER10:
|
|
|
+ case TIMER12:
|
|
|
+ case TIMER13:
|
|
|
+ timer_channel_output_config(timer_periph, TIMER_CH_0, ocpara);
|
|
|
+ timer_channel_output_pulse_value_config(timer_periph, TIMER_CH_0, 7999);
|
|
|
+ timer_channel_output_mode_config(timer_periph, TIMER_CH_0, TIMER_OC_MODE_PWM0);
|
|
|
+ timer_channel_output_shadow_config(timer_periph, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE);
|
|
|
+ /* auto-reload preload shadow reg enable */
|
|
|
+ /* timer_auto_reload_shadow_enable(timer_periph); */
|
|
|
+ timer_channel_output_state_config(timer_periph, TIMER_CH_0, TIMER_CCX_DISABLE);
|
|
|
+ timer_channel_complementary_output_state_config(timer_periph, TIMER_CH_0, TIMER_CCXN_DISABLE);
|
|
|
+ break;
|
|
|
|
|
|
- /* enable timer */
|
|
|
- for (i = 0; i < sizeof(gd32_timer_periph_list.TimerIndex) / sizeof(gd32_timer_periph_list.TimerIndex[0]); ++i)
|
|
|
- {
|
|
|
- if (-1 != gd32_timer_periph_list.TimerIndex[i])
|
|
|
- {
|
|
|
- timer_periph = index_to_timer(gd32_timer_periph_list.TimerIndex[i]);
|
|
|
- if (timer_periph == TIMER0 || timer_periph == TIMER7)
|
|
|
- {
|
|
|
- timer_primary_output_config(timer_periph, ENABLE);
|
|
|
- }
|
|
|
- timer_enable(timer_periph);
|
|
|
- }
|
|
|
+ default:
|
|
|
+ LOG_E("Unsport timer periph at channel_output_config!\n");
|
|
|
+ break;
|
|
|
}
|
|
|
+
|
|
|
+ timer_enable(timer_periph);
|
|
|
}
|
|
|
|
|
|
static void timer_config(void)
|
|
|
@@ -412,58 +489,103 @@ static void timer_config(void)
|
|
|
timer_parameter_struct timer_initpara;
|
|
|
|
|
|
/* TIMER configuration */
|
|
|
- timer_initpara.prescaler = 119;
|
|
|
+ timer_initpara.prescaler = 199;
|
|
|
timer_initpara.alignedmode = TIMER_COUNTER_EDGE;
|
|
|
timer_initpara.counterdirection = TIMER_COUNTER_UP;
|
|
|
timer_initpara.period = 15999;
|
|
|
timer_initpara.clockdivision = TIMER_CKDIV_DIV1;
|
|
|
timer_initpara.repetitioncounter = 0;
|
|
|
- timer_init_para(&timer_initpara);
|
|
|
+ for (size_t i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); ++i)
|
|
|
+ {
|
|
|
+ timer_init(gd32_pwm_obj[i].timerx, &timer_initpara);
|
|
|
+ }
|
|
|
|
|
|
/* CHX configuration in PWM mode */
|
|
|
- timer_ocintpara.outputstate = TIMER_CCX_ENABLE;
|
|
|
+ timer_ocintpara.outputstate = TIMER_CCX_DISABLE;
|
|
|
timer_ocintpara.outputnstate = TIMER_CCXN_DISABLE;
|
|
|
timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH;
|
|
|
timer_ocintpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH;
|
|
|
timer_ocintpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW;
|
|
|
timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
|
|
|
- channel_output_config(&timer_ocintpara);
|
|
|
+ /* config the channel config */
|
|
|
+ for (size_t i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); ++i)
|
|
|
+ {
|
|
|
+ channel_output_config(gd32_pwm_obj[i].timerx, &timer_ocintpara);
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
-static rt_err_t drv_pwm_enable(TIMER_PORT_CHANNEL_MAP_S *pstTimerMap, struct rt_pwm_configuration *configuration,
|
|
|
+static rt_err_t drv_pwm_enable(struct gd32_pwm *pwm, const struct rt_pwm_configuration *configuration,
|
|
|
rt_bool_t enable)
|
|
|
{
|
|
|
+ if(channel_num == 0)
|
|
|
+ {
|
|
|
+ LOG_E("GD32 PWM channel starts from 1!\n");
|
|
|
+ return -RT_EINVAL;
|
|
|
+ }
|
|
|
+ if(configuration->complementary)
|
|
|
+ {
|
|
|
+ if(channel_num > 3)
|
|
|
+ {
|
|
|
+ LOG_E("GD32 PWM complementary channel max 3!\n");
|
|
|
+ return -RT_EINVAL;
|
|
|
+ };
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ if(channel_num > 4)
|
|
|
+ {
|
|
|
+ LOG_E("GD32 PWM complementary channel max 4!\n");
|
|
|
+ return -RT_EINVAL;
|
|
|
+ };
|
|
|
+ }
|
|
|
+
|
|
|
if (!enable)
|
|
|
{
|
|
|
- timer_channel_output_state_config(index_to_timer(pstTimerMap->TimerIndex), configuration->channel,
|
|
|
- TIMER_CCX_DISABLE);
|
|
|
+ gpio_config_input(pwm, configuration);
|
|
|
+ if (configuration->complementary == RT_TRUE)
|
|
|
+ {
|
|
|
+ timer_channel_complementary_output_state_config(pwm->timerx, configuration->channel-1,
|
|
|
+ TIMER_CCXN_DISABLE);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ timer_channel_output_state_config(pwm->timerx, configuration->channel-1,
|
|
|
+ TIMER_CCX_DISABLE);
|
|
|
+ }
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
+ gpio_config_pwmout(pwm, configuration);
|
|
|
if (configuration->complementary == RT_TRUE)
|
|
|
{
|
|
|
- timer_channel_output_state_config(
|
|
|
- index_to_timer(pstTimerMap->TimerIndex), configuration->channel - 1, TIMER_CCXN_ENABLE);
|
|
|
+ timer_channel_complementary_output_state_config(pwm->timerx, configuration->channel-1,
|
|
|
+ TIMER_CCXN_ENABLE);
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
- timer_channel_output_state_config(
|
|
|
- index_to_timer(pstTimerMap->TimerIndex), configuration->channel, TIMER_CCX_ENABLE);
|
|
|
+ timer_channel_output_state_config(pwm->timerx, configuration->channel-1,
|
|
|
+ TIMER_CCX_ENABLE);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
return RT_EOK;
|
|
|
}
|
|
|
|
|
|
-static rt_err_t drv_pwm_get(TIMER_PORT_CHANNEL_MAP_S *pstTimerMap, struct rt_pwm_configuration *configuration)
|
|
|
+static rt_err_t drv_pwm_get(const struct gd32_pwm *pwm, struct rt_pwm_configuration *configuration)
|
|
|
{
|
|
|
rt_uint64_t tim_clock;
|
|
|
rt_uint16_t psc;
|
|
|
rt_uint32_t chxcv;
|
|
|
|
|
|
- tim_clock = rcu_clock_freq_get(CK_SYS);
|
|
|
+ if(configuration->channel == 0)
|
|
|
+ {
|
|
|
+ return -RT_EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ rt_uint8_t coef = (RCU_CFG1&RCU_CFG1_TIMERSEL)?4:2;
|
|
|
+ tim_clock = rcu_clock_freq_get(pwm->apb_of)*coef;
|
|
|
|
|
|
- psc = timer_prescaler_read(index_to_timer(pstTimerMap->TimerIndex));
|
|
|
+ psc = timer_prescaler_read(pwm->timerx);
|
|
|
if (psc == TIMER_CKDIV_DIV2)
|
|
|
{
|
|
|
tim_clock = tim_clock / 2;
|
|
|
@@ -473,21 +595,27 @@ static rt_err_t drv_pwm_get(TIMER_PORT_CHANNEL_MAP_S *pstTimerMap, struct rt_pwm
|
|
|
tim_clock = tim_clock / 4;
|
|
|
}
|
|
|
|
|
|
- chxcv = timer_channel_capture_value_register_read(index_to_timer(pstTimerMap->TimerIndex), configuration->channel);
|
|
|
+ chxcv = timer_channel_capture_value_register_read(pwm->timerx, configuration->channel-1);
|
|
|
/* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
|
|
|
tim_clock /= 1000000UL;
|
|
|
- configuration->period = (TIMER_CAR(index_to_timer(pstTimerMap->TimerIndex)) + 1) * (psc + 1) * 1000UL / tim_clock;
|
|
|
+ configuration->period = (TIMER_CAR(pwm->timerx) + 1) * (psc + 1) * 1000UL / tim_clock;
|
|
|
configuration->pulse = (chxcv + 1) * (psc + 1) * 1000UL / tim_clock;
|
|
|
|
|
|
return RT_EOK;
|
|
|
}
|
|
|
|
|
|
-static rt_err_t drv_pwm_set(TIMER_PORT_CHANNEL_MAP_S *pstTimerMap, struct rt_pwm_configuration *configuration)
|
|
|
+static rt_err_t drv_pwm_set(struct gd32_pwm *pwm, struct rt_pwm_configuration *configuration)
|
|
|
{
|
|
|
rt_uint32_t period, pulse;
|
|
|
rt_uint64_t tim_clock, psc;
|
|
|
|
|
|
- tim_clock = rcu_clock_freq_get(CK_SYS);
|
|
|
+ rt_uint8_t coef = (RCU_CFG1&RCU_CFG1_TIMERSEL)?4:2;
|
|
|
+ tim_clock = rcu_clock_freq_get(pwm->apb_of)*coef;
|
|
|
+
|
|
|
+ if(configuration->channel == 0)
|
|
|
+ {
|
|
|
+ return -RT_EINVAL;
|
|
|
+ }
|
|
|
|
|
|
/* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
|
|
|
tim_clock /= 1000000UL;
|
|
|
@@ -495,14 +623,14 @@ static rt_err_t drv_pwm_set(TIMER_PORT_CHANNEL_MAP_S *pstTimerMap, struct rt_pwm
|
|
|
psc = period / MAX_PERIOD + 1;
|
|
|
period = period / psc;
|
|
|
|
|
|
- timer_prescaler_config(index_to_timer(pstTimerMap->TimerIndex), psc - 1, TIMER_PSC_RELOAD_NOW);
|
|
|
+ timer_prescaler_config(pwm->timerx, psc - 1, TIMER_PSC_RELOAD_NOW);
|
|
|
|
|
|
if (period < MIN_PERIOD)
|
|
|
{
|
|
|
period = MIN_PERIOD;
|
|
|
}
|
|
|
|
|
|
- timer_autoreload_value_config(index_to_timer(pstTimerMap->TimerIndex), period - 1);
|
|
|
+ timer_autoreload_value_config(pwm->timerx, period - 1);
|
|
|
|
|
|
pulse = (unsigned long long)configuration->pulse * tim_clock / psc / 1000ULL;
|
|
|
if (pulse < MIN_PULSE)
|
|
|
@@ -514,11 +642,11 @@ static rt_err_t drv_pwm_set(TIMER_PORT_CHANNEL_MAP_S *pstTimerMap, struct rt_pwm
|
|
|
pulse = period;
|
|
|
}
|
|
|
|
|
|
- timer_channel_output_pulse_value_config(index_to_timer(pstTimerMap->TimerIndex), configuration->channel, pulse);
|
|
|
- timer_counter_value_config(index_to_timer(pstTimerMap->TimerIndex), 0);
|
|
|
+ timer_channel_output_pulse_value_config(pwm->timerx, configuration->channel-1, pulse);
|
|
|
+ timer_counter_value_config(pwm->timerx, 0);
|
|
|
|
|
|
/* Update frequency value */
|
|
|
- timer_event_software_generate(index_to_timer(pstTimerMap->TimerIndex), TIMER_EVENT_SRC_UPG);
|
|
|
+ timer_event_software_generate(pwm->timerx, TIMER_EVENT_SRC_UPG);
|
|
|
|
|
|
return RT_EOK;
|
|
|
}
|
|
|
@@ -526,18 +654,18 @@ static rt_err_t drv_pwm_set(TIMER_PORT_CHANNEL_MAP_S *pstTimerMap, struct rt_pwm
|
|
|
static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
|
|
|
{
|
|
|
struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
|
|
|
- TIMER_PORT_CHANNEL_MAP_S *pstTimerMap = (TIMER_PORT_CHANNEL_MAP_S *)device->parent.user_data;
|
|
|
+ struct gd32_pwm *pwm = rt_container_of(device, struct gd32_pwm, pwm_device);
|
|
|
|
|
|
switch (cmd)
|
|
|
{
|
|
|
case PWM_CMD_ENABLE:
|
|
|
- return drv_pwm_enable(pstTimerMap, configuration, RT_TRUE);
|
|
|
+ return drv_pwm_enable(pwm, configuration, RT_TRUE);
|
|
|
case PWM_CMD_DISABLE:
|
|
|
- return drv_pwm_enable(pstTimerMap, configuration, RT_FALSE);
|
|
|
+ return drv_pwm_enable(pwm, configuration, RT_FALSE);
|
|
|
case PWM_CMD_SET:
|
|
|
- return drv_pwm_set(pstTimerMap, configuration);
|
|
|
+ return drv_pwm_set(pwm, configuration);
|
|
|
case PWM_CMD_GET:
|
|
|
- return drv_pwm_get(pstTimerMap, configuration);
|
|
|
+ return drv_pwm_get(pwm, configuration);
|
|
|
default:
|
|
|
return -RT_EINVAL;
|
|
|
}
|
|
|
@@ -547,15 +675,19 @@ static struct rt_pwm_ops drv_ops = {drv_pwm_control};
|
|
|
|
|
|
static rt_err_t gd32_hw_pwm_init(void)
|
|
|
{
|
|
|
- pwm_find_timer_periph();
|
|
|
rcu_config();
|
|
|
- gpio_config();
|
|
|
timer_config();
|
|
|
|
|
|
+ /*
|
|
|
+ * GPIO is not configured here. When PWM channel is enabled, it will be configured as PWM output.
|
|
|
+ * When disabled, it will be configured as floating input.
|
|
|
+ * GPIO defaults to floating input.
|
|
|
+ */
|
|
|
+
|
|
|
return RT_EOK;
|
|
|
}
|
|
|
|
|
|
-static int gd32_pwm_init(void)
|
|
|
+static int rt_hw_pwm_init(void)
|
|
|
{
|
|
|
int i = 0;
|
|
|
int result = RT_EOK;
|
|
|
@@ -573,14 +705,14 @@ static int gd32_pwm_init(void)
|
|
|
for (i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); i++)
|
|
|
{
|
|
|
/* register pwm device */
|
|
|
- if (rt_device_pwm_register(&gd32_pwm_obj[i].pwm_device, gd32_pwm_obj[i].tim_handle.name, &drv_ops,
|
|
|
- &gd32_pwm_obj[i].tim_handle)== RT_EOK )
|
|
|
+ if (rt_device_pwm_register(&gd32_pwm_obj[i].pwm_device, gd32_pwm_obj[i].name, &drv_ops,
|
|
|
+ RT_NULL)== RT_EOK )
|
|
|
{
|
|
|
- LOG_D("%s register success", gd32_pwm_obj[i].tim_handle.name);
|
|
|
+ LOG_D("%s register success", gd32_pwm_obj[i].name);
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
- LOG_E("%s register failed", gd32_pwm_obj[i].tim_handle.name);
|
|
|
+ LOG_E("%s register failed", gd32_pwm_obj[i].name);
|
|
|
result = -RT_ERROR;
|
|
|
}
|
|
|
}
|
|
|
@@ -588,6 +720,5 @@ static int gd32_pwm_init(void)
|
|
|
__exit:
|
|
|
return result;
|
|
|
}
|
|
|
-INIT_DEVICE_EXPORT(gd32_pwm_init);
|
|
|
-#endif /* RT_USING_PWM */
|
|
|
-
|
|
|
+INIT_DEVICE_EXPORT(rt_hw_pwm_init);
|
|
|
+#endif /* BSP_USING_PWM */
|
ShiHongChao